CPUMDbg.cpp@ 35601

Last change on this file since 35601 was 35601, checked in by vboxsync, 14 years ago
DBGF,CPUM: Expose hypervisor registers as hypercpuX.
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1	/* $Id: CPUMDbg.cpp 35601 2011-01-18 10:43:11Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager, Debugger & Debugging APIs.
4	*/
5
6	/*
7	* Copyright (C) 2010-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DBGF
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/pdmapi.h>
26	#include "CPUMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/param.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/thread.h>
32	#include <iprt/uint128.h>
33
34
35	/**
36	* @interface_method_impl{DBGFREGDESC, pfnGet}
37	*/
38	static DECLCALLBACK(int) cpumR3RegGet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
39	{
40	PVMCPU pVCpu = (PVMCPU)pvUser;
41	void const pv = (uint8_t const )&pVCpu->cpum + pDesc->offRegister;
42
43	VMCPU_ASSERT_EMT(pVCpu);
44
45	switch (pDesc->enmType)
46	{
47	case DBGFREGVALTYPE_U8: pValue->u8 = (uint8_t const )pv; return VINF_SUCCESS;
48	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t const )pv; return VINF_SUCCESS;
49	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t const )pv; return VINF_SUCCESS;
50	case DBGFREGVALTYPE_U64: pValue->u64 = (uint64_t const )pv; return VINF_SUCCESS;
51	case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
52	default:
53	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_INTERNAL_ERROR_3);
54	}
55	}
56
57
58	/**
59	* @interface_method_impl{DBGFREGDESC, pfnGet}
60	*/
61	static DECLCALLBACK(int) cpumR3RegSet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
62	{
63	PVMCPU pVCpu = (PVMCPU)pvUser;
64	void pv = (uint8_t )&pVCpu->cpum + pDesc->offRegister;
65
66	VMCPU_ASSERT_EMT(pVCpu);
67
68	switch (pDesc->enmType)
69	{
70	case DBGFREGVALTYPE_U8:
71	(uint8_t )pv &= ~pfMask->u8;
72	(uint8_t )pv \|= pValue->u8 & pfMask->u8;
73	return VINF_SUCCESS;
74
75	case DBGFREGVALTYPE_U16:
76	(uint16_t )pv &= ~pfMask->u16;
77	(uint16_t )pv \|= pValue->u16 & pfMask->u16;
78	return VINF_SUCCESS;
79
80	case DBGFREGVALTYPE_U32:
81	(uint32_t )pv &= ~pfMask->u32;
82	(uint32_t )pv \|= pValue->u32 & pfMask->u32;
83	return VINF_SUCCESS;
84
85	case DBGFREGVALTYPE_U64:
86	(uint64_t )pv &= ~pfMask->u64;
87	(uint64_t )pv \|= pValue->u64 & pfMask->u64;
88	return VINF_SUCCESS;
89
90	case DBGFREGVALTYPE_U128:
91	{
92	RTUINT128U Val;
93	RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
94	RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
95	return VINF_SUCCESS;
96	}
97
98	default:
99	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_INTERNAL_ERROR_3);
100	}
101	}
102
103
104	/**
105	* @interface_method_impl{DBGFREGDESC, pfnGet}
106	*/
107	static DECLCALLBACK(int) cpumR3RegSet_seg(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
108	{
109	/** @todo perform a selector load, updating hidden selectors and stuff. */
110	return VERR_NOT_IMPLEMENTED;
111	}
112
113
114	/**
115	* @interface_method_impl{DBGFREGDESC, pfnGet}
116	*/
117	static DECLCALLBACK(int) cpumR3RegGet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
118	{
119	PVMCPU pVCpu = (PVMCPU)pvUser;
120	VBOXGDTR const pGdtr = (VBOXGDTR const )((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
121
122	VMCPU_ASSERT_EMT(pVCpu);
123	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
124
125	pValue->dtr.u32Limit = pGdtr->cbGdt;
126	pValue->dtr.u64Base = pGdtr->pGdt;
127	return VINF_SUCCESS;
128	}
129
130
131	/**
132	* @interface_method_impl{DBGFREGDESC, pfnGet}
133	*/
134	static DECLCALLBACK(int) cpumR3RegSet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
135	{
136	return VERR_NOT_IMPLEMENTED;
137	}
138
139
140	/**
141	* @interface_method_impl{DBGFREGDESC, pfnGet}
142	*/
143	static DECLCALLBACK(int) cpumR3RegGet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
144	{
145	PVMCPU pVCpu = (PVMCPU)pvUser;
146	VBOXIDTR const pIdtr = (VBOXIDTR const )((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
147
148	VMCPU_ASSERT_EMT(pVCpu);
149	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
150
151	pValue->dtr.u32Limit = pIdtr->cbIdt;
152	pValue->dtr.u64Base = pIdtr->pIdt;
153	return VINF_SUCCESS;
154	}
155
156
157	/**
158	* @interface_method_impl{DBGFREGDESC, pfnGet}
159	*/
160	static DECLCALLBACK(int) cpumR3RegSet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
161	{
162	return VERR_NOT_IMPLEMENTED;
163	}
164
165
166	/**
167	* Is the FPU state in FXSAVE format or not.
168	*
169	* @returns true if it is, false if it's in FNSAVE.
170	* @param pVCpu The virtual CPU handle.
171	*/
172	DECLINLINE(bool) cpumR3RegIsFxSaveFormat(PVMCPU pVCpu)
173	{
174	#ifdef RT_ARCH_AMD64
175	return true;
176	#else
177	return pVCpu->pVMR3->cpum.s.CPUFeatures.edx.u1FXSR;
178	#endif
179	}
180
181
182	/**
183	* Determins the tag register value for a CPU register when the FPU state
184	* format is FXSAVE.
185	*
186	* @returns The tag register value.
187	* @param pVCpu The virtual CPU handle.
188	* @param iReg The register number (0..7).
189	*/
190	DECLINLINE(uint16_t) cpumR3RegCalcFpuTagFromFxSave(PCX86FXSTATE pFpu, unsigned iReg)
191	{
192	/*
193	* See table 11-1 in the AMD docs.
194	*/
195	if (!(pFpu->FTW & RT_BIT_32(iReg)))
196	return 3; /* b11 - empty */
197
198	uint16_t const uExp = pFpu->aRegs[iReg].au16[4];
199	if (uExp == 0)
200	{
201	if (pFpu->aRegs[iReg].au64[0] == 0) /* J & M == 0 */
202	return 1; /* b01 - zero */
203	return 2; /* b10 - special */
204	}
205
206	if (uExp == UINT16_C(0xffff))
207	return 2; /* b10 - special */
208
209	if (!(pFpu->aRegs[iReg].au64[0] >> 63)) /* J == 0 */
210	return 2; /* b10 - special */
211
212	return 0; /* b00 - valid (normal) */
213	}
214
215
216	/**
217	* @interface_method_impl{DBGFREGDESC, pfnGet}
218	*/
219	static DECLCALLBACK(int) cpumR3RegGet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
220	{
221	PVMCPU pVCpu = (PVMCPU)pvUser;
222	PCX86FXSTATE pFpu = (PCX86FXSTATE)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
223
224	VMCPU_ASSERT_EMT(pVCpu);
225	Assert(pDesc->enmType == DBGFREGVALTYPE_U16);
226
227	if (cpumR3RegIsFxSaveFormat(pVCpu))
228	pValue->u16 = cpumR3RegCalcFpuTagFromFxSave(pFpu, 0)
229	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 1) << 2)
230	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 2) << 4)
231	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 3) << 6)
232	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 4) << 8)
233	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 5) << 10)
234	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 6) << 12)
235	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 7) << 14);
236	else
237	{
238	PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)pFpu;
239	pValue->u16 = pOldFpu->FTW;
240	}
241	return VINF_SUCCESS;
242	}
243
244
245	/**
246	* @interface_method_impl{DBGFREGDESC, pfnGet}
247	*/
248	static DECLCALLBACK(int) cpumR3RegSet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
249	{
250	return VERR_DBGF_READ_ONLY_REGISTER;
251	}
252
253
254
255	/*
256	*
257	* Guest register access functions.
258	*
259	*/
260
261	/**
262	* @interface_method_impl{DBGFREGDESC, pfnGet}
263	*/
264	static DECLCALLBACK(int) cpumR3RegGstGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
265	{
266	PVMCPU pVCpu = (PVMCPU)pvUser;
267	void const pv = (uint8_t const )&pVCpu->cpum + pDesc->offRegister;
268
269	VMCPU_ASSERT_EMT(pVCpu);
270
271	uint64_t u64Value;
272	int rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64Value);
273	AssertRCReturn(rc, rc);
274	switch (pDesc->enmType)
275	{
276	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
277	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
278	default:
279	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
280	}
281	return VINF_SUCCESS;
282	}
283
284
285	/**
286	* @interface_method_impl{DBGFREGDESC, pfnGet}
287	*/
288	static DECLCALLBACK(int) cpumR3RegGstSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
289	{
290	int rc;
291	PVMCPU pVCpu = (PVMCPU)pvUser;
292	void const pv = (uint8_t const )&pVCpu->cpum + pDesc->offRegister;
293
294	VMCPU_ASSERT_EMT(pVCpu);
295
296	/*
297	* Calculate the new value.
298	*/
299	uint64_t u64Value;
300	uint64_t fMask;
301	uint64_t fMaskMax;
302	switch (pDesc->enmType)
303	{
304	case DBGFREGVALTYPE_U64:
305	u64Value = pValue->u64;
306	fMask = pfMask->u64;
307	fMaskMax = UINT64_MAX;
308	break;
309	case DBGFREGVALTYPE_U32:
310	u64Value = pValue->u32;
311	fMask = pfMask->u32;
312	fMaskMax = UINT32_MAX;
313	break;
314	default: AssertFailedReturn(VERR_INTERNAL_ERROR_4);
315	}
316	if (fMask != fMaskMax)
317	{
318	uint64_t u64FullValue;
319	rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64FullValue);
320	if (RT_FAILURE(rc))
321	return rc;
322	u64Value = (u64FullValue & ~fMask)
323	\| (u64Value & fMask);
324	}
325
326	/*
327	* Perform the assignment.
328	*/
329	switch (pDesc->offRegister)
330	{
331	case 0: rc = CPUMSetGuestCR0(pVCpu, u64Value); break;
332	case 2: rc = CPUMSetGuestCR2(pVCpu, u64Value); break;
333	case 3: rc = CPUMSetGuestCR3(pVCpu, u64Value); break;
334	case 4: rc = CPUMSetGuestCR4(pVCpu, u64Value); break;
335	case 8: rc = PDMApicSetTPR(pVCpu, (uint8_t)(u64Value << 4)); break;
336	default:
337	AssertFailedReturn(VERR_INTERNAL_ERROR_2);
338	}
339	return rc;
340	}
341
342
343	/**
344	* @interface_method_impl{DBGFREGDESC, pfnGet}
345	*/
346	static DECLCALLBACK(int) cpumR3RegGstGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
347	{
348	PVMCPU pVCpu = (PVMCPU)pvUser;
349	void const pv = (uint8_t const )&pVCpu->cpum + pDesc->offRegister;
350
351	VMCPU_ASSERT_EMT(pVCpu);
352
353	uint64_t u64Value;
354	int rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64Value);
355	AssertRCReturn(rc, rc);
356	switch (pDesc->enmType)
357	{
358	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
359	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
360	default:
361	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
362	}
363	return VINF_SUCCESS;
364	}
365
366
367	/**
368	* @interface_method_impl{DBGFREGDESC, pfnGet}
369	*/
370	static DECLCALLBACK(int) cpumR3RegGstSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
371	{
372	int rc;
373	PVMCPU pVCpu = (PVMCPU)pvUser;
374	void const pv = (uint8_t const )&pVCpu->cpum + pDesc->offRegister;
375
376	VMCPU_ASSERT_EMT(pVCpu);
377
378	/*
379	* Calculate the new value.
380	*/
381	uint64_t u64Value;
382	uint64_t fMask;
383	uint64_t fMaskMax;
384	switch (pDesc->enmType)
385	{
386	case DBGFREGVALTYPE_U64:
387	u64Value = pValue->u64;
388	fMask = pfMask->u64;
389	fMaskMax = UINT64_MAX;
390	break;
391	case DBGFREGVALTYPE_U32:
392	u64Value = pValue->u32;
393	fMask = pfMask->u32;
394	fMaskMax = UINT32_MAX;
395	break;
396	default: AssertFailedReturn(VERR_INTERNAL_ERROR_4);
397	}
398	if (fMask != fMaskMax)
399	{
400	uint64_t u64FullValue;
401	rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64FullValue);
402	if (RT_FAILURE(rc))
403	return rc;
404	u64Value = (u64FullValue & ~fMask)
405	\| (u64Value & fMask);
406	}
407
408	/*
409	* Perform the assignment.
410	*/
411	return CPUMSetGuestDRx(pVCpu, pDesc->offRegister, u64Value);
412	}
413
414
415	/**
416	* @interface_method_impl{DBGFREGDESC, pfnGet}
417	*/
418	static DECLCALLBACK(int) cpumR3RegGstGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
419	{
420	PVMCPU pVCpu = (PVMCPU)pvUser;
421	void const pv = (uint8_t const )&pVCpu->cpum + pDesc->offRegister;
422
423	VMCPU_ASSERT_EMT(pVCpu);
424	uint64_t u64Value;
425	int rc = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64Value);
426	if (RT_SUCCESS(rc))
427	{
428	switch (pDesc->enmType)
429	{
430	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
431	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
432	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
433	default:
434	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
435	}
436	}
437	/** @todo what to do about errors? */
438	return rc;
439	}
440
441
442	/**
443	* @interface_method_impl{DBGFREGDESC, pfnGet}
444	*/
445	static DECLCALLBACK(int) cpumR3RegGstSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
446	{
447	int rc;
448	PVMCPU pVCpu = (PVMCPU)pvUser;
449	void const pv = (uint8_t const )&pVCpu->cpum + pDesc->offRegister;
450
451	VMCPU_ASSERT_EMT(pVCpu);
452
453	/*
454	* Calculate the new value.
455	*/
456	uint64_t u64Value;
457	uint64_t fMask;
458	uint64_t fMaskMax;
459	switch (pDesc->enmType)
460	{
461	case DBGFREGVALTYPE_U64:
462	u64Value = pValue->u64;
463	fMask = pfMask->u64;
464	fMaskMax = UINT64_MAX;
465	break;
466	case DBGFREGVALTYPE_U32:
467	u64Value = pValue->u32;
468	fMask = pfMask->u32;
469	fMaskMax = UINT32_MAX;
470	break;
471	case DBGFREGVALTYPE_U16:
472	u64Value = pValue->u16;
473	fMask = pfMask->u16;
474	fMaskMax = UINT16_MAX;
475	break;
476	default: AssertFailedReturn(VERR_INTERNAL_ERROR_4);
477	}
478	if (fMask != fMaskMax)
479	{
480	uint64_t u64FullValue;
481	rc = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64FullValue);
482	if (RT_FAILURE(rc))
483	return rc;
484	u64Value = (u64FullValue & ~fMask)
485	\| (u64Value & fMask);
486	}
487
488	/*
489	* Perform the assignment.
490	*/
491	return CPUMSetGuestMsr(pVCpu, pDesc->offRegister, u64Value);
492	}
493
494
495	/**
496	* @interface_method_impl{DBGFREGDESC, pfnGet}
497	*/
498	static DECLCALLBACK(int) cpumR3RegGstGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
499	{
500	PVMCPU pVCpu = (PVMCPU)pvUser;
501	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
502
503	VMCPU_ASSERT_EMT(pVCpu);
504	Assert(pDesc->enmType == DBGFREGVALTYPE_R80);
505
506	if (cpumR3RegIsFxSaveFormat(pVCpu))
507	{
508	unsigned iReg = (pVCpu->cpum.s.Guest.fpu.FSW >> 11) & 7;
509	iReg += pDesc->offRegister;
510	iReg &= 7;
511	pValue->r80 = pVCpu->cpum.s.Guest.fpu.aRegs[iReg].r80;
512	}
513	else
514	{
515	PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.fpu;
516
517	unsigned iReg = (pOldFpu->FSW >> 11) & 7;
518	iReg += pDesc->offRegister;
519	iReg &= 7;
520
521	pValue->r80 = pOldFpu->regs[iReg].r80;
522	}
523
524	return VINF_SUCCESS;
525	}
526
527
528	/**
529	* @interface_method_impl{DBGFREGDESC, pfnGet}
530	*/
531	static DECLCALLBACK(int) cpumR3RegGstSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
532	{
533	return VERR_NOT_IMPLEMENTED;
534	}
535
536
537
538	/*
539	*
540	* Hypervisor register access functions.
541	*
542	*/
543
544	/**
545	* @interface_method_impl{DBGFREGDESC, pfnGet}
546	*/
547	static DECLCALLBACK(int) cpumR3RegHyperGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
548	{
549	PVMCPU pVCpu = (PVMCPU)pvUser;
550	VMCPU_ASSERT_EMT(pVCpu);
551
552	uint64_t u64Value;
553	switch (pDesc->offRegister)
554	{
555	case 0: u64Value = UINT64_MAX; break;
556	case 2: u64Value = UINT64_MAX; break;
557	case 3: u64Value = CPUMGetHyperCR3(pVCpu); break;
558	case 4: u64Value = UINT64_MAX; break;
559	case 8: u64Value = UINT64_MAX; break;
560	default:
561	AssertFailedReturn(VERR_INTERNAL_ERROR_3);
562	}
563	switch (pDesc->enmType)
564	{
565	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
566	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
567	default:
568	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
569	}
570	return VINF_SUCCESS;
571	}
572
573
574	/**
575	* @interface_method_impl{DBGFREGDESC, pfnGet}
576	*/
577	static DECLCALLBACK(int) cpumR3RegHyperSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
578	{
579	/* Not settable, prevents killing your host. */
580	return VERR_ACCESS_DENIED;
581	}
582
583
584	/**
585	* @interface_method_impl{DBGFREGDESC, pfnGet}
586	*/
587	static DECLCALLBACK(int) cpumR3RegHyperGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
588	{
589	PVMCPU pVCpu = (PVMCPU)pvUser;
590	void const pv = (uint8_t const )&pVCpu->cpum + pDesc->offRegister;
591
592	VMCPU_ASSERT_EMT(pVCpu);
593
594	uint64_t u64Value;
595	switch (pDesc->offRegister)
596	{
597	case 0: u64Value = CPUMGetHyperDR0(pVCpu); break;
598	case 1: u64Value = CPUMGetHyperDR1(pVCpu); break;
599	case 2: u64Value = CPUMGetHyperDR2(pVCpu); break;
600	case 3: u64Value = CPUMGetHyperDR3(pVCpu); break;
601	case 6: u64Value = CPUMGetHyperDR6(pVCpu); break;
602	case 7: u64Value = CPUMGetHyperDR7(pVCpu); break;
603	default:
604	AssertFailedReturn(VERR_INTERNAL_ERROR_3);
605	}
606	switch (pDesc->enmType)
607	{
608	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
609	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
610	default:
611	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
612	}
613	return VINF_SUCCESS;
614	}
615
616
617	/**
618	* @interface_method_impl{DBGFREGDESC, pfnGet}
619	*/
620	static DECLCALLBACK(int) cpumR3RegHyperSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
621	{
622	/* Not settable, prevents killing your host. */
623	return VERR_ACCESS_DENIED;
624	}
625
626
627	/**
628	* @interface_method_impl{DBGFREGDESC, pfnGet}
629	*/
630	static DECLCALLBACK(int) cpumR3RegHyperGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
631	{
632	/* Not availble at present, return all FFs to keep things quiet */
633	uint64_t u64Value = UINT64_MAX;
634	switch (pDesc->enmType)
635	{
636	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
637	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
638	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
639	default:
640	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
641	}
642	return VINF_SUCCESS;
643	}
644
645
646	/**
647	* @interface_method_impl{DBGFREGDESC, pfnGet}
648	*/
649	static DECLCALLBACK(int) cpumR3RegHyperSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
650	{
651	/* Not settable, return failure. */
652	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
653	return VERR_ACCESS_DENIED;
654	}
655
656
657	/**
658	* @interface_method_impl{DBGFREGDESC, pfnGet}
659	*/
660	static DECLCALLBACK(int) cpumR3RegHyperGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
661	{
662	PVMCPU pVCpu = (PVMCPU)pvUser;
663
664	VMCPU_ASSERT_EMT(pVCpu);
665	Assert(pDesc->enmType == DBGFREGVALTYPE_R80);
666
667	if (cpumR3RegIsFxSaveFormat(pVCpu))
668	{
669	unsigned iReg = (pVCpu->cpum.s.Guest.fpu.FSW >> 11) & 7;
670	iReg += pDesc->offRegister;
671	iReg &= 7;
672	pValue->r80 = pVCpu->cpum.s.Guest.fpu.aRegs[iReg].r80;
673	}
674	else
675	{
676	PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.fpu;
677
678	unsigned iReg = (pOldFpu->FSW >> 11) & 7;
679	iReg += pDesc->offRegister;
680	iReg &= 7;
681
682	pValue->r80 = pOldFpu->regs[iReg].r80;
683	}
684
685	return VINF_SUCCESS;
686	}
687
688
689	/**
690	* @interface_method_impl{DBGFREGDESC, pfnGet}
691	*/
692	static DECLCALLBACK(int) cpumR3RegHyperSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
693	{
694	/* There isn't a FPU context for the hypervisor yet, so no point in trying to set stuff. */
695	return VERR_ACCESS_DENIED;
696	}
697
698
699
700	/*
701	* Set up aliases.
702	*/
703	#define CPUMREGALIAS_STD(Name, psz32, psz16, psz8) \
704	static DBGFREGALIAS const g_aCpumRegAliases_##Name[] = \
705	{ \
706	{ psz32, DBGFREGVALTYPE_U32 }, \
707	{ psz16, DBGFREGVALTYPE_U16 }, \
708	{ psz8, DBGFREGVALTYPE_U8 }, \
709	{ NULL, DBGFREGVALTYPE_INVALID } \
710	}
711	CPUMREGALIAS_STD(rax, "eax", "ax", "al");
712	CPUMREGALIAS_STD(rcx, "ecx", "cx", "cl");
713	CPUMREGALIAS_STD(rdx, "edx", "dx", "dl");
714	CPUMREGALIAS_STD(rbx, "ebx", "bx", "bl");
715	CPUMREGALIAS_STD(rsp, "esp", "sp", NULL);
716	CPUMREGALIAS_STD(rbp, "ebp", "bp", NULL);
717	CPUMREGALIAS_STD(rsi, "esi", "si", "sil");
718	CPUMREGALIAS_STD(rdi, "edi", "di", "dil");
719	CPUMREGALIAS_STD(r8, "r8d", "r8w", "r8b");
720	CPUMREGALIAS_STD(r9, "r9d", "r9w", "r9b");
721	CPUMREGALIAS_STD(r10, "r10d", "r10w", "r10b");
722	CPUMREGALIAS_STD(r11, "r11d", "r11w", "r11b");
723	CPUMREGALIAS_STD(r12, "r12d", "r12w", "r12b");
724	CPUMREGALIAS_STD(r13, "r13d", "r13w", "r13b");
725	CPUMREGALIAS_STD(r14, "r14d", "r14w", "r14b");
726	CPUMREGALIAS_STD(r15, "r15d", "r15w", "r15b");
727	CPUMREGALIAS_STD(rip, "eip", "ip", NULL);
728	CPUMREGALIAS_STD(rflags, "eflags", "flags", NULL);
729	#undef CPUMREGALIAS_STD
730
731	static DBGFREGALIAS const g_aCpumRegAliases_fpuip[] =
732	{
733	{ "fpuip16", DBGFREGVALTYPE_U16 },
734	{ NULL, DBGFREGVALTYPE_INVALID }
735	};
736
737	static DBGFREGALIAS const g_aCpumRegAliases_fpudp[] =
738	{
739	{ "fpudp16", DBGFREGVALTYPE_U16 },
740	{ NULL, DBGFREGVALTYPE_INVALID }
741	};
742
743	static DBGFREGALIAS const g_aCpumRegAliases_cr0[] =
744	{
745	{ "msw", DBGFREGVALTYPE_U16 },
746	{ NULL, DBGFREGVALTYPE_INVALID }
747	};
748
749	/*
750	* Sub fields.
751	*/
752	/** Sub-fields for the (hidden) segment attribute register. */
753	static DBGFREGSUBFIELD const g_aCpumRegFields_seg[] =
754	{
755	DBGFREGSUBFIELD_RW("type", 0, 4, 0),
756	DBGFREGSUBFIELD_RW("s", 4, 1, 0),
757	DBGFREGSUBFIELD_RW("dpl", 5, 2, 0),
758	DBGFREGSUBFIELD_RW("p", 7, 1, 0),
759	DBGFREGSUBFIELD_RW("avl", 12, 1, 0),
760	DBGFREGSUBFIELD_RW("l", 13, 1, 0),
761	DBGFREGSUBFIELD_RW("d", 14, 1, 0),
762	DBGFREGSUBFIELD_RW("g", 15, 1, 0),
763	DBGFREGSUBFIELD_TERMINATOR()
764	};
765
766	/** Sub-fields for the flags register. */
767	static DBGFREGSUBFIELD const g_aCpumRegFields_rflags[] =
768	{
769	DBGFREGSUBFIELD_RW("cf", 0, 1, 0),
770	DBGFREGSUBFIELD_RW("pf", 2, 1, 0),
771	DBGFREGSUBFIELD_RW("af", 4, 1, 0),
772	DBGFREGSUBFIELD_RW("zf", 6, 1, 0),
773	DBGFREGSUBFIELD_RW("sf", 7, 1, 0),
774	DBGFREGSUBFIELD_RW("tf", 8, 1, 0),
775	DBGFREGSUBFIELD_RW("if", 9, 1, 0),
776	DBGFREGSUBFIELD_RW("df", 10, 1, 0),
777	DBGFREGSUBFIELD_RW("of", 11, 1, 0),
778	DBGFREGSUBFIELD_RW("iopl", 12, 2, 0),
779	DBGFREGSUBFIELD_RW("nt", 14, 1, 0),
780	DBGFREGSUBFIELD_RW("rf", 16, 1, 0),
781	DBGFREGSUBFIELD_RW("vm", 17, 1, 0),
782	DBGFREGSUBFIELD_RW("ac", 18, 1, 0),
783	DBGFREGSUBFIELD_RW("vif", 19, 1, 0),
784	DBGFREGSUBFIELD_RW("vip", 20, 1, 0),
785	DBGFREGSUBFIELD_RW("id", 21, 1, 0),
786	DBGFREGSUBFIELD_TERMINATOR()
787	};
788
789	/** Sub-fields for the FPU control word register. */
790	static DBGFREGSUBFIELD const g_aCpumRegFields_fcw[] =
791	{
792	DBGFREGSUBFIELD_RW("im", 1, 1, 0),
793	DBGFREGSUBFIELD_RW("dm", 2, 1, 0),
794	DBGFREGSUBFIELD_RW("zm", 3, 1, 0),
795	DBGFREGSUBFIELD_RW("om", 4, 1, 0),
796	DBGFREGSUBFIELD_RW("um", 5, 1, 0),
797	DBGFREGSUBFIELD_RW("pm", 6, 1, 0),
798	DBGFREGSUBFIELD_RW("pc", 8, 2, 0),
799	DBGFREGSUBFIELD_RW("rc", 10, 2, 0),
800	DBGFREGSUBFIELD_RW("x", 12, 1, 0),
801	DBGFREGSUBFIELD_TERMINATOR()
802	};
803
804	/** Sub-fields for the FPU status word register. */
805	static DBGFREGSUBFIELD const g_aCpumRegFields_fsw[] =
806	{
807	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
808	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
809	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
810	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
811	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
812	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
813	DBGFREGSUBFIELD_RW("se", 6, 1, 0),
814	DBGFREGSUBFIELD_RW("es", 7, 1, 0),
815	DBGFREGSUBFIELD_RW("c0", 8, 1, 0),
816	DBGFREGSUBFIELD_RW("c1", 9, 1, 0),
817	DBGFREGSUBFIELD_RW("c2", 10, 1, 0),
818	DBGFREGSUBFIELD_RW("top", 11, 3, 0),
819	DBGFREGSUBFIELD_RW("c3", 14, 1, 0),
820	DBGFREGSUBFIELD_RW("b", 15, 1, 0),
821	DBGFREGSUBFIELD_TERMINATOR()
822	};
823
824	/** Sub-fields for the FPU tag word register. */
825	static DBGFREGSUBFIELD const g_aCpumRegFields_ftw[] =
826	{
827	DBGFREGSUBFIELD_RW("tag0", 0, 2, 0),
828	DBGFREGSUBFIELD_RW("tag1", 2, 2, 0),
829	DBGFREGSUBFIELD_RW("tag2", 4, 2, 0),
830	DBGFREGSUBFIELD_RW("tag3", 6, 2, 0),
831	DBGFREGSUBFIELD_RW("tag4", 8, 2, 0),
832	DBGFREGSUBFIELD_RW("tag5", 10, 2, 0),
833	DBGFREGSUBFIELD_RW("tag6", 12, 2, 0),
834	DBGFREGSUBFIELD_RW("tag7", 14, 2, 0),
835	DBGFREGSUBFIELD_TERMINATOR()
836	};
837
838	/** Sub-fields for the Multimedia Extensions Control and Status Register. */
839	static DBGFREGSUBFIELD const g_aCpumRegFields_mxcsr[] =
840	{
841	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
842	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
843	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
844	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
845	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
846	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
847	DBGFREGSUBFIELD_RW("daz", 6, 1, 0),
848	DBGFREGSUBFIELD_RW("im", 7, 1, 0),
849	DBGFREGSUBFIELD_RW("dm", 8, 1, 0),
850	DBGFREGSUBFIELD_RW("zm", 9, 1, 0),
851	DBGFREGSUBFIELD_RW("om", 10, 1, 0),
852	DBGFREGSUBFIELD_RW("um", 11, 1, 0),
853	DBGFREGSUBFIELD_RW("pm", 12, 1, 0),
854	DBGFREGSUBFIELD_RW("rc", 13, 2, 0),
855	DBGFREGSUBFIELD_RW("fz", 14, 1, 0),
856	DBGFREGSUBFIELD_TERMINATOR()
857	};
858
859	/** Sub-fields for the FPU tag word register. */
860	static DBGFREGSUBFIELD const g_aCpumRegFields_stN[] =
861	{
862	DBGFREGSUBFIELD_RW("man", 0, 64, 0),
863	DBGFREGSUBFIELD_RW("exp", 64, 15, 0),
864	DBGFREGSUBFIELD_RW("sig", 79, 1, 0),
865	DBGFREGSUBFIELD_TERMINATOR()
866	};
867
868	/** Sub-fields for the MMX registers. */
869	static DBGFREGSUBFIELD const g_aCpumRegFields_mmN[] =
870	{
871	DBGFREGSUBFIELD_RW("dw0", 0, 32, 0),
872	DBGFREGSUBFIELD_RW("dw1", 32, 32, 0),
873	DBGFREGSUBFIELD_RW("w0", 0, 16, 0),
874	DBGFREGSUBFIELD_RW("w1", 16, 16, 0),
875	DBGFREGSUBFIELD_RW("w2", 32, 16, 0),
876	DBGFREGSUBFIELD_RW("w3", 48, 16, 0),
877	DBGFREGSUBFIELD_RW("b0", 0, 8, 0),
878	DBGFREGSUBFIELD_RW("b1", 8, 8, 0),
879	DBGFREGSUBFIELD_RW("b2", 16, 8, 0),
880	DBGFREGSUBFIELD_RW("b3", 24, 8, 0),
881	DBGFREGSUBFIELD_RW("b4", 32, 8, 0),
882	DBGFREGSUBFIELD_RW("b5", 40, 8, 0),
883	DBGFREGSUBFIELD_RW("b6", 48, 8, 0),
884	DBGFREGSUBFIELD_RW("b7", 56, 8, 0),
885	DBGFREGSUBFIELD_TERMINATOR()
886	};
887
888	/** Sub-fields for the XMM registers. */
889	static DBGFREGSUBFIELD const g_aCpumRegFields_xmmN[] =
890	{
891	DBGFREGSUBFIELD_RW("r0", 0, 32, 0),
892	DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0),
893	DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0),
894	DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0),
895	DBGFREGSUBFIELD_RW("r1", 32, 32, 0),
896	DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0),
897	DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0),
898	DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0),
899	DBGFREGSUBFIELD_RW("r2", 64, 32, 0),
900	DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0),
901	DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0),
902	DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0),
903	DBGFREGSUBFIELD_RW("r3", 96, 32, 0),
904	DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0),
905	DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0),
906	DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0),
907	DBGFREGSUBFIELD_TERMINATOR()
908	};
909
910	/** Sub-fields for the CR0 register. */
911	static DBGFREGSUBFIELD const g_aCpumRegFields_cr0[] =
912	{
913	/** @todo */
914	DBGFREGSUBFIELD_TERMINATOR()
915	};
916
917	/** Sub-fields for the CR3 register. */
918	static DBGFREGSUBFIELD const g_aCpumRegFields_cr3[] =
919	{
920	/** @todo */
921	DBGFREGSUBFIELD_TERMINATOR()
922	};
923
924	/** Sub-fields for the CR4 register. */
925	static DBGFREGSUBFIELD const g_aCpumRegFields_cr4[] =
926	{
927	/** @todo */
928	DBGFREGSUBFIELD_TERMINATOR()
929	};
930
931	/** Sub-fields for the DR6 register. */
932	static DBGFREGSUBFIELD const g_aCpumRegFields_dr6[] =
933	{
934	/** @todo */
935	DBGFREGSUBFIELD_TERMINATOR()
936	};
937
938	/** Sub-fields for the DR7 register. */
939	static DBGFREGSUBFIELD const g_aCpumRegFields_dr7[] =
940	{
941	/** @todo */
942	DBGFREGSUBFIELD_TERMINATOR()
943	};
944
945	/** Sub-fields for the CR_PAT MSR. */
946	static DBGFREGSUBFIELD const g_aCpumRegFields_apic_base[] =
947	{
948	DBGFREGSUBFIELD_RW("bsp", 8, 1, 0),
949	DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
950	DBGFREGSUBFIELD_RW("base", 12, 20, 12),
951	DBGFREGSUBFIELD_TERMINATOR()
952	};
953
954	/** Sub-fields for the CR_PAT MSR. */
955	static DBGFREGSUBFIELD const g_aCpumRegFields_cr_pat[] =
956	{
957	/** @todo */
958	DBGFREGSUBFIELD_TERMINATOR()
959	};
960
961	/** Sub-fields for the PERF_STATUS MSR. */
962	static DBGFREGSUBFIELD const g_aCpumRegFields_perf_status[] =
963	{
964	/** @todo */
965	DBGFREGSUBFIELD_TERMINATOR()
966	};
967
968	/** Sub-fields for the EFER MSR. */
969	static DBGFREGSUBFIELD const g_aCpumRegFields_efer[] =
970	{
971	/** @todo */
972	DBGFREGSUBFIELD_TERMINATOR()
973	};
974
975	/** Sub-fields for the STAR MSR. */
976	static DBGFREGSUBFIELD const g_aCpumRegFields_star[] =
977	{
978	/** @todo */
979	DBGFREGSUBFIELD_TERMINATOR()
980	};
981
982	/** Sub-fields for the CSTAR MSR. */
983	static DBGFREGSUBFIELD const g_aCpumRegFields_cstar[] =
984	{
985	/** @todo */
986	DBGFREGSUBFIELD_TERMINATOR()
987	};
988
989	/** Sub-fields for the LSTAR MSR. */
990	static DBGFREGSUBFIELD const g_aCpumRegFields_lstar[] =
991	{
992	/** @todo */
993	DBGFREGSUBFIELD_TERMINATOR()
994	};
995
996	/** Sub-fields for the SF_MASK MSR. */
997	static DBGFREGSUBFIELD const g_aCpumRegFields_sf_mask[] =
998	{
999	/** @todo */
1000	DBGFREGSUBFIELD_TERMINATOR()
1001	};
1002
1003
1004	/** @name Macros for producing register descriptor table entries.
1005	* @{ */
1006	#define CPU_REG_EX_AS(a_szName, a_RegSuff, a_TypeSuff, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1007	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1008
1009	#define CPU_REG_REG(UName, LName) \
1010	CPU_REG_RW_AS(#LName, UName, U64, LName, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_##LName, NULL)
1011
1012	#define CPU_REG_SEG(UName, LName) \
1013	CPU_REG_RW_AS(#LName, UName, U16, LName, cpumR3RegGet_Generic, cpumR3RegSet_seg, NULL, NULL ), \
1014	CPU_REG_RW_AS(#LName "_attr", UName##_ATTR, U32, LName##Hid.Attr.u, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_seg), \
1015	CPU_REG_RW_AS(#LName "_base", UName##_BASE, U64, LName##Hid.u64Base, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), \
1016	CPU_REG_RW_AS(#LName "_lim", UName##_LIMIT, U32, LName##Hid.u32Limit, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL )
1017
1018	#define CPU_REG_MM(n) \
1019	CPU_REG_RW_AS("mm" #n, MM##n, U64, fpu.aRegs[n].mmx, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mmN)
1020
1021	#define CPU_REG_XMM(n) \
1022	CPU_REG_RW_AS("xmm" #n, XMM##n, U128, fpu.aXMM[n].xmm, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_xmmN)
1023	/** @} */
1024
1025
1026	/**
1027	* The guest register descriptors.
1028	*/
1029	static DBGFREGDESC const g_aCpumRegGstDescs[] =
1030	{
1031	#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1032	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1033	#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1034	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1035	#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
1036	CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegGstGet_msr, cpumR3RegGstSet_msr, NULL, a_paSubFields)
1037	#define CPU_REG_ST(n) \
1038	CPU_REG_EX_AS("st" #n, ST##n, R80, n, cpumR3RegGstGet_stN, cpumR3RegGstSet_stN, NULL, g_aCpumRegFields_stN)
1039
1040	CPU_REG_REG(RAX, rax),
1041	CPU_REG_REG(RCX, rcx),
1042	CPU_REG_REG(RDX, rdx),
1043	CPU_REG_REG(RBX, rbx),
1044	CPU_REG_REG(RSP, rsp),
1045	CPU_REG_REG(RBP, rbp),
1046	CPU_REG_REG(RSI, rsi),
1047	CPU_REG_REG(RDI, rdi),
1048	CPU_REG_REG(R8, r8),
1049	CPU_REG_REG(R9, r9),
1050	CPU_REG_REG(R10, r10),
1051	CPU_REG_REG(R11, r11),
1052	CPU_REG_REG(R12, r12),
1053	CPU_REG_REG(R13, r13),
1054	CPU_REG_REG(R14, r14),
1055	CPU_REG_REG(R15, r15),
1056	CPU_REG_SEG(CS, cs),
1057	CPU_REG_SEG(DS, ds),
1058	CPU_REG_SEG(ES, es),
1059	CPU_REG_SEG(FS, fs),
1060	CPU_REG_SEG(GS, gs),
1061	CPU_REG_SEG(SS, ss),
1062	CPU_REG_REG(RIP, rip),
1063	CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
1064	CPU_REG_RW_AS("fcw", FCW, U16, fpu.FCW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fcw ),
1065	CPU_REG_RW_AS("fsw", FSW, U16, fpu.FSW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fsw ),
1066	CPU_REG_RO_AS("ftw", FTW, U16, fpu, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ),
1067	CPU_REG_RW_AS("fop", FOP, U16, fpu.FOP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1068	CPU_REG_RW_AS("fpuip", FPUIP, U32, fpu.FPUIP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpuip, NULL ),
1069	CPU_REG_RW_AS("fpucs", FPUCS, U16, fpu.CS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1070	CPU_REG_RW_AS("fpudp", FPUDP, U32, fpu.FPUDP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpudp, NULL ),
1071	CPU_REG_RW_AS("fpuds", FPUDS, U16, fpu.DS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1072	CPU_REG_RW_AS("mxcsr", MXCSR, U32, fpu.MXCSR, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
1073	CPU_REG_RW_AS("mxcsr_mask", MXCSR_MASK, U32, fpu.MXCSR_MASK, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
1074	CPU_REG_ST(0),
1075	CPU_REG_ST(1),
1076	CPU_REG_ST(2),
1077	CPU_REG_ST(3),
1078	CPU_REG_ST(4),
1079	CPU_REG_ST(5),
1080	CPU_REG_ST(6),
1081	CPU_REG_ST(7),
1082	CPU_REG_MM(0),
1083	CPU_REG_MM(1),
1084	CPU_REG_MM(2),
1085	CPU_REG_MM(3),
1086	CPU_REG_MM(4),
1087	CPU_REG_MM(5),
1088	CPU_REG_MM(6),
1089	CPU_REG_MM(7),
1090	CPU_REG_XMM(0),
1091	CPU_REG_XMM(1),
1092	CPU_REG_XMM(2),
1093	CPU_REG_XMM(3),
1094	CPU_REG_XMM(4),
1095	CPU_REG_XMM(5),
1096	CPU_REG_XMM(6),
1097	CPU_REG_XMM(7),
1098	CPU_REG_XMM(8),
1099	CPU_REG_XMM(9),
1100	CPU_REG_XMM(10),
1101	CPU_REG_XMM(11),
1102	CPU_REG_XMM(12),
1103	CPU_REG_XMM(13),
1104	CPU_REG_XMM(14),
1105	CPU_REG_XMM(15),
1106	CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1107	CPU_REG_RW_AS("gdtr_limit", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1108	CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1109	CPU_REG_RW_AS("idtr_limit", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1110	CPU_REG_SEG(LDTR, ldtr),
1111	CPU_REG_SEG(TR, tr),
1112	CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
1113	CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1114	CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr3 ),
1115	CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr4 ),
1116	CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1117	CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1118	CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1119	CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1120	CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1121	CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr6 ),
1122	CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr7 ),
1123	CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
1124	CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
1125	CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
1126	CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
1127	CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ),
1128	CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ),
1129	CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ),
1130	CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
1131	CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
1132	CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
1133	CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
1134	CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
1135	CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
1136	CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
1137	CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
1138	CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
1139	CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Guest.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1140	CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Guest.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1141	CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Guest.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1142	CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Guest.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1143	CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
1144	CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
1145	DBGFREGDESC_TERMINATOR()
1146
1147	#undef CPU_REG_RW_AS
1148	#undef CPU_REG_RO_AS
1149	#undef CPU_REG_MSR
1150	#undef CPU_REG_ST
1151	};
1152
1153
1154	/**
1155	* The hypervisor (raw-mode) register descriptors.
1156	*/
1157	static DBGFREGDESC const g_aCpumRegHyperDescs[] =
1158	{
1159	#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1160	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(CPUMCPU, Hyper.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1161	#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1162	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Hyper.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1163	#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
1164	CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegHyperGet_msr, cpumR3RegHyperSet_msr, NULL, a_paSubFields)
1165	#define CPU_REG_ST(n) \
1166	CPU_REG_EX_AS("st" #n, ST##n, R80, n, cpumR3RegHyperGet_stN, cpumR3RegHyperSet_stN, NULL, g_aCpumRegFields_stN)
1167
1168	CPU_REG_REG(RAX, rax),
1169	CPU_REG_REG(RCX, rcx),
1170	CPU_REG_REG(RDX, rdx),
1171	CPU_REG_REG(RBX, rbx),
1172	CPU_REG_REG(RSP, rsp),
1173	CPU_REG_REG(RBP, rbp),
1174	CPU_REG_REG(RSI, rsi),
1175	CPU_REG_REG(RDI, rdi),
1176	CPU_REG_REG(R8, r8),
1177	CPU_REG_REG(R9, r9),
1178	CPU_REG_REG(R10, r10),
1179	CPU_REG_REG(R11, r11),
1180	CPU_REG_REG(R12, r12),
1181	CPU_REG_REG(R13, r13),
1182	CPU_REG_REG(R14, r14),
1183	CPU_REG_REG(R15, r15),
1184	CPU_REG_SEG(CS, cs),
1185	CPU_REG_SEG(DS, ds),
1186	CPU_REG_SEG(ES, es),
1187	CPU_REG_SEG(FS, fs),
1188	CPU_REG_SEG(GS, gs),
1189	CPU_REG_SEG(SS, ss),
1190	CPU_REG_REG(RIP, rip),
1191	CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
1192	CPU_REG_RW_AS("fcw", FCW, U16, fpu.FCW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fcw ),
1193	CPU_REG_RW_AS("fsw", FSW, U16, fpu.FSW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fsw ),
1194	CPU_REG_RO_AS("ftw", FTW, U16, fpu, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ),
1195	CPU_REG_RW_AS("fop", FOP, U16, fpu.FOP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1196	CPU_REG_RW_AS("fpuip", FPUIP, U32, fpu.FPUIP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpuip, NULL ),
1197	CPU_REG_RW_AS("fpucs", FPUCS, U16, fpu.CS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1198	CPU_REG_RW_AS("fpudp", FPUDP, U32, fpu.FPUDP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpudp, NULL ),
1199	CPU_REG_RW_AS("fpuds", FPUDS, U16, fpu.DS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1200	CPU_REG_RW_AS("mxcsr", MXCSR, U32, fpu.MXCSR, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
1201	CPU_REG_RW_AS("mxcsr_mask", MXCSR_MASK, U32, fpu.MXCSR_MASK, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
1202	CPU_REG_ST(0),
1203	CPU_REG_ST(1),
1204	CPU_REG_ST(2),
1205	CPU_REG_ST(3),
1206	CPU_REG_ST(4),
1207	CPU_REG_ST(5),
1208	CPU_REG_ST(6),
1209	CPU_REG_ST(7),
1210	CPU_REG_MM(0),
1211	CPU_REG_MM(1),
1212	CPU_REG_MM(2),
1213	CPU_REG_MM(3),
1214	CPU_REG_MM(4),
1215	CPU_REG_MM(5),
1216	CPU_REG_MM(6),
1217	CPU_REG_MM(7),
1218	CPU_REG_XMM(0),
1219	CPU_REG_XMM(1),
1220	CPU_REG_XMM(2),
1221	CPU_REG_XMM(3),
1222	CPU_REG_XMM(4),
1223	CPU_REG_XMM(5),
1224	CPU_REG_XMM(6),
1225	CPU_REG_XMM(7),
1226	CPU_REG_XMM(8),
1227	CPU_REG_XMM(9),
1228	CPU_REG_XMM(10),
1229	CPU_REG_XMM(11),
1230	CPU_REG_XMM(12),
1231	CPU_REG_XMM(13),
1232	CPU_REG_XMM(14),
1233	CPU_REG_XMM(15),
1234	CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1235	CPU_REG_RW_AS("gdtr_limit", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1236	CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1237	CPU_REG_RW_AS("idtr_limit", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1238	CPU_REG_SEG(LDTR, ldtr),
1239	CPU_REG_SEG(TR, tr),
1240	CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
1241	CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, NULL ),
1242	CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, g_aCpumRegFields_cr3 ),
1243	CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, g_aCpumRegFields_cr4 ),
1244	CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, NULL ),
1245	CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1246	CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1247	CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1248	CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1249	CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr6 ),
1250	CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr7 ),
1251	CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
1252	CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
1253	CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
1254	CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
1255	CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ),
1256	CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ),
1257	CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ),
1258	CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
1259	CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
1260	CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
1261	CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
1262	CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
1263	CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
1264	CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
1265	CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
1266	CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
1267	CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1268	CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1269	CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1270	CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1271	CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
1272	CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
1273	DBGFREGDESC_TERMINATOR()
1274	#undef CPU_REG_RW_AS
1275	#undef CPU_REG_RO_AS
1276	#undef CPU_REG_MSR
1277	#undef CPU_REG_ST
1278	};
1279
1280
1281	/**
1282	* Initializes the debugger related sides of the CPUM component.
1283	*
1284	* Called by CPUMR3Init.
1285	*
1286	* @returns VBox status code.
1287	* @param pVM The VM handle.
1288	*/
1289	int cpumR3DbgInit(PVM pVM)
1290	{
1291	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1292	{
1293	int rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegGstDescs, true /fGuestRegs/);
1294	AssertLogRelRCReturn(rc, rc);
1295	rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegHyperDescs, false /fGuestRegs/);
1296	AssertLogRelRCReturn(rc, rc);
1297	}
1298
1299	return VINF_SUCCESS;
1300	}
1301

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp@ 35601

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