CPUMDbg.cpp@ 39057

Last change on this file since 39057 was 39034, checked in by vboxsync, 13 years ago
VMM,INTNET: Addressing unused variable warnings.
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1	/* $Id: CPUMDbg.cpp 39034 2011-10-19 11:43:52Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager, Debugger & Debugging APIs.
4	*/
5
6	/*
7	* Copyright (C) 2010-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DBGF
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/pdmapi.h>
26	#include "CPUMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/param.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/thread.h>
32	#include <iprt/uint128.h>
33
34
35	/**
36	* @interface_method_impl{DBGFREGDESC, pfnGet}
37	*/
38	static DECLCALLBACK(int) cpumR3RegGet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
39	{
40	PVMCPU pVCpu = (PVMCPU)pvUser;
41	void const pv = (uint8_t const )&pVCpu->cpum + pDesc->offRegister;
42
43	VMCPU_ASSERT_EMT(pVCpu);
44
45	switch (pDesc->enmType)
46	{
47	case DBGFREGVALTYPE_U8: pValue->u8 = (uint8_t const )pv; return VINF_SUCCESS;
48	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t const )pv; return VINF_SUCCESS;
49	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t const )pv; return VINF_SUCCESS;
50	case DBGFREGVALTYPE_U64: pValue->u64 = (uint64_t const )pv; return VINF_SUCCESS;
51	case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
52	default:
53	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_INTERNAL_ERROR_3);
54	}
55	}
56
57
58	/**
59	* @interface_method_impl{DBGFREGDESC, pfnGet}
60	*/
61	static DECLCALLBACK(int) cpumR3RegSet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
62	{
63	PVMCPU pVCpu = (PVMCPU)pvUser;
64	void pv = (uint8_t )&pVCpu->cpum + pDesc->offRegister;
65
66	VMCPU_ASSERT_EMT(pVCpu);
67
68	switch (pDesc->enmType)
69	{
70	case DBGFREGVALTYPE_U8:
71	(uint8_t )pv &= ~pfMask->u8;
72	(uint8_t )pv \|= pValue->u8 & pfMask->u8;
73	return VINF_SUCCESS;
74
75	case DBGFREGVALTYPE_U16:
76	(uint16_t )pv &= ~pfMask->u16;
77	(uint16_t )pv \|= pValue->u16 & pfMask->u16;
78	return VINF_SUCCESS;
79
80	case DBGFREGVALTYPE_U32:
81	(uint32_t )pv &= ~pfMask->u32;
82	(uint32_t )pv \|= pValue->u32 & pfMask->u32;
83	return VINF_SUCCESS;
84
85	case DBGFREGVALTYPE_U64:
86	(uint64_t )pv &= ~pfMask->u64;
87	(uint64_t )pv \|= pValue->u64 & pfMask->u64;
88	return VINF_SUCCESS;
89
90	case DBGFREGVALTYPE_U128:
91	{
92	RTUINT128U Val;
93	RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
94	RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
95	return VINF_SUCCESS;
96	}
97
98	default:
99	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_INTERNAL_ERROR_3);
100	}
101	}
102
103
104	/**
105	* @interface_method_impl{DBGFREGDESC, pfnGet}
106	*/
107	static DECLCALLBACK(int) cpumR3RegSet_seg(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
108	{
109	/** @todo perform a selector load, updating hidden selectors and stuff. */
110	return VERR_NOT_IMPLEMENTED;
111	}
112
113
114	/**
115	* @interface_method_impl{DBGFREGDESC, pfnGet}
116	*/
117	static DECLCALLBACK(int) cpumR3RegGet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
118	{
119	PVMCPU pVCpu = (PVMCPU)pvUser;
120	VBOXGDTR const pGdtr = (VBOXGDTR const )((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
121
122	VMCPU_ASSERT_EMT(pVCpu);
123	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
124
125	pValue->dtr.u32Limit = pGdtr->cbGdt;
126	pValue->dtr.u64Base = pGdtr->pGdt;
127	return VINF_SUCCESS;
128	}
129
130
131	/**
132	* @interface_method_impl{DBGFREGDESC, pfnGet}
133	*/
134	static DECLCALLBACK(int) cpumR3RegSet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
135	{
136	return VERR_NOT_IMPLEMENTED;
137	}
138
139
140	/**
141	* @interface_method_impl{DBGFREGDESC, pfnGet}
142	*/
143	static DECLCALLBACK(int) cpumR3RegGet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
144	{
145	PVMCPU pVCpu = (PVMCPU)pvUser;
146	VBOXIDTR const pIdtr = (VBOXIDTR const )((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
147
148	VMCPU_ASSERT_EMT(pVCpu);
149	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
150
151	pValue->dtr.u32Limit = pIdtr->cbIdt;
152	pValue->dtr.u64Base = pIdtr->pIdt;
153	return VINF_SUCCESS;
154	}
155
156
157	/**
158	* @interface_method_impl{DBGFREGDESC, pfnGet}
159	*/
160	static DECLCALLBACK(int) cpumR3RegSet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
161	{
162	return VERR_NOT_IMPLEMENTED;
163	}
164
165
166	/**
167	* Is the FPU state in FXSAVE format or not.
168	*
169	* @returns true if it is, false if it's in FNSAVE.
170	* @param pVCpu The virtual CPU handle.
171	*/
172	DECLINLINE(bool) cpumR3RegIsFxSaveFormat(PVMCPU pVCpu)
173	{
174	#ifdef RT_ARCH_AMD64
175	return true;
176	#else
177	return pVCpu->pVMR3->cpum.s.CPUFeatures.edx.u1FXSR;
178	#endif
179	}
180
181
182	/**
183	* Determins the tag register value for a CPU register when the FPU state
184	* format is FXSAVE.
185	*
186	* @returns The tag register value.
187	* @param pVCpu The virtual CPU handle.
188	* @param iReg The register number (0..7).
189	*/
190	DECLINLINE(uint16_t) cpumR3RegCalcFpuTagFromFxSave(PCX86FXSTATE pFpu, unsigned iReg)
191	{
192	/*
193	* See table 11-1 in the AMD docs.
194	*/
195	if (!(pFpu->FTW & RT_BIT_32(iReg)))
196	return 3; /* b11 - empty */
197
198	uint16_t const uExp = pFpu->aRegs[iReg].au16[4];
199	if (uExp == 0)
200	{
201	if (pFpu->aRegs[iReg].au64[0] == 0) /* J & M == 0 */
202	return 1; /* b01 - zero */
203	return 2; /* b10 - special */
204	}
205
206	if (uExp == UINT16_C(0xffff))
207	return 2; /* b10 - special */
208
209	if (!(pFpu->aRegs[iReg].au64[0] >> 63)) /* J == 0 */
210	return 2; /* b10 - special */
211
212	return 0; /* b00 - valid (normal) */
213	}
214
215
216	/**
217	* @interface_method_impl{DBGFREGDESC, pfnGet}
218	*/
219	static DECLCALLBACK(int) cpumR3RegGet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
220	{
221	PVMCPU pVCpu = (PVMCPU)pvUser;
222	PCX86FXSTATE pFpu = (PCX86FXSTATE)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
223
224	VMCPU_ASSERT_EMT(pVCpu);
225	Assert(pDesc->enmType == DBGFREGVALTYPE_U16);
226
227	if (cpumR3RegIsFxSaveFormat(pVCpu))
228	pValue->u16 = cpumR3RegCalcFpuTagFromFxSave(pFpu, 0)
229	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 1) << 2)
230	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 2) << 4)
231	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 3) << 6)
232	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 4) << 8)
233	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 5) << 10)
234	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 6) << 12)
235	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 7) << 14);
236	else
237	{
238	PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)pFpu;
239	pValue->u16 = pOldFpu->FTW;
240	}
241	return VINF_SUCCESS;
242	}
243
244
245	/**
246	* @interface_method_impl{DBGFREGDESC, pfnGet}
247	*/
248	static DECLCALLBACK(int) cpumR3RegSet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
249	{
250	return VERR_DBGF_READ_ONLY_REGISTER;
251	}
252
253
254
255	/*
256	*
257	* Guest register access functions.
258	*
259	*/
260
261	/**
262	* @interface_method_impl{DBGFREGDESC, pfnGet}
263	*/
264	static DECLCALLBACK(int) cpumR3RegGstGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
265	{
266	PVMCPU pVCpu = (PVMCPU)pvUser;
267	VMCPU_ASSERT_EMT(pVCpu);
268
269	uint64_t u64Value;
270	int rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64Value);
271	AssertRCReturn(rc, rc);
272	switch (pDesc->enmType)
273	{
274	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
275	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
276	default:
277	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
278	}
279	return VINF_SUCCESS;
280	}
281
282
283	/**
284	* @interface_method_impl{DBGFREGDESC, pfnGet}
285	*/
286	static DECLCALLBACK(int) cpumR3RegGstSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
287	{
288	int rc;
289	PVMCPU pVCpu = (PVMCPU)pvUser;
290
291	VMCPU_ASSERT_EMT(pVCpu);
292
293	/*
294	* Calculate the new value.
295	*/
296	uint64_t u64Value;
297	uint64_t fMask;
298	uint64_t fMaskMax;
299	switch (pDesc->enmType)
300	{
301	case DBGFREGVALTYPE_U64:
302	u64Value = pValue->u64;
303	fMask = pfMask->u64;
304	fMaskMax = UINT64_MAX;
305	break;
306	case DBGFREGVALTYPE_U32:
307	u64Value = pValue->u32;
308	fMask = pfMask->u32;
309	fMaskMax = UINT32_MAX;
310	break;
311	default: AssertFailedReturn(VERR_INTERNAL_ERROR_4);
312	}
313	if (fMask != fMaskMax)
314	{
315	uint64_t u64FullValue;
316	rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64FullValue);
317	if (RT_FAILURE(rc))
318	return rc;
319	u64Value = (u64FullValue & ~fMask)
320	\| (u64Value & fMask);
321	}
322
323	/*
324	* Perform the assignment.
325	*/
326	switch (pDesc->offRegister)
327	{
328	case 0: rc = CPUMSetGuestCR0(pVCpu, u64Value); break;
329	case 2: rc = CPUMSetGuestCR2(pVCpu, u64Value); break;
330	case 3: rc = CPUMSetGuestCR3(pVCpu, u64Value); break;
331	case 4: rc = CPUMSetGuestCR4(pVCpu, u64Value); break;
332	case 8: rc = PDMApicSetTPR(pVCpu, (uint8_t)(u64Value << 4)); break;
333	default:
334	AssertFailedReturn(VERR_INTERNAL_ERROR_2);
335	}
336	return rc;
337	}
338
339
340	/**
341	* @interface_method_impl{DBGFREGDESC, pfnGet}
342	*/
343	static DECLCALLBACK(int) cpumR3RegGstGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
344	{
345	PVMCPU pVCpu = (PVMCPU)pvUser;
346	VMCPU_ASSERT_EMT(pVCpu);
347
348	uint64_t u64Value;
349	int rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64Value);
350	AssertRCReturn(rc, rc);
351	switch (pDesc->enmType)
352	{
353	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
354	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
355	default:
356	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
357	}
358	return VINF_SUCCESS;
359	}
360
361
362	/**
363	* @interface_method_impl{DBGFREGDESC, pfnGet}
364	*/
365	static DECLCALLBACK(int) cpumR3RegGstSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
366	{
367	int rc;
368	PVMCPU pVCpu = (PVMCPU)pvUser;
369
370	VMCPU_ASSERT_EMT(pVCpu);
371
372	/*
373	* Calculate the new value.
374	*/
375	uint64_t u64Value;
376	uint64_t fMask;
377	uint64_t fMaskMax;
378	switch (pDesc->enmType)
379	{
380	case DBGFREGVALTYPE_U64:
381	u64Value = pValue->u64;
382	fMask = pfMask->u64;
383	fMaskMax = UINT64_MAX;
384	break;
385	case DBGFREGVALTYPE_U32:
386	u64Value = pValue->u32;
387	fMask = pfMask->u32;
388	fMaskMax = UINT32_MAX;
389	break;
390	default: AssertFailedReturn(VERR_INTERNAL_ERROR_4);
391	}
392	if (fMask != fMaskMax)
393	{
394	uint64_t u64FullValue;
395	rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64FullValue);
396	if (RT_FAILURE(rc))
397	return rc;
398	u64Value = (u64FullValue & ~fMask)
399	\| (u64Value & fMask);
400	}
401
402	/*
403	* Perform the assignment.
404	*/
405	return CPUMSetGuestDRx(pVCpu, pDesc->offRegister, u64Value);
406	}
407
408
409	/**
410	* @interface_method_impl{DBGFREGDESC, pfnGet}
411	*/
412	static DECLCALLBACK(int) cpumR3RegGstGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
413	{
414	PVMCPU pVCpu = (PVMCPU)pvUser;
415	VMCPU_ASSERT_EMT(pVCpu);
416
417	uint64_t u64Value;
418	int rc = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64Value);
419	if (RT_SUCCESS(rc))
420	{
421	switch (pDesc->enmType)
422	{
423	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
424	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
425	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
426	default:
427	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
428	}
429	}
430	/** @todo what to do about errors? */
431	return rc;
432	}
433
434
435	/**
436	* @interface_method_impl{DBGFREGDESC, pfnGet}
437	*/
438	static DECLCALLBACK(int) cpumR3RegGstSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
439	{
440	int rc;
441	PVMCPU pVCpu = (PVMCPU)pvUser;
442
443	VMCPU_ASSERT_EMT(pVCpu);
444
445	/*
446	* Calculate the new value.
447	*/
448	uint64_t u64Value;
449	uint64_t fMask;
450	uint64_t fMaskMax;
451	switch (pDesc->enmType)
452	{
453	case DBGFREGVALTYPE_U64:
454	u64Value = pValue->u64;
455	fMask = pfMask->u64;
456	fMaskMax = UINT64_MAX;
457	break;
458	case DBGFREGVALTYPE_U32:
459	u64Value = pValue->u32;
460	fMask = pfMask->u32;
461	fMaskMax = UINT32_MAX;
462	break;
463	case DBGFREGVALTYPE_U16:
464	u64Value = pValue->u16;
465	fMask = pfMask->u16;
466	fMaskMax = UINT16_MAX;
467	break;
468	default: AssertFailedReturn(VERR_INTERNAL_ERROR_4);
469	}
470	if (fMask != fMaskMax)
471	{
472	uint64_t u64FullValue;
473	rc = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64FullValue);
474	if (RT_FAILURE(rc))
475	return rc;
476	u64Value = (u64FullValue & ~fMask)
477	\| (u64Value & fMask);
478	}
479
480	/*
481	* Perform the assignment.
482	*/
483	return CPUMSetGuestMsr(pVCpu, pDesc->offRegister, u64Value);
484	}
485
486
487	/**
488	* @interface_method_impl{DBGFREGDESC, pfnGet}
489	*/
490	static DECLCALLBACK(int) cpumR3RegGstGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
491	{
492	PVMCPU pVCpu = (PVMCPU)pvUser;
493	VMCPU_ASSERT_EMT(pVCpu);
494	Assert(pDesc->enmType == DBGFREGVALTYPE_R80);
495
496	if (cpumR3RegIsFxSaveFormat(pVCpu))
497	{
498	unsigned iReg = (pVCpu->cpum.s.Guest.fpu.FSW >> 11) & 7;
499	iReg += pDesc->offRegister;
500	iReg &= 7;
501	pValue->r80 = pVCpu->cpum.s.Guest.fpu.aRegs[iReg].r80;
502	}
503	else
504	{
505	PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.fpu;
506
507	unsigned iReg = (pOldFpu->FSW >> 11) & 7;
508	iReg += pDesc->offRegister;
509	iReg &= 7;
510
511	pValue->r80 = pOldFpu->regs[iReg].r80;
512	}
513
514	return VINF_SUCCESS;
515	}
516
517
518	/**
519	* @interface_method_impl{DBGFREGDESC, pfnGet}
520	*/
521	static DECLCALLBACK(int) cpumR3RegGstSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
522	{
523	return VERR_NOT_IMPLEMENTED;
524	}
525
526
527
528	/*
529	*
530	* Hypervisor register access functions.
531	*
532	*/
533
534	/**
535	* @interface_method_impl{DBGFREGDESC, pfnGet}
536	*/
537	static DECLCALLBACK(int) cpumR3RegHyperGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
538	{
539	PVMCPU pVCpu = (PVMCPU)pvUser;
540	VMCPU_ASSERT_EMT(pVCpu);
541
542	uint64_t u64Value;
543	switch (pDesc->offRegister)
544	{
545	case 0: u64Value = UINT64_MAX; break;
546	case 2: u64Value = UINT64_MAX; break;
547	case 3: u64Value = CPUMGetHyperCR3(pVCpu); break;
548	case 4: u64Value = UINT64_MAX; break;
549	case 8: u64Value = UINT64_MAX; break;
550	default:
551	AssertFailedReturn(VERR_INTERNAL_ERROR_3);
552	}
553	switch (pDesc->enmType)
554	{
555	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
556	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
557	default:
558	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
559	}
560	return VINF_SUCCESS;
561	}
562
563
564	/**
565	* @interface_method_impl{DBGFREGDESC, pfnGet}
566	*/
567	static DECLCALLBACK(int) cpumR3RegHyperSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
568	{
569	/* Not settable, prevents killing your host. */
570	return VERR_ACCESS_DENIED;
571	}
572
573
574	/**
575	* @interface_method_impl{DBGFREGDESC, pfnGet}
576	*/
577	static DECLCALLBACK(int) cpumR3RegHyperGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
578	{
579	PVMCPU pVCpu = (PVMCPU)pvUser;
580	VMCPU_ASSERT_EMT(pVCpu);
581
582	uint64_t u64Value;
583	switch (pDesc->offRegister)
584	{
585	case 0: u64Value = CPUMGetHyperDR0(pVCpu); break;
586	case 1: u64Value = CPUMGetHyperDR1(pVCpu); break;
587	case 2: u64Value = CPUMGetHyperDR2(pVCpu); break;
588	case 3: u64Value = CPUMGetHyperDR3(pVCpu); break;
589	case 6: u64Value = CPUMGetHyperDR6(pVCpu); break;
590	case 7: u64Value = CPUMGetHyperDR7(pVCpu); break;
591	default:
592	AssertFailedReturn(VERR_INTERNAL_ERROR_3);
593	}
594	switch (pDesc->enmType)
595	{
596	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
597	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
598	default:
599	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
600	}
601	return VINF_SUCCESS;
602	}
603
604
605	/**
606	* @interface_method_impl{DBGFREGDESC, pfnGet}
607	*/
608	static DECLCALLBACK(int) cpumR3RegHyperSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
609	{
610	/* Not settable, prevents killing your host. */
611	return VERR_ACCESS_DENIED;
612	}
613
614
615	/**
616	* @interface_method_impl{DBGFREGDESC, pfnGet}
617	*/
618	static DECLCALLBACK(int) cpumR3RegHyperGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
619	{
620	/* Not availble at present, return all FFs to keep things quiet */
621	uint64_t u64Value = UINT64_MAX;
622	switch (pDesc->enmType)
623	{
624	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
625	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
626	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
627	default:
628	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
629	}
630	return VINF_SUCCESS;
631	}
632
633
634	/**
635	* @interface_method_impl{DBGFREGDESC, pfnGet}
636	*/
637	static DECLCALLBACK(int) cpumR3RegHyperSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
638	{
639	/* Not settable, return failure. */
640	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
641	return VERR_ACCESS_DENIED;
642	}
643
644
645	/**
646	* @interface_method_impl{DBGFREGDESC, pfnGet}
647	*/
648	static DECLCALLBACK(int) cpumR3RegHyperGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
649	{
650	PVMCPU pVCpu = (PVMCPU)pvUser;
651
652	VMCPU_ASSERT_EMT(pVCpu);
653	Assert(pDesc->enmType == DBGFREGVALTYPE_R80);
654
655	if (cpumR3RegIsFxSaveFormat(pVCpu))
656	{
657	unsigned iReg = (pVCpu->cpum.s.Guest.fpu.FSW >> 11) & 7;
658	iReg += pDesc->offRegister;
659	iReg &= 7;
660	pValue->r80 = pVCpu->cpum.s.Guest.fpu.aRegs[iReg].r80;
661	}
662	else
663	{
664	PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.fpu;
665
666	unsigned iReg = (pOldFpu->FSW >> 11) & 7;
667	iReg += pDesc->offRegister;
668	iReg &= 7;
669
670	pValue->r80 = pOldFpu->regs[iReg].r80;
671	}
672
673	return VINF_SUCCESS;
674	}
675
676
677	/**
678	* @interface_method_impl{DBGFREGDESC, pfnGet}
679	*/
680	static DECLCALLBACK(int) cpumR3RegHyperSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
681	{
682	/* There isn't a FPU context for the hypervisor yet, so no point in trying to set stuff. */
683	return VERR_ACCESS_DENIED;
684	}
685
686
687
688	/*
689	* Set up aliases.
690	*/
691	#define CPUMREGALIAS_STD(Name, psz32, psz16, psz8) \
692	static DBGFREGALIAS const g_aCpumRegAliases_##Name[] = \
693	{ \
694	{ psz32, DBGFREGVALTYPE_U32 }, \
695	{ psz16, DBGFREGVALTYPE_U16 }, \
696	{ psz8, DBGFREGVALTYPE_U8 }, \
697	{ NULL, DBGFREGVALTYPE_INVALID } \
698	}
699	CPUMREGALIAS_STD(rax, "eax", "ax", "al");
700	CPUMREGALIAS_STD(rcx, "ecx", "cx", "cl");
701	CPUMREGALIAS_STD(rdx, "edx", "dx", "dl");
702	CPUMREGALIAS_STD(rbx, "ebx", "bx", "bl");
703	CPUMREGALIAS_STD(rsp, "esp", "sp", NULL);
704	CPUMREGALIAS_STD(rbp, "ebp", "bp", NULL);
705	CPUMREGALIAS_STD(rsi, "esi", "si", "sil");
706	CPUMREGALIAS_STD(rdi, "edi", "di", "dil");
707	CPUMREGALIAS_STD(r8, "r8d", "r8w", "r8b");
708	CPUMREGALIAS_STD(r9, "r9d", "r9w", "r9b");
709	CPUMREGALIAS_STD(r10, "r10d", "r10w", "r10b");
710	CPUMREGALIAS_STD(r11, "r11d", "r11w", "r11b");
711	CPUMREGALIAS_STD(r12, "r12d", "r12w", "r12b");
712	CPUMREGALIAS_STD(r13, "r13d", "r13w", "r13b");
713	CPUMREGALIAS_STD(r14, "r14d", "r14w", "r14b");
714	CPUMREGALIAS_STD(r15, "r15d", "r15w", "r15b");
715	CPUMREGALIAS_STD(rip, "eip", "ip", NULL);
716	CPUMREGALIAS_STD(rflags, "eflags", "flags", NULL);
717	#undef CPUMREGALIAS_STD
718
719	static DBGFREGALIAS const g_aCpumRegAliases_fpuip[] =
720	{
721	{ "fpuip16", DBGFREGVALTYPE_U16 },
722	{ NULL, DBGFREGVALTYPE_INVALID }
723	};
724
725	static DBGFREGALIAS const g_aCpumRegAliases_fpudp[] =
726	{
727	{ "fpudp16", DBGFREGVALTYPE_U16 },
728	{ NULL, DBGFREGVALTYPE_INVALID }
729	};
730
731	static DBGFREGALIAS const g_aCpumRegAliases_cr0[] =
732	{
733	{ "msw", DBGFREGVALTYPE_U16 },
734	{ NULL, DBGFREGVALTYPE_INVALID }
735	};
736
737	/*
738	* Sub fields.
739	*/
740	/** Sub-fields for the (hidden) segment attribute register. */
741	static DBGFREGSUBFIELD const g_aCpumRegFields_seg[] =
742	{
743	DBGFREGSUBFIELD_RW("type", 0, 4, 0),
744	DBGFREGSUBFIELD_RW("s", 4, 1, 0),
745	DBGFREGSUBFIELD_RW("dpl", 5, 2, 0),
746	DBGFREGSUBFIELD_RW("p", 7, 1, 0),
747	DBGFREGSUBFIELD_RW("avl", 12, 1, 0),
748	DBGFREGSUBFIELD_RW("l", 13, 1, 0),
749	DBGFREGSUBFIELD_RW("d", 14, 1, 0),
750	DBGFREGSUBFIELD_RW("g", 15, 1, 0),
751	DBGFREGSUBFIELD_TERMINATOR()
752	};
753
754	/** Sub-fields for the flags register. */
755	static DBGFREGSUBFIELD const g_aCpumRegFields_rflags[] =
756	{
757	DBGFREGSUBFIELD_RW("cf", 0, 1, 0),
758	DBGFREGSUBFIELD_RW("pf", 2, 1, 0),
759	DBGFREGSUBFIELD_RW("af", 4, 1, 0),
760	DBGFREGSUBFIELD_RW("zf", 6, 1, 0),
761	DBGFREGSUBFIELD_RW("sf", 7, 1, 0),
762	DBGFREGSUBFIELD_RW("tf", 8, 1, 0),
763	DBGFREGSUBFIELD_RW("if", 9, 1, 0),
764	DBGFREGSUBFIELD_RW("df", 10, 1, 0),
765	DBGFREGSUBFIELD_RW("of", 11, 1, 0),
766	DBGFREGSUBFIELD_RW("iopl", 12, 2, 0),
767	DBGFREGSUBFIELD_RW("nt", 14, 1, 0),
768	DBGFREGSUBFIELD_RW("rf", 16, 1, 0),
769	DBGFREGSUBFIELD_RW("vm", 17, 1, 0),
770	DBGFREGSUBFIELD_RW("ac", 18, 1, 0),
771	DBGFREGSUBFIELD_RW("vif", 19, 1, 0),
772	DBGFREGSUBFIELD_RW("vip", 20, 1, 0),
773	DBGFREGSUBFIELD_RW("id", 21, 1, 0),
774	DBGFREGSUBFIELD_TERMINATOR()
775	};
776
777	/** Sub-fields for the FPU control word register. */
778	static DBGFREGSUBFIELD const g_aCpumRegFields_fcw[] =
779	{
780	DBGFREGSUBFIELD_RW("im", 1, 1, 0),
781	DBGFREGSUBFIELD_RW("dm", 2, 1, 0),
782	DBGFREGSUBFIELD_RW("zm", 3, 1, 0),
783	DBGFREGSUBFIELD_RW("om", 4, 1, 0),
784	DBGFREGSUBFIELD_RW("um", 5, 1, 0),
785	DBGFREGSUBFIELD_RW("pm", 6, 1, 0),
786	DBGFREGSUBFIELD_RW("pc", 8, 2, 0),
787	DBGFREGSUBFIELD_RW("rc", 10, 2, 0),
788	DBGFREGSUBFIELD_RW("x", 12, 1, 0),
789	DBGFREGSUBFIELD_TERMINATOR()
790	};
791
792	/** Sub-fields for the FPU status word register. */
793	static DBGFREGSUBFIELD const g_aCpumRegFields_fsw[] =
794	{
795	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
796	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
797	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
798	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
799	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
800	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
801	DBGFREGSUBFIELD_RW("se", 6, 1, 0),
802	DBGFREGSUBFIELD_RW("es", 7, 1, 0),
803	DBGFREGSUBFIELD_RW("c0", 8, 1, 0),
804	DBGFREGSUBFIELD_RW("c1", 9, 1, 0),
805	DBGFREGSUBFIELD_RW("c2", 10, 1, 0),
806	DBGFREGSUBFIELD_RW("top", 11, 3, 0),
807	DBGFREGSUBFIELD_RW("c3", 14, 1, 0),
808	DBGFREGSUBFIELD_RW("b", 15, 1, 0),
809	DBGFREGSUBFIELD_TERMINATOR()
810	};
811
812	/** Sub-fields for the FPU tag word register. */
813	static DBGFREGSUBFIELD const g_aCpumRegFields_ftw[] =
814	{
815	DBGFREGSUBFIELD_RW("tag0", 0, 2, 0),
816	DBGFREGSUBFIELD_RW("tag1", 2, 2, 0),
817	DBGFREGSUBFIELD_RW("tag2", 4, 2, 0),
818	DBGFREGSUBFIELD_RW("tag3", 6, 2, 0),
819	DBGFREGSUBFIELD_RW("tag4", 8, 2, 0),
820	DBGFREGSUBFIELD_RW("tag5", 10, 2, 0),
821	DBGFREGSUBFIELD_RW("tag6", 12, 2, 0),
822	DBGFREGSUBFIELD_RW("tag7", 14, 2, 0),
823	DBGFREGSUBFIELD_TERMINATOR()
824	};
825
826	/** Sub-fields for the Multimedia Extensions Control and Status Register. */
827	static DBGFREGSUBFIELD const g_aCpumRegFields_mxcsr[] =
828	{
829	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
830	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
831	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
832	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
833	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
834	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
835	DBGFREGSUBFIELD_RW("daz", 6, 1, 0),
836	DBGFREGSUBFIELD_RW("im", 7, 1, 0),
837	DBGFREGSUBFIELD_RW("dm", 8, 1, 0),
838	DBGFREGSUBFIELD_RW("zm", 9, 1, 0),
839	DBGFREGSUBFIELD_RW("om", 10, 1, 0),
840	DBGFREGSUBFIELD_RW("um", 11, 1, 0),
841	DBGFREGSUBFIELD_RW("pm", 12, 1, 0),
842	DBGFREGSUBFIELD_RW("rc", 13, 2, 0),
843	DBGFREGSUBFIELD_RW("fz", 14, 1, 0),
844	DBGFREGSUBFIELD_TERMINATOR()
845	};
846
847	/** Sub-fields for the FPU tag word register. */
848	static DBGFREGSUBFIELD const g_aCpumRegFields_stN[] =
849	{
850	DBGFREGSUBFIELD_RW("man", 0, 64, 0),
851	DBGFREGSUBFIELD_RW("exp", 64, 15, 0),
852	DBGFREGSUBFIELD_RW("sig", 79, 1, 0),
853	DBGFREGSUBFIELD_TERMINATOR()
854	};
855
856	/** Sub-fields for the MMX registers. */
857	static DBGFREGSUBFIELD const g_aCpumRegFields_mmN[] =
858	{
859	DBGFREGSUBFIELD_RW("dw0", 0, 32, 0),
860	DBGFREGSUBFIELD_RW("dw1", 32, 32, 0),
861	DBGFREGSUBFIELD_RW("w0", 0, 16, 0),
862	DBGFREGSUBFIELD_RW("w1", 16, 16, 0),
863	DBGFREGSUBFIELD_RW("w2", 32, 16, 0),
864	DBGFREGSUBFIELD_RW("w3", 48, 16, 0),
865	DBGFREGSUBFIELD_RW("b0", 0, 8, 0),
866	DBGFREGSUBFIELD_RW("b1", 8, 8, 0),
867	DBGFREGSUBFIELD_RW("b2", 16, 8, 0),
868	DBGFREGSUBFIELD_RW("b3", 24, 8, 0),
869	DBGFREGSUBFIELD_RW("b4", 32, 8, 0),
870	DBGFREGSUBFIELD_RW("b5", 40, 8, 0),
871	DBGFREGSUBFIELD_RW("b6", 48, 8, 0),
872	DBGFREGSUBFIELD_RW("b7", 56, 8, 0),
873	DBGFREGSUBFIELD_TERMINATOR()
874	};
875
876	/** Sub-fields for the XMM registers. */
877	static DBGFREGSUBFIELD const g_aCpumRegFields_xmmN[] =
878	{
879	DBGFREGSUBFIELD_RW("r0", 0, 32, 0),
880	DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0),
881	DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0),
882	DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0),
883	DBGFREGSUBFIELD_RW("r1", 32, 32, 0),
884	DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0),
885	DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0),
886	DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0),
887	DBGFREGSUBFIELD_RW("r2", 64, 32, 0),
888	DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0),
889	DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0),
890	DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0),
891	DBGFREGSUBFIELD_RW("r3", 96, 32, 0),
892	DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0),
893	DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0),
894	DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0),
895	DBGFREGSUBFIELD_TERMINATOR()
896	};
897
898	/** Sub-fields for the CR0 register. */
899	static DBGFREGSUBFIELD const g_aCpumRegFields_cr0[] =
900	{
901	/** @todo */
902	DBGFREGSUBFIELD_TERMINATOR()
903	};
904
905	/** Sub-fields for the CR3 register. */
906	static DBGFREGSUBFIELD const g_aCpumRegFields_cr3[] =
907	{
908	/** @todo */
909	DBGFREGSUBFIELD_TERMINATOR()
910	};
911
912	/** Sub-fields for the CR4 register. */
913	static DBGFREGSUBFIELD const g_aCpumRegFields_cr4[] =
914	{
915	/** @todo */
916	DBGFREGSUBFIELD_TERMINATOR()
917	};
918
919	/** Sub-fields for the DR6 register. */
920	static DBGFREGSUBFIELD const g_aCpumRegFields_dr6[] =
921	{
922	/** @todo */
923	DBGFREGSUBFIELD_TERMINATOR()
924	};
925
926	/** Sub-fields for the DR7 register. */
927	static DBGFREGSUBFIELD const g_aCpumRegFields_dr7[] =
928	{
929	/** @todo */
930	DBGFREGSUBFIELD_TERMINATOR()
931	};
932
933	/** Sub-fields for the CR_PAT MSR. */
934	static DBGFREGSUBFIELD const g_aCpumRegFields_apic_base[] =
935	{
936	DBGFREGSUBFIELD_RW("bsp", 8, 1, 0),
937	DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
938	DBGFREGSUBFIELD_RW("base", 12, 20, 12),
939	DBGFREGSUBFIELD_TERMINATOR()
940	};
941
942	/** Sub-fields for the CR_PAT MSR. */
943	static DBGFREGSUBFIELD const g_aCpumRegFields_cr_pat[] =
944	{
945	/** @todo */
946	DBGFREGSUBFIELD_TERMINATOR()
947	};
948
949	/** Sub-fields for the PERF_STATUS MSR. */
950	static DBGFREGSUBFIELD const g_aCpumRegFields_perf_status[] =
951	{
952	/** @todo */
953	DBGFREGSUBFIELD_TERMINATOR()
954	};
955
956	/** Sub-fields for the EFER MSR. */
957	static DBGFREGSUBFIELD const g_aCpumRegFields_efer[] =
958	{
959	/** @todo */
960	DBGFREGSUBFIELD_TERMINATOR()
961	};
962
963	/** Sub-fields for the STAR MSR. */
964	static DBGFREGSUBFIELD const g_aCpumRegFields_star[] =
965	{
966	/** @todo */
967	DBGFREGSUBFIELD_TERMINATOR()
968	};
969
970	/** Sub-fields for the CSTAR MSR. */
971	static DBGFREGSUBFIELD const g_aCpumRegFields_cstar[] =
972	{
973	/** @todo */
974	DBGFREGSUBFIELD_TERMINATOR()
975	};
976
977	/** Sub-fields for the LSTAR MSR. */
978	static DBGFREGSUBFIELD const g_aCpumRegFields_lstar[] =
979	{
980	/** @todo */
981	DBGFREGSUBFIELD_TERMINATOR()
982	};
983
984	/** Sub-fields for the SF_MASK MSR. */
985	static DBGFREGSUBFIELD const g_aCpumRegFields_sf_mask[] =
986	{
987	/** @todo */
988	DBGFREGSUBFIELD_TERMINATOR()
989	};
990
991
992	/** @name Macros for producing register descriptor table entries.
993	* @{ */
994	#define CPU_REG_EX_AS(a_szName, a_RegSuff, a_TypeSuff, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
995	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
996
997	#define CPU_REG_REG(UName, LName) \
998	CPU_REG_RW_AS(#LName, UName, U64, LName, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_##LName, NULL)
999
1000	#define CPU_REG_SEG(UName, LName) \
1001	CPU_REG_RW_AS(#LName, UName, U16, LName, cpumR3RegGet_Generic, cpumR3RegSet_seg, NULL, NULL ), \
1002	CPU_REG_RW_AS(#LName "_attr", UName##_ATTR, U32, LName##Hid.Attr.u, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_seg), \
1003	CPU_REG_RW_AS(#LName "_base", UName##_BASE, U64, LName##Hid.u64Base, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), \
1004	CPU_REG_RW_AS(#LName "_lim", UName##_LIMIT, U32, LName##Hid.u32Limit, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL )
1005
1006	#define CPU_REG_MM(n) \
1007	CPU_REG_RW_AS("mm" #n, MM##n, U64, fpu.aRegs[n].mmx, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mmN)
1008
1009	#define CPU_REG_XMM(n) \
1010	CPU_REG_RW_AS("xmm" #n, XMM##n, U128, fpu.aXMM[n].xmm, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_xmmN)
1011	/** @} */
1012
1013
1014	/**
1015	* The guest register descriptors.
1016	*/
1017	static DBGFREGDESC const g_aCpumRegGstDescs[] =
1018	{
1019	#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1020	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1021	#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1022	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1023	#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
1024	CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegGstGet_msr, cpumR3RegGstSet_msr, NULL, a_paSubFields)
1025	#define CPU_REG_ST(n) \
1026	CPU_REG_EX_AS("st" #n, ST##n, R80, n, cpumR3RegGstGet_stN, cpumR3RegGstSet_stN, NULL, g_aCpumRegFields_stN)
1027
1028	CPU_REG_REG(RAX, rax),
1029	CPU_REG_REG(RCX, rcx),
1030	CPU_REG_REG(RDX, rdx),
1031	CPU_REG_REG(RBX, rbx),
1032	CPU_REG_REG(RSP, rsp),
1033	CPU_REG_REG(RBP, rbp),
1034	CPU_REG_REG(RSI, rsi),
1035	CPU_REG_REG(RDI, rdi),
1036	CPU_REG_REG(R8, r8),
1037	CPU_REG_REG(R9, r9),
1038	CPU_REG_REG(R10, r10),
1039	CPU_REG_REG(R11, r11),
1040	CPU_REG_REG(R12, r12),
1041	CPU_REG_REG(R13, r13),
1042	CPU_REG_REG(R14, r14),
1043	CPU_REG_REG(R15, r15),
1044	CPU_REG_SEG(CS, cs),
1045	CPU_REG_SEG(DS, ds),
1046	CPU_REG_SEG(ES, es),
1047	CPU_REG_SEG(FS, fs),
1048	CPU_REG_SEG(GS, gs),
1049	CPU_REG_SEG(SS, ss),
1050	CPU_REG_REG(RIP, rip),
1051	CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
1052	CPU_REG_RW_AS("fcw", FCW, U16, fpu.FCW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fcw ),
1053	CPU_REG_RW_AS("fsw", FSW, U16, fpu.FSW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fsw ),
1054	CPU_REG_RO_AS("ftw", FTW, U16, fpu, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ),
1055	CPU_REG_RW_AS("fop", FOP, U16, fpu.FOP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1056	CPU_REG_RW_AS("fpuip", FPUIP, U32, fpu.FPUIP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpuip, NULL ),
1057	CPU_REG_RW_AS("fpucs", FPUCS, U16, fpu.CS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1058	CPU_REG_RW_AS("fpudp", FPUDP, U32, fpu.FPUDP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpudp, NULL ),
1059	CPU_REG_RW_AS("fpuds", FPUDS, U16, fpu.DS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1060	CPU_REG_RW_AS("mxcsr", MXCSR, U32, fpu.MXCSR, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
1061	CPU_REG_RW_AS("mxcsr_mask", MXCSR_MASK, U32, fpu.MXCSR_MASK, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
1062	CPU_REG_ST(0),
1063	CPU_REG_ST(1),
1064	CPU_REG_ST(2),
1065	CPU_REG_ST(3),
1066	CPU_REG_ST(4),
1067	CPU_REG_ST(5),
1068	CPU_REG_ST(6),
1069	CPU_REG_ST(7),
1070	CPU_REG_MM(0),
1071	CPU_REG_MM(1),
1072	CPU_REG_MM(2),
1073	CPU_REG_MM(3),
1074	CPU_REG_MM(4),
1075	CPU_REG_MM(5),
1076	CPU_REG_MM(6),
1077	CPU_REG_MM(7),
1078	CPU_REG_XMM(0),
1079	CPU_REG_XMM(1),
1080	CPU_REG_XMM(2),
1081	CPU_REG_XMM(3),
1082	CPU_REG_XMM(4),
1083	CPU_REG_XMM(5),
1084	CPU_REG_XMM(6),
1085	CPU_REG_XMM(7),
1086	CPU_REG_XMM(8),
1087	CPU_REG_XMM(9),
1088	CPU_REG_XMM(10),
1089	CPU_REG_XMM(11),
1090	CPU_REG_XMM(12),
1091	CPU_REG_XMM(13),
1092	CPU_REG_XMM(14),
1093	CPU_REG_XMM(15),
1094	CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1095	CPU_REG_RW_AS("gdtr_lim", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1096	CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1097	CPU_REG_RW_AS("idtr_lim", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1098	CPU_REG_SEG(LDTR, ldtr),
1099	CPU_REG_SEG(TR, tr),
1100	CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
1101	CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1102	CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr3 ),
1103	CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr4 ),
1104	CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1105	CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1106	CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1107	CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1108	CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1109	CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr6 ),
1110	CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr7 ),
1111	CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
1112	CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
1113	CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
1114	CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
1115	CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ),
1116	CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ),
1117	CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ),
1118	CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
1119	CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
1120	CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
1121	CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
1122	CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
1123	CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
1124	CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
1125	CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
1126	CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
1127	CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Guest.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1128	CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Guest.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1129	CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Guest.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1130	CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Guest.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1131	CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
1132	CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
1133	DBGFREGDESC_TERMINATOR()
1134
1135	#undef CPU_REG_RW_AS
1136	#undef CPU_REG_RO_AS
1137	#undef CPU_REG_MSR
1138	#undef CPU_REG_ST
1139	};
1140
1141
1142	/**
1143	* The hypervisor (raw-mode) register descriptors.
1144	*/
1145	static DBGFREGDESC const g_aCpumRegHyperDescs[] =
1146	{
1147	#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1148	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(CPUMCPU, Hyper.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1149	#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1150	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Hyper.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1151	#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
1152	CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegHyperGet_msr, cpumR3RegHyperSet_msr, NULL, a_paSubFields)
1153	#define CPU_REG_ST(n) \
1154	CPU_REG_EX_AS("st" #n, ST##n, R80, n, cpumR3RegHyperGet_stN, cpumR3RegHyperSet_stN, NULL, g_aCpumRegFields_stN)
1155
1156	CPU_REG_REG(RAX, rax),
1157	CPU_REG_REG(RCX, rcx),
1158	CPU_REG_REG(RDX, rdx),
1159	CPU_REG_REG(RBX, rbx),
1160	CPU_REG_REG(RSP, rsp),
1161	CPU_REG_REG(RBP, rbp),
1162	CPU_REG_REG(RSI, rsi),
1163	CPU_REG_REG(RDI, rdi),
1164	CPU_REG_REG(R8, r8),
1165	CPU_REG_REG(R9, r9),
1166	CPU_REG_REG(R10, r10),
1167	CPU_REG_REG(R11, r11),
1168	CPU_REG_REG(R12, r12),
1169	CPU_REG_REG(R13, r13),
1170	CPU_REG_REG(R14, r14),
1171	CPU_REG_REG(R15, r15),
1172	CPU_REG_SEG(CS, cs),
1173	CPU_REG_SEG(DS, ds),
1174	CPU_REG_SEG(ES, es),
1175	CPU_REG_SEG(FS, fs),
1176	CPU_REG_SEG(GS, gs),
1177	CPU_REG_SEG(SS, ss),
1178	CPU_REG_REG(RIP, rip),
1179	CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
1180	CPU_REG_RW_AS("fcw", FCW, U16, fpu.FCW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fcw ),
1181	CPU_REG_RW_AS("fsw", FSW, U16, fpu.FSW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fsw ),
1182	CPU_REG_RO_AS("ftw", FTW, U16, fpu, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ),
1183	CPU_REG_RW_AS("fop", FOP, U16, fpu.FOP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1184	CPU_REG_RW_AS("fpuip", FPUIP, U32, fpu.FPUIP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpuip, NULL ),
1185	CPU_REG_RW_AS("fpucs", FPUCS, U16, fpu.CS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1186	CPU_REG_RW_AS("fpudp", FPUDP, U32, fpu.FPUDP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpudp, NULL ),
1187	CPU_REG_RW_AS("fpuds", FPUDS, U16, fpu.DS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1188	CPU_REG_RW_AS("mxcsr", MXCSR, U32, fpu.MXCSR, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
1189	CPU_REG_RW_AS("mxcsr_mask", MXCSR_MASK, U32, fpu.MXCSR_MASK, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
1190	CPU_REG_ST(0),
1191	CPU_REG_ST(1),
1192	CPU_REG_ST(2),
1193	CPU_REG_ST(3),
1194	CPU_REG_ST(4),
1195	CPU_REG_ST(5),
1196	CPU_REG_ST(6),
1197	CPU_REG_ST(7),
1198	CPU_REG_MM(0),
1199	CPU_REG_MM(1),
1200	CPU_REG_MM(2),
1201	CPU_REG_MM(3),
1202	CPU_REG_MM(4),
1203	CPU_REG_MM(5),
1204	CPU_REG_MM(6),
1205	CPU_REG_MM(7),
1206	CPU_REG_XMM(0),
1207	CPU_REG_XMM(1),
1208	CPU_REG_XMM(2),
1209	CPU_REG_XMM(3),
1210	CPU_REG_XMM(4),
1211	CPU_REG_XMM(5),
1212	CPU_REG_XMM(6),
1213	CPU_REG_XMM(7),
1214	CPU_REG_XMM(8),
1215	CPU_REG_XMM(9),
1216	CPU_REG_XMM(10),
1217	CPU_REG_XMM(11),
1218	CPU_REG_XMM(12),
1219	CPU_REG_XMM(13),
1220	CPU_REG_XMM(14),
1221	CPU_REG_XMM(15),
1222	CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1223	CPU_REG_RW_AS("gdtr_lim", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1224	CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1225	CPU_REG_RW_AS("idtr_lim", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1226	CPU_REG_SEG(LDTR, ldtr),
1227	CPU_REG_SEG(TR, tr),
1228	CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
1229	CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, NULL ),
1230	CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, g_aCpumRegFields_cr3 ),
1231	CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, g_aCpumRegFields_cr4 ),
1232	CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, NULL ),
1233	CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1234	CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1235	CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1236	CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1237	CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr6 ),
1238	CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr7 ),
1239	CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
1240	CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
1241	CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
1242	CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
1243	CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ),
1244	CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ),
1245	CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ),
1246	CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
1247	CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
1248	CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
1249	CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
1250	CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
1251	CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
1252	CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
1253	CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
1254	CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
1255	CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1256	CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1257	CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1258	CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1259	CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
1260	CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
1261	DBGFREGDESC_TERMINATOR()
1262	#undef CPU_REG_RW_AS
1263	#undef CPU_REG_RO_AS
1264	#undef CPU_REG_MSR
1265	#undef CPU_REG_ST
1266	};
1267
1268
1269	/**
1270	* Initializes the debugger related sides of the CPUM component.
1271	*
1272	* Called by CPUMR3Init.
1273	*
1274	* @returns VBox status code.
1275	* @param pVM The VM handle.
1276	*/
1277	int cpumR3DbgInit(PVM pVM)
1278	{
1279	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1280	{
1281	int rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegGstDescs, true /fGuestRegs/);
1282	AssertLogRelRCReturn(rc, rc);
1283	rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegHyperDescs, false /fGuestRegs/);
1284	AssertLogRelRCReturn(rc, rc);
1285	}
1286
1287	return VINF_SUCCESS;
1288	}
1289

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp@ 39057

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