CPUMDbg.cpp@ 39078

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1	/* $Id: CPUMDbg.cpp 39078 2011-10-21 14:18:22Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager, Debugger & Debugging APIs.
4	*/
5
6	/*
7	* Copyright (C) 2010-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DBGF
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/pdmapi.h>
26	#include "CPUMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/param.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/thread.h>
32	#include <iprt/uint128.h>
33
34
35	/**
36	* @interface_method_impl{DBGFREGDESC, pfnGet}
37	*/
38	static DECLCALLBACK(int) cpumR3RegGet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
39	{
40	PVMCPU pVCpu = (PVMCPU)pvUser;
41	void const pv = (uint8_t const )&pVCpu->cpum + pDesc->offRegister;
42
43	VMCPU_ASSERT_EMT(pVCpu);
44
45	switch (pDesc->enmType)
46	{
47	case DBGFREGVALTYPE_U8: pValue->u8 = (uint8_t const )pv; return VINF_SUCCESS;
48	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t const )pv; return VINF_SUCCESS;
49	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t const )pv; return VINF_SUCCESS;
50	case DBGFREGVALTYPE_U64: pValue->u64 = (uint64_t const )pv; return VINF_SUCCESS;
51	case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
52	default:
53	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_INTERNAL_ERROR_3);
54	}
55	}
56
57
58	/**
59	* @interface_method_impl{DBGFREGDESC, pfnGet}
60	*/
61	static DECLCALLBACK(int) cpumR3RegSet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
62	{
63	PVMCPU pVCpu = (PVMCPU)pvUser;
64	void pv = (uint8_t )&pVCpu->cpum + pDesc->offRegister;
65
66	VMCPU_ASSERT_EMT(pVCpu);
67
68	switch (pDesc->enmType)
69	{
70	case DBGFREGVALTYPE_U8:
71	(uint8_t )pv &= ~pfMask->u8;
72	(uint8_t )pv \|= pValue->u8 & pfMask->u8;
73	return VINF_SUCCESS;
74
75	case DBGFREGVALTYPE_U16:
76	(uint16_t )pv &= ~pfMask->u16;
77	(uint16_t )pv \|= pValue->u16 & pfMask->u16;
78	return VINF_SUCCESS;
79
80	case DBGFREGVALTYPE_U32:
81	(uint32_t )pv &= ~pfMask->u32;
82	(uint32_t )pv \|= pValue->u32 & pfMask->u32;
83	return VINF_SUCCESS;
84
85	case DBGFREGVALTYPE_U64:
86	(uint64_t )pv &= ~pfMask->u64;
87	(uint64_t )pv \|= pValue->u64 & pfMask->u64;
88	return VINF_SUCCESS;
89
90	case DBGFREGVALTYPE_U128:
91	{
92	RTUINT128U Val;
93	RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
94	RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
95	return VINF_SUCCESS;
96	}
97
98	default:
99	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_INTERNAL_ERROR_3);
100	}
101	}
102
103
104	/**
105	* @interface_method_impl{DBGFREGDESC, pfnGet}
106	*/
107	static DECLCALLBACK(int) cpumR3RegSet_seg(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
108	{
109	/** @todo perform a selector load, updating hidden selectors and stuff. */
110	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
111	return VERR_NOT_IMPLEMENTED;
112	}
113
114
115	/**
116	* @interface_method_impl{DBGFREGDESC, pfnGet}
117	*/
118	static DECLCALLBACK(int) cpumR3RegGet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
119	{
120	PVMCPU pVCpu = (PVMCPU)pvUser;
121	VBOXGDTR const pGdtr = (VBOXGDTR const )((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
122
123	VMCPU_ASSERT_EMT(pVCpu);
124	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
125
126	pValue->dtr.u32Limit = pGdtr->cbGdt;
127	pValue->dtr.u64Base = pGdtr->pGdt;
128	return VINF_SUCCESS;
129	}
130
131
132	/**
133	* @interface_method_impl{DBGFREGDESC, pfnGet}
134	*/
135	static DECLCALLBACK(int) cpumR3RegSet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
136	{
137	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
138	return VERR_NOT_IMPLEMENTED;
139	}
140
141
142	/**
143	* @interface_method_impl{DBGFREGDESC, pfnGet}
144	*/
145	static DECLCALLBACK(int) cpumR3RegGet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
146	{
147	PVMCPU pVCpu = (PVMCPU)pvUser;
148	VBOXIDTR const pIdtr = (VBOXIDTR const )((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
149
150	VMCPU_ASSERT_EMT(pVCpu);
151	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
152
153	pValue->dtr.u32Limit = pIdtr->cbIdt;
154	pValue->dtr.u64Base = pIdtr->pIdt;
155	return VINF_SUCCESS;
156	}
157
158
159	/**
160	* @interface_method_impl{DBGFREGDESC, pfnGet}
161	*/
162	static DECLCALLBACK(int) cpumR3RegSet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
163	{
164	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
165	return VERR_NOT_IMPLEMENTED;
166	}
167
168
169	/**
170	* Is the FPU state in FXSAVE format or not.
171	*
172	* @returns true if it is, false if it's in FNSAVE.
173	* @param pVCpu The virtual CPU handle.
174	*/
175	DECLINLINE(bool) cpumR3RegIsFxSaveFormat(PVMCPU pVCpu)
176	{
177	#ifdef RT_ARCH_AMD64
178	NOREF(pVCpu);
179	return true;
180	#else
181	return pVCpu->pVMR3->cpum.s.CPUFeatures.edx.u1FXSR;
182	#endif
183	}
184
185
186	/**
187	* Determins the tag register value for a CPU register when the FPU state
188	* format is FXSAVE.
189	*
190	* @returns The tag register value.
191	* @param pVCpu The virtual CPU handle.
192	* @param iReg The register number (0..7).
193	*/
194	DECLINLINE(uint16_t) cpumR3RegCalcFpuTagFromFxSave(PCX86FXSTATE pFpu, unsigned iReg)
195	{
196	/*
197	* See table 11-1 in the AMD docs.
198	*/
199	if (!(pFpu->FTW & RT_BIT_32(iReg)))
200	return 3; /* b11 - empty */
201
202	uint16_t const uExp = pFpu->aRegs[iReg].au16[4];
203	if (uExp == 0)
204	{
205	if (pFpu->aRegs[iReg].au64[0] == 0) /* J & M == 0 */
206	return 1; /* b01 - zero */
207	return 2; /* b10 - special */
208	}
209
210	if (uExp == UINT16_C(0xffff))
211	return 2; /* b10 - special */
212
213	if (!(pFpu->aRegs[iReg].au64[0] >> 63)) /* J == 0 */
214	return 2; /* b10 - special */
215
216	return 0; /* b00 - valid (normal) */
217	}
218
219
220	/**
221	* @interface_method_impl{DBGFREGDESC, pfnGet}
222	*/
223	static DECLCALLBACK(int) cpumR3RegGet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
224	{
225	PVMCPU pVCpu = (PVMCPU)pvUser;
226	PCX86FXSTATE pFpu = (PCX86FXSTATE)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
227
228	VMCPU_ASSERT_EMT(pVCpu);
229	Assert(pDesc->enmType == DBGFREGVALTYPE_U16);
230
231	if (cpumR3RegIsFxSaveFormat(pVCpu))
232	pValue->u16 = cpumR3RegCalcFpuTagFromFxSave(pFpu, 0)
233	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 1) << 2)
234	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 2) << 4)
235	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 3) << 6)
236	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 4) << 8)
237	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 5) << 10)
238	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 6) << 12)
239	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 7) << 14);
240	else
241	{
242	PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)pFpu;
243	pValue->u16 = pOldFpu->FTW;
244	}
245	return VINF_SUCCESS;
246	}
247
248
249	/**
250	* @interface_method_impl{DBGFREGDESC, pfnGet}
251	*/
252	static DECLCALLBACK(int) cpumR3RegSet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
253	{
254	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
255	return VERR_DBGF_READ_ONLY_REGISTER;
256	}
257
258
259
260	/*
261	*
262	* Guest register access functions.
263	*
264	*/
265
266	/**
267	* @interface_method_impl{DBGFREGDESC, pfnGet}
268	*/
269	static DECLCALLBACK(int) cpumR3RegGstGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
270	{
271	PVMCPU pVCpu = (PVMCPU)pvUser;
272	VMCPU_ASSERT_EMT(pVCpu);
273
274	uint64_t u64Value;
275	int rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64Value);
276	AssertRCReturn(rc, rc);
277	switch (pDesc->enmType)
278	{
279	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
280	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
281	default:
282	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
283	}
284	return VINF_SUCCESS;
285	}
286
287
288	/**
289	* @interface_method_impl{DBGFREGDESC, pfnGet}
290	*/
291	static DECLCALLBACK(int) cpumR3RegGstSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
292	{
293	int rc;
294	PVMCPU pVCpu = (PVMCPU)pvUser;
295
296	VMCPU_ASSERT_EMT(pVCpu);
297
298	/*
299	* Calculate the new value.
300	*/
301	uint64_t u64Value;
302	uint64_t fMask;
303	uint64_t fMaskMax;
304	switch (pDesc->enmType)
305	{
306	case DBGFREGVALTYPE_U64:
307	u64Value = pValue->u64;
308	fMask = pfMask->u64;
309	fMaskMax = UINT64_MAX;
310	break;
311	case DBGFREGVALTYPE_U32:
312	u64Value = pValue->u32;
313	fMask = pfMask->u32;
314	fMaskMax = UINT32_MAX;
315	break;
316	default: AssertFailedReturn(VERR_INTERNAL_ERROR_4);
317	}
318	if (fMask != fMaskMax)
319	{
320	uint64_t u64FullValue;
321	rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64FullValue);
322	if (RT_FAILURE(rc))
323	return rc;
324	u64Value = (u64FullValue & ~fMask)
325	\| (u64Value & fMask);
326	}
327
328	/*
329	* Perform the assignment.
330	*/
331	switch (pDesc->offRegister)
332	{
333	case 0: rc = CPUMSetGuestCR0(pVCpu, u64Value); break;
334	case 2: rc = CPUMSetGuestCR2(pVCpu, u64Value); break;
335	case 3: rc = CPUMSetGuestCR3(pVCpu, u64Value); break;
336	case 4: rc = CPUMSetGuestCR4(pVCpu, u64Value); break;
337	case 8: rc = PDMApicSetTPR(pVCpu, (uint8_t)(u64Value << 4)); break;
338	default:
339	AssertFailedReturn(VERR_INTERNAL_ERROR_2);
340	}
341	return rc;
342	}
343
344
345	/**
346	* @interface_method_impl{DBGFREGDESC, pfnGet}
347	*/
348	static DECLCALLBACK(int) cpumR3RegGstGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
349	{
350	PVMCPU pVCpu = (PVMCPU)pvUser;
351	VMCPU_ASSERT_EMT(pVCpu);
352
353	uint64_t u64Value;
354	int rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64Value);
355	AssertRCReturn(rc, rc);
356	switch (pDesc->enmType)
357	{
358	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
359	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
360	default:
361	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
362	}
363	return VINF_SUCCESS;
364	}
365
366
367	/**
368	* @interface_method_impl{DBGFREGDESC, pfnGet}
369	*/
370	static DECLCALLBACK(int) cpumR3RegGstSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
371	{
372	int rc;
373	PVMCPU pVCpu = (PVMCPU)pvUser;
374
375	VMCPU_ASSERT_EMT(pVCpu);
376
377	/*
378	* Calculate the new value.
379	*/
380	uint64_t u64Value;
381	uint64_t fMask;
382	uint64_t fMaskMax;
383	switch (pDesc->enmType)
384	{
385	case DBGFREGVALTYPE_U64:
386	u64Value = pValue->u64;
387	fMask = pfMask->u64;
388	fMaskMax = UINT64_MAX;
389	break;
390	case DBGFREGVALTYPE_U32:
391	u64Value = pValue->u32;
392	fMask = pfMask->u32;
393	fMaskMax = UINT32_MAX;
394	break;
395	default: AssertFailedReturn(VERR_INTERNAL_ERROR_4);
396	}
397	if (fMask != fMaskMax)
398	{
399	uint64_t u64FullValue;
400	rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64FullValue);
401	if (RT_FAILURE(rc))
402	return rc;
403	u64Value = (u64FullValue & ~fMask)
404	\| (u64Value & fMask);
405	}
406
407	/*
408	* Perform the assignment.
409	*/
410	return CPUMSetGuestDRx(pVCpu, pDesc->offRegister, u64Value);
411	}
412
413
414	/**
415	* @interface_method_impl{DBGFREGDESC, pfnGet}
416	*/
417	static DECLCALLBACK(int) cpumR3RegGstGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
418	{
419	PVMCPU pVCpu = (PVMCPU)pvUser;
420	VMCPU_ASSERT_EMT(pVCpu);
421
422	uint64_t u64Value;
423	int rc = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64Value);
424	if (RT_SUCCESS(rc))
425	{
426	switch (pDesc->enmType)
427	{
428	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
429	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
430	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
431	default:
432	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
433	}
434	}
435	/** @todo what to do about errors? */
436	return rc;
437	}
438
439
440	/**
441	* @interface_method_impl{DBGFREGDESC, pfnGet}
442	*/
443	static DECLCALLBACK(int) cpumR3RegGstSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
444	{
445	int rc;
446	PVMCPU pVCpu = (PVMCPU)pvUser;
447
448	VMCPU_ASSERT_EMT(pVCpu);
449
450	/*
451	* Calculate the new value.
452	*/
453	uint64_t u64Value;
454	uint64_t fMask;
455	uint64_t fMaskMax;
456	switch (pDesc->enmType)
457	{
458	case DBGFREGVALTYPE_U64:
459	u64Value = pValue->u64;
460	fMask = pfMask->u64;
461	fMaskMax = UINT64_MAX;
462	break;
463	case DBGFREGVALTYPE_U32:
464	u64Value = pValue->u32;
465	fMask = pfMask->u32;
466	fMaskMax = UINT32_MAX;
467	break;
468	case DBGFREGVALTYPE_U16:
469	u64Value = pValue->u16;
470	fMask = pfMask->u16;
471	fMaskMax = UINT16_MAX;
472	break;
473	default: AssertFailedReturn(VERR_INTERNAL_ERROR_4);
474	}
475	if (fMask != fMaskMax)
476	{
477	uint64_t u64FullValue;
478	rc = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64FullValue);
479	if (RT_FAILURE(rc))
480	return rc;
481	u64Value = (u64FullValue & ~fMask)
482	\| (u64Value & fMask);
483	}
484
485	/*
486	* Perform the assignment.
487	*/
488	return CPUMSetGuestMsr(pVCpu, pDesc->offRegister, u64Value);
489	}
490
491
492	/**
493	* @interface_method_impl{DBGFREGDESC, pfnGet}
494	*/
495	static DECLCALLBACK(int) cpumR3RegGstGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
496	{
497	PVMCPU pVCpu = (PVMCPU)pvUser;
498	VMCPU_ASSERT_EMT(pVCpu);
499	Assert(pDesc->enmType == DBGFREGVALTYPE_R80);
500
501	if (cpumR3RegIsFxSaveFormat(pVCpu))
502	{
503	unsigned iReg = (pVCpu->cpum.s.Guest.fpu.FSW >> 11) & 7;
504	iReg += pDesc->offRegister;
505	iReg &= 7;
506	pValue->r80 = pVCpu->cpum.s.Guest.fpu.aRegs[iReg].r80;
507	}
508	else
509	{
510	PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.fpu;
511
512	unsigned iReg = (pOldFpu->FSW >> 11) & 7;
513	iReg += pDesc->offRegister;
514	iReg &= 7;
515
516	pValue->r80 = pOldFpu->regs[iReg].r80;
517	}
518
519	return VINF_SUCCESS;
520	}
521
522
523	/**
524	* @interface_method_impl{DBGFREGDESC, pfnGet}
525	*/
526	static DECLCALLBACK(int) cpumR3RegGstSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
527	{
528	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
529	return VERR_NOT_IMPLEMENTED;
530	}
531
532
533
534	/*
535	*
536	* Hypervisor register access functions.
537	*
538	*/
539
540	/**
541	* @interface_method_impl{DBGFREGDESC, pfnGet}
542	*/
543	static DECLCALLBACK(int) cpumR3RegHyperGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
544	{
545	PVMCPU pVCpu = (PVMCPU)pvUser;
546	VMCPU_ASSERT_EMT(pVCpu);
547
548	uint64_t u64Value;
549	switch (pDesc->offRegister)
550	{
551	case 0: u64Value = UINT64_MAX; break;
552	case 2: u64Value = UINT64_MAX; break;
553	case 3: u64Value = CPUMGetHyperCR3(pVCpu); break;
554	case 4: u64Value = UINT64_MAX; break;
555	case 8: u64Value = UINT64_MAX; break;
556	default:
557	AssertFailedReturn(VERR_INTERNAL_ERROR_3);
558	}
559	switch (pDesc->enmType)
560	{
561	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
562	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
563	default:
564	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
565	}
566	return VINF_SUCCESS;
567	}
568
569
570	/**
571	* @interface_method_impl{DBGFREGDESC, pfnGet}
572	*/
573	static DECLCALLBACK(int) cpumR3RegHyperSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
574	{
575	/* Not settable, prevents killing your host. */
576	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
577	return VERR_ACCESS_DENIED;
578	}
579
580
581	/**
582	* @interface_method_impl{DBGFREGDESC, pfnGet}
583	*/
584	static DECLCALLBACK(int) cpumR3RegHyperGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
585	{
586	PVMCPU pVCpu = (PVMCPU)pvUser;
587	VMCPU_ASSERT_EMT(pVCpu);
588
589	uint64_t u64Value;
590	switch (pDesc->offRegister)
591	{
592	case 0: u64Value = CPUMGetHyperDR0(pVCpu); break;
593	case 1: u64Value = CPUMGetHyperDR1(pVCpu); break;
594	case 2: u64Value = CPUMGetHyperDR2(pVCpu); break;
595	case 3: u64Value = CPUMGetHyperDR3(pVCpu); break;
596	case 6: u64Value = CPUMGetHyperDR6(pVCpu); break;
597	case 7: u64Value = CPUMGetHyperDR7(pVCpu); break;
598	default:
599	AssertFailedReturn(VERR_INTERNAL_ERROR_3);
600	}
601	switch (pDesc->enmType)
602	{
603	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
604	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
605	default:
606	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
607	}
608	return VINF_SUCCESS;
609	}
610
611
612	/**
613	* @interface_method_impl{DBGFREGDESC, pfnGet}
614	*/
615	static DECLCALLBACK(int) cpumR3RegHyperSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
616	{
617	/* Not settable, prevents killing your host. */
618	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
619	return VERR_ACCESS_DENIED;
620	}
621
622
623	/**
624	* @interface_method_impl{DBGFREGDESC, pfnGet}
625	*/
626	static DECLCALLBACK(int) cpumR3RegHyperGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
627	{
628	NOREF(pvUser);
629
630	/* Not availble at present, return all FFs to keep things quiet */
631	uint64_t u64Value = UINT64_MAX;
632	switch (pDesc->enmType)
633	{
634	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
635	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
636	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
637	default:
638	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
639	}
640	return VINF_SUCCESS;
641	}
642
643
644	/**
645	* @interface_method_impl{DBGFREGDESC, pfnGet}
646	*/
647	static DECLCALLBACK(int) cpumR3RegHyperSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
648	{
649	/* Not settable, return failure. */
650	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
651	return VERR_ACCESS_DENIED;
652	}
653
654
655	/**
656	* @interface_method_impl{DBGFREGDESC, pfnGet}
657	*/
658	static DECLCALLBACK(int) cpumR3RegHyperGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
659	{
660	PVMCPU pVCpu = (PVMCPU)pvUser;
661
662	VMCPU_ASSERT_EMT(pVCpu);
663	Assert(pDesc->enmType == DBGFREGVALTYPE_R80);
664
665	if (cpumR3RegIsFxSaveFormat(pVCpu))
666	{
667	unsigned iReg = (pVCpu->cpum.s.Guest.fpu.FSW >> 11) & 7;
668	iReg += pDesc->offRegister;
669	iReg &= 7;
670	pValue->r80 = pVCpu->cpum.s.Guest.fpu.aRegs[iReg].r80;
671	}
672	else
673	{
674	PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.fpu;
675
676	unsigned iReg = (pOldFpu->FSW >> 11) & 7;
677	iReg += pDesc->offRegister;
678	iReg &= 7;
679
680	pValue->r80 = pOldFpu->regs[iReg].r80;
681	}
682
683	return VINF_SUCCESS;
684	}
685
686
687	/**
688	* @interface_method_impl{DBGFREGDESC, pfnGet}
689	*/
690	static DECLCALLBACK(int) cpumR3RegHyperSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
691	{
692	/* There isn't a FPU context for the hypervisor yet, so no point in trying to set stuff. */
693	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
694	return VERR_ACCESS_DENIED;
695	}
696
697
698
699	/*
700	* Set up aliases.
701	*/
702	#define CPUMREGALIAS_STD(Name, psz32, psz16, psz8) \
703	static DBGFREGALIAS const g_aCpumRegAliases_##Name[] = \
704	{ \
705	{ psz32, DBGFREGVALTYPE_U32 }, \
706	{ psz16, DBGFREGVALTYPE_U16 }, \
707	{ psz8, DBGFREGVALTYPE_U8 }, \
708	{ NULL, DBGFREGVALTYPE_INVALID } \
709	}
710	CPUMREGALIAS_STD(rax, "eax", "ax", "al");
711	CPUMREGALIAS_STD(rcx, "ecx", "cx", "cl");
712	CPUMREGALIAS_STD(rdx, "edx", "dx", "dl");
713	CPUMREGALIAS_STD(rbx, "ebx", "bx", "bl");
714	CPUMREGALIAS_STD(rsp, "esp", "sp", NULL);
715	CPUMREGALIAS_STD(rbp, "ebp", "bp", NULL);
716	CPUMREGALIAS_STD(rsi, "esi", "si", "sil");
717	CPUMREGALIAS_STD(rdi, "edi", "di", "dil");
718	CPUMREGALIAS_STD(r8, "r8d", "r8w", "r8b");
719	CPUMREGALIAS_STD(r9, "r9d", "r9w", "r9b");
720	CPUMREGALIAS_STD(r10, "r10d", "r10w", "r10b");
721	CPUMREGALIAS_STD(r11, "r11d", "r11w", "r11b");
722	CPUMREGALIAS_STD(r12, "r12d", "r12w", "r12b");
723	CPUMREGALIAS_STD(r13, "r13d", "r13w", "r13b");
724	CPUMREGALIAS_STD(r14, "r14d", "r14w", "r14b");
725	CPUMREGALIAS_STD(r15, "r15d", "r15w", "r15b");
726	CPUMREGALIAS_STD(rip, "eip", "ip", NULL);
727	CPUMREGALIAS_STD(rflags, "eflags", "flags", NULL);
728	#undef CPUMREGALIAS_STD
729
730	static DBGFREGALIAS const g_aCpumRegAliases_fpuip[] =
731	{
732	{ "fpuip16", DBGFREGVALTYPE_U16 },
733	{ NULL, DBGFREGVALTYPE_INVALID }
734	};
735
736	static DBGFREGALIAS const g_aCpumRegAliases_fpudp[] =
737	{
738	{ "fpudp16", DBGFREGVALTYPE_U16 },
739	{ NULL, DBGFREGVALTYPE_INVALID }
740	};
741
742	static DBGFREGALIAS const g_aCpumRegAliases_cr0[] =
743	{
744	{ "msw", DBGFREGVALTYPE_U16 },
745	{ NULL, DBGFREGVALTYPE_INVALID }
746	};
747
748	/*
749	* Sub fields.
750	*/
751	/** Sub-fields for the (hidden) segment attribute register. */
752	static DBGFREGSUBFIELD const g_aCpumRegFields_seg[] =
753	{
754	DBGFREGSUBFIELD_RW("type", 0, 4, 0),
755	DBGFREGSUBFIELD_RW("s", 4, 1, 0),
756	DBGFREGSUBFIELD_RW("dpl", 5, 2, 0),
757	DBGFREGSUBFIELD_RW("p", 7, 1, 0),
758	DBGFREGSUBFIELD_RW("avl", 12, 1, 0),
759	DBGFREGSUBFIELD_RW("l", 13, 1, 0),
760	DBGFREGSUBFIELD_RW("d", 14, 1, 0),
761	DBGFREGSUBFIELD_RW("g", 15, 1, 0),
762	DBGFREGSUBFIELD_TERMINATOR()
763	};
764
765	/** Sub-fields for the flags register. */
766	static DBGFREGSUBFIELD const g_aCpumRegFields_rflags[] =
767	{
768	DBGFREGSUBFIELD_RW("cf", 0, 1, 0),
769	DBGFREGSUBFIELD_RW("pf", 2, 1, 0),
770	DBGFREGSUBFIELD_RW("af", 4, 1, 0),
771	DBGFREGSUBFIELD_RW("zf", 6, 1, 0),
772	DBGFREGSUBFIELD_RW("sf", 7, 1, 0),
773	DBGFREGSUBFIELD_RW("tf", 8, 1, 0),
774	DBGFREGSUBFIELD_RW("if", 9, 1, 0),
775	DBGFREGSUBFIELD_RW("df", 10, 1, 0),
776	DBGFREGSUBFIELD_RW("of", 11, 1, 0),
777	DBGFREGSUBFIELD_RW("iopl", 12, 2, 0),
778	DBGFREGSUBFIELD_RW("nt", 14, 1, 0),
779	DBGFREGSUBFIELD_RW("rf", 16, 1, 0),
780	DBGFREGSUBFIELD_RW("vm", 17, 1, 0),
781	DBGFREGSUBFIELD_RW("ac", 18, 1, 0),
782	DBGFREGSUBFIELD_RW("vif", 19, 1, 0),
783	DBGFREGSUBFIELD_RW("vip", 20, 1, 0),
784	DBGFREGSUBFIELD_RW("id", 21, 1, 0),
785	DBGFREGSUBFIELD_TERMINATOR()
786	};
787
788	/** Sub-fields for the FPU control word register. */
789	static DBGFREGSUBFIELD const g_aCpumRegFields_fcw[] =
790	{
791	DBGFREGSUBFIELD_RW("im", 1, 1, 0),
792	DBGFREGSUBFIELD_RW("dm", 2, 1, 0),
793	DBGFREGSUBFIELD_RW("zm", 3, 1, 0),
794	DBGFREGSUBFIELD_RW("om", 4, 1, 0),
795	DBGFREGSUBFIELD_RW("um", 5, 1, 0),
796	DBGFREGSUBFIELD_RW("pm", 6, 1, 0),
797	DBGFREGSUBFIELD_RW("pc", 8, 2, 0),
798	DBGFREGSUBFIELD_RW("rc", 10, 2, 0),
799	DBGFREGSUBFIELD_RW("x", 12, 1, 0),
800	DBGFREGSUBFIELD_TERMINATOR()
801	};
802
803	/** Sub-fields for the FPU status word register. */
804	static DBGFREGSUBFIELD const g_aCpumRegFields_fsw[] =
805	{
806	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
807	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
808	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
809	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
810	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
811	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
812	DBGFREGSUBFIELD_RW("se", 6, 1, 0),
813	DBGFREGSUBFIELD_RW("es", 7, 1, 0),
814	DBGFREGSUBFIELD_RW("c0", 8, 1, 0),
815	DBGFREGSUBFIELD_RW("c1", 9, 1, 0),
816	DBGFREGSUBFIELD_RW("c2", 10, 1, 0),
817	DBGFREGSUBFIELD_RW("top", 11, 3, 0),
818	DBGFREGSUBFIELD_RW("c3", 14, 1, 0),
819	DBGFREGSUBFIELD_RW("b", 15, 1, 0),
820	DBGFREGSUBFIELD_TERMINATOR()
821	};
822
823	/** Sub-fields for the FPU tag word register. */
824	static DBGFREGSUBFIELD const g_aCpumRegFields_ftw[] =
825	{
826	DBGFREGSUBFIELD_RW("tag0", 0, 2, 0),
827	DBGFREGSUBFIELD_RW("tag1", 2, 2, 0),
828	DBGFREGSUBFIELD_RW("tag2", 4, 2, 0),
829	DBGFREGSUBFIELD_RW("tag3", 6, 2, 0),
830	DBGFREGSUBFIELD_RW("tag4", 8, 2, 0),
831	DBGFREGSUBFIELD_RW("tag5", 10, 2, 0),
832	DBGFREGSUBFIELD_RW("tag6", 12, 2, 0),
833	DBGFREGSUBFIELD_RW("tag7", 14, 2, 0),
834	DBGFREGSUBFIELD_TERMINATOR()
835	};
836
837	/** Sub-fields for the Multimedia Extensions Control and Status Register. */
838	static DBGFREGSUBFIELD const g_aCpumRegFields_mxcsr[] =
839	{
840	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
841	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
842	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
843	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
844	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
845	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
846	DBGFREGSUBFIELD_RW("daz", 6, 1, 0),
847	DBGFREGSUBFIELD_RW("im", 7, 1, 0),
848	DBGFREGSUBFIELD_RW("dm", 8, 1, 0),
849	DBGFREGSUBFIELD_RW("zm", 9, 1, 0),
850	DBGFREGSUBFIELD_RW("om", 10, 1, 0),
851	DBGFREGSUBFIELD_RW("um", 11, 1, 0),
852	DBGFREGSUBFIELD_RW("pm", 12, 1, 0),
853	DBGFREGSUBFIELD_RW("rc", 13, 2, 0),
854	DBGFREGSUBFIELD_RW("fz", 14, 1, 0),
855	DBGFREGSUBFIELD_TERMINATOR()
856	};
857
858	/** Sub-fields for the FPU tag word register. */
859	static DBGFREGSUBFIELD const g_aCpumRegFields_stN[] =
860	{
861	DBGFREGSUBFIELD_RW("man", 0, 64, 0),
862	DBGFREGSUBFIELD_RW("exp", 64, 15, 0),
863	DBGFREGSUBFIELD_RW("sig", 79, 1, 0),
864	DBGFREGSUBFIELD_TERMINATOR()
865	};
866
867	/** Sub-fields for the MMX registers. */
868	static DBGFREGSUBFIELD const g_aCpumRegFields_mmN[] =
869	{
870	DBGFREGSUBFIELD_RW("dw0", 0, 32, 0),
871	DBGFREGSUBFIELD_RW("dw1", 32, 32, 0),
872	DBGFREGSUBFIELD_RW("w0", 0, 16, 0),
873	DBGFREGSUBFIELD_RW("w1", 16, 16, 0),
874	DBGFREGSUBFIELD_RW("w2", 32, 16, 0),
875	DBGFREGSUBFIELD_RW("w3", 48, 16, 0),
876	DBGFREGSUBFIELD_RW("b0", 0, 8, 0),
877	DBGFREGSUBFIELD_RW("b1", 8, 8, 0),
878	DBGFREGSUBFIELD_RW("b2", 16, 8, 0),
879	DBGFREGSUBFIELD_RW("b3", 24, 8, 0),
880	DBGFREGSUBFIELD_RW("b4", 32, 8, 0),
881	DBGFREGSUBFIELD_RW("b5", 40, 8, 0),
882	DBGFREGSUBFIELD_RW("b6", 48, 8, 0),
883	DBGFREGSUBFIELD_RW("b7", 56, 8, 0),
884	DBGFREGSUBFIELD_TERMINATOR()
885	};
886
887	/** Sub-fields for the XMM registers. */
888	static DBGFREGSUBFIELD const g_aCpumRegFields_xmmN[] =
889	{
890	DBGFREGSUBFIELD_RW("r0", 0, 32, 0),
891	DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0),
892	DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0),
893	DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0),
894	DBGFREGSUBFIELD_RW("r1", 32, 32, 0),
895	DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0),
896	DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0),
897	DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0),
898	DBGFREGSUBFIELD_RW("r2", 64, 32, 0),
899	DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0),
900	DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0),
901	DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0),
902	DBGFREGSUBFIELD_RW("r3", 96, 32, 0),
903	DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0),
904	DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0),
905	DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0),
906	DBGFREGSUBFIELD_TERMINATOR()
907	};
908
909	/** Sub-fields for the CR0 register. */
910	static DBGFREGSUBFIELD const g_aCpumRegFields_cr0[] =
911	{
912	/** @todo */
913	DBGFREGSUBFIELD_TERMINATOR()
914	};
915
916	/** Sub-fields for the CR3 register. */
917	static DBGFREGSUBFIELD const g_aCpumRegFields_cr3[] =
918	{
919	/** @todo */
920	DBGFREGSUBFIELD_TERMINATOR()
921	};
922
923	/** Sub-fields for the CR4 register. */
924	static DBGFREGSUBFIELD const g_aCpumRegFields_cr4[] =
925	{
926	/** @todo */
927	DBGFREGSUBFIELD_TERMINATOR()
928	};
929
930	/** Sub-fields for the DR6 register. */
931	static DBGFREGSUBFIELD const g_aCpumRegFields_dr6[] =
932	{
933	/** @todo */
934	DBGFREGSUBFIELD_TERMINATOR()
935	};
936
937	/** Sub-fields for the DR7 register. */
938	static DBGFREGSUBFIELD const g_aCpumRegFields_dr7[] =
939	{
940	/** @todo */
941	DBGFREGSUBFIELD_TERMINATOR()
942	};
943
944	/** Sub-fields for the CR_PAT MSR. */
945	static DBGFREGSUBFIELD const g_aCpumRegFields_apic_base[] =
946	{
947	DBGFREGSUBFIELD_RW("bsp", 8, 1, 0),
948	DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
949	DBGFREGSUBFIELD_RW("base", 12, 20, 12),
950	DBGFREGSUBFIELD_TERMINATOR()
951	};
952
953	/** Sub-fields for the CR_PAT MSR. */
954	static DBGFREGSUBFIELD const g_aCpumRegFields_cr_pat[] =
955	{
956	/** @todo */
957	DBGFREGSUBFIELD_TERMINATOR()
958	};
959
960	/** Sub-fields for the PERF_STATUS MSR. */
961	static DBGFREGSUBFIELD const g_aCpumRegFields_perf_status[] =
962	{
963	/** @todo */
964	DBGFREGSUBFIELD_TERMINATOR()
965	};
966
967	/** Sub-fields for the EFER MSR. */
968	static DBGFREGSUBFIELD const g_aCpumRegFields_efer[] =
969	{
970	/** @todo */
971	DBGFREGSUBFIELD_TERMINATOR()
972	};
973
974	/** Sub-fields for the STAR MSR. */
975	static DBGFREGSUBFIELD const g_aCpumRegFields_star[] =
976	{
977	/** @todo */
978	DBGFREGSUBFIELD_TERMINATOR()
979	};
980
981	/** Sub-fields for the CSTAR MSR. */
982	static DBGFREGSUBFIELD const g_aCpumRegFields_cstar[] =
983	{
984	/** @todo */
985	DBGFREGSUBFIELD_TERMINATOR()
986	};
987
988	/** Sub-fields for the LSTAR MSR. */
989	static DBGFREGSUBFIELD const g_aCpumRegFields_lstar[] =
990	{
991	/** @todo */
992	DBGFREGSUBFIELD_TERMINATOR()
993	};
994
995	/** Sub-fields for the SF_MASK MSR. */
996	static DBGFREGSUBFIELD const g_aCpumRegFields_sf_mask[] =
997	{
998	/** @todo */
999	DBGFREGSUBFIELD_TERMINATOR()
1000	};
1001
1002
1003	/** @name Macros for producing register descriptor table entries.
1004	* @{ */
1005	#define CPU_REG_EX_AS(a_szName, a_RegSuff, a_TypeSuff, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1006	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1007
1008	#define CPU_REG_REG(UName, LName) \
1009	CPU_REG_RW_AS(#LName, UName, U64, LName, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_##LName, NULL)
1010
1011	#define CPU_REG_SEG(UName, LName) \
1012	CPU_REG_RW_AS(#LName, UName, U16, LName, cpumR3RegGet_Generic, cpumR3RegSet_seg, NULL, NULL ), \
1013	CPU_REG_RW_AS(#LName "_attr", UName##_ATTR, U32, LName##Hid.Attr.u, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_seg), \
1014	CPU_REG_RW_AS(#LName "_base", UName##_BASE, U64, LName##Hid.u64Base, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), \
1015	CPU_REG_RW_AS(#LName "_lim", UName##_LIMIT, U32, LName##Hid.u32Limit, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL )
1016
1017	#define CPU_REG_MM(n) \
1018	CPU_REG_RW_AS("mm" #n, MM##n, U64, fpu.aRegs[n].mmx, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mmN)
1019
1020	#define CPU_REG_XMM(n) \
1021	CPU_REG_RW_AS("xmm" #n, XMM##n, U128, fpu.aXMM[n].xmm, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_xmmN)
1022	/** @} */
1023
1024
1025	/**
1026	* The guest register descriptors.
1027	*/
1028	static DBGFREGDESC const g_aCpumRegGstDescs[] =
1029	{
1030	#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1031	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1032	#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1033	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1034	#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
1035	CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegGstGet_msr, cpumR3RegGstSet_msr, NULL, a_paSubFields)
1036	#define CPU_REG_ST(n) \
1037	CPU_REG_EX_AS("st" #n, ST##n, R80, n, cpumR3RegGstGet_stN, cpumR3RegGstSet_stN, NULL, g_aCpumRegFields_stN)
1038
1039	CPU_REG_REG(RAX, rax),
1040	CPU_REG_REG(RCX, rcx),
1041	CPU_REG_REG(RDX, rdx),
1042	CPU_REG_REG(RBX, rbx),
1043	CPU_REG_REG(RSP, rsp),
1044	CPU_REG_REG(RBP, rbp),
1045	CPU_REG_REG(RSI, rsi),
1046	CPU_REG_REG(RDI, rdi),
1047	CPU_REG_REG(R8, r8),
1048	CPU_REG_REG(R9, r9),
1049	CPU_REG_REG(R10, r10),
1050	CPU_REG_REG(R11, r11),
1051	CPU_REG_REG(R12, r12),
1052	CPU_REG_REG(R13, r13),
1053	CPU_REG_REG(R14, r14),
1054	CPU_REG_REG(R15, r15),
1055	CPU_REG_SEG(CS, cs),
1056	CPU_REG_SEG(DS, ds),
1057	CPU_REG_SEG(ES, es),
1058	CPU_REG_SEG(FS, fs),
1059	CPU_REG_SEG(GS, gs),
1060	CPU_REG_SEG(SS, ss),
1061	CPU_REG_REG(RIP, rip),
1062	CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
1063	CPU_REG_RW_AS("fcw", FCW, U16, fpu.FCW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fcw ),
1064	CPU_REG_RW_AS("fsw", FSW, U16, fpu.FSW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fsw ),
1065	CPU_REG_RO_AS("ftw", FTW, U16, fpu, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ),
1066	CPU_REG_RW_AS("fop", FOP, U16, fpu.FOP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1067	CPU_REG_RW_AS("fpuip", FPUIP, U32, fpu.FPUIP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpuip, NULL ),
1068	CPU_REG_RW_AS("fpucs", FPUCS, U16, fpu.CS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1069	CPU_REG_RW_AS("fpudp", FPUDP, U32, fpu.FPUDP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpudp, NULL ),
1070	CPU_REG_RW_AS("fpuds", FPUDS, U16, fpu.DS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1071	CPU_REG_RW_AS("mxcsr", MXCSR, U32, fpu.MXCSR, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
1072	CPU_REG_RW_AS("mxcsr_mask", MXCSR_MASK, U32, fpu.MXCSR_MASK, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
1073	CPU_REG_ST(0),
1074	CPU_REG_ST(1),
1075	CPU_REG_ST(2),
1076	CPU_REG_ST(3),
1077	CPU_REG_ST(4),
1078	CPU_REG_ST(5),
1079	CPU_REG_ST(6),
1080	CPU_REG_ST(7),
1081	CPU_REG_MM(0),
1082	CPU_REG_MM(1),
1083	CPU_REG_MM(2),
1084	CPU_REG_MM(3),
1085	CPU_REG_MM(4),
1086	CPU_REG_MM(5),
1087	CPU_REG_MM(6),
1088	CPU_REG_MM(7),
1089	CPU_REG_XMM(0),
1090	CPU_REG_XMM(1),
1091	CPU_REG_XMM(2),
1092	CPU_REG_XMM(3),
1093	CPU_REG_XMM(4),
1094	CPU_REG_XMM(5),
1095	CPU_REG_XMM(6),
1096	CPU_REG_XMM(7),
1097	CPU_REG_XMM(8),
1098	CPU_REG_XMM(9),
1099	CPU_REG_XMM(10),
1100	CPU_REG_XMM(11),
1101	CPU_REG_XMM(12),
1102	CPU_REG_XMM(13),
1103	CPU_REG_XMM(14),
1104	CPU_REG_XMM(15),
1105	CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1106	CPU_REG_RW_AS("gdtr_lim", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1107	CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1108	CPU_REG_RW_AS("idtr_lim", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1109	CPU_REG_SEG(LDTR, ldtr),
1110	CPU_REG_SEG(TR, tr),
1111	CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
1112	CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1113	CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr3 ),
1114	CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr4 ),
1115	CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1116	CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1117	CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1118	CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1119	CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1120	CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr6 ),
1121	CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr7 ),
1122	CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
1123	CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
1124	CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
1125	CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
1126	CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ),
1127	CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ),
1128	CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ),
1129	CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
1130	CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
1131	CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
1132	CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
1133	CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
1134	CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
1135	CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
1136	CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
1137	CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
1138	CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Guest.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1139	CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Guest.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1140	CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Guest.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1141	CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Guest.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1142	CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
1143	CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
1144	DBGFREGDESC_TERMINATOR()
1145
1146	#undef CPU_REG_RW_AS
1147	#undef CPU_REG_RO_AS
1148	#undef CPU_REG_MSR
1149	#undef CPU_REG_ST
1150	};
1151
1152
1153	/**
1154	* The hypervisor (raw-mode) register descriptors.
1155	*/
1156	static DBGFREGDESC const g_aCpumRegHyperDescs[] =
1157	{
1158	#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1159	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(CPUMCPU, Hyper.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1160	#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1161	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Hyper.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1162	#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
1163	CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegHyperGet_msr, cpumR3RegHyperSet_msr, NULL, a_paSubFields)
1164	#define CPU_REG_ST(n) \
1165	CPU_REG_EX_AS("st" #n, ST##n, R80, n, cpumR3RegHyperGet_stN, cpumR3RegHyperSet_stN, NULL, g_aCpumRegFields_stN)
1166
1167	CPU_REG_REG(RAX, rax),
1168	CPU_REG_REG(RCX, rcx),
1169	CPU_REG_REG(RDX, rdx),
1170	CPU_REG_REG(RBX, rbx),
1171	CPU_REG_REG(RSP, rsp),
1172	CPU_REG_REG(RBP, rbp),
1173	CPU_REG_REG(RSI, rsi),
1174	CPU_REG_REG(RDI, rdi),
1175	CPU_REG_REG(R8, r8),
1176	CPU_REG_REG(R9, r9),
1177	CPU_REG_REG(R10, r10),
1178	CPU_REG_REG(R11, r11),
1179	CPU_REG_REG(R12, r12),
1180	CPU_REG_REG(R13, r13),
1181	CPU_REG_REG(R14, r14),
1182	CPU_REG_REG(R15, r15),
1183	CPU_REG_SEG(CS, cs),
1184	CPU_REG_SEG(DS, ds),
1185	CPU_REG_SEG(ES, es),
1186	CPU_REG_SEG(FS, fs),
1187	CPU_REG_SEG(GS, gs),
1188	CPU_REG_SEG(SS, ss),
1189	CPU_REG_REG(RIP, rip),
1190	CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
1191	CPU_REG_RW_AS("fcw", FCW, U16, fpu.FCW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fcw ),
1192	CPU_REG_RW_AS("fsw", FSW, U16, fpu.FSW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fsw ),
1193	CPU_REG_RO_AS("ftw", FTW, U16, fpu, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ),
1194	CPU_REG_RW_AS("fop", FOP, U16, fpu.FOP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1195	CPU_REG_RW_AS("fpuip", FPUIP, U32, fpu.FPUIP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpuip, NULL ),
1196	CPU_REG_RW_AS("fpucs", FPUCS, U16, fpu.CS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1197	CPU_REG_RW_AS("fpudp", FPUDP, U32, fpu.FPUDP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpudp, NULL ),
1198	CPU_REG_RW_AS("fpuds", FPUDS, U16, fpu.DS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1199	CPU_REG_RW_AS("mxcsr", MXCSR, U32, fpu.MXCSR, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
1200	CPU_REG_RW_AS("mxcsr_mask", MXCSR_MASK, U32, fpu.MXCSR_MASK, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
1201	CPU_REG_ST(0),
1202	CPU_REG_ST(1),
1203	CPU_REG_ST(2),
1204	CPU_REG_ST(3),
1205	CPU_REG_ST(4),
1206	CPU_REG_ST(5),
1207	CPU_REG_ST(6),
1208	CPU_REG_ST(7),
1209	CPU_REG_MM(0),
1210	CPU_REG_MM(1),
1211	CPU_REG_MM(2),
1212	CPU_REG_MM(3),
1213	CPU_REG_MM(4),
1214	CPU_REG_MM(5),
1215	CPU_REG_MM(6),
1216	CPU_REG_MM(7),
1217	CPU_REG_XMM(0),
1218	CPU_REG_XMM(1),
1219	CPU_REG_XMM(2),
1220	CPU_REG_XMM(3),
1221	CPU_REG_XMM(4),
1222	CPU_REG_XMM(5),
1223	CPU_REG_XMM(6),
1224	CPU_REG_XMM(7),
1225	CPU_REG_XMM(8),
1226	CPU_REG_XMM(9),
1227	CPU_REG_XMM(10),
1228	CPU_REG_XMM(11),
1229	CPU_REG_XMM(12),
1230	CPU_REG_XMM(13),
1231	CPU_REG_XMM(14),
1232	CPU_REG_XMM(15),
1233	CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1234	CPU_REG_RW_AS("gdtr_lim", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1235	CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1236	CPU_REG_RW_AS("idtr_lim", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1237	CPU_REG_SEG(LDTR, ldtr),
1238	CPU_REG_SEG(TR, tr),
1239	CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
1240	CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, NULL ),
1241	CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, g_aCpumRegFields_cr3 ),
1242	CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, g_aCpumRegFields_cr4 ),
1243	CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, NULL ),
1244	CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1245	CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1246	CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1247	CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1248	CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr6 ),
1249	CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr7 ),
1250	CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
1251	CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
1252	CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
1253	CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
1254	CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ),
1255	CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ),
1256	CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ),
1257	CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
1258	CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
1259	CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
1260	CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
1261	CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
1262	CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
1263	CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
1264	CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
1265	CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
1266	CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1267	CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1268	CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1269	CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1270	CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
1271	CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
1272	DBGFREGDESC_TERMINATOR()
1273	#undef CPU_REG_RW_AS
1274	#undef CPU_REG_RO_AS
1275	#undef CPU_REG_MSR
1276	#undef CPU_REG_ST
1277	};
1278
1279
1280	/**
1281	* Initializes the debugger related sides of the CPUM component.
1282	*
1283	* Called by CPUMR3Init.
1284	*
1285	* @returns VBox status code.
1286	* @param pVM The VM handle.
1287	*/
1288	int cpumR3DbgInit(PVM pVM)
1289	{
1290	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1291	{
1292	int rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegGstDescs, true /fGuestRegs/);
1293	AssertLogRelRCReturn(rc, rc);
1294	rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegHyperDescs, false /fGuestRegs/);
1295	AssertLogRelRCReturn(rc, rc);
1296	}
1297
1298	return VINF_SUCCESS;
1299	}
1300

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp@ 39078

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