CPUMDbg.cpp@ 54338

Last change on this file since 54338 was 54047, checked in by vboxsync, 10 years ago
VMM/CPUMDbg: Fix assertion trip-up.
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1	/* $Id: CPUMDbg.cpp 54047 2015-01-30 13:34:23Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager, Debugger & Debugging APIs.
4	*/
5
6	/*
7	* Copyright (C) 2010-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DBGF
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/pdmapi.h>
26	#include "CPUMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/param.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/thread.h>
32	#include <iprt/uint128.h>
33
34
35	/**
36	* @interface_method_impl{DBGFREGDESC, pfnGet}
37	*/
38	static DECLCALLBACK(int) cpumR3RegGet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
39	{
40	PVMCPU pVCpu = (PVMCPU)pvUser;
41	void const pv = (uint8_t const )&pVCpu->cpum + pDesc->offRegister;
42
43	VMCPU_ASSERT_EMT(pVCpu);
44
45	switch (pDesc->enmType)
46	{
47	case DBGFREGVALTYPE_U8: pValue->u8 = (uint8_t const )pv; return VINF_SUCCESS;
48	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t const )pv; return VINF_SUCCESS;
49	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t const )pv; return VINF_SUCCESS;
50	case DBGFREGVALTYPE_U64: pValue->u64 = (uint64_t const )pv; return VINF_SUCCESS;
51	case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
52	default:
53	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
54	}
55	}
56
57
58	/**
59	* @interface_method_impl{DBGFREGDESC, pfnGet}
60	*/
61	static DECLCALLBACK(int) cpumR3RegSet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
62	{
63	PVMCPU pVCpu = (PVMCPU)pvUser;
64	void pv = (uint8_t )&pVCpu->cpum + pDesc->offRegister;
65
66	VMCPU_ASSERT_EMT(pVCpu);
67
68	switch (pDesc->enmType)
69	{
70	case DBGFREGVALTYPE_U8:
71	(uint8_t )pv &= ~pfMask->u8;
72	(uint8_t )pv \|= pValue->u8 & pfMask->u8;
73	return VINF_SUCCESS;
74
75	case DBGFREGVALTYPE_U16:
76	(uint16_t )pv &= ~pfMask->u16;
77	(uint16_t )pv \|= pValue->u16 & pfMask->u16;
78	return VINF_SUCCESS;
79
80	case DBGFREGVALTYPE_U32:
81	(uint32_t )pv &= ~pfMask->u32;
82	(uint32_t )pv \|= pValue->u32 & pfMask->u32;
83	return VINF_SUCCESS;
84
85	case DBGFREGVALTYPE_U64:
86	(uint64_t )pv &= ~pfMask->u64;
87	(uint64_t )pv \|= pValue->u64 & pfMask->u64;
88	return VINF_SUCCESS;
89
90	case DBGFREGVALTYPE_U128:
91	{
92	RTUINT128U Val;
93	RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
94	RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
95	return VINF_SUCCESS;
96	}
97
98	default:
99	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
100	}
101	}
102
103
104	/**
105	* @interface_method_impl{DBGFREGDESC, pfnGet}
106	*/
107	static DECLCALLBACK(int) cpumR3RegSet_seg(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
108	{
109	/** @todo perform a selector load, updating hidden selectors and stuff. */
110	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
111	return VERR_NOT_IMPLEMENTED;
112	}
113
114
115	/**
116	* @interface_method_impl{DBGFREGDESC, pfnGet}
117	*/
118	static DECLCALLBACK(int) cpumR3RegGet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
119	{
120	PVMCPU pVCpu = (PVMCPU)pvUser;
121	VBOXGDTR const pGdtr = (VBOXGDTR const )((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
122
123	VMCPU_ASSERT_EMT(pVCpu);
124	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
125
126	pValue->dtr.u32Limit = pGdtr->cbGdt;
127	pValue->dtr.u64Base = pGdtr->pGdt;
128	return VINF_SUCCESS;
129	}
130
131
132	/**
133	* @interface_method_impl{DBGFREGDESC, pfnGet}
134	*/
135	static DECLCALLBACK(int) cpumR3RegSet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
136	{
137	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
138	return VERR_NOT_IMPLEMENTED;
139	}
140
141
142	/**
143	* @interface_method_impl{DBGFREGDESC, pfnGet}
144	*/
145	static DECLCALLBACK(int) cpumR3RegGet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
146	{
147	PVMCPU pVCpu = (PVMCPU)pvUser;
148	VBOXIDTR const pIdtr = (VBOXIDTR const )((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
149
150	VMCPU_ASSERT_EMT(pVCpu);
151	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
152
153	pValue->dtr.u32Limit = pIdtr->cbIdt;
154	pValue->dtr.u64Base = pIdtr->pIdt;
155	return VINF_SUCCESS;
156	}
157
158
159	/**
160	* @interface_method_impl{DBGFREGDESC, pfnGet}
161	*/
162	static DECLCALLBACK(int) cpumR3RegSet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
163	{
164	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
165	return VERR_NOT_IMPLEMENTED;
166	}
167
168
169	/**
170	* Is the FPU state in FXSAVE format or not.
171	*
172	* @returns true if it is, false if it's in FNSAVE.
173	* @param pVCpu Pointer to the VMCPU.
174	*/
175	DECLINLINE(bool) cpumR3RegIsFxSaveFormat(PVMCPU pVCpu)
176	{
177	#ifdef RT_ARCH_AMD64
178	NOREF(pVCpu);
179	return true;
180	#else
181	return pVCpu->pVMR3->cpum.s.CPUFeatures.edx.u1FXSR;
182	#endif
183	}
184
185
186	/**
187	* Determins the tag register value for a CPU register when the FPU state
188	* format is FXSAVE.
189	*
190	* @returns The tag register value.
191	* @param pFpu Pointer to the guest FPU.
192	* @param iReg The register number (0..7).
193	*/
194	DECLINLINE(uint16_t) cpumR3RegCalcFpuTagFromFxSave(PCX86FXSTATE pFpu, unsigned iReg)
195	{
196	/*
197	* See table 11-1 in the AMD docs.
198	*/
199	if (!(pFpu->FTW & RT_BIT_32(iReg)))
200	return 3; /* b11 - empty */
201
202	uint16_t const uExp = pFpu->aRegs[iReg].au16[4];
203	if (uExp == 0)
204	{
205	if (pFpu->aRegs[iReg].au64[0] == 0) /* J & M == 0 */
206	return 1; /* b01 - zero */
207	return 2; /* b10 - special */
208	}
209
210	if (uExp == UINT16_C(0xffff))
211	return 2; /* b10 - special */
212
213	if (!(pFpu->aRegs[iReg].au64[0] >> 63)) /* J == 0 */
214	return 2; /* b10 - special */
215
216	return 0; /* b00 - valid (normal) */
217	}
218
219
220	/**
221	* @interface_method_impl{DBGFREGDESC, pfnGet}
222	*/
223	static DECLCALLBACK(int) cpumR3RegGet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
224	{
225	PVMCPU pVCpu = (PVMCPU)pvUser;
226	PCX86FXSTATE pFpu = (PCX86FXSTATE)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
227
228	VMCPU_ASSERT_EMT(pVCpu);
229	Assert(pDesc->enmType == DBGFREGVALTYPE_U16);
230
231	if (cpumR3RegIsFxSaveFormat(pVCpu))
232	pValue->u16 = cpumR3RegCalcFpuTagFromFxSave(pFpu, 0)
233	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 1) << 2)
234	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 2) << 4)
235	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 3) << 6)
236	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 4) << 8)
237	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 5) << 10)
238	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 6) << 12)
239	\| (cpumR3RegCalcFpuTagFromFxSave(pFpu, 7) << 14);
240	else
241	{
242	PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)pFpu;
243	pValue->u16 = pOldFpu->FTW;
244	}
245	return VINF_SUCCESS;
246	}
247
248
249	/**
250	* @interface_method_impl{DBGFREGDESC, pfnGet}
251	*/
252	static DECLCALLBACK(int) cpumR3RegSet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
253	{
254	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
255	return VERR_DBGF_READ_ONLY_REGISTER;
256	}
257
258
259
260	/*
261	*
262	* Guest register access functions.
263	*
264	*/
265
266	/**
267	* @interface_method_impl{DBGFREGDESC, pfnGet}
268	*/
269	static DECLCALLBACK(int) cpumR3RegGstGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
270	{
271	PVMCPU pVCpu = (PVMCPU)pvUser;
272	VMCPU_ASSERT_EMT(pVCpu);
273
274	uint64_t u64Value;
275	int rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64Value);
276	AssertRCReturn(rc, rc);
277	switch (pDesc->enmType)
278	{
279	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
280	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
281	default:
282	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
283	}
284	return VINF_SUCCESS;
285	}
286
287
288	/**
289	* @interface_method_impl{DBGFREGDESC, pfnGet}
290	*/
291	static DECLCALLBACK(int) cpumR3RegGstSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
292	{
293	int rc;
294	PVMCPU pVCpu = (PVMCPU)pvUser;
295
296	VMCPU_ASSERT_EMT(pVCpu);
297
298	/*
299	* Calculate the new value.
300	*/
301	uint64_t u64Value;
302	uint64_t fMask;
303	uint64_t fMaskMax;
304	switch (pDesc->enmType)
305	{
306	case DBGFREGVALTYPE_U64:
307	u64Value = pValue->u64;
308	fMask = pfMask->u64;
309	fMaskMax = UINT64_MAX;
310	break;
311	case DBGFREGVALTYPE_U32:
312	u64Value = pValue->u32;
313	fMask = pfMask->u32;
314	fMaskMax = UINT32_MAX;
315	break;
316	default:
317	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
318	}
319	if (fMask != fMaskMax)
320	{
321	uint64_t u64FullValue;
322	rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64FullValue);
323	if (RT_FAILURE(rc))
324	return rc;
325	u64Value = (u64FullValue & ~fMask)
326	\| (u64Value & fMask);
327	}
328
329	/*
330	* Perform the assignment.
331	*/
332	switch (pDesc->offRegister)
333	{
334	case 0: rc = CPUMSetGuestCR0(pVCpu, u64Value); break;
335	case 2: rc = CPUMSetGuestCR2(pVCpu, u64Value); break;
336	case 3: rc = CPUMSetGuestCR3(pVCpu, u64Value); break;
337	case 4: rc = CPUMSetGuestCR4(pVCpu, u64Value); break;
338	case 8: rc = PDMApicSetTPR(pVCpu, (uint8_t)(u64Value << 4)); break;
339	default:
340	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
341	}
342	return rc;
343	}
344
345
346	/**
347	* @interface_method_impl{DBGFREGDESC, pfnGet}
348	*/
349	static DECLCALLBACK(int) cpumR3RegGstGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
350	{
351	PVMCPU pVCpu = (PVMCPU)pvUser;
352	VMCPU_ASSERT_EMT(pVCpu);
353
354	uint64_t u64Value;
355	int rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64Value);
356	AssertRCReturn(rc, rc);
357	switch (pDesc->enmType)
358	{
359	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
360	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
361	default:
362	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
363	}
364	return VINF_SUCCESS;
365	}
366
367
368	/**
369	* @interface_method_impl{DBGFREGDESC, pfnGet}
370	*/
371	static DECLCALLBACK(int) cpumR3RegGstSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
372	{
373	int rc;
374	PVMCPU pVCpu = (PVMCPU)pvUser;
375
376	VMCPU_ASSERT_EMT(pVCpu);
377
378	/*
379	* Calculate the new value.
380	*/
381	uint64_t u64Value;
382	uint64_t fMask;
383	uint64_t fMaskMax;
384	switch (pDesc->enmType)
385	{
386	case DBGFREGVALTYPE_U64:
387	u64Value = pValue->u64;
388	fMask = pfMask->u64;
389	fMaskMax = UINT64_MAX;
390	break;
391	case DBGFREGVALTYPE_U32:
392	u64Value = pValue->u32;
393	fMask = pfMask->u32;
394	fMaskMax = UINT32_MAX;
395	break;
396	default:
397	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
398	}
399	if (fMask != fMaskMax)
400	{
401	uint64_t u64FullValue;
402	rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64FullValue);
403	if (RT_FAILURE(rc))
404	return rc;
405	u64Value = (u64FullValue & ~fMask)
406	\| (u64Value & fMask);
407	}
408
409	/*
410	* Perform the assignment.
411	*/
412	return CPUMSetGuestDRx(pVCpu, pDesc->offRegister, u64Value);
413	}
414
415
416	/**
417	* @interface_method_impl{DBGFREGDESC, pfnGet}
418	*/
419	static DECLCALLBACK(int) cpumR3RegGstGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
420	{
421	PVMCPU pVCpu = (PVMCPU)pvUser;
422	VMCPU_ASSERT_EMT(pVCpu);
423
424	uint64_t u64Value;
425	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64Value);
426	if (rcStrict == VINF_SUCCESS)
427	{
428	switch (pDesc->enmType)
429	{
430	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
431	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
432	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
433	default:
434	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
435	}
436	return VBOXSTRICTRC_VAL(rcStrict);
437	}
438
439	/** @todo what to do about errors? */
440	Assert(RT_FAILURE_NP(rcStrict));
441	return VBOXSTRICTRC_VAL(rcStrict);
442	}
443
444
445	/**
446	* @interface_method_impl{DBGFREGDESC, pfnGet}
447	*/
448	static DECLCALLBACK(int) cpumR3RegGstSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
449	{
450	PVMCPU pVCpu = (PVMCPU)pvUser;
451
452	VMCPU_ASSERT_EMT(pVCpu);
453
454	/*
455	* Calculate the new value.
456	*/
457	uint64_t u64Value;
458	uint64_t fMask;
459	uint64_t fMaskMax;
460	switch (pDesc->enmType)
461	{
462	case DBGFREGVALTYPE_U64:
463	u64Value = pValue->u64;
464	fMask = pfMask->u64;
465	fMaskMax = UINT64_MAX;
466	break;
467	case DBGFREGVALTYPE_U32:
468	u64Value = pValue->u32;
469	fMask = pfMask->u32;
470	fMaskMax = UINT32_MAX;
471	break;
472	case DBGFREGVALTYPE_U16:
473	u64Value = pValue->u16;
474	fMask = pfMask->u16;
475	fMaskMax = UINT16_MAX;
476	break;
477	default:
478	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
479	}
480	if (fMask != fMaskMax)
481	{
482	uint64_t u64FullValue;
483	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64FullValue);
484	if (rcStrict != VINF_SUCCESS)
485	{
486	AssertRC(RT_FAILURE_NP(rcStrict));
487	return VBOXSTRICTRC_VAL(rcStrict);
488	}
489	u64Value = (u64FullValue & ~fMask)
490	\| (u64Value & fMask);
491	}
492
493	/*
494	* Perform the assignment.
495	*/
496	VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pDesc->offRegister, u64Value);
497	if (rcStrict == VINF_SUCCESS)
498	return VINF_SUCCESS;
499	AssertRC(RT_FAILURE_NP(rcStrict));
500	return VBOXSTRICTRC_VAL(rcStrict);
501	}
502
503
504	/**
505	* @interface_method_impl{DBGFREGDESC, pfnGet}
506	*/
507	static DECLCALLBACK(int) cpumR3RegGstGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
508	{
509	PVMCPU pVCpu = (PVMCPU)pvUser;
510	VMCPU_ASSERT_EMT(pVCpu);
511	Assert(pDesc->enmType == DBGFREGVALTYPE_R80);
512
513	if (cpumR3RegIsFxSaveFormat(pVCpu))
514	{
515	unsigned iReg = (pVCpu->cpum.s.Guest.fpu.FSW >> 11) & 7;
516	iReg += pDesc->offRegister;
517	iReg &= 7;
518	pValue->r80Ex = pVCpu->cpum.s.Guest.fpu.aRegs[iReg].r80Ex;
519	}
520	else
521	{
522	PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.fpu;
523
524	unsigned iReg = (pOldFpu->FSW >> 11) & 7;
525	iReg += pDesc->offRegister;
526	iReg &= 7;
527
528	pValue->r80Ex = pOldFpu->regs[iReg].r80Ex;
529	}
530
531	return VINF_SUCCESS;
532	}
533
534
535	/**
536	* @interface_method_impl{DBGFREGDESC, pfnGet}
537	*/
538	static DECLCALLBACK(int) cpumR3RegGstSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
539	{
540	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
541	return VERR_NOT_IMPLEMENTED;
542	}
543
544
545
546	/*
547	*
548	* Hypervisor register access functions.
549	*
550	*/
551
552	/**
553	* @interface_method_impl{DBGFREGDESC, pfnGet}
554	*/
555	static DECLCALLBACK(int) cpumR3RegHyperGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
556	{
557	PVMCPU pVCpu = (PVMCPU)pvUser;
558	VMCPU_ASSERT_EMT(pVCpu);
559
560	uint64_t u64Value;
561	switch (pDesc->offRegister)
562	{
563	case 0: u64Value = UINT64_MAX; break;
564	case 2: u64Value = UINT64_MAX; break;
565	case 3: u64Value = CPUMGetHyperCR3(pVCpu); break;
566	case 4: u64Value = UINT64_MAX; break;
567	case 8: u64Value = UINT64_MAX; break;
568	default:
569	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
570	}
571	switch (pDesc->enmType)
572	{
573	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
574	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
575	default:
576	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
577	}
578	return VINF_SUCCESS;
579	}
580
581
582	/**
583	* @interface_method_impl{DBGFREGDESC, pfnGet}
584	*/
585	static DECLCALLBACK(int) cpumR3RegHyperSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
586	{
587	/* Not settable, prevents killing your host. */
588	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
589	return VERR_ACCESS_DENIED;
590	}
591
592
593	/**
594	* @interface_method_impl{DBGFREGDESC, pfnGet}
595	*/
596	static DECLCALLBACK(int) cpumR3RegHyperGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
597	{
598	PVMCPU pVCpu = (PVMCPU)pvUser;
599	VMCPU_ASSERT_EMT(pVCpu);
600
601	uint64_t u64Value;
602	switch (pDesc->offRegister)
603	{
604	case 0: u64Value = CPUMGetHyperDR0(pVCpu); break;
605	case 1: u64Value = CPUMGetHyperDR1(pVCpu); break;
606	case 2: u64Value = CPUMGetHyperDR2(pVCpu); break;
607	case 3: u64Value = CPUMGetHyperDR3(pVCpu); break;
608	case 6: u64Value = CPUMGetHyperDR6(pVCpu); break;
609	case 7: u64Value = CPUMGetHyperDR7(pVCpu); break;
610	default:
611	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
612	}
613	switch (pDesc->enmType)
614	{
615	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
616	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
617	default:
618	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
619	}
620	return VINF_SUCCESS;
621	}
622
623
624	/**
625	* @interface_method_impl{DBGFREGDESC, pfnGet}
626	*/
627	static DECLCALLBACK(int) cpumR3RegHyperSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
628	{
629	/* Not settable, prevents killing your host. */
630	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
631	return VERR_ACCESS_DENIED;
632	}
633
634
635	/**
636	* @interface_method_impl{DBGFREGDESC, pfnGet}
637	*/
638	static DECLCALLBACK(int) cpumR3RegHyperGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
639	{
640	NOREF(pvUser);
641
642	/* Not availble at present, return all FFs to keep things quiet */
643	uint64_t u64Value = UINT64_MAX;
644	switch (pDesc->enmType)
645	{
646	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
647	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
648	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
649	default:
650	AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
651	}
652	return VINF_SUCCESS;
653	}
654
655
656	/**
657	* @interface_method_impl{DBGFREGDESC, pfnGet}
658	*/
659	static DECLCALLBACK(int) cpumR3RegHyperSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
660	{
661	/* Not settable, return failure. */
662	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
663	return VERR_ACCESS_DENIED;
664	}
665
666
667	/**
668	* @interface_method_impl{DBGFREGDESC, pfnGet}
669	*/
670	static DECLCALLBACK(int) cpumR3RegHyperGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
671	{
672	PVMCPU pVCpu = (PVMCPU)pvUser;
673
674	VMCPU_ASSERT_EMT(pVCpu);
675	Assert(pDesc->enmType == DBGFREGVALTYPE_R80);
676
677	if (cpumR3RegIsFxSaveFormat(pVCpu))
678	{
679	unsigned iReg = (pVCpu->cpum.s.Guest.fpu.FSW >> 11) & 7;
680	iReg += pDesc->offRegister;
681	iReg &= 7;
682	pValue->r80Ex = pVCpu->cpum.s.Guest.fpu.aRegs[iReg].r80Ex;
683	}
684	else
685	{
686	PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.fpu;
687
688	unsigned iReg = (pOldFpu->FSW >> 11) & 7;
689	iReg += pDesc->offRegister;
690	iReg &= 7;
691
692	pValue->r80Ex = pOldFpu->regs[iReg].r80Ex;
693	}
694
695	return VINF_SUCCESS;
696	}
697
698
699	/**
700	* @interface_method_impl{DBGFREGDESC, pfnGet}
701	*/
702	static DECLCALLBACK(int) cpumR3RegHyperSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
703	{
704	/* There isn't a FPU context for the hypervisor yet, so no point in trying to set stuff. */
705	NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
706	return VERR_ACCESS_DENIED;
707	}
708
709
710
711	/*
712	* Set up aliases.
713	*/
714	#define CPUMREGALIAS_STD(Name, psz32, psz16, psz8) \
715	static DBGFREGALIAS const g_aCpumRegAliases_##Name[] = \
716	{ \
717	{ psz32, DBGFREGVALTYPE_U32 }, \
718	{ psz16, DBGFREGVALTYPE_U16 }, \
719	{ psz8, DBGFREGVALTYPE_U8 }, \
720	{ NULL, DBGFREGVALTYPE_INVALID } \
721	}
722	CPUMREGALIAS_STD(rax, "eax", "ax", "al");
723	CPUMREGALIAS_STD(rcx, "ecx", "cx", "cl");
724	CPUMREGALIAS_STD(rdx, "edx", "dx", "dl");
725	CPUMREGALIAS_STD(rbx, "ebx", "bx", "bl");
726	CPUMREGALIAS_STD(rsp, "esp", "sp", NULL);
727	CPUMREGALIAS_STD(rbp, "ebp", "bp", NULL);
728	CPUMREGALIAS_STD(rsi, "esi", "si", "sil");
729	CPUMREGALIAS_STD(rdi, "edi", "di", "dil");
730	CPUMREGALIAS_STD(r8, "r8d", "r8w", "r8b");
731	CPUMREGALIAS_STD(r9, "r9d", "r9w", "r9b");
732	CPUMREGALIAS_STD(r10, "r10d", "r10w", "r10b");
733	CPUMREGALIAS_STD(r11, "r11d", "r11w", "r11b");
734	CPUMREGALIAS_STD(r12, "r12d", "r12w", "r12b");
735	CPUMREGALIAS_STD(r13, "r13d", "r13w", "r13b");
736	CPUMREGALIAS_STD(r14, "r14d", "r14w", "r14b");
737	CPUMREGALIAS_STD(r15, "r15d", "r15w", "r15b");
738	CPUMREGALIAS_STD(rip, "eip", "ip", NULL);
739	CPUMREGALIAS_STD(rflags, "eflags", "flags", NULL);
740	#undef CPUMREGALIAS_STD
741
742	static DBGFREGALIAS const g_aCpumRegAliases_fpuip[] =
743	{
744	{ "fpuip16", DBGFREGVALTYPE_U16 },
745	{ NULL, DBGFREGVALTYPE_INVALID }
746	};
747
748	static DBGFREGALIAS const g_aCpumRegAliases_fpudp[] =
749	{
750	{ "fpudp16", DBGFREGVALTYPE_U16 },
751	{ NULL, DBGFREGVALTYPE_INVALID }
752	};
753
754	static DBGFREGALIAS const g_aCpumRegAliases_cr0[] =
755	{
756	{ "msw", DBGFREGVALTYPE_U16 },
757	{ NULL, DBGFREGVALTYPE_INVALID }
758	};
759
760	/*
761	* Sub fields.
762	*/
763	/** Sub-fields for the (hidden) segment attribute register. */
764	static DBGFREGSUBFIELD const g_aCpumRegFields_seg[] =
765	{
766	DBGFREGSUBFIELD_RW("type", 0, 4, 0),
767	DBGFREGSUBFIELD_RW("s", 4, 1, 0),
768	DBGFREGSUBFIELD_RW("dpl", 5, 2, 0),
769	DBGFREGSUBFIELD_RW("p", 7, 1, 0),
770	DBGFREGSUBFIELD_RW("avl", 12, 1, 0),
771	DBGFREGSUBFIELD_RW("l", 13, 1, 0),
772	DBGFREGSUBFIELD_RW("d", 14, 1, 0),
773	DBGFREGSUBFIELD_RW("g", 15, 1, 0),
774	DBGFREGSUBFIELD_TERMINATOR()
775	};
776
777	/** Sub-fields for the flags register. */
778	static DBGFREGSUBFIELD const g_aCpumRegFields_rflags[] =
779	{
780	DBGFREGSUBFIELD_RW("cf", 0, 1, 0),
781	DBGFREGSUBFIELD_RW("pf", 2, 1, 0),
782	DBGFREGSUBFIELD_RW("af", 4, 1, 0),
783	DBGFREGSUBFIELD_RW("zf", 6, 1, 0),
784	DBGFREGSUBFIELD_RW("sf", 7, 1, 0),
785	DBGFREGSUBFIELD_RW("tf", 8, 1, 0),
786	DBGFREGSUBFIELD_RW("if", 9, 1, 0),
787	DBGFREGSUBFIELD_RW("df", 10, 1, 0),
788	DBGFREGSUBFIELD_RW("of", 11, 1, 0),
789	DBGFREGSUBFIELD_RW("iopl", 12, 2, 0),
790	DBGFREGSUBFIELD_RW("nt", 14, 1, 0),
791	DBGFREGSUBFIELD_RW("rf", 16, 1, 0),
792	DBGFREGSUBFIELD_RW("vm", 17, 1, 0),
793	DBGFREGSUBFIELD_RW("ac", 18, 1, 0),
794	DBGFREGSUBFIELD_RW("vif", 19, 1, 0),
795	DBGFREGSUBFIELD_RW("vip", 20, 1, 0),
796	DBGFREGSUBFIELD_RW("id", 21, 1, 0),
797	DBGFREGSUBFIELD_TERMINATOR()
798	};
799
800	/** Sub-fields for the FPU control word register. */
801	static DBGFREGSUBFIELD const g_aCpumRegFields_fcw[] =
802	{
803	DBGFREGSUBFIELD_RW("im", 1, 1, 0),
804	DBGFREGSUBFIELD_RW("dm", 2, 1, 0),
805	DBGFREGSUBFIELD_RW("zm", 3, 1, 0),
806	DBGFREGSUBFIELD_RW("om", 4, 1, 0),
807	DBGFREGSUBFIELD_RW("um", 5, 1, 0),
808	DBGFREGSUBFIELD_RW("pm", 6, 1, 0),
809	DBGFREGSUBFIELD_RW("pc", 8, 2, 0),
810	DBGFREGSUBFIELD_RW("rc", 10, 2, 0),
811	DBGFREGSUBFIELD_RW("x", 12, 1, 0),
812	DBGFREGSUBFIELD_TERMINATOR()
813	};
814
815	/** Sub-fields for the FPU status word register. */
816	static DBGFREGSUBFIELD const g_aCpumRegFields_fsw[] =
817	{
818	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
819	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
820	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
821	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
822	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
823	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
824	DBGFREGSUBFIELD_RW("se", 6, 1, 0),
825	DBGFREGSUBFIELD_RW("es", 7, 1, 0),
826	DBGFREGSUBFIELD_RW("c0", 8, 1, 0),
827	DBGFREGSUBFIELD_RW("c1", 9, 1, 0),
828	DBGFREGSUBFIELD_RW("c2", 10, 1, 0),
829	DBGFREGSUBFIELD_RW("top", 11, 3, 0),
830	DBGFREGSUBFIELD_RW("c3", 14, 1, 0),
831	DBGFREGSUBFIELD_RW("b", 15, 1, 0),
832	DBGFREGSUBFIELD_TERMINATOR()
833	};
834
835	/** Sub-fields for the FPU tag word register. */
836	static DBGFREGSUBFIELD const g_aCpumRegFields_ftw[] =
837	{
838	DBGFREGSUBFIELD_RW("tag0", 0, 2, 0),
839	DBGFREGSUBFIELD_RW("tag1", 2, 2, 0),
840	DBGFREGSUBFIELD_RW("tag2", 4, 2, 0),
841	DBGFREGSUBFIELD_RW("tag3", 6, 2, 0),
842	DBGFREGSUBFIELD_RW("tag4", 8, 2, 0),
843	DBGFREGSUBFIELD_RW("tag5", 10, 2, 0),
844	DBGFREGSUBFIELD_RW("tag6", 12, 2, 0),
845	DBGFREGSUBFIELD_RW("tag7", 14, 2, 0),
846	DBGFREGSUBFIELD_TERMINATOR()
847	};
848
849	/** Sub-fields for the Multimedia Extensions Control and Status Register. */
850	static DBGFREGSUBFIELD const g_aCpumRegFields_mxcsr[] =
851	{
852	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
853	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
854	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
855	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
856	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
857	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
858	DBGFREGSUBFIELD_RW("daz", 6, 1, 0),
859	DBGFREGSUBFIELD_RW("im", 7, 1, 0),
860	DBGFREGSUBFIELD_RW("dm", 8, 1, 0),
861	DBGFREGSUBFIELD_RW("zm", 9, 1, 0),
862	DBGFREGSUBFIELD_RW("om", 10, 1, 0),
863	DBGFREGSUBFIELD_RW("um", 11, 1, 0),
864	DBGFREGSUBFIELD_RW("pm", 12, 1, 0),
865	DBGFREGSUBFIELD_RW("rc", 13, 2, 0),
866	DBGFREGSUBFIELD_RW("fz", 14, 1, 0),
867	DBGFREGSUBFIELD_TERMINATOR()
868	};
869
870	/** Sub-fields for the FPU tag word register. */
871	static DBGFREGSUBFIELD const g_aCpumRegFields_stN[] =
872	{
873	DBGFREGSUBFIELD_RW("man", 0, 64, 0),
874	DBGFREGSUBFIELD_RW("exp", 64, 15, 0),
875	DBGFREGSUBFIELD_RW("sig", 79, 1, 0),
876	DBGFREGSUBFIELD_TERMINATOR()
877	};
878
879	/** Sub-fields for the MMX registers. */
880	static DBGFREGSUBFIELD const g_aCpumRegFields_mmN[] =
881	{
882	DBGFREGSUBFIELD_RW("dw0", 0, 32, 0),
883	DBGFREGSUBFIELD_RW("dw1", 32, 32, 0),
884	DBGFREGSUBFIELD_RW("w0", 0, 16, 0),
885	DBGFREGSUBFIELD_RW("w1", 16, 16, 0),
886	DBGFREGSUBFIELD_RW("w2", 32, 16, 0),
887	DBGFREGSUBFIELD_RW("w3", 48, 16, 0),
888	DBGFREGSUBFIELD_RW("b0", 0, 8, 0),
889	DBGFREGSUBFIELD_RW("b1", 8, 8, 0),
890	DBGFREGSUBFIELD_RW("b2", 16, 8, 0),
891	DBGFREGSUBFIELD_RW("b3", 24, 8, 0),
892	DBGFREGSUBFIELD_RW("b4", 32, 8, 0),
893	DBGFREGSUBFIELD_RW("b5", 40, 8, 0),
894	DBGFREGSUBFIELD_RW("b6", 48, 8, 0),
895	DBGFREGSUBFIELD_RW("b7", 56, 8, 0),
896	DBGFREGSUBFIELD_TERMINATOR()
897	};
898
899	/** Sub-fields for the XMM registers. */
900	static DBGFREGSUBFIELD const g_aCpumRegFields_xmmN[] =
901	{
902	DBGFREGSUBFIELD_RW("r0", 0, 32, 0),
903	DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0),
904	DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0),
905	DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0),
906	DBGFREGSUBFIELD_RW("r1", 32, 32, 0),
907	DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0),
908	DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0),
909	DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0),
910	DBGFREGSUBFIELD_RW("r2", 64, 32, 0),
911	DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0),
912	DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0),
913	DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0),
914	DBGFREGSUBFIELD_RW("r3", 96, 32, 0),
915	DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0),
916	DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0),
917	DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0),
918	DBGFREGSUBFIELD_TERMINATOR()
919	};
920
921	/** Sub-fields for the CR0 register. */
922	static DBGFREGSUBFIELD const g_aCpumRegFields_cr0[] =
923	{
924	DBGFREGSUBFIELD_RW("pe", 0, 1, 0),
925	DBGFREGSUBFIELD_RW("mp", 1, 1, 0),
926	DBGFREGSUBFIELD_RW("em", 2, 1, 0),
927	DBGFREGSUBFIELD_RW("ts", 3, 1, 0),
928	DBGFREGSUBFIELD_RO("et", 4, 1, 0),
929	DBGFREGSUBFIELD_RW("ne", 5, 1, 0),
930	DBGFREGSUBFIELD_RW("wp", 16, 1, 0),
931	DBGFREGSUBFIELD_RW("am", 18, 1, 0),
932	DBGFREGSUBFIELD_RW("nw", 29, 1, 0),
933	DBGFREGSUBFIELD_RW("cd", 30, 1, 0),
934	DBGFREGSUBFIELD_RW("pg", 31, 1, 0),
935	DBGFREGSUBFIELD_TERMINATOR()
936	};
937
938	/** Sub-fields for the CR3 register. */
939	static DBGFREGSUBFIELD const g_aCpumRegFields_cr3[] =
940	{
941	DBGFREGSUBFIELD_RW("pwt", 3, 1, 0),
942	DBGFREGSUBFIELD_RW("pcd", 4, 1, 0),
943	DBGFREGSUBFIELD_TERMINATOR()
944	};
945
946	/** Sub-fields for the CR4 register. */
947	static DBGFREGSUBFIELD const g_aCpumRegFields_cr4[] =
948	{
949	DBGFREGSUBFIELD_RW("vme", 0, 1, 0),
950	DBGFREGSUBFIELD_RW("pvi", 1, 1, 0),
951	DBGFREGSUBFIELD_RW("tsd", 2, 1, 0),
952	DBGFREGSUBFIELD_RW("de", 3, 1, 0),
953	DBGFREGSUBFIELD_RW("pse", 4, 1, 0),
954	DBGFREGSUBFIELD_RW("pae", 5, 1, 0),
955	DBGFREGSUBFIELD_RW("mce", 6, 1, 0),
956	DBGFREGSUBFIELD_RW("pge", 7, 1, 0),
957	DBGFREGSUBFIELD_RW("pce", 8, 1, 0),
958	DBGFREGSUBFIELD_RW("osfsxr", 9, 1, 0),
959	DBGFREGSUBFIELD_RW("osxmmeexcpt", 10, 1, 0),
960	DBGFREGSUBFIELD_RW("vmxe", 10, 1, 0),
961	DBGFREGSUBFIELD_RW("smxe", 13, 1, 0),
962	DBGFREGSUBFIELD_RW("pcide", 14, 1, 0),
963	DBGFREGSUBFIELD_RW("osxsave", 17, 1, 0),
964	DBGFREGSUBFIELD_RW("smep", 18, 1, 0),
965	DBGFREGSUBFIELD_TERMINATOR()
966	};
967
968	/** Sub-fields for the DR6 register. */
969	static DBGFREGSUBFIELD const g_aCpumRegFields_dr6[] =
970	{
971	DBGFREGSUBFIELD_RW("b0", 0, 1, 0),
972	DBGFREGSUBFIELD_RW("b1", 1, 1, 0),
973	DBGFREGSUBFIELD_RW("b2", 2, 1, 0),
974	DBGFREGSUBFIELD_RW("b3", 3, 1, 0),
975	DBGFREGSUBFIELD_RW("bd", 13, 1, 0),
976	DBGFREGSUBFIELD_RW("bs", 14, 1, 0),
977	DBGFREGSUBFIELD_RW("bt", 15, 1, 0),
978	DBGFREGSUBFIELD_TERMINATOR()
979	};
980
981	/** Sub-fields for the DR7 register. */
982	static DBGFREGSUBFIELD const g_aCpumRegFields_dr7[] =
983	{
984	DBGFREGSUBFIELD_RW("l0", 0, 1, 0),
985	DBGFREGSUBFIELD_RW("g0", 1, 1, 0),
986	DBGFREGSUBFIELD_RW("l1", 2, 1, 0),
987	DBGFREGSUBFIELD_RW("g1", 3, 1, 0),
988	DBGFREGSUBFIELD_RW("l2", 4, 1, 0),
989	DBGFREGSUBFIELD_RW("g2", 5, 1, 0),
990	DBGFREGSUBFIELD_RW("l3", 6, 1, 0),
991	DBGFREGSUBFIELD_RW("g3", 7, 1, 0),
992	DBGFREGSUBFIELD_RW("le", 8, 1, 0),
993	DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
994	DBGFREGSUBFIELD_RW("gd", 13, 1, 0),
995	DBGFREGSUBFIELD_RW("rw0", 16, 2, 0),
996	DBGFREGSUBFIELD_RW("len0", 18, 2, 0),
997	DBGFREGSUBFIELD_RW("rw1", 20, 2, 0),
998	DBGFREGSUBFIELD_RW("len1", 22, 2, 0),
999	DBGFREGSUBFIELD_RW("rw2", 24, 2, 0),
1000	DBGFREGSUBFIELD_RW("len2", 26, 2, 0),
1001	DBGFREGSUBFIELD_RW("rw3", 28, 2, 0),
1002	DBGFREGSUBFIELD_RW("len3", 30, 2, 0),
1003	DBGFREGSUBFIELD_TERMINATOR()
1004	};
1005
1006	/** Sub-fields for the CR_PAT MSR. */
1007	static DBGFREGSUBFIELD const g_aCpumRegFields_apic_base[] =
1008	{
1009	DBGFREGSUBFIELD_RW("bsp", 8, 1, 0),
1010	DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
1011	DBGFREGSUBFIELD_RW("base", 12, 20, 12),
1012	DBGFREGSUBFIELD_TERMINATOR()
1013	};
1014
1015	/** Sub-fields for the CR_PAT MSR. */
1016	static DBGFREGSUBFIELD const g_aCpumRegFields_cr_pat[] =
1017	{
1018	/** @todo */
1019	DBGFREGSUBFIELD_TERMINATOR()
1020	};
1021
1022	/** Sub-fields for the PERF_STATUS MSR. */
1023	static DBGFREGSUBFIELD const g_aCpumRegFields_perf_status[] =
1024	{
1025	/** @todo */
1026	DBGFREGSUBFIELD_TERMINATOR()
1027	};
1028
1029	/** Sub-fields for the EFER MSR. */
1030	static DBGFREGSUBFIELD const g_aCpumRegFields_efer[] =
1031	{
1032	/** @todo */
1033	DBGFREGSUBFIELD_TERMINATOR()
1034	};
1035
1036	/** Sub-fields for the STAR MSR. */
1037	static DBGFREGSUBFIELD const g_aCpumRegFields_star[] =
1038	{
1039	/** @todo */
1040	DBGFREGSUBFIELD_TERMINATOR()
1041	};
1042
1043	/** Sub-fields for the CSTAR MSR. */
1044	static DBGFREGSUBFIELD const g_aCpumRegFields_cstar[] =
1045	{
1046	/** @todo */
1047	DBGFREGSUBFIELD_TERMINATOR()
1048	};
1049
1050	/** Sub-fields for the LSTAR MSR. */
1051	static DBGFREGSUBFIELD const g_aCpumRegFields_lstar[] =
1052	{
1053	/** @todo */
1054	DBGFREGSUBFIELD_TERMINATOR()
1055	};
1056
1057	/** Sub-fields for the SF_MASK MSR. */
1058	static DBGFREGSUBFIELD const g_aCpumRegFields_sf_mask[] =
1059	{
1060	/** @todo */
1061	DBGFREGSUBFIELD_TERMINATOR()
1062	};
1063
1064
1065	/** @name Macros for producing register descriptor table entries.
1066	* @{ */
1067	#define CPU_REG_EX_AS(a_szName, a_RegSuff, a_TypeSuff, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1068	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1069
1070	#define CPU_REG_REG(UName, LName) \
1071	CPU_REG_RW_AS(#LName, UName, U64, LName, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_##LName, NULL)
1072
1073	#define CPU_REG_SEG(UName, LName) \
1074	CPU_REG_RW_AS(#LName, UName, U16, LName.Sel, cpumR3RegGet_Generic, cpumR3RegSet_seg, NULL, NULL ), \
1075	CPU_REG_RW_AS(#LName "_attr", UName##_ATTR, U32, LName.Attr.u, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_seg), \
1076	CPU_REG_RW_AS(#LName "_base", UName##_BASE, U64, LName.u64Base, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), \
1077	CPU_REG_RW_AS(#LName "_lim", UName##_LIMIT, U32, LName.u32Limit, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL )
1078
1079	#define CPU_REG_MM(n) \
1080	CPU_REG_RW_AS("mm" #n, MM##n, U64, fpu.aRegs[n].mmx, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mmN)
1081
1082	#define CPU_REG_XMM(n) \
1083	CPU_REG_RW_AS("xmm" #n, XMM##n, U128, fpu.aXMM[n].xmm, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_xmmN)
1084	/** @} */
1085
1086
1087	/**
1088	* The guest register descriptors.
1089	*/
1090	static DBGFREGDESC const g_aCpumRegGstDescs[] =
1091	{
1092	#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1093	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1094	#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1095	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1096	#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
1097	CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegGstGet_msr, cpumR3RegGstSet_msr, NULL, a_paSubFields)
1098	#define CPU_REG_ST(n) \
1099	CPU_REG_EX_AS("st" #n, ST##n, R80, n, cpumR3RegGstGet_stN, cpumR3RegGstSet_stN, NULL, g_aCpumRegFields_stN)
1100
1101	CPU_REG_REG(RAX, rax),
1102	CPU_REG_REG(RCX, rcx),
1103	CPU_REG_REG(RDX, rdx),
1104	CPU_REG_REG(RBX, rbx),
1105	CPU_REG_REG(RSP, rsp),
1106	CPU_REG_REG(RBP, rbp),
1107	CPU_REG_REG(RSI, rsi),
1108	CPU_REG_REG(RDI, rdi),
1109	CPU_REG_REG(R8, r8),
1110	CPU_REG_REG(R9, r9),
1111	CPU_REG_REG(R10, r10),
1112	CPU_REG_REG(R11, r11),
1113	CPU_REG_REG(R12, r12),
1114	CPU_REG_REG(R13, r13),
1115	CPU_REG_REG(R14, r14),
1116	CPU_REG_REG(R15, r15),
1117	CPU_REG_SEG(CS, cs),
1118	CPU_REG_SEG(DS, ds),
1119	CPU_REG_SEG(ES, es),
1120	CPU_REG_SEG(FS, fs),
1121	CPU_REG_SEG(GS, gs),
1122	CPU_REG_SEG(SS, ss),
1123	CPU_REG_REG(RIP, rip),
1124	CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
1125	CPU_REG_RW_AS("fcw", FCW, U16, fpu.FCW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fcw ),
1126	CPU_REG_RW_AS("fsw", FSW, U16, fpu.FSW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fsw ),
1127	CPU_REG_RO_AS("ftw", FTW, U16, fpu, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ),
1128	CPU_REG_RW_AS("fop", FOP, U16, fpu.FOP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1129	CPU_REG_RW_AS("fpuip", FPUIP, U32, fpu.FPUIP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpuip, NULL ),
1130	CPU_REG_RW_AS("fpucs", FPUCS, U16, fpu.CS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1131	CPU_REG_RW_AS("fpudp", FPUDP, U32, fpu.FPUDP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpudp, NULL ),
1132	CPU_REG_RW_AS("fpuds", FPUDS, U16, fpu.DS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1133	CPU_REG_RW_AS("mxcsr", MXCSR, U32, fpu.MXCSR, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
1134	CPU_REG_RW_AS("mxcsr_mask", MXCSR_MASK, U32, fpu.MXCSR_MASK, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
1135	CPU_REG_ST(0),
1136	CPU_REG_ST(1),
1137	CPU_REG_ST(2),
1138	CPU_REG_ST(3),
1139	CPU_REG_ST(4),
1140	CPU_REG_ST(5),
1141	CPU_REG_ST(6),
1142	CPU_REG_ST(7),
1143	CPU_REG_MM(0),
1144	CPU_REG_MM(1),
1145	CPU_REG_MM(2),
1146	CPU_REG_MM(3),
1147	CPU_REG_MM(4),
1148	CPU_REG_MM(5),
1149	CPU_REG_MM(6),
1150	CPU_REG_MM(7),
1151	CPU_REG_XMM(0),
1152	CPU_REG_XMM(1),
1153	CPU_REG_XMM(2),
1154	CPU_REG_XMM(3),
1155	CPU_REG_XMM(4),
1156	CPU_REG_XMM(5),
1157	CPU_REG_XMM(6),
1158	CPU_REG_XMM(7),
1159	CPU_REG_XMM(8),
1160	CPU_REG_XMM(9),
1161	CPU_REG_XMM(10),
1162	CPU_REG_XMM(11),
1163	CPU_REG_XMM(12),
1164	CPU_REG_XMM(13),
1165	CPU_REG_XMM(14),
1166	CPU_REG_XMM(15),
1167	CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1168	CPU_REG_RW_AS("gdtr_lim", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1169	CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1170	CPU_REG_RW_AS("idtr_lim", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1171	CPU_REG_SEG(LDTR, ldtr),
1172	CPU_REG_SEG(TR, tr),
1173	CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
1174	CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1175	CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr3 ),
1176	CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr4 ),
1177	CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1178	CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1179	CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1180	CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1181	CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1182	CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr6 ),
1183	CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr7 ),
1184	CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
1185	CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
1186	CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
1187	CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
1188	CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ),
1189	CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ),
1190	CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ),
1191	CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
1192	CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
1193	CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
1194	CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
1195	CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
1196	CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
1197	CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
1198	CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
1199	CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
1200	CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Guest.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1201	CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Guest.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1202	CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Guest.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1203	CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Guest.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1204	CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
1205	CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
1206	DBGFREGDESC_TERMINATOR()
1207
1208	#undef CPU_REG_RW_AS
1209	#undef CPU_REG_RO_AS
1210	#undef CPU_REG_MSR
1211	#undef CPU_REG_ST
1212	};
1213
1214
1215	/**
1216	* The hypervisor (raw-mode) register descriptors.
1217	*/
1218	static DBGFREGDESC const g_aCpumRegHyperDescs[] =
1219	{
1220	#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1221	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(CPUMCPU, Hyper.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1222	#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1223	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Hyper.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1224	#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
1225	CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegHyperGet_msr, cpumR3RegHyperSet_msr, NULL, a_paSubFields)
1226	#define CPU_REG_ST(n) \
1227	CPU_REG_EX_AS("st" #n, ST##n, R80, n, cpumR3RegHyperGet_stN, cpumR3RegHyperSet_stN, NULL, g_aCpumRegFields_stN)
1228
1229	CPU_REG_REG(RAX, rax),
1230	CPU_REG_REG(RCX, rcx),
1231	CPU_REG_REG(RDX, rdx),
1232	CPU_REG_REG(RBX, rbx),
1233	CPU_REG_REG(RSP, rsp),
1234	CPU_REG_REG(RBP, rbp),
1235	CPU_REG_REG(RSI, rsi),
1236	CPU_REG_REG(RDI, rdi),
1237	CPU_REG_REG(R8, r8),
1238	CPU_REG_REG(R9, r9),
1239	CPU_REG_REG(R10, r10),
1240	CPU_REG_REG(R11, r11),
1241	CPU_REG_REG(R12, r12),
1242	CPU_REG_REG(R13, r13),
1243	CPU_REG_REG(R14, r14),
1244	CPU_REG_REG(R15, r15),
1245	CPU_REG_SEG(CS, cs),
1246	CPU_REG_SEG(DS, ds),
1247	CPU_REG_SEG(ES, es),
1248	CPU_REG_SEG(FS, fs),
1249	CPU_REG_SEG(GS, gs),
1250	CPU_REG_SEG(SS, ss),
1251	CPU_REG_REG(RIP, rip),
1252	CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
1253	CPU_REG_RW_AS("fcw", FCW, U16, fpu.FCW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fcw ),
1254	CPU_REG_RW_AS("fsw", FSW, U16, fpu.FSW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fsw ),
1255	CPU_REG_RO_AS("ftw", FTW, U16, fpu, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ),
1256	CPU_REG_RW_AS("fop", FOP, U16, fpu.FOP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1257	CPU_REG_RW_AS("fpuip", FPUIP, U32, fpu.FPUIP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpuip, NULL ),
1258	CPU_REG_RW_AS("fpucs", FPUCS, U16, fpu.CS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1259	CPU_REG_RW_AS("fpudp", FPUDP, U32, fpu.FPUDP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpudp, NULL ),
1260	CPU_REG_RW_AS("fpuds", FPUDS, U16, fpu.DS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1261	CPU_REG_RW_AS("mxcsr", MXCSR, U32, fpu.MXCSR, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
1262	CPU_REG_RW_AS("mxcsr_mask", MXCSR_MASK, U32, fpu.MXCSR_MASK, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
1263	CPU_REG_ST(0),
1264	CPU_REG_ST(1),
1265	CPU_REG_ST(2),
1266	CPU_REG_ST(3),
1267	CPU_REG_ST(4),
1268	CPU_REG_ST(5),
1269	CPU_REG_ST(6),
1270	CPU_REG_ST(7),
1271	CPU_REG_MM(0),
1272	CPU_REG_MM(1),
1273	CPU_REG_MM(2),
1274	CPU_REG_MM(3),
1275	CPU_REG_MM(4),
1276	CPU_REG_MM(5),
1277	CPU_REG_MM(6),
1278	CPU_REG_MM(7),
1279	CPU_REG_XMM(0),
1280	CPU_REG_XMM(1),
1281	CPU_REG_XMM(2),
1282	CPU_REG_XMM(3),
1283	CPU_REG_XMM(4),
1284	CPU_REG_XMM(5),
1285	CPU_REG_XMM(6),
1286	CPU_REG_XMM(7),
1287	CPU_REG_XMM(8),
1288	CPU_REG_XMM(9),
1289	CPU_REG_XMM(10),
1290	CPU_REG_XMM(11),
1291	CPU_REG_XMM(12),
1292	CPU_REG_XMM(13),
1293	CPU_REG_XMM(14),
1294	CPU_REG_XMM(15),
1295	CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1296	CPU_REG_RW_AS("gdtr_lim", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1297	CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1298	CPU_REG_RW_AS("idtr_lim", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1299	CPU_REG_SEG(LDTR, ldtr),
1300	CPU_REG_SEG(TR, tr),
1301	CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
1302	CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, NULL ),
1303	CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, g_aCpumRegFields_cr3 ),
1304	CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, g_aCpumRegFields_cr4 ),
1305	CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, NULL ),
1306	CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1307	CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1308	CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1309	CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1310	CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr6 ),
1311	CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr7 ),
1312	CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
1313	CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
1314	CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
1315	CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
1316	CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ),
1317	CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ),
1318	CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ),
1319	CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
1320	CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
1321	CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
1322	CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
1323	CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
1324	CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
1325	CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
1326	CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
1327	CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
1328	CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1329	CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1330	CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1331	CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1332	CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
1333	CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
1334	DBGFREGDESC_TERMINATOR()
1335	#undef CPU_REG_RW_AS
1336	#undef CPU_REG_RO_AS
1337	#undef CPU_REG_MSR
1338	#undef CPU_REG_ST
1339	};
1340
1341
1342	/**
1343	* Initializes the debugger related sides of the CPUM component.
1344	*
1345	* Called by CPUMR3Init.
1346	*
1347	* @returns VBox status code.
1348	* @param pVM Pointer to the VM.
1349	*/
1350	int cpumR3DbgInit(PVM pVM)
1351	{
1352	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1353	{
1354	int rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegGstDescs, true /fGuestRegs/);
1355	AssertLogRelRCReturn(rc, rc);
1356	rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegHyperDescs, false /fGuestRegs/);
1357	AssertLogRelRCReturn(rc, rc);
1358	}
1359
1360	return VINF_SUCCESS;
1361	}
1362

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp@ 54338

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