VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp@ 80050

Last change on this file since 80050 was 80050, checked in by vboxsync, 5 years ago

Main: Kicking out raw-mode - CPUM*Hyper*(). bugref:9517
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1/* $Id: CPUMDbg.cpp 80050 2019-07-29 20:04:35Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager, Debugger & Debugging APIs.
4 */
5
6/*
7 * Copyright (C) 2010-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DBGF
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/dbgf.h>
25#include <VBox/vmm/apic.h>
26#include "CPUMInternal.h"
27#include <VBox/vmm/vm.h>
28#include <VBox/param.h>
29#include <VBox/err.h>
30#include <VBox/log.h>
31#include <iprt/thread.h>
32#include <iprt/string.h>
33#include <iprt/uint128.h>
34
35
36/**
37 * @interface_method_impl{DBGFREGDESC,pfnGet}
38 */
39static DECLCALLBACK(int) cpumR3RegGet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
40{
41 PVMCPU pVCpu = (PVMCPU)pvUser;
42 void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister;
43
44 VMCPU_ASSERT_EMT(pVCpu);
45
46 switch (pDesc->enmType)
47 {
48 case DBGFREGVALTYPE_U8: pValue->u8 = *(uint8_t const *)pv; return VINF_SUCCESS;
49 case DBGFREGVALTYPE_U16: pValue->u16 = *(uint16_t const *)pv; return VINF_SUCCESS;
50 case DBGFREGVALTYPE_U32: pValue->u32 = *(uint32_t const *)pv; return VINF_SUCCESS;
51 case DBGFREGVALTYPE_U64: pValue->u64 = *(uint64_t const *)pv; return VINF_SUCCESS;
52 case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
53 case DBGFREGVALTYPE_U256: pValue->u256 = *(PCRTUINT256U )pv; return VINF_SUCCESS;
54 case DBGFREGVALTYPE_U512: pValue->u512 = *(PCRTUINT512U )pv; return VINF_SUCCESS;
55 default:
56 AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
57 }
58}
59
60
61/**
62 * @interface_method_impl{DBGFREGDESC,pfnSet}
63 */
64static DECLCALLBACK(int) cpumR3RegSet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
65{
66 PVMCPU pVCpu = (PVMCPU)pvUser;
67 void *pv = (uint8_t *)&pVCpu->cpum + pDesc->offRegister;
68
69 VMCPU_ASSERT_EMT(pVCpu);
70
71 switch (pDesc->enmType)
72 {
73 case DBGFREGVALTYPE_U8:
74 *(uint8_t *)pv &= ~pfMask->u8;
75 *(uint8_t *)pv |= pValue->u8 & pfMask->u8;
76 return VINF_SUCCESS;
77
78 case DBGFREGVALTYPE_U16:
79 *(uint16_t *)pv &= ~pfMask->u16;
80 *(uint16_t *)pv |= pValue->u16 & pfMask->u16;
81 return VINF_SUCCESS;
82
83 case DBGFREGVALTYPE_U32:
84 *(uint32_t *)pv &= ~pfMask->u32;
85 *(uint32_t *)pv |= pValue->u32 & pfMask->u32;
86 return VINF_SUCCESS;
87
88 case DBGFREGVALTYPE_U64:
89 *(uint64_t *)pv &= ~pfMask->u64;
90 *(uint64_t *)pv |= pValue->u64 & pfMask->u64;
91 return VINF_SUCCESS;
92
93 case DBGFREGVALTYPE_U128:
94 {
95 RTUINT128U Val;
96 RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
97 RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
98 return VINF_SUCCESS;
99 }
100
101 default:
102 AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
103 }
104}
105
106
107/**
108 * @interface_method_impl{DBGFREGDESC,pfnGet}
109 */
110static DECLCALLBACK(int) cpumR3RegGet_XStateGeneric(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
111{
112 PVMCPU pVCpu = (PVMCPU)pvUser;
113 void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest.pXStateR3 + pDesc->offRegister;
114
115 VMCPU_ASSERT_EMT(pVCpu);
116
117 switch (pDesc->enmType)
118 {
119 case DBGFREGVALTYPE_U8: pValue->u8 = *(uint8_t const *)pv; return VINF_SUCCESS;
120 case DBGFREGVALTYPE_U16: pValue->u16 = *(uint16_t const *)pv; return VINF_SUCCESS;
121 case DBGFREGVALTYPE_U32: pValue->u32 = *(uint32_t const *)pv; return VINF_SUCCESS;
122 case DBGFREGVALTYPE_U64: pValue->u64 = *(uint64_t const *)pv; return VINF_SUCCESS;
123 case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
124 default:
125 AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
126 }
127}
128
129
130/**
131 * @interface_method_impl{DBGFREGDESC,pfnSet}
132 */
133static DECLCALLBACK(int) cpumR3RegSet_XStateGeneric(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
134{
135 PVMCPU pVCpu = (PVMCPU)pvUser;
136 void *pv = (uint8_t *)&pVCpu->cpum.s.Guest.pXStateR3 + pDesc->offRegister;
137
138 VMCPU_ASSERT_EMT(pVCpu);
139
140 switch (pDesc->enmType)
141 {
142 case DBGFREGVALTYPE_U8:
143 *(uint8_t *)pv &= ~pfMask->u8;
144 *(uint8_t *)pv |= pValue->u8 & pfMask->u8;
145 return VINF_SUCCESS;
146
147 case DBGFREGVALTYPE_U16:
148 *(uint16_t *)pv &= ~pfMask->u16;
149 *(uint16_t *)pv |= pValue->u16 & pfMask->u16;
150 return VINF_SUCCESS;
151
152 case DBGFREGVALTYPE_U32:
153 *(uint32_t *)pv &= ~pfMask->u32;
154 *(uint32_t *)pv |= pValue->u32 & pfMask->u32;
155 return VINF_SUCCESS;
156
157 case DBGFREGVALTYPE_U64:
158 *(uint64_t *)pv &= ~pfMask->u64;
159 *(uint64_t *)pv |= pValue->u64 & pfMask->u64;
160 return VINF_SUCCESS;
161
162 case DBGFREGVALTYPE_U128:
163 {
164 RTUINT128U Val;
165 RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
166 RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
167 return VINF_SUCCESS;
168 }
169
170 default:
171 AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
172 }
173}
174
175
176
177/**
178 * @interface_method_impl{DBGFREGDESC,pfnGet}
179 */
180static DECLCALLBACK(int) cpumR3RegSet_seg(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
181{
182 /** @todo perform a selector load, updating hidden selectors and stuff. */
183 NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
184 return VERR_NOT_IMPLEMENTED;
185}
186
187
188/**
189 * @interface_method_impl{DBGFREGDESC,pfnGet}
190 */
191static DECLCALLBACK(int) cpumR3RegGet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
192{
193 PVMCPU pVCpu = (PVMCPU)pvUser;
194 VBOXGDTR const *pGdtr = (VBOXGDTR const *)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
195
196 VMCPU_ASSERT_EMT(pVCpu);
197 Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
198
199 pValue->dtr.u32Limit = pGdtr->cbGdt;
200 pValue->dtr.u64Base = pGdtr->pGdt;
201 return VINF_SUCCESS;
202}
203
204
205/**
206 * @interface_method_impl{DBGFREGDESC,pfnGet}
207 */
208static DECLCALLBACK(int) cpumR3RegSet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
209{
210 NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
211 return VERR_NOT_IMPLEMENTED;
212}
213
214
215/**
216 * @interface_method_impl{DBGFREGDESC,pfnGet}
217 */
218static DECLCALLBACK(int) cpumR3RegGet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
219{
220 PVMCPU pVCpu = (PVMCPU)pvUser;
221 VBOXIDTR const *pIdtr = (VBOXIDTR const *)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
222
223 VMCPU_ASSERT_EMT(pVCpu);
224 Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
225
226 pValue->dtr.u32Limit = pIdtr->cbIdt;
227 pValue->dtr.u64Base = pIdtr->pIdt;
228 return VINF_SUCCESS;
229}
230
231
232/**
233 * @interface_method_impl{DBGFREGDESC,pfnGet}
234 */
235static DECLCALLBACK(int) cpumR3RegSet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
236{
237 NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
238 return VERR_NOT_IMPLEMENTED;
239}
240
241
242/**
243 * Determins the tag register value for a CPU register when the FPU state
244 * format is FXSAVE.
245 *
246 * @returns The tag register value.
247 * @param pFpu Pointer to the guest FPU.
248 * @param iReg The register number (0..7).
249 */
250DECLINLINE(uint16_t) cpumR3RegCalcFpuTagFromFxSave(PCX86FXSTATE pFpu, unsigned iReg)
251{
252 /*
253 * See table 11-1 in the AMD docs.
254 */
255 if (!(pFpu->FTW & RT_BIT_32(iReg)))
256 return 3; /* b11 - empty */
257
258 uint16_t const uExp = pFpu->aRegs[iReg].au16[4];
259 if (uExp == 0)
260 {
261 if (pFpu->aRegs[iReg].au64[0] == 0) /* J & M == 0 */
262 return 1; /* b01 - zero */
263 return 2; /* b10 - special */
264 }
265
266 if (uExp == UINT16_C(0xffff))
267 return 2; /* b10 - special */
268
269 if (!(pFpu->aRegs[iReg].au64[0] >> 63)) /* J == 0 */
270 return 2; /* b10 - special */
271
272 return 0; /* b00 - valid (normal) */
273}
274
275
276/**
277 * @interface_method_impl{DBGFREGDESC,pfnGet}
278 */
279static DECLCALLBACK(int) cpumR3RegGet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
280{
281 PVMCPU pVCpu = (PVMCPU)pvUser;
282 PCX86FXSTATE pFpu = (PCX86FXSTATE)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister);
283
284 VMCPU_ASSERT_EMT(pVCpu);
285 Assert(pDesc->enmType == DBGFREGVALTYPE_U16);
286
287 pValue->u16 = cpumR3RegCalcFpuTagFromFxSave(pFpu, 0)
288 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 1) << 2)
289 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 2) << 4)
290 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 3) << 6)
291 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 4) << 8)
292 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 5) << 10)
293 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 6) << 12)
294 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 7) << 14);
295 return VINF_SUCCESS;
296}
297
298
299/**
300 * @interface_method_impl{DBGFREGDESC,pfnGet}
301 */
302static DECLCALLBACK(int) cpumR3RegSet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
303{
304 NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
305 return VERR_DBGF_READ_ONLY_REGISTER;
306}
307
308
309/**
310 * @interface_method_impl{DBGFREGDESC,pfnGet}
311 */
312static DECLCALLBACK(int) cpumR3RegGet_Dummy(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
313{
314 RT_NOREF_PV(pvUser);
315 switch (pDesc->enmType)
316 {
317 case DBGFREGVALTYPE_U8: pValue->u8 = 0; return VINF_SUCCESS;
318 case DBGFREGVALTYPE_U16: pValue->u16 = 0; return VINF_SUCCESS;
319 case DBGFREGVALTYPE_U32: pValue->u32 = 0; return VINF_SUCCESS;
320 case DBGFREGVALTYPE_U64: pValue->u64 = 0; return VINF_SUCCESS;
321 case DBGFREGVALTYPE_U128:
322 RT_ZERO(pValue->u128);
323 return VINF_SUCCESS;
324 case DBGFREGVALTYPE_DTR:
325 pValue->dtr.u32Limit = 0;
326 pValue->dtr.u64Base = 0;
327 return VINF_SUCCESS;
328 case DBGFREGVALTYPE_R80:
329 RT_ZERO(pValue->r80Ex);
330 return VINF_SUCCESS;
331 default:
332 AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
333 }
334}
335
336
337/**
338 * @interface_method_impl{DBGFREGDESC,pfnSet}
339 */
340static DECLCALLBACK(int) cpumR3RegSet_Dummy(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
341{
342 NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
343 return VERR_DBGF_READ_ONLY_REGISTER;
344}
345
346
347/**
348 * @interface_method_impl{DBGFREGDESC,pfnGet}
349 */
350static DECLCALLBACK(int) cpumR3RegGet_ymm(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
351{
352 PVMCPU pVCpu = (PVMCPU)pvUser;
353 uint32_t iReg = pDesc->offRegister;
354
355 Assert(pDesc->enmType == DBGFREGVALTYPE_U256);
356 VMCPU_ASSERT_EMT(pVCpu);
357
358 if (iReg < 16)
359 {
360 pValue->u256.DQWords.dqw0 = pVCpu->cpum.s.Guest.pXStateR3->x87.aXMM[iReg].uXmm;
361 pValue->u256.DQWords.dqw1 = pVCpu->cpum.s.Guest.pXStateR3->u.YmmHi.aYmmHi[iReg].uXmm;
362 return VINF_SUCCESS;
363 }
364 return VERR_NOT_IMPLEMENTED;
365}
366
367
368/**
369 * @interface_method_impl{DBGFREGDESC,pfnSet}
370 */
371static DECLCALLBACK(int) cpumR3RegSet_ymm(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
372{
373 PVMCPU pVCpu = (PVMCPU)pvUser;
374 uint32_t iReg = pDesc->offRegister;
375
376 Assert(pDesc->enmType == DBGFREGVALTYPE_U256);
377 VMCPU_ASSERT_EMT(pVCpu);
378
379 if (iReg < 16)
380 {
381 RTUINT128U Val;
382 RTUInt128AssignAnd(&pVCpu->cpum.s.Guest.pXStateR3->x87.aXMM[iReg].uXmm,
383 RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u256.DQWords.dqw0)));
384 RTUInt128AssignOr(&pVCpu->cpum.s.Guest.pXStateR3->u.YmmHi.aYmmHi[iReg].uXmm,
385 RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
386
387 }
388 return VERR_NOT_IMPLEMENTED;
389}
390
391
392/*
393 *
394 * Guest register access functions.
395 *
396 */
397
398/**
399 * @interface_method_impl{DBGFREGDESC,pfnGet}
400 */
401static DECLCALLBACK(int) cpumR3RegGstGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
402{
403 PVMCPU pVCpu = (PVMCPU)pvUser;
404 VMCPU_ASSERT_EMT(pVCpu);
405
406 uint64_t u64Value;
407 int rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64Value);
408 if (rc == VERR_PDM_NO_APIC_INSTANCE) /* CR8 might not be available, see @bugref{8868}.*/
409 u64Value = 0;
410 else
411 AssertRCReturn(rc, rc);
412 switch (pDesc->enmType)
413 {
414 case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
415 case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
416 default:
417 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
418 }
419 return VINF_SUCCESS;
420}
421
422
423/**
424 * @interface_method_impl{DBGFREGDESC,pfnGet}
425 */
426static DECLCALLBACK(int) cpumR3RegGstSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
427{
428 int rc;
429 PVMCPU pVCpu = (PVMCPU)pvUser;
430
431 VMCPU_ASSERT_EMT(pVCpu);
432
433 /*
434 * Calculate the new value.
435 */
436 uint64_t u64Value;
437 uint64_t fMask;
438 uint64_t fMaskMax;
439 switch (pDesc->enmType)
440 {
441 case DBGFREGVALTYPE_U64:
442 u64Value = pValue->u64;
443 fMask = pfMask->u64;
444 fMaskMax = UINT64_MAX;
445 break;
446 case DBGFREGVALTYPE_U32:
447 u64Value = pValue->u32;
448 fMask = pfMask->u32;
449 fMaskMax = UINT32_MAX;
450 break;
451 default:
452 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
453 }
454 if (fMask != fMaskMax)
455 {
456 uint64_t u64FullValue;
457 rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64FullValue);
458 if (RT_FAILURE(rc))
459 return rc;
460 u64Value = (u64FullValue & ~fMask)
461 | (u64Value & fMask);
462 }
463
464 /*
465 * Perform the assignment.
466 */
467 switch (pDesc->offRegister)
468 {
469 case 0: rc = CPUMSetGuestCR0(pVCpu, u64Value); break;
470 case 2: rc = CPUMSetGuestCR2(pVCpu, u64Value); break;
471 case 3: rc = CPUMSetGuestCR3(pVCpu, u64Value); break;
472 case 4: rc = CPUMSetGuestCR4(pVCpu, u64Value); break;
473 case 8: rc = APICSetTpr(pVCpu, (uint8_t)(u64Value << 4)); break;
474 default:
475 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
476 }
477 return rc;
478}
479
480
481/**
482 * @interface_method_impl{DBGFREGDESC,pfnGet}
483 */
484static DECLCALLBACK(int) cpumR3RegGstGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
485{
486 PVMCPU pVCpu = (PVMCPU)pvUser;
487 VMCPU_ASSERT_EMT(pVCpu);
488
489 uint64_t u64Value;
490 int rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64Value);
491 AssertRCReturn(rc, rc);
492 switch (pDesc->enmType)
493 {
494 case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
495 case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
496 default:
497 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
498 }
499 return VINF_SUCCESS;
500}
501
502
503/**
504 * @interface_method_impl{DBGFREGDESC,pfnGet}
505 */
506static DECLCALLBACK(int) cpumR3RegGstSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
507{
508 int rc;
509 PVMCPU pVCpu = (PVMCPU)pvUser;
510
511 VMCPU_ASSERT_EMT(pVCpu);
512
513 /*
514 * Calculate the new value.
515 */
516 uint64_t u64Value;
517 uint64_t fMask;
518 uint64_t fMaskMax;
519 switch (pDesc->enmType)
520 {
521 case DBGFREGVALTYPE_U64:
522 u64Value = pValue->u64;
523 fMask = pfMask->u64;
524 fMaskMax = UINT64_MAX;
525 break;
526 case DBGFREGVALTYPE_U32:
527 u64Value = pValue->u32;
528 fMask = pfMask->u32;
529 fMaskMax = UINT32_MAX;
530 break;
531 default:
532 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
533 }
534 if (fMask != fMaskMax)
535 {
536 uint64_t u64FullValue;
537 rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64FullValue);
538 if (RT_FAILURE(rc))
539 return rc;
540 u64Value = (u64FullValue & ~fMask)
541 | (u64Value & fMask);
542 }
543
544 /*
545 * Perform the assignment.
546 */
547 return CPUMSetGuestDRx(pVCpu, pDesc->offRegister, u64Value);
548}
549
550
551/**
552 * @interface_method_impl{DBGFREGDESC,pfnGet}
553 */
554static DECLCALLBACK(int) cpumR3RegGstGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
555{
556 PVMCPU pVCpu = (PVMCPU)pvUser;
557 VMCPU_ASSERT_EMT(pVCpu);
558
559 uint64_t u64Value;
560 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64Value);
561 if (rcStrict == VINF_SUCCESS)
562 {
563 switch (pDesc->enmType)
564 {
565 case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
566 case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
567 case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
568 default:
569 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
570 }
571 return VBOXSTRICTRC_VAL(rcStrict);
572 }
573
574 /** @todo what to do about errors? */
575 Assert(RT_FAILURE_NP(rcStrict));
576 return VBOXSTRICTRC_VAL(rcStrict);
577}
578
579
580/**
581 * @interface_method_impl{DBGFREGDESC,pfnGet}
582 */
583static DECLCALLBACK(int) cpumR3RegGstSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
584{
585 PVMCPU pVCpu = (PVMCPU)pvUser;
586
587 VMCPU_ASSERT_EMT(pVCpu);
588
589 /*
590 * Calculate the new value.
591 */
592 uint64_t u64Value;
593 uint64_t fMask;
594 uint64_t fMaskMax;
595 switch (pDesc->enmType)
596 {
597 case DBGFREGVALTYPE_U64:
598 u64Value = pValue->u64;
599 fMask = pfMask->u64;
600 fMaskMax = UINT64_MAX;
601 break;
602 case DBGFREGVALTYPE_U32:
603 u64Value = pValue->u32;
604 fMask = pfMask->u32;
605 fMaskMax = UINT32_MAX;
606 break;
607 case DBGFREGVALTYPE_U16:
608 u64Value = pValue->u16;
609 fMask = pfMask->u16;
610 fMaskMax = UINT16_MAX;
611 break;
612 default:
613 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
614 }
615 if (fMask != fMaskMax)
616 {
617 uint64_t u64FullValue;
618 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64FullValue);
619 if (rcStrict != VINF_SUCCESS)
620 {
621 AssertRC(RT_FAILURE_NP(rcStrict));
622 return VBOXSTRICTRC_VAL(rcStrict);
623 }
624 u64Value = (u64FullValue & ~fMask)
625 | (u64Value & fMask);
626 }
627
628 /*
629 * Perform the assignment.
630 */
631 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pDesc->offRegister, u64Value);
632 if (rcStrict == VINF_SUCCESS)
633 return VINF_SUCCESS;
634 AssertRC(RT_FAILURE_NP(rcStrict));
635 return VBOXSTRICTRC_VAL(rcStrict);
636}
637
638
639/**
640 * @interface_method_impl{DBGFREGDESC,pfnGet}
641 */
642static DECLCALLBACK(int) cpumR3RegGstGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
643{
644 PVMCPU pVCpu = (PVMCPU)pvUser;
645 VMCPU_ASSERT_EMT(pVCpu);
646 Assert(pDesc->enmType == DBGFREGVALTYPE_R80);
647
648 PX86FXSTATE pFpuCtx = &pVCpu->cpum.s.Guest.CTX_SUFF(pXState)->x87;
649 unsigned iReg = (pFpuCtx->FSW >> 11) & 7;
650 iReg += pDesc->offRegister;
651 iReg &= 7;
652 pValue->r80Ex = pFpuCtx->aRegs[iReg].r80Ex;
653
654 return VINF_SUCCESS;
655}
656
657
658/**
659 * @interface_method_impl{DBGFREGDESC,pfnGet}
660 */
661static DECLCALLBACK(int) cpumR3RegGstSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
662{
663 NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
664 return VERR_NOT_IMPLEMENTED;
665}
666
667
668
669/*
670 *
671 * Hypervisor register access functions.
672 *
673 */
674
675/**
676 * @interface_method_impl{DBGFREGDESC,pfnGet}
677 */
678static DECLCALLBACK(int) cpumR3RegHyperGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
679{
680 PVMCPU pVCpu = (PVMCPU)pvUser;
681 VMCPU_ASSERT_EMT(pVCpu);
682
683 uint64_t u64Value;
684 switch (pDesc->offRegister)
685 {
686 case 0: u64Value = CPUMGetHyperDR0(pVCpu); break;
687 case 1: u64Value = CPUMGetHyperDR1(pVCpu); break;
688 case 2: u64Value = CPUMGetHyperDR2(pVCpu); break;
689 case 3: u64Value = CPUMGetHyperDR3(pVCpu); break;
690 case 6: u64Value = CPUMGetHyperDR6(pVCpu); break;
691 case 7: u64Value = CPUMGetHyperDR7(pVCpu); break;
692 default:
693 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
694 }
695 switch (pDesc->enmType)
696 {
697 case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
698 case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
699 default:
700 AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);
701 }
702 return VINF_SUCCESS;
703}
704
705
706/**
707 * @interface_method_impl{DBGFREGDESC,pfnGet}
708 */
709static DECLCALLBACK(int) cpumR3RegHyperSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
710{
711 /* Not settable, prevents killing your host. */
712 NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask);
713 return VERR_ACCESS_DENIED;
714}
715
716
717/*
718 * Set up aliases.
719 */
720#define CPUMREGALIAS_STD(Name, psz32, psz16, psz8) \
721 static DBGFREGALIAS const g_aCpumRegAliases_##Name[] = \
722 { \
723 { psz32, DBGFREGVALTYPE_U32 }, \
724 { psz16, DBGFREGVALTYPE_U16 }, \
725 { psz8, DBGFREGVALTYPE_U8 }, \
726 { NULL, DBGFREGVALTYPE_INVALID } \
727 }
728CPUMREGALIAS_STD(rax, "eax", "ax", "al");
729CPUMREGALIAS_STD(rcx, "ecx", "cx", "cl");
730CPUMREGALIAS_STD(rdx, "edx", "dx", "dl");
731CPUMREGALIAS_STD(rbx, "ebx", "bx", "bl");
732CPUMREGALIAS_STD(rsp, "esp", "sp", NULL);
733CPUMREGALIAS_STD(rbp, "ebp", "bp", NULL);
734CPUMREGALIAS_STD(rsi, "esi", "si", "sil");
735CPUMREGALIAS_STD(rdi, "edi", "di", "dil");
736CPUMREGALIAS_STD(r8, "r8d", "r8w", "r8b");
737CPUMREGALIAS_STD(r9, "r9d", "r9w", "r9b");
738CPUMREGALIAS_STD(r10, "r10d", "r10w", "r10b");
739CPUMREGALIAS_STD(r11, "r11d", "r11w", "r11b");
740CPUMREGALIAS_STD(r12, "r12d", "r12w", "r12b");
741CPUMREGALIAS_STD(r13, "r13d", "r13w", "r13b");
742CPUMREGALIAS_STD(r14, "r14d", "r14w", "r14b");
743CPUMREGALIAS_STD(r15, "r15d", "r15w", "r15b");
744CPUMREGALIAS_STD(rip, "eip", "ip", NULL);
745CPUMREGALIAS_STD(rflags, "eflags", "flags", NULL);
746#undef CPUMREGALIAS_STD
747
748static DBGFREGALIAS const g_aCpumRegAliases_fpuip[] =
749{
750 { "fpuip16", DBGFREGVALTYPE_U16 },
751 { NULL, DBGFREGVALTYPE_INVALID }
752};
753
754static DBGFREGALIAS const g_aCpumRegAliases_fpudp[] =
755{
756 { "fpudp16", DBGFREGVALTYPE_U16 },
757 { NULL, DBGFREGVALTYPE_INVALID }
758};
759
760static DBGFREGALIAS const g_aCpumRegAliases_cr0[] =
761{
762 { "msw", DBGFREGVALTYPE_U16 },
763 { NULL, DBGFREGVALTYPE_INVALID }
764};
765
766/*
767 * Sub fields.
768 */
769/** Sub-fields for the (hidden) segment attribute register. */
770static DBGFREGSUBFIELD const g_aCpumRegFields_seg[] =
771{
772 DBGFREGSUBFIELD_RW("type", 0, 4, 0),
773 DBGFREGSUBFIELD_RW("s", 4, 1, 0),
774 DBGFREGSUBFIELD_RW("dpl", 5, 2, 0),
775 DBGFREGSUBFIELD_RW("p", 7, 1, 0),
776 DBGFREGSUBFIELD_RW("avl", 12, 1, 0),
777 DBGFREGSUBFIELD_RW("l", 13, 1, 0),
778 DBGFREGSUBFIELD_RW("d", 14, 1, 0),
779 DBGFREGSUBFIELD_RW("g", 15, 1, 0),
780 DBGFREGSUBFIELD_TERMINATOR()
781};
782
783/** Sub-fields for the flags register. */
784static DBGFREGSUBFIELD const g_aCpumRegFields_rflags[] =
785{
786 DBGFREGSUBFIELD_RW("cf", 0, 1, 0),
787 DBGFREGSUBFIELD_RW("pf", 2, 1, 0),
788 DBGFREGSUBFIELD_RW("af", 4, 1, 0),
789 DBGFREGSUBFIELD_RW("zf", 6, 1, 0),
790 DBGFREGSUBFIELD_RW("sf", 7, 1, 0),
791 DBGFREGSUBFIELD_RW("tf", 8, 1, 0),
792 DBGFREGSUBFIELD_RW("if", 9, 1, 0),
793 DBGFREGSUBFIELD_RW("df", 10, 1, 0),
794 DBGFREGSUBFIELD_RW("of", 11, 1, 0),
795 DBGFREGSUBFIELD_RW("iopl", 12, 2, 0),
796 DBGFREGSUBFIELD_RW("nt", 14, 1, 0),
797 DBGFREGSUBFIELD_RW("rf", 16, 1, 0),
798 DBGFREGSUBFIELD_RW("vm", 17, 1, 0),
799 DBGFREGSUBFIELD_RW("ac", 18, 1, 0),
800 DBGFREGSUBFIELD_RW("vif", 19, 1, 0),
801 DBGFREGSUBFIELD_RW("vip", 20, 1, 0),
802 DBGFREGSUBFIELD_RW("id", 21, 1, 0),
803 DBGFREGSUBFIELD_TERMINATOR()
804};
805
806/** Sub-fields for the FPU control word register. */
807static DBGFREGSUBFIELD const g_aCpumRegFields_fcw[] =
808{
809 DBGFREGSUBFIELD_RW("im", 1, 1, 0),
810 DBGFREGSUBFIELD_RW("dm", 2, 1, 0),
811 DBGFREGSUBFIELD_RW("zm", 3, 1, 0),
812 DBGFREGSUBFIELD_RW("om", 4, 1, 0),
813 DBGFREGSUBFIELD_RW("um", 5, 1, 0),
814 DBGFREGSUBFIELD_RW("pm", 6, 1, 0),
815 DBGFREGSUBFIELD_RW("pc", 8, 2, 0),
816 DBGFREGSUBFIELD_RW("rc", 10, 2, 0),
817 DBGFREGSUBFIELD_RW("x", 12, 1, 0),
818 DBGFREGSUBFIELD_TERMINATOR()
819};
820
821/** Sub-fields for the FPU status word register. */
822static DBGFREGSUBFIELD const g_aCpumRegFields_fsw[] =
823{
824 DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
825 DBGFREGSUBFIELD_RW("de", 1, 1, 0),
826 DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
827 DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
828 DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
829 DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
830 DBGFREGSUBFIELD_RW("se", 6, 1, 0),
831 DBGFREGSUBFIELD_RW("es", 7, 1, 0),
832 DBGFREGSUBFIELD_RW("c0", 8, 1, 0),
833 DBGFREGSUBFIELD_RW("c1", 9, 1, 0),
834 DBGFREGSUBFIELD_RW("c2", 10, 1, 0),
835 DBGFREGSUBFIELD_RW("top", 11, 3, 0),
836 DBGFREGSUBFIELD_RW("c3", 14, 1, 0),
837 DBGFREGSUBFIELD_RW("b", 15, 1, 0),
838 DBGFREGSUBFIELD_TERMINATOR()
839};
840
841/** Sub-fields for the FPU tag word register. */
842static DBGFREGSUBFIELD const g_aCpumRegFields_ftw[] =
843{
844 DBGFREGSUBFIELD_RW("tag0", 0, 2, 0),
845 DBGFREGSUBFIELD_RW("tag1", 2, 2, 0),
846 DBGFREGSUBFIELD_RW("tag2", 4, 2, 0),
847 DBGFREGSUBFIELD_RW("tag3", 6, 2, 0),
848 DBGFREGSUBFIELD_RW("tag4", 8, 2, 0),
849 DBGFREGSUBFIELD_RW("tag5", 10, 2, 0),
850 DBGFREGSUBFIELD_RW("tag6", 12, 2, 0),
851 DBGFREGSUBFIELD_RW("tag7", 14, 2, 0),
852 DBGFREGSUBFIELD_TERMINATOR()
853};
854
855/** Sub-fields for the Multimedia Extensions Control and Status Register. */
856static DBGFREGSUBFIELD const g_aCpumRegFields_mxcsr[] =
857{
858 DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
859 DBGFREGSUBFIELD_RW("de", 1, 1, 0),
860 DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
861 DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
862 DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
863 DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
864 DBGFREGSUBFIELD_RW("daz", 6, 1, 0),
865 DBGFREGSUBFIELD_RW("im", 7, 1, 0),
866 DBGFREGSUBFIELD_RW("dm", 8, 1, 0),
867 DBGFREGSUBFIELD_RW("zm", 9, 1, 0),
868 DBGFREGSUBFIELD_RW("om", 10, 1, 0),
869 DBGFREGSUBFIELD_RW("um", 11, 1, 0),
870 DBGFREGSUBFIELD_RW("pm", 12, 1, 0),
871 DBGFREGSUBFIELD_RW("rc", 13, 2, 0),
872 DBGFREGSUBFIELD_RW("fz", 14, 1, 0),
873 DBGFREGSUBFIELD_TERMINATOR()
874};
875
876/** Sub-fields for the FPU tag word register. */
877static DBGFREGSUBFIELD const g_aCpumRegFields_stN[] =
878{
879 DBGFREGSUBFIELD_RW("man", 0, 64, 0),
880 DBGFREGSUBFIELD_RW("exp", 64, 15, 0),
881 DBGFREGSUBFIELD_RW("sig", 79, 1, 0),
882 DBGFREGSUBFIELD_TERMINATOR()
883};
884
885/** Sub-fields for the MMX registers. */
886static DBGFREGSUBFIELD const g_aCpumRegFields_mmN[] =
887{
888 DBGFREGSUBFIELD_RW("dw0", 0, 32, 0),
889 DBGFREGSUBFIELD_RW("dw1", 32, 32, 0),
890 DBGFREGSUBFIELD_RW("w0", 0, 16, 0),
891 DBGFREGSUBFIELD_RW("w1", 16, 16, 0),
892 DBGFREGSUBFIELD_RW("w2", 32, 16, 0),
893 DBGFREGSUBFIELD_RW("w3", 48, 16, 0),
894 DBGFREGSUBFIELD_RW("b0", 0, 8, 0),
895 DBGFREGSUBFIELD_RW("b1", 8, 8, 0),
896 DBGFREGSUBFIELD_RW("b2", 16, 8, 0),
897 DBGFREGSUBFIELD_RW("b3", 24, 8, 0),
898 DBGFREGSUBFIELD_RW("b4", 32, 8, 0),
899 DBGFREGSUBFIELD_RW("b5", 40, 8, 0),
900 DBGFREGSUBFIELD_RW("b6", 48, 8, 0),
901 DBGFREGSUBFIELD_RW("b7", 56, 8, 0),
902 DBGFREGSUBFIELD_TERMINATOR()
903};
904
905/** Sub-fields for the XMM registers. */
906static DBGFREGSUBFIELD const g_aCpumRegFields_xmmN[] =
907{
908 DBGFREGSUBFIELD_RW("r0", 0, 32, 0),
909 DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0),
910 DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0),
911 DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0),
912 DBGFREGSUBFIELD_RW("r1", 32, 32, 0),
913 DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0),
914 DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0),
915 DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0),
916 DBGFREGSUBFIELD_RW("r2", 64, 32, 0),
917 DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0),
918 DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0),
919 DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0),
920 DBGFREGSUBFIELD_RW("r3", 96, 32, 0),
921 DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0),
922 DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0),
923 DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0),
924 DBGFREGSUBFIELD_TERMINATOR()
925};
926
927#if 0 /* needs special accessor, too lazy for that now. */
928/** Sub-fields for the YMM registers. */
929static DBGFREGSUBFIELD const g_aCpumRegFields_ymmN[] =
930{
931 DBGFREGSUBFIELD_RW("r0", 0, 32, 0),
932 DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0),
933 DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0),
934 DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0),
935 DBGFREGSUBFIELD_RW("r1", 32, 32, 0),
936 DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0),
937 DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0),
938 DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0),
939 DBGFREGSUBFIELD_RW("r2", 64, 32, 0),
940 DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0),
941 DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0),
942 DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0),
943 DBGFREGSUBFIELD_RW("r3", 96, 32, 0),
944 DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0),
945 DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0),
946 DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0),
947 DBGFREGSUBFIELD_RW("r4", 128, 32, 0),
948 DBGFREGSUBFIELD_RW("r4.man", 128+ 0, 23, 0),
949 DBGFREGSUBFIELD_RW("r4.exp", 128+23, 8, 0),
950 DBGFREGSUBFIELD_RW("r4.sig", 128+31, 1, 0),
951 DBGFREGSUBFIELD_RW("r5", 160, 32, 0),
952 DBGFREGSUBFIELD_RW("r5.man", 160+ 0, 23, 0),
953 DBGFREGSUBFIELD_RW("r5.exp", 160+23, 8, 0),
954 DBGFREGSUBFIELD_RW("r5.sig", 160+31, 1, 0),
955 DBGFREGSUBFIELD_RW("r6", 192, 32, 0),
956 DBGFREGSUBFIELD_RW("r6.man", 192+ 0, 23, 0),
957 DBGFREGSUBFIELD_RW("r6.exp", 192+23, 8, 0),
958 DBGFREGSUBFIELD_RW("r6.sig", 192+31, 1, 0),
959 DBGFREGSUBFIELD_RW("r7", 224, 32, 0),
960 DBGFREGSUBFIELD_RW("r7.man", 224+ 0, 23, 0),
961 DBGFREGSUBFIELD_RW("r7.exp", 224+23, 8, 0),
962 DBGFREGSUBFIELD_RW("r7.sig", 224+31, 1, 0),
963 DBGFREGSUBFIELD_TERMINATOR()
964};
965#endif
966
967/** Sub-fields for the CR0 register. */
968static DBGFREGSUBFIELD const g_aCpumRegFields_cr0[] =
969{
970 DBGFREGSUBFIELD_RW("pe", 0, 1, 0),
971 DBGFREGSUBFIELD_RW("mp", 1, 1, 0),
972 DBGFREGSUBFIELD_RW("em", 2, 1, 0),
973 DBGFREGSUBFIELD_RW("ts", 3, 1, 0),
974 DBGFREGSUBFIELD_RO("et", 4, 1, 0),
975 DBGFREGSUBFIELD_RW("ne", 5, 1, 0),
976 DBGFREGSUBFIELD_RW("wp", 16, 1, 0),
977 DBGFREGSUBFIELD_RW("am", 18, 1, 0),
978 DBGFREGSUBFIELD_RW("nw", 29, 1, 0),
979 DBGFREGSUBFIELD_RW("cd", 30, 1, 0),
980 DBGFREGSUBFIELD_RW("pg", 31, 1, 0),
981 DBGFREGSUBFIELD_TERMINATOR()
982};
983
984/** Sub-fields for the CR3 register. */
985static DBGFREGSUBFIELD const g_aCpumRegFields_cr3[] =
986{
987 DBGFREGSUBFIELD_RW("pwt", 3, 1, 0),
988 DBGFREGSUBFIELD_RW("pcd", 4, 1, 0),
989 DBGFREGSUBFIELD_TERMINATOR()
990};
991
992/** Sub-fields for the CR4 register. */
993static DBGFREGSUBFIELD const g_aCpumRegFields_cr4[] =
994{
995 DBGFREGSUBFIELD_RW("vme", 0, 1, 0),
996 DBGFREGSUBFIELD_RW("pvi", 1, 1, 0),
997 DBGFREGSUBFIELD_RW("tsd", 2, 1, 0),
998 DBGFREGSUBFIELD_RW("de", 3, 1, 0),
999 DBGFREGSUBFIELD_RW("pse", 4, 1, 0),
1000 DBGFREGSUBFIELD_RW("pae", 5, 1, 0),
1001 DBGFREGSUBFIELD_RW("mce", 6, 1, 0),
1002 DBGFREGSUBFIELD_RW("pge", 7, 1, 0),
1003 DBGFREGSUBFIELD_RW("pce", 8, 1, 0),
1004 DBGFREGSUBFIELD_RW("osfxsr", 9, 1, 0),
1005 DBGFREGSUBFIELD_RW("osxmmeexcpt", 10, 1, 0),
1006 DBGFREGSUBFIELD_RW("vmxe", 13, 1, 0),
1007 DBGFREGSUBFIELD_RW("smxe", 14, 1, 0),
1008 DBGFREGSUBFIELD_RW("pcide", 17, 1, 0),
1009 DBGFREGSUBFIELD_RW("osxsave", 18, 1, 0),
1010 DBGFREGSUBFIELD_RW("smep", 20, 1, 0),
1011 DBGFREGSUBFIELD_RW("smap", 21, 1, 0),
1012 DBGFREGSUBFIELD_TERMINATOR()
1013};
1014
1015/** Sub-fields for the DR6 register. */
1016static DBGFREGSUBFIELD const g_aCpumRegFields_dr6[] =
1017{
1018 DBGFREGSUBFIELD_RW("b0", 0, 1, 0),
1019 DBGFREGSUBFIELD_RW("b1", 1, 1, 0),
1020 DBGFREGSUBFIELD_RW("b2", 2, 1, 0),
1021 DBGFREGSUBFIELD_RW("b3", 3, 1, 0),
1022 DBGFREGSUBFIELD_RW("bd", 13, 1, 0),
1023 DBGFREGSUBFIELD_RW("bs", 14, 1, 0),
1024 DBGFREGSUBFIELD_RW("bt", 15, 1, 0),
1025 DBGFREGSUBFIELD_TERMINATOR()
1026};
1027
1028/** Sub-fields for the DR7 register. */
1029static DBGFREGSUBFIELD const g_aCpumRegFields_dr7[] =
1030{
1031 DBGFREGSUBFIELD_RW("l0", 0, 1, 0),
1032 DBGFREGSUBFIELD_RW("g0", 1, 1, 0),
1033 DBGFREGSUBFIELD_RW("l1", 2, 1, 0),
1034 DBGFREGSUBFIELD_RW("g1", 3, 1, 0),
1035 DBGFREGSUBFIELD_RW("l2", 4, 1, 0),
1036 DBGFREGSUBFIELD_RW("g2", 5, 1, 0),
1037 DBGFREGSUBFIELD_RW("l3", 6, 1, 0),
1038 DBGFREGSUBFIELD_RW("g3", 7, 1, 0),
1039 DBGFREGSUBFIELD_RW("le", 8, 1, 0),
1040 DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
1041 DBGFREGSUBFIELD_RW("gd", 13, 1, 0),
1042 DBGFREGSUBFIELD_RW("rw0", 16, 2, 0),
1043 DBGFREGSUBFIELD_RW("len0", 18, 2, 0),
1044 DBGFREGSUBFIELD_RW("rw1", 20, 2, 0),
1045 DBGFREGSUBFIELD_RW("len1", 22, 2, 0),
1046 DBGFREGSUBFIELD_RW("rw2", 24, 2, 0),
1047 DBGFREGSUBFIELD_RW("len2", 26, 2, 0),
1048 DBGFREGSUBFIELD_RW("rw3", 28, 2, 0),
1049 DBGFREGSUBFIELD_RW("len3", 30, 2, 0),
1050 DBGFREGSUBFIELD_TERMINATOR()
1051};
1052
1053/** Sub-fields for the CR_PAT MSR. */
1054static DBGFREGSUBFIELD const g_aCpumRegFields_apic_base[] =
1055{
1056 DBGFREGSUBFIELD_RW("bsp", 8, 1, 0),
1057 DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
1058 DBGFREGSUBFIELD_RW("base", 12, 20, 12),
1059 DBGFREGSUBFIELD_TERMINATOR()
1060};
1061
1062/** Sub-fields for the CR_PAT MSR. */
1063static DBGFREGSUBFIELD const g_aCpumRegFields_cr_pat[] =
1064{
1065 /** @todo */
1066 DBGFREGSUBFIELD_TERMINATOR()
1067};
1068
1069/** Sub-fields for the PERF_STATUS MSR. */
1070static DBGFREGSUBFIELD const g_aCpumRegFields_perf_status[] =
1071{
1072 /** @todo */
1073 DBGFREGSUBFIELD_TERMINATOR()
1074};
1075
1076/** Sub-fields for the EFER MSR. */
1077static DBGFREGSUBFIELD const g_aCpumRegFields_efer[] =
1078{
1079 /** @todo */
1080 DBGFREGSUBFIELD_TERMINATOR()
1081};
1082
1083/** Sub-fields for the STAR MSR. */
1084static DBGFREGSUBFIELD const g_aCpumRegFields_star[] =
1085{
1086 /** @todo */
1087 DBGFREGSUBFIELD_TERMINATOR()
1088};
1089
1090/** Sub-fields for the CSTAR MSR. */
1091static DBGFREGSUBFIELD const g_aCpumRegFields_cstar[] =
1092{
1093 /** @todo */
1094 DBGFREGSUBFIELD_TERMINATOR()
1095};
1096
1097/** Sub-fields for the LSTAR MSR. */
1098static DBGFREGSUBFIELD const g_aCpumRegFields_lstar[] =
1099{
1100 /** @todo */
1101 DBGFREGSUBFIELD_TERMINATOR()
1102};
1103
1104#if 0 /** @todo */
1105/** Sub-fields for the SF_MASK MSR. */
1106static DBGFREGSUBFIELD const g_aCpumRegFields_sf_mask[] =
1107{
1108 /** @todo */
1109 DBGFREGSUBFIELD_TERMINATOR()
1110};
1111#endif
1112
1113
1114/** @name Macros for producing register descriptor table entries.
1115 * @{ */
1116#define CPU_REG_EX_AS(a_szName, a_RegSuff, a_TypeSuff, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1117 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1118
1119#define CPU_REG_REG(UName, LName) \
1120 CPU_REG_RW_AS(#LName, UName, U64, LName, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_##LName, NULL)
1121
1122#define CPU_REG_SEG(UName, LName) \
1123 CPU_REG_RW_AS(#LName, UName, U16, LName.Sel, cpumR3RegGet_Generic, cpumR3RegSet_seg, NULL, NULL ), \
1124 CPU_REG_RW_AS(#LName "_attr", UName##_ATTR, U32, LName.Attr.u, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_seg), \
1125 CPU_REG_RW_AS(#LName "_base", UName##_BASE, U64, LName.u64Base, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), \
1126 CPU_REG_RW_AS(#LName "_lim", UName##_LIMIT, U32, LName.u32Limit, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL )
1127
1128#define CPU_REG_MM(n) \
1129 CPU_REG_XS_RW_AS("mm" #n, MM##n, U64, x87.aRegs[n].mmx, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mmN)
1130
1131#define CPU_REG_XMM(n) \
1132 CPU_REG_XS_RW_AS("xmm" #n, XMM##n, U128, x87.aXMM[n].xmm, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_xmmN)
1133
1134#define CPU_REG_YMM(n) \
1135 { "ymm" #n, DBGFREG_YMM##n, DBGFREGVALTYPE_U256, 0 /*fFlags*/, n, cpumR3RegGet_ymm, cpumR3RegSet_ymm, NULL /*paAliases*/, NULL /*paSubFields*/ }
1136
1137/** @} */
1138
1139
1140/**
1141 * The guest register descriptors.
1142 */
1143static DBGFREGDESC const g_aCpumRegGstDescs[] =
1144{
1145#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1146 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1147#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1148 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1149#define CPU_REG_XS_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_XStateMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1150 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, RT_OFFSETOF(X86XSAVEAREA, a_XStateMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1151#define CPU_REG_XS_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_XStateMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
1152 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(X86XSAVEAREA, a_XStateMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
1153#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
1154 CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegGstGet_msr, cpumR3RegGstSet_msr, NULL, a_paSubFields)
1155#define CPU_REG_ST(n) \
1156 CPU_REG_EX_AS("st" #n, ST##n, R80, n, cpumR3RegGstGet_stN, cpumR3RegGstSet_stN, NULL, g_aCpumRegFields_stN)
1157
1158 CPU_REG_REG(RAX, rax),
1159 CPU_REG_REG(RCX, rcx),
1160 CPU_REG_REG(RDX, rdx),
1161 CPU_REG_REG(RBX, rbx),
1162 CPU_REG_REG(RSP, rsp),
1163 CPU_REG_REG(RBP, rbp),
1164 CPU_REG_REG(RSI, rsi),
1165 CPU_REG_REG(RDI, rdi),
1166 CPU_REG_REG(R8, r8),
1167 CPU_REG_REG(R9, r9),
1168 CPU_REG_REG(R10, r10),
1169 CPU_REG_REG(R11, r11),
1170 CPU_REG_REG(R12, r12),
1171 CPU_REG_REG(R13, r13),
1172 CPU_REG_REG(R14, r14),
1173 CPU_REG_REG(R15, r15),
1174 CPU_REG_SEG(CS, cs),
1175 CPU_REG_SEG(DS, ds),
1176 CPU_REG_SEG(ES, es),
1177 CPU_REG_SEG(FS, fs),
1178 CPU_REG_SEG(GS, gs),
1179 CPU_REG_SEG(SS, ss),
1180 CPU_REG_REG(RIP, rip),
1181 CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
1182 CPU_REG_XS_RW_AS("fcw", FCW, U16, x87.FCW, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_fcw ),
1183 CPU_REG_XS_RW_AS("fsw", FSW, U16, x87.FSW, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_fsw ),
1184 CPU_REG_XS_RO_AS("ftw", FTW, U16, x87, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ),
1185 CPU_REG_XS_RW_AS("fop", FOP, U16, x87.FOP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
1186 CPU_REG_XS_RW_AS("fpuip", FPUIP, U32, x87.FPUIP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, g_aCpumRegAliases_fpuip, NULL ),
1187 CPU_REG_XS_RW_AS("fpucs", FPUCS, U16, x87.CS, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
1188 CPU_REG_XS_RW_AS("fpudp", FPUDP, U32, x87.FPUDP, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, g_aCpumRegAliases_fpudp, NULL ),
1189 CPU_REG_XS_RW_AS("fpuds", FPUDS, U16, x87.DS, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, NULL ),
1190 CPU_REG_XS_RW_AS("mxcsr", MXCSR, U32, x87.MXCSR, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mxcsr ),
1191 CPU_REG_XS_RW_AS("mxcsr_mask", MXCSR_MASK, U32, x87.MXCSR_MASK, cpumR3RegGet_XStateGeneric, cpumR3RegSet_XStateGeneric, NULL, g_aCpumRegFields_mxcsr ),
1192 CPU_REG_ST(0),
1193 CPU_REG_ST(1),
1194 CPU_REG_ST(2),
1195 CPU_REG_ST(3),
1196 CPU_REG_ST(4),
1197 CPU_REG_ST(5),
1198 CPU_REG_ST(6),
1199 CPU_REG_ST(7),
1200 CPU_REG_MM(0),
1201 CPU_REG_MM(1),
1202 CPU_REG_MM(2),
1203 CPU_REG_MM(3),
1204 CPU_REG_MM(4),
1205 CPU_REG_MM(5),
1206 CPU_REG_MM(6),
1207 CPU_REG_MM(7),
1208 CPU_REG_XMM(0),
1209 CPU_REG_XMM(1),
1210 CPU_REG_XMM(2),
1211 CPU_REG_XMM(3),
1212 CPU_REG_XMM(4),
1213 CPU_REG_XMM(5),
1214 CPU_REG_XMM(6),
1215 CPU_REG_XMM(7),
1216 CPU_REG_XMM(8),
1217 CPU_REG_XMM(9),
1218 CPU_REG_XMM(10),
1219 CPU_REG_XMM(11),
1220 CPU_REG_XMM(12),
1221 CPU_REG_XMM(13),
1222 CPU_REG_XMM(14),
1223 CPU_REG_XMM(15),
1224 CPU_REG_YMM(0),
1225 CPU_REG_YMM(1),
1226 CPU_REG_YMM(2),
1227 CPU_REG_YMM(3),
1228 CPU_REG_YMM(4),
1229 CPU_REG_YMM(5),
1230 CPU_REG_YMM(6),
1231 CPU_REG_YMM(7),
1232 CPU_REG_YMM(8),
1233 CPU_REG_YMM(9),
1234 CPU_REG_YMM(10),
1235 CPU_REG_YMM(11),
1236 CPU_REG_YMM(12),
1237 CPU_REG_YMM(13),
1238 CPU_REG_YMM(14),
1239 CPU_REG_YMM(15),
1240 CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1241 CPU_REG_RW_AS("gdtr_lim", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1242 CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1243 CPU_REG_RW_AS("idtr_lim", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1244 CPU_REG_SEG(LDTR, ldtr),
1245 CPU_REG_SEG(TR, tr),
1246 CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
1247 CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1248 CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr3 ),
1249 CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr4 ),
1250 CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ),
1251 CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1252 CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1253 CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1254 CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ),
1255 CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr6 ),
1256 CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr7 ),
1257 CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
1258 CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
1259 CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
1260 CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
1261 CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ),
1262 CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ),
1263 CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ),
1264 CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
1265 CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
1266 CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
1267 CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
1268 CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
1269 CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
1270 CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
1271 CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
1272 CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
1273 CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Guest.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1274 CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Guest.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1275 CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Guest.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1276 CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Guest.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
1277 CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
1278 CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
1279 DBGFREGDESC_TERMINATOR()
1280
1281#undef CPU_REG_RW_AS
1282#undef CPU_REG_RO_AS
1283#undef CPU_REG_MSR
1284#undef CPU_REG_ST
1285};
1286
1287
1288/**
1289 * The hypervisor (raw-mode) register descriptors.
1290 */
1291static DBGFREGDESC const g_aCpumRegHyperDescs[] =
1292{
1293 CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1294 CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1295 CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1296 CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ),
1297 CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr6 ),
1298 CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr7 ),
1299 DBGFREGDESC_TERMINATOR()
1300};
1301
1302
1303/**
1304 * Initializes the debugger related sides of the CPUM component.
1305 *
1306 * Called by CPUMR3Init.
1307 *
1308 * @returns VBox status code.
1309 * @param pVM The cross context VM structure.
1310 */
1311int cpumR3DbgInit(PVM pVM)
1312{
1313 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1314 {
1315 int rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegGstDescs, true /*fGuestRegs*/);
1316 AssertLogRelRCReturn(rc, rc);
1317 rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegHyperDescs, false /*fGuestRegs*/);
1318 AssertLogRelRCReturn(rc, rc);
1319 }
1320
1321 return VINF_SUCCESS;
1322}
1323
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