VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 55628

Last change on this file since 55628 was 55466, checked in by vboxsync, 10 years ago

CPUM: Need to save and restore the extended state stuff. duh.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 284.1 KB
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1/* $Id: CPUMR3CpuId.cpp 55466 2015-04-28 00:10:51Z vboxsync $ */
2/** @file
3 * CPUM - CPU ID part.
4 */
5
6/*
7 * Copyright (C) 2013-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_CPUM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/dbgf.h>
24#include <VBox/vmm/hm.h>
25#include <VBox/vmm/ssm.h>
26#include "CPUMInternal.h"
27#include <VBox/vmm/vm.h>
28#include <VBox/vmm/mm.h>
29
30#include <VBox/err.h>
31#include <iprt/asm-amd64-x86.h>
32#include <iprt/ctype.h>
33#include <iprt/mem.h>
34#include <iprt/string.h>
35
36
37/*******************************************************************************
38* Defined Constants And Macros *
39*******************************************************************************/
40/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
41#define CPUM_CPUID_MAX_LEAVES 2048
42
43
44/*******************************************************************************
45* Global Variables *
46*******************************************************************************/
47/**
48 * The intel pentium family.
49 */
50static const CPUMMICROARCH g_aenmIntelFamily06[] =
51{
52 /* [ 0(0x00)] = */ kCpumMicroarch_Intel_P6, /* Pentium Pro A-step (says sandpile.org). */
53 /* [ 1(0x01)] = */ kCpumMicroarch_Intel_P6, /* Pentium Pro */
54 /* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
55 /* [ 3(0x03)] = */ kCpumMicroarch_Intel_P6_II, /* PII Klamath */
56 /* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
57 /* [ 5(0x05)] = */ kCpumMicroarch_Intel_P6_II, /* PII Deschutes */
58 /* [ 6(0x06)] = */ kCpumMicroarch_Intel_P6_II, /* Celeron Mendocino. */
59 /* [ 7(0x07)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Katmai. */
60 /* [ 8(0x08)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Coppermine (includes Celeron). */
61 /* [ 9(0x09)] = */ kCpumMicroarch_Intel_P6_M_Banias, /* Pentium/Celeron M Banias. */
62 /* [10(0x0a)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Xeon */
63 /* [11(0x0b)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Tualatin (includes Celeron). */
64 /* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
65 /* [13(0x0d)] = */ kCpumMicroarch_Intel_P6_M_Dothan, /* Pentium/Celeron M Dothan. */
66 /* [14(0x0e)] = */ kCpumMicroarch_Intel_Core_Yonah, /* Core Yonah (Enhanced Pentium M). */
67 /* [15(0x0f)] = */ kCpumMicroarch_Intel_Core2_Merom, /* Merom */
68 /* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
69 /* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
70 /* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
71 /* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
72 /* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
73 /* [21(0x15)] = */ kCpumMicroarch_Intel_P6_M_Dothan, /* Tolapai - System-on-a-chip. */
74 /* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
75 /* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
76 /* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
77 /* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
78 /* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
79 /* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
80 /* [28(0x1c)] = */ kCpumMicroarch_Intel_Atom_Bonnell, /* Diamonville, Pineview, */
81 /* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
82 /* [30(0x1e)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Clarksfield, Lynnfield, Jasper Forest. */
83 /* [31(0x1f)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
84 /* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
85 /* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
86 /* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
87 /* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
88 /* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
89 /* [37(0x25)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Arrandale, Clarksdale. */
90 /* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
91 /* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
92 /* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
93 /* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
94 /* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
95 /* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
96 /* [44(0x2c)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Gulftown, Westmere-EP. */
97 /* [45(0x2d)] = */ kCpumMicroarch_Intel_Core7_SandyBridge, /* SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
98 /* [46(0x2e)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Beckton (Xeon). */
99 /* [47(0x2f)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Westmere-EX. */
100 /* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
101 /* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
102 /* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
103 /* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
104 /* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
105 /* [53(0x35)] = */ kCpumMicroarch_Intel_Atom_Saltwell, /* ?? */
106 /* [54(0x36)] = */ kCpumMicroarch_Intel_Atom_Saltwell, /* Cedarview, ++ */
107 /* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
108 /* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
109 /* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
110 /* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
111 /* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
112 /* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
113 /* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
114 /* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
115 /* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
116 /* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
117 /* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
118 /* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
119 /* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
120 /* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
121 /* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
122 /* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123 /* [71(0x47)] = */ kCpumMicroarch_Intel_Unknown,
124 /* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
125 /* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
126 /* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
127 /* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
128 /* [76(0x4c)] = */ kCpumMicroarch_Intel_Unknown,
129 /* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
130 /* [78(0x4e)] = */ kCpumMicroarch_Intel_Unknown,
131 /* [79(0x4f)] = */ kCpumMicroarch_Intel_Unknown,
132};
133
134
135
136/**
137 * Figures out the (sub-)micro architecture given a bit of CPUID info.
138 *
139 * @returns Micro architecture.
140 * @param enmVendor The CPU vendor .
141 * @param bFamily The CPU family.
142 * @param bModel The CPU model.
143 * @param bStepping The CPU stepping.
144 */
145VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
146 uint8_t bModel, uint8_t bStepping)
147{
148 if (enmVendor == CPUMCPUVENDOR_AMD)
149 {
150 switch (bFamily)
151 {
152 case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
153 case 0x03: return kCpumMicroarch_AMD_Am386;
154 case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
155 case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
156 case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
157 case 0x06:
158 switch (bModel)
159 {
160 case 0: return kCpumMicroarch_AMD_K7_Palomino;
161 case 1: return kCpumMicroarch_AMD_K7_Palomino;
162 case 2: return kCpumMicroarch_AMD_K7_Palomino;
163 case 3: return kCpumMicroarch_AMD_K7_Spitfire;
164 case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
165 case 6: return kCpumMicroarch_AMD_K7_Palomino;
166 case 7: return kCpumMicroarch_AMD_K7_Morgan;
167 case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
168 case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
169 }
170 return kCpumMicroarch_AMD_K7_Unknown;
171 case 0x0f:
172 /*
173 * This family is a friggin mess. Trying my best to make some
174 * sense out of it. Too much happened in the 0x0f family to
175 * lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
176 *
177 * Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
178 * cpu-world.com, and other places:
179 * - 130nm:
180 * - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
181 * - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
182 * - Newcastle: FC0/DH-CG (errum #180: FE0/DH-CG), FF0/DH-CG
183 * - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
184 * - Odessa: FC0/DH-CG (errum #180: FE0/DH-CG)
185 * - Paris: FF0/DH-CG, FC0/DH-CG (errum #180: FE0/DH-CG),
186 * - 90nm:
187 * - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
188 * - Oakville: 10FC0/DH-D0.
189 * - Georgetown: 10FC0/DH-D0.
190 * - Sonora: 10FC0/DH-D0.
191 * - Venus: 20F71/SH-E4
192 * - Troy: 20F51/SH-E4
193 * - Athens: 20F51/SH-E4
194 * - San Diego: 20F71/SH-E4.
195 * - Lancaster: 20F42/SH-E5
196 * - Newark: 20F42/SH-E5.
197 * - Albany: 20FC2/DH-E6.
198 * - Roma: 20FC2/DH-E6.
199 * - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
200 * - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
201 * - 90nm introducing Dual core:
202 * - Denmark: 20F30/JH-E1, 20F32/JH-E6
203 * - Italy: 20F10/JH-E1, 20F12/JH-E6
204 * - Egypt: 20F10/JH-E1, 20F12/JH-E6
205 * - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
206 * - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
207 * - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
208 * - Santa Ana: 40F32/JH-F2, /-F3
209 * - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
210 * - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
211 * - Manila: 50FF2/DH-F2, 40FF2/DH-F2
212 * - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
213 * - Keene: 40FC2/DH-F2.
214 * - Richmond: 40FC2/DH-F2
215 * - Taylor: 40F82/BH-F2
216 * - Trinidad: 40F82/BH-F2
217 *
218 * - 65nm:
219 * - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
220 * - Tyler: 60F81/BH-G1, 60F82/BH-G2.
221 * - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
222 * - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
223 * - Sherman: /-G1, 70FC2/DH-G2.
224 * - Huron: 70FF2/DH-G2.
225 */
226 if (bModel < 0x10)
227 return kCpumMicroarch_AMD_K8_130nm;
228 if (bModel >= 0x60 && bModel < 0x80)
229 return kCpumMicroarch_AMD_K8_65nm;
230 if (bModel >= 0x40)
231 return kCpumMicroarch_AMD_K8_90nm_AMDV;
232 switch (bModel)
233 {
234 case 0x21:
235 case 0x23:
236 case 0x2b:
237 case 0x2f:
238 case 0x37:
239 case 0x3f:
240 return kCpumMicroarch_AMD_K8_90nm_DualCore;
241 }
242 return kCpumMicroarch_AMD_K8_90nm;
243 case 0x10:
244 return kCpumMicroarch_AMD_K10;
245 case 0x11:
246 return kCpumMicroarch_AMD_K10_Lion;
247 case 0x12:
248 return kCpumMicroarch_AMD_K10_Llano;
249 case 0x14:
250 return kCpumMicroarch_AMD_Bobcat;
251 case 0x15:
252 switch (bModel)
253 {
254 case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
255 case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
256 case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
257 case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
258 case 0x11: /* ?? */
259 case 0x12: /* ?? */
260 case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
261 }
262 return kCpumMicroarch_AMD_15h_Unknown;
263 case 0x16:
264 return kCpumMicroarch_AMD_Jaguar;
265
266 }
267 return kCpumMicroarch_AMD_Unknown;
268 }
269
270 if (enmVendor == CPUMCPUVENDOR_INTEL)
271 {
272 switch (bFamily)
273 {
274 case 3:
275 return kCpumMicroarch_Intel_80386;
276 case 4:
277 return kCpumMicroarch_Intel_80486;
278 case 5:
279 return kCpumMicroarch_Intel_P5;
280 case 6:
281 if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
282 return g_aenmIntelFamily06[bModel];
283 return kCpumMicroarch_Intel_Atom_Unknown;
284 case 15:
285 switch (bModel)
286 {
287 case 0: return kCpumMicroarch_Intel_NB_Willamette;
288 case 1: return kCpumMicroarch_Intel_NB_Willamette;
289 case 2: return kCpumMicroarch_Intel_NB_Northwood;
290 case 3: return kCpumMicroarch_Intel_NB_Prescott;
291 case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
292 case 5: return kCpumMicroarch_Intel_NB_Unknown; /*??*/
293 case 6: return kCpumMicroarch_Intel_NB_CedarMill;
294 case 7: return kCpumMicroarch_Intel_NB_Gallatin;
295 default: return kCpumMicroarch_Intel_NB_Unknown;
296 }
297 break;
298 /* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
299 case 1:
300 return kCpumMicroarch_Intel_8086;
301 case 2:
302 return kCpumMicroarch_Intel_80286;
303 }
304 return kCpumMicroarch_Intel_Unknown;
305 }
306
307 if (enmVendor == CPUMCPUVENDOR_VIA)
308 {
309 switch (bFamily)
310 {
311 case 5:
312 switch (bModel)
313 {
314 case 1: return kCpumMicroarch_Centaur_C6;
315 case 4: return kCpumMicroarch_Centaur_C6;
316 case 8: return kCpumMicroarch_Centaur_C2;
317 case 9: return kCpumMicroarch_Centaur_C3;
318 }
319 break;
320
321 case 6:
322 switch (bModel)
323 {
324 case 5: return kCpumMicroarch_VIA_C3_M2;
325 case 6: return kCpumMicroarch_VIA_C3_C5A;
326 case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
327 case 8: return kCpumMicroarch_VIA_C3_C5N;
328 case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
329 case 10: return kCpumMicroarch_VIA_C7_C5J;
330 case 15: return kCpumMicroarch_VIA_Isaiah;
331 }
332 break;
333 }
334 return kCpumMicroarch_VIA_Unknown;
335 }
336
337 if (enmVendor == CPUMCPUVENDOR_CYRIX)
338 {
339 switch (bFamily)
340 {
341 case 4:
342 switch (bModel)
343 {
344 case 9: return kCpumMicroarch_Cyrix_5x86;
345 }
346 break;
347
348 case 5:
349 switch (bModel)
350 {
351 case 2: return kCpumMicroarch_Cyrix_M1;
352 case 4: return kCpumMicroarch_Cyrix_MediaGX;
353 case 5: return kCpumMicroarch_Cyrix_MediaGXm;
354 }
355 break;
356
357 case 6:
358 switch (bModel)
359 {
360 case 0: return kCpumMicroarch_Cyrix_M2;
361 }
362 break;
363
364 }
365 return kCpumMicroarch_Cyrix_Unknown;
366 }
367
368 return kCpumMicroarch_Unknown;
369}
370
371
372/**
373 * Translates a microarchitecture enum value to the corresponding string
374 * constant.
375 *
376 * @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
377 * NULL if the value is invalid.
378 *
379 * @param enmMicroarch The enum value to convert.
380 */
381VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
382{
383 switch (enmMicroarch)
384 {
385#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
386 CASE_RET_STR(kCpumMicroarch_Intel_8086);
387 CASE_RET_STR(kCpumMicroarch_Intel_80186);
388 CASE_RET_STR(kCpumMicroarch_Intel_80286);
389 CASE_RET_STR(kCpumMicroarch_Intel_80386);
390 CASE_RET_STR(kCpumMicroarch_Intel_80486);
391 CASE_RET_STR(kCpumMicroarch_Intel_P5);
392
393 CASE_RET_STR(kCpumMicroarch_Intel_P6);
394 CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
395 CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
396
397 CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
398 CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
399 CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
400
401 CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
402 CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
403
404 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
405 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
406 CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
407 CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
408 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
409 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
410 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
411 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Cannonlake);
412
413 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
414 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
415 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
416 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
417 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
418 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
419 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
420
421 CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
422 CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
423 CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
424 CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
425 CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
426 CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
427 CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
428
429 CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
430
431 CASE_RET_STR(kCpumMicroarch_AMD_Am286);
432 CASE_RET_STR(kCpumMicroarch_AMD_Am386);
433 CASE_RET_STR(kCpumMicroarch_AMD_Am486);
434 CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
435 CASE_RET_STR(kCpumMicroarch_AMD_K5);
436 CASE_RET_STR(kCpumMicroarch_AMD_K6);
437
438 CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
439 CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
440 CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
441 CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
442 CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
443 CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
444 CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
445
446 CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
447 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
448 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
449 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
450 CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
451
452 CASE_RET_STR(kCpumMicroarch_AMD_K10);
453 CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
454 CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
455 CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
456 CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
457
458 CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
459 CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
460 CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
461 CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
462 CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
463
464 CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
465
466 CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
467
468 CASE_RET_STR(kCpumMicroarch_Centaur_C6);
469 CASE_RET_STR(kCpumMicroarch_Centaur_C2);
470 CASE_RET_STR(kCpumMicroarch_Centaur_C3);
471 CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
472 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
473 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
474 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
475 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
476 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
477 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
478 CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
479 CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
480 CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
481
482 CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
483 CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
484 CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
485 CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
486 CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
487 CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
488
489 CASE_RET_STR(kCpumMicroarch_Unknown);
490
491#undef CASE_RET_STR
492 case kCpumMicroarch_Invalid:
493 case kCpumMicroarch_Intel_End:
494 case kCpumMicroarch_Intel_Core7_End:
495 case kCpumMicroarch_Intel_Atom_End:
496 case kCpumMicroarch_Intel_P6_Core_Atom_End:
497 case kCpumMicroarch_Intel_NB_End:
498 case kCpumMicroarch_AMD_K7_End:
499 case kCpumMicroarch_AMD_K8_End:
500 case kCpumMicroarch_AMD_15h_End:
501 case kCpumMicroarch_AMD_16h_End:
502 case kCpumMicroarch_AMD_End:
503 case kCpumMicroarch_VIA_End:
504 case kCpumMicroarch_Cyrix_End:
505 case kCpumMicroarch_32BitHack:
506 break;
507 /* no default! */
508 }
509
510 return NULL;
511}
512
513
514
515/**
516 * Gets a matching leaf in the CPUID leaf array.
517 *
518 * @returns Pointer to the matching leaf, or NULL if not found.
519 * @param paLeaves The CPUID leaves to search. This is sorted.
520 * @param cLeaves The number of leaves in the array.
521 * @param uLeaf The leaf to locate.
522 * @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
523 */
524static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
525{
526 /* Lazy bird does linear lookup here since this is only used for the
527 occational CPUID overrides. */
528 for (uint32_t i = 0; i < cLeaves; i++)
529 if ( paLeaves[i].uLeaf == uLeaf
530 && paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
531 return &paLeaves[i];
532 return NULL;
533}
534
535
536/**
537 * Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
538 *
539 * @returns true if found, false it not.
540 * @param paLeaves The CPUID leaves to search. This is sorted.
541 * @param cLeaves The number of leaves in the array.
542 * @param uLeaf The leaf to locate.
543 * @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
544 * @param pLegacy The legacy output leaf.
545 */
546static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
547 PCPUMCPUID pLegacy)
548{
549 PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
550 if (pLeaf)
551 {
552 pLegacy->uEax = pLeaf->uEax;
553 pLegacy->uEbx = pLeaf->uEbx;
554 pLegacy->uEcx = pLeaf->uEcx;
555 pLegacy->uEdx = pLeaf->uEdx;
556 return true;
557 }
558 return false;
559}
560
561
562/**
563 * Ensures that the CPUID leaf array can hold one more leaf.
564 *
565 * @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
566 * failure.
567 * @param pVM Pointer to the VM, used as the heap selector. Passing
568 * NULL uses the host-context heap, otherwise the VM's
569 * hyper heap is used.
570 * @param ppaLeaves Pointer to the variable holding the array pointer
571 * (input/output).
572 * @param cLeaves The current array size.
573 *
574 * @remarks This function will automatically update the R0 and RC pointers when
575 * using the hyper heap, which means @a ppaLeaves and @a cLeaves must
576 * be the corresponding VM's CPUID arrays (which is asserted).
577 */
578static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
579{
580 /*
581 * If pVM is not specified, we're on the regular heap and can waste a
582 * little space to speed things up.
583 */
584 uint32_t cAllocated;
585 if (!pVM)
586 {
587 cAllocated = RT_ALIGN(cLeaves, 16);
588 if (cLeaves + 1 > cAllocated)
589 {
590 void *pvNew = RTMemRealloc(*ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
591 if (pvNew)
592 *ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
593 else
594 {
595 RTMemFree(*ppaLeaves);
596 *ppaLeaves = NULL;
597 }
598 }
599 }
600 /*
601 * Otherwise, we're on the hyper heap and are probably just inserting
602 * one or two leaves and should conserve space.
603 */
604 else
605 {
606#ifdef IN_VBOX_CPU_REPORT
607 AssertReleaseFailed();
608#else
609 Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
610 Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
611
612 size_t cb = cLeaves * sizeof(**ppaLeaves);
613 size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
614 int rc = MMR3HyperRealloc(pVM, *ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void **)ppaLeaves);
615 if (RT_SUCCESS(rc))
616 {
617 /* Update the R0 and RC pointers. */
618 pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
619 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
620 }
621 else
622 {
623 *ppaLeaves = NULL;
624 pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
625 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
626 LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
627 }
628#endif
629 }
630 return *ppaLeaves;
631}
632
633
634/**
635 * Append a CPUID leaf or sub-leaf.
636 *
637 * ASSUMES linear insertion order, so we'll won't need to do any searching or
638 * replace anything. Use cpumR3CpuIdInsert() for those cases.
639 *
640 * @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
641 * the caller need do no more work.
642 * @param ppaLeaves Pointer to the the pointer to the array of sorted
643 * CPUID leaves and sub-leaves.
644 * @param pcLeaves Where we keep the leaf count for *ppaLeaves.
645 * @param uLeaf The leaf we're adding.
646 * @param uSubLeaf The sub-leaf number.
647 * @param fSubLeafMask The sub-leaf mask.
648 * @param uEax The EAX value.
649 * @param uEbx The EBX value.
650 * @param uEcx The ECX value.
651 * @param uEdx The EDX value.
652 * @param fFlags The flags.
653 */
654static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves,
655 uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
656 uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
657{
658 if (!cpumR3CpuIdEnsureSpace(NULL /* pVM */, ppaLeaves, *pcLeaves))
659 return VERR_NO_MEMORY;
660
661 PCPUMCPUIDLEAF pNew = &(*ppaLeaves)[*pcLeaves];
662 Assert( *pcLeaves == 0
663 || pNew[-1].uLeaf < uLeaf
664 || (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
665
666 pNew->uLeaf = uLeaf;
667 pNew->uSubLeaf = uSubLeaf;
668 pNew->fSubLeafMask = fSubLeafMask;
669 pNew->uEax = uEax;
670 pNew->uEbx = uEbx;
671 pNew->uEcx = uEcx;
672 pNew->uEdx = uEdx;
673 pNew->fFlags = fFlags;
674
675 *pcLeaves += 1;
676 return VINF_SUCCESS;
677}
678
679
680/**
681 * Checks that we've updated the CPUID leaves array correctly.
682 *
683 * This is a no-op in non-strict builds.
684 *
685 * @param paLeaves The leaves array.
686 * @param cLeaves The number of leaves.
687 */
688static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
689{
690#ifdef VBOX_STRICT
691 for (uint32_t i = 1; i < cLeaves; i++)
692 if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
693 AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
694 else
695 {
696 AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
697 ("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
698 AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
699 ("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
700 AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
701 ("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
702 }
703#else
704 NOREF(paLeaves);
705 NOREF(cLeaves);
706#endif
707}
708
709
710/**
711 * Inserts a CPU ID leaf, replacing any existing ones.
712 *
713 * When inserting a simple leaf where we already got a series of subleaves with
714 * the same leaf number (eax), the simple leaf will replace the whole series.
715 *
716 * When pVM is NULL, this ASSUMES that the leaves array is still on the normal
717 * host-context heap and has only been allocated/reallocated by the
718 * cpumR3CpuIdEnsureSpace function.
719 *
720 * @returns VBox status code.
721 * @param pVM Pointer to the VM, used as the heap selector.
722 * Passing NULL uses the host-context heap, otherwise
723 * the VM's hyper heap is used.
724 * @param ppaLeaves Pointer to the the pointer to the array of sorted
725 * CPUID leaves and sub-leaves. Must be NULL if using
726 * the hyper heap.
727 * @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must be
728 * NULL if using the hyper heap.
729 * @param pNewLeaf Pointer to the data of the new leaf we're about to
730 * insert.
731 */
732static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
733{
734 /*
735 * Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
736 */
737 if (pVM)
738 {
739 AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
740 AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
741
742 ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
743 pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
744 }
745
746 PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
747 uint32_t cLeaves = *pcLeaves;
748
749 /*
750 * Validate the new leaf a little.
751 */
752 AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
753 ("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
754 VERR_INVALID_FLAGS);
755 AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 || pNewLeaf->uSubLeaf == 0,
756 ("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
757 VERR_INVALID_PARAMETER);
758 AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
759 ("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
760 VERR_INVALID_PARAMETER);
761 AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
762 ("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
763 VERR_INVALID_PARAMETER);
764
765 /*
766 * Find insertion point. The lazy bird uses the same excuse as in
767 * cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
768 */
769 uint32_t i;
770 if ( cLeaves > 0
771 && paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
772 {
773 /* Add at end. */
774 i = cLeaves;
775 }
776 else if ( cLeaves > 0
777 && paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
778 {
779 /* Either replacing the last leaf or dealing with sub-leaves. Spool
780 back to the first sub-leaf to pretend we did the linear search. */
781 i = cLeaves - 1;
782 while ( i > 0
783 && paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
784 i--;
785 }
786 else
787 {
788 /* Linear search from the start. */
789 i = 0;
790 while ( i < cLeaves
791 && paLeaves[i].uLeaf < pNewLeaf->uLeaf)
792 i++;
793 }
794 if ( i < cLeaves
795 && paLeaves[i].uLeaf == pNewLeaf->uLeaf)
796 {
797 if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
798 {
799 /*
800 * The sub-leaf mask differs, replace all existing leaves with the
801 * same leaf number.
802 */
803 uint32_t c = 1;
804 while ( i + c < cLeaves
805 && paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
806 c++;
807 if (c > 1 && i + c < cLeaves)
808 {
809 memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
810 *pcLeaves = cLeaves -= c - 1;
811 }
812
813 paLeaves[i] = *pNewLeaf;
814 cpumR3CpuIdAssertOrder(*ppaLeaves, *pcLeaves);
815 return VINF_SUCCESS;
816 }
817
818 /* Find sub-leaf insertion point. */
819 while ( i < cLeaves
820 && paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
821 && paLeaves[i].uLeaf == pNewLeaf->uLeaf)
822 i++;
823
824 /*
825 * If we've got an exactly matching leaf, replace it.
826 */
827 if ( i < cLeaves
828 && paLeaves[i].uLeaf == pNewLeaf->uLeaf
829 && paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
830 {
831 paLeaves[i] = *pNewLeaf;
832 cpumR3CpuIdAssertOrder(*ppaLeaves, *pcLeaves);
833 return VINF_SUCCESS;
834 }
835 }
836
837 /*
838 * Adding a new leaf at 'i'.
839 */
840 AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
841 paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
842 if (!paLeaves)
843 return VERR_NO_MEMORY;
844
845 if (i < cLeaves)
846 memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
847 *pcLeaves += 1;
848 paLeaves[i] = *pNewLeaf;
849
850 cpumR3CpuIdAssertOrder(*ppaLeaves, *pcLeaves);
851 return VINF_SUCCESS;
852}
853
854
855/**
856 * Removes a range of CPUID leaves.
857 *
858 * This will not reallocate the array.
859 *
860 * @param paLeaves The array of sorted CPUID leaves and sub-leaves.
861 * @param pcLeaves Where we keep the leaf count for @a paLeaves.
862 * @param uFirst The first leaf.
863 * @param uLast The last leaf.
864 */
865static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
866{
867 uint32_t cLeaves = *pcLeaves;
868
869 Assert(uFirst <= uLast);
870
871 /*
872 * Find the first one.
873 */
874 uint32_t iFirst = 0;
875 while ( iFirst < cLeaves
876 && paLeaves[iFirst].uLeaf < uFirst)
877 iFirst++;
878
879 /*
880 * Find the end (last + 1).
881 */
882 uint32_t iEnd = iFirst;
883 while ( iEnd < cLeaves
884 && paLeaves[iEnd].uLeaf <= uLast)
885 iEnd++;
886
887 /*
888 * Adjust the array if anything needs removing.
889 */
890 if (iFirst < iEnd)
891 {
892 if (iEnd < cLeaves)
893 memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
894 *pcLeaves = cLeaves -= (iEnd - iFirst);
895 }
896
897 cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
898}
899
900
901
902/**
903 * Checks if ECX make a difference when reading a given CPUID leaf.
904 *
905 * @returns @c true if it does, @c false if it doesn't.
906 * @param uLeaf The leaf we're reading.
907 * @param pcSubLeaves Number of sub-leaves accessible via ECX.
908 * @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
909 * final sub-leaf (for leaf 0xb only).
910 */
911static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t *pcSubLeaves, bool *pfFinalEcxUnchanged)
912{
913 *pfFinalEcxUnchanged = false;
914
915 uint32_t auCur[4];
916 uint32_t auPrev[4];
917 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
918
919 /* Look for sub-leaves. */
920 uint32_t uSubLeaf = 1;
921 for (;;)
922 {
923 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
924 if (memcmp(auCur, auPrev, sizeof(auCur)))
925 break;
926
927 /* Advance / give up. */
928 uSubLeaf++;
929 if (uSubLeaf >= 64)
930 {
931 *pcSubLeaves = 1;
932 return false;
933 }
934 }
935
936 /* Count sub-leaves. */
937 uint32_t cRepeats = 0;
938 uSubLeaf = 0;
939 for (;;)
940 {
941 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
942
943 /* Figuring out when to stop isn't entirely straight forward as we need
944 to cover undocumented behavior up to a point and implementation shortcuts. */
945
946 /* 1. Look for zero values. */
947 if ( auCur[0] == 0
948 && auCur[1] == 0
949 && (auCur[2] == 0 || auCur[2] == uSubLeaf)
950 && (auCur[3] == 0 || uLeaf == 0xb /* edx is fixed */) )
951 {
952 cRepeats = 0;
953 break;
954 }
955
956 /* 2. Look for more than 4 repeating value sets. */
957 if ( auCur[0] == auPrev[0]
958 && auCur[1] == auPrev[1]
959 && ( auCur[2] == auPrev[2]
960 || ( auCur[2] == uSubLeaf
961 && auPrev[2] == uSubLeaf - 1) )
962 && auCur[3] == auPrev[3])
963 {
964 cRepeats++;
965 if (cRepeats > 4)
966 break;
967 }
968 else
969 cRepeats = 0;
970
971 /* 3. Leaf 0xb level type 0 check. */
972 if ( uLeaf == 0xb
973 && (auCur[2] & 0xff00) == 0
974 && (auPrev[2] & 0xff00) == 0)
975 {
976 cRepeats = 0;
977 break;
978 }
979
980 /* 99. Give up. */
981 if (uSubLeaf >= 128)
982 {
983#ifndef IN_VBOX_CPU_REPORT
984 /* Ok, limit it according to the documentation if possible just to
985 avoid annoying users with these detection issues. */
986 uint32_t cDocLimit = UINT32_MAX;
987 if (uLeaf == 0x4)
988 cDocLimit = 4;
989 else if (uLeaf == 0x7)
990 cDocLimit = 1;
991 else if (uLeaf == 0xf)
992 cDocLimit = 2;
993 if (cDocLimit != UINT32_MAX)
994 {
995 *pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
996 *pcSubLeaves = cDocLimit + 3;
997 return true;
998 }
999#endif
1000 *pcSubLeaves = UINT32_MAX;
1001 return true;
1002 }
1003
1004 /* Advance. */
1005 uSubLeaf++;
1006 memcpy(auPrev, auCur, sizeof(auCur));
1007 }
1008
1009 /* Standard exit. */
1010 *pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1011 *pcSubLeaves = uSubLeaf + 1 - cRepeats;
1012 if (*pcSubLeaves == 0)
1013 *pcSubLeaves = 1;
1014 return true;
1015}
1016
1017
1018/**
1019 * Gets a CPU ID leaf.
1020 *
1021 * @returns VBox status code.
1022 * @param pVM Pointer to the VM.
1023 * @param pLeaf Where to store the found leaf.
1024 * @param uLeaf The leaf to locate.
1025 * @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
1026 */
1027VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1028{
1029 PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1030 uLeaf, uSubLeaf);
1031 if (pcLeaf)
1032 {
1033 memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1034 return VINF_SUCCESS;
1035 }
1036
1037 return VERR_NOT_FOUND;
1038}
1039
1040
1041/**
1042 * Inserts a CPU ID leaf, replacing any existing ones.
1043 *
1044 * @returns VBox status code.
1045 * @param pVM Pointer to the VM.
1046 * @param pNewLeaf Pointer to the leaf being inserted.
1047 */
1048VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1049{
1050 /*
1051 * Validate parameters.
1052 */
1053 AssertReturn(pVM, VERR_INVALID_PARAMETER);
1054 AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1055
1056 /*
1057 * Disallow replacing CPU ID leaves that this API currently cannot manage.
1058 * These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1059 * If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1060 */
1061 if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1062 || pNewLeaf->uLeaf == UINT32_C(0x00000001)
1063 || pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1064 || pNewLeaf->uLeaf == UINT32_C(0x80000001)
1065 || pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1066 || pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1067 {
1068 return VERR_NOT_SUPPORTED;
1069 }
1070
1071 return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves */, NULL /* pcLeaves */, pNewLeaf);
1072}
1073
1074/**
1075 * Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1076 *
1077 * @returns VBox status code.
1078 * @param ppaLeaves Where to return the array pointer on success.
1079 * Use RTMemFree to release.
1080 * @param pcLeaves Where to return the size of the array on
1081 * success.
1082 */
1083VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
1084{
1085 *ppaLeaves = NULL;
1086 *pcLeaves = 0;
1087
1088 /*
1089 * Try out various candidates. This must be sorted!
1090 */
1091 static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1092 {
1093 { UINT32_C(0x00000000), false },
1094 { UINT32_C(0x10000000), false },
1095 { UINT32_C(0x20000000), false },
1096 { UINT32_C(0x30000000), false },
1097 { UINT32_C(0x40000000), false },
1098 { UINT32_C(0x50000000), false },
1099 { UINT32_C(0x60000000), false },
1100 { UINT32_C(0x70000000), false },
1101 { UINT32_C(0x80000000), false },
1102 { UINT32_C(0x80860000), false },
1103 { UINT32_C(0x8ffffffe), true },
1104 { UINT32_C(0x8fffffff), true },
1105 { UINT32_C(0x90000000), false },
1106 { UINT32_C(0xa0000000), false },
1107 { UINT32_C(0xb0000000), false },
1108 { UINT32_C(0xc0000000), false },
1109 { UINT32_C(0xd0000000), false },
1110 { UINT32_C(0xe0000000), false },
1111 { UINT32_C(0xf0000000), false },
1112 };
1113
1114 for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1115 {
1116 uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1117 uint32_t uEax, uEbx, uEcx, uEdx;
1118 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1119
1120 /*
1121 * Does EAX look like a typical leaf count value?
1122 */
1123 if ( uEax > uLeaf
1124 && uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1125 {
1126 /* Yes, dump them. */
1127 uint32_t cLeaves = uEax - uLeaf + 1;
1128 while (cLeaves-- > 0)
1129 {
1130 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1131
1132 uint32_t fFlags = 0;
1133
1134 /* There are currently three known leaves containing an APIC ID
1135 that needs EMT specific attention */
1136 if (uLeaf == 1)
1137 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1138 else if (uLeaf == 0xb && uEcx != 0)
1139 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1140 else if ( uLeaf == UINT32_C(0x8000001e)
1141 && ( uEax
1142 || uEbx
1143 || uEdx
1144 || ASMIsAmdCpuEx((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1145 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1146
1147
1148 /* Check three times here to reduce the chance of CPU migration
1149 resulting in false positives with things like the APIC ID. */
1150 uint32_t cSubLeaves;
1151 bool fFinalEcxUnchanged;
1152 if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1153 && cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1154 && cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1155 {
1156 if (cSubLeaves > 16)
1157 {
1158 /* This shouldn't happen. But in case it does, file all
1159 relevant details in the release log. */
1160 LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1161 LogRel(("------------------ dump of problematic subleaves ------------------\n"));
1162 for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1163 {
1164 uint32_t auTmp[4];
1165 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1166 LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1167 uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1168 }
1169 LogRel(("----------------- dump of what we've found so far -----------------\n"));
1170 for (uint32_t i = 0 ; i < *pcLeaves; i++)
1171 LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1172 (*ppaLeaves)[i].uLeaf, (*ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1173 (*ppaLeaves)[i].uEax, (*ppaLeaves)[i].uEbx, (*ppaLeaves)[i].uEcx, (*ppaLeaves)[i].uEdx));
1174 LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1175 return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1176 }
1177
1178 if (fFinalEcxUnchanged)
1179 fFlags |= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1180
1181 for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1182 {
1183 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1184 int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1185 uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1186 if (RT_FAILURE(rc))
1187 return rc;
1188 }
1189 }
1190 else
1191 {
1192 int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1193 uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1194 if (RT_FAILURE(rc))
1195 return rc;
1196 }
1197
1198 /* next */
1199 uLeaf++;
1200 }
1201 }
1202 /*
1203 * Special CPUIDs needs special handling as they don't follow the
1204 * leaf count principle used above.
1205 */
1206 else if (s_aCandidates[iOuter].fSpecial)
1207 {
1208 bool fKeep = false;
1209 if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1210 fKeep = true;
1211 else if ( uLeaf == 0x8fffffff
1212 && RT_C_IS_PRINT(RT_BYTE1(uEax))
1213 && RT_C_IS_PRINT(RT_BYTE2(uEax))
1214 && RT_C_IS_PRINT(RT_BYTE3(uEax))
1215 && RT_C_IS_PRINT(RT_BYTE4(uEax))
1216 && RT_C_IS_PRINT(RT_BYTE1(uEbx))
1217 && RT_C_IS_PRINT(RT_BYTE2(uEbx))
1218 && RT_C_IS_PRINT(RT_BYTE3(uEbx))
1219 && RT_C_IS_PRINT(RT_BYTE4(uEbx))
1220 && RT_C_IS_PRINT(RT_BYTE1(uEcx))
1221 && RT_C_IS_PRINT(RT_BYTE2(uEcx))
1222 && RT_C_IS_PRINT(RT_BYTE3(uEcx))
1223 && RT_C_IS_PRINT(RT_BYTE4(uEcx))
1224 && RT_C_IS_PRINT(RT_BYTE1(uEdx))
1225 && RT_C_IS_PRINT(RT_BYTE2(uEdx))
1226 && RT_C_IS_PRINT(RT_BYTE3(uEdx))
1227 && RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1228 fKeep = true;
1229 if (fKeep)
1230 {
1231 int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1232 uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1233 if (RT_FAILURE(rc))
1234 return rc;
1235 }
1236 }
1237 }
1238
1239 cpumR3CpuIdAssertOrder(*ppaLeaves, *pcLeaves);
1240 return VINF_SUCCESS;
1241}
1242
1243
1244/**
1245 * Determines the method the CPU uses to handle unknown CPUID leaves.
1246 *
1247 * @returns VBox status code.
1248 * @param penmUnknownMethod Where to return the method.
1249 * @param pDefUnknown Where to return default unknown values. This
1250 * will be set, even if the resulting method
1251 * doesn't actually needs it.
1252 */
1253VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1254{
1255 uint32_t uLastStd = ASMCpuId_EAX(0);
1256 uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1257 if (!ASMIsValidExtRange(uLastExt))
1258 uLastExt = 0x80000000;
1259
1260 uint32_t auChecks[] =
1261 {
1262 uLastStd + 1,
1263 uLastStd + 5,
1264 uLastStd + 8,
1265 uLastStd + 32,
1266 uLastStd + 251,
1267 uLastExt + 1,
1268 uLastExt + 8,
1269 uLastExt + 15,
1270 uLastExt + 63,
1271 uLastExt + 255,
1272 0x7fbbffcc,
1273 0x833f7872,
1274 0xefff2353,
1275 0x35779456,
1276 0x1ef6d33e,
1277 };
1278
1279 static const uint32_t s_auValues[] =
1280 {
1281 0xa95d2156,
1282 0x00000001,
1283 0x00000002,
1284 0x00000008,
1285 0x00000000,
1286 0x55773399,
1287 0x93401769,
1288 0x12039587,
1289 };
1290
1291 /*
1292 * Simple method, all zeros.
1293 */
1294 *penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1295 pDefUnknown->uEax = 0;
1296 pDefUnknown->uEbx = 0;
1297 pDefUnknown->uEcx = 0;
1298 pDefUnknown->uEdx = 0;
1299
1300 /*
1301 * Intel has been observed returning the last standard leaf.
1302 */
1303 uint32_t auLast[4];
1304 ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1305
1306 uint32_t cChecks = RT_ELEMENTS(auChecks);
1307 while (cChecks > 0)
1308 {
1309 uint32_t auCur[4];
1310 ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1311 if (memcmp(auCur, auLast, sizeof(auCur)))
1312 break;
1313 cChecks--;
1314 }
1315 if (cChecks == 0)
1316 {
1317 /* Now, what happens when the input changes? Esp. ECX. */
1318 uint32_t cTotal = 0;
1319 uint32_t cSame = 0;
1320 uint32_t cLastWithEcx = 0;
1321 uint32_t cNeither = 0;
1322 uint32_t cValues = RT_ELEMENTS(s_auValues);
1323 while (cValues > 0)
1324 {
1325 uint32_t uValue = s_auValues[cValues - 1];
1326 uint32_t auLastWithEcx[4];
1327 ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1328 &auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1329
1330 cChecks = RT_ELEMENTS(auChecks);
1331 while (cChecks > 0)
1332 {
1333 uint32_t auCur[4];
1334 ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1335 if (!memcmp(auCur, auLast, sizeof(auCur)))
1336 {
1337 cSame++;
1338 if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1339 cLastWithEcx++;
1340 }
1341 else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1342 cLastWithEcx++;
1343 else
1344 cNeither++;
1345 cTotal++;
1346 cChecks--;
1347 }
1348 cValues--;
1349 }
1350
1351 Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1352 if (cSame == cTotal)
1353 *penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1354 else if (cLastWithEcx == cTotal)
1355 *penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1356 else
1357 *penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1358 pDefUnknown->uEax = auLast[0];
1359 pDefUnknown->uEbx = auLast[1];
1360 pDefUnknown->uEcx = auLast[2];
1361 pDefUnknown->uEdx = auLast[3];
1362 return VINF_SUCCESS;
1363 }
1364
1365 /*
1366 * Unchanged register values?
1367 */
1368 cChecks = RT_ELEMENTS(auChecks);
1369 while (cChecks > 0)
1370 {
1371 uint32_t const uLeaf = auChecks[cChecks - 1];
1372 uint32_t cValues = RT_ELEMENTS(s_auValues);
1373 while (cValues > 0)
1374 {
1375 uint32_t uValue = s_auValues[cValues - 1];
1376 uint32_t auCur[4];
1377 ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1378 if ( auCur[0] != uLeaf
1379 || auCur[1] != uValue
1380 || auCur[2] != uValue
1381 || auCur[3] != uValue)
1382 break;
1383 cValues--;
1384 }
1385 if (cValues != 0)
1386 break;
1387 cChecks--;
1388 }
1389 if (cChecks == 0)
1390 {
1391 *penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1392 return VINF_SUCCESS;
1393 }
1394
1395 /*
1396 * Just go with the simple method.
1397 */
1398 return VINF_SUCCESS;
1399}
1400
1401
1402/**
1403 * Translates a unknow CPUID leaf method into the constant name (sans prefix).
1404 *
1405 * @returns Read only name string.
1406 * @param enmUnknownMethod The method to translate.
1407 */
1408VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1409{
1410 switch (enmUnknownMethod)
1411 {
1412 case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1413 case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1414 case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1415 case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1416
1417 case CPUMUNKNOWNCPUID_INVALID:
1418 case CPUMUNKNOWNCPUID_END:
1419 case CPUMUNKNOWNCPUID_32BIT_HACK:
1420 break;
1421 }
1422 return "Invalid-unknown-CPUID-method";
1423}
1424
1425
1426/**
1427 * Detect the CPU vendor give n the
1428 *
1429 * @returns The vendor.
1430 * @param uEAX EAX from CPUID(0).
1431 * @param uEBX EBX from CPUID(0).
1432 * @param uECX ECX from CPUID(0).
1433 * @param uEDX EDX from CPUID(0).
1434 */
1435VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1436{
1437 if (ASMIsValidStdRange(uEAX))
1438 {
1439 if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1440 return CPUMCPUVENDOR_AMD;
1441
1442 if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1443 return CPUMCPUVENDOR_INTEL;
1444
1445 if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1446 return CPUMCPUVENDOR_VIA;
1447
1448 if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1449 && uECX == UINT32_C(0x64616574)
1450 && uEDX == UINT32_C(0x736E4978))
1451 return CPUMCPUVENDOR_CYRIX;
1452
1453 /* "Geode by NSC", example: family 5, model 9. */
1454
1455 /** @todo detect the other buggers... */
1456 }
1457
1458 return CPUMCPUVENDOR_UNKNOWN;
1459}
1460
1461
1462/**
1463 * Translates a CPU vendor enum value into the corresponding string constant.
1464 *
1465 * The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1466 * value name. This can be useful when generating code.
1467 *
1468 * @returns Read only name string.
1469 * @param enmVendor The CPU vendor value.
1470 */
1471VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1472{
1473 switch (enmVendor)
1474 {
1475 case CPUMCPUVENDOR_INTEL: return "INTEL";
1476 case CPUMCPUVENDOR_AMD: return "AMD";
1477 case CPUMCPUVENDOR_VIA: return "VIA";
1478 case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1479 case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1480
1481 case CPUMCPUVENDOR_INVALID:
1482 case CPUMCPUVENDOR_32BIT_HACK:
1483 break;
1484 }
1485 return "Invalid-cpu-vendor";
1486}
1487
1488
1489static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1490{
1491 /* Could do binary search, doing linear now because I'm lazy. */
1492 PCCPUMCPUIDLEAF pLeaf = paLeaves;
1493 while (cLeaves-- > 0)
1494 {
1495 if (pLeaf->uLeaf == uLeaf)
1496 return pLeaf;
1497 pLeaf++;
1498 }
1499 return NULL;
1500}
1501
1502
1503static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1504{
1505 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1506 if ( !pLeaf
1507 || pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1508 return pLeaf;
1509
1510 /* Linear sub-leaf search. Lazy as usual. */
1511 cLeaves -= pLeaf - paLeaves;
1512 while ( cLeaves-- > 0
1513 && pLeaf->uLeaf == uLeaf)
1514 {
1515 if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1516 return pLeaf;
1517 pLeaf++;
1518 }
1519
1520 return NULL;
1521}
1522
1523
1524int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1525{
1526 RT_ZERO(*pFeatures);
1527 if (cLeaves >= 2)
1528 {
1529 AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1530 AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1531 PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1532 AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1533 PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1534 AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1535
1536 pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1537 pStd0Leaf->uEbx,
1538 pStd0Leaf->uEcx,
1539 pStd0Leaf->uEdx);
1540 pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1541 pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1542 pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1543 pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1544 pFeatures->uFamily,
1545 pFeatures->uModel,
1546 pFeatures->uStepping);
1547
1548 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1549 if (pLeaf)
1550 pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff;
1551 else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1552 pFeatures->cMaxPhysAddrWidth = 36;
1553 else
1554 pFeatures->cMaxPhysAddrWidth = 32;
1555
1556 /* Standard features. */
1557 pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1558 pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1559 pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1560 pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1561 pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1562 pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1563 pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1564 pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1565 pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1566 pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1567 pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1568 pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1569 pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1570 pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1571 pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1572 pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1573 pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1574 pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1575 pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1576 pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1577 pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1578 pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1579
1580 /* Structured extended features. */
1581 PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1582 if (pSxfLeaf0)
1583 {
1584 pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEcx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1585 pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEcx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1586 }
1587
1588 /* MWAIT/MONITOR leaf. */
1589 PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1590 if (pMWaitLeaf)
1591 {
1592 pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1593 == (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1594 }
1595
1596 /* Extended features. */
1597 PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1598 if (pExtLeaf)
1599 {
1600 pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1601 pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1602 pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1603 pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1604 pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1605 pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1606 pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1607 pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1608 || (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1609 | X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1610 }
1611
1612 if ( pExtLeaf
1613 && pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1614 {
1615 /* AMD features. */
1616 pFeatures->fMsr |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1617 pFeatures->fApic |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1618 pFeatures->fPse |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1619 pFeatures->fPse36 |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1620 pFeatures->fPae |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1621 pFeatures->fPat |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1622 pFeatures->fFxSaveRstor |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1623 pFeatures->fMmx |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1624 pFeatures->fTsc |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1625 pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1626 }
1627
1628 /*
1629 * Quirks.
1630 */
1631 pFeatures->fLeakyFxSR = pExtLeaf
1632 && (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1633 && pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1634 && pFeatures->uFamily >= 6 /* K7 and up */;
1635
1636 /*
1637 * Max extended (/FPU) state.
1638 */
1639 pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1640 if (pFeatures->fXSaveRstor)
1641 {
1642 PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1643 if (pXStateLeaf0)
1644 {
1645 if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1646 && pXStateLeaf0->uEcx <= _8K
1647 && RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1648 && pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1649 && pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1650 && RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1651 {
1652 pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1653 }
1654 else
1655 AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1656 pFeatures->fXSaveRstor = 0);
1657 }
1658 else
1659 AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1660 pFeatures->fXSaveRstor = 0);
1661 }
1662 }
1663 else
1664 AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1665 return VINF_SUCCESS;
1666}
1667
1668
1669/*
1670 *
1671 * Init related code.
1672 * Init related code.
1673 * Init related code.
1674 *
1675 *
1676 */
1677#ifdef VBOX_IN_VMM
1678
1679
1680/**
1681 * Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1682 *
1683 * This ignores the fSubLeafMask.
1684 *
1685 * @returns Pointer to the matching leaf, or NULL if not found.
1686 * @param paLeaves The CPUID leaves to search. This is sorted.
1687 * @param cLeaves The number of leaves in the array.
1688 * @param uLeaf The leaf to locate.
1689 * @param uSubLeaf The subleaf to locate.
1690 */
1691static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1692{
1693 uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1694 PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1695 uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1696 if (iEnd)
1697 {
1698 uint32_t iBegin = 0;
1699 for (;;)
1700 {
1701 uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1702 uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1703 if (uNeedle < uCur)
1704 {
1705 if (i > iBegin)
1706 iEnd = i;
1707 else
1708 break;
1709 }
1710 else if (uNeedle > uCur)
1711 {
1712 if (i + 1 < iEnd)
1713 iBegin = i + 1;
1714 else
1715 break;
1716 }
1717 else
1718 return &paLeaves[i];
1719 }
1720 }
1721 return NULL;
1722}
1723
1724
1725/**
1726 * Loads MSR range overrides.
1727 *
1728 * This must be called before the MSR ranges are moved from the normal heap to
1729 * the hyper heap!
1730 *
1731 * @returns VBox status code (VMSetError called).
1732 * @param pVM Pointer to the cross context VM structure
1733 * @param pMsrNode The CFGM node with the MSR overrides.
1734 */
1735static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1736{
1737 for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1738 {
1739 /*
1740 * Assemble a valid MSR range.
1741 */
1742 CPUMMSRRANGE MsrRange;
1743 MsrRange.offCpumCpu = 0;
1744 MsrRange.fReserved = 0;
1745
1746 int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1747 if (RT_FAILURE(rc))
1748 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1749
1750 rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1751 if (RT_FAILURE(rc))
1752 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1753 MsrRange.szName, rc);
1754
1755 rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1756 if (RT_FAILURE(rc))
1757 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1758 MsrRange.szName, rc);
1759
1760 char szType[32];
1761 rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1762 if (RT_FAILURE(rc))
1763 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1764 MsrRange.szName, rc);
1765 if (!RTStrICmp(szType, "FixedValue"))
1766 {
1767 MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1768 MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1769
1770 rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1771 if (RT_FAILURE(rc))
1772 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1773 MsrRange.szName, rc);
1774
1775 rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1776 if (RT_FAILURE(rc))
1777 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1778 MsrRange.szName, rc);
1779
1780 rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1781 if (RT_FAILURE(rc))
1782 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1783 MsrRange.szName, rc);
1784 }
1785 else
1786 return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1787 "Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1788
1789 /*
1790 * Insert the range into the table (replaces/splits/shrinks existing
1791 * MSR ranges).
1792 */
1793 rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1794 &MsrRange);
1795 if (RT_FAILURE(rc))
1796 return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
1797 }
1798
1799 return VINF_SUCCESS;
1800}
1801
1802
1803/**
1804 * Loads CPUID leaf overrides.
1805 *
1806 * This must be called before the CPUID leaves are moved from the normal
1807 * heap to the hyper heap!
1808 *
1809 * @returns VBox status code (VMSetError called).
1810 * @param pVM Pointer to the cross context VM structure
1811 * @param pParentNode The CFGM node with the CPUID leaves.
1812 * @param pszLabel How to label the overrides we're loading.
1813 */
1814static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
1815{
1816 for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1817 {
1818 /*
1819 * Get the leaf and subleaf numbers.
1820 */
1821 char szName[128];
1822 int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
1823 if (RT_FAILURE(rc))
1824 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
1825
1826 /* The leaf number is either specified directly or thru the node name. */
1827 uint32_t uLeaf;
1828 rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
1829 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1830 {
1831 rc = RTStrToUInt32Full(szName, 16, &uLeaf);
1832 if (rc != VINF_SUCCESS)
1833 return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
1834 "Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
1835 }
1836 else if (RT_FAILURE(rc))
1837 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
1838 pszLabel, szName, rc);
1839
1840 uint32_t uSubLeaf;
1841 rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
1842 if (RT_FAILURE(rc))
1843 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
1844 pszLabel, szName, rc);
1845
1846 uint32_t fSubLeafMask;
1847 rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
1848 if (RT_FAILURE(rc))
1849 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
1850 pszLabel, szName, rc);
1851
1852 /*
1853 * Look up the specified leaf, since the output register values
1854 * defaults to any existing values. This allows overriding a single
1855 * register, without needing to know the other values.
1856 */
1857 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
1858 CPUMCPUIDLEAF Leaf;
1859 if (pLeaf)
1860 Leaf = *pLeaf;
1861 else
1862 RT_ZERO(Leaf);
1863 Leaf.uLeaf = uLeaf;
1864 Leaf.uSubLeaf = uSubLeaf;
1865 Leaf.fSubLeafMask = fSubLeafMask;
1866
1867 rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
1868 if (RT_FAILURE(rc))
1869 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
1870 pszLabel, szName, rc);
1871 rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
1872 if (RT_FAILURE(rc))
1873 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
1874 pszLabel, szName, rc);
1875 rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
1876 if (RT_FAILURE(rc))
1877 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
1878 pszLabel, szName, rc);
1879 rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
1880 if (RT_FAILURE(rc))
1881 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
1882 pszLabel, szName, rc);
1883
1884 /*
1885 * Insert the leaf into the table (replaces existing ones).
1886 */
1887 rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1888 &Leaf);
1889 if (RT_FAILURE(rc))
1890 return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
1891 }
1892
1893 return VINF_SUCCESS;
1894}
1895
1896
1897
1898/**
1899 * Fetches overrides for a CPUID leaf.
1900 *
1901 * @returns VBox status code.
1902 * @param pLeaf The leaf to load the overrides into.
1903 * @param pCfgNode The CFGM node containing the overrides
1904 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
1905 * @param iLeaf The CPUID leaf number.
1906 */
1907static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
1908{
1909 PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
1910 if (pLeafNode)
1911 {
1912 uint32_t u32;
1913 int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
1914 if (RT_SUCCESS(rc))
1915 pLeaf->uEax = u32;
1916 else
1917 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1918
1919 rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
1920 if (RT_SUCCESS(rc))
1921 pLeaf->uEbx = u32;
1922 else
1923 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1924
1925 rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
1926 if (RT_SUCCESS(rc))
1927 pLeaf->uEcx = u32;
1928 else
1929 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1930
1931 rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
1932 if (RT_SUCCESS(rc))
1933 pLeaf->uEdx = u32;
1934 else
1935 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1936
1937 }
1938 return VINF_SUCCESS;
1939}
1940
1941
1942/**
1943 * Load the overrides for a set of CPUID leaves.
1944 *
1945 * @returns VBox status code.
1946 * @param paLeaves The leaf array.
1947 * @param cLeaves The number of leaves.
1948 * @param uStart The start leaf number.
1949 * @param pCfgNode The CFGM node containing the overrides
1950 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
1951 */
1952static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
1953{
1954 for (uint32_t i = 0; i < cLeaves; i++)
1955 {
1956 int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
1957 if (RT_FAILURE(rc))
1958 return rc;
1959 }
1960
1961 return VINF_SUCCESS;
1962}
1963
1964/**
1965 * Init a set of host CPUID leaves.
1966 *
1967 * @returns VBox status code.
1968 * @param paLeaves The leaf array.
1969 * @param cLeaves The number of leaves.
1970 * @param uStart The start leaf number.
1971 * @param pCfgNode The /CPUM/HostCPUID/ node.
1972 */
1973static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
1974{
1975 /* Using the ECX variant for all of them can't hurt... */
1976 for (uint32_t i = 0; i < cLeaves; i++)
1977 ASMCpuIdExSlow(uStart + i, 0, 0, 0, &paLeaves[i].uEax, &paLeaves[i].uEbx, &paLeaves[i].uEcx, &paLeaves[i].uEdx);
1978
1979 /* Load CPUID leaf override; we currently don't care if the user
1980 specifies features the host CPU doesn't support. */
1981 return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
1982}
1983
1984
1985static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
1986{
1987 cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
1988
1989 /*
1990 * Install the CPUID information.
1991 */
1992 int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
1993 MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
1994
1995 AssertLogRelRCReturn(rc, rc);
1996 pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
1997 pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
1998 pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
1999 Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2000 Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2001
2002 /*
2003 * Update the default CPUID leaf if necessary.
2004 */
2005 switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2006 {
2007 case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2008 case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2009 {
2010 /* We don't use CPUID(0).eax here because of the NT hack that only
2011 changes that value without actually removing any leaves. */
2012 uint32_t i = 0;
2013 if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2014 && pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2015 {
2016 while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2017 && pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2018 i++;
2019 pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2020 pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2021 pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2022 pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2023 }
2024 break;
2025 }
2026 default:
2027 break;
2028 }
2029
2030 /*
2031 * Explode the guest CPU features.
2032 */
2033 rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
2034 AssertLogRelRCReturn(rc, rc);
2035
2036 /*
2037 * Adjust the scalable bus frequency according to the CPUID information
2038 * we're now using.
2039 */
2040 if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2041 pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2042 ? UINT64_C(100000000) /* 100MHz */
2043 : UINT64_C(133333333); /* 133MHz */
2044
2045 /*
2046 * Populate the legacy arrays. Currently used for everything, later only
2047 * for patch manager.
2048 */
2049 struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2050 {
2051 { pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2052 { pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2053 { pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2054 };
2055 for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2056 {
2057 uint32_t cLeft = aOldRanges[i].cCpuIds;
2058 uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2059 PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2060 while (cLeft-- > 0)
2061 {
2062 uLeaf--;
2063 pLegacyLeaf--;
2064
2065 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2066 if (pLeaf)
2067 {
2068 pLegacyLeaf->uEax = pLeaf->uEax;
2069 pLegacyLeaf->uEbx = pLeaf->uEbx;
2070 pLegacyLeaf->uEcx = pLeaf->uEcx;
2071 pLegacyLeaf->uEdx = pLeaf->uEdx;
2072 }
2073 else
2074 *pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2075 }
2076 }
2077
2078 return VINF_SUCCESS;
2079}
2080
2081
2082/** @name Instruction Set Extension Options
2083 * @{ */
2084/** Configuration option type (extended boolean, really). */
2085typedef uint8_t CPUMISAEXTCFG;
2086/** Always disable the extension. */
2087#define CPUMISAEXTCFG_DISABLED false
2088/** Enable the extension if it's supported by the host CPU. */
2089#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2090/** Enable the extension if it's supported by the host CPU, but don't let
2091 * the portable CPUID feature disable it. */
2092#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2093/** Always enable the extension. */
2094#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2095/** @} */
2096
2097/**
2098 * CPUID Configuration (from CFGM).
2099 *
2100 * @remarks The members aren't document since we would only be duplicating the
2101 * \@cfgm entries in cpumR3CpuIdReadConfig.
2102 */
2103typedef struct CPUMCPUIDCONFIG
2104{
2105 bool fSyntheticCpu;
2106 bool fNt4LeafLimit;
2107 bool fInvariantTsc;
2108
2109 CPUMISAEXTCFG enmCmpXchg16b;
2110 CPUMISAEXTCFG enmMonitor;
2111 CPUMISAEXTCFG enmMWaitExtensions;
2112 CPUMISAEXTCFG enmSse41;
2113 CPUMISAEXTCFG enmSse42;
2114 CPUMISAEXTCFG enmAvx;
2115 CPUMISAEXTCFG enmAvx2;
2116 CPUMISAEXTCFG enmXSave;
2117 CPUMISAEXTCFG enmAesNi;
2118 CPUMISAEXTCFG enmPClMul;
2119 CPUMISAEXTCFG enmPopCnt;
2120 CPUMISAEXTCFG enmMovBe;
2121 CPUMISAEXTCFG enmRdRand;
2122 CPUMISAEXTCFG enmRdSeed;
2123 CPUMISAEXTCFG enmCLFlushOpt;
2124
2125 CPUMISAEXTCFG enmAbm;
2126 CPUMISAEXTCFG enmSse4A;
2127 CPUMISAEXTCFG enmMisAlnSse;
2128 CPUMISAEXTCFG enm3dNowPrf;
2129 CPUMISAEXTCFG enmAmdExtMmx;
2130
2131 uint32_t uMaxStdLeaf;
2132 uint32_t uMaxExtLeaf;
2133 uint32_t uMaxCentaurLeaf;
2134 uint32_t uMaxIntelFamilyModelStep;
2135 char szCpuName[128];
2136} CPUMCPUIDCONFIG;
2137/** Pointer to CPUID config (from CFGM). */
2138typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2139
2140
2141/**
2142 * Insert hypervisor identification leaves.
2143 *
2144 * We only return minimal information, primarily ensuring that the
2145 * 0x40000000 function returns 0x40000001 and identifying ourselves.
2146 * Hypervisor-specific interface is supported through GIM which will
2147 * modify these leaves if required depending on the GIM provider.
2148 *
2149 * @returns VBox status code.
2150 * @param pCpum The CPUM instance data.
2151 * @param pConfig The CPUID configuration we've read from CFGM.
2152 */
2153static int cpumR3CpuIdPlantHypervisorLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2154{
2155 CPUMCPUIDLEAF NewLeaf;
2156 NewLeaf.uLeaf = UINT32_C(0x40000000);
2157 NewLeaf.uSubLeaf = 0;
2158 NewLeaf.fSubLeafMask = 0;
2159 NewLeaf.uEax = UINT32_C(0x40000001);
2160 NewLeaf.uEbx = 0x786f4256 /* 'VBox' */;
2161 NewLeaf.uEcx = 0x786f4256 /* 'VBox' */;
2162 NewLeaf.uEdx = 0x786f4256 /* 'VBox' */;
2163 NewLeaf.fFlags = 0;
2164 int rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
2165 AssertLogRelRCReturn(rc, rc);
2166
2167 NewLeaf.uLeaf = UINT32_C(0x40000001);
2168 NewLeaf.uEax = 0x656e6f6e; /* 'none' */
2169 NewLeaf.uEbx = 0;
2170 NewLeaf.uEcx = 0;
2171 NewLeaf.uEdx = 0;
2172 NewLeaf.fFlags = 0;
2173 rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
2174 AssertLogRelRCReturn(rc, rc);
2175
2176 return VINF_SUCCESS;
2177}
2178
2179
2180/**
2181 * Mini CPU selection support for making Mac OS X happy.
2182 *
2183 * Executes the /CPUM/MaxIntelFamilyModelStep config.
2184 *
2185 * @param pCpum The CPUM instance data.
2186 * @param pConfig The CPUID configuration we've read from CFGM.
2187 */
2188static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2189{
2190 if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2191 {
2192 PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2193 uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2194 ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2195 ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2196 0);
2197 uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2198 if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2199 {
2200 uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2201 uNew |= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2202 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2203 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2204 uNew |= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2205 if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2206 uNew |= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2207 LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2208 pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2209 pStdFeatureLeaf->uEax = uNew;
2210 }
2211 }
2212}
2213
2214
2215
2216/**
2217 * Limit it the number of entries, zapping the remainder.
2218 *
2219 * The limits are masking off stuff about power saving and similar, this
2220 * is perhaps a bit crudely done as there is probably some relatively harmless
2221 * info too in these leaves (like words about having a constant TSC).
2222 *
2223 * @param pCpum The CPUM instance data.
2224 * @param pConfig The CPUID configuration we've read from CFGM.
2225 */
2226static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2227{
2228 /*
2229 * Standard leaves.
2230 */
2231 uint32_t uSubLeaf = 0;
2232 PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2233 if (pCurLeaf)
2234 {
2235 uint32_t uLimit = pCurLeaf->uEax;
2236 if (uLimit <= UINT32_C(0x000fffff))
2237 {
2238 if (uLimit > pConfig->uMaxStdLeaf)
2239 {
2240 pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2241 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2242 uLimit + 1, UINT32_C(0x000fffff));
2243 }
2244
2245 /* NT4 hack, no zapping of extra leaves here. */
2246 if (pConfig->fNt4LeafLimit && uLimit > 3)
2247 pCurLeaf->uEax = uLimit = 3;
2248
2249 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2250 pCurLeaf->uEax = uLimit;
2251 }
2252 else
2253 {
2254 LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2255 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2256 UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2257 }
2258 }
2259
2260 /*
2261 * Extended leaves.
2262 */
2263 uSubLeaf = 0;
2264 pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2265 if (pCurLeaf)
2266 {
2267 uint32_t uLimit = pCurLeaf->uEax;
2268 if ( uLimit >= UINT32_C(0x80000000)
2269 && uLimit <= UINT32_C(0x800fffff))
2270 {
2271 if (uLimit > pConfig->uMaxExtLeaf)
2272 {
2273 pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2274 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2275 uLimit + 1, UINT32_C(0x800fffff));
2276 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2277 pCurLeaf->uEax = uLimit;
2278 }
2279 }
2280 else
2281 {
2282 LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2283 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2284 UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2285 }
2286 }
2287
2288 /*
2289 * Centaur leaves (VIA).
2290 */
2291 uSubLeaf = 0;
2292 pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2293 if (pCurLeaf)
2294 {
2295 uint32_t uLimit = pCurLeaf->uEax;
2296 if ( uLimit >= UINT32_C(0xc0000000)
2297 && uLimit <= UINT32_C(0xc00fffff))
2298 {
2299 if (uLimit > pConfig->uMaxCentaurLeaf)
2300 {
2301 pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2302 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2303 uLimit + 1, UINT32_C(0xcfffffff));
2304 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2305 pCurLeaf->uEax = uLimit;
2306 }
2307 }
2308 else
2309 {
2310 LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2311 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2312 UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2313 }
2314 }
2315}
2316
2317
2318/**
2319 * Clears a CPUID leaf and all sub-leaves (to zero).
2320 *
2321 * @param pCpum The CPUM instance data.
2322 * @param uLeaf The leaf to clear.
2323 */
2324static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2325{
2326 uint32_t uSubLeaf = 0;
2327 PCPUMCPUIDLEAF pCurLeaf;
2328 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2329 {
2330 pCurLeaf->uEax = 0;
2331 pCurLeaf->uEbx = 0;
2332 pCurLeaf->uEcx = 0;
2333 pCurLeaf->uEdx = 0;
2334 uSubLeaf++;
2335 }
2336}
2337
2338
2339/**
2340 * Sanitizes and adjust the CPUID leaves.
2341 *
2342 * Drop features that aren't virtualized (or virtualizable). Adjust information
2343 * and capabilities to fit the virtualized hardware. Remove information the
2344 * guest shouldn't have (because it's wrong in the virtual world or because it
2345 * gives away host details) or that we don't have documentation for and no idea
2346 * what means.
2347 *
2348 * @returns VBox status code.
2349 * @param pVM Pointer to the cross context VM structure (for cCpus).
2350 * @param pCpum The CPUM instance data.
2351 * @param pConfig The CPUID configuration we've read from CFGM.
2352 */
2353static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2354{
2355#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2356 if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2357 { \
2358 LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2359 (a_pLeafReg) &= ~(uint32_t)(fMask); \
2360 }
2361#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2362 if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2363 { \
2364 LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2365 (a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2366 }
2367#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2368 if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2369 && ((a_pLeafReg) & (fBitMask)) \
2370 && (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2371 { \
2372 LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2373 (a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2374 }
2375 Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2376
2377 /* Cpuid 1:
2378 * EAX: CPU model, family and stepping.
2379 *
2380 * ECX + EDX: Supported features. Only report features we can support.
2381 * Note! When enabling new features the Synthetic CPU and Portable CPUID
2382 * options may require adjusting (i.e. stripping what was enabled).
2383 *
2384 * EBX: Branding, CLFLUSH line size, logical processors per package and
2385 * initial APIC ID.
2386 */
2387 PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2388 AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2389 AssertLogRelReturn(pStdFeatureLeaf->fSubLeafMask == 0, VERR_CPUM_IPE_2);
2390
2391 pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2392 | X86_CPUID_FEATURE_EDX_VME
2393 | X86_CPUID_FEATURE_EDX_DE
2394 | X86_CPUID_FEATURE_EDX_PSE
2395 | X86_CPUID_FEATURE_EDX_TSC
2396 | X86_CPUID_FEATURE_EDX_MSR
2397 //| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2398 | X86_CPUID_FEATURE_EDX_MCE
2399 | X86_CPUID_FEATURE_EDX_CX8
2400 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2401 //| RT_BIT_32(10) - not defined
2402 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2403 //| X86_CPUID_FEATURE_EDX_SEP
2404 | X86_CPUID_FEATURE_EDX_MTRR
2405 | X86_CPUID_FEATURE_EDX_PGE
2406 | X86_CPUID_FEATURE_EDX_MCA
2407 | X86_CPUID_FEATURE_EDX_CMOV
2408 | X86_CPUID_FEATURE_EDX_PAT /* 16 */
2409 | X86_CPUID_FEATURE_EDX_PSE36
2410 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2411 | X86_CPUID_FEATURE_EDX_CLFSH
2412 //| RT_BIT_32(20) - not defined
2413 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
2414 //| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2415 | X86_CPUID_FEATURE_EDX_MMX
2416 | X86_CPUID_FEATURE_EDX_FXSR
2417 | X86_CPUID_FEATURE_EDX_SSE
2418 | X86_CPUID_FEATURE_EDX_SSE2
2419 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2420 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading/cores - see below.
2421 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2422 //| RT_BIT_32(30) - not defined
2423 //| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2424 ;
2425 pStdFeatureLeaf->uEcx &= 0
2426 | X86_CPUID_FEATURE_ECX_SSE3
2427 | (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2428 //| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2429 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2430 | ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2431 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2432 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized yet.
2433 //| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2434 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2435 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2436 | X86_CPUID_FEATURE_ECX_SSSE3
2437 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2438 //| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2439 | (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2440 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2441 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
2442 //| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2443 //| X86_CPUID_FEATURE_ECX_PCID - not implemented yet.
2444 //| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2445 | (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2446 | (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2447 //| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2448 | (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2449 | (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2450 //| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2451 | (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2452 | (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2453 //| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2454 | (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2455 //| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2456 | (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2457 //| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2458 ;
2459
2460 if (pCpum->u8PortableCpuIdLevel > 0)
2461 {
2462 PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2463 PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2464 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2465 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2466 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2467 PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2468 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2469 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2470 PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2471 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2472 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2473 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2474 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2475 PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2476 PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2477 PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2478 PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2479 PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2480
2481 Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2482 | X86_CPUID_FEATURE_EDX_PSN
2483 | X86_CPUID_FEATURE_EDX_DS
2484 | X86_CPUID_FEATURE_EDX_ACPI
2485 | X86_CPUID_FEATURE_EDX_SS
2486 | X86_CPUID_FEATURE_EDX_TM
2487 | X86_CPUID_FEATURE_EDX_PBE
2488 )));
2489 Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2490 | X86_CPUID_FEATURE_ECX_CPLDS
2491 | X86_CPUID_FEATURE_ECX_VMX
2492 | X86_CPUID_FEATURE_ECX_SMX
2493 | X86_CPUID_FEATURE_ECX_EST
2494 | X86_CPUID_FEATURE_ECX_TM2
2495 | X86_CPUID_FEATURE_ECX_CNTXID
2496 | X86_CPUID_FEATURE_ECX_FMA
2497 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2498 | X86_CPUID_FEATURE_ECX_PDCM
2499 | X86_CPUID_FEATURE_ECX_DCA
2500 | X86_CPUID_FEATURE_ECX_OSXSAVE
2501 )));
2502 }
2503
2504 /* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2505 pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2506#ifdef VBOX_WITH_MULTI_CORE
2507 if (pVM->cCpus > 1)
2508 {
2509 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2510 core times the number of CPU cores per processor */
2511 pStdFeatureLeaf->uEbx |= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2512 pStdFeatureLeaf->uEdx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
2513 }
2514#endif
2515
2516 /* Force standard feature bits. */
2517 if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2518 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_PCLMUL;
2519 if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2520 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_MONITOR;
2521 if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2522 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_CX16;
2523 if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2524 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_SSE4_1;
2525 if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2526 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_SSE4_2;
2527 if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2528 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_MOVBE;
2529 if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2530 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_POPCNT;
2531 if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2532 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_AES;
2533 if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2534 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_XSAVE;
2535 if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2536 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_AVX;
2537 if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2538 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_RDRAND;
2539
2540 pStdFeatureLeaf = NULL; /* Must refetch! */
2541
2542 /* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2543 * AMD:
2544 * EAX: CPU model, family and stepping.
2545 *
2546 * ECX + EDX: Supported features. Only report features we can support.
2547 * Note! When enabling new features the Synthetic CPU and Portable CPUID
2548 * options may require adjusting (i.e. stripping what was enabled).
2549 * ASSUMES that this is ALWAYS the AMD defined feature set if present.
2550 *
2551 * EBX: Branding ID and package type (or reserved).
2552 *
2553 * Intel and probably most others:
2554 * EAX: 0
2555 * EBX: 0
2556 * ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2557 */
2558 PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2559 if (pExtFeatureLeaf)
2560 {
2561 AssertLogRelReturn(pExtFeatureLeaf->fSubLeafMask == 0, VERR_CPUM_IPE_2);
2562
2563 pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2564 | X86_CPUID_AMD_FEATURE_EDX_VME
2565 | X86_CPUID_AMD_FEATURE_EDX_DE
2566 | X86_CPUID_AMD_FEATURE_EDX_PSE
2567 | X86_CPUID_AMD_FEATURE_EDX_TSC
2568 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2569 //| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2570 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2571 | X86_CPUID_AMD_FEATURE_EDX_CX8
2572 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2573 //| RT_BIT_32(10) - reserved
2574 /* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2575 eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2576 //| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2577 | X86_CPUID_AMD_FEATURE_EDX_MTRR
2578 | X86_CPUID_AMD_FEATURE_EDX_PGE
2579 | X86_CPUID_AMD_FEATURE_EDX_MCA
2580 | X86_CPUID_AMD_FEATURE_EDX_CMOV
2581 | X86_CPUID_AMD_FEATURE_EDX_PAT
2582 | X86_CPUID_AMD_FEATURE_EDX_PSE36
2583 //| RT_BIT_32(18) - reserved
2584 //| RT_BIT_32(19) - reserved
2585 //| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2586 //| RT_BIT_32(21) - reserved
2587 | (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2588 | X86_CPUID_AMD_FEATURE_EDX_MMX
2589 | X86_CPUID_AMD_FEATURE_EDX_FXSR
2590 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
2591 //| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2592 | X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2593 //| RT_BIT_32(28) - reserved
2594 //| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2595 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2596 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
2597 ;
2598 pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2599 //| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2600 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
2601 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2602 /* Note: This could prevent teleporting from AMD to Intel CPUs! */
2603 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2604 | (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2605 | (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2606 | (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2607 | (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2608 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
2609 //| X86_CPUID_AMD_FEATURE_ECX_IBS
2610 //| X86_CPUID_AMD_FEATURE_ECX_XOP
2611 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2612 //| X86_CPUID_AMD_FEATURE_ECX_WDT
2613 //| RT_BIT_32(14) - reserved
2614 //| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2615 //| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2616 //| RT_BIT_32(17) - reserved
2617 //| RT_BIT_32(18) - reserved
2618 //| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2619 //| RT_BIT_32(20) - reserved
2620 //| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2621 //| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2622 //| RT_BIT_32(23) - reserved
2623 //| RT_BIT_32(24) - reserved
2624 //| RT_BIT_32(25) - reserved
2625 //| RT_BIT_32(26) - reserved
2626 //| RT_BIT_32(27) - reserved
2627 //| RT_BIT_32(28) - reserved
2628 //| RT_BIT_32(29) - reserved
2629 //| RT_BIT_32(30) - reserved
2630 //| RT_BIT_32(31) - reserved
2631 ;
2632#ifdef VBOX_WITH_MULTI_CORE
2633 if ( pVM->cCpus > 1
2634 && pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2635 pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2636#endif
2637
2638 if (pCpum->u8PortableCpuIdLevel > 0)
2639 {
2640 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2641 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2642 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2643 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2644 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2645 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2646 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2647 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2648 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2649 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2650 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2651 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2652 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2653 PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2654 PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2655
2656 Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2657 | X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2658 | X86_CPUID_AMD_FEATURE_ECX_OSVW
2659 | X86_CPUID_AMD_FEATURE_ECX_IBS
2660 | X86_CPUID_AMD_FEATURE_ECX_SKINIT
2661 | X86_CPUID_AMD_FEATURE_ECX_WDT
2662 | X86_CPUID_AMD_FEATURE_ECX_LWP
2663 | X86_CPUID_AMD_FEATURE_ECX_NODEID
2664 | X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2665 | UINT32_C(0xff964000)
2666 )));
2667 Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2668 | X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2669 | RT_BIT(18)
2670 | RT_BIT(19)
2671 | RT_BIT(21)
2672 | X86_CPUID_AMD_FEATURE_EDX_AXMMX
2673 | X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2674 | RT_BIT(28)
2675 )));
2676 }
2677
2678 /* Force extended feature bits. */
2679 if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2680 pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_ABM;
2681 if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2682 pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2683 if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2684 pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2685 if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2686 pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2687 if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2688 pExtFeatureLeaf->uEdx |= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2689 }
2690 pExtFeatureLeaf = NULL; /* Must refetch! */
2691
2692
2693 /* Cpuid 2:
2694 * Intel: (Nondeterministic) Cache and TLB information
2695 * AMD: Reserved
2696 * VIA: Reserved
2697 * Safe to expose. Restrict the number of calls to 1 since we don't
2698 * implement this kind of subleaves (is there hardware that does??).
2699 */
2700 uint32_t uSubLeaf = 0;
2701 PCPUMCPUIDLEAF pCurLeaf;
2702 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2703 {
2704 if ((pCurLeaf->uEax & 0xff) > 1)
2705 {
2706 LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2707 pCurLeaf->uEax &= UINT32_C(0xffffff01);
2708 }
2709 uSubLeaf++;
2710 }
2711
2712 /* Cpuid 3:
2713 * Intel: EAX, EBX - reserved (transmeta uses these)
2714 * ECX, EDX - Processor Serial Number if available, otherwise reserved
2715 * AMD: Reserved
2716 * VIA: Reserved
2717 * Safe to expose
2718 */
2719 pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2720 if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
2721 {
2722 uSubLeaf = 0;
2723 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
2724 {
2725 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2726 if (pCpum->u8PortableCpuIdLevel > 0)
2727 pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2728 uSubLeaf++;
2729 }
2730 }
2731
2732 /* Cpuid 4 + ECX:
2733 * Intel: Deterministic Cache Parameters Leaf.
2734 * AMD: Reserved
2735 * VIA: Reserved
2736 * Safe to expose, except for EAX:
2737 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
2738 * Bits 31-26: Maximum number of processor cores in this physical package**
2739 * Note: These SMP values are constant regardless of ECX
2740 */
2741 uSubLeaf = 0;
2742 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
2743 {
2744 pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
2745#ifdef VBOX_WITH_MULTI_CORE
2746 if ( pVM->cCpus > 1
2747 && pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2748 {
2749 AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
2750 /* One logical processor with possibly multiple cores. */
2751 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
2752 pCurLeaf->uEax |= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
2753 }
2754#endif
2755 uSubLeaf++;
2756 }
2757
2758 /* Cpuid 5: Monitor/mwait Leaf
2759 * Intel: ECX, EDX - reserved
2760 * EAX, EBX - Smallest and largest monitor line size
2761 * AMD: EDX - reserved
2762 * EAX, EBX - Smallest and largest monitor line size
2763 * ECX - extensions (ignored for now)
2764 * VIA: Reserved
2765 * Safe to expose
2766 */
2767 uSubLeaf = 0;
2768 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
2769 {
2770 pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2771 if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
2772 pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2773
2774 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2775 if (pConfig->enmMWaitExtensions)
2776 {
2777 pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
2778 /** @todo: for now we just expose host's MWAIT C-states, although conceptually
2779 it shall be part of our power management virtualization model */
2780#if 0
2781 /* MWAIT sub C-states */
2782 pCurLeaf->uEdx =
2783 (0 << 0) /* 0 in C0 */ |
2784 (2 << 4) /* 2 in C1 */ |
2785 (2 << 8) /* 2 in C2 */ |
2786 (2 << 12) /* 2 in C3 */ |
2787 (0 << 16) /* 0 in C4 */
2788 ;
2789#endif
2790 }
2791 else
2792 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2793 uSubLeaf++;
2794 }
2795
2796 /* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
2797 * Intel: Various stuff.
2798 * AMD: EAX, EBX, EDX - reserved.
2799 * ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
2800 * present. Same as intel.
2801 * VIA: ??
2802 *
2803 * We clear everything here for now.
2804 */
2805 cpumR3CpuIdZeroLeaf(pCpum, 6);
2806
2807 /* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
2808 * EAX: Number of sub leaves.
2809 * EBX+ECX+EDX: Feature flags
2810 *
2811 * We only have documentation for one sub-leaf, so clear all other (no need
2812 * to remove them as such, just set them to zero).
2813 *
2814 * Note! When enabling new features the Synthetic CPU and Portable CPUID
2815 * options may require adjusting (i.e. stripping what was enabled).
2816 */
2817 uSubLeaf = 0;
2818 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
2819 {
2820 switch (uSubLeaf)
2821 {
2822 case 0:
2823 {
2824 pCurLeaf->uEax = 0; /* Max ECX input is 0. */
2825 pCurLeaf->uEbx &= 0
2826 //| X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
2827 //| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
2828 //| RT_BIT(2) - reserved
2829 //| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
2830 //| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
2831 | (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
2832 //| RT_BIT(6) - reserved
2833 //| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
2834 //| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
2835 //| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
2836 //| X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
2837 //| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
2838 //| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
2839 | X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
2840 //| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
2841 //| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
2842 //| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
2843 //| RT_BIT(17) - reserved
2844 | (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
2845 //| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
2846 //| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
2847 //| RT_BIT(21) - reserved
2848 //| RT_BIT(22) - reserved
2849 | (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
2850 //| RT_BIT(24) - reserved
2851 //| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
2852 //| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
2853 //| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
2854 //| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
2855 //| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
2856 //| RT_BIT(30) - reserved
2857 //| RT_BIT(31) - reserved
2858 ;
2859 pCurLeaf->uEcx &= 0
2860 //| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
2861 ;
2862 pCurLeaf->uEdx &= 0;
2863
2864 if (pCpum->u8PortableCpuIdLevel > 0)
2865 {
2866 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
2867 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
2868 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
2869 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
2870 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
2871 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
2872 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
2873 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
2874 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
2875 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
2876 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
2877 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
2878 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
2879 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
2880 }
2881
2882 /* Force standard feature bits. */
2883 if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2884 pCurLeaf->uEbx |= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
2885 if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
2886 pCurLeaf->uEbx |= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
2887 if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2888 pCurLeaf->uEbx |= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
2889 break;
2890 }
2891
2892 default:
2893 /* Invalid index, all values are zero. */
2894 pCurLeaf->uEax = 0;
2895 pCurLeaf->uEbx = 0;
2896 pCurLeaf->uEcx = 0;
2897 pCurLeaf->uEdx = 0;
2898 break;
2899 }
2900 uSubLeaf++;
2901 }
2902
2903 /* Cpuid 8: Marked as reserved by Intel and AMD.
2904 * We zero this since we don't know what it may have been used for.
2905 */
2906 cpumR3CpuIdZeroLeaf(pCpum, 8);
2907
2908 /* Cpuid 9: Direct Cache Access (DCA) Parameters
2909 * Intel: EAX - Value of PLATFORM_DCA_CAP bits.
2910 * EBX, ECX, EDX - reserved.
2911 * AMD: Reserved
2912 * VIA: ??
2913 *
2914 * We zero this.
2915 */
2916 cpumR3CpuIdZeroLeaf(pCpum, 9);
2917
2918 /* Cpuid 0xa: Architectural Performance Monitor Features
2919 * Intel: EAX - Value of PLATFORM_DCA_CAP bits.
2920 * EBX, ECX, EDX - reserved.
2921 * AMD: Reserved
2922 * VIA: ??
2923 *
2924 * We zero this, for now at least.
2925 */
2926 cpumR3CpuIdZeroLeaf(pCpum, 10);
2927
2928 /* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
2929 * Intel: EAX - APCI ID shift right for next level.
2930 * EBX - Factory configured cores/threads at this level.
2931 * ECX - Level number (same as input) and level type (1,2,0).
2932 * EDX - Extended initial APIC ID.
2933 * AMD: Reserved
2934 * VIA: ??
2935 */
2936 uSubLeaf = 0;
2937 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
2938 {
2939 if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
2940 {
2941 uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
2942 if (bLevelType == 1)
2943 {
2944 /* Thread level - we don't do threads at the moment. */
2945 pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
2946 pCurLeaf->uEbx = 1;
2947 }
2948 else if (bLevelType == 2)
2949 {
2950 /* Core level. */
2951 pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
2952#ifdef VBOX_WITH_MULTI_CORE
2953 while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
2954 pCurLeaf->uEax++;
2955#endif
2956 pCurLeaf->uEbx = pVM->cCpus;
2957 }
2958 else
2959 {
2960 AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
2961 pCurLeaf->uEax = 0;
2962 pCurLeaf->uEbx = 0;
2963 pCurLeaf->uEcx = 0;
2964 }
2965 pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) | (uSubLeaf & 0xff);
2966 pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
2967 }
2968 else
2969 {
2970 Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INTEL);
2971 pCurLeaf->uEax = 0;
2972 pCurLeaf->uEbx = 0;
2973 pCurLeaf->uEcx = 0;
2974 pCurLeaf->uEdx = 0;
2975 }
2976 uSubLeaf++;
2977 }
2978
2979 /* Cpuid 0xc: Marked as reserved by Intel and AMD.
2980 * We zero this since we don't know what it may have been used for.
2981 */
2982 cpumR3CpuIdZeroLeaf(pCpum, 12);
2983
2984 /* Cpuid 0xd + ECX: Processor Extended State Enumeration
2985 * ECX=0: EAX - Valid bits in XCR0[31:0].
2986 * EBX - Maximum state size as per current XCR0 value.
2987 * ECX - Maximum state size for all supported features.
2988 * EDX - Valid bits in XCR0[63:32].
2989 * ECX=1: EAX - Various X-features.
2990 * EBX - Maximum state size as per current XCR0|IA32_XSS value.
2991 * ECX - Valid bits in IA32_XSS[31:0].
2992 * EDX - Valid bits in IA32_XSS[63:32].
2993 * ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
2994 * if the bit invalid all four registers are set to zero.
2995 * EAX - The state size for this feature.
2996 * EBX - The state byte offset of this feature.
2997 * ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
2998 * EDX - Reserved, but is set to zero if invalid sub-leaf index.
2999 *
3000 * Clear them all as we don't currently implement extended CPU state.
3001 */
3002 /* Figure out the supported XCR0/XSS mask component. */
3003 uint64_t fGuestXcr0Mask = 0;
3004 pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3005 if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3006 {
3007 fGuestXcr0Mask = XSAVE_C_X87 | XSAVE_C_SSE;
3008 if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3009 fGuestXcr0Mask |= XSAVE_C_YMM;
3010 pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3011 if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3012 fGuestXcr0Mask |= XSAVE_C_ZMM_16HI | XSAVE_C_ZMM_HI256 | XSAVE_C_OPMASK;
3013 fGuestXcr0Mask &= pCpum->fXStateHostMask;
3014 }
3015 pStdFeatureLeaf = NULL;
3016 pCpum->fXStateGuestMask = fGuestXcr0Mask;
3017
3018 /* Work the sub-leaves. */
3019 for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3020 {
3021 pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3022 if (pCurLeaf)
3023 {
3024 if (fGuestXcr0Mask)
3025 {
3026 switch (uSubLeaf)
3027 {
3028 case 0:
3029 pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3030 pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3031 continue;
3032 case 1:
3033 pCurLeaf->uEax &= 0;
3034 pCurLeaf->uEcx &= 0;
3035 pCurLeaf->uEdx &= 0;
3036 continue;
3037 default:
3038 if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3039 {
3040 AssertLogRel(!(pCurLeaf->uEcx & 1));
3041 pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3042 pCurLeaf->uEdx = 0; /* it's reserved... */
3043 continue;
3044 }
3045 break;
3046 }
3047 }
3048
3049 /* Clear the leaf. */
3050 pCurLeaf->uEax = 0;
3051 pCurLeaf->uEbx = 0;
3052 pCurLeaf->uEcx = 0;
3053 pCurLeaf->uEdx = 0;
3054 }
3055 }
3056
3057 /* Cpuid 0xe: Marked as reserved by Intel and AMD.
3058 * We zero this since we don't know what it may have been used for.
3059 */
3060 cpumR3CpuIdZeroLeaf(pCpum, 14);
3061
3062 /* Cpuid 0xf + ECX: Platform qualifity of service monitoring (PQM).
3063 * We zero this as we don't currently virtualize PQM.
3064 */
3065 cpumR3CpuIdZeroLeaf(pCpum, 15);
3066
3067 /* Cpuid 0x10 + ECX: Platform qualifity of service enforcement (PQE).
3068 * We zero this as we don't currently virtualize PQE.
3069 */
3070 cpumR3CpuIdZeroLeaf(pCpum, 16);
3071
3072 /* Cpuid 0x11: Marked as reserved by Intel and AMD.
3073 * We zero this since we don't know what it may have been used for.
3074 */
3075 cpumR3CpuIdZeroLeaf(pCpum, 17);
3076
3077 /* Cpuid 0x12 + ECX: SGX resource enumeration.
3078 * We zero this as we don't currently virtualize this.
3079 */
3080 cpumR3CpuIdZeroLeaf(pCpum, 18);
3081
3082 /* Cpuid 0x13: Marked as reserved by Intel and AMD.
3083 * We zero this since we don't know what it may have been used for.
3084 */
3085 cpumR3CpuIdZeroLeaf(pCpum, 19);
3086
3087 /* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3088 * We zero this as we don't currently virtualize this.
3089 */
3090 cpumR3CpuIdZeroLeaf(pCpum, 20);
3091
3092 /* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3093 * Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3094 * EAX - denominator (unsigned).
3095 * EBX - numerator (unsigned).
3096 * ECX, EDX - reserved.
3097 * AMD: Reserved / undefined / not implemented.
3098 * VIA: Reserved / undefined / not implemented.
3099 * We zero this as we don't currently virtualize this.
3100 */
3101 cpumR3CpuIdZeroLeaf(pCpum, 21);
3102
3103 /* Cpuid 0x16: Processor frequency info
3104 * Intel: EAX - Core base frequency in MHz.
3105 * EBX - Core maximum frequency in MHz.
3106 * ECX - Bus (reference) frequency in MHz.
3107 * EDX - Reserved.
3108 * AMD: Reserved / undefined / not implemented.
3109 * VIA: Reserved / undefined / not implemented.
3110 * We zero this as we don't currently virtualize this.
3111 */
3112 cpumR3CpuIdZeroLeaf(pCpum, 22);
3113
3114 /* Cpuid 0x17..0x10000000: Unknown.
3115 * We don't know these and what they mean, so remove them. */
3116 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3117 UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3118
3119
3120 /* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3121 * We remove all these as we're a hypervisor and must provide our own.
3122 */
3123 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3124 UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3125
3126
3127 /* Cpuid 0x80000000 is harmless. */
3128
3129 /* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3130
3131 /* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3132
3133 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3134 * Safe to pass on to the guest.
3135 *
3136 * AMD: 0x800000005 L1 cache information
3137 * 0x800000006 L2/L3 cache information
3138 * Intel: 0x800000005 reserved
3139 * 0x800000006 L2 cache information
3140 * VIA: 0x800000005 TLB and L1 cache information
3141 * 0x800000006 L2 cache information
3142 */
3143
3144 /* Cpuid 0x800000007: Advanced Power Management Information.
3145 * AMD: EAX: Processor feedback capabilities.
3146 * EBX: RAS capabilites.
3147 * ECX: Advanced power monitoring interface.
3148 * EDX: Enhanced power management capabilities.
3149 * Intel: EAX, EBX, ECX - reserved.
3150 * EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3151 * VIA: Reserved
3152 * We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3153 */
3154 uSubLeaf = 0;
3155 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3156 {
3157 pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3158 if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3159 {
3160 pCurLeaf->uEdx &= 0
3161 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
3162 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
3163 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
3164 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3165 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
3166 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
3167 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
3168 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3169#if 0 /*
3170 * We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
3171 * Linux kernels blindly assume that the AMD performance counters work
3172 * if this is set for 64 bits guests. (Can't really find a CPUID feature
3173 * bit for them though.)
3174 */
3175 /** @todo need to recheck this with new MSR emulation. */
3176 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3177#endif
3178 //| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3179 //| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3180 //| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3181 //| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3182 | 0;
3183 }
3184 else
3185 pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3186 if (pConfig->fInvariantTsc)
3187 pCurLeaf->uEdx |= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3188 uSubLeaf++;
3189 }
3190
3191 /* Cpuid 0x80000008:
3192 * AMD: EBX, EDX - reserved
3193 * EAX: Virtual/Physical/Guest address Size
3194 * ECX: Number of cores + APICIdCoreIdSize
3195 * Intel: EAX: Virtual/Physical address Size
3196 * EBX, ECX, EDX - reserved
3197 * VIA: EAX: Virtual/Physical address Size
3198 * EBX, ECX, EDX - reserved
3199 *
3200 * We only expose the virtual+pysical address size to the guest atm.
3201 * On AMD we set the core count, but not the apic id stuff as we're
3202 * currently not doing the apic id assignments in a complatible manner.
3203 */
3204 uSubLeaf = 0;
3205 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3206 {
3207 pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3208 pCurLeaf->uEbx = 0; /* reserved */
3209 pCurLeaf->uEdx = 0; /* reserved */
3210
3211 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3212 * Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3213 pCurLeaf->uEcx = 0;
3214#ifdef VBOX_WITH_MULTI_CORE
3215 if ( pVM->cCpus > 1
3216 && pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3217 pCurLeaf->uEcx |= (pVM->cCpus - 1) & UINT32_C(0xff);
3218#endif
3219 uSubLeaf++;
3220 }
3221
3222 /* Cpuid 0x80000009: Reserved
3223 * We zero this since we don't know what it may have been used for.
3224 */
3225 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3226
3227 /* Cpuid 0x8000000a: SVM Information
3228 * AMD: EAX - SVM revision.
3229 * EBX - Number of ASIDs.
3230 * ECX - Reserved.
3231 * EDX - SVM Feature identification.
3232 * We clear all as we currently does not virtualize SVM.
3233 */
3234 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3235
3236 /* Cpuid 0x8000000b thru 0x80000018: Reserved
3237 * We clear these as we don't know what purpose they might have. */
3238 for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3239 cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3240
3241 /* Cpuid 0x80000019: TLB configuration
3242 * Seems to be harmless, pass them thru as is. */
3243
3244 /* Cpuid 0x8000001a: Peformance optimization identifiers.
3245 * Strip anything we don't know what is or addresses feature we don't implement. */
3246 uSubLeaf = 0;
3247 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3248 {
3249 pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3250 | RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3251 //| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3252 ;
3253 pCurLeaf->uEbx = 0; /* reserved */
3254 pCurLeaf->uEcx = 0; /* reserved */
3255 pCurLeaf->uEdx = 0; /* reserved */
3256 uSubLeaf++;
3257 }
3258
3259 /* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3260 * Clear this as we don't currently virtualize this feature. */
3261 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3262
3263 /* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3264 * Clear this as we don't currently virtualize this feature. */
3265 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3266
3267 /* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3268 * We need to sanitize the cores per cache (EAX[25:14]).
3269 *
3270 * This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3271 * and EDX[2] are reserved here, and EAX[14:25] is documented having a
3272 * slightly different meaning.
3273 */
3274 uSubLeaf = 0;
3275 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3276 {
3277#ifdef VBOX_WITH_MULTI_CORE
3278 uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3279 if (cCores > pVM->cCpus)
3280 cCores = pVM->cCpus;
3281 pCurLeaf->uEax &= UINT32_C(0x00003fff);
3282 pCurLeaf->uEax |= ((cCores - 1) & 0xfff) << 14;
3283#else
3284 pCurLeaf->uEax &= UINT32_C(0x00003fff);
3285#endif
3286 uSubLeaf++;
3287 }
3288
3289 /* Cpuid 0x8000001e: Get APIC / unit / node information.
3290 * If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3291 * setup, we have one compute unit with all the cores in it. Single node.
3292 */
3293 uSubLeaf = 0;
3294 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3295 {
3296 pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3297 if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3298 {
3299#ifdef VBOX_WITH_MULTI_CORE
3300 pCurLeaf->uEbx = pVM->cCpus < 0x100
3301 ? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3302#else
3303 pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3304#endif
3305 pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3306 }
3307 else
3308 {
3309 Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3310 pCurLeaf->uEbx = 0; /* Reserved. */
3311 pCurLeaf->uEcx = 0; /* Reserved. */
3312 }
3313 pCurLeaf->uEdx = 0; /* Reserved. */
3314 uSubLeaf++;
3315 }
3316
3317 /* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3318 * We don't know these and what they mean, so remove them. */
3319 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3320 UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3321
3322 /* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3323 * Just pass it thru for now. */
3324
3325 /* Cpuid 0x8fffffff: Mystery hammer time leaf!
3326 * Just pass it thru for now. */
3327
3328 /* Cpuid 0xc0000000: Centaur stuff.
3329 * Harmless, pass it thru. */
3330
3331 /* Cpuid 0xc0000001: Centaur features.
3332 * VIA: EAX - Family, model, stepping.
3333 * EDX - Centaur extended feature flags. Nothing interesting, except may
3334 * FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3335 * EBX, ECX - reserved.
3336 * We keep EAX but strips the rest.
3337 */
3338 uSubLeaf = 0;
3339 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3340 {
3341 pCurLeaf->uEbx = 0;
3342 pCurLeaf->uEcx = 0;
3343 pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3344 uSubLeaf++;
3345 }
3346
3347 /* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3348 * We only have fixed stale values, but should be harmless. */
3349
3350 /* Cpuid 0xc0000003: Reserved.
3351 * We zero this since we don't know what it may have been used for.
3352 */
3353 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3354
3355 /* Cpuid 0xc0000004: Centaur Performance Info.
3356 * We only have fixed stale values, but should be harmless. */
3357
3358
3359 /* Cpuid 0xc0000005...0xcfffffff: Unknown.
3360 * We don't know these and what they mean, so remove them. */
3361 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3362 UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3363
3364 return VINF_SUCCESS;
3365#undef PORTABLE_DISABLE_FEATURE_BIT
3366#undef PORTABLE_CLEAR_BITS_WHEN
3367}
3368
3369
3370/**
3371 * Reads a value in /CPUM/IsaExts/ node.
3372 *
3373 * @returns VBox status code (error message raised).
3374 * @param pVM The VM handle (for errors).
3375 * @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3376 * @param pszValueName The value / extension name.
3377 * @param penmValue Where to return the choice.
3378 * @param enmDefault The default choice.
3379 */
3380static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3381 CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3382{
3383 /*
3384 * Try integer encoding first.
3385 */
3386 uint64_t uValue;
3387 int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3388 if (RT_SUCCESS(rc))
3389 switch (uValue)
3390 {
3391 case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3392 case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3393 case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3394 case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3395 default:
3396 return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3397 "Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3398 pszValueName, uValue);
3399 }
3400 /*
3401 * If missing, use default.
3402 */
3403 else if (rc == VERR_CFGM_VALUE_NOT_FOUND || rc == VERR_CFGM_NO_PARENT)
3404 *penmValue = enmDefault;
3405 else
3406 {
3407 if (rc == VERR_CFGM_NOT_INTEGER)
3408 {
3409 /*
3410 * Not an integer, try read it as a string.
3411 */
3412 char szValue[32];
3413 rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3414 if (RT_SUCCESS(rc))
3415 {
3416 RTStrToLower(szValue);
3417 size_t cchValue = strlen(szValue);
3418#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3419 if ( EQ("disabled") || EQ("disable") || EQ("off") || EQ("no"))
3420 *penmValue = CPUMISAEXTCFG_DISABLED;
3421 else if (EQ("enabled") || EQ("enable") || EQ("on") || EQ("yes"))
3422 *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3423 else if (EQ("forced") || EQ("force") || EQ("always"))
3424 *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3425 else if (EQ("portable"))
3426 *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3427 else if (EQ("default") || EQ("def"))
3428 *penmValue = enmDefault;
3429 else
3430 return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3431 "Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3432 pszValueName, uValue);
3433#undef EQ
3434 }
3435 }
3436 if (RT_FAILURE(rc))
3437 return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3438 }
3439 return VINF_SUCCESS;
3440}
3441
3442
3443/**
3444 * Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3445 *
3446 * @returns VBox status code (error message raised).
3447 * @param pVM The VM handle (for errors).
3448 * @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3449 * @param pszValueName The value / extension name.
3450 * @param penmValue Where to return the choice.
3451 * @param enmDefault The default choice.
3452 * @param fAllowed Allowed choice. Applied both to the result and to
3453 * the default value.
3454 */
3455static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3456 CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3457{
3458 int rc;
3459 if (fAllowed)
3460 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3461 else
3462 {
3463 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /*enmDefault*/);
3464 if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3465 LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3466 *penmValue = CPUMISAEXTCFG_DISABLED;
3467 }
3468 return rc;
3469}
3470
3471
3472/**
3473 * Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3474 *
3475 * @returns VBox status code (error message raised).
3476 * @param pVM The VM handle (for errors).
3477 * @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3478 * @param pCpumCfg The /CPUM node (can be NULL).
3479 * @param pszValueName The value / extension name.
3480 * @param penmValue Where to return the choice.
3481 * @param enmDefault The default choice.
3482 */
3483static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3484 CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3485{
3486 if (CFGMR3Exists(pCpumCfg, pszValueName))
3487 {
3488 if (!CFGMR3Exists(pIsaExts, pszValueName))
3489 LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3490 else
3491 return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3492 "Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3493 pszValueName, pszValueName);
3494
3495 bool fLegacy;
3496 int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3497 if (RT_SUCCESS(rc))
3498 {
3499 *penmValue = fLegacy;
3500 return VINF_SUCCESS;
3501 }
3502 return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3503 }
3504
3505 return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3506}
3507
3508
3509static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3510{
3511 int rc;
3512
3513 /** @cfgm{/CPUM/SyntheticCpu, boolean, false}
3514 * Enables the Synthetic CPU. The Vendor ID and Processor Name are
3515 * completely overridden by VirtualBox custom strings. Some
3516 * CPUID information is withheld, like the cache info.
3517 *
3518 * This is obsoleted by PortableCpuIdLevel. */
3519 rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pConfig->fSyntheticCpu, false);
3520 AssertRCReturn(rc, rc);
3521
3522 /** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3523 * When non-zero CPUID features that could cause portability issues will be
3524 * stripped. The higher the value the more features gets stripped. Higher
3525 * values should only be used when older CPUs are involved since it may
3526 * harm performance and maybe also cause problems with specific guests. */
3527 rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, pConfig->fSyntheticCpu ? 1 : 0);
3528 AssertLogRelRCReturn(rc, rc);
3529
3530 /** @cfgm{/CPUM/GuestCpuName, string}
3531 * The name of the CPU we're to emulate. The default is the host CPU.
3532 * Note! CPUs other than "host" one is currently unsupported. */
3533 rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3534 AssertLogRelRCReturn(rc, rc);
3535
3536 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3537 * Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3538 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3539 * This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3540 */
3541 rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3542 AssertLogRelRCReturn(rc, rc);
3543
3544 /** @cfgm{/CPUM/InvariantTsc, boolean, complicated}
3545 * Set the invariant TSC flag in 0x80000007 if true, otherwas take default
3546 * action. By default the flag is passed thru as is from the host CPU, except
3547 * on AMD CPUs where it's suppressed to avoid trouble from linux assuming we
3548 * virtualize performance counters.
3549 */
3550 rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, false);
3551 AssertLogRelRCReturn(rc, rc);
3552
3553 /** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3554 * Restrict the reported CPU family+model+stepping of intel CPUs. This is
3555 * probably going to be a temporary hack, so don't depend on this.
3556 * The 1st byte of the value is the stepping, the 2nd byte value is the model
3557 * number and the 3rd byte value is the family, and the 4th value must be zero.
3558 */
3559 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3560 AssertLogRelRCReturn(rc, rc);
3561
3562 /** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3563 * The last standard leaf to keep. The actual last value that is stored in EAX
3564 * is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3565 * removed. (This works independently of and differently from NT4LeafLimit.)
3566 * The default is usually set to what we're able to reasonably sanitize.
3567 */
3568 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3569 AssertLogRelRCReturn(rc, rc);
3570
3571 /** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3572 * The last extended leaf to keep. The actual last value that is stored in EAX
3573 * is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3574 * leaf are removed. The default is set to what we're able to sanitize.
3575 */
3576 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3577 AssertLogRelRCReturn(rc, rc);
3578
3579 /** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3580 * The last extended leaf to keep. The actual last value that is stored in EAX
3581 * is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3582 * leaf are removed. The default is set to what we're able to sanitize.
3583 */
3584 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3585 AssertLogRelRCReturn(rc, rc);
3586
3587
3588 /*
3589 * Instruction Set Architecture (ISA) Extensions.
3590 */
3591 PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3592 if (pIsaExts)
3593 {
3594 rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3595 "CMPXCHG16B"
3596 "|MONITOR"
3597 "|MWaitExtensions"
3598 "|SSE4.1"
3599 "|SSE4.2"
3600 "|AESNI"
3601 "|PCLMUL"
3602 "|POPCNT"
3603 "|MOVBE"
3604 "|RDRAND"
3605 "|RDSEED"
3606 "|CLFLUSHOPT"
3607 , "" /*pszValidNodes*/, "CPUM" /*pszWho*/, 0 /*uInstance*/);
3608 if (RT_FAILURE(rc))
3609 return rc;
3610 }
3611
3612 /** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
3613 * Expose CMPXCHG16B to the guest if supported by the host. For the time
3614 * being the default is to only do this for VMs with nested paging and AMD-V or
3615 * unrestricted guest mode.
3616 */
3617 rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
3618 AssertLogRelRCReturn(rc, rc);
3619
3620 /** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
3621 * Expose MONITOR/MWAIT instructions to the guest.
3622 */
3623 rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
3624 AssertLogRelRCReturn(rc, rc);
3625
3626 /** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
3627 * Expose MWAIT extended features to the guest. For now we expose just MWAIT
3628 * break on interrupt feature (bit 1).
3629 */
3630 rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
3631 AssertLogRelRCReturn(rc, rc);
3632
3633 /** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
3634 * Expose SSE4.1 to the guest if available.
3635 */
3636 rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
3637 AssertLogRelRCReturn(rc, rc);
3638
3639 /** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
3640 * Expose SSE4.2 to the guest if available.
3641 */
3642 rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
3643 AssertLogRelRCReturn(rc, rc);
3644
3645 bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
3646 && pVM->cpum.s.HostFeatures.fXSaveRstor
3647 && pVM->cpum.s.HostFeatures.fOpSysXSaveRstor;
3648 /** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
3649 * Expose XSAVE/XRSTOR to the guest if available. For the time being the
3650 * default is to only expose this to VMs with nested paging and AMD-V or
3651 * unrestricted guest execution mode. Not possible to force this one without
3652 * host support at the moment.
3653 */
3654 rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
3655 fMayHaveXSave /*fAllowed*/);
3656 AssertLogRelRCReturn(rc, rc);
3657
3658 /** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
3659 * Expose the AVX instruction set extensions to the guest if available and
3660 * XSAVE is exposed too. For the time being the default is to only expose this
3661 * to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3662 */
3663 rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
3664 fMayHaveXSave && pConfig->enmXSave /*fAllowed*/);
3665 AssertLogRelRCReturn(rc, rc);
3666
3667 /** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
3668 * Expose the AVX2 instruction set extensions to the guest if available and
3669 * XSAVE is exposed too. For the time being the default is to only expose this
3670 * to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3671 */
3672 rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec,
3673 fMayHaveXSave && pConfig->enmXSave /*fAllowed*/);
3674 AssertLogRelRCReturn(rc, rc);
3675
3676 /** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
3677 * Whether to expose the AES instructions to the guest. For the time being the
3678 * default is to only do this for VMs with nested paging and AMD-V or
3679 * unrestricted guest mode.
3680 */
3681 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
3682 AssertLogRelRCReturn(rc, rc);
3683
3684 /** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
3685 * Whether to expose the PCLMULQDQ instructions to the guest. For the time
3686 * being the default is to only do this for VMs with nested paging and AMD-V or
3687 * unrestricted guest mode.
3688 */
3689 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
3690 AssertLogRelRCReturn(rc, rc);
3691
3692 /** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
3693 * Whether to expose the POPCNT instructions to the guest. For the time
3694 * being the default is to only do this for VMs with nested paging and AMD-V or
3695 * unrestricted guest mode.
3696 */
3697 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
3698 AssertLogRelRCReturn(rc, rc);
3699
3700 /** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
3701 * Whether to expose the MOVBE instructions to the guest. For the time
3702 * being the default is to only do this for VMs with nested paging and AMD-V or
3703 * unrestricted guest mode.
3704 */
3705 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
3706 AssertLogRelRCReturn(rc, rc);
3707
3708 /** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
3709 * Whether to expose the RDRAND instructions to the guest. For the time being
3710 * the default is to only do this for VMs with nested paging and AMD-V or
3711 * unrestricted guest mode.
3712 */
3713 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
3714 AssertLogRelRCReturn(rc, rc);
3715
3716 /** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
3717 * Whether to expose the RDSEED instructions to the guest. For the time being
3718 * the default is to only do this for VMs with nested paging and AMD-V or
3719 * unrestricted guest mode.
3720 */
3721 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
3722 AssertLogRelRCReturn(rc, rc);
3723
3724 /** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
3725 * Whether to expose the CLFLUSHOPT instructions to the guest. For the time
3726 * being the default is to only do this for VMs with nested paging and AMD-V or
3727 * unrestricted guest mode.
3728 */
3729 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
3730 AssertLogRelRCReturn(rc, rc);
3731
3732
3733 /* AMD: */
3734
3735 /** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
3736 * Whether to expose the AMD ABM instructions to the guest. For the time
3737 * being the default is to only do this for VMs with nested paging and AMD-V or
3738 * unrestricted guest mode.
3739 */
3740 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
3741 AssertLogRelRCReturn(rc, rc);
3742
3743 /** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
3744 * Whether to expose the AMD SSE4A instructions to the guest. For the time
3745 * being the default is to only do this for VMs with nested paging and AMD-V or
3746 * unrestricted guest mode.
3747 */
3748 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
3749 AssertLogRelRCReturn(rc, rc);
3750
3751 /** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
3752 * Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
3753 * the time being the default is to only do this for VMs with nested paging and
3754 * AMD-V or unrestricted guest mode.
3755 */
3756 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
3757 AssertLogRelRCReturn(rc, rc);
3758
3759 /** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
3760 * Whether to expose the AMD 3D Now! prefetch instructions to the guest.
3761 * For the time being the default is to only do this for VMs with nested paging
3762 * and AMD-V or unrestricted guest mode.
3763 */
3764 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
3765 AssertLogRelRCReturn(rc, rc);
3766
3767 /** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
3768 * Whether to expose the AMD's MMX Extensions to the guest. For the time being
3769 * the default is to only do this for VMs with nested paging and AMD-V or
3770 * unrestricted guest mode.
3771 */
3772 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
3773 AssertLogRelRCReturn(rc, rc);
3774
3775 return VINF_SUCCESS;
3776}
3777
3778
3779/**
3780 * Initializes the emulated CPU's CPUID & MSR information.
3781 *
3782 * @returns VBox status code.
3783 * @param pVM Pointer to the VM.
3784 */
3785int cpumR3InitCpuIdAndMsrs(PVM pVM)
3786{
3787 PCPUM pCpum = &pVM->cpum.s;
3788 PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
3789
3790 /*
3791 * Read the configuration.
3792 */
3793 CPUMCPUIDCONFIG Config;
3794 RT_ZERO(Config);
3795
3796 int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
3797 AssertRCReturn(rc, rc);
3798
3799 /*
3800 * Get the guest CPU data from the database and/or the host.
3801 *
3802 * The CPUID and MSRs are currently living on the regular heap to avoid
3803 * fragmenting the hyper heap (and because there isn't/wasn't any realloc
3804 * API for the hyper heap). This means special cleanup considerations.
3805 */
3806 rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
3807 if (RT_FAILURE(rc))
3808 return rc == VERR_CPUM_DB_CPU_NOT_FOUND
3809 ? VMSetError(pVM, rc, RT_SRC_POS,
3810 "Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
3811 : rc;
3812
3813 /** @cfgm{/CPUM/MSRs/[Name]/[First|Last|Type|Value|...],}
3814 * Overrides the guest MSRs.
3815 */
3816 rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
3817
3818 /** @cfgm{/CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
3819 * Overrides the CPUID leaf values (from the host CPU usually) used for
3820 * calculating the guest CPUID leaves. This can be used to preserve the CPUID
3821 * values when moving a VM to a different machine. Another use is restricting
3822 * (or extending) the feature set exposed to the guest. */
3823 if (RT_SUCCESS(rc))
3824 rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
3825
3826 if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
3827 rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
3828 "Found unsupported configuration node '/CPUM/CPUID/'. "
3829 "Please use IMachine::setCPUIDLeaf() instead.");
3830
3831 /*
3832 * Pre-explode the CPUID info.
3833 */
3834 if (RT_SUCCESS(rc))
3835 rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
3836
3837 /*
3838 * Sanitize the cpuid information passed on to the guest.
3839 */
3840 if (RT_SUCCESS(rc))
3841 {
3842 rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
3843 if (RT_SUCCESS(rc))
3844 {
3845 cpumR3CpuIdLimitLeaves(pCpum, &Config);
3846 cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
3847 }
3848 }
3849
3850 /*
3851 * Plant our own hypervisor CPUID leaves.
3852 */
3853 if (RT_SUCCESS(rc))
3854 rc = cpumR3CpuIdPlantHypervisorLeaves(pCpum, &Config);
3855
3856 /*
3857 * MSR fudging.
3858 */
3859 if (RT_SUCCESS(rc))
3860 {
3861 /** @cfgm{/CPUM/FudgeMSRs, boolean, true}
3862 * Fudges some common MSRs if not present in the selected CPU database entry.
3863 * This is for trying to keep VMs running when moved between different hosts
3864 * and different CPU vendors. */
3865 bool fEnable;
3866 rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
3867 if (RT_SUCCESS(rc) && fEnable)
3868 {
3869 rc = cpumR3MsrApplyFudge(pVM);
3870 AssertLogRelRC(rc);
3871 }
3872 }
3873 if (RT_SUCCESS(rc))
3874 {
3875 /*
3876 * Move the MSR and CPUID arrays over on the hypervisor heap, and explode
3877 * guest CPU features again.
3878 */
3879 void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
3880 int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
3881 pCpum->GuestInfo.cCpuIdLeaves);
3882 RTMemFree(pvFree);
3883
3884 pvFree = pCpum->GuestInfo.paMsrRangesR3;
3885 int rc2 = MMHyperDupMem(pVM, pvFree,
3886 sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
3887 MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
3888 RTMemFree(pvFree);
3889 AssertLogRelRCReturn(rc1, rc1);
3890 AssertLogRelRCReturn(rc2, rc2);
3891
3892 pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
3893 pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
3894 cpumR3MsrRegStats(pVM);
3895
3896
3897 /*
3898 * Some more configuration that we're applying at the end of everything
3899 * via the CPUMSetGuestCpuIdFeature API.
3900 */
3901
3902 /* Check if PAE was explicitely enabled by the user. */
3903 bool fEnable;
3904 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
3905 AssertRCReturn(rc, rc);
3906 if (fEnable)
3907 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3908
3909 /* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
3910 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
3911 AssertRCReturn(rc, rc);
3912 if (fEnable)
3913 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3914
3915 /* We don't enable the Hypervisor Present bit by default, but it may be needed by some guests. */
3916 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false);
3917 AssertRCReturn(rc, rc);
3918 if (fEnable)
3919 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
3920
3921 return VINF_SUCCESS;
3922 }
3923
3924 /*
3925 * Failed before switching to hyper heap.
3926 */
3927 RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
3928 pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
3929 RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3930 pCpum->GuestInfo.paMsrRangesR3 = NULL;
3931 return rc;
3932}
3933
3934
3935
3936/*
3937 *
3938 *
3939 * Saved state related code.
3940 * Saved state related code.
3941 * Saved state related code.
3942 *
3943 *
3944 */
3945
3946/**
3947 * Called both in pass 0 and the final pass.
3948 *
3949 * @param pVM Pointer to the VM.
3950 * @param pSSM The saved state handle.
3951 */
3952void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
3953{
3954 /*
3955 * Save all the CPU ID leaves.
3956 */
3957 SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
3958 SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
3959 SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
3960 sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
3961
3962 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
3963
3964 /*
3965 * Save a good portion of the raw CPU IDs as well as they may come in
3966 * handy when validating features for raw mode.
3967 */
3968 CPUMCPUID aRawStd[16];
3969 for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
3970 ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
3971 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
3972 SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
3973
3974 CPUMCPUID aRawExt[32];
3975 for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
3976 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
3977 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
3978 SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
3979}
3980
3981
3982static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
3983{
3984 uint32_t cCpuIds;
3985 int rc = SSMR3GetU32(pSSM, &cCpuIds);
3986 if (RT_SUCCESS(rc))
3987 {
3988 if (cCpuIds < 64)
3989 {
3990 for (uint32_t i = 0; i < cCpuIds; i++)
3991 {
3992 CPUMCPUID CpuId;
3993 rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
3994 if (RT_FAILURE(rc))
3995 break;
3996
3997 CPUMCPUIDLEAF NewLeaf;
3998 NewLeaf.uLeaf = uBase + i;
3999 NewLeaf.uSubLeaf = 0;
4000 NewLeaf.fSubLeafMask = 0;
4001 NewLeaf.uEax = CpuId.uEax;
4002 NewLeaf.uEbx = CpuId.uEbx;
4003 NewLeaf.uEcx = CpuId.uEcx;
4004 NewLeaf.uEdx = CpuId.uEdx;
4005 NewLeaf.fFlags = 0;
4006 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4007 }
4008 }
4009 else
4010 rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4011 }
4012 if (RT_FAILURE(rc))
4013 {
4014 RTMemFree(*ppaLeaves);
4015 *ppaLeaves = NULL;
4016 *pcLeaves = 0;
4017 }
4018 return rc;
4019}
4020
4021
4022static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
4023{
4024 *ppaLeaves = NULL;
4025 *pcLeaves = 0;
4026
4027 int rc;
4028 if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4029 {
4030 /*
4031 * The new format. Starts by declaring the leave size and count.
4032 */
4033 uint32_t cbLeaf;
4034 SSMR3GetU32(pSSM, &cbLeaf);
4035 uint32_t cLeaves;
4036 rc = SSMR3GetU32(pSSM, &cLeaves);
4037 if (RT_SUCCESS(rc))
4038 {
4039 if (cbLeaf == sizeof(**ppaLeaves))
4040 {
4041 if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4042 {
4043 /*
4044 * Load the leaves one by one.
4045 *
4046 * The uPrev stuff is a kludge for working around a week worth of bad saved
4047 * states during the CPUID revamp in March 2015. We saved too many leaves
4048 * due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4049 * garbage entires at the end of the array when restoring. We also had
4050 * a subleaf insertion bug that triggered with the leaf 4 stuff below,
4051 * this kludge doesn't deal correctly with that, but who cares...
4052 */
4053 uint32_t uPrev = 0;
4054 for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4055 {
4056 CPUMCPUIDLEAF Leaf;
4057 rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
4058 if (RT_SUCCESS(rc))
4059 {
4060 if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
4061 || Leaf.uLeaf >= uPrev)
4062 {
4063 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4064 uPrev = Leaf.uLeaf;
4065 }
4066 else
4067 uPrev = UINT32_MAX;
4068 }
4069 }
4070 }
4071 else
4072 rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
4073 "Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
4074 }
4075 else
4076 rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
4077 "CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
4078 }
4079 }
4080 else
4081 {
4082 /*
4083 * The old format with its three inflexible arrays.
4084 */
4085 rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
4086 if (RT_SUCCESS(rc))
4087 rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
4088 if (RT_SUCCESS(rc))
4089 rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
4090 if (RT_SUCCESS(rc))
4091 {
4092 /*
4093 * Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
4094 */
4095 PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(*ppaLeaves, *pcLeaves, 0, 0);
4096 if ( pLeaf
4097 && ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
4098 {
4099 CPUMCPUIDLEAF Leaf;
4100 Leaf.uLeaf = 4;
4101 Leaf.fSubLeafMask = UINT32_MAX;
4102 Leaf.uSubLeaf = 0;
4103 Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
4104 Leaf.uEcx = UINT32_C(63); /* sets - 1 */
4105 Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
4106 | (UINT32_C(0) << 12) /* phys line partitions - 1 */
4107 | UINT32_C(63); /* system coherency line size - 1 */
4108 Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
4109 | (UINT32_C(0) << 14) /* threads per cache - 1 */
4110 | (UINT32_C(1) << 5) /* cache level */
4111 | UINT32_C(1); /* cache type (data) */
4112 Leaf.fFlags = 0;
4113 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4114 if (RT_SUCCESS(rc))
4115 {
4116 Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
4117 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4118 }
4119 if (RT_SUCCESS(rc))
4120 {
4121 Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
4122 Leaf.uEcx = 4095; /* sets - 1 */
4123 Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
4124 Leaf.uEbx |= UINT32_C(23) << 22;
4125 Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
4126 Leaf.uEax |= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
4127 Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
4128 Leaf.uEax |= UINT32_C(2) << 5;
4129 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4130 }
4131 }
4132 }
4133 }
4134 return rc;
4135}
4136
4137
4138/**
4139 * Loads the CPU ID leaves saved by pass 0, inner worker.
4140 *
4141 * @returns VBox status code.
4142 * @param pVM Pointer to the VM.
4143 * @param pSSM The saved state handle.
4144 * @param uVersion The format version.
4145 * @param paLeaves Guest CPUID leaves loaded from the state.
4146 * @param cLeaves The number of leaves in @a paLeaves.
4147 */
4148int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
4149{
4150 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4151
4152 /*
4153 * Continue loading the state into stack buffers.
4154 */
4155 CPUMCPUID GuestDefCpuId;
4156 int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
4157 AssertRCReturn(rc, rc);
4158
4159 CPUMCPUID aRawStd[16];
4160 uint32_t cRawStd;
4161 rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
4162 if (cRawStd > RT_ELEMENTS(aRawStd))
4163 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4164 rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
4165 AssertRCReturn(rc, rc);
4166 for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
4167 ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4168
4169 CPUMCPUID aRawExt[32];
4170 uint32_t cRawExt;
4171 rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
4172 if (cRawExt > RT_ELEMENTS(aRawExt))
4173 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4174 rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
4175 AssertRCReturn(rc, rc);
4176 for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
4177 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4178
4179 /*
4180 * Get the raw CPU IDs for the current host.
4181 */
4182 CPUMCPUID aHostRawStd[16];
4183 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
4184 ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
4185
4186 CPUMCPUID aHostRawExt[32];
4187 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
4188 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0,
4189 &aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4190
4191 /*
4192 * Get the host and guest overrides so we don't reject the state because
4193 * some feature was enabled thru these interfaces.
4194 * Note! We currently only need the feature leaves, so skip rest.
4195 */
4196 PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4197 CPUMCPUID aHostOverrideStd[2];
4198 memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4199 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4200
4201 CPUMCPUID aHostOverrideExt[2];
4202 memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4203 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4204
4205 /*
4206 * This can be skipped.
4207 */
4208 bool fStrictCpuIdChecks;
4209 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
4210
4211 /*
4212 * Define a bunch of macros for simplifying the santizing/checking code below.
4213 */
4214 /* Generic expression + failure message. */
4215#define CPUID_CHECK_RET(expr, fmt) \
4216 do { \
4217 if (!(expr)) \
4218 { \
4219 char *pszMsg = RTStrAPrintf2 fmt; /* lack of variadic macros sucks */ \
4220 if (fStrictCpuIdChecks) \
4221 { \
4222 int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4223 RTStrFree(pszMsg); \
4224 return rcCpuid; \
4225 } \
4226 LogRel(("CPUM: %s\n", pszMsg)); \
4227 RTStrFree(pszMsg); \
4228 } \
4229 } while (0)
4230#define CPUID_CHECK_WRN(expr, fmt) \
4231 do { \
4232 if (!(expr)) \
4233 LogRel(fmt); \
4234 } while (0)
4235
4236 /* For comparing two values and bitch if they differs. */
4237#define CPUID_CHECK2_RET(what, host, saved) \
4238 do { \
4239 if ((host) != (saved)) \
4240 { \
4241 if (fStrictCpuIdChecks) \
4242 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4243 N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
4244 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4245 } \
4246 } while (0)
4247#define CPUID_CHECK2_WRN(what, host, saved) \
4248 do { \
4249 if ((host) != (saved)) \
4250 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4251 } while (0)
4252
4253 /* For checking raw cpu features (raw mode). */
4254#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
4255 do { \
4256 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4257 { \
4258 if (fStrictCpuIdChecks) \
4259 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4260 N_(#bit " mismatch: host=%d saved=%d"), \
4261 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
4262 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4263 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4264 } \
4265 } while (0)
4266#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
4267 do { \
4268 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4269 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4270 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4271 } while (0)
4272#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
4273
4274 /* For checking guest features. */
4275#define CPUID_GST_FEATURE_RET(set, reg, bit) \
4276 do { \
4277 if ( (aGuestCpuId##set [1].reg & bit) \
4278 && !(aHostRaw##set [1].reg & bit) \
4279 && !(aHostOverride##set [1].reg & bit) \
4280 ) \
4281 { \
4282 if (fStrictCpuIdChecks) \
4283 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4284 N_(#bit " is not supported by the host but has already exposed to the guest")); \
4285 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4286 } \
4287 } while (0)
4288#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
4289 do { \
4290 if ( (aGuestCpuId##set [1].reg & bit) \
4291 && !(aHostRaw##set [1].reg & bit) \
4292 && !(aHostOverride##set [1].reg & bit) \
4293 ) \
4294 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4295 } while (0)
4296#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
4297 do { \
4298 if ( (aGuestCpuId##set [1].reg & bit) \
4299 && !(aHostRaw##set [1].reg & bit) \
4300 && !(aHostOverride##set [1].reg & bit) \
4301 ) \
4302 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4303 } while (0)
4304#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
4305
4306 /* For checking guest features if AMD guest CPU. */
4307#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
4308 do { \
4309 if ( (aGuestCpuId##set [1].reg & bit) \
4310 && fGuestAmd \
4311 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
4312 && !(aHostOverride##set [1].reg & bit) \
4313 ) \
4314 { \
4315 if (fStrictCpuIdChecks) \
4316 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4317 N_(#bit " is not supported by the host but has already exposed to the guest")); \
4318 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4319 } \
4320 } while (0)
4321#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
4322 do { \
4323 if ( (aGuestCpuId##set [1].reg & bit) \
4324 && fGuestAmd \
4325 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
4326 && !(aHostOverride##set [1].reg & bit) \
4327 ) \
4328 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4329 } while (0)
4330#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
4331 do { \
4332 if ( (aGuestCpuId##set [1].reg & bit) \
4333 && fGuestAmd \
4334 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
4335 && !(aHostOverride##set [1].reg & bit) \
4336 ) \
4337 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4338 } while (0)
4339#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
4340
4341 /* For checking AMD features which have a corresponding bit in the standard
4342 range. (Intel defines very few bits in the extended feature sets.) */
4343#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
4344 do { \
4345 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4346 && !(fHostAmd \
4347 ? aHostRawExt[1].reg & (ExtBit) \
4348 : aHostRawStd[1].reg & (StdBit)) \
4349 && !(aHostOverrideExt[1].reg & (ExtBit)) \
4350 ) \
4351 { \
4352 if (fStrictCpuIdChecks) \
4353 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4354 N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
4355 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4356 } \
4357 } while (0)
4358#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
4359 do { \
4360 if ( (aGuestCpuId[1].reg & (ExtBit)) \
4361 && !(fHostAmd \
4362 ? aHostRawExt[1].reg & (ExtBit) \
4363 : aHostRawStd[1].reg & (StdBit)) \
4364 && !(aHostOverrideExt[1].reg & (ExtBit)) \
4365 ) \
4366 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4367 } while (0)
4368#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
4369 do { \
4370 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4371 && !(fHostAmd \
4372 ? aHostRawExt[1].reg & (ExtBit) \
4373 : aHostRawStd[1].reg & (StdBit)) \
4374 && !(aHostOverrideExt[1].reg & (ExtBit)) \
4375 ) \
4376 LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4377 } while (0)
4378#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
4379
4380 /*
4381 * For raw-mode we'll require that the CPUs are very similar since we don't
4382 * intercept CPUID instructions for user mode applications.
4383 */
4384 if (!HMIsEnabled(pVM))
4385 {
4386 /* CPUID(0) */
4387 CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
4388 && aHostRawStd[0].uEcx == aRawStd[0].uEcx
4389 && aHostRawStd[0].uEdx == aRawStd[0].uEdx,
4390 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
4391 &aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
4392 &aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
4393 CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
4394 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
4395 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
4396
4397 bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
4398
4399 /* CPUID(1).eax */
4400 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
4401 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
4402 CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
4403
4404 /* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
4405 CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
4406 CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
4407
4408 /* CPUID(1).ecx */
4409 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
4410 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
4411 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
4412 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4413 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
4414 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
4415 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
4416 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
4417 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
4418 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
4419 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
4420 CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /*reserved*/ );
4421 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
4422 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
4423 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
4424 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
4425 CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /*reserved*/);
4426 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4427 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
4428 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
4429 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
4430 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4431 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
4432 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
4433 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4434 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
4435 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
4436 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4437 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
4438 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4439 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4440 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
4441
4442 /* CPUID(1).edx */
4443 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4444 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4445 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
4446 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4447 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
4448 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
4449 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4450 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4451 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
4452 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4453 CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /*reserved*/);
4454 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4455 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4456 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4457 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4458 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
4459 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4460 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4461 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4462 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
4463 CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /*reserved*/);
4464 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
4465 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
4466 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
4467 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
4468 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
4469 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
4470 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
4471 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
4472 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
4473 CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /*JMPE/IA64*/);
4474 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
4475
4476 /* CPUID(2) - config, mostly about caches. ignore. */
4477 /* CPUID(3) - processor serial number. ignore. */
4478 /* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
4479 /* CPUID(5) - mwait/monitor config. ignore. */
4480 /* CPUID(6) - power management. ignore. */
4481 /* CPUID(7) - ???. ignore. */
4482 /* CPUID(8) - ???. ignore. */
4483 /* CPUID(9) - DCA. ignore for now. */
4484 /* CPUID(a) - PeMo info. ignore for now. */
4485 /* CPUID(b) - topology info - takes ECX as input. ignore. */
4486
4487 /* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
4488 CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
4489 || aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
4490 ("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
4491 if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
4492 && aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
4493 {
4494 CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
4495 CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
4496 CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
4497/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
4498 CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
4499 }
4500
4501 /* CPUID(0x80000000) - same as CPUID(0) except for eax.
4502 Note! Intel have/is marking many of the fields here as reserved. We
4503 will verify them as if it's an AMD CPU. */
4504 CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
4505 || !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
4506 (N_("Extended leaves was present on saved state host, but is missing on the current\n")));
4507 if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
4508 {
4509 CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
4510 && aHostRawExt[0].uEcx == aRawExt[0].uEcx
4511 && aHostRawExt[0].uEdx == aRawExt[0].uEdx,
4512 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
4513 &aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
4514 &aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
4515 CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
4516
4517 /* CPUID(0x80000001).eax - same as CPUID(0).eax. */
4518 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
4519 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
4520 CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
4521 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
4522 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
4523
4524 /* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
4525 CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
4526 CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
4527 CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
4528
4529 /* CPUID(0x80000001).ecx */
4530 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
4531 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
4532 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
4533 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
4534 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
4535 CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
4536 CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
4537 CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
4538 CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
4539 CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
4540 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
4541 CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
4542 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
4543 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
4544 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4545 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4546 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4547 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4548 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4549 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4550 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4551 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4552 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4553 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4554 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4555 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4556 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4557 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4558 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4559 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4560 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4561 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4562
4563 /* CPUID(0x80000001).edx */
4564 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
4565 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
4566 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
4567 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
4568 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
4569 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
4570 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
4571 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
4572 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
4573 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
4574 CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /*reserved*/);
4575 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
4576 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
4577 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
4578 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
4579 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
4580 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
4581 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
4582 CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /*reserved*/);
4583 CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /*reserved*/);
4584 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4585 CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /*reserved*/);
4586 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4587 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
4588 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
4589 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4590 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4591 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4592 CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /*reserved*/);
4593 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4594 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4595 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4596
4597 /** @todo verify the rest as well. */
4598 }
4599 }
4600
4601
4602
4603 /*
4604 * Verify that we can support the features already exposed to the guest on
4605 * this host.
4606 *
4607 * Most of the features we're emulating requires intercepting instruction
4608 * and doing it the slow way, so there is no need to warn when they aren't
4609 * present in the host CPU. Thus we use IGN instead of EMU on these.
4610 *
4611 * Trailing comments:
4612 * "EMU" - Possible to emulate, could be lots of work and very slow.
4613 * "EMU?" - Can this be emulated?
4614 */
4615 CPUMCPUID aGuestCpuIdStd[2];
4616 RT_ZERO(aGuestCpuIdStd);
4617 cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
4618
4619 /* CPUID(1).ecx */
4620 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
4621 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
4622 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
4623 CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4624 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
4625 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
4626 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
4627 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
4628 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
4629 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
4630 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
4631 CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
4632 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
4633 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
4634 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
4635 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
4636 CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /*reserved*/);
4637 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4638 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
4639 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
4640 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
4641 CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4642 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
4643 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
4644 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4645 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
4646 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
4647 CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4648 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
4649 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4650 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4651 CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
4652
4653 /* CPUID(1).edx */
4654 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4655 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4656 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
4657 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4658 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4659 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4660 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4661 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4662 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4663 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4664 CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /*reserved*/);
4665 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4666 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4667 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4668 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4669 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4670 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4671 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4672 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4673 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
4674 CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /*reserved*/);
4675 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
4676 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
4677 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4678 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4679 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
4680 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
4681 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
4682 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
4683 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
4684 CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /*JMPE/IA64*/); // -> EMU
4685 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
4686
4687 /* CPUID(0x80000000). */
4688 CPUMCPUID aGuestCpuIdExt[2];
4689 RT_ZERO(aGuestCpuIdExt);
4690 if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
4691 {
4692 /** @todo deal with no 0x80000001 on the host. */
4693 bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
4694 bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
4695
4696 /* CPUID(0x80000001).ecx */
4697 CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
4698 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
4699 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
4700 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
4701 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
4702 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
4703 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
4704 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
4705 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
4706 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
4707 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
4708 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
4709 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
4710 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
4711 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4712 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4713 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4714 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4715 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4716 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4717 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4718 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4719 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4720 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4721 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4722 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4723 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4724 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4725 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4726 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4727 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4728 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4729
4730 /* CPUID(0x80000001).edx */
4731 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
4732 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
4733 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
4734 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
4735 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4736 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4737 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
4738 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
4739 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4740 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
4741 CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /*reserved*/);
4742 CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
4743 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
4744 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
4745 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
4746 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4747 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
4748 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
4749 CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /*reserved*/);
4750 CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /*reserved*/);
4751 CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4752 CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /*reserved*/);
4753 CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4754 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4755 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4756 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4757 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4758 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4759 CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /*reserved*/);
4760 CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4761 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4762 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4763 }
4764
4765 /** @todo check leaf 7 */
4766
4767 /* CPUID(d) - XCR0 stuff - takes ECX as input.
4768 * ECX=0: EAX - Valid bits in XCR0[31:0].
4769 * EBX - Maximum state size as per current XCR0 value.
4770 * ECX - Maximum state size for all supported features.
4771 * EDX - Valid bits in XCR0[63:32].
4772 * ECX=1: EAX - Various X-features.
4773 * EBX - Maximum state size as per current XCR0|IA32_XSS value.
4774 * ECX - Valid bits in IA32_XSS[31:0].
4775 * EDX - Valid bits in IA32_XSS[63:32].
4776 * ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
4777 * if the bit invalid all four registers are set to zero.
4778 * EAX - The state size for this feature.
4779 * EBX - The state byte offset of this feature.
4780 * ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
4781 * EDX - Reserved, but is set to zero if invalid sub-leaf index.
4782 */
4783 PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
4784 if ( pCurLeaf
4785 && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
4786 && ( pCurLeaf->uEax
4787 || pCurLeaf->uEbx
4788 || pCurLeaf->uEcx
4789 || pCurLeaf->uEdx) )
4790 {
4791 uint64_t fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
4792 if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
4793 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4794 N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
4795 fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
4796
4797 /* We don't support any additional features yet. */
4798 pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
4799 if (pCurLeaf && pCurLeaf->uEax)
4800 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4801 N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
4802 if (pCurLeaf && (pCurLeaf->uEcx || pCurLeaf->uEdx))
4803 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4804 N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
4805 RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
4806
4807
4808 if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
4809 {
4810 LogRel(("CPUM: fXStateGuestMask=%#lx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
4811 pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
4812 }
4813
4814 for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
4815 {
4816 pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4817 if (pCurLeaf)
4818 {
4819 /* If advertised, the state component offset and size must match the one used by host. */
4820 if (pCurLeaf->uEax || pCurLeaf->uEbx || pCurLeaf->uEcx || pCurLeaf->uEdx)
4821 {
4822 CPUMCPUID RawHost;
4823 ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
4824 &RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
4825 if ( RawHost.uEbx != pCurLeaf->uEbx
4826 || RawHost.uEax != pCurLeaf->uEax)
4827 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4828 N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
4829 uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
4830 }
4831 }
4832 }
4833 }
4834
4835#undef CPUID_CHECK_RET
4836#undef CPUID_CHECK_WRN
4837#undef CPUID_CHECK2_RET
4838#undef CPUID_CHECK2_WRN
4839#undef CPUID_RAW_FEATURE_RET
4840#undef CPUID_RAW_FEATURE_WRN
4841#undef CPUID_RAW_FEATURE_IGN
4842#undef CPUID_GST_FEATURE_RET
4843#undef CPUID_GST_FEATURE_WRN
4844#undef CPUID_GST_FEATURE_EMU
4845#undef CPUID_GST_FEATURE_IGN
4846#undef CPUID_GST_FEATURE2_RET
4847#undef CPUID_GST_FEATURE2_WRN
4848#undef CPUID_GST_FEATURE2_EMU
4849#undef CPUID_GST_FEATURE2_IGN
4850#undef CPUID_GST_AMD_FEATURE_RET
4851#undef CPUID_GST_AMD_FEATURE_WRN
4852#undef CPUID_GST_AMD_FEATURE_EMU
4853#undef CPUID_GST_AMD_FEATURE_IGN
4854
4855 /*
4856 * We're good, commit the CPU ID leaves.
4857 */
4858 MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
4859 pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
4860 pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
4861 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
4862 pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
4863 rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
4864 AssertLogRelRCReturn(rc, rc);
4865
4866 return VINF_SUCCESS;
4867}
4868
4869
4870/**
4871 * Loads the CPU ID leaves saved by pass 0.
4872 *
4873 * @returns VBox status code.
4874 * @param pVM Pointer to the VM.
4875 * @param pSSM The saved state handle.
4876 * @param uVersion The format version.
4877 */
4878int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
4879{
4880 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4881
4882 /*
4883 * Load the CPUID leaves array first and call worker to do the rest, just so
4884 * we can free the memory when we need to without ending up in column 1000.
4885 */
4886 PCPUMCPUIDLEAF paLeaves;
4887 uint32_t cLeaves;
4888 int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
4889 AssertRC(rc);
4890 if (RT_SUCCESS(rc))
4891 {
4892 rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
4893 RTMemFree(paLeaves);
4894 }
4895 return rc;
4896}
4897
4898
4899
4900/**
4901 * Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
4902 *
4903 * @returns VBox status code.
4904 * @param pVM Pointer to the VM.
4905 * @param pSSM The saved state handle.
4906 * @param uVersion The format version.
4907 */
4908int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
4909{
4910 AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4911
4912 /*
4913 * Restore the CPUID leaves.
4914 *
4915 * Note that we support restoring less than the current amount of standard
4916 * leaves because we've been allowed more is newer version of VBox.
4917 */
4918 uint32_t cElements;
4919 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
4920 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
4921 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4922 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
4923
4924 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
4925 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
4926 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4927 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
4928
4929 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
4930 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
4931 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4932 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
4933
4934 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4935
4936 /*
4937 * Check that the basic cpuid id information is unchanged.
4938 */
4939 /** @todo we should check the 64 bits capabilities too! */
4940 uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
4941 ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
4942 ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
4943 uint32_t au32CpuIdSaved[8];
4944 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
4945 if (RT_SUCCESS(rc))
4946 {
4947 /* Ignore CPU stepping. */
4948 au32CpuId[4] &= 0xfffffff0;
4949 au32CpuIdSaved[4] &= 0xfffffff0;
4950
4951 /* Ignore APIC ID (AMD specs). */
4952 au32CpuId[5] &= ~0xff000000;
4953 au32CpuIdSaved[5] &= ~0xff000000;
4954
4955 /* Ignore the number of Logical CPUs (AMD specs). */
4956 au32CpuId[5] &= ~0x00ff0000;
4957 au32CpuIdSaved[5] &= ~0x00ff0000;
4958
4959 /* Ignore some advanced capability bits, that we don't expose to the guest. */
4960 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
4961 | X86_CPUID_FEATURE_ECX_VMX
4962 | X86_CPUID_FEATURE_ECX_SMX
4963 | X86_CPUID_FEATURE_ECX_EST
4964 | X86_CPUID_FEATURE_ECX_TM2
4965 | X86_CPUID_FEATURE_ECX_CNTXID
4966 | X86_CPUID_FEATURE_ECX_TPRUPDATE
4967 | X86_CPUID_FEATURE_ECX_PDCM
4968 | X86_CPUID_FEATURE_ECX_DCA
4969 | X86_CPUID_FEATURE_ECX_X2APIC
4970 );
4971 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
4972 | X86_CPUID_FEATURE_ECX_VMX
4973 | X86_CPUID_FEATURE_ECX_SMX
4974 | X86_CPUID_FEATURE_ECX_EST
4975 | X86_CPUID_FEATURE_ECX_TM2
4976 | X86_CPUID_FEATURE_ECX_CNTXID
4977 | X86_CPUID_FEATURE_ECX_TPRUPDATE
4978 | X86_CPUID_FEATURE_ECX_PDCM
4979 | X86_CPUID_FEATURE_ECX_DCA
4980 | X86_CPUID_FEATURE_ECX_X2APIC
4981 );
4982
4983 /* Make sure we don't forget to update the masks when enabling
4984 * features in the future.
4985 */
4986 AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
4987 ( X86_CPUID_FEATURE_ECX_DTES64
4988 | X86_CPUID_FEATURE_ECX_VMX
4989 | X86_CPUID_FEATURE_ECX_SMX
4990 | X86_CPUID_FEATURE_ECX_EST
4991 | X86_CPUID_FEATURE_ECX_TM2
4992 | X86_CPUID_FEATURE_ECX_CNTXID
4993 | X86_CPUID_FEATURE_ECX_TPRUPDATE
4994 | X86_CPUID_FEATURE_ECX_PDCM
4995 | X86_CPUID_FEATURE_ECX_DCA
4996 | X86_CPUID_FEATURE_ECX_X2APIC
4997 )));
4998 /* do the compare */
4999 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5000 {
5001 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5002 LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5003 "Saved=%.*Rhxs\n"
5004 "Real =%.*Rhxs\n",
5005 sizeof(au32CpuIdSaved), au32CpuIdSaved,
5006 sizeof(au32CpuId), au32CpuId));
5007 else
5008 {
5009 LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5010 "Saved=%.*Rhxs\n"
5011 "Real =%.*Rhxs\n",
5012 sizeof(au32CpuIdSaved), au32CpuIdSaved,
5013 sizeof(au32CpuId), au32CpuId));
5014 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5015 }
5016 }
5017 }
5018
5019 return rc;
5020}
5021
5022
5023
5024/*
5025 *
5026 *
5027 * CPUID Info Handler.
5028 * CPUID Info Handler.
5029 * CPUID Info Handler.
5030 *
5031 *
5032 */
5033
5034
5035
5036/**
5037 * Get L1 cache / TLS associativity.
5038 */
5039static const char *getCacheAss(unsigned u, char *pszBuf)
5040{
5041 if (u == 0)
5042 return "res0 ";
5043 if (u == 1)
5044 return "direct";
5045 if (u == 255)
5046 return "fully";
5047 if (u >= 256)
5048 return "???";
5049
5050 RTStrPrintf(pszBuf, 16, "%d way", u);
5051 return pszBuf;
5052}
5053
5054
5055/**
5056 * Get L2 cache associativity.
5057 */
5058const char *getL2CacheAss(unsigned u)
5059{
5060 switch (u)
5061 {
5062 case 0: return "off ";
5063 case 1: return "direct";
5064 case 2: return "2 way ";
5065 case 3: return "res3 ";
5066 case 4: return "4 way ";
5067 case 5: return "res5 ";
5068 case 6: return "8 way ";
5069 case 7: return "res7 ";
5070 case 8: return "16 way";
5071 case 9: return "res9 ";
5072 case 10: return "res10 ";
5073 case 11: return "res11 ";
5074 case 12: return "res12 ";
5075 case 13: return "res13 ";
5076 case 14: return "res14 ";
5077 case 15: return "fully ";
5078 default: return "????";
5079 }
5080}
5081
5082
5083/** CPUID(1).EDX field descriptions. */
5084static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
5085{
5086 DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5087 DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5088 DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5089 DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5090 DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5091 DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
5092 DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5093 DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5094 DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5095 DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5096 DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
5097 DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5098 DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5099 DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5100 DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5101 DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5102 DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5103 DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
5104 DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
5105 DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
5106 DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
5107 DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5108 DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
5109 DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
5110 DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
5111 DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
5112 DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
5113 DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
5114 DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
5115 DBGFREGSUBFIELD_TERMINATOR()
5116};
5117
5118/** CPUID(1).ECX field descriptions. */
5119static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
5120{
5121 DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
5122 DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
5123 DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
5124 DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
5125 DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
5126 DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
5127 DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
5128 DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
5129 DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
5130 DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
5131 DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
5132 DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
5133 DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
5134 DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
5135 DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
5136 DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
5137 DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
5138 DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
5139 DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
5140 DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
5141 DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
5142 DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
5143 DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
5144 DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
5145 DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
5146 DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
5147 DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
5148 DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
5149 DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
5150 DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
5151 DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
5152 DBGFREGSUBFIELD_TERMINATOR()
5153};
5154
5155/** CPUID(7,0).EBX field descriptions. */
5156static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
5157{
5158 DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
5159 DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
5160 DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
5161 DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
5162 DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
5163 DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
5164 DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
5165 DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
5166 DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
5167 DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
5168 DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
5169 DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
5170 DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
5171 DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
5172 DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
5173 DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
5174 DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
5175 DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
5176 DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
5177 DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
5178 DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
5179 DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
5180 DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
5181 DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
5182 DBGFREGSUBFIELD_TERMINATOR()
5183};
5184
5185/** CPUID(7,0).ECX field descriptions. */
5186static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
5187{
5188 DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
5189 DBGFREGSUBFIELD_TERMINATOR()
5190};
5191
5192
5193/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
5194static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
5195{
5196 DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
5197 DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
5198 DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
5199 DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
5200 DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
5201 DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
5202 DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
5203 DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
5204 DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
5205 DBGFREGSUBFIELD_TERMINATOR()
5206};
5207
5208/** CPUID(13,1).EAX field descriptions. */
5209static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
5210{
5211 DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
5212 DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
5213 DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
5214 DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
5215 DBGFREGSUBFIELD_TERMINATOR()
5216};
5217
5218
5219/** CPUID(0x80000001,0).EDX field descriptions. */
5220static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
5221{
5222 DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5223 DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5224 DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5225 DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5226 DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5227 DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
5228 DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5229 DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5230 DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5231 DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5232 DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
5233 DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5234 DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5235 DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5236 DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5237 DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5238 DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5239 DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
5240 DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
5241 DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5242 DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
5243 DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
5244 DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
5245 DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
5246 DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
5247 DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
5248 DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
5249 DBGFREGSUBFIELD_TERMINATOR()
5250};
5251
5252/** CPUID(0x80000001,0).ECX field descriptions. */
5253static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
5254{
5255 DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
5256 DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
5257 DBGFREGSUBFIELD_RO("SVM\0" "AMD VM extensions", 2, 1, 0),
5258 DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
5259 DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
5260 DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
5261 DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
5262 DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
5263 DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
5264 DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
5265 DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
5266 DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
5267 DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
5268 DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
5269 DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
5270 DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
5271 DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
5272 DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
5273 DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
5274 DBGFREGSUBFIELD_TERMINATOR()
5275};
5276
5277
5278static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
5279 const char *pszLeadIn, uint32_t cchWidth)
5280{
5281 if (pszLeadIn)
5282 pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5283
5284 for (uint32_t iBit = 0; iBit < 32; iBit++)
5285 if (RT_BIT_32(iBit) & uVal)
5286 {
5287 while ( pDesc->pszName != NULL
5288 && iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5289 pDesc++;
5290 if ( pDesc->pszName != NULL
5291 && iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5292 {
5293 if (pDesc->cBits == 1)
5294 pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5295 else
5296 {
5297 uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
5298 if (pDesc->cBits < 32)
5299 uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5300 pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
5301 iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5302 }
5303 }
5304 else
5305 pHlp->pfnPrintf(pHlp, " %u", iBit);
5306 }
5307 if (pszLeadIn)
5308 pHlp->pfnPrintf(pHlp, "\n");
5309}
5310
5311
5312static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5313 const char *pszLeadIn, uint32_t cchWidth)
5314{
5315 if (pszLeadIn)
5316 pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5317
5318 for (uint32_t iBit = 0; iBit < 64; iBit++)
5319 if (RT_BIT_64(iBit) & uVal)
5320 {
5321 while ( pDesc->pszName != NULL
5322 && iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5323 pDesc++;
5324 if ( pDesc->pszName != NULL
5325 && iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5326 {
5327 if (pDesc->cBits == 1)
5328 pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5329 else
5330 {
5331 uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
5332 if (pDesc->cBits < 64)
5333 uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
5334 pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
5335 iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5336 }
5337 }
5338 else
5339 pHlp->pfnPrintf(pHlp, " %u", iBit);
5340 }
5341 if (pszLeadIn)
5342 pHlp->pfnPrintf(pHlp, "\n");
5343}
5344
5345
5346static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5347 const char *pszLeadIn, uint32_t cchWidth)
5348{
5349 if (!uVal)
5350 pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5351 else
5352 {
5353 pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5354 cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
5355 pHlp->pfnPrintf(pHlp, " )\n");
5356 }
5357}
5358
5359
5360static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
5361 uint32_t cchWidth)
5362{
5363 uint32_t uCombined = uVal1 | uVal2;
5364 for (uint32_t iBit = 0; iBit < 32; iBit++)
5365 if ( (RT_BIT_32(iBit) & uCombined)
5366 || (iBit == pDesc->iFirstBit && pDesc->pszName) )
5367 {
5368 while ( pDesc->pszName != NULL
5369 && iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5370 pDesc++;
5371
5372 if ( pDesc->pszName != NULL
5373 && iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5374 {
5375 size_t cchMnemonic = strlen(pDesc->pszName);
5376 const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
5377 size_t cchDesc = strlen(pszDesc);
5378 uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
5379 uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
5380 if (pDesc->cBits < 32)
5381 {
5382 uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5383 uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5384 }
5385
5386 pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%*s= %u (%u)\n" : " %s - %s%*s= %#x (%#x)\n",
5387 pDesc->pszName, pszDesc,
5388 cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
5389 uFieldValue1, uFieldValue2);
5390
5391 iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
5392 pDesc++;
5393 }
5394 else
5395 pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
5396 RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
5397 }
5398}
5399
5400
5401/**
5402 * Produces a detailed summary of standard leaf 0x00000001.
5403 *
5404 * @param pHlp The info helper functions.
5405 * @param paLeaves The CPUID leaves array.
5406 * @param cLeaves The number of leaves in the array.
5407 * @param pCurLeaf The 0x00000001 leaf.
5408 * @param fVerbose Whether to be very verbose or not.
5409 * @param fIntel Set if intel CPU.
5410 */
5411static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5412 PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
5413{
5414 Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
5415 static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
5416 uint32_t uEAX = pCurLeaf->uEax;
5417 uint32_t uEBX = pCurLeaf->uEbx;
5418
5419 pHlp->pfnPrintf(pHlp,
5420 "%36s %2d \tExtended: %d \tEffective: %d\n"
5421 "%36s %2d \tExtended: %d \tEffective: %d\n"
5422 "%36s %d\n"
5423 "%36s %d (%s)\n"
5424 "%36s %#04x\n"
5425 "%36s %d\n"
5426 "%36s %d\n"
5427 "%36s %#04x\n"
5428 ,
5429 "Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
5430 "Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
5431 "Stepping:", ASMGetCpuStepping(uEAX),
5432 "Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
5433 "APIC ID:", (uEBX >> 24) & 0xff,
5434 "Logical CPUs:",(uEBX >> 16) & 0xff,
5435 "CLFLUSH Size:",(uEBX >> 8) & 0xff,
5436 "Brand ID:", (uEBX >> 0) & 0xff);
5437 if (fVerbose)
5438 {
5439 CPUMCPUID Host;
5440 ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5441 pHlp->pfnPrintf(pHlp, "Features\n");
5442 pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5443 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
5444 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
5445 }
5446 else
5447 {
5448 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
5449 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
5450 }
5451}
5452
5453
5454/**
5455 * Produces a detailed summary of standard leaf 0x00000007.
5456 *
5457 * @param pHlp The info helper functions.
5458 * @param paLeaves The CPUID leaves array.
5459 * @param cLeaves The number of leaves in the array.
5460 * @param pCurLeaf The first 0x00000007 leaf.
5461 * @param fVerbose Whether to be very verbose or not.
5462 */
5463static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5464 PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5465{
5466 Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
5467 pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
5468 for (;;)
5469 {
5470 CPUMCPUID Host;
5471 ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5472
5473 switch (pCurLeaf->uSubLeaf)
5474 {
5475 case 0:
5476 if (fVerbose)
5477 {
5478 pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5479 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
5480 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
5481 if (pCurLeaf->uEdx || Host.uEdx)
5482 pHlp->pfnPrintf(pHlp, "%36 %#x (%#x)\n", "Ext Features EDX:", pCurLeaf->uEdx, Host.uEdx);
5483 }
5484 else
5485 {
5486 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
5487 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
5488 if (pCurLeaf->uEdx)
5489 pHlp->pfnPrintf(pHlp, "%36 %#x\n", "Ext Features EDX:", pCurLeaf->uEdx);
5490 }
5491 break;
5492
5493 default:
5494 if (pCurLeaf->uEdx || pCurLeaf->uEcx || pCurLeaf->uEbx)
5495 pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
5496 pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
5497 break;
5498
5499 }
5500
5501 /* advance. */
5502 pCurLeaf++;
5503 if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5504 || pCurLeaf->uLeaf != 0x7)
5505 break;
5506 }
5507}
5508
5509
5510/**
5511 * Produces a detailed summary of standard leaf 0x0000000d.
5512 *
5513 * @param pHlp The info helper functions.
5514 * @param paLeaves The CPUID leaves array.
5515 * @param cLeaves The number of leaves in the array.
5516 * @param pCurLeaf The first 0x00000007 leaf.
5517 * @param fVerbose Whether to be very verbose or not.
5518 */
5519static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5520 PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5521{
5522 Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
5523 pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
5524 for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5525 {
5526 CPUMCPUID Host;
5527 ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5528
5529 switch (uSubLeaf)
5530 {
5531 case 0:
5532 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5533 pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
5534 pCurLeaf->uEbx, pCurLeaf->uEcx);
5535 pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
5536
5537 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5538 cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
5539 "Valid XCR0 bits, guest:", 42);
5540 cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
5541 "Valid XCR0 bits, host:", 42);
5542 break;
5543
5544 case 1:
5545 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5546 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
5547 cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
5548
5549 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5550 pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0|XSS, guest:", pCurLeaf->uEbx);
5551 pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0|XSS, host:", Host.uEbx);
5552
5553 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5554 cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
5555 " Valid IA32_XSS bits, guest:", 42);
5556 cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
5557 " Valid IA32_XSS bits, host:", 42);
5558 break;
5559
5560 default:
5561 if ( pCurLeaf
5562 && pCurLeaf->uSubLeaf == uSubLeaf
5563 && (pCurLeaf->uEax || pCurLeaf->uEbx || pCurLeaf->uEcx || pCurLeaf->uEdx) )
5564 {
5565 pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
5566 pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5567 if (pCurLeaf->uEcx & ~RT_BIT_32(0))
5568 pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
5569 if (pCurLeaf->uEdx)
5570 pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
5571 pHlp->pfnPrintf(pHlp, " --");
5572 cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5573 pHlp->pfnPrintf(pHlp, "\n");
5574 }
5575 if (Host.uEax || Host.uEbx || Host.uEcx || Host.uEdx)
5576 {
5577 pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
5578 Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5579 if (Host.uEcx & ~RT_BIT_32(0))
5580 pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
5581 if (Host.uEdx)
5582 pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
5583 pHlp->pfnPrintf(pHlp, " --");
5584 cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5585 pHlp->pfnPrintf(pHlp, "\n");
5586 }
5587 break;
5588
5589 }
5590
5591 /* advance. */
5592 if (pCurLeaf)
5593 {
5594 while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5595 && pCurLeaf->uSubLeaf <= uSubLeaf
5596 && pCurLeaf->uLeaf == UINT32_C(0x0000000d))
5597 pCurLeaf++;
5598 if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5599 || pCurLeaf->uLeaf != UINT32_C(0x0000000d))
5600 pCurLeaf = NULL;
5601 }
5602 }
5603}
5604
5605
5606static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5607 PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
5608{
5609 if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5610 && pCurLeaf->uLeaf <= uUpToLeaf)
5611 {
5612 pHlp->pfnPrintf(pHlp,
5613 " %s\n"
5614 " Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
5615 while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5616 && pCurLeaf->uLeaf <= uUpToLeaf)
5617 {
5618 CPUMCPUID Host;
5619 ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5620 pHlp->pfnPrintf(pHlp,
5621 "Gst: %08x/%04x %08x %08x %08x %08x\n"
5622 "Hst: %08x %08x %08x %08x\n",
5623 pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5624 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5625 pCurLeaf++;
5626 }
5627 }
5628
5629 return pCurLeaf;
5630}
5631
5632
5633/**
5634 * Display the guest CpuId leaves.
5635 *
5636 * @param pVM Pointer to the VM.
5637 * @param pHlp The info helper functions.
5638 * @param pszArgs "terse", "default" or "verbose".
5639 */
5640DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
5641{
5642 /*
5643 * Parse the argument.
5644 */
5645 unsigned iVerbosity = 1;
5646 if (pszArgs)
5647 {
5648 pszArgs = RTStrStripL(pszArgs);
5649 if (!strcmp(pszArgs, "terse"))
5650 iVerbosity--;
5651 else if (!strcmp(pszArgs, "verbose"))
5652 iVerbosity++;
5653 }
5654
5655 uint32_t uLeaf;
5656 CPUMCPUID Host;
5657 uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
5658 PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
5659 PCCPUMCPUIDLEAF pCurLeaf;
5660 PCCPUMCPUIDLEAF pNextLeaf;
5661 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
5662 pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
5663 pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
5664
5665 /*
5666 * Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
5667 */
5668 uint32_t cHstMax = ASMCpuId_EAX(0);
5669 uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
5670 uint32_t cMax = RT_MAX(cGstMax, cHstMax);
5671 pHlp->pfnPrintf(pHlp,
5672 " Raw Standard CPUID Leaves\n"
5673 " Leaf/sub-leaf eax ebx ecx edx\n");
5674 for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
5675 {
5676 uint32_t cMaxSubLeaves = 1;
5677 if (uLeaf == 4 || uLeaf == 7 || uLeaf == 0xb)
5678 cMaxSubLeaves = 16;
5679 else if (uLeaf == 0xd)
5680 cMaxSubLeaves = 128;
5681
5682 for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5683 {
5684 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5685 if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5686 && pCurLeaf->uLeaf == uLeaf
5687 && pCurLeaf->uSubLeaf == uSubLeaf)
5688 {
5689 pHlp->pfnPrintf(pHlp,
5690 "Gst: %08x/%04x %08x %08x %08x %08x\n"
5691 "Hst: %08x %08x %08x %08x\n",
5692 uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5693 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5694 pCurLeaf++;
5695 }
5696 else if ( uLeaf != 0xd
5697 || uSubLeaf <= 1
5698 || Host.uEbx != 0 )
5699 pHlp->pfnPrintf(pHlp,
5700 "Hst: %08x/%04x %08x %08x %08x %08x\n",
5701 uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5702
5703 /* Done? */
5704 if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5705 || pCurLeaf->uLeaf != uLeaf)
5706 && ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 || (Host.uEax & 0x000f) >= 8))
5707 || (uLeaf == 0x7 && Host.uEax == 0)
5708 || (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 || (Host.uEcx & 0xff00) >= 8))
5709 || (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
5710 || (uLeaf == 0xd && uSubLeaf >= 128)
5711 )
5712 )
5713 break;
5714 }
5715 }
5716 pNextLeaf = pCurLeaf;
5717
5718 /*
5719 * If verbose, decode it.
5720 */
5721 if (iVerbosity && paLeaves[0].uLeaf == 0)
5722 pHlp->pfnPrintf(pHlp,
5723 "%36s %.04s%.04s%.04s\n"
5724 "%36s 0x00000000-%#010x\n"
5725 ,
5726 "Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
5727 "Supports:", paLeaves[0].uEax);
5728
5729 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
5730 cpumR3CpuIdInfoStdLeaf1Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1, fIntel);
5731
5732 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
5733 cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5734
5735 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
5736 cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5737
5738 pCurLeaf = pNextLeaf;
5739
5740 /*
5741 * Hypervisor leaves.
5742 *
5743 * Unlike most of the other leaves reported, the guest hypervisor leaves
5744 * aren't a subset of the host CPUID bits.
5745 */
5746 pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
5747
5748 ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5749 cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
5750 cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
5751 ? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
5752 cMax = RT_MAX(cHstMax, cGstMax);
5753 if (cMax >= UINT32_C(0x40000000))
5754 {
5755 pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
5756
5757 /** @todo dump these in more detail. */
5758
5759 pCurLeaf = pNextLeaf;
5760 }
5761
5762
5763 /*
5764 * Extended. Custom raw dump here due to ECX sub-leaves host handling.
5765 * Implemented after AMD specs.
5766 */
5767 pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
5768
5769 ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5770 cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
5771 cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
5772 ? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
5773 cMax = RT_MAX(cHstMax, cGstMax);
5774 if (cMax >= UINT32_C(0x80000000))
5775 {
5776
5777 pHlp->pfnPrintf(pHlp,
5778 " Raw Extended CPUID Leaves\n"
5779 " Leaf/sub-leaf eax ebx ecx edx\n");
5780 PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
5781 for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
5782 {
5783 uint32_t cMaxSubLeaves = 1;
5784 if (uLeaf == UINT32_C(0x8000001d))
5785 cMaxSubLeaves = 16;
5786
5787 for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5788 {
5789 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5790 if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5791 && pCurLeaf->uLeaf == uLeaf
5792 && pCurLeaf->uSubLeaf == uSubLeaf)
5793 {
5794 pHlp->pfnPrintf(pHlp,
5795 "Gst: %08x/%04x %08x %08x %08x %08x\n"
5796 "Hst: %08x %08x %08x %08x\n",
5797 uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5798 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5799 pCurLeaf++;
5800 }
5801 else if ( uLeaf != 0xd
5802 || uSubLeaf <= 1
5803 || Host.uEbx != 0 )
5804 pHlp->pfnPrintf(pHlp,
5805 "Hst: %08x/%04x %08x %08x %08x %08x\n",
5806 uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5807
5808 /* Done? */
5809 if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5810 || pCurLeaf->uLeaf != uLeaf)
5811 && (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 || (Host.uEax & 0x000f) >= 8)) )
5812 break;
5813 }
5814 }
5815 pNextLeaf = pCurLeaf;
5816
5817 /*
5818 * Understandable output
5819 */
5820 if (iVerbosity)
5821 pHlp->pfnPrintf(pHlp,
5822 "Ext Name: %.4s%.4s%.4s\n"
5823 "Ext Supports: 0x80000000-%#010x\n",
5824 &pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
5825
5826 pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
5827 if (iVerbosity && pCurLeaf)
5828 {
5829 uint32_t uEAX = pCurLeaf->uEax;
5830 pHlp->pfnPrintf(pHlp,
5831 "Family: %d \tExtended: %d \tEffective: %d\n"
5832 "Model: %d \tExtended: %d \tEffective: %d\n"
5833 "Stepping: %d\n"
5834 "Brand ID: %#05x\n",
5835 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
5836 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
5837 ASMGetCpuStepping(uEAX),
5838 pCurLeaf->uEbx & 0xfff);
5839
5840 if (iVerbosity == 1)
5841 {
5842 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
5843 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
5844 }
5845 else
5846 {
5847 ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5848 pHlp->pfnPrintf(pHlp, "Ext Features\n");
5849 pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5850 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
5851 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
5852 }
5853 }
5854
5855 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
5856 {
5857 char szString[4*4*3+1] = {0};
5858 uint32_t *pu32 = (uint32_t *)szString;
5859 *pu32++ = pCurLeaf->uEax;
5860 *pu32++ = pCurLeaf->uEbx;
5861 *pu32++ = pCurLeaf->uEcx;
5862 *pu32++ = pCurLeaf->uEdx;
5863 pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
5864 if (pCurLeaf)
5865 {
5866 *pu32++ = pCurLeaf->uEax;
5867 *pu32++ = pCurLeaf->uEbx;
5868 *pu32++ = pCurLeaf->uEcx;
5869 *pu32++ = pCurLeaf->uEdx;
5870 }
5871 pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
5872 if (pCurLeaf)
5873 {
5874 *pu32++ = pCurLeaf->uEax;
5875 *pu32++ = pCurLeaf->uEbx;
5876 *pu32++ = pCurLeaf->uEcx;
5877 *pu32++ = pCurLeaf->uEdx;
5878 }
5879 pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
5880 }
5881
5882 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
5883 {
5884 uint32_t uEAX = pCurLeaf->uEax;
5885 uint32_t uEBX = pCurLeaf->uEbx;
5886 uint32_t uECX = pCurLeaf->uEcx;
5887 uint32_t uEDX = pCurLeaf->uEdx;
5888 char sz1[32];
5889 char sz2[32];
5890
5891 pHlp->pfnPrintf(pHlp,
5892 "TLB 2/4M Instr/Uni: %s %3d entries\n"
5893 "TLB 2/4M Data: %s %3d entries\n",
5894 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
5895 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
5896 pHlp->pfnPrintf(pHlp,
5897 "TLB 4K Instr/Uni: %s %3d entries\n"
5898 "TLB 4K Data: %s %3d entries\n",
5899 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
5900 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
5901 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
5902 "L1 Instr Cache Lines Per Tag: %d\n"
5903 "L1 Instr Cache Associativity: %s\n"
5904 "L1 Instr Cache Size: %d KB\n",
5905 (uEDX >> 0) & 0xff,
5906 (uEDX >> 8) & 0xff,
5907 getCacheAss((uEDX >> 16) & 0xff, sz1),
5908 (uEDX >> 24) & 0xff);
5909 pHlp->pfnPrintf(pHlp,
5910 "L1 Data Cache Line Size: %d bytes\n"
5911 "L1 Data Cache Lines Per Tag: %d\n"
5912 "L1 Data Cache Associativity: %s\n"
5913 "L1 Data Cache Size: %d KB\n",
5914 (uECX >> 0) & 0xff,
5915 (uECX >> 8) & 0xff,
5916 getCacheAss((uECX >> 16) & 0xff, sz1),
5917 (uECX >> 24) & 0xff);
5918 }
5919
5920 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
5921 {
5922 uint32_t uEAX = pCurLeaf->uEax;
5923 uint32_t uEBX = pCurLeaf->uEbx;
5924 uint32_t uEDX = pCurLeaf->uEdx;
5925
5926 pHlp->pfnPrintf(pHlp,
5927 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
5928 "L2 TLB 2/4M Data: %s %4d entries\n",
5929 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
5930 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
5931 pHlp->pfnPrintf(pHlp,
5932 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
5933 "L2 TLB 4K Data: %s %4d entries\n",
5934 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
5935 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
5936 pHlp->pfnPrintf(pHlp,
5937 "L2 Cache Line Size: %d bytes\n"
5938 "L2 Cache Lines Per Tag: %d\n"
5939 "L2 Cache Associativity: %s\n"
5940 "L2 Cache Size: %d KB\n",
5941 (uEDX >> 0) & 0xff,
5942 (uEDX >> 8) & 0xf,
5943 getL2CacheAss((uEDX >> 12) & 0xf),
5944 (uEDX >> 16) & 0xffff);
5945 }
5946
5947 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
5948 {
5949 uint32_t uEDX = pCurLeaf->uEdx;
5950
5951 pHlp->pfnPrintf(pHlp, "APM Features: ");
5952 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
5953 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
5954 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
5955 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
5956 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
5957 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
5958 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " MC");
5959 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " HWPSTATE");
5960 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TscInvariant");
5961 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " CPB");
5962 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " EffFreqRO");
5963 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PFI");
5964 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PA");
5965 for (unsigned iBit = 13; iBit < 32; iBit++)
5966 if (uEDX & RT_BIT(iBit))
5967 pHlp->pfnPrintf(pHlp, " %d", iBit);
5968 pHlp->pfnPrintf(pHlp, "\n");
5969
5970 ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5971 pHlp->pfnPrintf(pHlp, "Host Invariant-TSC support: %RTbool\n",
5972 cHstMax >= UINT32_C(0x80000007) && (Host.uEdx & RT_BIT(8)));
5973
5974 }
5975
5976 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0)) != NULL)
5977 {
5978 uint32_t uEAX = pCurLeaf->uEax;
5979 uint32_t uECX = pCurLeaf->uEcx;
5980
5981 pHlp->pfnPrintf(pHlp,
5982 "Physical Address Width: %d bits\n"
5983 "Virtual Address Width: %d bits\n"
5984 "Guest Physical Address Width: %d bits\n",
5985 (uEAX >> 0) & 0xff,
5986 (uEAX >> 8) & 0xff,
5987 (uEAX >> 16) & 0xff);
5988 pHlp->pfnPrintf(pHlp,
5989 "Physical Core Count: %d\n",
5990 (uECX >> 0) & 0xff);
5991 }
5992
5993 pCurLeaf = pNextLeaf;
5994 }
5995
5996
5997
5998 /*
5999 * Centaur.
6000 */
6001 pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
6002
6003 ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6004 cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
6005 ? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
6006 cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
6007 ? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
6008 cMax = RT_MAX(cHstMax, cGstMax);
6009 if (cMax >= UINT32_C(0xc0000000))
6010 {
6011 pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
6012
6013 /*
6014 * Understandable output
6015 */
6016 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
6017 pHlp->pfnPrintf(pHlp,
6018 "Centaur Supports: 0xc0000000-%#010x\n",
6019 pCurLeaf->uEax);
6020
6021 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
6022 {
6023 ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6024 uint32_t uEdxGst = pCurLeaf->uEdx;
6025 uint32_t uEdxHst = Host.uEdx;
6026
6027 if (iVerbosity == 1)
6028 {
6029 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
6030 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
6031 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
6032 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
6033 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
6034 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
6035 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
6036 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
6037 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
6038 /* possibly indicating MM/HE and MM/HE-E on older chips... */
6039 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
6040 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
6041 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
6042 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
6043 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
6044 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
6045 for (unsigned iBit = 14; iBit < 32; iBit++)
6046 if (uEdxGst & RT_BIT(iBit))
6047 pHlp->pfnPrintf(pHlp, " %d", iBit);
6048 pHlp->pfnPrintf(pHlp, "\n");
6049 }
6050 else
6051 {
6052 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
6053 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
6054 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
6055 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
6056 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
6057 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
6058 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
6059 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
6060 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
6061 /* possibly indicating MM/HE and MM/HE-E on older chips... */
6062 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
6063 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
6064 pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
6065 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
6066 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
6067 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
6068 pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
6069 pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
6070 pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
6071 pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
6072 pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
6073 pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
6074 pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
6075 pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
6076 pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
6077 pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
6078 pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
6079 pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
6080 pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
6081 for (unsigned iBit = 27; iBit < 32; iBit++)
6082 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
6083 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
6084 pHlp->pfnPrintf(pHlp, "\n");
6085 }
6086 }
6087
6088 pCurLeaf = pNextLeaf;
6089 }
6090
6091 /*
6092 * The remainder.
6093 */
6094 pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
6095}
6096
6097
6098
6099
6100
6101/*
6102 *
6103 *
6104 * PATM interfaces.
6105 * PATM interfaces.
6106 * PATM interfaces.
6107 *
6108 *
6109 */
6110
6111
6112# if defined(VBOX_WITH_RAW_MODE) || defined(DOXYGEN_RUNNING)
6113/** @name Patchmanager CPUID legacy table APIs
6114 * @{
6115 */
6116
6117/**
6118 * Gets a pointer to the default CPUID leaf.
6119 *
6120 * @returns Raw-mode pointer to the default CPUID leaf (read-only).
6121 * @param pVM Pointer to the VM.
6122 * @remark Intended for PATM only.
6123 */
6124VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
6125{
6126 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
6127}
6128
6129
6130/**
6131 * Gets a number of standard CPUID leaves (PATM only).
6132 *
6133 * @returns Number of leaves.
6134 * @param pVM Pointer to the VM.
6135 * @remark Intended for PATM - legacy, don't use in new code.
6136 */
6137VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
6138{
6139 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
6140}
6141
6142
6143/**
6144 * Gets a number of extended CPUID leaves (PATM only).
6145 *
6146 * @returns Number of leaves.
6147 * @param pVM Pointer to the VM.
6148 * @remark Intended for PATM - legacy, don't use in new code.
6149 */
6150VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
6151{
6152 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
6153}
6154
6155
6156/**
6157 * Gets a number of centaur CPUID leaves.
6158 *
6159 * @returns Number of leaves.
6160 * @param pVM Pointer to the VM.
6161 * @remark Intended for PATM - legacy, don't use in new code.
6162 */
6163VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
6164{
6165 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
6166}
6167
6168
6169/**
6170 * Gets a pointer to the array of standard CPUID leaves.
6171 *
6172 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
6173 *
6174 * @returns Raw-mode pointer to the standard CPUID leaves (read-only).
6175 * @param pVM Pointer to the VM.
6176 * @remark Intended for PATM - legacy, don't use in new code.
6177 */
6178VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
6179{
6180 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
6181}
6182
6183
6184/**
6185 * Gets a pointer to the array of extended CPUID leaves.
6186 *
6187 * CPUMGetGuestCpuIdExtMax() give the size of the array.
6188 *
6189 * @returns Raw-mode pointer to the extended CPUID leaves (read-only).
6190 * @param pVM Pointer to the VM.
6191 * @remark Intended for PATM - legacy, don't use in new code.
6192 */
6193VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
6194{
6195 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
6196}
6197
6198
6199/**
6200 * Gets a pointer to the array of centaur CPUID leaves.
6201 *
6202 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
6203 *
6204 * @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
6205 * @param pVM Pointer to the VM.
6206 * @remark Intended for PATM - legacy, don't use in new code.
6207 */
6208VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
6209{
6210 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
6211}
6212
6213/** @} */
6214# endif /* VBOX_WITH_RAW_MODE || DOXYGEN_RUNNING */
6215
6216#endif /* VBOX_IN_VMM */
6217
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