CPUMR3CpuId.cpp@ 100696

Last change on this file since 100696 was 100625, checked in by vboxsync, 17 months ago
CPUID: Expose AMD XSaveErPtr CPUID bit to guests. Eliminates fxsave_leak bug in Linux.
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File size: 272.6 KB

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1	/* $Id: CPUMR3CpuId.cpp 100625 2023-07-18 10:10:57Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_CPUM
33	#include <VBox/vmm/cpum.h>
34	#include <VBox/vmm/dbgf.h>
35	#include <VBox/vmm/hm.h>
36	#include <VBox/vmm/nem.h>
37	#include <VBox/vmm/ssm.h>
38	#include "CPUMInternal.h"
39	#include <VBox/vmm/vmcc.h>
40	#include <VBox/sup.h>
41
42	#include <VBox/err.h>
43	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
44	# include <iprt/asm-amd64-x86.h>
45	#endif
46	#include <iprt/ctype.h>
47	#include <iprt/mem.h>
48	#include <iprt/string.h>
49	#include <iprt/x86-helpers.h>
50
51
52	/*********************************************************************************************************************************
53	* Defined Constants And Macros *
54	*********************************************************************************************************************************/
55	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
56	#define CPUM_CPUID_MAX_LEAVES 2048
57
58
59	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
60	/**
61	* Determins the host CPU MXCSR mask.
62	*
63	* @returns MXCSR mask.
64	*/
65	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
66	{
67	if ( ASMHasCpuId()
68	&& RTX86IsValidStdRange(ASMCpuId_EAX(0))
69	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
70	{
71	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
72	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
73	RT_ZERO(*pState);
74	ASMFxSave(pState);
75	if (pState->MXCSR_MASK == 0)
76	return 0xffbf;
77	return pState->MXCSR_MASK;
78	}
79	return 0;
80	}
81	#endif
82
83
84
85	#ifndef IN_VBOX_CPU_REPORT
86	/**
87	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
88	*
89	* @returns true if found, false it not.
90	* @param paLeaves The CPUID leaves to search. This is sorted.
91	* @param cLeaves The number of leaves in the array.
92	* @param uLeaf The leaf to locate.
93	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
94	* @param pLegacy The legacy output leaf.
95	*/
96	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
97	PCPUMCPUID pLegacy)
98	{
99	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, uLeaf, uSubLeaf);
100	if (pLeaf)
101	{
102	pLegacy->uEax = pLeaf->uEax;
103	pLegacy->uEbx = pLeaf->uEbx;
104	pLegacy->uEcx = pLeaf->uEcx;
105	pLegacy->uEdx = pLeaf->uEdx;
106	return true;
107	}
108	return false;
109	}
110	#endif /* IN_VBOX_CPU_REPORT */
111
112
113	/**
114	* Inserts a CPU ID leaf, replacing any existing ones.
115	*
116	* When inserting a simple leaf where we already got a series of sub-leaves with
117	* the same leaf number (eax), the simple leaf will replace the whole series.
118	*
119	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
120	* host-context heap and has only been allocated/reallocated by the
121	* cpumCpuIdEnsureSpace function.
122	*
123	* @returns VBox status code.
124	* @param pVM The cross context VM structure. If NULL, use
125	* the process heap, otherwise the VM's hyper heap.
126	* @param ppaLeaves Pointer to the pointer to the array of sorted
127	* CPUID leaves and sub-leaves. Must be NULL if using
128	* the hyper heap.
129	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
130	* be NULL if using the hyper heap.
131	* @param pNewLeaf Pointer to the data of the new leaf we're about to
132	* insert.
133	*/
134	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
135	{
136	/*
137	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
138	*/
139	if (pVM)
140	{
141	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
142	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
143	AssertReturn(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 == pVM->cpum.s.GuestInfo.aCpuIdLeaves, VERR_INVALID_PARAMETER);
144
145	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
146	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
147	}
148
149	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
150	uint32_t cLeaves = *pcLeaves;
151
152	/*
153	* Validate the new leaf a little.
154	*/
155	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
156	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
157	VERR_INVALID_FLAGS);
158	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
159	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
160	VERR_INVALID_PARAMETER);
161	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
162	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
163	VERR_INVALID_PARAMETER);
164	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
165	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
166	VERR_INVALID_PARAMETER);
167
168	/*
169	* Find insertion point. The lazy bird uses the same excuse as in
170	* cpumCpuIdGetLeaf(), but optimizes for linear insertion (saved state).
171	*/
172	uint32_t i;
173	if ( cLeaves > 0
174	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
175	{
176	/* Add at end. */
177	i = cLeaves;
178	}
179	else if ( cLeaves > 0
180	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
181	{
182	/* Either replacing the last leaf or dealing with sub-leaves. Spool
183	back to the first sub-leaf to pretend we did the linear search. */
184	i = cLeaves - 1;
185	while ( i > 0
186	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
187	i--;
188	}
189	else
190	{
191	/* Linear search from the start. */
192	i = 0;
193	while ( i < cLeaves
194	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
195	i++;
196	}
197	if ( i < cLeaves
198	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
199	{
200	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
201	{
202	/*
203	* The sub-leaf mask differs, replace all existing leaves with the
204	* same leaf number.
205	*/
206	uint32_t c = 1;
207	while ( i + c < cLeaves
208	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
209	c++;
210	if (c > 1 && i + c < cLeaves)
211	{
212	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
213	*pcLeaves = cLeaves -= c - 1;
214	}
215
216	paLeaves[i] = *pNewLeaf;
217	#ifdef VBOX_STRICT
218	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
219	#endif
220	return VINF_SUCCESS;
221	}
222
223	/* Find sub-leaf insertion point. */
224	while ( i < cLeaves
225	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
226	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
227	i++;
228
229	/*
230	* If we've got an exactly matching leaf, replace it.
231	*/
232	if ( i < cLeaves
233	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
234	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
235	{
236	paLeaves[i] = *pNewLeaf;
237	#ifdef VBOX_STRICT
238	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
239	#endif
240	return VINF_SUCCESS;
241	}
242	}
243
244	/*
245	* Adding a new leaf at 'i'.
246	*/
247	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
248	paLeaves = cpumCpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
249	if (!paLeaves)
250	return VERR_NO_MEMORY;
251
252	if (i < cLeaves)
253	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
254	*pcLeaves += 1;
255	paLeaves[i] = *pNewLeaf;
256
257	#ifdef VBOX_STRICT
258	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
259	#endif
260	return VINF_SUCCESS;
261	}
262
263
264	#ifndef IN_VBOX_CPU_REPORT
265	/**
266	* Removes a range of CPUID leaves.
267	*
268	* This will not reallocate the array.
269	*
270	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
271	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
272	* @param uFirst The first leaf.
273	* @param uLast The last leaf.
274	*/
275	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
276	{
277	uint32_t cLeaves = *pcLeaves;
278
279	Assert(uFirst <= uLast);
280
281	/*
282	* Find the first one.
283	*/
284	uint32_t iFirst = 0;
285	while ( iFirst < cLeaves
286	&& paLeaves[iFirst].uLeaf < uFirst)
287	iFirst++;
288
289	/*
290	* Find the end (last + 1).
291	*/
292	uint32_t iEnd = iFirst;
293	while ( iEnd < cLeaves
294	&& paLeaves[iEnd].uLeaf <= uLast)
295	iEnd++;
296
297	/*
298	* Adjust the array if anything needs removing.
299	*/
300	if (iFirst < iEnd)
301	{
302	if (iEnd < cLeaves)
303	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
304	*pcLeaves = cLeaves -= (iEnd - iFirst);
305	}
306
307	# ifdef VBOX_STRICT
308	cpumCpuIdAssertOrder(paLeaves, *pcLeaves);
309	# endif
310	}
311	#endif /* IN_VBOX_CPU_REPORT */
312
313
314	/**
315	* Gets a CPU ID leaf.
316	*
317	* @returns VBox status code.
318	* @param pVM The cross context VM structure.
319	* @param pLeaf Where to store the found leaf.
320	* @param uLeaf The leaf to locate.
321	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
322	*/
323	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
324	{
325	PCPUMCPUIDLEAF pcLeaf = cpumCpuIdGetLeafInt(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
326	uLeaf, uSubLeaf);
327	if (pcLeaf)
328	{
329	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
330	return VINF_SUCCESS;
331	}
332
333	return VERR_NOT_FOUND;
334	}
335
336
337	/**
338	* Gets all the leaves.
339	*
340	* This only works after the CPUID leaves have been initialized. The interface
341	* is intended for NEM and configuring CPUID leaves for the native hypervisor.
342	*
343	* @returns Pointer to the array of leaves. NULL on failure.
344	* @param pVM The cross context VM structure.
345	* @param pcLeaves Where to return the number of leaves.
346	*/
347	VMMR3_INT_DECL(PCCPUMCPUIDLEAF) CPUMR3CpuIdGetPtr(PVM pVM, uint32_t *pcLeaves)
348	{
349	*pcLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
350	return pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
351	}
352
353
354	/**
355	* Inserts a CPU ID leaf, replacing any existing ones.
356	*
357	* @returns VBox status code.
358	* @param pVM The cross context VM structure.
359	* @param pNewLeaf Pointer to the leaf being inserted.
360	*/
361	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
362	{
363	/*
364	* Validate parameters.
365	*/
366	AssertReturn(pVM, VERR_INVALID_PARAMETER);
367	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
368
369	/*
370	* Disallow replacing CPU ID leaves that this API currently cannot manage.
371	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
372	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
373	*/
374	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
375	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
376	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
377	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
378	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
379	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
380	{
381	return VERR_NOT_SUPPORTED;
382	}
383
384	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
385	}
386
387
388	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
389	/**
390	* Determines the method the CPU uses to handle unknown CPUID leaves.
391	*
392	* @returns VBox status code.
393	* @param penmUnknownMethod Where to return the method.
394	* @param pDefUnknown Where to return default unknown values. This
395	* will be set, even if the resulting method
396	* doesn't actually needs it.
397	*/
398	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
399	{
400	uint32_t uLastStd = ASMCpuId_EAX(0);
401	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
402	if (!RTX86IsValidExtRange(uLastExt))
403	uLastExt = 0x80000000;
404
405	uint32_t auChecks[] =
406	{
407	uLastStd + 1,
408	uLastStd + 5,
409	uLastStd + 8,
410	uLastStd + 32,
411	uLastStd + 251,
412	uLastExt + 1,
413	uLastExt + 8,
414	uLastExt + 15,
415	uLastExt + 63,
416	uLastExt + 255,
417	0x7fbbffcc,
418	0x833f7872,
419	0xefff2353,
420	0x35779456,
421	0x1ef6d33e,
422	};
423
424	static const uint32_t s_auValues[] =
425	{
426	0xa95d2156,
427	0x00000001,
428	0x00000002,
429	0x00000008,
430	0x00000000,
431	0x55773399,
432	0x93401769,
433	0x12039587,
434	};
435
436	/*
437	* Simple method, all zeros.
438	*/
439	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
440	pDefUnknown->uEax = 0;
441	pDefUnknown->uEbx = 0;
442	pDefUnknown->uEcx = 0;
443	pDefUnknown->uEdx = 0;
444
445	/*
446	* Intel has been observed returning the last standard leaf.
447	*/
448	uint32_t auLast[4];
449	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
450
451	uint32_t cChecks = RT_ELEMENTS(auChecks);
452	while (cChecks > 0)
453	{
454	uint32_t auCur[4];
455	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
456	if (memcmp(auCur, auLast, sizeof(auCur)))
457	break;
458	cChecks--;
459	}
460	if (cChecks == 0)
461	{
462	/* Now, what happens when the input changes? Esp. ECX. */
463	uint32_t cTotal = 0;
464	uint32_t cSame = 0;
465	uint32_t cLastWithEcx = 0;
466	uint32_t cNeither = 0;
467	uint32_t cValues = RT_ELEMENTS(s_auValues);
468	while (cValues > 0)
469	{
470	uint32_t uValue = s_auValues[cValues - 1];
471	uint32_t auLastWithEcx[4];
472	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
473	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
474
475	cChecks = RT_ELEMENTS(auChecks);
476	while (cChecks > 0)
477	{
478	uint32_t auCur[4];
479	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
480	if (!memcmp(auCur, auLast, sizeof(auCur)))
481	{
482	cSame++;
483	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
484	cLastWithEcx++;
485	}
486	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
487	cLastWithEcx++;
488	else
489	cNeither++;
490	cTotal++;
491	cChecks--;
492	}
493	cValues--;
494	}
495
496	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
497	if (cSame == cTotal)
498	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
499	else if (cLastWithEcx == cTotal)
500	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
501	else
502	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
503	pDefUnknown->uEax = auLast[0];
504	pDefUnknown->uEbx = auLast[1];
505	pDefUnknown->uEcx = auLast[2];
506	pDefUnknown->uEdx = auLast[3];
507	return VINF_SUCCESS;
508	}
509
510	/*
511	* Unchanged register values?
512	*/
513	cChecks = RT_ELEMENTS(auChecks);
514	while (cChecks > 0)
515	{
516	uint32_t const uLeaf = auChecks[cChecks - 1];
517	uint32_t cValues = RT_ELEMENTS(s_auValues);
518	while (cValues > 0)
519	{
520	uint32_t uValue = s_auValues[cValues - 1];
521	uint32_t auCur[4];
522	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
523	if ( auCur[0] != uLeaf
524	\|\| auCur[1] != uValue
525	\|\| auCur[2] != uValue
526	\|\| auCur[3] != uValue)
527	break;
528	cValues--;
529	}
530	if (cValues != 0)
531	break;
532	cChecks--;
533	}
534	if (cChecks == 0)
535	{
536	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
537	return VINF_SUCCESS;
538	}
539
540	/*
541	* Just go with the simple method.
542	*/
543	return VINF_SUCCESS;
544	}
545	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
546
547
548	/**
549	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
550	*
551	* @returns Read only name string.
552	* @param enmUnknownMethod The method to translate.
553	*/
554	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
555	{
556	switch (enmUnknownMethod)
557	{
558	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
559	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
560	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
561	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
562
563	case CPUMUNKNOWNCPUID_INVALID:
564	case CPUMUNKNOWNCPUID_END:
565	case CPUMUNKNOWNCPUID_32BIT_HACK:
566	break;
567	}
568	return "Invalid-unknown-CPUID-method";
569	}
570
571
572	/*
573	*
574	* Init related code.
575	* Init related code.
576	* Init related code.
577	*
578	*
579	*/
580	#ifndef IN_VBOX_CPU_REPORT
581
582
583	/**
584	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
585	*
586	* This ignores the fSubLeafMask.
587	*
588	* @returns Pointer to the matching leaf, or NULL if not found.
589	* @param pCpum The CPUM instance data.
590	* @param uLeaf The leaf to locate.
591	* @param uSubLeaf The subleaf to locate.
592	*/
593	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
594	{
595	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
596	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
597	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
598	if (iEnd)
599	{
600	uint32_t iBegin = 0;
601	for (;;)
602	{
603	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
604	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
605	if (uNeedle < uCur)
606	{
607	if (i > iBegin)
608	iEnd = i;
609	else
610	break;
611	}
612	else if (uNeedle > uCur)
613	{
614	if (i + 1 < iEnd)
615	iBegin = i + 1;
616	else
617	break;
618	}
619	else
620	return &paLeaves[i];
621	}
622	}
623	return NULL;
624	}
625
626
627	/**
628	* Loads MSR range overrides.
629	*
630	* This must be called before the MSR ranges are moved from the normal heap to
631	* the hyper heap!
632	*
633	* @returns VBox status code (VMSetError called).
634	* @param pVM The cross context VM structure.
635	* @param pMsrNode The CFGM node with the MSR overrides.
636	*/
637	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
638	{
639	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
640	{
641	/*
642	* Assemble a valid MSR range.
643	*/
644	CPUMMSRRANGE MsrRange;
645	MsrRange.offCpumCpu = 0;
646	MsrRange.fReserved = 0;
647
648	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
649	if (RT_FAILURE(rc))
650	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
651
652	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
653	if (RT_FAILURE(rc))
654	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
655	MsrRange.szName, rc);
656
657	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
658	if (RT_FAILURE(rc))
659	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
660	MsrRange.szName, rc);
661
662	char szType[32];
663	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
664	if (RT_FAILURE(rc))
665	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
666	MsrRange.szName, rc);
667	if (!RTStrICmp(szType, "FixedValue"))
668	{
669	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
670	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
671
672	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
673	if (RT_FAILURE(rc))
674	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
675	MsrRange.szName, rc);
676
677	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
678	if (RT_FAILURE(rc))
679	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
680	MsrRange.szName, rc);
681
682	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
683	if (RT_FAILURE(rc))
684	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
685	MsrRange.szName, rc);
686	}
687	else
688	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
689	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
690
691	/*
692	* Insert the range into the table (replaces/splits/shrinks existing
693	* MSR ranges).
694	*/
695	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
696	&MsrRange);
697	if (RT_FAILURE(rc))
698	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
699	}
700
701	return VINF_SUCCESS;
702	}
703
704
705	/**
706	* Loads CPUID leaf overrides.
707	*
708	* This must be called before the CPUID leaves are moved from the normal
709	* heap to the hyper heap!
710	*
711	* @returns VBox status code (VMSetError called).
712	* @param pVM The cross context VM structure.
713	* @param pParentNode The CFGM node with the CPUID leaves.
714	* @param pszLabel How to label the overrides we're loading.
715	*/
716	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
717	{
718	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
719	{
720	/*
721	* Get the leaf and subleaf numbers.
722	*/
723	char szName[128];
724	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
725	if (RT_FAILURE(rc))
726	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
727
728	/* The leaf number is either specified directly or thru the node name. */
729	uint32_t uLeaf;
730	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
731	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
732	{
733	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
734	if (rc != VINF_SUCCESS)
735	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
736	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
737	}
738	else if (RT_FAILURE(rc))
739	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
740	pszLabel, szName, rc);
741
742	uint32_t uSubLeaf;
743	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
744	if (RT_FAILURE(rc))
745	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
746	pszLabel, szName, rc);
747
748	uint32_t fSubLeafMask;
749	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
750	if (RT_FAILURE(rc))
751	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
752	pszLabel, szName, rc);
753
754	/*
755	* Look up the specified leaf, since the output register values
756	* defaults to any existing values. This allows overriding a single
757	* register, without needing to know the other values.
758	*/
759	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
760	CPUMCPUIDLEAF Leaf;
761	if (pLeaf)
762	Leaf = *pLeaf;
763	else
764	RT_ZERO(Leaf);
765	Leaf.uLeaf = uLeaf;
766	Leaf.uSubLeaf = uSubLeaf;
767	Leaf.fSubLeafMask = fSubLeafMask;
768
769	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
770	if (RT_FAILURE(rc))
771	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
772	pszLabel, szName, rc);
773	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
774	if (RT_FAILURE(rc))
775	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
776	pszLabel, szName, rc);
777	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
778	if (RT_FAILURE(rc))
779	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
780	pszLabel, szName, rc);
781	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
782	if (RT_FAILURE(rc))
783	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
784	pszLabel, szName, rc);
785
786	/*
787	* Insert the leaf into the table (replaces existing ones).
788	*/
789	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
790	&Leaf);
791	if (RT_FAILURE(rc))
792	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
793	}
794
795	return VINF_SUCCESS;
796	}
797
798
799
800	/**
801	* Fetches overrides for a CPUID leaf.
802	*
803	* @returns VBox status code.
804	* @param pLeaf The leaf to load the overrides into.
805	* @param pCfgNode The CFGM node containing the overrides
806	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
807	* @param iLeaf The CPUID leaf number.
808	*/
809	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
810	{
811	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
812	if (pLeafNode)
813	{
814	uint32_t u32;
815	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
816	if (RT_SUCCESS(rc))
817	pLeaf->uEax = u32;
818	else
819	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
820
821	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
822	if (RT_SUCCESS(rc))
823	pLeaf->uEbx = u32;
824	else
825	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
826
827	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
828	if (RT_SUCCESS(rc))
829	pLeaf->uEcx = u32;
830	else
831	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
832
833	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
834	if (RT_SUCCESS(rc))
835	pLeaf->uEdx = u32;
836	else
837	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
838
839	}
840	return VINF_SUCCESS;
841	}
842
843
844	/**
845	* Load the overrides for a set of CPUID leaves.
846	*
847	* @returns VBox status code.
848	* @param paLeaves The leaf array.
849	* @param cLeaves The number of leaves.
850	* @param uStart The start leaf number.
851	* @param pCfgNode The CFGM node containing the overrides
852	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
853	*/
854	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
855	{
856	for (uint32_t i = 0; i < cLeaves; i++)
857	{
858	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
859	if (RT_FAILURE(rc))
860	return rc;
861	}
862
863	return VINF_SUCCESS;
864	}
865
866
867	/**
868	* Installs the CPUID leaves and explods the data into structures like
869	* GuestFeatures and CPUMCTX::aoffXState.
870	*
871	* @returns VBox status code.
872	* @param pVM The cross context VM structure.
873	* @param pCpum The CPUM part of @a VM.
874	* @param paLeaves The leaves. These will be copied (but not freed).
875	* @param cLeaves The number of leaves.
876	* @param pMsrs The MSRs.
877	*/
878	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
879	{
880	# ifdef VBOX_STRICT
881	cpumCpuIdAssertOrder(paLeaves, cLeaves);
882	# endif
883
884	/*
885	* Install the CPUID information.
886	*/
887	AssertLogRelMsgReturn(cLeaves <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves),
888	("cLeaves=%u - max %u\n", cLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves)),
889	VERR_CPUM_IPE_1); /** @todo better status! */
890	if (paLeaves != pCpum->GuestInfo.aCpuIdLeaves)
891	memcpy(pCpum->GuestInfo.aCpuIdLeaves, paLeaves, cLeaves * sizeof(paLeaves[0]));
892	pCpum->GuestInfo.paCpuIdLeavesR3 = pCpum->GuestInfo.aCpuIdLeaves;
893	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
894
895	/*
896	* Update the default CPUID leaf if necessary.
897	*/
898	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
899	{
900	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
901	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
902	{
903	/* We don't use CPUID(0).eax here because of the NT hack that only
904	changes that value without actually removing any leaves. */
905	uint32_t i = 0;
906	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
907	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
908	{
909	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
910	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
911	i++;
912	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
913	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
914	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
915	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
916	}
917	break;
918	}
919	default:
920	break;
921	}
922
923	/*
924	* Explode the guest CPU features.
925	*/
926	int rc = cpumCpuIdExplodeFeaturesX86(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
927	&pCpum->GuestFeatures);
928	AssertLogRelRCReturn(rc, rc);
929
930	/*
931	* Adjust the scalable bus frequency according to the CPUID information
932	* we're now using.
933	*/
934	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
935	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
936	? UINT64_C(100000000) /* 100MHz */
937	: UINT64_C(133333333); /* 133MHz */
938
939	/*
940	* Populate the legacy arrays. Currently used for everything, later only
941	* for patch manager.
942	*/
943	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
944	{
945	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
946	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
947	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
948	};
949	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
950	{
951	uint32_t cLeft = aOldRanges[i].cCpuIds;
952	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
953	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
954	while (cLeft-- > 0)
955	{
956	uLeaf--;
957	pLegacyLeaf--;
958
959	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
960	if (pLeaf)
961	{
962	pLegacyLeaf->uEax = pLeaf->uEax;
963	pLegacyLeaf->uEbx = pLeaf->uEbx;
964	pLegacyLeaf->uEcx = pLeaf->uEcx;
965	pLegacyLeaf->uEdx = pLeaf->uEdx;
966	}
967	else
968	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
969	}
970	}
971
972	/*
973	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
974	*/
975	PVMCPU pVCpu0 = pVM->apCpusR3[0];
976	AssertCompile(sizeof(pVCpu0->cpum.s.Guest.abXState) == CPUM_MAX_XSAVE_AREA_SIZE);
977	memset(&pVCpu0->cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVCpu0->cpum.s.Guest.aoffXState));
978	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
979	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
980	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
981	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
982	{
983	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
984	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
985	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
986	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
987	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
988	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
989	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
990	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
991	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
992	pCpum->GuestFeatures.cbMaxExtendedState),
993	VERR_CPUM_IPE_1);
994	pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
995	}
996
997	/* Copy the CPU #0 data to the other CPUs. */
998	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
999	{
1000	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1001	memcpy(&pVCpu->cpum.s.Guest.aoffXState[0], &pVCpu0->cpum.s.Guest.aoffXState[0], sizeof(pVCpu0->cpum.s.Guest.aoffXState));
1002	}
1003
1004	return VINF_SUCCESS;
1005	}
1006
1007
1008	/** @name Instruction Set Extension Options
1009	* @{ */
1010	/** Configuration option type (extended boolean, really). */
1011	typedef uint8_t CPUMISAEXTCFG;
1012	/** Always disable the extension. */
1013	#define CPUMISAEXTCFG_DISABLED false
1014	/** Enable the extension if it's supported by the host CPU. */
1015	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
1016	/** Enable the extension if it's supported by the host CPU, but don't let
1017	* the portable CPUID feature disable it. */
1018	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
1019	/** Always enable the extension. */
1020	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
1021	/** @} */
1022
1023	/**
1024	* CPUID Configuration (from CFGM).
1025	*
1026	* @remarks The members aren't document since we would only be duplicating the
1027	* \@cfgm entries in cpumR3CpuIdReadConfig.
1028	*/
1029	typedef struct CPUMCPUIDCONFIG
1030	{
1031	bool fNt4LeafLimit;
1032	bool fInvariantTsc;
1033	bool fForceVme;
1034	bool fNestedHWVirt;
1035
1036	CPUMISAEXTCFG enmCmpXchg16b;
1037	CPUMISAEXTCFG enmMonitor;
1038	CPUMISAEXTCFG enmMWaitExtensions;
1039	CPUMISAEXTCFG enmSse41;
1040	CPUMISAEXTCFG enmSse42;
1041	CPUMISAEXTCFG enmAvx;
1042	CPUMISAEXTCFG enmAvx2;
1043	CPUMISAEXTCFG enmXSave;
1044	CPUMISAEXTCFG enmAesNi;
1045	CPUMISAEXTCFG enmPClMul;
1046	CPUMISAEXTCFG enmPopCnt;
1047	CPUMISAEXTCFG enmMovBe;
1048	CPUMISAEXTCFG enmRdRand;
1049	CPUMISAEXTCFG enmRdSeed;
1050	CPUMISAEXTCFG enmSha;
1051	CPUMISAEXTCFG enmAdx;
1052	CPUMISAEXTCFG enmCLFlushOpt;
1053	CPUMISAEXTCFG enmFsGsBase;
1054	CPUMISAEXTCFG enmPcid;
1055	CPUMISAEXTCFG enmInvpcid;
1056	CPUMISAEXTCFG enmFlushCmdMsr;
1057	CPUMISAEXTCFG enmMdsClear;
1058	CPUMISAEXTCFG enmArchCapMsr;
1059
1060	CPUMISAEXTCFG enmAbm;
1061	CPUMISAEXTCFG enmSse4A;
1062	CPUMISAEXTCFG enmMisAlnSse;
1063	CPUMISAEXTCFG enm3dNowPrf;
1064	CPUMISAEXTCFG enmAmdExtMmx;
1065
1066	uint32_t uMaxStdLeaf;
1067	uint32_t uMaxExtLeaf;
1068	uint32_t uMaxCentaurLeaf;
1069	uint32_t uMaxIntelFamilyModelStep;
1070	char szCpuName[128];
1071	} CPUMCPUIDCONFIG;
1072	/** Pointer to CPUID config (from CFGM). */
1073	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
1074
1075
1076	/**
1077	* Mini CPU selection support for making Mac OS X happy.
1078	*
1079	* Executes the /CPUM/MaxIntelFamilyModelStep config.
1080	*
1081	* @param pCpum The CPUM instance data.
1082	* @param pConfig The CPUID configuration we've read from CFGM.
1083	*/
1084	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1085	{
1086	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1087	{
1088	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1089	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(RTX86GetCpuStepping(pStdFeatureLeaf->uEax),
1090	RTX86GetCpuModelIntel(pStdFeatureLeaf->uEax),
1091	RTX86GetCpuFamily(pStdFeatureLeaf->uEax),
1092	0);
1093	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
1094	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
1095	{
1096	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
1097	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
1098	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
1099	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
1100	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
1101	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
1102	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
1103	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
1104	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
1105	pStdFeatureLeaf->uEax = uNew;
1106	}
1107	}
1108	}
1109
1110
1111
1112	/**
1113	* Limit it the number of entries, zapping the remainder.
1114	*
1115	* The limits are masking off stuff about power saving and similar, this
1116	* is perhaps a bit crudely done as there is probably some relatively harmless
1117	* info too in these leaves (like words about having a constant TSC).
1118	*
1119	* @param pCpum The CPUM instance data.
1120	* @param pConfig The CPUID configuration we've read from CFGM.
1121	*/
1122	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1123	{
1124	/*
1125	* Standard leaves.
1126	*/
1127	uint32_t uSubLeaf = 0;
1128	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
1129	if (pCurLeaf)
1130	{
1131	uint32_t uLimit = pCurLeaf->uEax;
1132	if (uLimit <= UINT32_C(0x000fffff))
1133	{
1134	if (uLimit > pConfig->uMaxStdLeaf)
1135	{
1136	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
1137	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1138	uLimit + 1, UINT32_C(0x000fffff));
1139	}
1140
1141	/* NT4 hack, no zapping of extra leaves here. */
1142	if (pConfig->fNt4LeafLimit && uLimit > 3)
1143	pCurLeaf->uEax = uLimit = 3;
1144
1145	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
1146	pCurLeaf->uEax = uLimit;
1147	}
1148	else
1149	{
1150	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
1151	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1152	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
1153	}
1154	}
1155
1156	/*
1157	* Extended leaves.
1158	*/
1159	uSubLeaf = 0;
1160	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
1161	if (pCurLeaf)
1162	{
1163	uint32_t uLimit = pCurLeaf->uEax;
1164	if ( uLimit >= UINT32_C(0x80000000)
1165	&& uLimit <= UINT32_C(0x800fffff))
1166	{
1167	if (uLimit > pConfig->uMaxExtLeaf)
1168	{
1169	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
1170	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1171	uLimit + 1, UINT32_C(0x800fffff));
1172	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
1173	pCurLeaf->uEax = uLimit;
1174	}
1175	}
1176	else
1177	{
1178	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
1179	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1180	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
1181	}
1182	}
1183
1184	/*
1185	* Centaur leaves (VIA).
1186	*/
1187	uSubLeaf = 0;
1188	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
1189	if (pCurLeaf)
1190	{
1191	uint32_t uLimit = pCurLeaf->uEax;
1192	if ( uLimit >= UINT32_C(0xc0000000)
1193	&& uLimit <= UINT32_C(0xc00fffff))
1194	{
1195	if (uLimit > pConfig->uMaxCentaurLeaf)
1196	{
1197	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
1198	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1199	uLimit + 1, UINT32_C(0xcfffffff));
1200	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
1201	pCurLeaf->uEax = uLimit;
1202	}
1203	}
1204	else
1205	{
1206	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
1207	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1208	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
1209	}
1210	}
1211	}
1212
1213
1214	/**
1215	* Clears a CPUID leaf and all sub-leaves (to zero).
1216	*
1217	* @param pCpum The CPUM instance data.
1218	* @param uLeaf The leaf to clear.
1219	*/
1220	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
1221	{
1222	uint32_t uSubLeaf = 0;
1223	PCPUMCPUIDLEAF pCurLeaf;
1224	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
1225	{
1226	pCurLeaf->uEax = 0;
1227	pCurLeaf->uEbx = 0;
1228	pCurLeaf->uEcx = 0;
1229	pCurLeaf->uEdx = 0;
1230	uSubLeaf++;
1231	}
1232	}
1233
1234
1235	/**
1236	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
1237	* the given leaf.
1238	*
1239	* @returns pLeaf.
1240	* @param pCpum The CPUM instance data.
1241	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
1242	*/
1243	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
1244	{
1245	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
1246	if (pLeaf->fSubLeafMask != 0)
1247	{
1248	/*
1249	* Figure out how many sub-leaves in need of removal (we'll keep the first).
1250	* Log everything while we're at it.
1251	*/
1252	LogRel(("CPUM:\n"
1253	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
1254	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
1255	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
1256	for (;;)
1257	{
1258	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
1259	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
1260	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
1261	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
1262	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
1263	break;
1264	pSubLeaf++;
1265	}
1266	LogRel(("CPUM:\n"));
1267
1268	/*
1269	* Remove the offending sub-leaves.
1270	*/
1271	if (pSubLeaf != pLeaf)
1272	{
1273	if (pSubLeaf != pLast)
1274	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
1275	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
1276	}
1277
1278	/*
1279	* Convert the first sub-leaf into a single leaf.
1280	*/
1281	pLeaf->uSubLeaf = 0;
1282	pLeaf->fSubLeafMask = 0;
1283	}
1284	return pLeaf;
1285	}
1286
1287
1288	/**
1289	* Sanitizes and adjust the CPUID leaves.
1290	*
1291	* Drop features that aren't virtualized (or virtualizable). Adjust information
1292	* and capabilities to fit the virtualized hardware. Remove information the
1293	* guest shouldn't have (because it's wrong in the virtual world or because it
1294	* gives away host details) or that we don't have documentation for and no idea
1295	* what means.
1296	*
1297	* @returns VBox status code.
1298	* @param pVM The cross context VM structure (for cCpus).
1299	* @param pCpum The CPUM instance data.
1300	* @param pConfig The CPUID configuration we've read from CFGM.
1301	*/
1302	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1303	{
1304	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
1305	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
1306	{ \
1307	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
1308	(a_pLeafReg) &= ~(uint32_t)(fMask); \
1309	}
1310	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
1311	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
1312	{ \
1313	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
1314	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
1315	}
1316	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
1317	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
1318	&& ((a_pLeafReg) & (fBitMask)) \
1319	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
1320	{ \
1321	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
1322	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
1323	}
1324	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
1325
1326	/* The CPUID entries we start with here isn't necessarily the ones of the host, so we
1327	must consult HostFeatures when processing CPUMISAEXTCFG variables. */
1328	PCCPUMFEATURES pHstFeat = &pCpum->HostFeatures;
1329	#define PASSTHRU_FEATURE(enmConfig, fHostFeature, fConst) \
1330	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) ? (fConst) : 0)
1331	#define PASSTHRU_FEATURE_EX(enmConfig, fHostFeature, fAndExpr, fConst) \
1332	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) && (fAndExpr) ? (fConst) : 0)
1333	#define PASSTHRU_FEATURE_TODO(enmConfig, fConst) ((enmConfig) ? (fConst) : 0)
1334
1335	/* Cpuid 1:
1336	* EAX: CPU model, family and stepping.
1337	*
1338	* ECX + EDX: Supported features. Only report features we can support.
1339	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1340	* options may require adjusting (i.e. stripping what was enabled).
1341	*
1342	* EBX: Branding, CLFLUSH line size, logical processors per package and
1343	* initial APIC ID.
1344	*/
1345	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
1346	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
1347	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
1348
1349	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
1350	\| X86_CPUID_FEATURE_EDX_VME
1351	\| X86_CPUID_FEATURE_EDX_DE
1352	\| X86_CPUID_FEATURE_EDX_PSE
1353	\| X86_CPUID_FEATURE_EDX_TSC
1354	\| X86_CPUID_FEATURE_EDX_MSR
1355	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
1356	\| X86_CPUID_FEATURE_EDX_MCE
1357	\| X86_CPUID_FEATURE_EDX_CX8
1358	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
1359	//\| RT_BIT_32(10) - not defined
1360	\| X86_CPUID_FEATURE_EDX_SEP
1361	\| X86_CPUID_FEATURE_EDX_MTRR
1362	\| X86_CPUID_FEATURE_EDX_PGE
1363	\| X86_CPUID_FEATURE_EDX_MCA
1364	\| X86_CPUID_FEATURE_EDX_CMOV
1365	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
1366	\| X86_CPUID_FEATURE_EDX_PSE36
1367	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
1368	\| X86_CPUID_FEATURE_EDX_CLFSH
1369	//\| RT_BIT_32(20) - not defined
1370	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
1371	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
1372	\| X86_CPUID_FEATURE_EDX_MMX
1373	\| X86_CPUID_FEATURE_EDX_FXSR
1374	\| X86_CPUID_FEATURE_EDX_SSE
1375	\| X86_CPUID_FEATURE_EDX_SSE2
1376	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
1377	\| X86_CPUID_FEATURE_EDX_HTT
1378	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
1379	//\| RT_BIT_32(30) - not defined
1380	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
1381	;
1382	pStdFeatureLeaf->uEcx &= X86_CPUID_FEATURE_ECX_SSE3
1383	\| PASSTHRU_FEATURE_TODO(pConfig->enmPClMul, X86_CPUID_FEATURE_ECX_PCLMUL)
1384	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
1385	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
1386	\| PASSTHRU_FEATURE_EX(pConfig->enmMonitor, pHstFeat->fMonitorMWait, pVM->cCpus == 1, X86_CPUID_FEATURE_ECX_MONITOR)
1387	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
1388	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
1389	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
1390	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
1391	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
1392	\| X86_CPUID_FEATURE_ECX_SSSE3
1393	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
1394	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
1395	\| PASSTHRU_FEATURE(pConfig->enmCmpXchg16b, pHstFeat->fMovCmpXchg16b, X86_CPUID_FEATURE_ECX_CX16)
1396	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
1397	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1398	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
1399	\| PASSTHRU_FEATURE(pConfig->enmPcid, pHstFeat->fPcid, X86_CPUID_FEATURE_ECX_PCID)
1400	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
1401	\| PASSTHRU_FEATURE(pConfig->enmSse41, pHstFeat->fSse41, X86_CPUID_FEATURE_ECX_SSE4_1)
1402	\| PASSTHRU_FEATURE(pConfig->enmSse42, pHstFeat->fSse42, X86_CPUID_FEATURE_ECX_SSE4_2)
1403	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
1404	\| PASSTHRU_FEATURE_TODO(pConfig->enmMovBe, X86_CPUID_FEATURE_ECX_MOVBE)
1405	\| PASSTHRU_FEATURE(pConfig->enmPopCnt, pHstFeat->fPopCnt, X86_CPUID_FEATURE_ECX_POPCNT)
1406	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
1407	\| PASSTHRU_FEATURE_TODO(pConfig->enmAesNi, X86_CPUID_FEATURE_ECX_AES)
1408	\| PASSTHRU_FEATURE(pConfig->enmXSave, pHstFeat->fXSaveRstor, X86_CPUID_FEATURE_ECX_XSAVE)
1409	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
1410	\| PASSTHRU_FEATURE(pConfig->enmAvx, pHstFeat->fAvx, X86_CPUID_FEATURE_ECX_AVX)
1411	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
1412	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdRand, X86_CPUID_FEATURE_ECX_RDRAND)
1413	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
1414	;
1415
1416	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
1417	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
1418	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
1419	{
1420	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
1421	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
1422	}
1423
1424	if (pCpum->u8PortableCpuIdLevel > 0)
1425	{
1426	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
1427	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
1428	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
1429	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
1430	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
1431	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
1432	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
1433	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
1434	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
1435	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
1436	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
1437	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
1438	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
1439	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
1440	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
1441	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
1442	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
1443	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
1444	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
1445	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
1446
1447	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP ///??
1448	\| X86_CPUID_FEATURE_EDX_PSN
1449	\| X86_CPUID_FEATURE_EDX_DS
1450	\| X86_CPUID_FEATURE_EDX_ACPI
1451	\| X86_CPUID_FEATURE_EDX_SS
1452	\| X86_CPUID_FEATURE_EDX_TM
1453	\| X86_CPUID_FEATURE_EDX_PBE
1454	)));
1455	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
1456	\| X86_CPUID_FEATURE_ECX_CPLDS
1457	\| X86_CPUID_FEATURE_ECX_AES
1458	\| X86_CPUID_FEATURE_ECX_VMX
1459	\| X86_CPUID_FEATURE_ECX_SMX
1460	\| X86_CPUID_FEATURE_ECX_EST
1461	\| X86_CPUID_FEATURE_ECX_TM2
1462	\| X86_CPUID_FEATURE_ECX_CNTXID
1463	\| X86_CPUID_FEATURE_ECX_FMA
1464	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1465	\| X86_CPUID_FEATURE_ECX_PDCM
1466	\| X86_CPUID_FEATURE_ECX_DCA
1467	\| X86_CPUID_FEATURE_ECX_OSXSAVE
1468	)));
1469	}
1470
1471	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
1472	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
1473
1474	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
1475	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
1476	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
1477	*/
1478	#ifdef VBOX_WITH_MULTI_CORE
1479	if (pVM->cCpus > 1)
1480	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
1481	#endif
1482	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
1483	{
1484	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
1485	core times the number of CPU cores per processor */
1486	#ifdef VBOX_WITH_MULTI_CORE
1487	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
1488	#else
1489	/* Single logical processor in a package. */
1490	pStdFeatureLeaf->uEbx \|= (1 << 16);
1491	#endif
1492	}
1493
1494	uint32_t uMicrocodeRev;
1495	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
1496	if (RT_SUCCESS(rc))
1497	{
1498	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
1499	}
1500	else
1501	{
1502	uMicrocodeRev = 0;
1503	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
1504	}
1505
1506	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
1507	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
1508	*/
1509	if ( ( pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen
1510	/** @todo The following ASSUMES that Hygon uses the same version numbering
1511	* as AMD and that they shipped buggy firmware. */
1512	\|\| pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Hygon_Dhyana)
1513	&& uMicrocodeRev < 0x8001126
1514	&& !pConfig->fForceVme)
1515	{
1516	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
1517	LogRel(("CPUM: Zen VME workaround engaged\n"));
1518	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
1519	}
1520
1521	/* Force standard feature bits. */
1522	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
1523	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
1524	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
1525	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
1526	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
1527	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
1528	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1529	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
1530	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1531	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
1532	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
1533	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
1534	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
1535	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
1536	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
1537	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
1538	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
1539	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
1540	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1541	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
1542	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
1543	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
1544
1545	pStdFeatureLeaf = NULL; /* Must refetch! */
1546
1547	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
1548	* AMD:
1549	* EAX: CPU model, family and stepping.
1550	*
1551	* ECX + EDX: Supported features. Only report features we can support.
1552	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1553	* options may require adjusting (i.e. stripping what was enabled).
1554	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
1555	*
1556	* EBX: Branding ID and package type (or reserved).
1557	*
1558	* Intel and probably most others:
1559	* EAX: 0
1560	* EBX: 0
1561	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
1562	*/
1563	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
1564	if (pExtFeatureLeaf)
1565	{
1566	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
1567
1568	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
1569	\| X86_CPUID_AMD_FEATURE_EDX_VME
1570	\| X86_CPUID_AMD_FEATURE_EDX_DE
1571	\| X86_CPUID_AMD_FEATURE_EDX_PSE
1572	\| X86_CPUID_AMD_FEATURE_EDX_TSC
1573	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
1574	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
1575	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
1576	\| X86_CPUID_AMD_FEATURE_EDX_CX8
1577	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
1578	//\| RT_BIT_32(10) - reserved
1579	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1580	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
1581	\| X86_CPUID_AMD_FEATURE_EDX_PGE
1582	\| X86_CPUID_AMD_FEATURE_EDX_MCA
1583	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
1584	\| X86_CPUID_AMD_FEATURE_EDX_PAT
1585	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
1586	//\| RT_BIT_32(18) - reserved
1587	//\| RT_BIT_32(19) - reserved
1588	\| X86_CPUID_EXT_FEATURE_EDX_NX
1589	//\| RT_BIT_32(21) - reserved
1590	\| PASSTHRU_FEATURE(pConfig->enmAmdExtMmx, pHstFeat->fAmdMmxExts, X86_CPUID_AMD_FEATURE_EDX_AXMMX)
1591	\| X86_CPUID_AMD_FEATURE_EDX_MMX
1592	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
1593	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
1594	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1595	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
1596	//\| RT_BIT_32(28) - reserved
1597	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
1598	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
1599	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
1600	;
1601	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
1602	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
1603	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
1604	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1605	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
1606	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
1607	\| PASSTHRU_FEATURE(pConfig->enmAbm, pHstFeat->fAbm, X86_CPUID_AMD_FEATURE_ECX_ABM)
1608	\| PASSTHRU_FEATURE_TODO(pConfig->enmSse4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A)
1609	\| PASSTHRU_FEATURE_TODO(pConfig->enmMisAlnSse, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE)
1610	\| PASSTHRU_FEATURE(pConfig->enm3dNowPrf, pHstFeat->f3DNowPrefetch, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1611	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
1612	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
1613	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
1614	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1615	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
1616	//\| RT_BIT_32(14) - reserved
1617	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
1618	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
1619	//\| RT_BIT_32(17) - reserved
1620	//\| RT_BIT_32(18) - reserved
1621	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
1622	//\| RT_BIT_32(20) - reserved
1623	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
1624	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
1625	//\| RT_BIT_32(23) - reserved
1626	//\| RT_BIT_32(24) - reserved
1627	//\| RT_BIT_32(25) - reserved
1628	//\| RT_BIT_32(26) - reserved
1629	//\| RT_BIT_32(27) - reserved
1630	//\| RT_BIT_32(28) - reserved
1631	//\| RT_BIT_32(29) - reserved
1632	//\| RT_BIT_32(30) - reserved
1633	//\| RT_BIT_32(31) - reserved
1634	;
1635	#ifdef VBOX_WITH_MULTI_CORE
1636	if ( pVM->cCpus > 1
1637	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
1638	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
1639	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
1640	#endif
1641
1642	if (pCpum->u8PortableCpuIdLevel > 0)
1643	{
1644	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1645	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
1646	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
1647	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
1648	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
1649	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
1650	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
1651	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
1652	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
1653	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
1654	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1655	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1656	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1657	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1658	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1659	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1660
1661	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
1662	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1663	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
1664	\| X86_CPUID_AMD_FEATURE_ECX_IBS
1665	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1666	\| X86_CPUID_AMD_FEATURE_ECX_WDT
1667	\| X86_CPUID_AMD_FEATURE_ECX_LWP
1668	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
1669	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
1670	\| UINT32_C(0xff964000)
1671	)));
1672	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
1673	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1674	\| RT_BIT(18)
1675	\| RT_BIT(19)
1676	\| RT_BIT(21)
1677	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
1678	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1679	\| RT_BIT(28)
1680	)));
1681	}
1682
1683	/* Force extended feature bits. */
1684	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
1685	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
1686	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
1687	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
1688	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
1689	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
1690	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
1691	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
1692	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1693	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
1694	}
1695	pExtFeatureLeaf = NULL; /* Must refetch! */
1696
1697
1698	/* Cpuid 2:
1699	* Intel: (Nondeterministic) Cache and TLB information
1700	* AMD: Reserved
1701	* VIA: Reserved
1702	* Safe to expose.
1703	*/
1704	uint32_t uSubLeaf = 0;
1705	PCPUMCPUIDLEAF pCurLeaf;
1706	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
1707	{
1708	if ((pCurLeaf->uEax & 0xff) > 1)
1709	{
1710	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
1711	pCurLeaf->uEax &= UINT32_C(0xffffff01);
1712	}
1713	uSubLeaf++;
1714	}
1715
1716	/* Cpuid 3:
1717	* Intel: EAX, EBX - reserved (transmeta uses these)
1718	* ECX, EDX - Processor Serial Number if available, otherwise reserved
1719	* AMD: Reserved
1720	* VIA: Reserved
1721	* Safe to expose
1722	*/
1723	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1724	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
1725	{
1726	uSubLeaf = 0;
1727	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
1728	{
1729	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1730	if (pCpum->u8PortableCpuIdLevel > 0)
1731	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1732	uSubLeaf++;
1733	}
1734	}
1735
1736	/* Cpuid 4 + ECX:
1737	* Intel: Deterministic Cache Parameters Leaf.
1738	* AMD: Reserved
1739	* VIA: Reserved
1740	* Safe to expose, except for EAX:
1741	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1742	* Bits 31-26: Maximum number of processor cores in this physical package**
1743	* Note: These SMP values are constant regardless of ECX
1744	*/
1745	uSubLeaf = 0;
1746	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
1747	{
1748	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
1749	#ifdef VBOX_WITH_MULTI_CORE
1750	if ( pVM->cCpus > 1
1751	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1752	{
1753	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1754	/* One logical processor with possibly multiple cores. */
1755	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1756	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
1757	}
1758	#endif
1759	uSubLeaf++;
1760	}
1761
1762	/* Cpuid 5: Monitor/mwait Leaf
1763	* Intel: ECX, EDX - reserved
1764	* EAX, EBX - Smallest and largest monitor line size
1765	* AMD: EDX - reserved
1766	* EAX, EBX - Smallest and largest monitor line size
1767	* ECX - extensions (ignored for now)
1768	* VIA: Reserved
1769	* Safe to expose
1770	*/
1771	uSubLeaf = 0;
1772	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
1773	{
1774	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1775	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
1776	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1777
1778	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1779	if (pConfig->enmMWaitExtensions)
1780	{
1781	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1782	/** @todo for now we just expose host's MWAIT C-states, although conceptually
1783	it shall be part of our power management virtualization model */
1784	#if 0
1785	/* MWAIT sub C-states */
1786	pCurLeaf->uEdx =
1787	(0 << 0) /* 0 in C0 */ \|
1788	(2 << 4) /* 2 in C1 */ \|
1789	(2 << 8) /* 2 in C2 */ \|
1790	(2 << 12) /* 2 in C3 */ \|
1791	(0 << 16) /* 0 in C4 */
1792	;
1793	#endif
1794	}
1795	else
1796	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1797	uSubLeaf++;
1798	}
1799
1800	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
1801	* Intel: Various stuff.
1802	* AMD: EAX, EBX, EDX - reserved.
1803	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
1804	* present. Same as intel.
1805	* VIA: ??
1806	*
1807	* We clear everything here for now.
1808	*/
1809	cpumR3CpuIdZeroLeaf(pCpum, 6);
1810
1811	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
1812	* EAX: Number of sub leaves.
1813	* EBX+ECX+EDX: Feature flags
1814	*
1815	* We only have documentation for one sub-leaf, so clear all other (no need
1816	* to remove them as such, just set them to zero).
1817	*
1818	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1819	* options may require adjusting (i.e. stripping what was enabled).
1820	*/
1821	uSubLeaf = 0;
1822	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
1823	{
1824	switch (uSubLeaf)
1825	{
1826	case 0:
1827	{
1828	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
1829	pCurLeaf->uEbx &= 0
1830	\| PASSTHRU_FEATURE(pConfig->enmFsGsBase, pHstFeat->fFsGsBase, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE)
1831	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
1832	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
1833	\| X86_CPUID_STEXT_FEATURE_EBX_BMI1
1834	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
1835	\| PASSTHRU_FEATURE(pConfig->enmAvx2, pHstFeat->fAvx2, X86_CPUID_STEXT_FEATURE_EBX_AVX2)
1836	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
1837	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
1838	\| X86_CPUID_STEXT_FEATURE_EBX_BMI2
1839	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
1840	\| PASSTHRU_FEATURE(pConfig->enmInvpcid, pHstFeat->fInvpcid, X86_CPUID_STEXT_FEATURE_EBX_INVPCID)
1841	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
1842	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
1843	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
1844	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
1845	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
1846	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
1847	//\| RT_BIT(17) - reserved
1848	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdSeed, X86_CPUID_STEXT_FEATURE_EBX_RDSEED)
1849	\| PASSTHRU_FEATURE(pConfig->enmAdx, pHstFeat->fAdx, X86_CPUID_STEXT_FEATURE_EBX_ADX)
1850	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
1851	//\| RT_BIT(21) - reserved
1852	//\| RT_BIT(22) - reserved
1853	\| PASSTHRU_FEATURE(pConfig->enmCLFlushOpt, pHstFeat->fClFlushOpt, X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT)
1854	//\| RT_BIT(24) - reserved
1855	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
1856	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
1857	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
1858	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
1859	\| PASSTHRU_FEATURE(pConfig->enmSha, pHstFeat->fSha, X86_CPUID_STEXT_FEATURE_EBX_SHA)
1860	//\| RT_BIT(30) - reserved
1861	//\| RT_BIT(31) - reserved
1862	;
1863	pCurLeaf->uEcx &= 0
1864	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
1865	;
1866	pCurLeaf->uEdx &= 0
1867	\| PASSTHRU_FEATURE(pConfig->enmMdsClear, pHstFeat->fMdsClear, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR)
1868	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
1869	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
1870	\| PASSTHRU_FEATURE(pConfig->enmFlushCmdMsr, pHstFeat->fFlushCmd, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD)
1871	\| PASSTHRU_FEATURE(pConfig->enmArchCapMsr, pHstFeat->fArchCap, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
1872	;
1873
1874	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
1875	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
1876	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
1877	{
1878	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
1879	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
1880	}
1881
1882	if (pCpum->u8PortableCpuIdLevel > 0)
1883	{
1884	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
1885	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
1886	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
1887	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
1888	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
1889	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
1890	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1891	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
1892	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, ADX, X86_CPUID_STEXT_FEATURE_EBX_ADX, pConfig->enmAdx);
1893	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
1894	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
1895	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
1896	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
1897	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
1898	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA, pConfig->enmSha);
1899	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
1900	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
1901	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
1902	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
1903	}
1904
1905	/* Dependencies. */
1906	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
1907	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
1908
1909	/* Force standard feature bits. */
1910	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
1911	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
1912	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1913	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
1914	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
1915	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
1916	if (pConfig->enmAdx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1917	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_ADX;
1918	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
1919	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
1920	if (pConfig->enmSha == CPUMISAEXTCFG_ENABLED_ALWAYS)
1921	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_SHA;
1922	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
1923	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
1924	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
1925	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
1926	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
1927	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
1928	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
1929	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
1930	break;
1931	}
1932
1933	default:
1934	/* Invalid index, all values are zero. */
1935	pCurLeaf->uEax = 0;
1936	pCurLeaf->uEbx = 0;
1937	pCurLeaf->uEcx = 0;
1938	pCurLeaf->uEdx = 0;
1939	break;
1940	}
1941	uSubLeaf++;
1942	}
1943
1944	/* Cpuid 8: Marked as reserved by Intel and AMD.
1945	* We zero this since we don't know what it may have been used for.
1946	*/
1947	cpumR3CpuIdZeroLeaf(pCpum, 8);
1948
1949	/* Cpuid 9: Direct Cache Access (DCA) Parameters
1950	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
1951	* EBX, ECX, EDX - reserved.
1952	* AMD: Reserved
1953	* VIA: ??
1954	*
1955	* We zero this.
1956	*/
1957	cpumR3CpuIdZeroLeaf(pCpum, 9);
1958
1959	/* Cpuid 0xa: Architectural Performance Monitor Features
1960	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
1961	* EBX, ECX, EDX - reserved.
1962	* AMD: Reserved
1963	* VIA: ??
1964	*
1965	* We zero this, for now at least.
1966	*/
1967	cpumR3CpuIdZeroLeaf(pCpum, 10);
1968
1969	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
1970	* Intel: EAX - APCI ID shift right for next level.
1971	* EBX - Factory configured cores/threads at this level.
1972	* ECX - Level number (same as input) and level type (1,2,0).
1973	* EDX - Extended initial APIC ID.
1974	* AMD: Reserved
1975	* VIA: ??
1976	*/
1977	uSubLeaf = 0;
1978	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
1979	{
1980	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
1981	{
1982	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
1983	if (bLevelType == 1)
1984	{
1985	/* Thread level - we don't do threads at the moment. */
1986	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
1987	pCurLeaf->uEbx = 1;
1988	}
1989	else if (bLevelType == 2)
1990	{
1991	/* Core level. */
1992	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
1993	#ifdef VBOX_WITH_MULTI_CORE
1994	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
1995	pCurLeaf->uEax++;
1996	#endif
1997	pCurLeaf->uEbx = pVM->cCpus;
1998	}
1999	else
2000	{
2001	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
2002	pCurLeaf->uEax = 0;
2003	pCurLeaf->uEbx = 0;
2004	pCurLeaf->uEcx = 0;
2005	}
2006	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
2007	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
2008	}
2009	else
2010	{
2011	pCurLeaf->uEax = 0;
2012	pCurLeaf->uEbx = 0;
2013	pCurLeaf->uEcx = 0;
2014	pCurLeaf->uEdx = 0;
2015	}
2016	uSubLeaf++;
2017	}
2018
2019	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
2020	* We zero this since we don't know what it may have been used for.
2021	*/
2022	cpumR3CpuIdZeroLeaf(pCpum, 12);
2023
2024	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
2025	* ECX=0: EAX - Valid bits in XCR0[31:0].
2026	* EBX - Maximum state size as per current XCR0 value.
2027	* ECX - Maximum state size for all supported features.
2028	* EDX - Valid bits in XCR0[63:32].
2029	* ECX=1: EAX - Various X-features.
2030	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
2031	* ECX - Valid bits in IA32_XSS[31:0].
2032	* EDX - Valid bits in IA32_XSS[63:32].
2033	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
2034	* if the bit invalid all four registers are set to zero.
2035	* EAX - The state size for this feature.
2036	* EBX - The state byte offset of this feature.
2037	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
2038	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
2039	*
2040	* Clear them all as we don't currently implement extended CPU state.
2041	*/
2042	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
2043	uint64_t fGuestXcr0Mask = 0;
2044	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2045	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
2046	{
2047	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
2048	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
2049	fGuestXcr0Mask \|= XSAVE_C_YMM;
2050	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
2051	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
2052	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
2053	fGuestXcr0Mask &= pCpum->fXStateHostMask;
2054
2055	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
2056	}
2057	pStdFeatureLeaf = NULL;
2058	pCpum->fXStateGuestMask = fGuestXcr0Mask;
2059
2060	/* Work the sub-leaves. */
2061	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
2062	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
2063	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
2064	{
2065	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
2066	if (pCurLeaf)
2067	{
2068	if (fGuestXcr0Mask)
2069	{
2070	switch (uSubLeaf)
2071	{
2072	case 0:
2073	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
2074	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
2075	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2076	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
2077	VERR_CPUM_IPE_1);
2078	cbXSaveMaxActual = pCurLeaf->uEcx;
2079	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
2080	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
2081	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
2082	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
2083	VERR_CPUM_IPE_2);
2084	continue;
2085	case 1:
2086	pCurLeaf->uEax &= 0;
2087	pCurLeaf->uEcx &= 0;
2088	pCurLeaf->uEdx &= 0;
2089	/** @todo what about checking ebx? */
2090	continue;
2091	default:
2092	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
2093	{
2094	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
2095	&& pCurLeaf->uEax > 0
2096	&& pCurLeaf->uEbx < cbXSaveMaxActual
2097	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2098	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
2099	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
2100	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
2101	VERR_CPUM_IPE_2);
2102	AssertLogRel(!(pCurLeaf->uEcx & 1));
2103	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
2104	pCurLeaf->uEdx = 0; /* it's reserved... */
2105	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
2106	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
2107	continue;
2108	}
2109	break;
2110	}
2111	}
2112
2113	/* Clear the leaf. */
2114	pCurLeaf->uEax = 0;
2115	pCurLeaf->uEbx = 0;
2116	pCurLeaf->uEcx = 0;
2117	pCurLeaf->uEdx = 0;
2118	}
2119	}
2120
2121	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
2122	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
2123	{
2124	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
2125	if (pCurLeaf)
2126	{
2127	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
2128	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
2129	pCurLeaf->uEbx = cbXSaveMaxReport;
2130	pCurLeaf->uEcx = cbXSaveMaxReport;
2131	}
2132	}
2133
2134	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
2135	* We zero this since we don't know what it may have been used for.
2136	*/
2137	cpumR3CpuIdZeroLeaf(pCpum, 14);
2138
2139	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
2140	* also known as Intel Resource Director Technology (RDT) Monitoring
2141	* We zero this as we don't currently virtualize PQM.
2142	*/
2143	cpumR3CpuIdZeroLeaf(pCpum, 15);
2144
2145	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
2146	* also known as Intel Resource Director Technology (RDT) Allocation
2147	* We zero this as we don't currently virtualize PQE.
2148	*/
2149	cpumR3CpuIdZeroLeaf(pCpum, 16);
2150
2151	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
2152	* We zero this since we don't know what it may have been used for.
2153	*/
2154	cpumR3CpuIdZeroLeaf(pCpum, 17);
2155
2156	/* Cpuid 0x12 + ECX: SGX resource enumeration.
2157	* We zero this as we don't currently virtualize this.
2158	*/
2159	cpumR3CpuIdZeroLeaf(pCpum, 18);
2160
2161	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
2162	* We zero this since we don't know what it may have been used for.
2163	*/
2164	cpumR3CpuIdZeroLeaf(pCpum, 19);
2165
2166	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
2167	* We zero this as we don't currently virtualize this.
2168	*/
2169	cpumR3CpuIdZeroLeaf(pCpum, 20);
2170
2171	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
2172	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
2173	* EAX - denominator (unsigned).
2174	* EBX - numerator (unsigned).
2175	* ECX, EDX - reserved.
2176	* AMD: Reserved / undefined / not implemented.
2177	* VIA: Reserved / undefined / not implemented.
2178	* We zero this as we don't currently virtualize this.
2179	*/
2180	cpumR3CpuIdZeroLeaf(pCpum, 21);
2181
2182	/* Cpuid 0x16: Processor frequency info
2183	* Intel: EAX - Core base frequency in MHz.
2184	* EBX - Core maximum frequency in MHz.
2185	* ECX - Bus (reference) frequency in MHz.
2186	* EDX - Reserved.
2187	* AMD: Reserved / undefined / not implemented.
2188	* VIA: Reserved / undefined / not implemented.
2189	* We zero this as we don't currently virtualize this.
2190	*/
2191	cpumR3CpuIdZeroLeaf(pCpum, 22);
2192
2193	/* Cpuid 0x17..0x10000000: Unknown.
2194	* We don't know these and what they mean, so remove them. */
2195	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2196	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
2197
2198
2199	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
2200	* We remove all these as we're a hypervisor and must provide our own.
2201	*/
2202	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2203	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
2204
2205
2206	/* Cpuid 0x80000000 is harmless. */
2207
2208	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
2209
2210	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
2211
2212	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
2213	* Safe to pass on to the guest.
2214	*
2215	* AMD: 0x800000005 L1 cache information
2216	* 0x800000006 L2/L3 cache information
2217	* Intel: 0x800000005 reserved
2218	* 0x800000006 L2 cache information
2219	* VIA: 0x800000005 TLB and L1 cache information
2220	* 0x800000006 L2 cache information
2221	*/
2222
2223	/* Cpuid 0x800000007: Advanced Power Management Information.
2224	* AMD: EAX: Processor feedback capabilities.
2225	* EBX: RAS capabilites.
2226	* ECX: Advanced power monitoring interface.
2227	* EDX: Enhanced power management capabilities.
2228	* Intel: EAX, EBX, ECX - reserved.
2229	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
2230	* VIA: Reserved
2231	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
2232	*/
2233	uSubLeaf = 0;
2234	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
2235	{
2236	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
2237	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2238	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2239	{
2240	/*
2241	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
2242	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
2243	* bit is now configurable.
2244	*/
2245	pCurLeaf->uEdx &= 0
2246	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
2247	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
2248	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
2249	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
2250	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
2251	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
2252	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
2253	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
2254	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
2255	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
2256	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
2257	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
2258	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
2259	\| 0;
2260	}
2261	else
2262	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2263	if (!pConfig->fInvariantTsc)
2264	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2265	uSubLeaf++;
2266	}
2267
2268	/* Cpuid 0x80000008:
2269	* AMD: EAX: Long Mode Size Identifiers
2270	* EBX: Extended Feature Identifiers
2271	* ECX: Number of cores + APICIdCoreIdSize
2272	* EDX: RDPRU Register Identifier Range
2273	* Intel: EAX: Virtual/Physical address Size
2274	* EBX, ECX, EDX - reserved
2275	* VIA: EAX: Virtual/Physical address Size
2276	* EBX, ECX, EDX - reserved
2277	*
2278	* We only expose the virtual+pysical address size to the guest atm.
2279	* On AMD we set the core count, but not the apic id stuff as we're
2280	* currently not doing the apic id assignments in a compatible manner.
2281	*/
2282	uSubLeaf = 0;
2283	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
2284	{
2285	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
2286	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2287	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2288	{
2289	/* Expose XSaveErPtr aka RstrFpErrPtrs to guest. */
2290	pCurLeaf->uEbx &= X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR; /* reserved - [12] == IBPB */
2291	}
2292	else
2293	pCurLeaf->uEbx = 0; /* reserved */
2294
2295	pCurLeaf->uEdx = 0; /* reserved */
2296
2297	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
2298	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
2299	pCurLeaf->uEcx = 0;
2300	#ifdef VBOX_WITH_MULTI_CORE
2301	if ( pVM->cCpus > 1
2302	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2303	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
2304	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
2305	#endif
2306	uSubLeaf++;
2307	}
2308
2309	/* Cpuid 0x80000009: Reserved
2310	* We zero this since we don't know what it may have been used for.
2311	*/
2312	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
2313
2314	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
2315	* AMD: EAX - SVM revision.
2316	* EBX - Number of ASIDs.
2317	* ECX - Reserved.
2318	* EDX - SVM Feature identification.
2319	*/
2320	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2321	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2322	{
2323	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2324	if ( pExtFeatureLeaf
2325	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
2326	{
2327	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
2328	if (pSvmFeatureLeaf)
2329	{
2330	pSvmFeatureLeaf->uEax = 0x1;
2331	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
2332	pSvmFeatureLeaf->uEcx = 0;
2333	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
2334	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
2335	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
2336	}
2337	else
2338	{
2339	/* Should never happen. */
2340	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
2341	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2342	}
2343	}
2344	else
2345	{
2346	/* If SVM is not supported, this is reserved, zero out. */
2347	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2348	}
2349	}
2350	else
2351	{
2352	/* Cpuid 0x8000000a: Reserved on Intel.
2353	* We zero this since we don't know what it may have been used for.
2354	*/
2355	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2356	}
2357
2358	/* Cpuid 0x8000000b thru 0x80000018: Reserved
2359	* We clear these as we don't know what purpose they might have. */
2360	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
2361	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
2362
2363	/* Cpuid 0x80000019: TLB configuration
2364	* Seems to be harmless, pass them thru as is. */
2365
2366	/* Cpuid 0x8000001a: Peformance optimization identifiers.
2367	* Strip anything we don't know what is or addresses feature we don't implement. */
2368	uSubLeaf = 0;
2369	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
2370	{
2371	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
2372	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
2373	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
2374	;
2375	pCurLeaf->uEbx = 0; /* reserved */
2376	pCurLeaf->uEcx = 0; /* reserved */
2377	pCurLeaf->uEdx = 0; /* reserved */
2378	uSubLeaf++;
2379	}
2380
2381	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
2382	* Clear this as we don't currently virtualize this feature. */
2383	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
2384
2385	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
2386	* Clear this as we don't currently virtualize this feature. */
2387	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
2388
2389	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
2390	* We need to sanitize the cores per cache (EAX[25:14]).
2391	*
2392	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
2393	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
2394	* slightly different meaning.
2395	*/
2396	uSubLeaf = 0;
2397	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
2398	{
2399	#ifdef VBOX_WITH_MULTI_CORE
2400	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
2401	if (cCores > pVM->cCpus)
2402	cCores = pVM->cCpus;
2403	pCurLeaf->uEax &= UINT32_C(0x00003fff);
2404	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
2405	#else
2406	pCurLeaf->uEax &= UINT32_C(0x00003fff);
2407	#endif
2408	uSubLeaf++;
2409	}
2410
2411	/* Cpuid 0x8000001e: Get APIC / unit / node information.
2412	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
2413	* setup, we have one compute unit with all the cores in it. Single node.
2414	*/
2415	uSubLeaf = 0;
2416	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
2417	{
2418	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
2419	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
2420	{
2421	#ifdef VBOX_WITH_MULTI_CORE
2422	pCurLeaf->uEbx = pVM->cCpus < 0x100
2423	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
2424	#else
2425	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
2426	#endif
2427	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
2428	}
2429	else
2430	{
2431	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
2432	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_HYGON);
2433	pCurLeaf->uEbx = 0; /* Reserved. */
2434	pCurLeaf->uEcx = 0; /* Reserved. */
2435	}
2436	pCurLeaf->uEdx = 0; /* Reserved. */
2437	uSubLeaf++;
2438	}
2439
2440	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
2441	* We don't know these and what they mean, so remove them. */
2442	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2443	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
2444
2445	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
2446	* Just pass it thru for now. */
2447
2448	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
2449	* Just pass it thru for now. */
2450
2451	/* Cpuid 0xc0000000: Centaur stuff.
2452	* Harmless, pass it thru. */
2453
2454	/* Cpuid 0xc0000001: Centaur features.
2455	* VIA: EAX - Family, model, stepping.
2456	* EDX - Centaur extended feature flags. Nothing interesting, except may
2457	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
2458	* EBX, ECX - reserved.
2459	* We keep EAX but strips the rest.
2460	*/
2461	uSubLeaf = 0;
2462	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
2463	{
2464	pCurLeaf->uEbx = 0;
2465	pCurLeaf->uEcx = 0;
2466	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
2467	uSubLeaf++;
2468	}
2469
2470	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
2471	* We only have fixed stale values, but should be harmless. */
2472
2473	/* Cpuid 0xc0000003: Reserved.
2474	* We zero this since we don't know what it may have been used for.
2475	*/
2476	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
2477
2478	/* Cpuid 0xc0000004: Centaur Performance Info.
2479	* We only have fixed stale values, but should be harmless. */
2480
2481
2482	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
2483	* We don't know these and what they mean, so remove them. */
2484	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2485	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
2486
2487	return VINF_SUCCESS;
2488	#undef PORTABLE_DISABLE_FEATURE_BIT
2489	#undef PORTABLE_CLEAR_BITS_WHEN
2490	}
2491
2492
2493	/**
2494	* Reads a value in /CPUM/IsaExts/ node.
2495	*
2496	* @returns VBox status code (error message raised).
2497	* @param pVM The cross context VM structure. (For errors.)
2498	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2499	* @param pszValueName The value / extension name.
2500	* @param penmValue Where to return the choice.
2501	* @param enmDefault The default choice.
2502	*/
2503	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
2504	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
2505	{
2506	/*
2507	* Try integer encoding first.
2508	*/
2509	uint64_t uValue;
2510	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
2511	if (RT_SUCCESS(rc))
2512	switch (uValue)
2513	{
2514	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
2515	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
2516	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
2517	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
2518	default:
2519	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
2520	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
2521	pszValueName, uValue);
2522	}
2523	/*
2524	* If missing, use default.
2525	*/
2526	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
2527	*penmValue = enmDefault;
2528	else
2529	{
2530	if (rc == VERR_CFGM_NOT_INTEGER)
2531	{
2532	/*
2533	* Not an integer, try read it as a string.
2534	*/
2535	char szValue[32];
2536	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
2537	if (RT_SUCCESS(rc))
2538	{
2539	RTStrToLower(szValue);
2540	size_t cchValue = strlen(szValue);
2541	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
2542	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
2543	*penmValue = CPUMISAEXTCFG_DISABLED;
2544	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
2545	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
2546	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
2547	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
2548	else if (EQ("portable"))
2549	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
2550	else if (EQ("default") \|\| EQ("def"))
2551	*penmValue = enmDefault;
2552	else
2553	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
2554	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
2555	pszValueName, uValue);
2556	#undef EQ
2557	}
2558	}
2559	if (RT_FAILURE(rc))
2560	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
2561	}
2562	return VINF_SUCCESS;
2563	}
2564
2565
2566	/**
2567	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
2568	*
2569	* @returns VBox status code (error message raised).
2570	* @param pVM The cross context VM structure. (For errors.)
2571	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2572	* @param pszValueName The value / extension name.
2573	* @param penmValue Where to return the choice.
2574	* @param enmDefault The default choice.
2575	* @param fAllowed Allowed choice. Applied both to the result and to
2576	* the default value.
2577	*/
2578	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
2579	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
2580	{
2581	int rc;
2582	if (fAllowed)
2583	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
2584	else
2585	{
2586	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
2587	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
2588	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
2589	*penmValue = CPUMISAEXTCFG_DISABLED;
2590	}
2591	return rc;
2592	}
2593
2594
2595	/**
2596	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
2597	*
2598	* @returns VBox status code (error message raised).
2599	* @param pVM The cross context VM structure. (For errors.)
2600	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2601	* @param pCpumCfg The /CPUM node (can be NULL).
2602	* @param pszValueName The value / extension name.
2603	* @param penmValue Where to return the choice.
2604	* @param enmDefault The default choice.
2605	*/
2606	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
2607	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
2608	{
2609	if (CFGMR3Exists(pCpumCfg, pszValueName))
2610	{
2611	if (!CFGMR3Exists(pIsaExts, pszValueName))
2612	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
2613	else
2614	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
2615	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
2616	pszValueName, pszValueName);
2617
2618	bool fLegacy;
2619	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
2620	if (RT_SUCCESS(rc))
2621	{
2622	*penmValue = fLegacy;
2623	return VINF_SUCCESS;
2624	}
2625	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
2626	}
2627
2628	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
2629	}
2630
2631
2632	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
2633	{
2634	int rc;
2635
2636	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
2637	* When non-zero CPUID features that could cause portability issues will be
2638	* stripped. The higher the value the more features gets stripped. Higher
2639	* values should only be used when older CPUs are involved since it may
2640	* harm performance and maybe also cause problems with specific guests. */
2641	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
2642	AssertLogRelRCReturn(rc, rc);
2643
2644	/** @cfgm{/CPUM/GuestCpuName, string}
2645	* The name of the CPU we're to emulate. The default is the host CPU.
2646	* Note! CPUs other than "host" one is currently unsupported. */
2647	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
2648	AssertLogRelRCReturn(rc, rc);
2649
2650	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
2651	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
2652	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
2653	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
2654	*/
2655	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
2656	AssertLogRelRCReturn(rc, rc);
2657
2658	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
2659	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
2660	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
2661	* 64-bit linux guests which assume the presence of AMD performance counters
2662	* that we do not virtualize.
2663	*/
2664	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
2665	AssertLogRelRCReturn(rc, rc);
2666
2667	/** @cfgm{/CPUM/ForceVme, boolean, false}
2668	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
2669	* By default the flag is passed thru as is from the host CPU, except
2670	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
2671	* guests and DOS boxes in general.
2672	*/
2673	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
2674	AssertLogRelRCReturn(rc, rc);
2675
2676	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
2677	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
2678	* probably going to be a temporary hack, so don't depend on this.
2679	* The 1st byte of the value is the stepping, the 2nd byte value is the model
2680	* number and the 3rd byte value is the family, and the 4th value must be zero.
2681	*/
2682	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
2683	AssertLogRelRCReturn(rc, rc);
2684
2685	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
2686	* The last standard leaf to keep. The actual last value that is stored in EAX
2687	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
2688	* removed. (This works independently of and differently from NT4LeafLimit.)
2689	* The default is usually set to what we're able to reasonably sanitize.
2690	*/
2691	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
2692	AssertLogRelRCReturn(rc, rc);
2693
2694	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
2695	* The last extended leaf to keep. The actual last value that is stored in EAX
2696	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
2697	* leaf are removed. The default is set to what we're able to sanitize.
2698	*/
2699	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
2700	AssertLogRelRCReturn(rc, rc);
2701
2702	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
2703	* The last extended leaf to keep. The actual last value that is stored in EAX
2704	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
2705	* leaf are removed. The default is set to what we're able to sanitize.
2706	*/
2707	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
2708	AssertLogRelRCReturn(rc, rc);
2709
2710	bool fQueryNestedHwvirt = false
2711	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2712	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2713	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON
2714	#endif
2715	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2716	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
2717	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA
2718	#endif
2719	;
2720	if (fQueryNestedHwvirt)
2721	{
2722	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
2723	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
2724	* The default is false, and when enabled requires a 64-bit CPU with support for
2725	* nested-paging and AMD-V or unrestricted guest mode.
2726	*/
2727	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
2728	AssertLogRelRCReturn(rc, rc);
2729	if (pConfig->fNestedHWVirt)
2730	{
2731	/** @todo Think about enabling this later with NEM/KVM. */
2732	if (VM_IS_NEM_ENABLED(pVM))
2733	{
2734	LogRel(("CPUM: Warning! Can't turn on nested VT-x/AMD-V when NEM is used! (later)\n"));
2735	pConfig->fNestedHWVirt = false;
2736	}
2737	else if (!fNestedPagingAndFullGuestExec)
2738	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
2739	"Cannot enable nested VT-x/AMD-V without nested-paging and unrestricted guest execution!\n");
2740	}
2741	}
2742
2743	/*
2744	* Instruction Set Architecture (ISA) Extensions.
2745	*/
2746	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
2747	if (pIsaExts)
2748	{
2749	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
2750	"CMPXCHG16B"
2751	"\|MONITOR"
2752	"\|MWaitExtensions"
2753	"\|SSE4.1"
2754	"\|SSE4.2"
2755	"\|XSAVE"
2756	"\|AVX"
2757	"\|AVX2"
2758	"\|AESNI"
2759	"\|PCLMUL"
2760	"\|POPCNT"
2761	"\|MOVBE"
2762	"\|RDRAND"
2763	"\|RDSEED"
2764	"\|ADX"
2765	"\|CLFLUSHOPT"
2766	"\|SHA"
2767	"\|FSGSBASE"
2768	"\|PCID"
2769	"\|INVPCID"
2770	"\|FlushCmdMsr"
2771	"\|ABM"
2772	"\|SSE4A"
2773	"\|MISALNSSE"
2774	"\|3DNOWPRF"
2775	"\|AXMMX"
2776	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
2777	if (RT_FAILURE(rc))
2778	return rc;
2779	}
2780
2781	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, true}
2782	* Expose CMPXCHG16B to the guest if available. All host CPUs which support
2783	* hardware virtualization have it.
2784	*/
2785	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, true);
2786	AssertLogRelRCReturn(rc, rc);
2787
2788	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
2789	* Expose MONITOR/MWAIT instructions to the guest.
2790	*/
2791	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
2792	AssertLogRelRCReturn(rc, rc);
2793
2794	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
2795	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
2796	* break on interrupt feature (bit 1).
2797	*/
2798	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
2799	AssertLogRelRCReturn(rc, rc);
2800
2801	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
2802	* Expose SSE4.1 to the guest if available.
2803	*/
2804	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
2805	AssertLogRelRCReturn(rc, rc);
2806
2807	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
2808	* Expose SSE4.2 to the guest if available.
2809	*/
2810	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
2811	AssertLogRelRCReturn(rc, rc);
2812
2813	bool const fMayHaveXSave = pVM->cpum.s.HostFeatures.fXSaveRstor
2814	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
2815	&& ( VM_IS_NEM_ENABLED(pVM)
2816	? NEMHCGetFeatures(pVM) & NEM_FEAT_F_XSAVE_XRSTOR
2817	: VM_IS_EXEC_ENGINE_IEM(pVM)
2818	? false /** @todo IEM and XSAVE @bugref{9898} */
2819	: fNestedPagingAndFullGuestExec);
2820	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
2821
2822	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
2823	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
2824	* default is to only expose this to VMs with nested paging and AMD-V or
2825	* unrestricted guest execution mode. Not possible to force this one without
2826	* host support at the moment.
2827	*/
2828	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
2829	fMayHaveXSave /fAllowed/);
2830	AssertLogRelRCReturn(rc, rc);
2831
2832	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
2833	* Expose the AVX instruction set extensions to the guest if available and
2834	* XSAVE is exposed too. For the time being the default is to only expose this
2835	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
2836	*/
2837	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
2838	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
2839	AssertLogRelRCReturn(rc, rc);
2840
2841	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
2842	* Expose the AVX2 instruction set extensions to the guest if available and
2843	* XSAVE is exposed too. For the time being the default is to only expose this
2844	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
2845	*/
2846	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
2847	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
2848	AssertLogRelRCReturn(rc, rc);
2849
2850	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
2851	* Whether to expose the AES instructions to the guest. For the time being the
2852	* default is to only do this for VMs with nested paging and AMD-V or
2853	* unrestricted guest mode.
2854	*/
2855	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
2856	AssertLogRelRCReturn(rc, rc);
2857
2858	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
2859	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
2860	* being the default is to only do this for VMs with nested paging and AMD-V or
2861	* unrestricted guest mode.
2862	*/
2863	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
2864	AssertLogRelRCReturn(rc, rc);
2865
2866	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, true}
2867	* Whether to expose the POPCNT instructions to the guest.
2868	*/
2869	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, CPUMISAEXTCFG_ENABLED_SUPPORTED);
2870	AssertLogRelRCReturn(rc, rc);
2871
2872	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
2873	* Whether to expose the MOVBE instructions to the guest. For the time
2874	* being the default is to only do this for VMs with nested paging and AMD-V or
2875	* unrestricted guest mode.
2876	*/
2877	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
2878	AssertLogRelRCReturn(rc, rc);
2879
2880	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
2881	* Whether to expose the RDRAND instructions to the guest. For the time being
2882	* the default is to only do this for VMs with nested paging and AMD-V or
2883	* unrestricted guest mode.
2884	*/
2885	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
2886	AssertLogRelRCReturn(rc, rc);
2887
2888	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
2889	* Whether to expose the RDSEED instructions to the guest. For the time being
2890	* the default is to only do this for VMs with nested paging and AMD-V or
2891	* unrestricted guest mode.
2892	*/
2893	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
2894	AssertLogRelRCReturn(rc, rc);
2895
2896	/** @cfgm{/CPUM/IsaExts/ADX, isaextcfg, depends}
2897	* Whether to expose the ADX instructions to the guest. For the time being
2898	* the default is to only do this for VMs with nested paging and AMD-V or
2899	* unrestricted guest mode.
2900	*/
2901	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ADX", &pConfig->enmAdx, fNestedPagingAndFullGuestExec);
2902	AssertLogRelRCReturn(rc, rc);
2903
2904	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
2905	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
2906	* being the default is to only do this for VMs with nested paging and AMD-V or
2907	* unrestricted guest mode.
2908	*/
2909	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
2910	AssertLogRelRCReturn(rc, rc);
2911
2912	/** @cfgm{/CPUM/IsaExts/SHA, isaextcfg, depends}
2913	* Whether to expose the SHA instructions to the guest. For the time being
2914	* the default is to only do this for VMs with nested paging and AMD-V or
2915	* unrestricted guest mode.
2916	*/
2917	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SHA", &pConfig->enmSha, fNestedPagingAndFullGuestExec);
2918	AssertLogRelRCReturn(rc, rc);
2919
2920	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
2921	* Whether to expose the read/write FSGSBASE instructions to the guest.
2922	*/
2923	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
2924	AssertLogRelRCReturn(rc, rc);
2925
2926	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
2927	* Whether to expose the PCID feature to the guest.
2928	*/
2929	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
2930	AssertLogRelRCReturn(rc, rc);
2931
2932	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
2933	* Whether to expose the INVPCID instruction to the guest.
2934	*/
2935	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
2936	AssertLogRelRCReturn(rc, rc);
2937
2938	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
2939	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
2940	*/
2941	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
2942	AssertLogRelRCReturn(rc, rc);
2943
2944	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
2945	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
2946	* the guest. Requires FlushCmdMsr to be present too.
2947	*/
2948	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
2949	AssertLogRelRCReturn(rc, rc);
2950
2951	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
2952	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
2953	*/
2954	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
2955	AssertLogRelRCReturn(rc, rc);
2956
2957
2958	/* AMD: */
2959
2960	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, true}
2961	* Whether to expose the AMD ABM instructions to the guest.
2962	*/
2963	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, CPUMISAEXTCFG_ENABLED_SUPPORTED);
2964	AssertLogRelRCReturn(rc, rc);
2965
2966	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
2967	* Whether to expose the AMD SSE4A instructions to the guest. For the time
2968	* being the default is to only do this for VMs with nested paging and AMD-V or
2969	* unrestricted guest mode.
2970	*/
2971	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
2972	AssertLogRelRCReturn(rc, rc);
2973
2974	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
2975	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
2976	* the time being the default is to only do this for VMs with nested paging and
2977	* AMD-V or unrestricted guest mode.
2978	*/
2979	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
2980	AssertLogRelRCReturn(rc, rc);
2981
2982	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
2983	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
2984	* For the time being the default is to only do this for VMs with nested paging
2985	* and AMD-V or unrestricted guest mode.
2986	*/
2987	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
2988	AssertLogRelRCReturn(rc, rc);
2989
2990	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
2991	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
2992	* the default is to only do this for VMs with nested paging and AMD-V or
2993	* unrestricted guest mode.
2994	*/
2995	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
2996	AssertLogRelRCReturn(rc, rc);
2997
2998	return VINF_SUCCESS;
2999	}
3000
3001
3002	/**
3003	* Initializes the emulated CPU's CPUID & MSR information.
3004	*
3005	* @returns VBox status code.
3006	* @param pVM The cross context VM structure.
3007	* @param pHostMsrs Pointer to the host MSRs.
3008	*/
3009	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
3010	{
3011	Assert(pHostMsrs);
3012
3013	PCPUM pCpum = &pVM->cpum.s;
3014	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
3015
3016	/*
3017	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
3018	* on construction and manage everything from here on.
3019	*/
3020	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3021	{
3022	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3023	pVCpu->cpum.s.fCpuIdApicFeatureVisible = true;
3024	}
3025
3026	/*
3027	* Read the configuration.
3028	*/
3029	CPUMCPUIDCONFIG Config;
3030	RT_ZERO(Config);
3031
3032	bool const fNestedPagingAndFullGuestExec = VM_IS_NEM_ENABLED(pVM)
3033	\|\| HMAreNestedPagingAndFullGuestExecEnabled(pVM);
3034	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, fNestedPagingAndFullGuestExec);
3035	AssertRCReturn(rc, rc);
3036
3037	/*
3038	* Get the guest CPU data from the database and/or the host.
3039	*
3040	* The CPUID and MSRs are currently living on the regular heap to avoid
3041	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
3042	* API for the hyper heap). This means special cleanup considerations.
3043	*/
3044	/** @todo The hyper heap will be removed ASAP, so the final destination is
3045	* now a fixed sized arrays in the VM structure. Maybe we can simplify
3046	* this allocation fun a little now? Or maybe it's too convenient for
3047	* the CPU reporter code... No time to figure that out now. */
3048	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
3049	if (RT_FAILURE(rc))
3050	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
3051	? VMSetError(pVM, rc, RT_SRC_POS,
3052	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
3053	: rc;
3054
3055	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
3056	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
3057	{
3058	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
3059	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
3060	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
3061	}
3062	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
3063	#else
3064	LogRel(("CPUM: MXCSR_MASK=%#x\n", pCpum->GuestInfo.fMxCsrMask));
3065	#endif
3066
3067	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
3068	* Overrides the guest MSRs.
3069	*/
3070	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
3071
3072	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
3073	* Overrides the CPUID leaf values (from the host CPU usually) used for
3074	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
3075	* values when moving a VM to a different machine. Another use is restricting
3076	* (or extending) the feature set exposed to the guest. */
3077	if (RT_SUCCESS(rc))
3078	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
3079
3080	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
3081	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
3082	"Found unsupported configuration node '/CPUM/CPUID/'. "
3083	"Please use IMachine::setCPUIDLeaf() instead.");
3084
3085	CPUMMSRS GuestMsrs;
3086	RT_ZERO(GuestMsrs);
3087
3088	/*
3089	* Pre-explode the CPUID info.
3090	*/
3091	if (RT_SUCCESS(rc))
3092	rc = cpumCpuIdExplodeFeaturesX86(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
3093	&pCpum->GuestFeatures);
3094
3095	/*
3096	* Sanitize the cpuid information passed on to the guest.
3097	*/
3098	if (RT_SUCCESS(rc))
3099	{
3100	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
3101	if (RT_SUCCESS(rc))
3102	{
3103	cpumR3CpuIdLimitLeaves(pCpum, &Config);
3104	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
3105	}
3106	}
3107
3108	/*
3109	* Setup MSRs introduced in microcode updates or that are otherwise not in
3110	* the CPU profile, but are advertised in the CPUID info we just sanitized.
3111	*/
3112	if (RT_SUCCESS(rc))
3113	rc = cpumR3MsrReconcileWithCpuId(pVM);
3114	/*
3115	* MSR fudging.
3116	*/
3117	if (RT_SUCCESS(rc))
3118	{
3119	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
3120	* Fudges some common MSRs if not present in the selected CPU database entry.
3121	* This is for trying to keep VMs running when moved between different hosts
3122	* and different CPU vendors. */
3123	bool fEnable;
3124	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
3125	if (RT_SUCCESS(rc) && fEnable)
3126	{
3127	rc = cpumR3MsrApplyFudge(pVM);
3128	AssertLogRelRC(rc);
3129	}
3130	}
3131	if (RT_SUCCESS(rc))
3132	{
3133	/*
3134	* Move the MSR and CPUID arrays over to the static VM structure allocations
3135	* and explode guest CPU features again.
3136	*/
3137	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
3138	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
3139	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
3140	RTMemFree(pvFree);
3141
3142	AssertFatalMsg(pCpum->GuestInfo.cMsrRanges <= RT_ELEMENTS(pCpum->GuestInfo.aMsrRanges),
3143	("%u\n", pCpum->GuestInfo.cMsrRanges));
3144	memcpy(pCpum->GuestInfo.aMsrRanges, pCpum->GuestInfo.paMsrRangesR3,
3145	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges);
3146	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3147	pCpum->GuestInfo.paMsrRangesR3 = pCpum->GuestInfo.aMsrRanges;
3148
3149	AssertLogRelRCReturn(rc, rc);
3150
3151	/*
3152	* Some more configuration that we're applying at the end of everything
3153	* via the CPUMR3SetGuestCpuIdFeature API.
3154	*/
3155
3156	/* Check if 64-bit guest supported was enabled. */
3157	bool fEnable64bit;
3158	rc = CFGMR3QueryBoolDef(pCpumCfg, "Enable64bit", &fEnable64bit, false);
3159	AssertRCReturn(rc, rc);
3160	if (fEnable64bit)
3161	{
3162	/* In case of a CPU upgrade: */
3163	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
3164	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* (Long mode only on Intel CPUs.) */
3165	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3166	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
3167	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3168
3169	/* The actual feature: */
3170	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
3171	}
3172
3173	/* Check if PAE was explicitely enabled by the user. */
3174	bool fEnable;
3175	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, fEnable64bit);
3176	AssertRCReturn(rc, rc);
3177	if (fEnable && !pVM->cpum.s.GuestFeatures.fPae)
3178	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3179
3180	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
3181	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, fEnable64bit);
3182	AssertRCReturn(rc, rc);
3183	if (fEnable && !pVM->cpum.s.GuestFeatures.fNoExecute)
3184	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3185
3186	/* Check if speculation control is enabled. */
3187	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
3188	AssertRCReturn(rc, rc);
3189	if (fEnable)
3190	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
3191	else
3192	{
3193	/*
3194	* Set the "SSBD-not-needed" flag to work around a bug in some Linux kernels when the VIRT_SPEC_CTL
3195	* feature is not exposed on AMD CPUs and there is only 1 vCPU configured.
3196	* This was observed with kernel "4.15.0-29-generic #31~16.04.1-Ubuntu" but more versions are likely affected.
3197	*
3198	* The kernel doesn't initialize a lock and causes a NULL pointer exception later on when configuring SSBD:
3199	* EIP: _raw_spin_lock+0x14/0x30
3200	* EFLAGS: 00010046 CPU: 0
3201	* EAX: 00000000 EBX: 00000001 ECX: 00000004 EDX: 00000000
3202	* ESI: 00000000 EDI: 00000000 EBP: ee023f1c ESP: ee023f18
3203	* DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
3204	* CR0: 80050033 CR2: 00000004 CR3: 3671c180 CR4: 000006f0
3205	* Call Trace:
3206	* speculative_store_bypass_update+0x8e/0x180
3207	* ssb_prctl_set+0xc0/0xe0
3208	* arch_seccomp_spec_mitigate+0x1d/0x20
3209	* do_seccomp+0x3cb/0x610
3210	* SyS_seccomp+0x16/0x20
3211	* do_fast_syscall_32+0x7f/0x1d0
3212	* entry_SYSENTER_32+0x4e/0x7c
3213	*
3214	* The lock would've been initialized in process.c:speculative_store_bypass_ht_init() called from two places in smpboot.c.
3215	* First when a secondary CPU is started and second in native_smp_prepare_cpus() which is not called in a single vCPU environment.
3216	*
3217	* As spectre control features are completely disabled anyway when we arrived here there is no harm done in informing the
3218	* guest to not even try.
3219	*/
3220	if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3221	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3222	{
3223	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x80000008), 0);
3224	if (pLeaf)
3225	{
3226	pLeaf->uEbx \|= X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED;
3227	LogRel(("CPUM: Set SSBD not required flag for AMD to work around some buggy Linux kernels!\n"));
3228	}
3229	}
3230	}
3231
3232	/*
3233	* Finally, initialize guest VMX MSRs.
3234	*
3235	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
3236	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
3237	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
3238	*/
3239	/** @todo r=bird: given that long mode never used to be enabled before the
3240	* VMINITCOMPLETED_RING0 state, and we're a lot earlier here in ring-3
3241	* init, the above comment cannot be entirely accurate. */
3242	if (pVM->cpum.s.GuestFeatures.fVmx)
3243	{
3244	Assert(Config.fNestedHWVirt);
3245	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, pCpumCfg, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
3246
3247	/* Copy MSRs to all VCPUs */
3248	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
3249	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3250	{
3251	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3252	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
3253	}
3254	}
3255
3256	return VINF_SUCCESS;
3257	}
3258
3259	/*
3260	* Failed before switching to hyper heap.
3261	*/
3262	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
3263	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
3264	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3265	pCpum->GuestInfo.paMsrRangesR3 = NULL;
3266	return rc;
3267	}
3268
3269
3270	/**
3271	* Sets a CPUID feature bit during VM initialization.
3272	*
3273	* Since the CPUID feature bits are generally related to CPU features, other
3274	* CPUM configuration like MSRs can also be modified by calls to this API.
3275	*
3276	* @param pVM The cross context VM structure.
3277	* @param enmFeature The feature to set.
3278	*/
3279	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
3280	{
3281	PCPUMCPUIDLEAF pLeaf;
3282	PCPUMMSRRANGE pMsrRange;
3283
3284	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
3285	# define CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) \
3286	if (!pVM->cpum.s.HostFeatures. a_fFeature) \
3287	{ \
3288	LogRel(("CPUM: WARNING! Can't turn on " a_szFeature " when the host doesn't support it!\n")); \
3289	return; \
3290	} else do { } while (0)
3291	#else
3292	# define CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) do { } while (0)
3293	#endif
3294
3295	#define GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) \
3296	do \
3297	{ \
3298	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001)); \
3299	if (!pLeaf) \
3300	{ \
3301	LogRel(("CPUM: WARNING! Can't turn on " a_szFeature " when no 0x80000001 CPUID leaf!\n")); \
3302	return; \
3303	} \
3304	CHECK_X86_HOST_FEATURE_RET(a_fFeature,a_szFeature); \
3305	} while (0)
3306
3307	switch (enmFeature)
3308	{
3309	/*
3310	* Set the APIC bit in both feature masks.
3311	*/
3312	case CPUMCPUIDFEATURE_APIC:
3313	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3314	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3315	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
3316
3317	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3318	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3319	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
3320
3321	pVM->cpum.s.GuestFeatures.fApic = 1;
3322
3323	/* Make sure we've got the APICBASE MSR present. */
3324	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
3325	if (!pMsrRange)
3326	{
3327	static CPUMMSRRANGE const s_ApicBase =
3328	{
3329	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
3330	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
3331	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3332	/.szName = / "IA32_APIC_BASE"
3333	};
3334	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
3335	AssertLogRelRC(rc);
3336	}
3337
3338	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
3339	break;
3340
3341	/*
3342	* Set the x2APIC bit in the standard feature mask.
3343	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
3344	*/
3345	case CPUMCPUIDFEATURE_X2APIC:
3346	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3347	if (pLeaf)
3348	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
3349	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
3350
3351	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
3352	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
3353	if (pMsrRange)
3354	{
3355	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
3356	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
3357	}
3358
3359	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
3360	break;
3361
3362	/*
3363	* Set the sysenter/sysexit bit in the standard feature mask.
3364	* Assumes the caller knows what it's doing! (host must support these)
3365	*/
3366	case CPUMCPUIDFEATURE_SEP:
3367	CHECK_X86_HOST_FEATURE_RET(fSysEnter, "SEP");
3368	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3369	if (pLeaf)
3370	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
3371	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
3372	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
3373	break;
3374
3375	/*
3376	* Set the syscall/sysret bit in the extended feature mask.
3377	* Assumes the caller knows what it's doing! (host must support these)
3378	*/
3379	case CPUMCPUIDFEATURE_SYSCALL:
3380	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fSysCall, "SYSCALL/SYSRET");
3381
3382	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
3383	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
3384	pVM->cpum.s.GuestFeatures.fSysCall = 1;
3385	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
3386	break;
3387
3388	/*
3389	* Set the PAE bit in both feature masks.
3390	* Assumes the caller knows what it's doing! (host must support these)
3391	*/
3392	case CPUMCPUIDFEATURE_PAE:
3393	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3394	if (pLeaf)
3395	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
3396
3397	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3398	if ( pLeaf
3399	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3400	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3401	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
3402
3403	pVM->cpum.s.GuestFeatures.fPae = 1;
3404	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
3405	break;
3406
3407	/*
3408	* Set the LONG MODE bit in the extended feature mask.
3409	* Assumes the caller knows what it's doing! (host must support these)
3410	*/
3411	case CPUMCPUIDFEATURE_LONG_MODE:
3412	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fLongMode, "LONG MODE");
3413
3414	/* Valid for both Intel and AMD. */
3415	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
3416	pVM->cpum.s.GuestFeatures.fLongMode = 1;
3417	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
3418	if (pVM->cpum.s.GuestFeatures.fVmx)
3419	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3420	{
3421	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3422	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic &= ~VMX_BASIC_PHYSADDR_WIDTH_32BIT;
3423	}
3424	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
3425	break;
3426
3427	/*
3428	* Set the NX/XD bit in the extended feature mask.
3429	* Assumes the caller knows what it's doing! (host must support these)
3430	*/
3431	case CPUMCPUIDFEATURE_NX:
3432	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fNoExecute, "NX/XD");
3433
3434	/* Valid for both Intel and AMD. */
3435	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
3436	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
3437	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
3438	break;
3439
3440
3441	/*
3442	* Set the LAHF/SAHF support in 64-bit mode.
3443	* Assumes the caller knows what it's doing! (host must support this)
3444	*/
3445	case CPUMCPUIDFEATURE_LAHF:
3446	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fLahfSahf, "LAHF/SAHF");
3447
3448	/* Valid for both Intel and AMD. */
3449	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
3450	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
3451	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
3452	break;
3453
3454	/*
3455	* Set the RDTSCP support bit.
3456	* Assumes the caller knows what it's doing! (host must support this)
3457	*/
3458	case CPUMCPUIDFEATURE_RDTSCP:
3459	if (pVM->cpum.s.u8PortableCpuIdLevel > 0)
3460	return;
3461	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fRdTscP, "RDTSCP");
3462	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3463
3464	/* Valid for both Intel and AMD. */
3465	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
3466	pVM->cpum.s.HostFeatures.fRdTscP = 1;
3467	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
3468	break;
3469
3470	/*
3471	* Set the Hypervisor Present bit in the standard feature mask.
3472	*/
3473	case CPUMCPUIDFEATURE_HVP:
3474	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3475	if (pLeaf)
3476	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
3477	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
3478	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
3479	break;
3480
3481	/*
3482	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
3483	* on Intel CPUs, and different on AMDs.
3484	*/
3485	case CPUMCPUIDFEATURE_SPEC_CTRL:
3486	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3487	{
3488	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
3489	if ( !pLeaf
3490	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
3491	{
3492	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
3493	return;
3494	}
3495
3496	/* The feature can be enabled. Let's see what we can actually do. */
3497	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
3498
3499	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
3500	if (pVM->cpum.s.HostFeatures.fIbrs)
3501	{
3502	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
3503	pVM->cpum.s.GuestFeatures.fIbrs = 1;
3504	if (pVM->cpum.s.HostFeatures.fStibp)
3505	{
3506	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
3507	pVM->cpum.s.GuestFeatures.fStibp = 1;
3508	}
3509
3510	/* Make sure we have the speculation control MSR... */
3511	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
3512	if (!pMsrRange)
3513	{
3514	static CPUMMSRRANGE const s_SpecCtrl =
3515	{
3516	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
3517	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
3518	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3519	/.szName = / "IA32_SPEC_CTRL"
3520	};
3521	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
3522	AssertLogRelRC(rc);
3523	}
3524
3525	/* ... and the predictor command MSR. */
3526	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
3527	if (!pMsrRange)
3528	{
3529	/** @todo incorrect fWrGpMask. */
3530	static CPUMMSRRANGE const s_SpecCtrl =
3531	{
3532	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
3533	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
3534	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3535	/.szName = / "IA32_PRED_CMD"
3536	};
3537	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
3538	AssertLogRelRC(rc);
3539	}
3540
3541	}
3542
3543	if (pVM->cpum.s.HostFeatures.fArchCap)
3544	{
3545	/* Install the architectural capabilities MSR. */
3546	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
3547	if (!pMsrRange)
3548	{
3549	static CPUMMSRRANGE const s_ArchCaps =
3550	{
3551	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
3552	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
3553	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
3554	/.szName = / "IA32_ARCH_CAPABILITIES"
3555	};
3556	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
3557	AssertLogRelRC(rc);
3558	}
3559
3560	/* Advertise IBRS_ALL if present at this point... */
3561	if (pVM->cpum.s.HostFeatures.fArchCap & MSR_IA32_ARCH_CAP_F_IBRS_ALL)
3562	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps \|= MSR_IA32_ARCH_CAP_F_IBRS_ALL);
3563	}
3564
3565	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
3566	}
3567	else if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3568	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3569	{
3570	/* The precise details of AMD's implementation are not yet clear. */
3571	}
3572	break;
3573
3574	default:
3575	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
3576	break;
3577	}
3578
3579	/** @todo can probably kill this as this API is now init time only... */
3580	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3581	{
3582	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3583	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
3584	}
3585
3586	#undef GET_8000_0001_CHECK_X86_HOST_FEATURE_RET
3587	#undef CHECK_X86_HOST_FEATURE_RET
3588	}
3589
3590
3591	/**
3592	* Queries a CPUID feature bit.
3593	*
3594	* @returns boolean for feature presence
3595	* @param pVM The cross context VM structure.
3596	* @param enmFeature The feature to query.
3597	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
3598	*/
3599	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
3600	{
3601	switch (enmFeature)
3602	{
3603	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
3604	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
3605	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
3606	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
3607	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
3608	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
3609	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
3610	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
3611	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
3612	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
3613	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
3614	case CPUMCPUIDFEATURE_INVALID:
3615	case CPUMCPUIDFEATURE_32BIT_HACK:
3616	break;
3617	}
3618	AssertFailed();
3619	return false;
3620	}
3621
3622
3623	/**
3624	* Clears a CPUID feature bit.
3625	*
3626	* @param pVM The cross context VM structure.
3627	* @param enmFeature The feature to clear.
3628	*
3629	* @deprecated Probably better to default the feature to disabled and only allow
3630	* setting (enabling) it during construction.
3631	*/
3632	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
3633	{
3634	PCPUMCPUIDLEAF pLeaf;
3635	switch (enmFeature)
3636	{
3637	case CPUMCPUIDFEATURE_APIC:
3638	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
3639	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3640	if (pLeaf)
3641	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
3642
3643	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3644	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3645	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
3646
3647	pVM->cpum.s.GuestFeatures.fApic = 0;
3648	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
3649	break;
3650
3651	case CPUMCPUIDFEATURE_X2APIC:
3652	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
3653	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3654	if (pLeaf)
3655	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
3656	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
3657	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
3658	break;
3659
3660	#if 0
3661	case CPUMCPUIDFEATURE_PAE:
3662	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3663	if (pLeaf)
3664	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
3665
3666	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3667	if ( pLeaf
3668	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3669	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3670	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
3671
3672	pVM->cpum.s.GuestFeatures.fPae = 0;
3673	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
3674	break;
3675
3676	case CPUMCPUIDFEATURE_LONG_MODE:
3677	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3678	if (pLeaf)
3679	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
3680	pVM->cpum.s.GuestFeatures.fLongMode = 0;
3681	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
3682	if (pVM->cpum.s.GuestFeatures.fVmx)
3683	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3684	{
3685	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3686	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic \|= VMX_BASIC_PHYSADDR_WIDTH_32BIT;
3687	}
3688	break;
3689
3690	case CPUMCPUIDFEATURE_LAHF:
3691	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3692	if (pLeaf)
3693	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
3694	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
3695	break;
3696	#endif
3697	case CPUMCPUIDFEATURE_RDTSCP:
3698	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3699	if (pLeaf)
3700	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
3701	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
3702	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
3703	break;
3704
3705	#if 0
3706	case CPUMCPUIDFEATURE_HVP:
3707	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3708	if (pLeaf)
3709	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
3710	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
3711	break;
3712
3713	case CPUMCPUIDFEATURE_SPEC_CTRL:
3714	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
3715	if (pLeaf)
3716	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
3717	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL);
3718	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
3719	break;
3720	#endif
3721	default:
3722	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
3723	break;
3724	}
3725
3726	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3727	{
3728	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3729	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
3730	}
3731	}
3732
3733
3734	/**
3735	* Do some final polishing after all calls to CPUMR3SetGuestCpuIdFeature and
3736	* CPUMR3ClearGuestCpuIdFeature are (probably) done.
3737	*
3738	* @param pVM The cross context VM structure.
3739	*/
3740	void cpumR3CpuIdRing3InitDone(PVM pVM)
3741	{
3742	/*
3743	* Do not advertise NX w/o PAE, seems to confuse windows 7 (black screen very
3744	* early in real mode).
3745	*/
3746	PCPUMCPUIDLEAF pStdLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3747	PCPUMCPUIDLEAF pExtLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3748	if (pStdLeaf && pExtLeaf)
3749	{
3750	if ( !(pStdLeaf->uEdx & X86_CPUID_FEATURE_EDX_PAE)
3751	&& (pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX))
3752	pExtLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_NX;
3753	}
3754	}
3755
3756
3757	/*
3758	*
3759	*
3760	* Saved state related code.
3761	* Saved state related code.
3762	* Saved state related code.
3763	*
3764	*
3765	*/
3766
3767	/**
3768	* Called both in pass 0 and the final pass.
3769	*
3770	* @param pVM The cross context VM structure.
3771	* @param pSSM The saved state handle.
3772	*/
3773	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
3774	{
3775	/*
3776	* Save all the CPU ID leaves.
3777	*/
3778	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
3779	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
3780	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
3781	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
3782
3783	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
3784
3785	/*
3786	* Save a good portion of the raw CPU IDs as well as they may come in
3787	* handy when validating features for raw mode.
3788	*/
3789	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
3790	CPUMCPUID aRawStd[16];
3791	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
3792	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
3793	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
3794	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
3795
3796	CPUMCPUID aRawExt[32];
3797	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
3798	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
3799	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
3800	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
3801
3802	#else
3803	/* Two zero counts on non-x86 hosts. */
3804	SSMR3PutU32(pSSM, 0);
3805	SSMR3PutU32(pSSM, 0);
3806	#endif
3807	}
3808
3809
3810	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
3811	{
3812	uint32_t cCpuIds;
3813	int rc = SSMR3GetU32(pSSM, &cCpuIds);
3814	if (RT_SUCCESS(rc))
3815	{
3816	if (cCpuIds < 64)
3817	{
3818	for (uint32_t i = 0; i < cCpuIds; i++)
3819	{
3820	CPUMCPUID CpuId;
3821	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
3822	if (RT_FAILURE(rc))
3823	break;
3824
3825	CPUMCPUIDLEAF NewLeaf;
3826	NewLeaf.uLeaf = uBase + i;
3827	NewLeaf.uSubLeaf = 0;
3828	NewLeaf.fSubLeafMask = 0;
3829	NewLeaf.uEax = CpuId.uEax;
3830	NewLeaf.uEbx = CpuId.uEbx;
3831	NewLeaf.uEcx = CpuId.uEcx;
3832	NewLeaf.uEdx = CpuId.uEdx;
3833	NewLeaf.fFlags = 0;
3834	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
3835	}
3836	}
3837	else
3838	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3839	}
3840	if (RT_FAILURE(rc))
3841	{
3842	RTMemFree(*ppaLeaves);
3843	*ppaLeaves = NULL;
3844	*pcLeaves = 0;
3845	}
3846	return rc;
3847	}
3848
3849
3850	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
3851	{
3852	*ppaLeaves = NULL;
3853	*pcLeaves = 0;
3854
3855	int rc;
3856	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
3857	{
3858	/*
3859	* The new format. Starts by declaring the leave size and count.
3860	*/
3861	uint32_t cbLeaf;
3862	SSMR3GetU32(pSSM, &cbLeaf);
3863	uint32_t cLeaves;
3864	rc = SSMR3GetU32(pSSM, &cLeaves);
3865	if (RT_SUCCESS(rc))
3866	{
3867	if (cbLeaf == sizeof(**ppaLeaves))
3868	{
3869	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
3870	{
3871	/*
3872	* Load the leaves one by one.
3873	*
3874	* The uPrev stuff is a kludge for working around a week worth of bad saved
3875	* states during the CPUID revamp in March 2015. We saved too many leaves
3876	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
3877	* garbage entires at the end of the array when restoring. We also had
3878	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
3879	* this kludge doesn't deal correctly with that, but who cares...
3880	*/
3881	uint32_t uPrev = 0;
3882	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
3883	{
3884	CPUMCPUIDLEAF Leaf;
3885	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
3886	if (RT_SUCCESS(rc))
3887	{
3888	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
3889	\|\| Leaf.uLeaf >= uPrev)
3890	{
3891	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3892	uPrev = Leaf.uLeaf;
3893	}
3894	else
3895	uPrev = UINT32_MAX;
3896	}
3897	}
3898	}
3899	else
3900	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
3901	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
3902	}
3903	else
3904	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
3905	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
3906	}
3907	}
3908	else
3909	{
3910	/*
3911	* The old format with its three inflexible arrays.
3912	*/
3913	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
3914	if (RT_SUCCESS(rc))
3915	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
3916	if (RT_SUCCESS(rc))
3917	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
3918	if (RT_SUCCESS(rc))
3919	{
3920	/*
3921	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
3922	*/
3923	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(ppaLeaves, pcLeaves, 0, 0);
3924	if ( pLeaf
3925	&& RTX86IsIntelCpu(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
3926	{
3927	CPUMCPUIDLEAF Leaf;
3928	Leaf.uLeaf = 4;
3929	Leaf.fSubLeafMask = UINT32_MAX;
3930	Leaf.uSubLeaf = 0;
3931	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
3932	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
3933	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
3934	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
3935	\| UINT32_C(63); /* system coherency line size - 1 */
3936	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
3937	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
3938	\| (UINT32_C(1) << 5) /* cache level */
3939	\| UINT32_C(1); /* cache type (data) */
3940	Leaf.fFlags = 0;
3941	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3942	if (RT_SUCCESS(rc))
3943	{
3944	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
3945	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3946	}
3947	if (RT_SUCCESS(rc))
3948	{
3949	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
3950	Leaf.uEcx = 4095; /* sets - 1 */
3951	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
3952	Leaf.uEbx \|= UINT32_C(23) << 22;
3953	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
3954	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
3955	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
3956	Leaf.uEax \|= UINT32_C(2) << 5;
3957	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3958	}
3959	}
3960	}
3961	}
3962	return rc;
3963	}
3964
3965
3966	/**
3967	* Loads the CPU ID leaves saved by pass 0, inner worker.
3968	*
3969	* @returns VBox status code.
3970	* @param pVM The cross context VM structure.
3971	* @param pSSM The saved state handle.
3972	* @param uVersion The format version.
3973	* @param paLeaves Guest CPUID leaves loaded from the state.
3974	* @param cLeaves The number of leaves in @a paLeaves.
3975	* @param pMsrs The guest MSRs.
3976	*/
3977	static int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
3978	{
3979	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
3980	#if !defined(RT_ARCH_AMD64) && !defined(RT_ARCH_X86)
3981	AssertMsgFailed(("Port me!"));
3982	#endif
3983
3984	/*
3985	* Continue loading the state into stack buffers.
3986	*/
3987	CPUMCPUID GuestDefCpuId;
3988	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
3989	AssertRCReturn(rc, rc);
3990
3991	CPUMCPUID aRawStd[16];
3992	uint32_t cRawStd;
3993	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
3994	if (cRawStd > RT_ELEMENTS(aRawStd))
3995	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3996	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
3997	AssertRCReturn(rc, rc);
3998	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
3999	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4000	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4001	#else
4002	RT_ZERO(aRawStd[i]);
4003	#endif
4004
4005	CPUMCPUID aRawExt[32];
4006	uint32_t cRawExt;
4007	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
4008	if (cRawExt > RT_ELEMENTS(aRawExt))
4009	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4010	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
4011	AssertRCReturn(rc, rc);
4012	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
4013	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4014	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4015	#else
4016	RT_ZERO(aRawExt[i]);
4017	#endif
4018
4019	/*
4020	* Get the raw CPU IDs for the current host.
4021	*/
4022	CPUMCPUID aHostRawStd[16];
4023	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4024	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
4025	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
4026	#else
4027	RT_ZERO(aHostRawStd);
4028	#endif
4029
4030	CPUMCPUID aHostRawExt[32];
4031	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4032	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
4033	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
4034	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4035	#else
4036	RT_ZERO(aHostRawExt);
4037	#endif
4038
4039	/*
4040	* Get the host and guest overrides so we don't reject the state because
4041	* some feature was enabled thru these interfaces.
4042	* Note! We currently only need the feature leaves, so skip rest.
4043	*/
4044	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4045	CPUMCPUID aHostOverrideStd[2];
4046	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4047	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4048
4049	CPUMCPUID aHostOverrideExt[2];
4050	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4051	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4052
4053	/*
4054	* This can be skipped.
4055	*/
4056	bool fStrictCpuIdChecks;
4057	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
4058
4059	/*
4060	* Define a bunch of macros for simplifying the santizing/checking code below.
4061	*/
4062	/* Generic expression + failure message. */
4063	#define CPUID_CHECK_RET(expr, fmt) \
4064	do { \
4065	if (!(expr)) \
4066	{ \
4067	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
4068	if (fStrictCpuIdChecks) \
4069	{ \
4070	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4071	RTStrFree(pszMsg); \
4072	return rcCpuid; \
4073	} \
4074	LogRel(("CPUM: %s\n", pszMsg)); \
4075	RTStrFree(pszMsg); \
4076	} \
4077	} while (0)
4078	#define CPUID_CHECK_WRN(expr, fmt) \
4079	do { \
4080	if (!(expr)) \
4081	LogRel(fmt); \
4082	} while (0)
4083
4084	/* For comparing two values and bitch if they differs. */
4085	#define CPUID_CHECK2_RET(what, host, saved) \
4086	do { \
4087	if ((host) != (saved)) \
4088	{ \
4089	if (fStrictCpuIdChecks) \
4090	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4091	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
4092	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4093	} \
4094	} while (0)
4095	#define CPUID_CHECK2_WRN(what, host, saved) \
4096	do { \
4097	if ((host) != (saved)) \
4098	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4099	} while (0)
4100
4101	/* For checking raw cpu features (raw mode). */
4102	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
4103	do { \
4104	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4105	{ \
4106	if (fStrictCpuIdChecks) \
4107	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4108	N_(#bit " mismatch: host=%d saved=%d"), \
4109	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
4110	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4111	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4112	} \
4113	} while (0)
4114	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
4115	do { \
4116	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4117	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4118	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4119	} while (0)
4120	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
4121
4122	/* For checking guest features. */
4123	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
4124	do { \
4125	if ( (aGuestCpuId##set [1].reg & bit) \
4126	&& !(aHostRaw##set [1].reg & bit) \
4127	&& !(aHostOverride##set [1].reg & bit) \
4128	) \
4129	{ \
4130	if (fStrictCpuIdChecks) \
4131	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4132	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4133	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4134	} \
4135	} while (0)
4136	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
4137	do { \
4138	if ( (aGuestCpuId##set [1].reg & bit) \
4139	&& !(aHostRaw##set [1].reg & bit) \
4140	&& !(aHostOverride##set [1].reg & bit) \
4141	) \
4142	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4143	} while (0)
4144	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
4145	do { \
4146	if ( (aGuestCpuId##set [1].reg & bit) \
4147	&& !(aHostRaw##set [1].reg & bit) \
4148	&& !(aHostOverride##set [1].reg & bit) \
4149	) \
4150	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4151	} while (0)
4152	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
4153
4154	/* For checking guest features if AMD guest CPU. */
4155	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
4156	do { \
4157	if ( (aGuestCpuId##set [1].reg & bit) \
4158	&& fGuestAmd \
4159	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4160	&& !(aHostOverride##set [1].reg & bit) \
4161	) \
4162	{ \
4163	if (fStrictCpuIdChecks) \
4164	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4165	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4166	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4167	} \
4168	} while (0)
4169	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
4170	do { \
4171	if ( (aGuestCpuId##set [1].reg & bit) \
4172	&& fGuestAmd \
4173	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4174	&& !(aHostOverride##set [1].reg & bit) \
4175	) \
4176	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4177	} while (0)
4178	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
4179	do { \
4180	if ( (aGuestCpuId##set [1].reg & bit) \
4181	&& fGuestAmd \
4182	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4183	&& !(aHostOverride##set [1].reg & bit) \
4184	) \
4185	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4186	} while (0)
4187	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
4188
4189	/* For checking AMD features which have a corresponding bit in the standard
4190	range. (Intel defines very few bits in the extended feature sets.) */
4191	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
4192	do { \
4193	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4194	&& !(fHostAmd \
4195	? aHostRawExt[1].reg & (ExtBit) \
4196	: aHostRawStd[1].reg & (StdBit)) \
4197	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4198	) \
4199	{ \
4200	if (fStrictCpuIdChecks) \
4201	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4202	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
4203	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4204	} \
4205	} while (0)
4206	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
4207	do { \
4208	if ( (aGuestCpuId[1].reg & (ExtBit)) \
4209	&& !(fHostAmd \
4210	? aHostRawExt[1].reg & (ExtBit) \
4211	: aHostRawStd[1].reg & (StdBit)) \
4212	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4213	) \
4214	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4215	} while (0)
4216	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
4217	do { \
4218	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4219	&& !(fHostAmd \
4220	? aHostRawExt[1].reg & (ExtBit) \
4221	: aHostRawStd[1].reg & (StdBit)) \
4222	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4223	) \
4224	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4225	} while (0)
4226	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
4227
4228
4229	/*
4230	* Verify that we can support the features already exposed to the guest on
4231	* this host.
4232	*
4233	* Most of the features we're emulating requires intercepting instruction
4234	* and doing it the slow way, so there is no need to warn when they aren't
4235	* present in the host CPU. Thus we use IGN instead of EMU on these.
4236	*
4237	* Trailing comments:
4238	* "EMU" - Possible to emulate, could be lots of work and very slow.
4239	* "EMU?" - Can this be emulated?
4240	*/
4241	CPUMCPUID aGuestCpuIdStd[2];
4242	RT_ZERO(aGuestCpuIdStd);
4243	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
4244
4245	/* CPUID(1).ecx */
4246	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
4247	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
4248	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
4249	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4250	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
4251	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
4252	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
4253	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
4254	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
4255	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
4256	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
4257	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
4258	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
4259	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
4260	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
4261	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
4262	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
4263	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4264	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
4265	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
4266	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
4267	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4268	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
4269	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
4270	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4271	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
4272	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
4273	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4274	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
4275	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4276	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4277	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
4278
4279	/* CPUID(1).edx */
4280	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4281	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4282	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
4283	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4284	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4285	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4286	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4287	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4288	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4289	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4290	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
4291	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4292	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4293	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4294	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4295	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4296	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4297	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4298	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4299	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
4300	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
4301	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
4302	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
4303	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4304	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4305	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
4306	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
4307	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
4308	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
4309	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
4310	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
4311	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
4312
4313	/* CPUID(0x80000000). */
4314	CPUMCPUID aGuestCpuIdExt[2];
4315	RT_ZERO(aGuestCpuIdExt);
4316	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
4317	{
4318	/** @todo deal with no 0x80000001 on the host. */
4319	bool const fHostAmd = RTX86IsAmdCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx)
4320	\|\| RTX86IsHygonCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
4321	bool const fGuestAmd = RTX86IsAmdCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx)
4322	\|\| RTX86IsHygonCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
4323
4324	/* CPUID(0x80000001).ecx */
4325	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
4326	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
4327	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
4328	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
4329	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
4330	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
4331	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
4332	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
4333	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
4334	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
4335	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
4336	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
4337	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
4338	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
4339	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4340	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4341	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4342	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4343	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4344	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4345	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4346	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4347	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4348	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4349	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4350	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4351	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4352	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4353	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4354	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4355	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4356	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4357
4358	/* CPUID(0x80000001).edx */
4359	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
4360	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
4361	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
4362	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
4363	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4364	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4365	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
4366	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
4367	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4368	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
4369	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4370	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
4371	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
4372	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
4373	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
4374	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4375	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
4376	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
4377	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4378	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4379	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4380	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
4381	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4382	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4383	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4384	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4385	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4386	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4387	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
4388	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4389	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4390	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4391	}
4392
4393	/** @todo check leaf 7 */
4394
4395	/* CPUID(d) - XCR0 stuff - takes ECX as input.
4396	* ECX=0: EAX - Valid bits in XCR0[31:0].
4397	* EBX - Maximum state size as per current XCR0 value.
4398	* ECX - Maximum state size for all supported features.
4399	* EDX - Valid bits in XCR0[63:32].
4400	* ECX=1: EAX - Various X-features.
4401	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
4402	* ECX - Valid bits in IA32_XSS[31:0].
4403	* EDX - Valid bits in IA32_XSS[63:32].
4404	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
4405	* if the bit invalid all four registers are set to zero.
4406	* EAX - The state size for this feature.
4407	* EBX - The state byte offset of this feature.
4408	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
4409	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
4410	*/
4411	uint64_t fGuestXcr0Mask = 0;
4412	PCPUMCPUIDLEAF pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
4413	if ( pCurLeaf
4414	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
4415	&& ( pCurLeaf->uEax
4416	\|\| pCurLeaf->uEbx
4417	\|\| pCurLeaf->uEcx
4418	\|\| pCurLeaf->uEdx) )
4419	{
4420	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
4421	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
4422	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4423	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
4424	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
4425	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
4426	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4427	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
4428
4429	/* We don't support any additional features yet. */
4430	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
4431	if (pCurLeaf && pCurLeaf->uEax)
4432	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4433	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
4434	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
4435	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4436	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
4437	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
4438
4439
4440	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4441	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
4442	{
4443	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4444	if (pCurLeaf)
4445	{
4446	/* If advertised, the state component offset and size must match the one used by host. */
4447	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
4448	{
4449	CPUMCPUID RawHost;
4450	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
4451	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
4452	if ( RawHost.uEbx != pCurLeaf->uEbx
4453	\|\| RawHost.uEax != pCurLeaf->uEax)
4454	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4455	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
4456	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
4457	}
4458	}
4459	}
4460	#endif
4461	}
4462	/* Clear leaf 0xd just in case we're loading an old state... */
4463	else if (pCurLeaf)
4464	{
4465	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
4466	{
4467	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4468	if (pCurLeaf)
4469	{
4470	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
4471	\|\| ( pCurLeaf->uEax == 0
4472	&& pCurLeaf->uEbx == 0
4473	&& pCurLeaf->uEcx == 0
4474	&& pCurLeaf->uEdx == 0),
4475	("uVersion=%#x; %#x %#x %#x %#x\n",
4476	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
4477	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
4478	}
4479	}
4480	}
4481
4482	/* Update the fXStateGuestMask value for the VM. */
4483	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
4484	{
4485	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
4486	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
4487	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
4488	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4489	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
4490	}
4491
4492	#undef CPUID_CHECK_RET
4493	#undef CPUID_CHECK_WRN
4494	#undef CPUID_CHECK2_RET
4495	#undef CPUID_CHECK2_WRN
4496	#undef CPUID_RAW_FEATURE_RET
4497	#undef CPUID_RAW_FEATURE_WRN
4498	#undef CPUID_RAW_FEATURE_IGN
4499	#undef CPUID_GST_FEATURE_RET
4500	#undef CPUID_GST_FEATURE_WRN
4501	#undef CPUID_GST_FEATURE_EMU
4502	#undef CPUID_GST_FEATURE_IGN
4503	#undef CPUID_GST_FEATURE2_RET
4504	#undef CPUID_GST_FEATURE2_WRN
4505	#undef CPUID_GST_FEATURE2_EMU
4506	#undef CPUID_GST_FEATURE2_IGN
4507	#undef CPUID_GST_AMD_FEATURE_RET
4508	#undef CPUID_GST_AMD_FEATURE_WRN
4509	#undef CPUID_GST_AMD_FEATURE_EMU
4510	#undef CPUID_GST_AMD_FEATURE_IGN
4511
4512	/*
4513	* We're good, commit the CPU ID leaves.
4514	*/
4515	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
4516	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
4517	AssertLogRelRCReturn(rc, rc);
4518
4519	return VINF_SUCCESS;
4520	}
4521
4522
4523	/**
4524	* Loads the CPU ID leaves saved by pass 0.
4525	*
4526	* @returns VBox status code.
4527	* @param pVM The cross context VM structure.
4528	* @param pSSM The saved state handle.
4529	* @param uVersion The format version.
4530	* @param pMsrs The guest MSRs.
4531	*/
4532	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
4533	{
4534	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4535
4536	/*
4537	* Load the CPUID leaves array first and call worker to do the rest, just so
4538	* we can free the memory when we need to without ending up in column 1000.
4539	*/
4540	PCPUMCPUIDLEAF paLeaves;
4541	uint32_t cLeaves;
4542	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
4543	AssertRC(rc);
4544	if (RT_SUCCESS(rc))
4545	{
4546	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
4547	RTMemFree(paLeaves);
4548	}
4549	return rc;
4550	}
4551
4552
4553
4554	/**
4555	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
4556	*
4557	* @returns VBox status code.
4558	* @param pVM The cross context VM structure.
4559	* @param pSSM The saved state handle.
4560	* @param uVersion The format version.
4561	*/
4562	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
4563	{
4564	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4565
4566	/*
4567	* Restore the CPUID leaves.
4568	*
4569	* Note that we support restoring less than the current amount of standard
4570	* leaves because we've been allowed more is newer version of VBox.
4571	*/
4572	uint32_t cElements;
4573	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
4574	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
4575	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4576	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
4577
4578	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
4579	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
4580	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4581	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
4582
4583	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
4584	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
4585	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4586	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
4587
4588	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4589
4590	/*
4591	* Check that the basic cpuid id information is unchanged.
4592	*/
4593	/** @todo we should check the 64 bits capabilities too! */
4594	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
4595	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4596	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
4597	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
4598	#endif
4599	uint32_t au32CpuIdSaved[8];
4600	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
4601	if (RT_SUCCESS(rc))
4602	{
4603	/* Ignore CPU stepping. */
4604	au32CpuId[4] &= 0xfffffff0;
4605	au32CpuIdSaved[4] &= 0xfffffff0;
4606
4607	/* Ignore APIC ID (AMD specs). */
4608	au32CpuId[5] &= ~0xff000000;
4609	au32CpuIdSaved[5] &= ~0xff000000;
4610
4611	/* Ignore the number of Logical CPUs (AMD specs). */
4612	au32CpuId[5] &= ~0x00ff0000;
4613	au32CpuIdSaved[5] &= ~0x00ff0000;
4614
4615	/* Ignore some advanced capability bits, that we don't expose to the guest. */
4616	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
4617	\| X86_CPUID_FEATURE_ECX_VMX
4618	\| X86_CPUID_FEATURE_ECX_SMX
4619	\| X86_CPUID_FEATURE_ECX_EST
4620	\| X86_CPUID_FEATURE_ECX_TM2
4621	\| X86_CPUID_FEATURE_ECX_CNTXID
4622	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
4623	\| X86_CPUID_FEATURE_ECX_PDCM
4624	\| X86_CPUID_FEATURE_ECX_DCA
4625	\| X86_CPUID_FEATURE_ECX_X2APIC
4626	);
4627	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
4628	\| X86_CPUID_FEATURE_ECX_VMX
4629	\| X86_CPUID_FEATURE_ECX_SMX
4630	\| X86_CPUID_FEATURE_ECX_EST
4631	\| X86_CPUID_FEATURE_ECX_TM2
4632	\| X86_CPUID_FEATURE_ECX_CNTXID
4633	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
4634	\| X86_CPUID_FEATURE_ECX_PDCM
4635	\| X86_CPUID_FEATURE_ECX_DCA
4636	\| X86_CPUID_FEATURE_ECX_X2APIC
4637	);
4638
4639	/* Make sure we don't forget to update the masks when enabling
4640	* features in the future.
4641	*/
4642	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
4643	( X86_CPUID_FEATURE_ECX_DTES64
4644	\| X86_CPUID_FEATURE_ECX_VMX
4645	\| X86_CPUID_FEATURE_ECX_SMX
4646	\| X86_CPUID_FEATURE_ECX_EST
4647	\| X86_CPUID_FEATURE_ECX_TM2
4648	\| X86_CPUID_FEATURE_ECX_CNTXID
4649	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
4650	\| X86_CPUID_FEATURE_ECX_PDCM
4651	\| X86_CPUID_FEATURE_ECX_DCA
4652	\| X86_CPUID_FEATURE_ECX_X2APIC
4653	)));
4654	/* do the compare */
4655	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
4656	{
4657	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
4658	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
4659	"Saved=%.*Rhxs\n"
4660	"Real =%.*Rhxs\n",
4661	sizeof(au32CpuIdSaved), au32CpuIdSaved,
4662	sizeof(au32CpuId), au32CpuId));
4663	else
4664	{
4665	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
4666	"Saved=%.*Rhxs\n"
4667	"Real =%.*Rhxs\n",
4668	sizeof(au32CpuIdSaved), au32CpuIdSaved,
4669	sizeof(au32CpuId), au32CpuId));
4670	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
4671	}
4672	}
4673	}
4674
4675	return rc;
4676	}
4677
4678
4679
4680	/*
4681	*
4682	*
4683	* CPUID Info Handler.
4684	* CPUID Info Handler.
4685	* CPUID Info Handler.
4686	*
4687	*
4688	*/
4689
4690
4691
4692	/**
4693	* Get L1 cache / TLS associativity.
4694	*/
4695	static const char getCacheAss(unsigned u, char pszBuf)
4696	{
4697	if (u == 0)
4698	return "res0 ";
4699	if (u == 1)
4700	return "direct";
4701	if (u == 255)
4702	return "fully";
4703	if (u >= 256)
4704	return "???";
4705
4706	RTStrPrintf(pszBuf, 16, "%d way", u);
4707	return pszBuf;
4708	}
4709
4710
4711	/**
4712	* Get L2 cache associativity.
4713	*/
4714	static const char *getL2CacheAss(unsigned u)
4715	{
4716	switch (u)
4717	{
4718	case 0: return "off ";
4719	case 1: return "direct";
4720	case 2: return "2 way ";
4721	case 3: return "res3 ";
4722	case 4: return "4 way ";
4723	case 5: return "res5 ";
4724	case 6: return "8 way ";
4725	case 7: return "res7 ";
4726	case 8: return "16 way";
4727	case 9: return "res9 ";
4728	case 10: return "res10 ";
4729	case 11: return "res11 ";
4730	case 12: return "res12 ";
4731	case 13: return "res13 ";
4732	case 14: return "res14 ";
4733	case 15: return "fully ";
4734	default: return "????";
4735	}
4736	}
4737
4738
4739	/** CPUID(1).EDX field descriptions. */
4740	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
4741	{
4742	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
4743	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
4744	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
4745	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
4746	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
4747	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
4748	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
4749	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
4750	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
4751	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
4752	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
4753	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
4754	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
4755	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
4756	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
4757	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
4758	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
4759	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
4760	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
4761	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
4762	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
4763	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
4764	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
4765	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
4766	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
4767	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
4768	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
4769	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
4770	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
4771	DBGFREGSUBFIELD_TERMINATOR()
4772	};
4773
4774	/** CPUID(1).ECX field descriptions. */
4775	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
4776	{
4777	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
4778	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
4779	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
4780	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
4781	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
4782	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
4783	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
4784	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
4785	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
4786	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
4787	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
4788	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
4789	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
4790	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
4791	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
4792	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
4793	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
4794	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
4795	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
4796	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
4797	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
4798	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
4799	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
4800	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
4801	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
4802	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
4803	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
4804	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
4805	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
4806	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
4807	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
4808	DBGFREGSUBFIELD_TERMINATOR()
4809	};
4810
4811	/** CPUID(7,0).EBX field descriptions. */
4812	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
4813	{
4814	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
4815	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
4816	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
4817	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
4818	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
4819	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
4820	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
4821	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
4822	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
4823	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
4824	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
4825	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
4826	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
4827	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
4828	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
4829	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
4830	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
4831	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
4832	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
4833	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
4834	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
4835	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
4836	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
4837	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
4838	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
4839	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
4840	DBGFREGSUBFIELD_TERMINATOR()
4841	};
4842
4843	/** CPUID(7,0).ECX field descriptions. */
4844	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
4845	{
4846	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
4847	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
4848	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
4849	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
4850	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
4851	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
4852	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
4853	DBGFREGSUBFIELD_TERMINATOR()
4854	};
4855
4856	/** CPUID(7,0).EDX field descriptions. */
4857	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
4858	{
4859	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
4860	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
4861	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
4862	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
4863	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
4864	DBGFREGSUBFIELD_RO("CORECAP\0" "Supports IA32_CORE_CAP", 30, 1, 0),
4865	DBGFREGSUBFIELD_RO("SSBD\0" "Supports IA32_SPEC_CTRL.SSBD", 31, 1, 0),
4866	DBGFREGSUBFIELD_TERMINATOR()
4867	};
4868
4869
4870	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
4871	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
4872	{
4873	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
4874	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
4875	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
4876	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
4877	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
4878	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
4879	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
4880	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
4881	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
4882	DBGFREGSUBFIELD_TERMINATOR()
4883	};
4884
4885	/** CPUID(13,1).EAX field descriptions. */
4886	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
4887	{
4888	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
4889	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
4890	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
4891	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
4892	DBGFREGSUBFIELD_TERMINATOR()
4893	};
4894
4895
4896	/** CPUID(0x80000001,0).EDX field descriptions. */
4897	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
4898	{
4899	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
4900	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
4901	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
4902	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
4903	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
4904	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
4905	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
4906	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
4907	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
4908	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
4909	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
4910	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
4911	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
4912	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
4913	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
4914	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
4915	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
4916	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
4917	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
4918	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
4919	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
4920	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
4921	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
4922	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
4923	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
4924	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
4925	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
4926	DBGFREGSUBFIELD_TERMINATOR()
4927	};
4928
4929	/** CPUID(0x80000001,0).ECX field descriptions. */
4930	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
4931	{
4932	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
4933	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
4934	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
4935	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
4936	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
4937	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
4938	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
4939	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
4940	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
4941	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
4942	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
4943	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
4944	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
4945	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
4946	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
4947	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
4948	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
4949	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
4950	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
4951	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
4952	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
4953	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
4954	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
4955	DBGFREGSUBFIELD_RO("PCX_L2I\0" "L2I/L3 Performance Counter Extensions", 28, 1, 0),
4956	DBGFREGSUBFIELD_RO("MWAITX\0" "MWAITX and MONITORX instructions", 29, 1, 0),
4957	DBGFREGSUBFIELD_TERMINATOR()
4958	};
4959
4960	/** CPUID(0x8000000a,0).EDX field descriptions. */
4961	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
4962	{
4963	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
4964	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
4965	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
4966	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
4967	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
4968	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
4969	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
4970	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
4971	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
4972	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
4973	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
4974	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
4975	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
4976	DBGFREGSUBFIELD_RO("GMET\0" "Guest Mode Execute Trap Extension", 17, 1, 0),
4977	DBGFREGSUBFIELD_TERMINATOR()
4978	};
4979
4980
4981	/** CPUID(0x80000007,0).EDX field descriptions. */
4982	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
4983	{
4984	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
4985	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
4986	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
4987	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
4988	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
4989	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
4990	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
4991	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
4992	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
4993	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
4994	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
4995	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
4996	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
4997	DBGFREGSUBFIELD_TERMINATOR()
4998	};
4999
5000	/** CPUID(0x80000008,0).EBX field descriptions. */
5001	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
5002	{
5003	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
5004	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
5005	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR)", 2, 1, 0),
5006	DBGFREGSUBFIELD_RO("RDPRU\0" "RDPRU instruction", 4, 1, 0),
5007	DBGFREGSUBFIELD_RO("MCOMMIT\0" "MCOMMIT instruction", 8, 1, 0),
5008	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
5009	DBGFREGSUBFIELD_TERMINATOR()
5010	};
5011
5012
5013	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
5014	const char *pszLeadIn, uint32_t cchWidth)
5015	{
5016	if (pszLeadIn)
5017	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5018
5019	for (uint32_t iBit = 0; iBit < 32; iBit++)
5020	if (RT_BIT_32(iBit) & uVal)
5021	{
5022	while ( pDesc->pszName != NULL
5023	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5024	pDesc++;
5025	if ( pDesc->pszName != NULL
5026	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5027	{
5028	if (pDesc->cBits == 1)
5029	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5030	else
5031	{
5032	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
5033	if (pDesc->cBits < 32)
5034	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5035	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
5036	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5037	}
5038	}
5039	else
5040	pHlp->pfnPrintf(pHlp, " %u", iBit);
5041	}
5042	if (pszLeadIn)
5043	pHlp->pfnPrintf(pHlp, "\n");
5044	}
5045
5046
5047	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5048	const char *pszLeadIn, uint32_t cchWidth)
5049	{
5050	if (pszLeadIn)
5051	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5052
5053	for (uint32_t iBit = 0; iBit < 64; iBit++)
5054	if (RT_BIT_64(iBit) & uVal)
5055	{
5056	while ( pDesc->pszName != NULL
5057	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5058	pDesc++;
5059	if ( pDesc->pszName != NULL
5060	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5061	{
5062	if (pDesc->cBits == 1)
5063	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5064	else
5065	{
5066	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
5067	if (pDesc->cBits < 64)
5068	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
5069	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
5070	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5071	}
5072	}
5073	else
5074	pHlp->pfnPrintf(pHlp, " %u", iBit);
5075	}
5076	if (pszLeadIn)
5077	pHlp->pfnPrintf(pHlp, "\n");
5078	}
5079
5080
5081	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5082	const char *pszLeadIn, uint32_t cchWidth)
5083	{
5084	if (!uVal)
5085	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5086	else
5087	{
5088	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5089	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
5090	pHlp->pfnPrintf(pHlp, " )\n");
5091	}
5092	}
5093
5094
5095	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
5096	uint32_t cchWidth)
5097	{
5098	uint32_t uCombined = uVal1 \| uVal2;
5099	for (uint32_t iBit = 0; iBit < 32; iBit++)
5100	if ( (RT_BIT_32(iBit) & uCombined)
5101	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
5102	{
5103	while ( pDesc->pszName != NULL
5104	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5105	pDesc++;
5106
5107	if ( pDesc->pszName != NULL
5108	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5109	{
5110	size_t cchMnemonic = strlen(pDesc->pszName);
5111	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
5112	size_t cchDesc = strlen(pszDesc);
5113	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
5114	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
5115	if (pDesc->cBits < 32)
5116	{
5117	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5118	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5119	}
5120
5121	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
5122	pDesc->pszName, pszDesc,
5123	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
5124	uFieldValue1, uFieldValue2);
5125
5126	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
5127	pDesc++;
5128	}
5129	else
5130	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
5131	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
5132	}
5133	}
5134
5135
5136	/**
5137	* Produces a detailed summary of standard leaf 0x00000001.
5138	*
5139	* @param pHlp The info helper functions.
5140	* @param pCurLeaf The 0x00000001 leaf.
5141	* @param fVerbose Whether to be very verbose or not.
5142	* @param fIntel Set if intel CPU.
5143	*/
5144	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
5145	{
5146	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
5147	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
5148	uint32_t uEAX = pCurLeaf->uEax;
5149	uint32_t uEBX = pCurLeaf->uEbx;
5150
5151	pHlp->pfnPrintf(pHlp,
5152	"%36s %2d \tExtended: %d \tEffective: %d\n"
5153	"%36s %2d \tExtended: %d \tEffective: %d\n"
5154	"%36s %d\n"
5155	"%36s %d (%s)\n"
5156	"%36s %#04x\n"
5157	"%36s %d\n"
5158	"%36s %d\n"
5159	"%36s %#04x\n"
5160	,
5161	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
5162	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
5163	"Stepping:", RTX86GetCpuStepping(uEAX),
5164	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
5165	"APIC ID:", (uEBX >> 24) & 0xff,
5166	"Logical CPUs:",(uEBX >> 16) & 0xff,
5167	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
5168	"Brand ID:", (uEBX >> 0) & 0xff);
5169	if (fVerbose)
5170	{
5171	CPUMCPUID Host = {0};
5172	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5173	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5174	#endif
5175	pHlp->pfnPrintf(pHlp, "Features\n");
5176	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5177	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
5178	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
5179	}
5180	else
5181	{
5182	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
5183	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
5184	}
5185	}
5186
5187
5188	/**
5189	* Produces a detailed summary of standard leaf 0x00000007.
5190	*
5191	* @param pHlp The info helper functions.
5192	* @param paLeaves The CPUID leaves array.
5193	* @param cLeaves The number of leaves in the array.
5194	* @param pCurLeaf The first 0x00000007 leaf.
5195	* @param fVerbose Whether to be very verbose or not.
5196	*/
5197	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5198	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5199	{
5200	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
5201	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
5202	for (;;)
5203	{
5204	CPUMCPUID Host = {0};
5205	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5206	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5207	#endif
5208
5209	switch (pCurLeaf->uSubLeaf)
5210	{
5211	case 0:
5212	if (fVerbose)
5213	{
5214	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5215	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
5216	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
5217	if (pCurLeaf->uEdx \|\| Host.uEdx)
5218	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
5219	}
5220	else
5221	{
5222	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
5223	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
5224	if (pCurLeaf->uEdx)
5225	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
5226	}
5227	break;
5228
5229	default:
5230	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
5231	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
5232	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
5233	break;
5234
5235	}
5236
5237	/* advance. */
5238	pCurLeaf++;
5239	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5240	\|\| pCurLeaf->uLeaf != 0x7)
5241	break;
5242	}
5243	}
5244
5245
5246	/**
5247	* Produces a detailed summary of standard leaf 0x0000000d.
5248	*
5249	* @param pHlp The info helper functions.
5250	* @param paLeaves The CPUID leaves array.
5251	* @param cLeaves The number of leaves in the array.
5252	* @param pCurLeaf The first 0x00000007 leaf.
5253	* @param fVerbose Whether to be very verbose or not.
5254	*/
5255	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5256	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5257	{
5258	RT_NOREF_PV(fVerbose);
5259	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
5260	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
5261	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5262	{
5263	CPUMCPUID Host = {0};
5264	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5265	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5266	#endif
5267
5268	switch (uSubLeaf)
5269	{
5270	case 0:
5271	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5272	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
5273	pCurLeaf->uEbx, pCurLeaf->uEcx);
5274	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
5275
5276	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5277	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
5278	"Valid XCR0 bits, guest:", 42);
5279	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
5280	"Valid XCR0 bits, host:", 42);
5281	break;
5282
5283	case 1:
5284	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5285	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
5286	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
5287
5288	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5289	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
5290	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
5291
5292	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5293	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
5294	" Valid IA32_XSS bits, guest:", 42);
5295	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
5296	" Valid IA32_XSS bits, host:", 42);
5297	break;
5298
5299	default:
5300	if ( pCurLeaf
5301	&& pCurLeaf->uSubLeaf == uSubLeaf
5302	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
5303	{
5304	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
5305	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5306	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
5307	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
5308	if (pCurLeaf->uEdx)
5309	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
5310	pHlp->pfnPrintf(pHlp, " --");
5311	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5312	pHlp->pfnPrintf(pHlp, "\n");
5313	}
5314	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
5315	{
5316	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
5317	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5318	if (Host.uEcx & ~RT_BIT_32(0))
5319	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
5320	if (Host.uEdx)
5321	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
5322	pHlp->pfnPrintf(pHlp, " --");
5323	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5324	pHlp->pfnPrintf(pHlp, "\n");
5325	}
5326	break;
5327
5328	}
5329
5330	/* advance. */
5331	if (pCurLeaf)
5332	{
5333	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5334	&& pCurLeaf->uSubLeaf <= uSubLeaf
5335	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
5336	pCurLeaf++;
5337	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5338	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
5339	pCurLeaf = NULL;
5340	}
5341	}
5342	}
5343
5344
5345	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5346	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
5347	{
5348	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5349	&& pCurLeaf->uLeaf <= uUpToLeaf)
5350	{
5351	pHlp->pfnPrintf(pHlp,
5352	" %s\n"
5353	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
5354	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5355	&& pCurLeaf->uLeaf <= uUpToLeaf)
5356	{
5357	CPUMCPUID Host = {0};
5358	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5359	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5360	#endif
5361	pHlp->pfnPrintf(pHlp,
5362	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5363	"Hst: %08x %08x %08x %08x\n",
5364	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5365	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5366	pCurLeaf++;
5367	}
5368	}
5369
5370	return pCurLeaf;
5371	}
5372
5373
5374	/**
5375	* Display the guest CpuId leaves.
5376	*
5377	* @param pVM The cross context VM structure.
5378	* @param pHlp The info helper functions.
5379	* @param pszArgs "terse", "default" or "verbose".
5380	*/
5381	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
5382	{
5383	/*
5384	* Parse the argument.
5385	*/
5386	unsigned iVerbosity = 1;
5387	if (pszArgs)
5388	{
5389	pszArgs = RTStrStripL(pszArgs);
5390	if (!strcmp(pszArgs, "terse"))
5391	iVerbosity--;
5392	else if (!strcmp(pszArgs, "verbose"))
5393	iVerbosity++;
5394	}
5395
5396	uint32_t uLeaf;
5397	CPUMCPUID Host = {0};
5398	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
5399	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
5400	PCCPUMCPUIDLEAF pCurLeaf;
5401	PCCPUMCPUIDLEAF pNextLeaf;
5402	bool const fIntel = RTX86IsIntelCpu(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
5403	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
5404	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
5405
5406	/*
5407	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
5408	*/
5409	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5410	uint32_t cHstMax = ASMCpuId_EAX(0);
5411	#else
5412	uint32_t cHstMax = 0;
5413	#endif
5414	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
5415	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
5416	pHlp->pfnPrintf(pHlp,
5417	" Raw Standard CPUID Leaves\n"
5418	" Leaf/sub-leaf eax ebx ecx edx\n");
5419	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
5420	{
5421	uint32_t cMaxSubLeaves = 1;
5422	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
5423	cMaxSubLeaves = 16;
5424	else if (uLeaf == 0xd)
5425	cMaxSubLeaves = 128;
5426
5427	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5428	{
5429	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5430	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5431	#endif
5432	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5433	&& pCurLeaf->uLeaf == uLeaf
5434	&& pCurLeaf->uSubLeaf == uSubLeaf)
5435	{
5436	pHlp->pfnPrintf(pHlp,
5437	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5438	"Hst: %08x %08x %08x %08x\n",
5439	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5440	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5441	pCurLeaf++;
5442	}
5443	else if ( uLeaf != 0xd
5444	\|\| uSubLeaf <= 1
5445	\|\| Host.uEbx != 0 )
5446	pHlp->pfnPrintf(pHlp,
5447	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5448	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5449
5450	/* Done? */
5451	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5452	\|\| pCurLeaf->uLeaf != uLeaf)
5453	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
5454	\|\| (uLeaf == 0x7 && Host.uEax == 0)
5455	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
5456	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
5457	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
5458	)
5459	)
5460	break;
5461	}
5462	}
5463	pNextLeaf = pCurLeaf;
5464
5465	/*
5466	* If verbose, decode it.
5467	*/
5468	if (iVerbosity && paLeaves[0].uLeaf == 0)
5469	pHlp->pfnPrintf(pHlp,
5470	"%36s %.04s%.04s%.04s\n"
5471	"%36s 0x00000000-%#010x\n"
5472	,
5473	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
5474	"Supports:", paLeaves[0].uEax);
5475
5476	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
5477	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
5478
5479	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
5480	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5481
5482	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
5483	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5484
5485	pCurLeaf = pNextLeaf;
5486
5487	/*
5488	* Hypervisor leaves.
5489	*
5490	* Unlike most of the other leaves reported, the guest hypervisor leaves
5491	* aren't a subset of the host CPUID bits.
5492	*/
5493	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
5494
5495	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5496	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5497	#endif
5498	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
5499	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
5500	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
5501	cMax = RT_MAX(cHstMax, cGstMax);
5502	if (cMax >= UINT32_C(0x40000000))
5503	{
5504	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
5505
5506	/** @todo dump these in more detail. */
5507
5508	pCurLeaf = pNextLeaf;
5509	}
5510
5511
5512	/*
5513	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
5514	* Implemented after AMD specs.
5515	*/
5516	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
5517
5518	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5519	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5520	#endif
5521	cHstMax = RTX86IsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
5522	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
5523	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
5524	cMax = RT_MAX(cHstMax, cGstMax);
5525	if (cMax >= UINT32_C(0x80000000))
5526	{
5527
5528	pHlp->pfnPrintf(pHlp,
5529	" Raw Extended CPUID Leaves\n"
5530	" Leaf/sub-leaf eax ebx ecx edx\n");
5531	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
5532	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
5533	{
5534	uint32_t cMaxSubLeaves = 1;
5535	if (uLeaf == UINT32_C(0x8000001d))
5536	cMaxSubLeaves = 16;
5537
5538	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5539	{
5540	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5541	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5542	#endif
5543	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5544	&& pCurLeaf->uLeaf == uLeaf
5545	&& pCurLeaf->uSubLeaf == uSubLeaf)
5546	{
5547	pHlp->pfnPrintf(pHlp,
5548	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5549	"Hst: %08x %08x %08x %08x\n",
5550	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5551	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5552	pCurLeaf++;
5553	}
5554	else if ( uLeaf != 0xd
5555	\|\| uSubLeaf <= 1
5556	\|\| Host.uEbx != 0 )
5557	pHlp->pfnPrintf(pHlp,
5558	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5559	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5560
5561	/* Done? */
5562	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5563	\|\| pCurLeaf->uLeaf != uLeaf)
5564	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
5565	break;
5566	}
5567	}
5568	pNextLeaf = pCurLeaf;
5569
5570	/*
5571	* Understandable output
5572	*/
5573	if (iVerbosity)
5574	pHlp->pfnPrintf(pHlp,
5575	"Ext Name: %.4s%.4s%.4s\n"
5576	"Ext Supports: 0x80000000-%#010x\n",
5577	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
5578
5579	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
5580	if (iVerbosity && pCurLeaf)
5581	{
5582	uint32_t uEAX = pCurLeaf->uEax;
5583	pHlp->pfnPrintf(pHlp,
5584	"Family: %d \tExtended: %d \tEffective: %d\n"
5585	"Model: %d \tExtended: %d \tEffective: %d\n"
5586	"Stepping: %d\n"
5587	"Brand ID: %#05x\n",
5588	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
5589	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
5590	RTX86GetCpuStepping(uEAX),
5591	pCurLeaf->uEbx & 0xfff);
5592
5593	if (iVerbosity == 1)
5594	{
5595	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
5596	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
5597	}
5598	else
5599	{
5600	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5601	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5602	#endif
5603	pHlp->pfnPrintf(pHlp, "Ext Features\n");
5604	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5605	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
5606	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
5607	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
5608	{
5609	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
5610	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5611	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5612	#endif
5613	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
5614	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
5615	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
5616	}
5617	}
5618	}
5619
5620	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
5621	{
5622	char szString[443+1] = {0};
5623	uint32_t pu32 = (uint32_t )szString;
5624	*pu32++ = pCurLeaf->uEax;
5625	*pu32++ = pCurLeaf->uEbx;
5626	*pu32++ = pCurLeaf->uEcx;
5627	*pu32++ = pCurLeaf->uEdx;
5628	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
5629	if (pCurLeaf)
5630	{
5631	*pu32++ = pCurLeaf->uEax;
5632	*pu32++ = pCurLeaf->uEbx;
5633	*pu32++ = pCurLeaf->uEcx;
5634	*pu32++ = pCurLeaf->uEdx;
5635	}
5636	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
5637	if (pCurLeaf)
5638	{
5639	*pu32++ = pCurLeaf->uEax;
5640	*pu32++ = pCurLeaf->uEbx;
5641	*pu32++ = pCurLeaf->uEcx;
5642	*pu32++ = pCurLeaf->uEdx;
5643	}
5644	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
5645	}
5646
5647	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
5648	{
5649	uint32_t uEAX = pCurLeaf->uEax;
5650	uint32_t uEBX = pCurLeaf->uEbx;
5651	uint32_t uECX = pCurLeaf->uEcx;
5652	uint32_t uEDX = pCurLeaf->uEdx;
5653	char sz1[32];
5654	char sz2[32];
5655
5656	pHlp->pfnPrintf(pHlp,
5657	"TLB 2/4M Instr/Uni: %s %3d entries\n"
5658	"TLB 2/4M Data: %s %3d entries\n",
5659	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
5660	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
5661	pHlp->pfnPrintf(pHlp,
5662	"TLB 4K Instr/Uni: %s %3d entries\n"
5663	"TLB 4K Data: %s %3d entries\n",
5664	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
5665	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
5666	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
5667	"L1 Instr Cache Lines Per Tag: %d\n"
5668	"L1 Instr Cache Associativity: %s\n"
5669	"L1 Instr Cache Size: %d KB\n",
5670	(uEDX >> 0) & 0xff,
5671	(uEDX >> 8) & 0xff,
5672	getCacheAss((uEDX >> 16) & 0xff, sz1),
5673	(uEDX >> 24) & 0xff);
5674	pHlp->pfnPrintf(pHlp,
5675	"L1 Data Cache Line Size: %d bytes\n"
5676	"L1 Data Cache Lines Per Tag: %d\n"
5677	"L1 Data Cache Associativity: %s\n"
5678	"L1 Data Cache Size: %d KB\n",
5679	(uECX >> 0) & 0xff,
5680	(uECX >> 8) & 0xff,
5681	getCacheAss((uECX >> 16) & 0xff, sz1),
5682	(uECX >> 24) & 0xff);
5683	}
5684
5685	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
5686	{
5687	uint32_t uEAX = pCurLeaf->uEax;
5688	uint32_t uEBX = pCurLeaf->uEbx;
5689	uint32_t uEDX = pCurLeaf->uEdx;
5690
5691	pHlp->pfnPrintf(pHlp,
5692	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
5693	"L2 TLB 2/4M Data: %s %4d entries\n",
5694	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
5695	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
5696	pHlp->pfnPrintf(pHlp,
5697	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
5698	"L2 TLB 4K Data: %s %4d entries\n",
5699	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
5700	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
5701	pHlp->pfnPrintf(pHlp,
5702	"L2 Cache Line Size: %d bytes\n"
5703	"L2 Cache Lines Per Tag: %d\n"
5704	"L2 Cache Associativity: %s\n"
5705	"L2 Cache Size: %d KB\n",
5706	(uEDX >> 0) & 0xff,
5707	(uEDX >> 8) & 0xf,
5708	getL2CacheAss((uEDX >> 12) & 0xf),
5709	(uEDX >> 16) & 0xffff);
5710	}
5711
5712	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
5713	{
5714	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5715	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5716	#endif
5717	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
5718	{
5719	if (iVerbosity < 1)
5720	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
5721	else
5722	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
5723	}
5724	}
5725
5726	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
5727	if (pCurLeaf != NULL)
5728	{
5729	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5730	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5731	#endif
5732	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
5733	{
5734	if (iVerbosity < 1)
5735	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
5736	else
5737	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
5738	}
5739
5740	if (iVerbosity)
5741	{
5742	uint32_t uEAX = pCurLeaf->uEax;
5743	uint32_t uECX = pCurLeaf->uEcx;
5744
5745	/** @todo 0x80000008:EAX[23:16] is only defined for AMD. We'll get 0 on Intel. On
5746	* AMD if we get 0, the guest physical address width should be taken from
5747	* 0x80000008:EAX[7:0] instead. Guest Physical address width is relevant
5748	* for guests using nested paging. */
5749	pHlp->pfnPrintf(pHlp,
5750	"Physical Address Width: %d bits\n"
5751	"Virtual Address Width: %d bits\n"
5752	"Guest Physical Address Width: %d bits\n",
5753	(uEAX >> 0) & 0xff,
5754	(uEAX >> 8) & 0xff,
5755	(uEAX >> 16) & 0xff);
5756
5757	/** @todo 0x80000008:ECX is reserved on Intel (we'll get incorrect physical core
5758	* count here). */
5759	pHlp->pfnPrintf(pHlp,
5760	"Physical Core Count: %d\n",
5761	((uECX >> 0) & 0xff) + 1);
5762	}
5763	}
5764
5765	pCurLeaf = pNextLeaf;
5766	}
5767
5768
5769
5770	/*
5771	* Centaur.
5772	*/
5773	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
5774
5775	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5776	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5777	#endif
5778	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
5779	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
5780	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
5781	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
5782	cMax = RT_MAX(cHstMax, cGstMax);
5783	if (cMax >= UINT32_C(0xc0000000))
5784	{
5785	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
5786
5787	/*
5788	* Understandable output
5789	*/
5790	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
5791	pHlp->pfnPrintf(pHlp,
5792	"Centaur Supports: 0xc0000000-%#010x\n",
5793	pCurLeaf->uEax);
5794
5795	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
5796	{
5797	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5798	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5799	#endif
5800	uint32_t uEdxGst = pCurLeaf->uEdx;
5801	uint32_t uEdxHst = Host.uEdx;
5802
5803	if (iVerbosity == 1)
5804	{
5805	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
5806	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
5807	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
5808	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
5809	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
5810	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
5811	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
5812	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
5813	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
5814	/* possibly indicating MM/HE and MM/HE-E on older chips... */
5815	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
5816	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
5817	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
5818	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
5819	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
5820	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
5821	for (unsigned iBit = 14; iBit < 32; iBit++)
5822	if (uEdxGst & RT_BIT(iBit))
5823	pHlp->pfnPrintf(pHlp, " %d", iBit);
5824	pHlp->pfnPrintf(pHlp, "\n");
5825	}
5826	else
5827	{
5828	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
5829	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
5830	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
5831	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
5832	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
5833	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
5834	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
5835	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
5836	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
5837	/* possibly indicating MM/HE and MM/HE-E on older chips... */
5838	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
5839	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
5840	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
5841	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
5842	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
5843	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
5844	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
5845	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
5846	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
5847	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
5848	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
5849	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
5850	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
5851	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
5852	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
5853	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
5854	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
5855	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
5856	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
5857	for (unsigned iBit = 27; iBit < 32; iBit++)
5858	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
5859	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
5860	pHlp->pfnPrintf(pHlp, "\n");
5861	}
5862	}
5863
5864	pCurLeaf = pNextLeaf;
5865	}
5866
5867	/*
5868	* The remainder.
5869	*/
5870	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
5871	}
5872
5873	#endif /* !IN_VBOX_CPU_REPORT */
5874

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 100696

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