CPUMR3CpuId.cpp@ 107570

Last change on this file since 107570 was 107570, checked in by vboxsync, 10 days ago
VMM/CPUM: Report the host CPU microcode revision number to the guest when on an amd64 host. jiraref:VBP-947
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1	/* $Id: CPUMR3CpuId.cpp 107570 2025-01-09 09:23:18Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_CPUM
33	#include <VBox/vmm/cpum.h>
34	#include <VBox/vmm/dbgf.h>
35	#include <VBox/vmm/hm.h>
36	#include <VBox/vmm/nem.h>
37	#include <VBox/vmm/ssm.h>
38	#include "CPUMInternal.h"
39	#include <VBox/vmm/vmcc.h>
40	#include <VBox/sup.h>
41
42	#include <VBox/err.h>
43	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
44	# include <iprt/asm-amd64-x86.h>
45	#endif
46	#include <iprt/ctype.h>
47	#include <iprt/mem.h>
48	#include <iprt/string.h>
49	#include <iprt/x86-helpers.h>
50
51
52	/*********************************************************************************************************************************
53	* Defined Constants And Macros *
54	*********************************************************************************************************************************/
55	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
56	#define CPUM_CPUID_MAX_LEAVES 2048
57
58
59	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
60	/**
61	* Determins the host CPU MXCSR mask.
62	*
63	* @returns MXCSR mask.
64	*/
65	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
66	{
67	if ( ASMHasCpuId()
68	&& RTX86IsValidStdRange(ASMCpuId_EAX(0))
69	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
70	{
71	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
72	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
73	RT_ZERO(*pState);
74	ASMFxSave(pState);
75	if (pState->MXCSR_MASK == 0)
76	return 0xffbf;
77	return pState->MXCSR_MASK;
78	}
79	return 0;
80	}
81	#endif
82
83
84
85	#ifndef IN_VBOX_CPU_REPORT
86	/**
87	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
88	*
89	* @returns true if found, false it not.
90	* @param paLeaves The CPUID leaves to search. This is sorted.
91	* @param cLeaves The number of leaves in the array.
92	* @param uLeaf The leaf to locate.
93	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
94	* @param pLegacy The legacy output leaf.
95	*/
96	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
97	PCPUMCPUID pLegacy)
98	{
99	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, uLeaf, uSubLeaf);
100	if (pLeaf)
101	{
102	pLegacy->uEax = pLeaf->uEax;
103	pLegacy->uEbx = pLeaf->uEbx;
104	pLegacy->uEcx = pLeaf->uEcx;
105	pLegacy->uEdx = pLeaf->uEdx;
106	return true;
107	}
108	return false;
109	}
110	#endif /* IN_VBOX_CPU_REPORT */
111
112
113	/**
114	* Inserts a CPU ID leaf, replacing any existing ones.
115	*
116	* When inserting a simple leaf where we already got a series of sub-leaves with
117	* the same leaf number (eax), the simple leaf will replace the whole series.
118	*
119	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
120	* host-context heap and has only been allocated/reallocated by the
121	* cpumCpuIdEnsureSpace function.
122	*
123	* @returns VBox status code.
124	* @param pVM The cross context VM structure. If NULL, use
125	* the process heap, otherwise the VM's hyper heap.
126	* @param ppaLeaves Pointer to the pointer to the array of sorted
127	* CPUID leaves and sub-leaves. Must be NULL if using
128	* the hyper heap.
129	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
130	* be NULL if using the hyper heap.
131	* @param pNewLeaf Pointer to the data of the new leaf we're about to
132	* insert.
133	*/
134	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
135	{
136	/*
137	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
138	*/
139	if (pVM)
140	{
141	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
142	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
143	AssertReturn(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 == pVM->cpum.s.GuestInfo.aCpuIdLeaves, VERR_INVALID_PARAMETER);
144
145	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
146	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
147	}
148
149	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
150	uint32_t cLeaves = *pcLeaves;
151
152	/*
153	* Validate the new leaf a little.
154	*/
155	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
156	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
157	VERR_INVALID_FLAGS);
158	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
159	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
160	VERR_INVALID_PARAMETER);
161	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
162	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
163	VERR_INVALID_PARAMETER);
164	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
165	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
166	VERR_INVALID_PARAMETER);
167
168	/*
169	* Find insertion point. The lazy bird uses the same excuse as in
170	* cpumCpuIdGetLeaf(), but optimizes for linear insertion (saved state).
171	*/
172	uint32_t i;
173	if ( cLeaves > 0
174	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
175	{
176	/* Add at end. */
177	i = cLeaves;
178	}
179	else if ( cLeaves > 0
180	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
181	{
182	/* Either replacing the last leaf or dealing with sub-leaves. Spool
183	back to the first sub-leaf to pretend we did the linear search. */
184	i = cLeaves - 1;
185	while ( i > 0
186	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
187	i--;
188	}
189	else
190	{
191	/* Linear search from the start. */
192	i = 0;
193	while ( i < cLeaves
194	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
195	i++;
196	}
197	if ( i < cLeaves
198	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
199	{
200	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
201	{
202	/*
203	* The sub-leaf mask differs, replace all existing leaves with the
204	* same leaf number.
205	*/
206	uint32_t c = 1;
207	while ( i + c < cLeaves
208	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
209	c++;
210	if (c > 1 && i + c < cLeaves)
211	{
212	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
213	*pcLeaves = cLeaves -= c - 1;
214	}
215
216	paLeaves[i] = *pNewLeaf;
217	#ifdef VBOX_STRICT
218	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
219	#endif
220	return VINF_SUCCESS;
221	}
222
223	/* Find sub-leaf insertion point. */
224	while ( i < cLeaves
225	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
226	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
227	i++;
228
229	/*
230	* If we've got an exactly matching leaf, replace it.
231	*/
232	if ( i < cLeaves
233	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
234	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
235	{
236	paLeaves[i] = *pNewLeaf;
237	#ifdef VBOX_STRICT
238	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
239	#endif
240	return VINF_SUCCESS;
241	}
242	}
243
244	/*
245	* Adding a new leaf at 'i'.
246	*/
247	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
248	paLeaves = cpumCpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
249	if (!paLeaves)
250	return VERR_NO_MEMORY;
251
252	if (i < cLeaves)
253	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
254	*pcLeaves += 1;
255	paLeaves[i] = *pNewLeaf;
256
257	#ifdef VBOX_STRICT
258	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
259	#endif
260	return VINF_SUCCESS;
261	}
262
263
264	#ifndef IN_VBOX_CPU_REPORT
265	/**
266	* Removes a range of CPUID leaves.
267	*
268	* This will not reallocate the array.
269	*
270	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
271	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
272	* @param uFirst The first leaf.
273	* @param uLast The last leaf.
274	*/
275	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
276	{
277	uint32_t cLeaves = *pcLeaves;
278
279	Assert(uFirst <= uLast);
280
281	/*
282	* Find the first one.
283	*/
284	uint32_t iFirst = 0;
285	while ( iFirst < cLeaves
286	&& paLeaves[iFirst].uLeaf < uFirst)
287	iFirst++;
288
289	/*
290	* Find the end (last + 1).
291	*/
292	uint32_t iEnd = iFirst;
293	while ( iEnd < cLeaves
294	&& paLeaves[iEnd].uLeaf <= uLast)
295	iEnd++;
296
297	/*
298	* Adjust the array if anything needs removing.
299	*/
300	if (iFirst < iEnd)
301	{
302	if (iEnd < cLeaves)
303	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
304	*pcLeaves = cLeaves -= (iEnd - iFirst);
305	}
306
307	# ifdef VBOX_STRICT
308	cpumCpuIdAssertOrder(paLeaves, *pcLeaves);
309	# endif
310	}
311	#endif /* IN_VBOX_CPU_REPORT */
312
313
314	/**
315	* Gets a CPU ID leaf.
316	*
317	* @returns VBox status code.
318	* @param pVM The cross context VM structure.
319	* @param pLeaf Where to store the found leaf.
320	* @param uLeaf The leaf to locate.
321	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
322	*/
323	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
324	{
325	PCPUMCPUIDLEAF pcLeaf = cpumCpuIdGetLeafInt(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
326	uLeaf, uSubLeaf);
327	if (pcLeaf)
328	{
329	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
330	return VINF_SUCCESS;
331	}
332
333	return VERR_NOT_FOUND;
334	}
335
336
337	/**
338	* Gets all the leaves.
339	*
340	* This only works after the CPUID leaves have been initialized. The interface
341	* is intended for NEM and configuring CPUID leaves for the native hypervisor.
342	*
343	* @returns Pointer to the array of leaves. NULL on failure.
344	* @param pVM The cross context VM structure.
345	* @param pcLeaves Where to return the number of leaves.
346	*/
347	VMMR3_INT_DECL(PCCPUMCPUIDLEAF) CPUMR3CpuIdGetPtr(PVM pVM, uint32_t *pcLeaves)
348	{
349	*pcLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
350	return pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
351	}
352
353
354	/**
355	* Inserts a CPU ID leaf, replacing any existing ones.
356	*
357	* @returns VBox status code.
358	* @param pVM The cross context VM structure.
359	* @param pNewLeaf Pointer to the leaf being inserted.
360	*/
361	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
362	{
363	/*
364	* Validate parameters.
365	*/
366	AssertReturn(pVM, VERR_INVALID_PARAMETER);
367	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
368
369	/*
370	* Disallow replacing CPU ID leaves that this API currently cannot manage.
371	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
372	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
373	*/
374	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
375	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
376	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
377	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
378	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
379	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
380	{
381	return VERR_NOT_SUPPORTED;
382	}
383
384	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
385	}
386
387
388	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
389	/**
390	* Determines the method the CPU uses to handle unknown CPUID leaves.
391	*
392	* @returns VBox status code.
393	* @param penmUnknownMethod Where to return the method.
394	* @param pDefUnknown Where to return default unknown values. This
395	* will be set, even if the resulting method
396	* doesn't actually needs it.
397	*/
398	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
399	{
400	uint32_t uLastStd = ASMCpuId_EAX(0);
401	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
402	if (!RTX86IsValidExtRange(uLastExt))
403	uLastExt = 0x80000000;
404
405	uint32_t auChecks[] =
406	{
407	uLastStd + 1,
408	uLastStd + 5,
409	uLastStd + 8,
410	uLastStd + 32,
411	uLastStd + 251,
412	uLastExt + 1,
413	uLastExt + 8,
414	uLastExt + 15,
415	uLastExt + 63,
416	uLastExt + 255,
417	0x7fbbffcc,
418	0x833f7872,
419	0xefff2353,
420	0x35779456,
421	0x1ef6d33e,
422	};
423
424	static const uint32_t s_auValues[] =
425	{
426	0xa95d2156,
427	0x00000001,
428	0x00000002,
429	0x00000008,
430	0x00000000,
431	0x55773399,
432	0x93401769,
433	0x12039587,
434	};
435
436	/*
437	* Simple method, all zeros.
438	*/
439	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
440	pDefUnknown->uEax = 0;
441	pDefUnknown->uEbx = 0;
442	pDefUnknown->uEcx = 0;
443	pDefUnknown->uEdx = 0;
444
445	/*
446	* Intel has been observed returning the last standard leaf.
447	*/
448	uint32_t auLast[4];
449	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
450
451	uint32_t cChecks = RT_ELEMENTS(auChecks);
452	while (cChecks > 0)
453	{
454	uint32_t auCur[4];
455	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
456	if (memcmp(auCur, auLast, sizeof(auCur)))
457	break;
458	cChecks--;
459	}
460	if (cChecks == 0)
461	{
462	/* Now, what happens when the input changes? Esp. ECX. */
463	uint32_t cTotal = 0;
464	uint32_t cSame = 0;
465	uint32_t cLastWithEcx = 0;
466	uint32_t cNeither = 0;
467	uint32_t cValues = RT_ELEMENTS(s_auValues);
468	while (cValues > 0)
469	{
470	uint32_t uValue = s_auValues[cValues - 1];
471	uint32_t auLastWithEcx[4];
472	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
473	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
474
475	cChecks = RT_ELEMENTS(auChecks);
476	while (cChecks > 0)
477	{
478	uint32_t auCur[4];
479	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
480	if (!memcmp(auCur, auLast, sizeof(auCur)))
481	{
482	cSame++;
483	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
484	cLastWithEcx++;
485	}
486	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
487	cLastWithEcx++;
488	else
489	cNeither++;
490	cTotal++;
491	cChecks--;
492	}
493	cValues--;
494	}
495
496	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
497	if (cSame == cTotal)
498	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
499	else if (cLastWithEcx == cTotal)
500	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
501	else
502	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
503	pDefUnknown->uEax = auLast[0];
504	pDefUnknown->uEbx = auLast[1];
505	pDefUnknown->uEcx = auLast[2];
506	pDefUnknown->uEdx = auLast[3];
507	return VINF_SUCCESS;
508	}
509
510	/*
511	* Unchanged register values?
512	*/
513	cChecks = RT_ELEMENTS(auChecks);
514	while (cChecks > 0)
515	{
516	uint32_t const uLeaf = auChecks[cChecks - 1];
517	uint32_t cValues = RT_ELEMENTS(s_auValues);
518	while (cValues > 0)
519	{
520	uint32_t uValue = s_auValues[cValues - 1];
521	uint32_t auCur[4];
522	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
523	if ( auCur[0] != uLeaf
524	\|\| auCur[1] != uValue
525	\|\| auCur[2] != uValue
526	\|\| auCur[3] != uValue)
527	break;
528	cValues--;
529	}
530	if (cValues != 0)
531	break;
532	cChecks--;
533	}
534	if (cChecks == 0)
535	{
536	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
537	return VINF_SUCCESS;
538	}
539
540	/*
541	* Just go with the simple method.
542	*/
543	return VINF_SUCCESS;
544	}
545	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
546
547
548	/**
549	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
550	*
551	* @returns Read only name string.
552	* @param enmUnknownMethod The method to translate.
553	*/
554	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
555	{
556	switch (enmUnknownMethod)
557	{
558	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
559	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
560	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
561	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
562
563	case CPUMUNKNOWNCPUID_INVALID:
564	case CPUMUNKNOWNCPUID_END:
565	case CPUMUNKNOWNCPUID_32BIT_HACK:
566	break;
567	}
568	return "Invalid-unknown-CPUID-method";
569	}
570
571
572	/*
573	*
574	* Init related code.
575	* Init related code.
576	* Init related code.
577	*
578	*
579	*/
580	#ifndef IN_VBOX_CPU_REPORT
581
582
583	/**
584	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
585	*
586	* This ignores the fSubLeafMask.
587	*
588	* @returns Pointer to the matching leaf, or NULL if not found.
589	* @param pCpum The CPUM instance data.
590	* @param uLeaf The leaf to locate.
591	* @param uSubLeaf The subleaf to locate.
592	*/
593	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
594	{
595	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
596	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
597	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
598	if (iEnd)
599	{
600	uint32_t iBegin = 0;
601	for (;;)
602	{
603	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
604	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
605	if (uNeedle < uCur)
606	{
607	if (i > iBegin)
608	iEnd = i;
609	else
610	break;
611	}
612	else if (uNeedle > uCur)
613	{
614	if (i + 1 < iEnd)
615	iBegin = i + 1;
616	else
617	break;
618	}
619	else
620	return &paLeaves[i];
621	}
622	}
623	return NULL;
624	}
625
626
627	/**
628	* Loads MSR range overrides.
629	*
630	* This must be called before the MSR ranges are moved from the normal heap to
631	* the hyper heap!
632	*
633	* @returns VBox status code (VMSetError called).
634	* @param pVM The cross context VM structure.
635	* @param pMsrNode The CFGM node with the MSR overrides.
636	*/
637	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
638	{
639	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
640	{
641	/*
642	* Assemble a valid MSR range.
643	*/
644	CPUMMSRRANGE MsrRange;
645	MsrRange.offCpumCpu = 0;
646	MsrRange.fReserved = 0;
647
648	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
649	if (RT_FAILURE(rc))
650	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
651
652	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
653	if (RT_FAILURE(rc))
654	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
655	MsrRange.szName, rc);
656
657	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
658	if (RT_FAILURE(rc))
659	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
660	MsrRange.szName, rc);
661
662	char szType[32];
663	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
664	if (RT_FAILURE(rc))
665	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
666	MsrRange.szName, rc);
667	if (!RTStrICmp(szType, "FixedValue"))
668	{
669	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
670	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
671
672	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
673	if (RT_FAILURE(rc))
674	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
675	MsrRange.szName, rc);
676
677	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
678	if (RT_FAILURE(rc))
679	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
680	MsrRange.szName, rc);
681
682	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
683	if (RT_FAILURE(rc))
684	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
685	MsrRange.szName, rc);
686	}
687	else
688	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
689	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
690
691	/*
692	* Insert the range into the table (replaces/splits/shrinks existing
693	* MSR ranges).
694	*/
695	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
696	&MsrRange);
697	if (RT_FAILURE(rc))
698	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
699	}
700
701	return VINF_SUCCESS;
702	}
703
704
705	/**
706	* Loads CPUID leaf overrides.
707	*
708	* This must be called before the CPUID leaves are moved from the normal
709	* heap to the hyper heap!
710	*
711	* @returns VBox status code (VMSetError called).
712	* @param pVM The cross context VM structure.
713	* @param pParentNode The CFGM node with the CPUID leaves.
714	* @param pszLabel How to label the overrides we're loading.
715	*/
716	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
717	{
718	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
719	{
720	/*
721	* Get the leaf and subleaf numbers.
722	*/
723	char szName[128];
724	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
725	if (RT_FAILURE(rc))
726	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
727
728	/* The leaf number is either specified directly or thru the node name. */
729	uint32_t uLeaf;
730	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
731	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
732	{
733	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
734	if (rc != VINF_SUCCESS)
735	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
736	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
737	}
738	else if (RT_FAILURE(rc))
739	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
740	pszLabel, szName, rc);
741
742	uint32_t uSubLeaf;
743	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
744	if (RT_FAILURE(rc))
745	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
746	pszLabel, szName, rc);
747
748	uint32_t fSubLeafMask;
749	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
750	if (RT_FAILURE(rc))
751	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
752	pszLabel, szName, rc);
753
754	/*
755	* Look up the specified leaf, since the output register values
756	* defaults to any existing values. This allows overriding a single
757	* register, without needing to know the other values.
758	*/
759	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
760	CPUMCPUIDLEAF Leaf;
761	if (pLeaf)
762	Leaf = *pLeaf;
763	else
764	RT_ZERO(Leaf);
765	Leaf.uLeaf = uLeaf;
766	Leaf.uSubLeaf = uSubLeaf;
767	Leaf.fSubLeafMask = fSubLeafMask;
768
769	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
770	if (RT_FAILURE(rc))
771	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
772	pszLabel, szName, rc);
773	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
774	if (RT_FAILURE(rc))
775	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
776	pszLabel, szName, rc);
777	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
778	if (RT_FAILURE(rc))
779	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
780	pszLabel, szName, rc);
781	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
782	if (RT_FAILURE(rc))
783	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
784	pszLabel, szName, rc);
785
786	/*
787	* Insert the leaf into the table (replaces existing ones).
788	*/
789	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
790	&Leaf);
791	if (RT_FAILURE(rc))
792	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
793	}
794
795	return VINF_SUCCESS;
796	}
797
798
799
800	/**
801	* Fetches overrides for a CPUID leaf.
802	*
803	* @returns VBox status code.
804	* @param pLeaf The leaf to load the overrides into.
805	* @param pCfgNode The CFGM node containing the overrides
806	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
807	* @param iLeaf The CPUID leaf number.
808	*/
809	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
810	{
811	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
812	if (pLeafNode)
813	{
814	uint32_t u32;
815	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
816	if (RT_SUCCESS(rc))
817	pLeaf->uEax = u32;
818	else
819	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
820
821	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
822	if (RT_SUCCESS(rc))
823	pLeaf->uEbx = u32;
824	else
825	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
826
827	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
828	if (RT_SUCCESS(rc))
829	pLeaf->uEcx = u32;
830	else
831	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
832
833	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
834	if (RT_SUCCESS(rc))
835	pLeaf->uEdx = u32;
836	else
837	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
838
839	}
840	return VINF_SUCCESS;
841	}
842
843
844	/**
845	* Load the overrides for a set of CPUID leaves.
846	*
847	* @returns VBox status code.
848	* @param paLeaves The leaf array.
849	* @param cLeaves The number of leaves.
850	* @param uStart The start leaf number.
851	* @param pCfgNode The CFGM node containing the overrides
852	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
853	*/
854	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
855	{
856	for (uint32_t i = 0; i < cLeaves; i++)
857	{
858	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
859	if (RT_FAILURE(rc))
860	return rc;
861	}
862
863	return VINF_SUCCESS;
864	}
865
866
867	/**
868	* Installs the CPUID leaves and explods the data into structures like
869	* GuestFeatures and CPUMCTX::aoffXState.
870	*
871	* @returns VBox status code.
872	* @param pVM The cross context VM structure.
873	* @param pCpum The CPUM part of @a VM.
874	* @param paLeaves The leaves. These will be copied (but not freed).
875	* @param cLeaves The number of leaves.
876	* @param pMsrs The MSRs.
877	*/
878	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
879	{
880	# ifdef VBOX_STRICT
881	cpumCpuIdAssertOrder(paLeaves, cLeaves);
882	# endif
883
884	/*
885	* Install the CPUID information.
886	*/
887	AssertLogRelMsgReturn(cLeaves <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves),
888	("cLeaves=%u - max %u\n", cLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves)),
889	VERR_CPUM_IPE_1); /** @todo better status! */
890	if (paLeaves != pCpum->GuestInfo.aCpuIdLeaves)
891	memcpy(pCpum->GuestInfo.aCpuIdLeaves, paLeaves, cLeaves * sizeof(paLeaves[0]));
892	pCpum->GuestInfo.paCpuIdLeavesR3 = pCpum->GuestInfo.aCpuIdLeaves;
893	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
894
895	/*
896	* Update the default CPUID leaf if necessary.
897	*/
898	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
899	{
900	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
901	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
902	{
903	/* We don't use CPUID(0).eax here because of the NT hack that only
904	changes that value without actually removing any leaves. */
905	uint32_t i = 0;
906	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
907	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
908	{
909	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
910	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
911	i++;
912	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
913	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
914	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
915	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
916	}
917	break;
918	}
919	default:
920	break;
921	}
922
923	/*
924	* Explode the guest CPU features.
925	*/
926	int rc = cpumCpuIdExplodeFeaturesX86(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
927	&pCpum->GuestFeatures);
928	AssertLogRelRCReturn(rc, rc);
929
930	/*
931	* Adjust the scalable bus frequency according to the CPUID information
932	* we're now using.
933	*/
934	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
935	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
936	? UINT64_C(100000000) /* 100MHz */
937	: UINT64_C(133333333); /* 133MHz */
938
939	/*
940	* Populate the legacy arrays. Currently used for everything, later only
941	* for patch manager.
942	*/
943	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
944	{
945	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
946	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
947	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
948	};
949	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
950	{
951	uint32_t cLeft = aOldRanges[i].cCpuIds;
952	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
953	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
954	while (cLeft-- > 0)
955	{
956	uLeaf--;
957	pLegacyLeaf--;
958
959	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
960	if (pLeaf)
961	{
962	pLegacyLeaf->uEax = pLeaf->uEax;
963	pLegacyLeaf->uEbx = pLeaf->uEbx;
964	pLegacyLeaf->uEcx = pLeaf->uEcx;
965	pLegacyLeaf->uEdx = pLeaf->uEdx;
966	}
967	else
968	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
969	}
970	}
971
972	/*
973	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
974	*/
975	PVMCPU pVCpu0 = pVM->apCpusR3[0];
976	AssertCompile(sizeof(pVCpu0->cpum.s.Guest.abXState) == CPUM_MAX_XSAVE_AREA_SIZE);
977	memset(&pVCpu0->cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVCpu0->cpum.s.Guest.aoffXState));
978	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
979	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
980	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
981	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
982	{
983	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
984	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
985	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
986	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
987	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
988	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
989	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
990	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
991	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
992	pCpum->GuestFeatures.cbMaxExtendedState),
993	VERR_CPUM_IPE_1);
994	pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
995	}
996
997	/* Copy the CPU #0 data to the other CPUs. */
998	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
999	{
1000	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1001	memcpy(&pVCpu->cpum.s.Guest.aoffXState[0], &pVCpu0->cpum.s.Guest.aoffXState[0], sizeof(pVCpu0->cpum.s.Guest.aoffXState));
1002	}
1003
1004	return VINF_SUCCESS;
1005	}
1006
1007
1008	/** @name Instruction Set Extension Options
1009	* @{ */
1010	/** Configuration option type (extended boolean, really). */
1011	typedef uint8_t CPUMISAEXTCFG;
1012	/** Always disable the extension. */
1013	#define CPUMISAEXTCFG_DISABLED false
1014	/** Enable the extension if it's supported by the host CPU. */
1015	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
1016	/** Enable the extension if it's supported by the host CPU or when on ARM64. */
1017	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1018	# define CPUMISAEXTCFG_ENABLED_SUPPORTED_OR_NOT_AMD64 CPUMISAEXTCFG_ENABLED_SUPPORTED
1019	#else
1020	# define CPUMISAEXTCFG_ENABLED_SUPPORTED_OR_NOT_AMD64 CPUMISAEXTCFG_ENABLED_ALWAYS
1021	#endif
1022	/** Enable the extension if it's supported by the host CPU, but don't let
1023	* the portable CPUID feature disable it. */
1024	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
1025	/** Always enable the extension. */
1026	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
1027	/** @} */
1028
1029	/**
1030	* CPUID Configuration (from CFGM).
1031	*
1032	* @remarks The members aren't document since we would only be duplicating the
1033	* \@cfgm entries in cpumR3CpuIdReadConfig.
1034	*/
1035	typedef struct CPUMCPUIDCONFIG
1036	{
1037	bool fNt4LeafLimit;
1038	bool fInvariantTsc;
1039	bool fInvariantApic;
1040	bool fForceVme;
1041	bool fNestedHWVirt;
1042
1043	CPUMISAEXTCFG enmCmpXchg16b;
1044	CPUMISAEXTCFG enmMonitor;
1045	CPUMISAEXTCFG enmMWaitExtensions;
1046	CPUMISAEXTCFG enmSse41;
1047	CPUMISAEXTCFG enmSse42;
1048	CPUMISAEXTCFG enmAvx;
1049	CPUMISAEXTCFG enmAvx2;
1050	CPUMISAEXTCFG enmXSave;
1051	CPUMISAEXTCFG enmAesNi;
1052	CPUMISAEXTCFG enmPClMul;
1053	CPUMISAEXTCFG enmPopCnt;
1054	CPUMISAEXTCFG enmMovBe;
1055	CPUMISAEXTCFG enmRdRand;
1056	CPUMISAEXTCFG enmRdSeed;
1057	CPUMISAEXTCFG enmSha;
1058	CPUMISAEXTCFG enmAdx;
1059	CPUMISAEXTCFG enmCLFlushOpt;
1060	CPUMISAEXTCFG enmFsGsBase;
1061	CPUMISAEXTCFG enmPcid;
1062	CPUMISAEXTCFG enmInvpcid;
1063	CPUMISAEXTCFG enmFlushCmdMsr;
1064	CPUMISAEXTCFG enmMdsClear;
1065	CPUMISAEXTCFG enmArchCapMsr;
1066	CPUMISAEXTCFG enmFma;
1067	CPUMISAEXTCFG enmF16c;
1068
1069	CPUMISAEXTCFG enmAbm;
1070	CPUMISAEXTCFG enmSse4A;
1071	CPUMISAEXTCFG enmMisAlnSse;
1072	CPUMISAEXTCFG enm3dNowPrf;
1073	CPUMISAEXTCFG enmAmdExtMmx;
1074
1075	uint32_t uMaxStdLeaf;
1076	uint32_t uMaxExtLeaf;
1077	uint32_t uMaxCentaurLeaf;
1078	uint32_t uMaxIntelFamilyModelStep;
1079	char szCpuName[128];
1080	} CPUMCPUIDCONFIG;
1081	/** Pointer to CPUID config (from CFGM). */
1082	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
1083
1084
1085	/**
1086	* Mini CPU selection support for making Mac OS X happy.
1087	*
1088	* Executes the /CPUM/MaxIntelFamilyModelStep config.
1089	*
1090	* @param pCpum The CPUM instance data.
1091	* @param pConfig The CPUID configuration we've read from CFGM.
1092	*/
1093	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1094	{
1095	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1096	{
1097	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1098	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(RTX86GetCpuStepping(pStdFeatureLeaf->uEax),
1099	RTX86GetCpuModelIntel(pStdFeatureLeaf->uEax),
1100	RTX86GetCpuFamily(pStdFeatureLeaf->uEax),
1101	0);
1102	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
1103	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
1104	{
1105	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
1106	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
1107	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
1108	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
1109	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
1110	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
1111	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
1112	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
1113	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
1114	pStdFeatureLeaf->uEax = uNew;
1115	}
1116	}
1117	}
1118
1119
1120
1121	/**
1122	* Limit it the number of entries, zapping the remainder.
1123	*
1124	* The limits are masking off stuff about power saving and similar, this
1125	* is perhaps a bit crudely done as there is probably some relatively harmless
1126	* info too in these leaves (like words about having a constant TSC).
1127	*
1128	* @param pCpum The CPUM instance data.
1129	* @param pConfig The CPUID configuration we've read from CFGM.
1130	*/
1131	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1132	{
1133	/*
1134	* Standard leaves.
1135	*/
1136	uint32_t uSubLeaf = 0;
1137	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
1138	if (pCurLeaf)
1139	{
1140	uint32_t uLimit = pCurLeaf->uEax;
1141	if (uLimit <= UINT32_C(0x000fffff))
1142	{
1143	if (uLimit > pConfig->uMaxStdLeaf)
1144	{
1145	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
1146	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1147	uLimit + 1, UINT32_C(0x000fffff));
1148	}
1149
1150	/* NT4 hack, no zapping of extra leaves here. */
1151	if (pConfig->fNt4LeafLimit && uLimit > 3)
1152	pCurLeaf->uEax = uLimit = 3;
1153
1154	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
1155	pCurLeaf->uEax = uLimit;
1156	}
1157	else
1158	{
1159	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
1160	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1161	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
1162	}
1163	}
1164
1165	/*
1166	* Extended leaves.
1167	*/
1168	uSubLeaf = 0;
1169	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
1170	if (pCurLeaf)
1171	{
1172	uint32_t uLimit = pCurLeaf->uEax;
1173	if ( uLimit >= UINT32_C(0x80000000)
1174	&& uLimit <= UINT32_C(0x800fffff))
1175	{
1176	if (uLimit > pConfig->uMaxExtLeaf)
1177	{
1178	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
1179	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1180	uLimit + 1, UINT32_C(0x800fffff));
1181	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
1182	pCurLeaf->uEax = uLimit;
1183	}
1184	}
1185	else
1186	{
1187	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
1188	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1189	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
1190	}
1191	}
1192
1193	/*
1194	* Centaur leaves (VIA).
1195	*/
1196	uSubLeaf = 0;
1197	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
1198	if (pCurLeaf)
1199	{
1200	uint32_t uLimit = pCurLeaf->uEax;
1201	if ( uLimit >= UINT32_C(0xc0000000)
1202	&& uLimit <= UINT32_C(0xc00fffff))
1203	{
1204	if (uLimit > pConfig->uMaxCentaurLeaf)
1205	{
1206	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
1207	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1208	uLimit + 1, UINT32_C(0xcfffffff));
1209	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
1210	pCurLeaf->uEax = uLimit;
1211	}
1212	}
1213	else
1214	{
1215	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
1216	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1217	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
1218	}
1219	}
1220	}
1221
1222
1223	/**
1224	* Clears a CPUID leaf and all sub-leaves (to zero).
1225	*
1226	* @param pCpum The CPUM instance data.
1227	* @param uLeaf The leaf to clear.
1228	*/
1229	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
1230	{
1231	uint32_t uSubLeaf = 0;
1232	PCPUMCPUIDLEAF pCurLeaf;
1233	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
1234	{
1235	pCurLeaf->uEax = 0;
1236	pCurLeaf->uEbx = 0;
1237	pCurLeaf->uEcx = 0;
1238	pCurLeaf->uEdx = 0;
1239	uSubLeaf++;
1240	}
1241	}
1242
1243
1244	/**
1245	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
1246	* the given leaf.
1247	*
1248	* @returns pLeaf.
1249	* @param pCpum The CPUM instance data.
1250	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
1251	*/
1252	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
1253	{
1254	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
1255	if (pLeaf->fSubLeafMask != 0)
1256	{
1257	/*
1258	* Figure out how many sub-leaves in need of removal (we'll keep the first).
1259	* Log everything while we're at it.
1260	*/
1261	LogRel(("CPUM:\n"
1262	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
1263	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
1264	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
1265	for (;;)
1266	{
1267	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
1268	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
1269	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
1270	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
1271	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
1272	break;
1273	pSubLeaf++;
1274	}
1275	LogRel(("CPUM:\n"));
1276
1277	/*
1278	* Remove the offending sub-leaves.
1279	*/
1280	if (pSubLeaf != pLeaf)
1281	{
1282	if (pSubLeaf != pLast)
1283	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
1284	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
1285	}
1286
1287	/*
1288	* Convert the first sub-leaf into a single leaf.
1289	*/
1290	pLeaf->uSubLeaf = 0;
1291	pLeaf->fSubLeafMask = 0;
1292	}
1293	return pLeaf;
1294	}
1295
1296
1297	/**
1298	* Sanitizes and adjust the CPUID leaves.
1299	*
1300	* Drop features that aren't virtualized (or virtualizable). Adjust information
1301	* and capabilities to fit the virtualized hardware. Remove information the
1302	* guest shouldn't have (because it's wrong in the virtual world or because it
1303	* gives away host details) or that we don't have documentation for and no idea
1304	* what means.
1305	*
1306	* @returns VBox status code.
1307	* @param pVM The cross context VM structure (for cCpus).
1308	* @param pCpum The CPUM instance data.
1309	* @param pConfig The CPUID configuration we've read from CFGM.
1310	*/
1311	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1312	{
1313	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
1314	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
1315	{ \
1316	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
1317	(a_pLeafReg) &= ~(uint32_t)(fMask); \
1318	}
1319	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
1320	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
1321	{ \
1322	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
1323	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
1324	}
1325	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
1326	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
1327	&& ((a_pLeafReg) & (fBitMask)) \
1328	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
1329	{ \
1330	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
1331	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
1332	}
1333	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
1334
1335	/* The CPUID entries we start with here isn't necessarily the ones of the host, so we
1336	must consult HostFeatures when processing CPUMISAEXTCFG variables. */
1337	PCCPUMFEATURES pHstFeat = &pCpum->HostFeatures;
1338	#define PASSTHRU_FEATURE(enmConfig, fHostFeature, fConst) \
1339	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) ? (fConst) : 0)
1340	#define PASSTHRU_FEATURE_EX(enmConfig, fHostFeature, fAndExpr, fConst) \
1341	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) && (fAndExpr) ? (fConst) : 0)
1342	#define PASSTHRU_FEATURE_TODO(enmConfig, fConst) ((enmConfig) ? (fConst) : 0)
1343
1344	/* Cpuid 1:
1345	* EAX: CPU model, family and stepping.
1346	*
1347	* ECX + EDX: Supported features. Only report features we can support.
1348	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1349	* options may require adjusting (i.e. stripping what was enabled).
1350	*
1351	* EBX: Branding, CLFLUSH line size, logical processors per package and
1352	* initial APIC ID.
1353	*/
1354	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
1355	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
1356	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
1357
1358	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
1359	\| X86_CPUID_FEATURE_EDX_VME
1360	\| X86_CPUID_FEATURE_EDX_DE
1361	\| X86_CPUID_FEATURE_EDX_PSE
1362	\| X86_CPUID_FEATURE_EDX_TSC
1363	\| X86_CPUID_FEATURE_EDX_MSR
1364	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
1365	\| X86_CPUID_FEATURE_EDX_MCE
1366	\| X86_CPUID_FEATURE_EDX_CX8
1367	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
1368	//\| RT_BIT_32(10) - not defined
1369	\| X86_CPUID_FEATURE_EDX_SEP
1370	\| X86_CPUID_FEATURE_EDX_MTRR
1371	\| X86_CPUID_FEATURE_EDX_PGE
1372	\| X86_CPUID_FEATURE_EDX_MCA
1373	\| X86_CPUID_FEATURE_EDX_CMOV
1374	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
1375	\| X86_CPUID_FEATURE_EDX_PSE36
1376	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
1377	\| X86_CPUID_FEATURE_EDX_CLFSH
1378	//\| RT_BIT_32(20) - not defined
1379	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
1380	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
1381	\| X86_CPUID_FEATURE_EDX_MMX
1382	\| X86_CPUID_FEATURE_EDX_FXSR
1383	\| X86_CPUID_FEATURE_EDX_SSE
1384	\| X86_CPUID_FEATURE_EDX_SSE2
1385	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
1386	\| X86_CPUID_FEATURE_EDX_HTT
1387	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
1388	//\| RT_BIT_32(30) - not defined
1389	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
1390	;
1391	pStdFeatureLeaf->uEcx &= X86_CPUID_FEATURE_ECX_SSE3
1392	\| PASSTHRU_FEATURE_TODO(pConfig->enmPClMul, X86_CPUID_FEATURE_ECX_PCLMUL)
1393	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
1394	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
1395	\| PASSTHRU_FEATURE_EX(pConfig->enmMonitor, pHstFeat->fMonitorMWait, pVM->cCpus == 1, X86_CPUID_FEATURE_ECX_MONITOR)
1396	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
1397	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
1398	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
1399	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
1400	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
1401	\| X86_CPUID_FEATURE_ECX_SSSE3
1402	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
1403	\| PASSTHRU_FEATURE(pConfig->enmFma, pHstFeat->fFma, X86_CPUID_FEATURE_ECX_FMA)
1404	\| PASSTHRU_FEATURE(pConfig->enmCmpXchg16b, pHstFeat->fCmpXchg16b, X86_CPUID_FEATURE_ECX_CX16)
1405	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
1406	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1407	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
1408	\| PASSTHRU_FEATURE(pConfig->enmPcid, pHstFeat->fPcid, X86_CPUID_FEATURE_ECX_PCID)
1409	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
1410	\| PASSTHRU_FEATURE(pConfig->enmSse41, pHstFeat->fSse41, X86_CPUID_FEATURE_ECX_SSE4_1)
1411	\| PASSTHRU_FEATURE(pConfig->enmSse42, pHstFeat->fSse42, X86_CPUID_FEATURE_ECX_SSE4_2)
1412	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
1413	\| PASSTHRU_FEATURE(pConfig->enmMovBe, pHstFeat->fMovBe, X86_CPUID_FEATURE_ECX_MOVBE)
1414	\| PASSTHRU_FEATURE(pConfig->enmPopCnt, pHstFeat->fPopCnt, X86_CPUID_FEATURE_ECX_POPCNT)
1415	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
1416	\| PASSTHRU_FEATURE_TODO(pConfig->enmAesNi, X86_CPUID_FEATURE_ECX_AES)
1417	\| PASSTHRU_FEATURE(pConfig->enmXSave, pHstFeat->fXSaveRstor, X86_CPUID_FEATURE_ECX_XSAVE)
1418	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
1419	\| PASSTHRU_FEATURE(pConfig->enmAvx, pHstFeat->fAvx, X86_CPUID_FEATURE_ECX_AVX)
1420	\| PASSTHRU_FEATURE(pConfig->enmF16c, pHstFeat->fF16c, X86_CPUID_FEATURE_ECX_F16C)
1421	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdRand, X86_CPUID_FEATURE_ECX_RDRAND)
1422	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
1423	;
1424
1425	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
1426	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
1427	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
1428	{
1429	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
1430	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
1431	}
1432
1433	if (pCpum->u8PortableCpuIdLevel > 0)
1434	{
1435	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
1436	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
1437	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
1438	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
1439	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
1440	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
1441	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
1442	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
1443	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
1444	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
1445	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
1446	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
1447	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
1448	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
1449	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
1450	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
1451	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
1452	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
1453	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
1454	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
1455
1456	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP ///??
1457	\| X86_CPUID_FEATURE_EDX_PSN
1458	\| X86_CPUID_FEATURE_EDX_DS
1459	\| X86_CPUID_FEATURE_EDX_ACPI
1460	\| X86_CPUID_FEATURE_EDX_SS
1461	\| X86_CPUID_FEATURE_EDX_TM
1462	\| X86_CPUID_FEATURE_EDX_PBE
1463	)));
1464	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
1465	\| X86_CPUID_FEATURE_ECX_CPLDS
1466	\| X86_CPUID_FEATURE_ECX_AES
1467	\| X86_CPUID_FEATURE_ECX_VMX
1468	\| X86_CPUID_FEATURE_ECX_SMX
1469	\| X86_CPUID_FEATURE_ECX_EST
1470	\| X86_CPUID_FEATURE_ECX_TM2
1471	\| X86_CPUID_FEATURE_ECX_CNTXID
1472	\| X86_CPUID_FEATURE_ECX_FMA
1473	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1474	\| X86_CPUID_FEATURE_ECX_PDCM
1475	\| X86_CPUID_FEATURE_ECX_DCA
1476	\| X86_CPUID_FEATURE_ECX_OSXSAVE
1477	)));
1478	}
1479
1480	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
1481	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
1482
1483	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
1484	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
1485	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
1486	*/
1487	#ifdef VBOX_WITH_MULTI_CORE
1488	if (pVM->cCpus > 1)
1489	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
1490	#endif
1491	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
1492	{
1493	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
1494	core times the number of CPU cores per processor */
1495	#ifdef VBOX_WITH_MULTI_CORE
1496	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
1497	#else
1498	/* Single logical processor in a package. */
1499	pStdFeatureLeaf->uEbx \|= (1 << 16);
1500	#endif
1501	}
1502
1503	uint32_t uMicrocodeRev;
1504	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
1505	if (RT_SUCCESS(rc))
1506	{
1507	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
1508	}
1509	else
1510	{
1511	uMicrocodeRev = 0;
1512	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
1513	}
1514
1515	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
1516	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
1517	*/
1518	if ( ( pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen
1519	/** @todo The following ASSUMES that Hygon uses the same version numbering
1520	* as AMD and that they shipped buggy firmware. */
1521	\|\| pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Hygon_Dhyana)
1522	&& uMicrocodeRev < 0x8001126
1523	&& !pConfig->fForceVme)
1524	{
1525	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
1526	LogRel(("CPUM: Zen VME workaround engaged\n"));
1527	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
1528	}
1529
1530	/* Force standard feature bits. */
1531	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
1532	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
1533	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
1534	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
1535	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
1536	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
1537	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1538	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
1539	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1540	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
1541	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
1542	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
1543	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
1544	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
1545	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
1546	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
1547	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
1548	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
1549	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1550	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
1551	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
1552	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
1553
1554	pStdFeatureLeaf = NULL; /* Must refetch! */
1555
1556	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
1557	* AMD:
1558	* EAX: CPU model, family and stepping.
1559	*
1560	* ECX + EDX: Supported features. Only report features we can support.
1561	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1562	* options may require adjusting (i.e. stripping what was enabled).
1563	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
1564	*
1565	* EBX: Branding ID and package type (or reserved).
1566	*
1567	* Intel and probably most others:
1568	* EAX: 0
1569	* EBX: 0
1570	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
1571	*/
1572	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
1573	if (pExtFeatureLeaf)
1574	{
1575	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
1576
1577	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
1578	\| X86_CPUID_AMD_FEATURE_EDX_VME
1579	\| X86_CPUID_AMD_FEATURE_EDX_DE
1580	\| X86_CPUID_AMD_FEATURE_EDX_PSE
1581	\| X86_CPUID_AMD_FEATURE_EDX_TSC
1582	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
1583	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
1584	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
1585	\| X86_CPUID_AMD_FEATURE_EDX_CX8
1586	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
1587	//\| RT_BIT_32(10) - reserved
1588	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1589	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
1590	\| X86_CPUID_AMD_FEATURE_EDX_PGE
1591	\| X86_CPUID_AMD_FEATURE_EDX_MCA
1592	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
1593	\| X86_CPUID_AMD_FEATURE_EDX_PAT
1594	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
1595	//\| RT_BIT_32(18) - reserved
1596	//\| RT_BIT_32(19) - reserved
1597	\| X86_CPUID_EXT_FEATURE_EDX_NX
1598	//\| RT_BIT_32(21) - reserved
1599	\| PASSTHRU_FEATURE(pConfig->enmAmdExtMmx, pHstFeat->fAmdMmxExts, X86_CPUID_AMD_FEATURE_EDX_AXMMX)
1600	\| X86_CPUID_AMD_FEATURE_EDX_MMX
1601	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
1602	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
1603	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1604	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
1605	//\| RT_BIT_32(28) - reserved
1606	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
1607	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
1608	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
1609	;
1610	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
1611	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
1612	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
1613	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1614	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
1615	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
1616	\| PASSTHRU_FEATURE(pConfig->enmAbm, pHstFeat->fAbm, X86_CPUID_AMD_FEATURE_ECX_ABM)
1617	\| PASSTHRU_FEATURE_TODO(pConfig->enmSse4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A)
1618	\| PASSTHRU_FEATURE_TODO(pConfig->enmMisAlnSse, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE)
1619	\| PASSTHRU_FEATURE(pConfig->enm3dNowPrf, pHstFeat->f3DNowPrefetch, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1620	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
1621	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
1622	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
1623	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1624	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
1625	//\| RT_BIT_32(14) - reserved
1626	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
1627	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
1628	//\| RT_BIT_32(17) - reserved
1629	//\| RT_BIT_32(18) - reserved
1630	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
1631	//\| RT_BIT_32(20) - reserved
1632	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
1633	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
1634	//\| RT_BIT_32(23) - reserved
1635	//\| RT_BIT_32(24) - reserved
1636	//\| RT_BIT_32(25) - reserved
1637	//\| RT_BIT_32(26) - reserved
1638	//\| RT_BIT_32(27) - reserved
1639	//\| RT_BIT_32(28) - reserved
1640	//\| RT_BIT_32(29) - reserved
1641	//\| RT_BIT_32(30) - reserved
1642	//\| RT_BIT_32(31) - reserved
1643	;
1644	#ifdef VBOX_WITH_MULTI_CORE
1645	if ( pVM->cCpus > 1
1646	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
1647	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
1648	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
1649	#endif
1650
1651	if (pCpum->u8PortableCpuIdLevel > 0)
1652	{
1653	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1654	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
1655	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
1656	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
1657	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
1658	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
1659	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
1660	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
1661	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
1662	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
1663	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1664	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1665	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1666	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1667	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1668	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1669
1670	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
1671	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1672	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
1673	\| X86_CPUID_AMD_FEATURE_ECX_IBS
1674	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1675	\| X86_CPUID_AMD_FEATURE_ECX_WDT
1676	\| X86_CPUID_AMD_FEATURE_ECX_LWP
1677	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
1678	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
1679	\| UINT32_C(0xff964000)
1680	)));
1681	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
1682	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1683	\| RT_BIT(18)
1684	\| RT_BIT(19)
1685	\| RT_BIT(21)
1686	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
1687	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1688	\| RT_BIT(28)
1689	)));
1690	}
1691
1692	/* Force extended feature bits. */
1693	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
1694	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
1695	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
1696	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
1697	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
1698	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
1699	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
1700	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
1701	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1702	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
1703	}
1704	pExtFeatureLeaf = NULL; /* Must refetch! */
1705
1706
1707	/* Cpuid 2:
1708	* Intel: (Nondeterministic) Cache and TLB information
1709	* AMD: Reserved
1710	* VIA: Reserved
1711	* Safe to expose.
1712	*/
1713	uint32_t uSubLeaf = 0;
1714	PCPUMCPUIDLEAF pCurLeaf;
1715	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
1716	{
1717	if ((pCurLeaf->uEax & 0xff) > 1)
1718	{
1719	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
1720	pCurLeaf->uEax &= UINT32_C(0xffffff01);
1721	}
1722	uSubLeaf++;
1723	}
1724
1725	/* Cpuid 3:
1726	* Intel: EAX, EBX - reserved (transmeta uses these)
1727	* ECX, EDX - Processor Serial Number if available, otherwise reserved
1728	* AMD: Reserved
1729	* VIA: Reserved
1730	* Safe to expose
1731	*/
1732	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1733	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
1734	{
1735	uSubLeaf = 0;
1736	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
1737	{
1738	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1739	if (pCpum->u8PortableCpuIdLevel > 0)
1740	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1741	uSubLeaf++;
1742	}
1743	}
1744
1745	/* Cpuid 4 + ECX:
1746	* Intel: Deterministic Cache Parameters Leaf.
1747	* AMD: Reserved
1748	* VIA: Reserved
1749	* Safe to expose, except for EAX:
1750	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1751	* Bits 31-26: Maximum number of processor cores in this physical package**
1752	* Note: These SMP values are constant regardless of ECX
1753	*/
1754	uSubLeaf = 0;
1755	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
1756	{
1757	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
1758	#ifdef VBOX_WITH_MULTI_CORE
1759	if ( pVM->cCpus > 1
1760	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1761	{
1762	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1763	/* One logical processor with possibly multiple cores. */
1764	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1765	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
1766	}
1767	#endif
1768	uSubLeaf++;
1769	}
1770
1771	/* Cpuid 5: Monitor/mwait Leaf
1772	* Intel: ECX, EDX - reserved
1773	* EAX, EBX - Smallest and largest monitor line size
1774	* AMD: EDX - reserved
1775	* EAX, EBX - Smallest and largest monitor line size
1776	* ECX - extensions (ignored for now)
1777	* VIA: Reserved
1778	* Safe to expose
1779	*/
1780	uSubLeaf = 0;
1781	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
1782	{
1783	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1784	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
1785	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1786
1787	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1788	if (pConfig->enmMWaitExtensions)
1789	{
1790	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1791	/** @todo for now we just expose host's MWAIT C-states, although conceptually
1792	it shall be part of our power management virtualization model */
1793	#if 0
1794	/* MWAIT sub C-states */
1795	pCurLeaf->uEdx =
1796	(0 << 0) /* 0 in C0 */ \|
1797	(2 << 4) /* 2 in C1 */ \|
1798	(2 << 8) /* 2 in C2 */ \|
1799	(2 << 12) /* 2 in C3 */ \|
1800	(0 << 16) /* 0 in C4 */
1801	;
1802	#endif
1803	}
1804	else
1805	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1806	uSubLeaf++;
1807	}
1808
1809	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
1810	* Intel: Various thermal and power management related stuff.
1811	* AMD: EBX, EDX - reserved.
1812	* EAX - Bit two is ARAT, indicating that APIC timers run at a constant
1813	* rate regardless of processor P-states. Same as Intel.
1814	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
1815	* present. Same as Intel.
1816	* VIA: ??
1817	*
1818	* We clear everything except for the ARAT bit which is important for Windows 11.
1819	*/
1820	uSubLeaf = 0;
1821	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 6, uSubLeaf)) != NULL)
1822	{
1823	pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1824	pCurLeaf->uEax &= 0
1825	\| X86_CPUID_POWER_EAX_ARAT
1826	;
1827
1828	/* Since we emulate the APIC timers, we can normally set the ARAT bit
1829	* regardless of whether the host CPU sets it or not. Intel sets the ARAT
1830	* bit circa since the Westmere generation, AMD probably only since Zen.
1831	* See @bugref{10567}.
1832	*/
1833	if (pConfig->fInvariantApic)
1834	pCurLeaf->uEax \|= X86_CPUID_POWER_EAX_ARAT;
1835
1836	uSubLeaf++;
1837	}
1838
1839	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
1840	* EAX: Number of sub leaves.
1841	* EBX+ECX+EDX: Feature flags
1842	*
1843	* We only have documentation for one sub-leaf, so clear all other (no need
1844	* to remove them as such, just set them to zero).
1845	*
1846	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1847	* options may require adjusting (i.e. stripping what was enabled).
1848	*/
1849	uSubLeaf = 0;
1850	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
1851	{
1852	switch (uSubLeaf)
1853	{
1854	case 0:
1855	{
1856	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
1857	pCurLeaf->uEbx &= 0
1858	\| PASSTHRU_FEATURE(pConfig->enmFsGsBase, pHstFeat->fFsGsBase, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE)
1859	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
1860	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
1861	\| X86_CPUID_STEXT_FEATURE_EBX_BMI1
1862	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
1863	\| PASSTHRU_FEATURE(pConfig->enmAvx2, pHstFeat->fAvx2, X86_CPUID_STEXT_FEATURE_EBX_AVX2)
1864	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
1865	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
1866	\| X86_CPUID_STEXT_FEATURE_EBX_BMI2
1867	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
1868	\| PASSTHRU_FEATURE(pConfig->enmInvpcid, pHstFeat->fInvpcid, X86_CPUID_STEXT_FEATURE_EBX_INVPCID)
1869	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
1870	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
1871	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
1872	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
1873	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
1874	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
1875	//\| RT_BIT(17) - reserved
1876	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdSeed, X86_CPUID_STEXT_FEATURE_EBX_RDSEED)
1877	\| PASSTHRU_FEATURE(pConfig->enmAdx, pHstFeat->fAdx, X86_CPUID_STEXT_FEATURE_EBX_ADX)
1878	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
1879	//\| RT_BIT(21) - reserved
1880	//\| RT_BIT(22) - reserved
1881	\| PASSTHRU_FEATURE(pConfig->enmCLFlushOpt, pHstFeat->fClFlushOpt, X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT)
1882	//\| RT_BIT(24) - reserved
1883	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
1884	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
1885	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
1886	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
1887	\| PASSTHRU_FEATURE(pConfig->enmSha, pHstFeat->fSha, X86_CPUID_STEXT_FEATURE_EBX_SHA)
1888	//\| RT_BIT(30) - reserved
1889	//\| RT_BIT(31) - reserved
1890	;
1891	pCurLeaf->uEcx &= 0
1892	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
1893	;
1894	pCurLeaf->uEdx &= 0
1895	\| PASSTHRU_FEATURE(pConfig->enmMdsClear, pHstFeat->fMdsClear, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR)
1896	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
1897	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
1898	\| PASSTHRU_FEATURE(pConfig->enmFlushCmdMsr, pHstFeat->fFlushCmd, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD)
1899	\| PASSTHRU_FEATURE(pConfig->enmArchCapMsr, pHstFeat->fArchCap, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
1900	;
1901
1902	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
1903	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
1904	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
1905	{
1906	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
1907	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
1908	}
1909
1910	if (pCpum->u8PortableCpuIdLevel > 0)
1911	{
1912	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
1913	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
1914	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
1915	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
1916	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
1917	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
1918	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1919	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
1920	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, ADX, X86_CPUID_STEXT_FEATURE_EBX_ADX, pConfig->enmAdx);
1921	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
1922	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
1923	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
1924	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
1925	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
1926	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA, pConfig->enmSha);
1927	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
1928	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
1929	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
1930	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
1931	}
1932
1933	/* Dependencies. */
1934	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
1935	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
1936
1937	/* Force standard feature bits. */
1938	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
1939	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
1940	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1941	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
1942	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
1943	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
1944	if (pConfig->enmAdx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1945	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_ADX;
1946	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
1947	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
1948	if (pConfig->enmSha == CPUMISAEXTCFG_ENABLED_ALWAYS)
1949	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_SHA;
1950	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
1951	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
1952	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
1953	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
1954	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
1955	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
1956	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
1957	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
1958	break;
1959	}
1960
1961	default:
1962	/* Invalid index, all values are zero. */
1963	pCurLeaf->uEax = 0;
1964	pCurLeaf->uEbx = 0;
1965	pCurLeaf->uEcx = 0;
1966	pCurLeaf->uEdx = 0;
1967	break;
1968	}
1969	uSubLeaf++;
1970	}
1971
1972	/* Cpuid 8: Marked as reserved by Intel and AMD.
1973	* We zero this since we don't know what it may have been used for.
1974	*/
1975	cpumR3CpuIdZeroLeaf(pCpum, 8);
1976
1977	/* Cpuid 9: Direct Cache Access (DCA) Parameters
1978	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
1979	* EBX, ECX, EDX - reserved.
1980	* AMD: Reserved
1981	* VIA: ??
1982	*
1983	* We zero this.
1984	*/
1985	cpumR3CpuIdZeroLeaf(pCpum, 9);
1986
1987	/* Cpuid 0xa: Architectural Performance Monitor Features
1988	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
1989	* EBX, ECX, EDX - reserved.
1990	* AMD: Reserved
1991	* VIA: ??
1992	*
1993	* We zero this, for now at least.
1994	*/
1995	cpumR3CpuIdZeroLeaf(pCpum, 10);
1996
1997	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
1998	* Intel: EAX - APCI ID shift right for next level.
1999	* EBX - Factory configured cores/threads at this level.
2000	* ECX - Level number (same as input) and level type (1,2,0).
2001	* EDX - Extended initial APIC ID.
2002	* AMD: Reserved
2003	* VIA: ??
2004	*/
2005	uSubLeaf = 0;
2006	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
2007	{
2008	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
2009	{
2010	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
2011	if (bLevelType == 1)
2012	{
2013	/* Thread level - we don't do threads at the moment. */
2014	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
2015	pCurLeaf->uEbx = 1;
2016	}
2017	else if (bLevelType == 2)
2018	{
2019	/* Core level. */
2020	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
2021	#ifdef VBOX_WITH_MULTI_CORE
2022	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
2023	pCurLeaf->uEax++;
2024	#endif
2025	pCurLeaf->uEbx = pVM->cCpus;
2026	}
2027	else
2028	{
2029	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
2030	pCurLeaf->uEax = 0;
2031	pCurLeaf->uEbx = 0;
2032	pCurLeaf->uEcx = 0;
2033	}
2034	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
2035	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
2036	}
2037	else
2038	{
2039	pCurLeaf->uEax = 0;
2040	pCurLeaf->uEbx = 0;
2041	pCurLeaf->uEcx = 0;
2042	pCurLeaf->uEdx = 0;
2043	}
2044	uSubLeaf++;
2045	}
2046
2047	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
2048	* We zero this since we don't know what it may have been used for.
2049	*/
2050	cpumR3CpuIdZeroLeaf(pCpum, 12);
2051
2052	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
2053	* ECX=0: EAX - Valid bits in XCR0[31:0].
2054	* EBX - Maximum state size as per current XCR0 value.
2055	* ECX - Maximum state size for all supported features.
2056	* EDX - Valid bits in XCR0[63:32].
2057	* ECX=1: EAX - Various X-features.
2058	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
2059	* ECX - Valid bits in IA32_XSS[31:0].
2060	* EDX - Valid bits in IA32_XSS[63:32].
2061	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
2062	* if the bit invalid all four registers are set to zero.
2063	* EAX - The state size for this feature.
2064	* EBX - The state byte offset of this feature.
2065	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
2066	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
2067	*
2068	* Clear them all as we don't currently implement extended CPU state.
2069	*/
2070	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
2071	uint64_t fGuestXcr0Mask = 0;
2072	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2073	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
2074	{
2075	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
2076	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
2077	fGuestXcr0Mask \|= XSAVE_C_YMM;
2078	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
2079	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
2080	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
2081	fGuestXcr0Mask &= pCpum->fXStateHostMask;
2082
2083	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
2084	}
2085	pStdFeatureLeaf = NULL;
2086	pCpum->fXStateGuestMask = fGuestXcr0Mask;
2087
2088	/* Work the sub-leaves. */
2089	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
2090	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
2091	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
2092	{
2093	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
2094	if (pCurLeaf)
2095	{
2096	if (fGuestXcr0Mask)
2097	{
2098	switch (uSubLeaf)
2099	{
2100	case 0:
2101	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
2102	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
2103	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2104	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
2105	VERR_CPUM_IPE_1);
2106	cbXSaveMaxActual = pCurLeaf->uEcx;
2107	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
2108	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
2109	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
2110	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
2111	VERR_CPUM_IPE_2);
2112	continue;
2113	case 1:
2114	pCurLeaf->uEax &= 0;
2115	pCurLeaf->uEcx &= 0;
2116	pCurLeaf->uEdx &= 0;
2117	/** @todo what about checking ebx? */
2118	continue;
2119	default:
2120	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
2121	{
2122	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
2123	&& pCurLeaf->uEax > 0
2124	&& pCurLeaf->uEbx < cbXSaveMaxActual
2125	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2126	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
2127	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
2128	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
2129	VERR_CPUM_IPE_2);
2130	AssertLogRel(!(pCurLeaf->uEcx & 1));
2131	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
2132	pCurLeaf->uEdx = 0; /* it's reserved... */
2133	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
2134	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
2135	continue;
2136	}
2137	break;
2138	}
2139	}
2140
2141	/* Clear the leaf. */
2142	pCurLeaf->uEax = 0;
2143	pCurLeaf->uEbx = 0;
2144	pCurLeaf->uEcx = 0;
2145	pCurLeaf->uEdx = 0;
2146	}
2147	}
2148
2149	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
2150	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
2151	{
2152	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
2153	if (pCurLeaf)
2154	{
2155	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
2156	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
2157	pCurLeaf->uEbx = cbXSaveMaxReport;
2158	pCurLeaf->uEcx = cbXSaveMaxReport;
2159	}
2160	}
2161
2162	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
2163	* We zero this since we don't know what it may have been used for.
2164	*/
2165	cpumR3CpuIdZeroLeaf(pCpum, 14);
2166
2167	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
2168	* also known as Intel Resource Director Technology (RDT) Monitoring
2169	* We zero this as we don't currently virtualize PQM.
2170	*/
2171	cpumR3CpuIdZeroLeaf(pCpum, 15);
2172
2173	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
2174	* also known as Intel Resource Director Technology (RDT) Allocation
2175	* We zero this as we don't currently virtualize PQE.
2176	*/
2177	cpumR3CpuIdZeroLeaf(pCpum, 16);
2178
2179	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
2180	* We zero this since we don't know what it may have been used for.
2181	*/
2182	cpumR3CpuIdZeroLeaf(pCpum, 17);
2183
2184	/* Cpuid 0x12 + ECX: SGX resource enumeration.
2185	* We zero this as we don't currently virtualize this.
2186	*/
2187	cpumR3CpuIdZeroLeaf(pCpum, 18);
2188
2189	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
2190	* We zero this since we don't know what it may have been used for.
2191	*/
2192	cpumR3CpuIdZeroLeaf(pCpum, 19);
2193
2194	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
2195	* We zero this as we don't currently virtualize this.
2196	*/
2197	cpumR3CpuIdZeroLeaf(pCpum, 20);
2198
2199	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
2200	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
2201	* EAX - denominator (unsigned).
2202	* EBX - numerator (unsigned).
2203	* ECX, EDX - reserved.
2204	* AMD: Reserved / undefined / not implemented.
2205	* VIA: Reserved / undefined / not implemented.
2206	* We zero this as we don't currently virtualize this.
2207	*/
2208	cpumR3CpuIdZeroLeaf(pCpum, 21);
2209
2210	/* Cpuid 0x16: Processor frequency info
2211	* Intel: EAX - Core base frequency in MHz.
2212	* EBX - Core maximum frequency in MHz.
2213	* ECX - Bus (reference) frequency in MHz.
2214	* EDX - Reserved.
2215	* AMD: Reserved / undefined / not implemented.
2216	* VIA: Reserved / undefined / not implemented.
2217	* We zero this as we don't currently virtualize this.
2218	*/
2219	cpumR3CpuIdZeroLeaf(pCpum, 22);
2220
2221	/* Cpuid 0x17..0x10000000: Unknown.
2222	* We don't know these and what they mean, so remove them. */
2223	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2224	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
2225
2226
2227	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
2228	* We remove all these as we're a hypervisor and must provide our own.
2229	*/
2230	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2231	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
2232
2233
2234	/* Cpuid 0x80000000 is harmless. */
2235
2236	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
2237
2238	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
2239
2240	/* Cpuid 0x80000005 & 0x80000006 contain information about L1, L2 & L3 cache and TLB identifiers.
2241	* Safe to pass on to the guest.
2242	*
2243	* AMD: 0x80000005 L1 cache information
2244	* 0x80000006 L2/L3 cache information
2245	* Intel: 0x80000005 reserved
2246	* 0x80000006 L2 cache information
2247	* VIA: 0x80000005 TLB and L1 cache information
2248	* 0x80000006 L2 cache information
2249	*/
2250
2251	uSubLeaf = 0;
2252	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000006), uSubLeaf)) != NULL)
2253	{
2254	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2255	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2256	{
2257	/*
2258	* Some AMD CPUs (e.g. Ryzen 7940HS) report zero L3 cache line size here and refer
2259	* to CPUID Fn8000_001D. This triggers division by zero in Linux if the
2260	* TopologyExtensions aka TOPOEXT bit in Fn8000_0001_ECX is not set, or if the kernel
2261	* is old enough (e.g. Linux 3.13) that it does not know about the topology extension
2262	* CPUID leaves.
2263	* We put a non-zero value in the cache line size here, if possible the actual value
2264	* gleaned from Fn8000_001D, or worst case a made-up valid number.
2265	*/
2266	PCPUMCPUIDLEAF pTopoLeaf;
2267	uint32_t uTopoSubLeaf;
2268	uint32_t uCacheLineSize;
2269
2270	if ((pCurLeaf->uEdx & 0xff) == 0)
2271	{
2272	uTopoSubLeaf = 0;
2273
2274	uCacheLineSize = 64; /* Use 64-byte line size as a fallback. */
2275
2276	/* Find L3 cache information. Have to check the cache level in EAX. */
2277	while ((pTopoLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uTopoSubLeaf)) != NULL)
2278	{
2279	if (((pTopoLeaf->uEax >> 5) & 0x07) == 3) {
2280	uCacheLineSize = (pTopoLeaf->uEbx & 0xfff) + 1;
2281	/* Fn8000_0006 can't report power of two line sizes greater than 128. */
2282	if (uCacheLineSize > 128)
2283	uCacheLineSize = 128;
2284
2285	break;
2286	}
2287	uTopoSubLeaf++;
2288	}
2289
2290	Assert(uCacheLineSize < 256);
2291	pCurLeaf->uEdx \|= uCacheLineSize;
2292	LogRel(("CPUM: AMD L3 cache line size in CPUID leaf 0x80000006 was zero, adjusting to %u\n", uCacheLineSize));
2293	}
2294	}
2295	uSubLeaf++;
2296	}
2297
2298	/* Cpuid 0x80000007: Advanced Power Management Information.
2299	* AMD: EAX: Processor feedback capabilities.
2300	* EBX: RAS capabilites.
2301	* ECX: Advanced power monitoring interface.
2302	* EDX: Enhanced power management capabilities.
2303	* Intel: EAX, EBX, ECX - reserved.
2304	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
2305	* VIA: Reserved
2306	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
2307	*/
2308	uSubLeaf = 0;
2309	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
2310	{
2311	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
2312	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2313	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2314	{
2315	/*
2316	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
2317	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
2318	* bit is now configurable.
2319	*/
2320	pCurLeaf->uEdx &= 0
2321	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
2322	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
2323	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
2324	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
2325	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
2326	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
2327	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
2328	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
2329	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
2330	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
2331	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
2332	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
2333	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
2334	\| 0;
2335	}
2336	else
2337	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2338	if (!pConfig->fInvariantTsc)
2339	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2340	uSubLeaf++;
2341	}
2342
2343	/* Cpuid 0x80000008:
2344	* AMD: EAX: Long Mode Size Identifiers
2345	* EBX: Extended Feature Identifiers
2346	* ECX: Number of cores + APICIdCoreIdSize
2347	* EDX: RDPRU Register Identifier Range
2348	* Intel: EAX: Virtual/Physical address Size
2349	* EBX, ECX, EDX - reserved
2350	* VIA: EAX: Virtual/Physical address Size
2351	* EBX, ECX, EDX - reserved
2352	*
2353	* We only expose the virtual+pysical address size to the guest atm.
2354	* On AMD we set the core count, but not the apic id stuff as we're
2355	* currently not doing the apic id assignments in a compatible manner.
2356	*/
2357	uSubLeaf = 0;
2358	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
2359	{
2360	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
2361	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2362	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2363	{
2364	/* Expose XSaveErPtr aka RstrFpErrPtrs to guest. */
2365	pCurLeaf->uEbx &= X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR; /* reserved - [12] == IBPB */
2366	}
2367	else
2368	pCurLeaf->uEbx = 0; /* reserved */
2369
2370	pCurLeaf->uEdx = 0; /* reserved */
2371
2372	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
2373	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
2374	pCurLeaf->uEcx = 0;
2375	#ifdef VBOX_WITH_MULTI_CORE
2376	if ( pVM->cCpus > 1
2377	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2378	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
2379	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
2380	#endif
2381	uSubLeaf++;
2382	}
2383
2384	/* Cpuid 0x80000009: Reserved
2385	* We zero this since we don't know what it may have been used for.
2386	*/
2387	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
2388
2389	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
2390	* AMD: EAX - SVM revision.
2391	* EBX - Number of ASIDs.
2392	* ECX - Reserved.
2393	* EDX - SVM Feature identification.
2394	*/
2395	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2396	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2397	{
2398	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2399	if ( pExtFeatureLeaf
2400	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
2401	{
2402	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
2403	if (pSvmFeatureLeaf)
2404	{
2405	pSvmFeatureLeaf->uEax = 0x1;
2406	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
2407	pSvmFeatureLeaf->uEcx = 0;
2408	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
2409	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
2410	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
2411	}
2412	else
2413	{
2414	/* Should never happen. */
2415	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
2416	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2417	}
2418	}
2419	else
2420	{
2421	/* If SVM is not supported, this is reserved, zero out. */
2422	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2423	}
2424	}
2425	else
2426	{
2427	/* Cpuid 0x8000000a: Reserved on Intel.
2428	* We zero this since we don't know what it may have been used for.
2429	*/
2430	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2431	}
2432
2433	/* Cpuid 0x8000000b thru 0x80000018: Reserved
2434	* We clear these as we don't know what purpose they might have. */
2435	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
2436	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
2437
2438	/* Cpuid 0x80000019: TLB configuration
2439	* Seems to be harmless, pass them thru as is. */
2440
2441	/* Cpuid 0x8000001a: Peformance optimization identifiers.
2442	* Strip anything we don't know what is or addresses feature we don't implement. */
2443	uSubLeaf = 0;
2444	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
2445	{
2446	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
2447	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
2448	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
2449	;
2450	pCurLeaf->uEbx = 0; /* reserved */
2451	pCurLeaf->uEcx = 0; /* reserved */
2452	pCurLeaf->uEdx = 0; /* reserved */
2453	uSubLeaf++;
2454	}
2455
2456	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
2457	* Clear this as we don't currently virtualize this feature. */
2458	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
2459
2460	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
2461	* Clear this as we don't currently virtualize this feature. */
2462	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
2463
2464	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
2465	* We need to sanitize the cores per cache (EAX[25:14]).
2466	*
2467	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
2468	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
2469	* slightly different meaning.
2470	*/
2471	uSubLeaf = 0;
2472	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
2473	{
2474	#ifdef VBOX_WITH_MULTI_CORE
2475	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
2476	if (cCores > pVM->cCpus)
2477	cCores = pVM->cCpus;
2478	pCurLeaf->uEax &= UINT32_C(0x00003fff);
2479	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
2480	#else
2481	pCurLeaf->uEax &= UINT32_C(0x00003fff);
2482	#endif
2483	uSubLeaf++;
2484	}
2485
2486	/* Cpuid 0x8000001e: Get APIC / unit / node information.
2487	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
2488	* setup, we have one compute unit with all the cores in it. Single node.
2489	*/
2490	uSubLeaf = 0;
2491	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
2492	{
2493	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
2494	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
2495	{
2496	#ifdef VBOX_WITH_MULTI_CORE
2497	pCurLeaf->uEbx = pVM->cCpus < 0x100
2498	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
2499	#else
2500	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
2501	#endif
2502	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
2503	}
2504	else
2505	{
2506	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
2507	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_HYGON);
2508	pCurLeaf->uEbx = 0; /* Reserved. */
2509	pCurLeaf->uEcx = 0; /* Reserved. */
2510	}
2511	pCurLeaf->uEdx = 0; /* Reserved. */
2512	uSubLeaf++;
2513	}
2514
2515	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
2516	* We don't know these and what they mean, so remove them. */
2517	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2518	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
2519
2520	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
2521	* Just pass it thru for now. */
2522
2523	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
2524	* Just pass it thru for now. */
2525
2526	/* Cpuid 0xc0000000: Centaur stuff.
2527	* Harmless, pass it thru. */
2528
2529	/* Cpuid 0xc0000001: Centaur features.
2530	* VIA: EAX - Family, model, stepping.
2531	* EDX - Centaur extended feature flags. Nothing interesting, except may
2532	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
2533	* EBX, ECX - reserved.
2534	* We keep EAX but strips the rest.
2535	*/
2536	uSubLeaf = 0;
2537	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
2538	{
2539	pCurLeaf->uEbx = 0;
2540	pCurLeaf->uEcx = 0;
2541	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
2542	uSubLeaf++;
2543	}
2544
2545	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
2546	* We only have fixed stale values, but should be harmless. */
2547
2548	/* Cpuid 0xc0000003: Reserved.
2549	* We zero this since we don't know what it may have been used for.
2550	*/
2551	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
2552
2553	/* Cpuid 0xc0000004: Centaur Performance Info.
2554	* We only have fixed stale values, but should be harmless. */
2555
2556
2557	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
2558	* We don't know these and what they mean, so remove them. */
2559	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2560	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
2561
2562	return VINF_SUCCESS;
2563	#undef PORTABLE_DISABLE_FEATURE_BIT
2564	#undef PORTABLE_CLEAR_BITS_WHEN
2565	}
2566
2567
2568	/**
2569	* Reads a value in /CPUM/IsaExts/ node.
2570	*
2571	* @returns VBox status code (error message raised).
2572	* @param pVM The cross context VM structure. (For errors.)
2573	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2574	* @param pszValueName The value / extension name.
2575	* @param penmValue Where to return the choice.
2576	* @param enmDefault The default choice.
2577	*/
2578	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
2579	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
2580	{
2581	/*
2582	* Try integer encoding first.
2583	*/
2584	uint64_t uValue;
2585	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
2586	if (RT_SUCCESS(rc))
2587	switch (uValue)
2588	{
2589	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
2590	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
2591	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
2592	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
2593	default:
2594	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
2595	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
2596	pszValueName, uValue);
2597	}
2598	/*
2599	* If missing, use default.
2600	*/
2601	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
2602	*penmValue = enmDefault;
2603	else
2604	{
2605	if (rc == VERR_CFGM_NOT_INTEGER)
2606	{
2607	/*
2608	* Not an integer, try read it as a string.
2609	*/
2610	char szValue[32];
2611	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
2612	if (RT_SUCCESS(rc))
2613	{
2614	RTStrToLower(szValue);
2615	size_t cchValue = strlen(szValue);
2616	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
2617	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
2618	*penmValue = CPUMISAEXTCFG_DISABLED;
2619	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
2620	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
2621	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
2622	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
2623	else if (EQ("portable"))
2624	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
2625	else if (EQ("default") \|\| EQ("def"))
2626	*penmValue = enmDefault;
2627	else
2628	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
2629	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
2630	pszValueName, uValue);
2631	#undef EQ
2632	}
2633	}
2634	if (RT_FAILURE(rc))
2635	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
2636	}
2637	return VINF_SUCCESS;
2638	}
2639
2640
2641	/**
2642	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
2643	*
2644	* @returns VBox status code (error message raised).
2645	* @param pVM The cross context VM structure. (For errors.)
2646	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2647	* @param pszValueName The value / extension name.
2648	* @param penmValue Where to return the choice.
2649	* @param enmDefault The default choice.
2650	* @param fAllowed Allowed choice. Applied both to the result and to
2651	* the default value.
2652	*/
2653	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
2654	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
2655	{
2656	int rc;
2657	if (fAllowed)
2658	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
2659	else
2660	{
2661	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
2662	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
2663	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
2664	*penmValue = CPUMISAEXTCFG_DISABLED;
2665	}
2666	return rc;
2667	}
2668
2669
2670	/**
2671	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
2672	*
2673	* @returns VBox status code (error message raised).
2674	* @param pVM The cross context VM structure. (For errors.)
2675	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2676	* @param pCpumCfg The /CPUM node (can be NULL).
2677	* @param pszValueName The value / extension name.
2678	* @param penmValue Where to return the choice.
2679	* @param enmDefault The default choice.
2680	*/
2681	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
2682	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
2683	{
2684	if (CFGMR3Exists(pCpumCfg, pszValueName))
2685	{
2686	if (!CFGMR3Exists(pIsaExts, pszValueName))
2687	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
2688	else
2689	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
2690	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
2691	pszValueName, pszValueName);
2692
2693	bool fLegacy;
2694	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
2695	if (RT_SUCCESS(rc))
2696	{
2697	*penmValue = fLegacy;
2698	return VINF_SUCCESS;
2699	}
2700	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
2701	}
2702
2703	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
2704	}
2705
2706
2707	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
2708	{
2709	int rc;
2710
2711	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
2712	* When non-zero CPUID features that could cause portability issues will be
2713	* stripped. The higher the value the more features gets stripped. Higher
2714	* values should only be used when older CPUs are involved since it may
2715	* harm performance and maybe also cause problems with specific guests. */
2716	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
2717	AssertLogRelRCReturn(rc, rc);
2718
2719	/** @cfgm{/CPUM/GuestCpuName, string}
2720	* The name of the CPU we're to emulate. The default is the host CPU.
2721	* Note! CPUs other than "host" one is currently unsupported. */
2722	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
2723	AssertLogRelRCReturn(rc, rc);
2724
2725	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
2726	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
2727	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
2728	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
2729	*/
2730	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
2731	AssertLogRelRCReturn(rc, rc);
2732
2733	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
2734	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
2735	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
2736	* 64-bit linux guests which assume the presence of AMD performance counters
2737	* that we do not virtualize.
2738	*/
2739	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
2740	AssertLogRelRCReturn(rc, rc);
2741
2742	/** @cfgm{/CPUM/InvariantApic, boolean, true}
2743	* Set the Always Running APIC Timer (ARAT) flag in lea if true; otherwise
2744	* pass through the host setting. The Windows 10/11 HAL won't use APIC timers
2745	* unless the ARAT bit is set. Note that both Intel and AMD set this bit.
2746	*/
2747	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantApic", &pConfig->fInvariantApic, true);
2748	AssertLogRelRCReturn(rc, rc);
2749
2750	/** @cfgm{/CPUM/ForceVme, boolean, false}
2751	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
2752	* By default the flag is passed thru as is from the host CPU, except
2753	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
2754	* guests and DOS boxes in general.
2755	*/
2756	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
2757	AssertLogRelRCReturn(rc, rc);
2758
2759	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
2760	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
2761	* probably going to be a temporary hack, so don't depend on this.
2762	* The 1st byte of the value is the stepping, the 2nd byte value is the model
2763	* number and the 3rd byte value is the family, and the 4th value must be zero.
2764	*/
2765	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
2766	AssertLogRelRCReturn(rc, rc);
2767
2768	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
2769	* The last standard leaf to keep. The actual last value that is stored in EAX
2770	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
2771	* removed. (This works independently of and differently from NT4LeafLimit.)
2772	* The default is usually set to what we're able to reasonably sanitize.
2773	*/
2774	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
2775	AssertLogRelRCReturn(rc, rc);
2776
2777	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
2778	* The last extended leaf to keep. The actual last value that is stored in EAX
2779	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
2780	* leaf are removed. The default is set to what we're able to sanitize.
2781	*/
2782	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
2783	AssertLogRelRCReturn(rc, rc);
2784
2785	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
2786	* The last extended leaf to keep. The actual last value that is stored in EAX
2787	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
2788	* leaf are removed. The default is set to what we're able to sanitize.
2789	*/
2790	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
2791	AssertLogRelRCReturn(rc, rc);
2792
2793	bool fQueryNestedHwvirt = false
2794	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2795	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2796	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON
2797	#endif
2798	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2799	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
2800	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA
2801	#endif
2802	;
2803	if (fQueryNestedHwvirt)
2804	{
2805	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
2806	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
2807	* The default is false, and when enabled requires a 64-bit CPU with support for
2808	* nested-paging and AMD-V or unrestricted guest mode.
2809	*/
2810	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
2811	AssertLogRelRCReturn(rc, rc);
2812	if (pConfig->fNestedHWVirt)
2813	{
2814	/** @todo Think about enabling this later with NEM/KVM. */
2815	if (VM_IS_NEM_ENABLED(pVM))
2816	{
2817	LogRel(("CPUM: Warning! Can't turn on nested VT-x/AMD-V when NEM is used! (later)\n"));
2818	pConfig->fNestedHWVirt = false;
2819	}
2820	else if (!fNestedPagingAndFullGuestExec)
2821	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
2822	"Cannot enable nested VT-x/AMD-V without nested-paging and unrestricted guest execution!\n");
2823	}
2824	}
2825
2826	/*
2827	* Instruction Set Architecture (ISA) Extensions.
2828	*/
2829	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
2830	if (pIsaExts)
2831	{
2832	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
2833	"CMPXCHG16B"
2834	"\|MONITOR"
2835	"\|MWaitExtensions"
2836	"\|SSE4.1"
2837	"\|SSE4.2"
2838	"\|XSAVE"
2839	"\|AVX"
2840	"\|AVX2"
2841	"\|AESNI"
2842	"\|PCLMUL"
2843	"\|POPCNT"
2844	"\|MOVBE"
2845	"\|RDRAND"
2846	"\|RDSEED"
2847	"\|ADX"
2848	"\|CLFLUSHOPT"
2849	"\|SHA"
2850	"\|FSGSBASE"
2851	"\|PCID"
2852	"\|INVPCID"
2853	"\|FlushCmdMsr"
2854	"\|MdsClear"
2855	"\|ArchCapMsr"
2856	"\|FMA"
2857	"\|F16C"
2858	"\|ABM"
2859	"\|SSE4A"
2860	"\|MISALNSSE"
2861	"\|3DNOWPRF"
2862	"\|AXMMX"
2863	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
2864	if (RT_FAILURE(rc))
2865	return rc;
2866	}
2867
2868	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, true}
2869	* Expose CMPXCHG16B to the guest if available. All host CPUs which support
2870	* hardware virtualization have it.
2871	*/
2872	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, true);
2873	AssertLogRelRCReturn(rc, rc);
2874
2875	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
2876	* Expose MONITOR/MWAIT instructions to the guest.
2877	*/
2878	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
2879	AssertLogRelRCReturn(rc, rc);
2880
2881	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
2882	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
2883	* break on interrupt feature (bit 1).
2884	*/
2885	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
2886	AssertLogRelRCReturn(rc, rc);
2887
2888	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
2889	* Expose SSE4.1 to the guest if available.
2890	*/
2891	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
2892	AssertLogRelRCReturn(rc, rc);
2893
2894	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
2895	* Expose SSE4.2 to the guest if available.
2896	*/
2897	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
2898	AssertLogRelRCReturn(rc, rc);
2899
2900	bool const fMayHaveXSave = pVM->cpum.s.HostFeatures.fXSaveRstor
2901	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
2902	&& ( VM_IS_NEM_ENABLED(pVM)
2903	? NEMHCGetFeatures(pVM) & NEM_FEAT_F_XSAVE_XRSTOR
2904	: VM_IS_EXEC_ENGINE_IEM(pVM)
2905	? true
2906	: fNestedPagingAndFullGuestExec);
2907	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
2908
2909	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
2910	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
2911	* default is to only expose this to VMs with nested paging and AMD-V or
2912	* unrestricted guest execution mode. Not possible to force this one without
2913	* host support at the moment.
2914	*/
2915	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, true,
2916	fMayHaveXSave /fAllowed/);
2917	AssertLogRelRCReturn(rc, rc);
2918
2919	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
2920	* Expose the AVX instruction set extensions to the guest if available and
2921	* XSAVE is exposed too. For the time being the default is to only expose this
2922	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
2923	*/
2924	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
2925	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
2926	AssertLogRelRCReturn(rc, rc);
2927
2928	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
2929	* Expose the AVX2 instruction set extensions to the guest if available and
2930	* XSAVE is exposed too. For the time being the default is to only expose this
2931	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
2932	*/
2933	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
2934	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
2935	AssertLogRelRCReturn(rc, rc);
2936
2937	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
2938	* Whether to expose the AES instructions to the guest. For the time being the
2939	* default is to only do this for VMs with nested paging and AMD-V or
2940	* unrestricted guest mode.
2941	*/
2942	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
2943	AssertLogRelRCReturn(rc, rc);
2944
2945	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
2946	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
2947	* being the default is to only do this for VMs with nested paging and AMD-V or
2948	* unrestricted guest mode.
2949	*/
2950	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
2951	AssertLogRelRCReturn(rc, rc);
2952
2953	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, true}
2954	* Whether to expose the POPCNT instructions to the guest.
2955	*/
2956	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, CPUMISAEXTCFG_ENABLED_SUPPORTED);
2957	AssertLogRelRCReturn(rc, rc);
2958
2959	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
2960	* Whether to expose the MOVBE instructions to the guest. For the time
2961	* being the default is to only do this for VMs with nested paging and AMD-V or
2962	* unrestricted guest mode.
2963	*/
2964	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, true);
2965	AssertLogRelRCReturn(rc, rc);
2966
2967	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
2968	* Whether to expose the RDRAND instructions to the guest. For the time being
2969	* the default is to only do this for VMs with nested paging and AMD-V or
2970	* unrestricted guest mode.
2971	*/
2972	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
2973	AssertLogRelRCReturn(rc, rc);
2974
2975	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
2976	* Whether to expose the RDSEED instructions to the guest. For the time being
2977	* the default is to only do this for VMs with nested paging and AMD-V or
2978	* unrestricted guest mode.
2979	*/
2980	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
2981	AssertLogRelRCReturn(rc, rc);
2982
2983	/** @cfgm{/CPUM/IsaExts/ADX, isaextcfg, depends}
2984	* Whether to expose the ADX instructions to the guest. For the time being
2985	* the default is to only do this for VMs with nested paging and AMD-V or
2986	* unrestricted guest mode.
2987	*/
2988	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ADX", &pConfig->enmAdx, fNestedPagingAndFullGuestExec);
2989	AssertLogRelRCReturn(rc, rc);
2990
2991	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
2992	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
2993	* being the default is to only do this for VMs with nested paging and AMD-V or
2994	* unrestricted guest mode.
2995	*/
2996	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
2997	AssertLogRelRCReturn(rc, rc);
2998
2999	/** @cfgm{/CPUM/IsaExts/SHA, isaextcfg, depends}
3000	* Whether to expose the SHA instructions to the guest. For the time being
3001	* the default is to only do this for VMs with nested paging and AMD-V or
3002	* unrestricted guest mode.
3003	*/
3004	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SHA", &pConfig->enmSha, fNestedPagingAndFullGuestExec);
3005	AssertLogRelRCReturn(rc, rc);
3006
3007	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
3008	* Whether to expose the read/write FSGSBASE instructions to the guest.
3009	*/
3010	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
3011	AssertLogRelRCReturn(rc, rc);
3012
3013	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
3014	* Whether to expose the PCID feature to the guest.
3015	*/
3016	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
3017	AssertLogRelRCReturn(rc, rc);
3018
3019	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
3020	* Whether to expose the INVPCID instruction to the guest.
3021	*/
3022	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
3023	AssertLogRelRCReturn(rc, rc);
3024
3025	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
3026	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
3027	*/
3028	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
3029	AssertLogRelRCReturn(rc, rc);
3030
3031	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
3032	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
3033	* the guest. Requires FlushCmdMsr to be present too.
3034	*/
3035	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
3036	AssertLogRelRCReturn(rc, rc);
3037
3038	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
3039	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
3040	*/
3041	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED_OR_NOT_AMD64);
3042	AssertLogRelRCReturn(rc, rc);
3043
3044	/** @cfgm{/CPUM/IsaExts/FMA, boolean, depends}
3045	* Expose the FMA instruction set extensions to the guest if available and
3046	* XSAVE is exposed too. For the time being the default is to only expose this
3047	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3048	*/
3049	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "FMA", &pConfig->enmFma, fNestedPagingAndFullGuestExec /* temporarily */,
3050	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3051	AssertLogRelRCReturn(rc, rc);
3052
3053	/** @cfgm{/CPUM/IsaExts/F16C, boolean, depends}
3054	* Expose the F16C instruction set extensions to the guest if available and
3055	* XSAVE is exposed too. For the time being the default is to only expose this
3056	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3057	*/
3058	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "F16C", &pConfig->enmF16c, fNestedPagingAndFullGuestExec /* temporarily */,
3059	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3060	AssertLogRelRCReturn(rc, rc);
3061
3062
3063	/* AMD: */
3064
3065	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, true}
3066	* Whether to expose the AMD ABM instructions to the guest.
3067	*/
3068	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, CPUMISAEXTCFG_ENABLED_SUPPORTED);
3069	AssertLogRelRCReturn(rc, rc);
3070
3071	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
3072	* Whether to expose the AMD SSE4A instructions to the guest. For the time
3073	* being the default is to only do this for VMs with nested paging and AMD-V or
3074	* unrestricted guest mode.
3075	*/
3076	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
3077	AssertLogRelRCReturn(rc, rc);
3078
3079	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
3080	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
3081	* the time being the default is to only do this for VMs with nested paging and
3082	* AMD-V or unrestricted guest mode.
3083	*/
3084	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
3085	AssertLogRelRCReturn(rc, rc);
3086
3087	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
3088	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
3089	* For the time being the default is to only do this for VMs with nested paging
3090	* and AMD-V or unrestricted guest mode.
3091	*/
3092	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
3093	AssertLogRelRCReturn(rc, rc);
3094
3095	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
3096	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
3097	* the default is to only do this for VMs with nested paging and AMD-V or
3098	* unrestricted guest mode.
3099	*/
3100	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
3101	AssertLogRelRCReturn(rc, rc);
3102
3103	return VINF_SUCCESS;
3104	}
3105
3106
3107	/**
3108	* Checks and fixes the maximum physical address width supported by the
3109	* variable-range MTRR MSRs to be consistent with what is reported in CPUID.
3110	*
3111	* @returns VBox status code.
3112	* @param pVM The cross context VM structure.
3113	* @param cVarMtrrs The number of variable-range MTRRs reported to the guest.
3114	*/
3115	static int cpumR3FixVarMtrrPhysAddrWidths(PVM pVM, uint8_t const cVarMtrrs)
3116	{
3117	AssertLogRelMsgReturn(cVarMtrrs <= RT_ELEMENTS(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr.aMtrrVarMsrs),
3118	("Invalid number of variable range MTRRs reported (%u)\n", cVarMtrrs),
3119	VERR_CPUM_IPE_2);
3120
3121	/*
3122	* CPUID determines the actual maximum physical address width reported and supported.
3123	* If the CPU DB profile reported fewer address bits, we must correct it here by
3124	* updating the MSR write #GP masks of all the variable-range MTRR MSRs. Otherwise,
3125	* they cause problems when guests write to these MTRR MSRs, see @bugref{10498#c32}.
3126	*/
3127	PCPUMMSRRANGE pBaseRange0 = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_PHYSBASE0);
3128	AssertLogRelMsgReturn(pBaseRange0, ("Failed to lookup the IA32_MTRR_PHYSBASE[0] MSR range\n"), VERR_NOT_FOUND);
3129
3130	PCPUMMSRRANGE pMaskRange0 = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_PHYSMASK0);
3131	AssertLogRelMsgReturn(pMaskRange0, ("Failed to lookup the IA32_MTRR_PHYSMASK[0] MSR range\n"), VERR_NOT_FOUND);
3132
3133	uint64_t const fPhysBaseWrGpMask = pBaseRange0->fWrGpMask;
3134	uint64_t const fPhysMaskWrGpMask = pMaskRange0->fWrGpMask;
3135
3136	uint8_t const cGuestMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
3137	uint8_t const cProfilePhysBaseMaxPhysAddrWidth = ASMBitLastSetU64(~fPhysBaseWrGpMask);
3138	uint8_t const cProfilePhysMaskMaxPhysAddrWidth = ASMBitLastSetU64(~fPhysMaskWrGpMask);
3139
3140	AssertLogRelMsgReturn(cProfilePhysBaseMaxPhysAddrWidth == cProfilePhysMaskMaxPhysAddrWidth,
3141	("IA32_MTRR_PHYSBASE and IA32_MTRR_PHYSMASK report different physical address widths (%u and %u)\n",
3142	cProfilePhysBaseMaxPhysAddrWidth, cProfilePhysMaskMaxPhysAddrWidth),
3143	VERR_CPUM_IPE_2);
3144	AssertLogRelMsgReturn(cProfilePhysBaseMaxPhysAddrWidth > 12 && cProfilePhysBaseMaxPhysAddrWidth <= 64,
3145	("IA32_MTRR_PHYSBASE and IA32_MTRR_PHYSMASK reports an invalid physical address width of %u bits\n",
3146	cProfilePhysBaseMaxPhysAddrWidth), VERR_CPUM_IPE_2);
3147
3148	if (cProfilePhysBaseMaxPhysAddrWidth < cGuestMaxPhysAddrWidth)
3149	{
3150	uint64_t fNewPhysBaseWrGpMask = fPhysBaseWrGpMask;
3151	uint64_t fNewPhysMaskWrGpMask = fPhysMaskWrGpMask;
3152	int8_t cBits = cGuestMaxPhysAddrWidth - cProfilePhysBaseMaxPhysAddrWidth;
3153	while (cBits)
3154	{
3155	uint64_t const fWrGpAndMask = ~(uint64_t)RT_BIT_64(cProfilePhysBaseMaxPhysAddrWidth + cBits - 1);
3156	fNewPhysBaseWrGpMask &= fWrGpAndMask;
3157	fNewPhysMaskWrGpMask &= fWrGpAndMask;
3158	--cBits;
3159	}
3160
3161	for (uint8_t iVarMtrr = 1; iVarMtrr < cVarMtrrs; iVarMtrr++)
3162	{
3163	PCPUMMSRRANGE pBaseRange = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_PHYSBASE0 + (iVarMtrr * 2));
3164	AssertLogRelMsgReturn(pBaseRange, ("Failed to lookup the IA32_MTRR_PHYSBASE[%u] MSR range\n", iVarMtrr),
3165	VERR_NOT_FOUND);
3166
3167	PCPUMMSRRANGE pMaskRange = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_PHYSMASK0 + (iVarMtrr * 2));
3168	AssertLogRelMsgReturn(pMaskRange, ("Failed to lookup the IA32_MTRR_PHYSMASK[%u] MSR range\n", iVarMtrr),
3169	VERR_NOT_FOUND);
3170
3171	AssertLogRelMsgReturn(pBaseRange->fWrGpMask == fPhysBaseWrGpMask,
3172	("IA32_MTRR_PHYSBASE[%u] write GP mask (%#016RX64) differs from IA32_MTRR_PHYSBASE[0] write GP mask (%#016RX64)\n",
3173	iVarMtrr, pBaseRange->fWrGpMask, fPhysBaseWrGpMask),
3174	VERR_CPUM_IPE_1);
3175	AssertLogRelMsgReturn(pMaskRange->fWrGpMask == fPhysMaskWrGpMask,
3176	("IA32_MTRR_PHYSMASK[%u] write GP mask (%#016RX64) differs from IA32_MTRR_PHYSMASK[0] write GP mask (%#016RX64)\n",
3177	iVarMtrr, pMaskRange->fWrGpMask, fPhysMaskWrGpMask),
3178	VERR_CPUM_IPE_1);
3179
3180	pBaseRange->fWrGpMask = fNewPhysBaseWrGpMask;
3181	pMaskRange->fWrGpMask = fNewPhysMaskWrGpMask;
3182	}
3183
3184	pBaseRange0->fWrGpMask = fNewPhysBaseWrGpMask;
3185	pMaskRange0->fWrGpMask = fNewPhysMaskWrGpMask;
3186
3187	LogRel(("CPUM: Updated IA32_MTRR_PHYSBASE[0..%u] MSR write #GP mask (old=%#016RX64 new=%#016RX64)\n",
3188	cVarMtrrs - 1, fPhysBaseWrGpMask, fNewPhysBaseWrGpMask));
3189	LogRel(("CPUM: Updated IA32_MTRR_PHYSMASK[0..%u] MSR write #GP mask (old=%#016RX64 new=%#016RX64)\n",
3190	cVarMtrrs - 1, fPhysMaskWrGpMask, fNewPhysMaskWrGpMask));
3191	}
3192
3193	return VINF_SUCCESS;
3194	}
3195
3196
3197	/**
3198	* Inserts variable-range MTRR MSR ranges based on the given count.
3199	*
3200	* Since we need to insert the MSRs beyond what the CPU profile has inserted, we
3201	* reinsert the whole range here since the variable-range MTRR MSR read+write
3202	* functions handle ranges as well as the \#GP checking.
3203	*
3204	* @returns VBox status code.
3205	* @param pVM The cross context VM structure.
3206	* @param cVarMtrrs The number of variable-range MTRRs to insert. This must be
3207	* less than or equal to CPUMCTX_MAX_MTRRVAR_COUNT.
3208	*/
3209	static int cpumR3VarMtrrMsrRangeInsert(PVM pVM, uint8_t const cVarMtrrs)
3210	{
3211	#ifdef VBOX_WITH_STATISTICS
3212	# define CPUM_MTRR_PHYSBASE_MSRRANGE(a_uMsr, a_uValue, a_szName) \
3213	{ (a_uMsr), (a_uMsr), kCpumMsrRdFn_Ia32MtrrPhysBaseN, kCpumMsrWrFn_Ia32MtrrPhysBaseN, 0, 0, a_uValue, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
3214	# define CPUM_MTRR_PHYSMASK_MSRRANGE(a_uMsr, a_uValue, a_szName) \
3215	{ (a_uMsr), (a_uMsr), kCpumMsrRdFn_Ia32MtrrPhysMaskN, kCpumMsrWrFn_Ia32MtrrPhysMaskN, 0, 0, a_uValue, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
3216	#else
3217	# define CPUM_MTRR_PHYSBASE_MSRRANGE(a_uMsr, a_uValue, a_szName) \
3218	{ (a_uMsr), (a_uMsr), kCpumMsrRdFn_Ia32MtrrPhysBaseN, kCpumMsrWrFn_Ia32MtrrPhysBaseN, 0, 0, a_uValue, 0, 0, a_szName }
3219	# define CPUM_MTRR_PHYSMASK_MSRRANGE(a_uMsr, a_uValue, a_szName) \
3220	{ (a_uMsr), (a_uMsr), kCpumMsrRdFn_Ia32MtrrPhysMaskN, kCpumMsrWrFn_Ia32MtrrPhysMaskN, 0, 0, a_uValue, 0, 0, a_szName }
3221	#endif
3222	static CPUMMSRRANGE const s_aMsrRanges_MtrrPhysBase[CPUMCTX_MAX_MTRRVAR_COUNT] =
3223	{
3224	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE0, 0, "MSR_IA32_MTRR_PHYSBASE0"),
3225	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE1, 1, "MSR_IA32_MTRR_PHYSBASE1"),
3226	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE2, 2, "MSR_IA32_MTRR_PHYSBASE2"),
3227	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE3, 3, "MSR_IA32_MTRR_PHYSBASE3"),
3228	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE4, 4, "MSR_IA32_MTRR_PHYSBASE4"),
3229	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE5, 5, "MSR_IA32_MTRR_PHYSBASE5"),
3230	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE6, 6, "MSR_IA32_MTRR_PHYSBASE6"),
3231	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE7, 7, "MSR_IA32_MTRR_PHYSBASE7"),
3232	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE8, 8, "MSR_IA32_MTRR_PHYSBASE8"),
3233	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9, 9, "MSR_IA32_MTRR_PHYSBASE9"),
3234	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 2, 10, "MSR_IA32_MTRR_PHYSBASE10"),
3235	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 4, 11, "MSR_IA32_MTRR_PHYSBASE11"),
3236	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 6, 12, "MSR_IA32_MTRR_PHYSBASE12"),
3237	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 8, 13, "MSR_IA32_MTRR_PHYSBASE13"),
3238	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 10, 14, "MSR_IA32_MTRR_PHYSBASE14"),
3239	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 12, 15, "MSR_IA32_MTRR_PHYSBASE15"),
3240	};
3241	static CPUMMSRRANGE const s_aMsrRanges_MtrrPhysMask[CPUMCTX_MAX_MTRRVAR_COUNT] =
3242	{
3243	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK0, 0, "MSR_IA32_MTRR_PHYSMASK0"),
3244	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK1, 1, "MSR_IA32_MTRR_PHYSMASK1"),
3245	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK2, 2, "MSR_IA32_MTRR_PHYSMASK2"),
3246	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK3, 3, "MSR_IA32_MTRR_PHYSMASK3"),
3247	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK4, 4, "MSR_IA32_MTRR_PHYSMASK4"),
3248	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK5, 5, "MSR_IA32_MTRR_PHYSMASK5"),
3249	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK6, 6, "MSR_IA32_MTRR_PHYSMASK6"),
3250	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK7, 7, "MSR_IA32_MTRR_PHYSMASK7"),
3251	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK8, 8, "MSR_IA32_MTRR_PHYSMASK8"),
3252	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9, 9, "MSR_IA32_MTRR_PHYSMASK9"),
3253	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 2, 10, "MSR_IA32_MTRR_PHYSMASK10"),
3254	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 4, 11, "MSR_IA32_MTRR_PHYSMASK11"),
3255	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 6, 12, "MSR_IA32_MTRR_PHYSMASK12"),
3256	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 8, 13, "MSR_IA32_MTRR_PHYSMASK13"),
3257	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 10, 14, "MSR_IA32_MTRR_PHYSMASK14"),
3258	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 12, 15, "MSR_IA32_MTRR_PHYSMASK15"),
3259	};
3260	AssertCompile(RT_ELEMENTS(s_aMsrRanges_MtrrPhysBase) == RT_ELEMENTS(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr.aMtrrVarMsrs));
3261	AssertCompile(RT_ELEMENTS(s_aMsrRanges_MtrrPhysMask) == RT_ELEMENTS(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr.aMtrrVarMsrs));
3262
3263	Assert(cVarMtrrs <= RT_ELEMENTS(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr.aMtrrVarMsrs));
3264	for (unsigned i = 0; i < cVarMtrrs; i++)
3265	{
3266	int rc = CPUMR3MsrRangesInsert(pVM, &s_aMsrRanges_MtrrPhysBase[i]);
3267	AssertLogRelRCReturn(rc, rc);
3268	rc = CPUMR3MsrRangesInsert(pVM, &s_aMsrRanges_MtrrPhysMask[i]);
3269	AssertLogRelRCReturn(rc, rc);
3270	}
3271	return VINF_SUCCESS;
3272
3273	#undef CPUM_MTRR_PHYSBASE_MSRRANGE
3274	#undef CPUM_MTRR_PHYSMASK_MSRRANGE
3275	}
3276
3277
3278	/**
3279	* Initialize MTRR capability based on what the guest CPU profile (typically host)
3280	* supports.
3281	*
3282	* @returns VBox status code.
3283	* @param pVM The cross context VM structure.
3284	* @param fMtrrVarCountIsVirt Whether the variable-range MTRR count is fully
3285	* virtualized (@c true) or derived from the CPU
3286	* profile (@c false).
3287	*/
3288	static int cpumR3InitMtrrCap(PVM pVM, bool fMtrrVarCountIsVirt)
3289	{
3290	#ifdef RT_ARCH_AMD64
3291	Assert(pVM->cpum.s.HostFeatures.fMtrr);
3292	#endif
3293
3294	/* Lookup the number of variable-range MTRRs supported by the CPU profile. */
3295	PCCPUMMSRRANGE pMtrrCapRange = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_CAP);
3296	AssertLogRelMsgReturn(pMtrrCapRange, ("Failed to lookup IA32_MTRR_CAP MSR range\n"), VERR_NOT_FOUND);
3297	uint8_t const cProfileVarRangeRegs = pMtrrCapRange->uValue & MSR_IA32_MTRR_CAP_VCNT_MASK;
3298
3299	/* Construct guest MTRR support capabilities. */
3300	uint8_t const cGuestVarRangeRegs = fMtrrVarCountIsVirt ? CPUMCTX_MAX_MTRRVAR_COUNT
3301	: RT_MIN(cProfileVarRangeRegs, CPUMCTX_MAX_MTRRVAR_COUNT);
3302	uint64_t const uGstMtrrCap = cGuestVarRangeRegs
3303	\| MSR_IA32_MTRR_CAP_FIX
3304	\| MSR_IA32_MTRR_CAP_WC;
3305	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3306	{
3307	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3308	pVCpu->cpum.s.GuestMsrs.msr.MtrrCap = uGstMtrrCap;
3309	pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = MSR_IA32_MTRR_DEF_TYPE_FIXED_EN
3310	\| MSR_IA32_MTRR_DEF_TYPE_MTRR_EN
3311	\| X86_MTRR_MT_UC;
3312	}
3313
3314	if (fMtrrVarCountIsVirt)
3315	{
3316	/*
3317	* Insert the full variable-range MTRR MSR range ourselves so it extends beyond what is
3318	* typically reported by the hardware CPU profile.
3319	*/
3320	LogRel(("CPUM: Enabled fixed-range MTRRs and %u (virtualized) variable-range MTRRs\n", cGuestVarRangeRegs));
3321	return cpumR3VarMtrrMsrRangeInsert(pVM, cGuestVarRangeRegs);
3322	}
3323
3324	/*
3325	* Ensure that the maximum physical address width supported by the variable-range MTRRs
3326	* are consistent with what is reported to the guest via CPUID.
3327	*/
3328	LogRel(("CPUM: Enabled fixed-range MTRRs and %u (CPU profile derived) variable-range MTRRs\n", cGuestVarRangeRegs));
3329	return cpumR3FixVarMtrrPhysAddrWidths(pVM, cGuestVarRangeRegs);
3330	}
3331
3332
3333	/**
3334	* Initializes the emulated CPU's CPUID & MSR information.
3335	*
3336	* @returns VBox status code.
3337	* @param pVM The cross context VM structure.
3338	* @param pHostMsrs Pointer to the host MSRs.
3339	*/
3340	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
3341	{
3342	Assert(pHostMsrs);
3343
3344	PCPUM pCpum = &pVM->cpum.s;
3345	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
3346
3347	/*
3348	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
3349	* on construction and manage everything from here on.
3350	*/
3351	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3352	{
3353	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3354	pVCpu->cpum.s.fCpuIdApicFeatureVisible = true;
3355	}
3356
3357	/*
3358	* Read the configuration.
3359	*/
3360	CPUMCPUIDCONFIG Config;
3361	RT_ZERO(Config);
3362
3363	bool const fNestedPagingAndFullGuestExec = VM_IS_NEM_ENABLED(pVM)
3364	\|\| HMAreNestedPagingAndFullGuestExecEnabled(pVM);
3365	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, fNestedPagingAndFullGuestExec);
3366	AssertRCReturn(rc, rc);
3367
3368	/*
3369	* Get the guest CPU data from the database and/or the host.
3370	*
3371	* The CPUID and MSRs are currently living on the regular heap to avoid
3372	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
3373	* API for the hyper heap). This means special cleanup considerations.
3374	*/
3375	/** @todo The hyper heap will be removed ASAP, so the final destination is
3376	* now a fixed sized arrays in the VM structure. Maybe we can simplify
3377	* this allocation fun a little now? Or maybe it's too convenient for
3378	* the CPU reporter code... No time to figure that out now. */
3379	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
3380	if (RT_FAILURE(rc))
3381	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
3382	? VMSetError(pVM, rc, RT_SRC_POS,
3383	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
3384	: rc;
3385
3386	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
3387	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
3388	{
3389	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
3390	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
3391	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
3392	}
3393	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
3394	#else
3395	LogRel(("CPUM: MXCSR_MASK=%#x\n", pCpum->GuestInfo.fMxCsrMask));
3396	#endif
3397
3398	/** @cfgm{/CPUM/GuestMicrocodeRev,32-bit}
3399	* CPU microcode revision number to use. If UINT32_MAX we use the host
3400	* revision of the host CPU for the host-cpu profile and the database entry if a
3401	* specific one is selected (amd64 host only). */
3402	rc = CFGMR3QueryU32Def(pCpumCfg, "GuestMicrocodeRevision", &pCpum->GuestInfo.uMicrocodeRevision, UINT32_MAX);
3403	AssertLogRelRCReturn(rc, rc);
3404	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
3405	if ( pCpum->GuestInfo.uMicrocodeRevision == UINT32_MAX
3406	&& strcmp(Config.szCpuName, "host") == 0)
3407	{
3408	rc = SUPR3QueryMicrocodeRev(&pCpum->GuestInfo.uMicrocodeRevision);
3409	if (RT_FAILURE(rc))
3410	pCpum->GuestInfo.uMicrocodeRevision = UINT32_MAX;
3411	}
3412	#endif
3413
3414	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
3415	* Overrides the guest MSRs.
3416	*/
3417	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
3418
3419	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
3420	* Overrides the CPUID leaf values (from the host CPU usually) used for
3421	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
3422	* values when moving a VM to a different machine. Another use is restricting
3423	* (or extending) the feature set exposed to the guest. */
3424	if (RT_SUCCESS(rc))
3425	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
3426
3427	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
3428	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
3429	"Found unsupported configuration node '/CPUM/CPUID/'. "
3430	"Please use IMachine::setCPUIDLeaf() instead.");
3431
3432	CPUMMSRS GuestMsrs;
3433	RT_ZERO(GuestMsrs);
3434
3435	/*
3436	* Pre-explode the CPUID info.
3437	*/
3438	if (RT_SUCCESS(rc))
3439	rc = cpumCpuIdExplodeFeaturesX86(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
3440	&pCpum->GuestFeatures);
3441
3442	/*
3443	* Sanitize the cpuid information passed on to the guest.
3444	*/
3445	if (RT_SUCCESS(rc))
3446	{
3447	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
3448	if (RT_SUCCESS(rc))
3449	{
3450	cpumR3CpuIdLimitLeaves(pCpum, &Config);
3451	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
3452	}
3453	}
3454
3455	/*
3456	* Move the CPUID array over to the static VM structure allocation
3457	* and explode guest CPU features again. We must do this before
3458	* reconciling MSRs with CPUIDs and applying any fudging (esp on ARM64).
3459	*/
3460	if (RT_SUCCESS(rc))
3461	{
3462	void * const pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
3463	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
3464	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
3465	AssertLogRelRC(rc);
3466	RTMemFree(pvFree);
3467	if (RT_SUCCESS(rc))
3468	{
3469	/*
3470	* Setup MSRs introduced in microcode updates or that are otherwise not in
3471	* the CPU profile, but are advertised in the CPUID info we just sanitized.
3472	*/
3473	if (RT_SUCCESS(rc))
3474	rc = cpumR3MsrReconcileWithCpuId(pVM);
3475	/*
3476	* MSR fudging.
3477	*/
3478	if (RT_SUCCESS(rc))
3479	{
3480	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
3481	* Fudges some common MSRs if not present in the selected CPU database entry.
3482	* This is for trying to keep VMs running when moved between different hosts
3483	* and different CPU vendors. */
3484	bool fEnable;
3485	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
3486	if (RT_SUCCESS(rc) && fEnable)
3487	{
3488	rc = cpumR3MsrApplyFudge(pVM);
3489	AssertLogRelRC(rc);
3490	}
3491	}
3492	if (RT_SUCCESS(rc))
3493	{
3494	/*
3495	* Move the MSR arrays over to the static VM structure allocation.
3496	*/
3497	AssertFatalMsg(pCpum->GuestInfo.cMsrRanges <= RT_ELEMENTS(pCpum->GuestInfo.aMsrRanges),
3498	("%u\n", pCpum->GuestInfo.cMsrRanges));
3499	memcpy(pCpum->GuestInfo.aMsrRanges, pCpum->GuestInfo.paMsrRangesR3,
3500	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges);
3501	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3502	pCpum->GuestInfo.paMsrRangesR3 = pCpum->GuestInfo.aMsrRanges;
3503
3504	/*
3505	* Some more configuration that we're applying at the end of everything
3506	* via the CPUMR3SetGuestCpuIdFeature API.
3507	*/
3508
3509	/* Check if 64-bit guest supported was enabled. */
3510	bool fEnable64bit;
3511	rc = CFGMR3QueryBoolDef(pCpumCfg, "Enable64bit", &fEnable64bit, false);
3512	AssertRCReturn(rc, rc);
3513	if (fEnable64bit)
3514	{
3515	/* In case of a CPU upgrade: */
3516	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
3517	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* (Long mode only on Intel CPUs.) */
3518	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3519	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
3520	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3521
3522	/* The actual feature: */
3523	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
3524	}
3525
3526	/* Check if PAE was explicitely enabled by the user. */
3527	bool fEnable;
3528	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, fEnable64bit);
3529	AssertRCReturn(rc, rc);
3530	if (fEnable && !pVM->cpum.s.GuestFeatures.fPae)
3531	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3532
3533	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
3534	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, fEnable64bit);
3535	AssertRCReturn(rc, rc);
3536	if (fEnable && !pVM->cpum.s.GuestFeatures.fNoExecute)
3537	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3538
3539	/* Check if speculation control is enabled. */
3540	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
3541	AssertRCReturn(rc, rc);
3542	if (fEnable)
3543	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
3544	else
3545	{
3546	/*
3547	* Set the "SSBD-not-needed" flag to work around a bug in some Linux kernels when the VIRT_SPEC_CTL
3548	* feature is not exposed on AMD CPUs and there is only 1 vCPU configured.
3549	* This was observed with kernel "4.15.0-29-generic #31~16.04.1-Ubuntu" but more versions are likely affected.
3550	*
3551	* The kernel doesn't initialize a lock and causes a NULL pointer exception later on when configuring SSBD:
3552	* EIP: _raw_spin_lock+0x14/0x30
3553	* EFLAGS: 00010046 CPU: 0
3554	* EAX: 00000000 EBX: 00000001 ECX: 00000004 EDX: 00000000
3555	* ESI: 00000000 EDI: 00000000 EBP: ee023f1c ESP: ee023f18
3556	* DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
3557	* CR0: 80050033 CR2: 00000004 CR3: 3671c180 CR4: 000006f0
3558	* Call Trace:
3559	* speculative_store_bypass_update+0x8e/0x180
3560	* ssb_prctl_set+0xc0/0xe0
3561	* arch_seccomp_spec_mitigate+0x1d/0x20
3562	* do_seccomp+0x3cb/0x610
3563	* SyS_seccomp+0x16/0x20
3564	* do_fast_syscall_32+0x7f/0x1d0
3565	* entry_SYSENTER_32+0x4e/0x7c
3566	*
3567	* The lock would've been initialized in process.c:speculative_store_bypass_ht_init() called from two places in smpboot.c.
3568	* First when a secondary CPU is started and second in native_smp_prepare_cpus() which is not called in a single vCPU environment.
3569	*
3570	* As spectre control features are completely disabled anyway when we arrived here there is no harm done in informing the
3571	* guest to not even try.
3572	*/
3573	if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3574	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3575	{
3576	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x80000008), 0);
3577	if (pLeaf)
3578	{
3579	pLeaf->uEbx \|= X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED;
3580	LogRel(("CPUM: Set SSBD not required flag for AMD to work around some buggy Linux kernels!\n"));
3581	}
3582	}
3583	}
3584
3585	/*
3586	* MTRR support.
3587	* We've always reported the MTRR feature bit in CPUID.
3588	* Here we allow exposing MTRRs with reasonable default values (especially required
3589	* by Windows 10 guests with Hyper-V enabled). The MTRR support isn't feature
3590	* complete, see @bugref{10318} and bugref{10498}.
3591	*/
3592	if (pVM->cpum.s.GuestFeatures.fMtrr)
3593	{
3594	/** @cfgm{/CPUM/MtrrWrite, boolean, true}
3595	* Whether to enable MTRR read-write support. This overrides the MTRR read-only CFGM
3596	* setting. */
3597	bool fEnableMtrrReadWrite;
3598	rc = CFGMR3QueryBoolDef(pCpumCfg, "MtrrReadWrite", &fEnableMtrrReadWrite, true);
3599	AssertRCReturn(rc, rc);
3600	if (fEnableMtrrReadWrite)
3601	{
3602	pVM->cpum.s.fMtrrRead = true;
3603	pVM->cpum.s.fMtrrWrite = true;
3604	LogRel(("CPUM: Enabled MTRR read-write support\n"));
3605	}
3606	else
3607	{
3608	/** @cfgm{/CPUM/MtrrReadOnly, boolean, false}
3609	* Whether to enable MTRR read-only support and to initialize mapping of guest
3610	* memory via MTRRs. When disabled, MTRRs are left blank, returns 0 on reads and
3611	* ignores writes. Some guests like GNU/Linux recognize a virtual system when MTRRs
3612	* are left blank but some guests may expect their RAM to be mapped via MTRRs
3613	* similar to real hardware. */
3614	rc = CFGMR3QueryBoolDef(pCpumCfg, "MtrrReadOnly", &pVM->cpum.s.fMtrrRead, false);
3615	AssertRCReturn(rc, rc);
3616	LogRel(("CPUM: Enabled MTRR read-only support\n"));
3617	}
3618
3619	/* Setup MTRR capability based on what the guest CPU profile (typically host) supports. */
3620	Assert(!pVM->cpum.s.fMtrrWrite \|\| pVM->cpum.s.fMtrrRead);
3621	if (pVM->cpum.s.fMtrrRead)
3622	{
3623	/** @cfgm{/CPUM/MtrrVarCountIsVirtual, boolean, true}
3624	* When enabled, the number of variable-range MTRRs are virtualized. When disabled,
3625	* the number of variable-range MTRRs are derived from the CPU profile. Unless
3626	* guests have problems with a virtualized number of variable-range MTRRs, it is
3627	* recommended to keep this enabled so that there are sufficient MTRRs to fully
3628	* describe all regions of the guest RAM. */
3629	bool fMtrrVarCountIsVirt;
3630	rc = CFGMR3QueryBoolDef(pCpumCfg, "MtrrVarCountIsVirtual", &fMtrrVarCountIsVirt, true);
3631	AssertRCReturn(rc, rc);
3632
3633	rc = cpumR3InitMtrrCap(pVM, fMtrrVarCountIsVirt);
3634	if (RT_SUCCESS(rc))
3635	{ /* likely */ }
3636	else
3637	return rc;
3638	}
3639	}
3640
3641	/*
3642	* Finally, initialize guest VMX MSRs.
3643	*
3644	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
3645	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
3646	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
3647	*/
3648	/** @todo r=bird: given that long mode never used to be enabled before the
3649	* VMINITCOMPLETED_RING0 state, and we're a lot earlier here in ring-3
3650	* init, the above comment cannot be entirely accurate. */
3651	if (pVM->cpum.s.GuestFeatures.fVmx)
3652	{
3653	Assert(Config.fNestedHWVirt);
3654	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, pCpumCfg, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
3655
3656	/* Copy MSRs to all VCPUs */
3657	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
3658	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3659	{
3660	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3661	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
3662	}
3663	}
3664
3665	return VINF_SUCCESS;
3666	}
3667
3668	/*
3669	* Failed before/while switching to internal VM structure storage.
3670	*/
3671	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
3672	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
3673	}
3674	}
3675	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3676	pCpum->GuestInfo.paMsrRangesR3 = NULL;
3677	return rc;
3678	}
3679
3680
3681	/**
3682	* Sets a CPUID feature bit during VM initialization.
3683	*
3684	* Since the CPUID feature bits are generally related to CPU features, other
3685	* CPUM configuration like MSRs can also be modified by calls to this API.
3686	*
3687	* @param pVM The cross context VM structure.
3688	* @param enmFeature The feature to set.
3689	*/
3690	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
3691	{
3692	PCPUMCPUIDLEAF pLeaf;
3693	PCPUMMSRRANGE pMsrRange;
3694
3695	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
3696	# define CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) \
3697	if (!pVM->cpum.s.HostFeatures. a_fFeature) \
3698	{ \
3699	LogRel(("CPUM: WARNING! Can't turn on " a_szFeature " when the host doesn't support it!\n")); \
3700	return; \
3701	} else do { } while (0)
3702	#else
3703	# define CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) do { } while (0)
3704	#endif
3705
3706	#define GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) \
3707	do \
3708	{ \
3709	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001)); \
3710	if (!pLeaf) \
3711	{ \
3712	LogRel(("CPUM: WARNING! Can't turn on " a_szFeature " when no 0x80000001 CPUID leaf!\n")); \
3713	return; \
3714	} \
3715	CHECK_X86_HOST_FEATURE_RET(a_fFeature,a_szFeature); \
3716	} while (0)
3717
3718	switch (enmFeature)
3719	{
3720	/*
3721	* Set the APIC bit in both feature masks.
3722	*/
3723	case CPUMCPUIDFEATURE_APIC:
3724	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3725	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3726	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
3727
3728	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3729	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3730	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
3731
3732	pVM->cpum.s.GuestFeatures.fApic = 1;
3733
3734	/* Make sure we've got the APICBASE MSR present. */
3735	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
3736	if (!pMsrRange)
3737	{
3738	static CPUMMSRRANGE const s_ApicBase =
3739	{
3740	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
3741	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
3742	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3743	/.szName = / "IA32_APIC_BASE"
3744	};
3745	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
3746	AssertLogRelRC(rc);
3747	}
3748
3749	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
3750	break;
3751
3752	/*
3753	* Set the x2APIC bit in the standard feature mask.
3754	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
3755	*/
3756	case CPUMCPUIDFEATURE_X2APIC:
3757	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3758	if (pLeaf)
3759	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
3760	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
3761
3762	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
3763	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
3764	if (pMsrRange)
3765	{
3766	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
3767	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
3768	}
3769
3770	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
3771	break;
3772
3773	/*
3774	* Set the sysenter/sysexit bit in the standard feature mask.
3775	* Assumes the caller knows what it's doing! (host must support these)
3776	*/
3777	case CPUMCPUIDFEATURE_SEP:
3778	CHECK_X86_HOST_FEATURE_RET(fSysEnter, "SEP");
3779	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3780	if (pLeaf)
3781	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
3782	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
3783	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
3784	break;
3785
3786	/*
3787	* Set the syscall/sysret bit in the extended feature mask.
3788	* Assumes the caller knows what it's doing! (host must support these)
3789	*/
3790	case CPUMCPUIDFEATURE_SYSCALL:
3791	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fSysCall, "SYSCALL/SYSRET");
3792
3793	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
3794	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
3795	pVM->cpum.s.GuestFeatures.fSysCall = 1;
3796	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
3797	break;
3798
3799	/*
3800	* Set the PAE bit in both feature masks.
3801	* Assumes the caller knows what it's doing! (host must support these)
3802	*/
3803	case CPUMCPUIDFEATURE_PAE:
3804	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3805	if (pLeaf)
3806	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
3807
3808	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3809	if ( pLeaf
3810	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3811	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3812	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
3813
3814	pVM->cpum.s.GuestFeatures.fPae = 1;
3815	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
3816	break;
3817
3818	/*
3819	* Set the LONG MODE bit in the extended feature mask.
3820	* Assumes the caller knows what it's doing! (host must support these)
3821	*/
3822	case CPUMCPUIDFEATURE_LONG_MODE:
3823	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fLongMode, "LONG MODE");
3824
3825	/* Valid for both Intel and AMD. */
3826	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
3827	pVM->cpum.s.GuestFeatures.fLongMode = 1;
3828	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
3829	if (pVM->cpum.s.GuestFeatures.fVmx)
3830	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3831	{
3832	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3833	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic &= ~VMX_BASIC_PHYSADDR_WIDTH_32BIT;
3834	}
3835	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
3836	break;
3837
3838	/*
3839	* Set the NX/XD bit in the extended feature mask.
3840	* Assumes the caller knows what it's doing! (host must support these)
3841	*/
3842	case CPUMCPUIDFEATURE_NX:
3843	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fNoExecute, "NX/XD");
3844
3845	/* Valid for both Intel and AMD. */
3846	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
3847	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
3848	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
3849	break;
3850
3851
3852	/*
3853	* Set the LAHF/SAHF support in 64-bit mode.
3854	* Assumes the caller knows what it's doing! (host must support this)
3855	*/
3856	case CPUMCPUIDFEATURE_LAHF:
3857	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fLahfSahf, "LAHF/SAHF");
3858
3859	/* Valid for both Intel and AMD. */
3860	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
3861	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
3862	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
3863	break;
3864
3865	/*
3866	* Set the RDTSCP support bit.
3867	* Assumes the caller knows what it's doing! (host must support this)
3868	*/
3869	case CPUMCPUIDFEATURE_RDTSCP:
3870	if (pVM->cpum.s.u8PortableCpuIdLevel > 0)
3871	return;
3872	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fRdTscP, "RDTSCP");
3873	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3874
3875	/* Valid for both Intel and AMD. */
3876	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
3877	pVM->cpum.s.HostFeatures.fRdTscP = 1;
3878	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
3879	break;
3880
3881	/*
3882	* Set the Hypervisor Present bit in the standard feature mask.
3883	*/
3884	case CPUMCPUIDFEATURE_HVP:
3885	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3886	if (pLeaf)
3887	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
3888	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
3889	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
3890	break;
3891
3892	/*
3893	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
3894	* on Intel CPUs, and different on AMDs.
3895	*/
3896	case CPUMCPUIDFEATURE_SPEC_CTRL:
3897	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3898	{
3899	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
3900	#ifdef RT_ARCH_AMD64
3901	if ( !pLeaf
3902	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
3903	{
3904	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
3905	return;
3906	}
3907	#else
3908	if (!pLeaf)
3909	{
3910	LogRel(("CPUM: WARNING! Can't turn on Speculation Control without leaf 0x00000007!\n"));
3911	return;
3912	}
3913	#endif
3914
3915	/* The feature can be enabled. Let's see what we can actually do. */
3916	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
3917
3918	#ifdef RT_ARCH_AMD64
3919	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
3920	if (pVM->cpum.s.HostFeatures.fIbrs)
3921	#endif
3922	{
3923	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
3924	pVM->cpum.s.GuestFeatures.fIbrs = 1;
3925	#ifdef RT_ARCH_AMD64
3926	if (pVM->cpum.s.HostFeatures.fStibp)
3927	#endif
3928	{
3929	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
3930	pVM->cpum.s.GuestFeatures.fStibp = 1;
3931	}
3932
3933	/* Make sure we have the speculation control MSR... */
3934	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
3935	if (!pMsrRange)
3936	{
3937	static CPUMMSRRANGE const s_SpecCtrl =
3938	{
3939	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
3940	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
3941	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3942	/.szName = / "IA32_SPEC_CTRL"
3943	};
3944	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
3945	AssertLogRelRC(rc);
3946	}
3947
3948	/* ... and the predictor command MSR. */
3949	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
3950	if (!pMsrRange)
3951	{
3952	/** @todo incorrect fWrGpMask. */
3953	static CPUMMSRRANGE const s_SpecCtrl =
3954	{
3955	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
3956	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
3957	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3958	/.szName = / "IA32_PRED_CMD"
3959	};
3960	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
3961	AssertLogRelRC(rc);
3962	}
3963
3964	}
3965
3966	#ifdef RT_ARCH_AMD64
3967	if (pVM->cpum.s.HostFeatures.fArchCap)
3968	#endif
3969	{
3970	/* Install the architectural capabilities MSR. */
3971	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
3972	if (!pMsrRange)
3973	{
3974	static CPUMMSRRANGE const s_ArchCaps =
3975	{
3976	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
3977	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
3978	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
3979	/.szName = / "IA32_ARCH_CAPABILITIES"
3980	};
3981	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
3982	AssertLogRelRC(rc);
3983	}
3984
3985	/* Advertise IBRS_ALL if present at this point... */
3986	if (pVM->cpum.s.HostFeatures.fArchCap & MSR_IA32_ARCH_CAP_F_IBRS_ALL)
3987	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps \|= MSR_IA32_ARCH_CAP_F_IBRS_ALL);
3988	}
3989
3990	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
3991	}
3992	else if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3993	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3994	{
3995	/* The precise details of AMD's implementation are not yet clear. */
3996	}
3997	break;
3998
3999	default:
4000	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4001	break;
4002	}
4003
4004	/** @todo can probably kill this as this API is now init time only... */
4005	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4006	{
4007	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4008	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4009	}
4010
4011	#undef GET_8000_0001_CHECK_X86_HOST_FEATURE_RET
4012	#undef CHECK_X86_HOST_FEATURE_RET
4013	}
4014
4015
4016	/**
4017	* Queries a CPUID feature bit.
4018	*
4019	* @returns boolean for feature presence
4020	* @param pVM The cross context VM structure.
4021	* @param enmFeature The feature to query.
4022	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4023	*/
4024	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4025	{
4026	switch (enmFeature)
4027	{
4028	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4029	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4030	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4031	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4032	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4033	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4034	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4035	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4036	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4037	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4038	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
4039	case CPUMCPUIDFEATURE_INVALID:
4040	case CPUMCPUIDFEATURE_32BIT_HACK:
4041	break;
4042	}
4043	AssertFailed();
4044	return false;
4045	}
4046
4047
4048	/**
4049	* Clears a CPUID feature bit.
4050	*
4051	* @param pVM The cross context VM structure.
4052	* @param enmFeature The feature to clear.
4053	*
4054	* @deprecated Probably better to default the feature to disabled and only allow
4055	* setting (enabling) it during construction.
4056	*/
4057	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4058	{
4059	PCPUMCPUIDLEAF pLeaf;
4060	switch (enmFeature)
4061	{
4062	case CPUMCPUIDFEATURE_APIC:
4063	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
4064	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4065	if (pLeaf)
4066	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
4067
4068	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4069	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4070	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4071
4072	pVM->cpum.s.GuestFeatures.fApic = 0;
4073	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4074	break;
4075
4076	case CPUMCPUIDFEATURE_X2APIC:
4077	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4078	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4079	if (pLeaf)
4080	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
4081	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
4082	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
4083	break;
4084
4085	#if 0
4086	case CPUMCPUIDFEATURE_PAE:
4087	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4088	if (pLeaf)
4089	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
4090
4091	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4092	if ( pLeaf
4093	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4094	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
4095	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
4096
4097	pVM->cpum.s.GuestFeatures.fPae = 0;
4098	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
4099	break;
4100
4101	case CPUMCPUIDFEATURE_LONG_MODE:
4102	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4103	if (pLeaf)
4104	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4105	pVM->cpum.s.GuestFeatures.fLongMode = 0;
4106	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
4107	if (pVM->cpum.s.GuestFeatures.fVmx)
4108	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4109	{
4110	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4111	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic \|= VMX_BASIC_PHYSADDR_WIDTH_32BIT;
4112	}
4113	break;
4114
4115	case CPUMCPUIDFEATURE_LAHF:
4116	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4117	if (pLeaf)
4118	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4119	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
4120	break;
4121	#endif
4122	case CPUMCPUIDFEATURE_RDTSCP:
4123	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4124	if (pLeaf)
4125	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4126	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
4127	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
4128	break;
4129
4130	#if 0
4131	case CPUMCPUIDFEATURE_HVP:
4132	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4133	if (pLeaf)
4134	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
4135	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
4136	break;
4137
4138	case CPUMCPUIDFEATURE_SPEC_CTRL:
4139	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4140	if (pLeaf)
4141	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
4142	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL);
4143	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
4144	break;
4145	#endif
4146	default:
4147	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4148	break;
4149	}
4150
4151	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4152	{
4153	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4154	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4155	}
4156	}
4157
4158
4159	/**
4160	* Do some final polishing after all calls to CPUMR3SetGuestCpuIdFeature and
4161	* CPUMR3ClearGuestCpuIdFeature are (probably) done.
4162	*
4163	* @param pVM The cross context VM structure.
4164	*/
4165	void cpumR3CpuIdRing3InitDone(PVM pVM)
4166	{
4167	/*
4168	* Do not advertise NX w/o PAE, seems to confuse windows 7 (black screen very
4169	* early in real mode).
4170	*/
4171	PCPUMCPUIDLEAF pStdLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4172	PCPUMCPUIDLEAF pExtLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4173	if (pStdLeaf && pExtLeaf)
4174	{
4175	if ( !(pStdLeaf->uEdx & X86_CPUID_FEATURE_EDX_PAE)
4176	&& (pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX))
4177	pExtLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_NX;
4178	}
4179	}
4180
4181
4182	/*
4183	*
4184	*
4185	* Saved state related code.
4186	* Saved state related code.
4187	* Saved state related code.
4188	*
4189	*
4190	*/
4191
4192	/**
4193	* Called both in pass 0 and the final pass.
4194	*
4195	* @param pVM The cross context VM structure.
4196	* @param pSSM The saved state handle.
4197	*/
4198	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4199	{
4200	/*
4201	* Save all the CPU ID leaves.
4202	*/
4203	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4204	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4205	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4206	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4207
4208	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4209
4210	/*
4211	* Save a good portion of the raw CPU IDs as well as they may come in
4212	* handy when validating features for raw mode.
4213	*/
4214	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4215	CPUMCPUID aRawStd[16];
4216	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4217	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4218	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4219	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4220
4221	CPUMCPUID aRawExt[32];
4222	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4223	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4224	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4225	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4226
4227	#else
4228	/* Two zero counts on non-x86 hosts. */
4229	SSMR3PutU32(pSSM, 0);
4230	SSMR3PutU32(pSSM, 0);
4231	#endif
4232	}
4233
4234
4235	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4236	{
4237	uint32_t cCpuIds;
4238	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4239	if (RT_SUCCESS(rc))
4240	{
4241	if (cCpuIds < 64)
4242	{
4243	for (uint32_t i = 0; i < cCpuIds; i++)
4244	{
4245	CPUMCPUID CpuId;
4246	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4247	if (RT_FAILURE(rc))
4248	break;
4249
4250	CPUMCPUIDLEAF NewLeaf;
4251	NewLeaf.uLeaf = uBase + i;
4252	NewLeaf.uSubLeaf = 0;
4253	NewLeaf.fSubLeafMask = 0;
4254	NewLeaf.uEax = CpuId.uEax;
4255	NewLeaf.uEbx = CpuId.uEbx;
4256	NewLeaf.uEcx = CpuId.uEcx;
4257	NewLeaf.uEdx = CpuId.uEdx;
4258	NewLeaf.fFlags = 0;
4259	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4260	}
4261	}
4262	else
4263	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4264	}
4265	if (RT_FAILURE(rc))
4266	{
4267	RTMemFree(*ppaLeaves);
4268	*ppaLeaves = NULL;
4269	*pcLeaves = 0;
4270	}
4271	return rc;
4272	}
4273
4274
4275	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4276	{
4277	*ppaLeaves = NULL;
4278	*pcLeaves = 0;
4279
4280	int rc;
4281	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4282	{
4283	/*
4284	* The new format. Starts by declaring the leave size and count.
4285	*/
4286	uint32_t cbLeaf;
4287	SSMR3GetU32(pSSM, &cbLeaf);
4288	uint32_t cLeaves;
4289	rc = SSMR3GetU32(pSSM, &cLeaves);
4290	if (RT_SUCCESS(rc))
4291	{
4292	if (cbLeaf == sizeof(**ppaLeaves))
4293	{
4294	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4295	{
4296	/*
4297	* Load the leaves one by one.
4298	*
4299	* The uPrev stuff is a kludge for working around a week worth of bad saved
4300	* states during the CPUID revamp in March 2015. We saved too many leaves
4301	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4302	* garbage entires at the end of the array when restoring. We also had
4303	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
4304	* this kludge doesn't deal correctly with that, but who cares...
4305	*/
4306	uint32_t uPrev = 0;
4307	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4308	{
4309	CPUMCPUIDLEAF Leaf;
4310	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
4311	if (RT_SUCCESS(rc))
4312	{
4313	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
4314	\|\| Leaf.uLeaf >= uPrev)
4315	{
4316	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4317	uPrev = Leaf.uLeaf;
4318	}
4319	else
4320	uPrev = UINT32_MAX;
4321	}
4322	}
4323	}
4324	else
4325	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
4326	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
4327	}
4328	else
4329	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
4330	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
4331	}
4332	}
4333	else
4334	{
4335	/*
4336	* The old format with its three inflexible arrays.
4337	*/
4338	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
4339	if (RT_SUCCESS(rc))
4340	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
4341	if (RT_SUCCESS(rc))
4342	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
4343	if (RT_SUCCESS(rc))
4344	{
4345	/*
4346	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
4347	*/
4348	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(ppaLeaves, pcLeaves, 0, 0);
4349	if ( pLeaf
4350	&& RTX86IsIntelCpu(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
4351	{
4352	CPUMCPUIDLEAF Leaf;
4353	Leaf.uLeaf = 4;
4354	Leaf.fSubLeafMask = UINT32_MAX;
4355	Leaf.uSubLeaf = 0;
4356	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
4357	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
4358	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
4359	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
4360	\| UINT32_C(63); /* system coherency line size - 1 */
4361	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
4362	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
4363	\| (UINT32_C(1) << 5) /* cache level */
4364	\| UINT32_C(1); /* cache type (data) */
4365	Leaf.fFlags = 0;
4366	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4367	if (RT_SUCCESS(rc))
4368	{
4369	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
4370	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4371	}
4372	if (RT_SUCCESS(rc))
4373	{
4374	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
4375	Leaf.uEcx = 4095; /* sets - 1 */
4376	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
4377	Leaf.uEbx \|= UINT32_C(23) << 22;
4378	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
4379	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
4380	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
4381	Leaf.uEax \|= UINT32_C(2) << 5;
4382	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4383	}
4384	}
4385	}
4386	}
4387	return rc;
4388	}
4389
4390
4391	/**
4392	* Loads the CPU ID leaves saved by pass 0, inner worker.
4393	*
4394	* @returns VBox status code.
4395	* @param pVM The cross context VM structure.
4396	* @param pSSM The saved state handle.
4397	* @param uVersion The format version.
4398	* @param paLeaves Guest CPUID leaves loaded from the state.
4399	* @param cLeaves The number of leaves in @a paLeaves.
4400	* @param pMsrs The guest MSRs.
4401	*/
4402	static int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
4403	{
4404	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4405	#if !defined(RT_ARCH_AMD64) && !defined(RT_ARCH_X86)
4406	AssertMsgFailed(("Port me!"));
4407	#endif
4408
4409	/*
4410	* Continue loading the state into stack buffers.
4411	*/
4412	CPUMCPUID GuestDefCpuId;
4413	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
4414	AssertRCReturn(rc, rc);
4415
4416	CPUMCPUID aRawStd[16];
4417	uint32_t cRawStd;
4418	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
4419	if (cRawStd > RT_ELEMENTS(aRawStd))
4420	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4421	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
4422	AssertRCReturn(rc, rc);
4423	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
4424	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4425	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4426	#else
4427	RT_ZERO(aRawStd[i]);
4428	#endif
4429
4430	CPUMCPUID aRawExt[32];
4431	uint32_t cRawExt;
4432	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
4433	if (cRawExt > RT_ELEMENTS(aRawExt))
4434	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4435	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
4436	AssertRCReturn(rc, rc);
4437	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
4438	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4439	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4440	#else
4441	RT_ZERO(aRawExt[i]);
4442	#endif
4443
4444	/*
4445	* Get the raw CPU IDs for the current host.
4446	*/
4447	CPUMCPUID aHostRawStd[16];
4448	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4449	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
4450	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
4451	#else
4452	RT_ZERO(aHostRawStd);
4453	#endif
4454
4455	CPUMCPUID aHostRawExt[32];
4456	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4457	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
4458	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
4459	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4460	#else
4461	RT_ZERO(aHostRawExt);
4462	#endif
4463
4464	/*
4465	* Get the host and guest overrides so we don't reject the state because
4466	* some feature was enabled thru these interfaces.
4467	* Note! We currently only need the feature leaves, so skip rest.
4468	*/
4469	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4470	CPUMCPUID aHostOverrideStd[2];
4471	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4472	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4473
4474	CPUMCPUID aHostOverrideExt[2];
4475	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4476	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4477
4478	/*
4479	* This can be skipped.
4480	*
4481	* @note On ARM we disable the strict checks for now because we can't verify with what the host supports
4482	* and just assume the interpreter/recompiler supports everything what was exposed earlier.
4483	*/
4484	bool fStrictCpuIdChecks;
4485	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks,
4486	#ifdef RT_ARCH_ARM64
4487	false
4488	#else
4489	true
4490	#endif
4491	);
4492
4493	/*
4494	* Define a bunch of macros for simplifying the santizing/checking code below.
4495	*/
4496	/* Generic expression + failure message. */
4497	#define CPUID_CHECK_RET(expr, fmt) \
4498	do { \
4499	if (!(expr)) \
4500	{ \
4501	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
4502	if (fStrictCpuIdChecks) \
4503	{ \
4504	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4505	RTStrFree(pszMsg); \
4506	return rcCpuid; \
4507	} \
4508	LogRel(("CPUM: %s\n", pszMsg)); \
4509	RTStrFree(pszMsg); \
4510	} \
4511	} while (0)
4512	#define CPUID_CHECK_WRN(expr, fmt) \
4513	do { \
4514	if (!(expr)) \
4515	LogRel(fmt); \
4516	} while (0)
4517
4518	/* For comparing two values and bitch if they differs. */
4519	#define CPUID_CHECK2_RET(what, host, saved) \
4520	do { \
4521	if ((host) != (saved)) \
4522	{ \
4523	if (fStrictCpuIdChecks) \
4524	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4525	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
4526	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4527	} \
4528	} while (0)
4529	#define CPUID_CHECK2_WRN(what, host, saved) \
4530	do { \
4531	if ((host) != (saved)) \
4532	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4533	} while (0)
4534
4535	/* For checking raw cpu features (raw mode). */
4536	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
4537	do { \
4538	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4539	{ \
4540	if (fStrictCpuIdChecks) \
4541	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4542	N_(#bit " mismatch: host=%d saved=%d"), \
4543	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
4544	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4545	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4546	} \
4547	} while (0)
4548	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
4549	do { \
4550	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4551	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4552	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4553	} while (0)
4554	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
4555
4556	/* For checking guest features. */
4557	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
4558	do { \
4559	if ( (aGuestCpuId##set [1].reg & bit) \
4560	&& !(aHostRaw##set [1].reg & bit) \
4561	&& !(aHostOverride##set [1].reg & bit) \
4562	) \
4563	{ \
4564	if (fStrictCpuIdChecks) \
4565	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4566	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4567	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4568	} \
4569	} while (0)
4570	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
4571	do { \
4572	if ( (aGuestCpuId##set [1].reg & bit) \
4573	&& !(aHostRaw##set [1].reg & bit) \
4574	&& !(aHostOverride##set [1].reg & bit) \
4575	) \
4576	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4577	} while (0)
4578	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
4579	do { \
4580	if ( (aGuestCpuId##set [1].reg & bit) \
4581	&& !(aHostRaw##set [1].reg & bit) \
4582	&& !(aHostOverride##set [1].reg & bit) \
4583	) \
4584	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4585	} while (0)
4586	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
4587
4588	/* For checking guest features if AMD guest CPU. */
4589	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
4590	do { \
4591	if ( (aGuestCpuId##set [1].reg & bit) \
4592	&& fGuestAmd \
4593	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4594	&& !(aHostOverride##set [1].reg & bit) \
4595	) \
4596	{ \
4597	if (fStrictCpuIdChecks) \
4598	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4599	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4600	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4601	} \
4602	} while (0)
4603	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
4604	do { \
4605	if ( (aGuestCpuId##set [1].reg & bit) \
4606	&& fGuestAmd \
4607	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4608	&& !(aHostOverride##set [1].reg & bit) \
4609	) \
4610	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4611	} while (0)
4612	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
4613	do { \
4614	if ( (aGuestCpuId##set [1].reg & bit) \
4615	&& fGuestAmd \
4616	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4617	&& !(aHostOverride##set [1].reg & bit) \
4618	) \
4619	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4620	} while (0)
4621	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
4622
4623	/* For checking AMD features which have a corresponding bit in the standard
4624	range. (Intel defines very few bits in the extended feature sets.) */
4625	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
4626	do { \
4627	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4628	&& !(fHostAmd \
4629	? aHostRawExt[1].reg & (ExtBit) \
4630	: aHostRawStd[1].reg & (StdBit)) \
4631	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4632	) \
4633	{ \
4634	if (fStrictCpuIdChecks) \
4635	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4636	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
4637	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4638	} \
4639	} while (0)
4640	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
4641	do { \
4642	if ( (aGuestCpuId[1].reg & (ExtBit)) \
4643	&& !(fHostAmd \
4644	? aHostRawExt[1].reg & (ExtBit) \
4645	: aHostRawStd[1].reg & (StdBit)) \
4646	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4647	) \
4648	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4649	} while (0)
4650	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
4651	do { \
4652	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4653	&& !(fHostAmd \
4654	? aHostRawExt[1].reg & (ExtBit) \
4655	: aHostRawStd[1].reg & (StdBit)) \
4656	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4657	) \
4658	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4659	} while (0)
4660	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
4661
4662
4663	/*
4664	* Verify that we can support the features already exposed to the guest on
4665	* this host.
4666	*
4667	* Most of the features we're emulating requires intercepting instruction
4668	* and doing it the slow way, so there is no need to warn when they aren't
4669	* present in the host CPU. Thus we use IGN instead of EMU on these.
4670	*
4671	* Trailing comments:
4672	* "EMU" - Possible to emulate, could be lots of work and very slow.
4673	* "EMU?" - Can this be emulated?
4674	*/
4675	CPUMCPUID aGuestCpuIdStd[2];
4676	RT_ZERO(aGuestCpuIdStd);
4677	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
4678
4679	/* CPUID(1).ecx */
4680	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
4681	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
4682	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
4683	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4684	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
4685	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
4686	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
4687	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
4688	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
4689	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
4690	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
4691	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
4692	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
4693	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
4694	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
4695	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
4696	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
4697	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4698	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
4699	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
4700	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
4701	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4702	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
4703	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
4704	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4705	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
4706	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
4707	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4708	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
4709	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4710	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4711	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
4712
4713	/* CPUID(1).edx */
4714	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4715	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4716	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
4717	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4718	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4719	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4720	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4721	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4722	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4723	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4724	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
4725	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4726	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4727	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4728	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4729	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4730	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4731	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4732	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4733	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
4734	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
4735	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
4736	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
4737	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4738	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4739	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
4740	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
4741	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
4742	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
4743	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
4744	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
4745	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
4746
4747	/* CPUID(0x80000000). */
4748	CPUMCPUID aGuestCpuIdExt[2];
4749	RT_ZERO(aGuestCpuIdExt);
4750	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
4751	{
4752	/** @todo deal with no 0x80000001 on the host. */
4753	bool const fHostAmd = RTX86IsAmdCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx)
4754	\|\| RTX86IsHygonCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
4755	bool const fGuestAmd = RTX86IsAmdCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx)
4756	\|\| RTX86IsHygonCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
4757
4758	/* CPUID(0x80000001).ecx */
4759	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
4760	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
4761	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
4762	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
4763	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
4764	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
4765	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
4766	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
4767	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
4768	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
4769	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
4770	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
4771	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
4772	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
4773	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4774	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4775	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4776	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4777	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4778	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4779	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4780	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4781	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4782	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4783	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4784	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4785	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4786	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4787	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4788	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4789	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4790	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4791
4792	/* CPUID(0x80000001).edx */
4793	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
4794	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
4795	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
4796	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
4797	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4798	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4799	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
4800	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
4801	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4802	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
4803	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4804	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
4805	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
4806	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
4807	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
4808	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4809	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
4810	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
4811	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4812	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4813	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4814	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
4815	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4816	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4817	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4818	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4819	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4820	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4821	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
4822	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4823	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4824	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4825	}
4826
4827	/** @todo check leaf 7 */
4828
4829	/* CPUID(d) - XCR0 stuff - takes ECX as input.
4830	* ECX=0: EAX - Valid bits in XCR0[31:0].
4831	* EBX - Maximum state size as per current XCR0 value.
4832	* ECX - Maximum state size for all supported features.
4833	* EDX - Valid bits in XCR0[63:32].
4834	* ECX=1: EAX - Various X-features.
4835	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
4836	* ECX - Valid bits in IA32_XSS[31:0].
4837	* EDX - Valid bits in IA32_XSS[63:32].
4838	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
4839	* if the bit invalid all four registers are set to zero.
4840	* EAX - The state size for this feature.
4841	* EBX - The state byte offset of this feature.
4842	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
4843	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
4844	*/
4845	uint64_t fGuestXcr0Mask = 0;
4846	PCPUMCPUIDLEAF pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
4847	if ( pCurLeaf
4848	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
4849	&& ( pCurLeaf->uEax
4850	\|\| pCurLeaf->uEbx
4851	\|\| pCurLeaf->uEcx
4852	\|\| pCurLeaf->uEdx) )
4853	{
4854	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
4855	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
4856	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4857	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
4858	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
4859	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
4860	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4861	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
4862
4863	/* We don't support any additional features yet. */
4864	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
4865	if (pCurLeaf && pCurLeaf->uEax)
4866	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4867	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
4868	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
4869	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4870	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
4871	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
4872
4873
4874	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4875	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
4876	{
4877	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4878	if (pCurLeaf)
4879	{
4880	/* If advertised, the state component offset and size must match the one used by host. */
4881	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
4882	{
4883	CPUMCPUID RawHost;
4884	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
4885	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
4886	if ( RawHost.uEbx != pCurLeaf->uEbx
4887	\|\| RawHost.uEax != pCurLeaf->uEax)
4888	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4889	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
4890	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
4891	}
4892	}
4893	}
4894	#endif
4895	}
4896	/* Clear leaf 0xd just in case we're loading an old state... */
4897	else if (pCurLeaf)
4898	{
4899	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
4900	{
4901	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4902	if (pCurLeaf)
4903	{
4904	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
4905	\|\| ( pCurLeaf->uEax == 0
4906	&& pCurLeaf->uEbx == 0
4907	&& pCurLeaf->uEcx == 0
4908	&& pCurLeaf->uEdx == 0),
4909	("uVersion=%#x; %#x %#x %#x %#x\n",
4910	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
4911	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
4912	}
4913	}
4914	}
4915
4916	/* Update the fXStateGuestMask value for the VM. */
4917	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
4918	{
4919	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
4920	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
4921	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
4922	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4923	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
4924	}
4925
4926	#undef CPUID_CHECK_RET
4927	#undef CPUID_CHECK_WRN
4928	#undef CPUID_CHECK2_RET
4929	#undef CPUID_CHECK2_WRN
4930	#undef CPUID_RAW_FEATURE_RET
4931	#undef CPUID_RAW_FEATURE_WRN
4932	#undef CPUID_RAW_FEATURE_IGN
4933	#undef CPUID_GST_FEATURE_RET
4934	#undef CPUID_GST_FEATURE_WRN
4935	#undef CPUID_GST_FEATURE_EMU
4936	#undef CPUID_GST_FEATURE_IGN
4937	#undef CPUID_GST_FEATURE2_RET
4938	#undef CPUID_GST_FEATURE2_WRN
4939	#undef CPUID_GST_FEATURE2_EMU
4940	#undef CPUID_GST_FEATURE2_IGN
4941	#undef CPUID_GST_AMD_FEATURE_RET
4942	#undef CPUID_GST_AMD_FEATURE_WRN
4943	#undef CPUID_GST_AMD_FEATURE_EMU
4944	#undef CPUID_GST_AMD_FEATURE_IGN
4945
4946	/*
4947	* We're good, commit the CPU ID leaves.
4948	*/
4949	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
4950	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
4951	AssertLogRelRCReturn(rc, rc);
4952
4953	return VINF_SUCCESS;
4954	}
4955
4956
4957	/**
4958	* Loads the CPU ID leaves saved by pass 0.
4959	*
4960	* @returns VBox status code.
4961	* @param pVM The cross context VM structure.
4962	* @param pSSM The saved state handle.
4963	* @param uVersion The format version.
4964	* @param pMsrs The guest MSRs.
4965	*/
4966	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
4967	{
4968	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4969
4970	/*
4971	* Load the CPUID leaves array first and call worker to do the rest, just so
4972	* we can free the memory when we need to without ending up in column 1000.
4973	*/
4974	PCPUMCPUIDLEAF paLeaves;
4975	uint32_t cLeaves;
4976	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
4977	AssertRC(rc);
4978	if (RT_SUCCESS(rc))
4979	{
4980	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
4981	RTMemFree(paLeaves);
4982	}
4983	return rc;
4984	}
4985
4986
4987
4988	/**
4989	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
4990	*
4991	* @returns VBox status code.
4992	* @param pVM The cross context VM structure.
4993	* @param pSSM The saved state handle.
4994	* @param uVersion The format version.
4995	*/
4996	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
4997	{
4998	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4999
5000	/*
5001	* Restore the CPUID leaves.
5002	*
5003	* Note that we support restoring less than the current amount of standard
5004	* leaves because we've been allowed more is newer version of VBox.
5005	*/
5006	uint32_t cElements;
5007	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5008	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5009	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5010	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5011
5012	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5013	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5014	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5015	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5016
5017	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5018	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5019	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5020	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5021
5022	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5023
5024	/*
5025	* Check that the basic cpuid id information is unchanged.
5026	*/
5027	/** @todo we should check the 64 bits capabilities too! */
5028	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5029	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5030	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5031	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5032	#endif
5033	uint32_t au32CpuIdSaved[8];
5034	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5035	if (RT_SUCCESS(rc))
5036	{
5037	/* Ignore CPU stepping. */
5038	au32CpuId[4] &= 0xfffffff0;
5039	au32CpuIdSaved[4] &= 0xfffffff0;
5040
5041	/* Ignore APIC ID (AMD specs). */
5042	au32CpuId[5] &= ~0xff000000;
5043	au32CpuIdSaved[5] &= ~0xff000000;
5044
5045	/* Ignore the number of Logical CPUs (AMD specs). */
5046	au32CpuId[5] &= ~0x00ff0000;
5047	au32CpuIdSaved[5] &= ~0x00ff0000;
5048
5049	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5050	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5051	\| X86_CPUID_FEATURE_ECX_VMX
5052	\| X86_CPUID_FEATURE_ECX_SMX
5053	\| X86_CPUID_FEATURE_ECX_EST
5054	\| X86_CPUID_FEATURE_ECX_TM2
5055	\| X86_CPUID_FEATURE_ECX_CNTXID
5056	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5057	\| X86_CPUID_FEATURE_ECX_PDCM
5058	\| X86_CPUID_FEATURE_ECX_DCA
5059	\| X86_CPUID_FEATURE_ECX_X2APIC
5060	);
5061	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5062	\| X86_CPUID_FEATURE_ECX_VMX
5063	\| X86_CPUID_FEATURE_ECX_SMX
5064	\| X86_CPUID_FEATURE_ECX_EST
5065	\| X86_CPUID_FEATURE_ECX_TM2
5066	\| X86_CPUID_FEATURE_ECX_CNTXID
5067	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5068	\| X86_CPUID_FEATURE_ECX_PDCM
5069	\| X86_CPUID_FEATURE_ECX_DCA
5070	\| X86_CPUID_FEATURE_ECX_X2APIC
5071	);
5072
5073	/* Make sure we don't forget to update the masks when enabling
5074	* features in the future.
5075	*/
5076	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5077	( X86_CPUID_FEATURE_ECX_DTES64
5078	\| X86_CPUID_FEATURE_ECX_VMX
5079	\| X86_CPUID_FEATURE_ECX_SMX
5080	\| X86_CPUID_FEATURE_ECX_EST
5081	\| X86_CPUID_FEATURE_ECX_TM2
5082	\| X86_CPUID_FEATURE_ECX_CNTXID
5083	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5084	\| X86_CPUID_FEATURE_ECX_PDCM
5085	\| X86_CPUID_FEATURE_ECX_DCA
5086	\| X86_CPUID_FEATURE_ECX_X2APIC
5087	)));
5088	/* do the compare */
5089	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5090	{
5091	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5092	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5093	"Saved=%.*Rhxs\n"
5094	"Real =%.*Rhxs\n",
5095	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5096	sizeof(au32CpuId), au32CpuId));
5097	else
5098	{
5099	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5100	"Saved=%.*Rhxs\n"
5101	"Real =%.*Rhxs\n",
5102	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5103	sizeof(au32CpuId), au32CpuId));
5104	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5105	}
5106	}
5107	}
5108
5109	return rc;
5110	}
5111
5112
5113
5114	/*
5115	*
5116	*
5117	* CPUID Info Handler.
5118	* CPUID Info Handler.
5119	* CPUID Info Handler.
5120	*
5121	*
5122	*/
5123
5124
5125
5126	/**
5127	* Get L1 cache / TLS associativity.
5128	*/
5129	static const char getCacheAss(unsigned u, char pszBuf)
5130	{
5131	if (u == 0)
5132	return "res0 ";
5133	if (u == 1)
5134	return "direct";
5135	if (u == 255)
5136	return "fully";
5137	if (u >= 256)
5138	return "???";
5139
5140	RTStrPrintf(pszBuf, 16, "%d way", u);
5141	return pszBuf;
5142	}
5143
5144
5145	/**
5146	* Get L2/L3 cache associativity.
5147	*/
5148	static const char *getL23CacheAss(unsigned u)
5149	{
5150	switch (u)
5151	{
5152	case 0: return "off ";
5153	case 1: return "direct";
5154	case 2: return "2 way ";
5155	case 3: return "3 way ";
5156	case 4: return "4 way ";
5157	case 5: return "6 way ";
5158	case 6: return "8 way ";
5159	case 7: return "res7 ";
5160	case 8: return "16 way";
5161	case 9: return "tpoext"; /* Overridden by Fn8000_001D */
5162	case 10: return "32 way";
5163	case 11: return "48 way";
5164	case 12: return "64 way";
5165	case 13: return "96 way";
5166	case 14: return "128way";
5167	case 15: return "fully ";
5168	default: return "????";
5169	}
5170	}
5171
5172
5173	/** CPUID(1).EDX field descriptions. */
5174	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
5175	{
5176	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5177	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5178	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5179	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5180	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5181	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
5182	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5183	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5184	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5185	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5186	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
5187	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5188	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5189	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5190	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5191	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5192	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5193	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
5194	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
5195	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
5196	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
5197	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5198	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
5199	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
5200	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
5201	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
5202	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
5203	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
5204	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
5205	DBGFREGSUBFIELD_TERMINATOR()
5206	};
5207
5208	/** CPUID(1).ECX field descriptions. */
5209	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
5210	{
5211	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
5212	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
5213	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
5214	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
5215	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
5216	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
5217	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
5218	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
5219	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
5220	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
5221	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
5222	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
5223	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
5224	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
5225	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
5226	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
5227	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
5228	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
5229	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
5230	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
5231	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
5232	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
5233	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
5234	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
5235	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
5236	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
5237	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
5238	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
5239	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
5240	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
5241	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
5242	DBGFREGSUBFIELD_TERMINATOR()
5243	};
5244
5245	/** CPUID(7,0).EBX field descriptions. */
5246	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
5247	{
5248	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
5249	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
5250	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
5251	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
5252	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
5253	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
5254	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
5255	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
5256	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
5257	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
5258	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
5259	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
5260	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
5261	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
5262	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
5263	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
5264	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
5265	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
5266	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
5267	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
5268	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
5269	DBGFREGSUBFIELD_RO("CLWB\0" "CLWB instruction", 24, 1, 0),
5270	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
5271	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
5272	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
5273	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
5274	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
5275	DBGFREGSUBFIELD_TERMINATOR()
5276	};
5277
5278	/** CPUID(7,0).ECX field descriptions. */
5279	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
5280	{
5281	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
5282	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
5283	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
5284	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
5285	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
5286	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
5287	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
5288	DBGFREGSUBFIELD_TERMINATOR()
5289	};
5290
5291	/** CPUID(7,0).EDX field descriptions. */
5292	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
5293	{
5294	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
5295	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
5296	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
5297	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
5298	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
5299	DBGFREGSUBFIELD_RO("CORECAP\0" "Supports IA32_CORE_CAP", 30, 1, 0),
5300	DBGFREGSUBFIELD_RO("SSBD\0" "Supports IA32_SPEC_CTRL.SSBD", 31, 1, 0),
5301	DBGFREGSUBFIELD_TERMINATOR()
5302	};
5303
5304
5305	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
5306	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
5307	{
5308	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
5309	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
5310	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
5311	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
5312	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
5313	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
5314	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
5315	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
5316	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
5317	DBGFREGSUBFIELD_TERMINATOR()
5318	};
5319
5320	/** CPUID(13,1).EAX field descriptions. */
5321	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
5322	{
5323	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
5324	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
5325	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
5326	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
5327	DBGFREGSUBFIELD_TERMINATOR()
5328	};
5329
5330
5331	/** CPUID(0x80000001,0).EDX field descriptions. */
5332	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
5333	{
5334	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5335	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5336	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5337	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5338	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5339	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
5340	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5341	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5342	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5343	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5344	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
5345	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5346	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5347	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5348	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5349	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5350	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5351	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
5352	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
5353	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5354	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
5355	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
5356	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
5357	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
5358	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
5359	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
5360	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
5361	DBGFREGSUBFIELD_TERMINATOR()
5362	};
5363
5364	/** CPUID(0x80000001,0).ECX field descriptions. */
5365	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
5366	{
5367	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
5368	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
5369	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
5370	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
5371	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
5372	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
5373	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
5374	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
5375	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
5376	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
5377	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
5378	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
5379	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
5380	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
5381	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
5382	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
5383	DBGFREGSUBFIELD_RO("TCE\0" "Translation Cache Extension support", 17, 1, 0),
5384	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
5385	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
5386	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
5387	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
5388	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
5389	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
5390	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
5391	DBGFREGSUBFIELD_RO("PCX_L2I\0" "L2I/L3 Performance Counter Extensions", 28, 1, 0),
5392	DBGFREGSUBFIELD_RO("MONITORX\0" "MWAITX and MONITORX instructions", 29, 1, 0),
5393	DBGFREGSUBFIELD_RO("AddrMaskExt\0" "BP Addressing masking extended to bit 31", 30, 1, 0),
5394	DBGFREGSUBFIELD_TERMINATOR()
5395	};
5396
5397	/** CPUID(0x8000000a,0).EDX field descriptions. */
5398	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
5399	{
5400	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
5401	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
5402	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
5403	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
5404	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
5405	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
5406	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
5407	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
5408	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
5409	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
5410	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
5411	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
5412	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
5413	DBGFREGSUBFIELD_RO("GMET\0" "Guest Mode Execute Trap Extension", 17, 1, 0),
5414	DBGFREGSUBFIELD_RO("x2AVIC\0" "AVIC support for x2APIC mode", 18, 1, 0),
5415	DBGFREGSUBFIELD_RO("SSSCheck\0" "SVM supervisor shadow stack restrictions", 19, 1, 0),
5416	DBGFREGSUBFIELD_RO("SpecCtrl\0" "SPEC_CTRL virtualization", 20, 1, 0),
5417	DBGFREGSUBFIELD_RO("ROGPT\0" "Read-Only Guest Page Table feature support", 21, 1, 0),
5418	DBGFREGSUBFIELD_RO("HOST_MCE_OVERRIDE\0" "Guest #MC can be intercepted", 23, 1, 0),
5419	DBGFREGSUBFIELD_RO("TlbiCtl\0" "INVLPGB/TLBSYNC enable and intercept", 24, 1, 0),
5420	DBGFREGSUBFIELD_RO("VNMI\0" "NMI Virtualization", 25, 1, 0),
5421	DBGFREGSUBFIELD_RO("IbsVirt\0" "IBS Virtualization", 26, 1, 0),
5422	DBGFREGSUBFIELD_RO("ExtLvtAvicAccessChg\0" "Extended LVT AVIC access changes", 27, 1, 0),
5423	DBGFREGSUBFIELD_RO("NestedVirtVmcbAddrChk\0""Guest VMCB address check", 28, 1, 0),
5424	DBGFREGSUBFIELD_RO("BusLockThreshold\0" "Bus Lock Threshold", 29, 1, 0),
5425	DBGFREGSUBFIELD_TERMINATOR()
5426	};
5427
5428
5429	/** CPUID(0x80000007,0).EDX field descriptions. */
5430	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
5431	{
5432	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
5433	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
5434	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
5435	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
5436	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
5437	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
5438	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
5439	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
5440	DBGFREGSUBFIELD_RO("CPB\0" "Core Performance Boost", 9, 1, 0),
5441	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
5442	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
5443	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
5444	DBGFREGSUBFIELD_RO("ConnectedStandby\0" "Connected Standby", 13, 1, 0),
5445	DBGFREGSUBFIELD_RO("RAPL\0" "Running average power limit", 14, 1, 0),
5446	DBGFREGSUBFIELD_TERMINATOR()
5447	};
5448
5449	/** CPUID(0x80000008,0).EBX field descriptions. */
5450	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
5451	{
5452	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
5453	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
5454	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR)", 2, 1, 0),
5455	DBGFREGSUBFIELD_RO("INVLPGB\0" "INVLPGB and TLBSYNC instructions", 3, 1, 0),
5456	DBGFREGSUBFIELD_RO("RDPRU\0" "RDPRU instruction", 4, 1, 0),
5457	DBGFREGSUBFIELD_RO("BE\0" "Bandwidth Enforcement extension", 6, 1, 0),
5458	DBGFREGSUBFIELD_RO("MCOMMIT\0" "MCOMMIT instruction", 8, 1, 0),
5459	DBGFREGSUBFIELD_RO("WBNOINVD\0" "WBNOINVD instruction", 9, 1, 0),
5460	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
5461	DBGFREGSUBFIELD_RO("INT_WBINVD\0" "WBINVD/WBNOINVD interruptible", 13, 1, 0),
5462	DBGFREGSUBFIELD_RO("IBRS\0" "Indirect Branch Restricted Speculation", 14, 1, 0),
5463	DBGFREGSUBFIELD_RO("STIBP\0" "Single Thread Indirect Branch Prediction", 15, 1, 0),
5464	DBGFREGSUBFIELD_RO("IbrsAlwaysOn\0" "Processor prefers that IBRS be left on", 16, 1, 0),
5465	DBGFREGSUBFIELD_RO("StibpAlwaysOn\0""Processor prefers that STIBP be left on", 17, 1, 0),
5466	DBGFREGSUBFIELD_RO("IbrsPreferred\0""IBRS preferred over software solution", 18, 1, 0),
5467	DBGFREGSUBFIELD_RO("IbrsSameMode\0" "IBRS limits same mode speculation", 19, 1, 0),
5468	DBGFREGSUBFIELD_RO("EferLmsleUnsupported\0" "EFER.LMSLE is unsupported", 20, 1, 0),
5469	DBGFREGSUBFIELD_RO("INVLPGBnestedPages\0" "INVLPGB for nested translation", 21, 1, 0),
5470	DBGFREGSUBFIELD_RO("SSBD\0" "Speculative Store Bypass Disable", 24, 1, 0),
5471	DBGFREGSUBFIELD_RO("SsbdVirtSpecCtrl\0" "Use VIRT_SPEC_CTL for SSBD", 25, 1, 0),
5472	DBGFREGSUBFIELD_RO("SsbdNotRequired\0" "SSBD not needed on this processor", 26, 1, 0),
5473	DBGFREGSUBFIELD_RO("CPPC\0" "Collaborative Processor Performance Control", 27, 1, 0),
5474	DBGFREGSUBFIELD_RO("PSFD\0" "Predictive Store Forward Disable", 28, 1, 0),
5475	DBGFREGSUBFIELD_RO("BTC_NO\0" "Unaffected by branch type confusion", 29, 1, 0),
5476	DBGFREGSUBFIELD_RO("IBPB_RET\0" "Clears RA predictor when PRED_CMD.IBPB set", 30, 1, 0),
5477	DBGFREGSUBFIELD_TERMINATOR()
5478	};
5479
5480
5481	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
5482	const char *pszLeadIn, uint32_t cchWidth)
5483	{
5484	if (pszLeadIn)
5485	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5486
5487	for (uint32_t iBit = 0; iBit < 32; iBit++)
5488	if (RT_BIT_32(iBit) & uVal)
5489	{
5490	while ( pDesc->pszName != NULL
5491	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5492	pDesc++;
5493	if ( pDesc->pszName != NULL
5494	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5495	{
5496	if (pDesc->cBits == 1)
5497	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5498	else
5499	{
5500	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
5501	if (pDesc->cBits < 32)
5502	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5503	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
5504	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5505	}
5506	}
5507	else
5508	pHlp->pfnPrintf(pHlp, " %u", iBit);
5509	}
5510	if (pszLeadIn)
5511	pHlp->pfnPrintf(pHlp, "\n");
5512	}
5513
5514
5515	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5516	const char *pszLeadIn, uint32_t cchWidth)
5517	{
5518	if (pszLeadIn)
5519	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5520
5521	for (uint32_t iBit = 0; iBit < 64; iBit++)
5522	if (RT_BIT_64(iBit) & uVal)
5523	{
5524	while ( pDesc->pszName != NULL
5525	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5526	pDesc++;
5527	if ( pDesc->pszName != NULL
5528	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5529	{
5530	if (pDesc->cBits == 1)
5531	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5532	else
5533	{
5534	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
5535	if (pDesc->cBits < 64)
5536	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
5537	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
5538	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5539	}
5540	}
5541	else
5542	pHlp->pfnPrintf(pHlp, " %u", iBit);
5543	}
5544	if (pszLeadIn)
5545	pHlp->pfnPrintf(pHlp, "\n");
5546	}
5547
5548
5549	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5550	const char *pszLeadIn, uint32_t cchWidth)
5551	{
5552	if (!uVal)
5553	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5554	else
5555	{
5556	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5557	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
5558	pHlp->pfnPrintf(pHlp, " )\n");
5559	}
5560	}
5561
5562
5563	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
5564	uint32_t cchWidth)
5565	{
5566	uint32_t uCombined = uVal1 \| uVal2;
5567	for (uint32_t iBit = 0; iBit < 32; iBit++)
5568	if ( (RT_BIT_32(iBit) & uCombined)
5569	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
5570	{
5571	while ( pDesc->pszName != NULL
5572	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5573	pDesc++;
5574
5575	if ( pDesc->pszName != NULL
5576	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5577	{
5578	size_t cchMnemonic = strlen(pDesc->pszName);
5579	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
5580	size_t cchDesc = strlen(pszDesc);
5581	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
5582	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
5583	if (pDesc->cBits < 32)
5584	{
5585	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5586	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5587	}
5588
5589	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
5590	pDesc->pszName, pszDesc,
5591	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
5592	uFieldValue1, uFieldValue2);
5593
5594	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
5595	pDesc++;
5596	}
5597	else
5598	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
5599	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
5600	}
5601	}
5602
5603
5604	/**
5605	* Produces a detailed summary of standard leaf 0x00000001.
5606	*
5607	* @param pHlp The info helper functions.
5608	* @param pCurLeaf The 0x00000001 leaf.
5609	* @param fVerbose Whether to be very verbose or not.
5610	* @param fIntel Set if intel CPU.
5611	*/
5612	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
5613	{
5614	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
5615	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
5616	uint32_t uEAX = pCurLeaf->uEax;
5617	uint32_t uEBX = pCurLeaf->uEbx;
5618
5619	pHlp->pfnPrintf(pHlp,
5620	"%36s %2d \tExtended: %d \tEffective: %d\n"
5621	"%36s %2d \tExtended: %d \tEffective: %d\n"
5622	"%36s %d\n"
5623	"%36s %d (%s)\n"
5624	"%36s %#04x\n"
5625	"%36s %d\n"
5626	"%36s %d\n"
5627	"%36s %#04x\n"
5628	,
5629	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
5630	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
5631	"Stepping:", RTX86GetCpuStepping(uEAX),
5632	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
5633	"APIC ID:", (uEBX >> 24) & 0xff,
5634	"Logical CPUs:",(uEBX >> 16) & 0xff,
5635	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
5636	"Brand ID:", (uEBX >> 0) & 0xff);
5637	if (fVerbose)
5638	{
5639	CPUMCPUID Host = {0};
5640	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5641	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5642	#endif
5643	pHlp->pfnPrintf(pHlp, "Features\n");
5644	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5645	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
5646	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
5647	}
5648	else
5649	{
5650	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
5651	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
5652	}
5653	}
5654
5655
5656	/**
5657	* Produces a detailed summary of standard leaf 0x00000007.
5658	*
5659	* @param pHlp The info helper functions.
5660	* @param paLeaves The CPUID leaves array.
5661	* @param cLeaves The number of leaves in the array.
5662	* @param pCurLeaf The first 0x00000007 leaf.
5663	* @param fVerbose Whether to be very verbose or not.
5664	*/
5665	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5666	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5667	{
5668	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
5669	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
5670	for (;;)
5671	{
5672	CPUMCPUID Host = {0};
5673	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5674	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5675	#endif
5676
5677	switch (pCurLeaf->uSubLeaf)
5678	{
5679	case 0:
5680	if (fVerbose)
5681	{
5682	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5683	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
5684	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
5685	if (pCurLeaf->uEdx \|\| Host.uEdx)
5686	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
5687	}
5688	else
5689	{
5690	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
5691	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
5692	if (pCurLeaf->uEdx)
5693	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
5694	}
5695	break;
5696
5697	default:
5698	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
5699	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
5700	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
5701	break;
5702
5703	}
5704
5705	/* advance. */
5706	pCurLeaf++;
5707	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5708	\|\| pCurLeaf->uLeaf != 0x7)
5709	break;
5710	}
5711	}
5712
5713
5714	/**
5715	* Produces a detailed summary of standard leaf 0x0000000d.
5716	*
5717	* @param pHlp The info helper functions.
5718	* @param paLeaves The CPUID leaves array.
5719	* @param cLeaves The number of leaves in the array.
5720	* @param pCurLeaf The first 0x00000007 leaf.
5721	* @param fVerbose Whether to be very verbose or not.
5722	*/
5723	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5724	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5725	{
5726	RT_NOREF_PV(fVerbose);
5727	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
5728	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
5729	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5730	{
5731	CPUMCPUID Host = {0};
5732	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5733	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5734	#endif
5735
5736	switch (uSubLeaf)
5737	{
5738	case 0:
5739	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5740	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
5741	pCurLeaf->uEbx, pCurLeaf->uEcx);
5742	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
5743
5744	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5745	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
5746	"Valid XCR0 bits, guest:", 42);
5747	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
5748	"Valid XCR0 bits, host:", 42);
5749	break;
5750
5751	case 1:
5752	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5753	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
5754	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
5755
5756	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5757	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
5758	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
5759
5760	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5761	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
5762	" Valid IA32_XSS bits, guest:", 42);
5763	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
5764	" Valid IA32_XSS bits, host:", 42);
5765	break;
5766
5767	default:
5768	if ( pCurLeaf
5769	&& pCurLeaf->uSubLeaf == uSubLeaf
5770	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
5771	{
5772	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
5773	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5774	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
5775	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
5776	if (pCurLeaf->uEdx)
5777	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
5778	pHlp->pfnPrintf(pHlp, " --");
5779	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5780	pHlp->pfnPrintf(pHlp, "\n");
5781	}
5782	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
5783	{
5784	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
5785	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5786	if (Host.uEcx & ~RT_BIT_32(0))
5787	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
5788	if (Host.uEdx)
5789	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
5790	pHlp->pfnPrintf(pHlp, " --");
5791	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5792	pHlp->pfnPrintf(pHlp, "\n");
5793	}
5794	break;
5795
5796	}
5797
5798	/* advance. */
5799	if (pCurLeaf)
5800	{
5801	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5802	&& pCurLeaf->uSubLeaf <= uSubLeaf
5803	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
5804	pCurLeaf++;
5805	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5806	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
5807	pCurLeaf = NULL;
5808	}
5809	}
5810	}
5811
5812
5813	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5814	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
5815	{
5816	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5817	&& pCurLeaf->uLeaf <= uUpToLeaf)
5818	{
5819	pHlp->pfnPrintf(pHlp,
5820	" %s\n"
5821	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
5822	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5823	&& pCurLeaf->uLeaf <= uUpToLeaf)
5824	{
5825	CPUMCPUID Host = {0};
5826	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5827	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5828	#endif
5829	pHlp->pfnPrintf(pHlp,
5830	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5831	"Hst: %08x %08x %08x %08x\n",
5832	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5833	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5834	pCurLeaf++;
5835	}
5836	}
5837
5838	return pCurLeaf;
5839	}
5840
5841
5842	/**
5843	* Display the guest CpuId leaves.
5844	*
5845	* @param pVM The cross context VM structure.
5846	* @param pHlp The info helper functions.
5847	* @param pszArgs "terse", "default" or "verbose".
5848	*/
5849	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
5850	{
5851	/*
5852	* Parse the argument.
5853	*/
5854	unsigned iVerbosity = 1;
5855	if (pszArgs)
5856	{
5857	pszArgs = RTStrStripL(pszArgs);
5858	if (!strcmp(pszArgs, "terse"))
5859	iVerbosity--;
5860	else if (!strcmp(pszArgs, "verbose"))
5861	iVerbosity++;
5862	}
5863
5864	uint32_t uLeaf;
5865	CPUMCPUID Host = {0};
5866	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
5867	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
5868	PCCPUMCPUIDLEAF pCurLeaf;
5869	PCCPUMCPUIDLEAF pNextLeaf;
5870	bool const fIntel = RTX86IsIntelCpu(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
5871	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
5872	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
5873
5874	/*
5875	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
5876	*/
5877	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5878	uint32_t cHstMax = ASMCpuId_EAX(0);
5879	#else
5880	uint32_t cHstMax = 0;
5881	#endif
5882	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
5883	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
5884	pHlp->pfnPrintf(pHlp,
5885	" Raw Standard CPUID Leaves\n"
5886	" Leaf/sub-leaf eax ebx ecx edx\n");
5887	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
5888	{
5889	uint32_t cMaxSubLeaves = 1;
5890	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
5891	cMaxSubLeaves = 16;
5892	else if (uLeaf == 0xd)
5893	cMaxSubLeaves = 128;
5894
5895	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5896	{
5897	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5898	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5899	#endif
5900	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5901	&& pCurLeaf->uLeaf == uLeaf
5902	&& pCurLeaf->uSubLeaf == uSubLeaf)
5903	{
5904	pHlp->pfnPrintf(pHlp,
5905	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5906	"Hst: %08x %08x %08x %08x\n",
5907	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5908	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5909	pCurLeaf++;
5910	}
5911	else if ( uLeaf != 0xd
5912	\|\| uSubLeaf <= 1
5913	\|\| Host.uEbx != 0 )
5914	pHlp->pfnPrintf(pHlp,
5915	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5916	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5917
5918	/* Done? */
5919	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5920	\|\| pCurLeaf->uLeaf != uLeaf)
5921	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
5922	\|\| (uLeaf == 0x7 && Host.uEax == 0)
5923	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
5924	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
5925	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
5926	)
5927	)
5928	break;
5929	}
5930	}
5931	pNextLeaf = pCurLeaf;
5932
5933	/*
5934	* If verbose, decode it.
5935	*/
5936	if (iVerbosity && paLeaves[0].uLeaf == 0)
5937	pHlp->pfnPrintf(pHlp,
5938	"%36s %.04s%.04s%.04s\n"
5939	"%36s 0x00000000-%#010x\n"
5940	,
5941	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
5942	"Supports:", paLeaves[0].uEax);
5943
5944	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
5945	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
5946
5947	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
5948	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5949
5950	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
5951	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5952
5953	pCurLeaf = pNextLeaf;
5954
5955	/*
5956	* Hypervisor leaves.
5957	*
5958	* Unlike most of the other leaves reported, the guest hypervisor leaves
5959	* aren't a subset of the host CPUID bits.
5960	*/
5961	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
5962
5963	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5964	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5965	#endif
5966	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
5967	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
5968	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
5969	cMax = RT_MAX(cHstMax, cGstMax);
5970	if (cMax >= UINT32_C(0x40000000))
5971	{
5972	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
5973
5974	/** @todo dump these in more detail. */
5975
5976	pCurLeaf = pNextLeaf;
5977	}
5978
5979
5980	/*
5981	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
5982	* Implemented after AMD specs.
5983	*/
5984	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
5985
5986	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5987	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5988	#endif
5989	cHstMax = RTX86IsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
5990	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
5991	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
5992	cMax = RT_MAX(cHstMax, cGstMax);
5993	if (cMax >= UINT32_C(0x80000000))
5994	{
5995
5996	pHlp->pfnPrintf(pHlp,
5997	" Raw Extended CPUID Leaves\n"
5998	" Leaf/sub-leaf eax ebx ecx edx\n");
5999	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6000	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6001	{
6002	uint32_t cMaxSubLeaves = 1;
6003	if (uLeaf == UINT32_C(0x8000001d))
6004	cMaxSubLeaves = 16;
6005
6006	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6007	{
6008	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6009	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6010	#endif
6011	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6012	&& pCurLeaf->uLeaf == uLeaf
6013	&& pCurLeaf->uSubLeaf == uSubLeaf)
6014	{
6015	pHlp->pfnPrintf(pHlp,
6016	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6017	"Hst: %08x %08x %08x %08x\n",
6018	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6019	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6020	pCurLeaf++;
6021	}
6022	else if ( uLeaf != 0xd
6023	\|\| uSubLeaf <= 1
6024	\|\| Host.uEbx != 0 )
6025	pHlp->pfnPrintf(pHlp,
6026	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6027	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6028
6029	/* Done? */
6030	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6031	\|\| pCurLeaf->uLeaf != uLeaf)
6032	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6033	break;
6034	}
6035	}
6036	pNextLeaf = pCurLeaf;
6037
6038	/*
6039	* Understandable output
6040	*/
6041	if (iVerbosity)
6042	pHlp->pfnPrintf(pHlp,
6043	"Ext Name: %.4s%.4s%.4s\n"
6044	"Ext Supports: 0x80000000-%#010x\n",
6045	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6046
6047	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6048	if (iVerbosity && pCurLeaf)
6049	{
6050	uint32_t uEAX = pCurLeaf->uEax;
6051	pHlp->pfnPrintf(pHlp,
6052	"Family: %d \tExtended: %d \tEffective: %d\n"
6053	"Model: %d \tExtended: %d \tEffective: %d\n"
6054	"Stepping: %d\n"
6055	"Brand ID: %#05x\n",
6056	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
6057	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
6058	RTX86GetCpuStepping(uEAX),
6059	pCurLeaf->uEbx & 0xfff);
6060
6061	if (iVerbosity == 1)
6062	{
6063	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6064	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6065	}
6066	else
6067	{
6068	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6069	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6070	#endif
6071	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6072	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6073	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6074	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6075	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
6076	{
6077	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
6078	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6079	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6080	#endif
6081	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
6082	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
6083	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
6084	}
6085	}
6086	}
6087
6088	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6089	{
6090	char szString[443+1] = {0};
6091	uint32_t pu32 = (uint32_t )szString;
6092	*pu32++ = pCurLeaf->uEax;
6093	*pu32++ = pCurLeaf->uEbx;
6094	*pu32++ = pCurLeaf->uEcx;
6095	*pu32++ = pCurLeaf->uEdx;
6096	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6097	if (pCurLeaf)
6098	{
6099	*pu32++ = pCurLeaf->uEax;
6100	*pu32++ = pCurLeaf->uEbx;
6101	*pu32++ = pCurLeaf->uEcx;
6102	*pu32++ = pCurLeaf->uEdx;
6103	}
6104	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6105	if (pCurLeaf)
6106	{
6107	*pu32++ = pCurLeaf->uEax;
6108	*pu32++ = pCurLeaf->uEbx;
6109	*pu32++ = pCurLeaf->uEcx;
6110	*pu32++ = pCurLeaf->uEdx;
6111	}
6112	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6113	}
6114
6115	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6116	{
6117	uint32_t uEAX = pCurLeaf->uEax;
6118	uint32_t uEBX = pCurLeaf->uEbx;
6119	uint32_t uECX = pCurLeaf->uEcx;
6120	uint32_t uEDX = pCurLeaf->uEdx;
6121	char sz1[32];
6122	char sz2[32];
6123
6124	pHlp->pfnPrintf(pHlp,
6125	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6126	"TLB 2/4M Data: %s %3d entries\n",
6127	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6128	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6129	pHlp->pfnPrintf(pHlp,
6130	"TLB 4K Instr/Uni: %s %3d entries\n"
6131	"TLB 4K Data: %s %3d entries\n",
6132	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6133	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6134	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6135	"L1 Instr Cache Lines Per Tag: %d\n"
6136	"L1 Instr Cache Associativity: %s\n"
6137	"L1 Instr Cache Size: %d KB\n",
6138	(uEDX >> 0) & 0xff,
6139	(uEDX >> 8) & 0xff,
6140	getCacheAss((uEDX >> 16) & 0xff, sz1),
6141	(uEDX >> 24) & 0xff);
6142	pHlp->pfnPrintf(pHlp,
6143	"L1 Data Cache Line Size: %d bytes\n"
6144	"L1 Data Cache Lines Per Tag: %d\n"
6145	"L1 Data Cache Associativity: %s\n"
6146	"L1 Data Cache Size: %d KB\n",
6147	(uECX >> 0) & 0xff,
6148	(uECX >> 8) & 0xff,
6149	getCacheAss((uECX >> 16) & 0xff, sz1),
6150	(uECX >> 24) & 0xff);
6151	}
6152
6153	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6154	{
6155	uint32_t uEAX = pCurLeaf->uEax;
6156	uint32_t uEBX = pCurLeaf->uEbx;
6157	uint32_t uECX = pCurLeaf->uEcx;
6158	uint32_t uEDX = pCurLeaf->uEdx;
6159
6160	pHlp->pfnPrintf(pHlp,
6161	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6162	"L2 TLB 2/4M Data: %s %4d entries\n",
6163	getL23CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6164	getL23CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6165	pHlp->pfnPrintf(pHlp,
6166	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6167	"L2 TLB 4K Data: %s %4d entries\n",
6168	getL23CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6169	getL23CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6170	pHlp->pfnPrintf(pHlp,
6171	"L2 Cache Line Size: %d bytes\n"
6172	"L2 Cache Lines Per Tag: %d\n"
6173	"L2 Cache Associativity: %s\n"
6174	"L2 Cache Size: %d KB\n",
6175	(uECX >> 0) & 0xff,
6176	(uECX >> 8) & 0xf,
6177	getL23CacheAss((uECX >> 12) & 0xf),
6178	(uECX >> 16) & 0xffff);
6179	pHlp->pfnPrintf(pHlp,
6180	"L3 Cache Line Size: %d bytes\n"
6181	"L3 Cache Lines Per Tag: %d\n"
6182	"L3 Cache Associativity: %s\n"
6183	"L3 Cache Size: %d KB\n",
6184	(uEDX >> 0) & 0xff,
6185	(uEDX >> 8) & 0xf,
6186	getL23CacheAss((uEDX >> 12) & 0xf),
6187	((uEDX >> 18) & 0x3fff) * 512);
6188	}
6189
6190	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
6191	{
6192	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6193	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6194	#endif
6195	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
6196	{
6197	if (iVerbosity < 1)
6198	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
6199	else
6200	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
6201	}
6202	}
6203
6204	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
6205	if (pCurLeaf != NULL)
6206	{
6207	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6208	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6209	#endif
6210	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
6211	{
6212	if (iVerbosity < 1)
6213	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
6214	else
6215	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
6216	}
6217
6218	if (iVerbosity)
6219	{
6220	uint32_t uEAX = pCurLeaf->uEax;
6221	uint32_t uECX = pCurLeaf->uEcx;
6222
6223	/** @todo 0x80000008:EAX[23:16] is only defined for AMD. We'll get 0 on Intel. On
6224	* AMD if we get 0, the guest physical address width should be taken from
6225	* 0x80000008:EAX[7:0] instead. Guest Physical address width is relevant
6226	* for guests using nested paging. */
6227	pHlp->pfnPrintf(pHlp,
6228	"Physical Address Width: %d bits\n"
6229	"Virtual Address Width: %d bits\n"
6230	"Guest Physical Address Width: %d bits\n",
6231	(uEAX >> 0) & 0xff,
6232	(uEAX >> 8) & 0xff,
6233	(uEAX >> 16) & 0xff);
6234
6235	/** @todo 0x80000008:ECX is reserved on Intel (we'll get incorrect physical core
6236	* count here). */
6237	pHlp->pfnPrintf(pHlp,
6238	"Physical Core Count: %d\n",
6239	((uECX >> 0) & 0xff) + 1);
6240	}
6241	}
6242
6243	pCurLeaf = pNextLeaf;
6244	}
6245
6246
6247
6248	/*
6249	* Centaur.
6250	*/
6251	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
6252
6253	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6254	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6255	#endif
6256	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
6257	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
6258	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
6259	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
6260	cMax = RT_MAX(cHstMax, cGstMax);
6261	if (cMax >= UINT32_C(0xc0000000))
6262	{
6263	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
6264
6265	/*
6266	* Understandable output
6267	*/
6268	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
6269	pHlp->pfnPrintf(pHlp,
6270	"Centaur Supports: 0xc0000000-%#010x\n",
6271	pCurLeaf->uEax);
6272
6273	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
6274	{
6275	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6276	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6277	#endif
6278	uint32_t uEdxGst = pCurLeaf->uEdx;
6279	uint32_t uEdxHst = Host.uEdx;
6280
6281	if (iVerbosity == 1)
6282	{
6283	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
6284	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
6285	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
6286	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
6287	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
6288	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
6289	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
6290	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
6291	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
6292	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6293	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
6294	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
6295	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
6296	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
6297	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
6298	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
6299	for (unsigned iBit = 14; iBit < 32; iBit++)
6300	if (uEdxGst & RT_BIT(iBit))
6301	pHlp->pfnPrintf(pHlp, " %d", iBit);
6302	pHlp->pfnPrintf(pHlp, "\n");
6303	}
6304	else
6305	{
6306	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
6307	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
6308	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
6309	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
6310	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
6311	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
6312	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
6313	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
6314	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
6315	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6316	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
6317	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
6318	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
6319	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
6320	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
6321	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
6322	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
6323	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
6324	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
6325	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
6326	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
6327	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
6328	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
6329	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
6330	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
6331	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
6332	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
6333	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
6334	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
6335	for (unsigned iBit = 27; iBit < 32; iBit++)
6336	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
6337	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
6338	pHlp->pfnPrintf(pHlp, "\n");
6339	}
6340	}
6341
6342	pCurLeaf = pNextLeaf;
6343	}
6344
6345	/*
6346	* The remainder.
6347	*/
6348	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
6349	}
6350
6351	#endif /* !IN_VBOX_CPU_REPORT */
6352

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 107570

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