CPUMR3CpuId.cpp@ 107650

Last change on this file since 107650 was 107650, checked in by vboxsync, 3 weeks ago
VMM/CPUM,++: Made the HostFeatures match the host when targeting x86 guests on arm64 hosts. Merged and deduplicated code targeting x86 & amd64. jiraref:VBP-1470
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1	/* $Id: CPUMR3CpuId.cpp 107650 2025-01-10 13:42:28Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_CPUM
33	#include <VBox/vmm/cpum.h>
34	#include <VBox/vmm/dbgf.h>
35	#include <VBox/vmm/hm.h>
36	#include <VBox/vmm/nem.h>
37	#include <VBox/vmm/ssm.h>
38	#include "CPUMInternal.h"
39	#include <VBox/vmm/vmcc.h>
40	#include <VBox/sup.h>
41
42	#include <VBox/err.h>
43	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
44	# include <iprt/asm-amd64-x86.h>
45	#endif
46	#include <iprt/ctype.h>
47	#include <iprt/mem.h>
48	#include <iprt/string.h>
49	#include <iprt/x86-helpers.h>
50
51
52	/*********************************************************************************************************************************
53	* Defined Constants And Macros *
54	*********************************************************************************************************************************/
55	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
56	#define CPUM_CPUID_MAX_LEAVES 2048
57
58
59	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
60	/**
61	* Determins the host CPU MXCSR mask.
62	*
63	* @returns MXCSR mask.
64	*/
65	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
66	{
67	if ( ASMHasCpuId()
68	&& RTX86IsValidStdRange(ASMCpuId_EAX(0))
69	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
70	{
71	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
72	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
73	RT_ZERO(*pState);
74	ASMFxSave(pState);
75	if (pState->MXCSR_MASK == 0)
76	return 0xffbf;
77	return pState->MXCSR_MASK;
78	}
79	return 0;
80	}
81	#endif
82
83
84
85	#ifndef IN_VBOX_CPU_REPORT
86	/**
87	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
88	*
89	* @returns true if found, false it not.
90	* @param paLeaves The CPUID leaves to search. This is sorted.
91	* @param cLeaves The number of leaves in the array.
92	* @param uLeaf The leaf to locate.
93	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
94	* @param pLegacy The legacy output leaf.
95	*/
96	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
97	PCPUMCPUID pLegacy)
98	{
99	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, uLeaf, uSubLeaf);
100	if (pLeaf)
101	{
102	pLegacy->uEax = pLeaf->uEax;
103	pLegacy->uEbx = pLeaf->uEbx;
104	pLegacy->uEcx = pLeaf->uEcx;
105	pLegacy->uEdx = pLeaf->uEdx;
106	return true;
107	}
108	return false;
109	}
110	#endif /* IN_VBOX_CPU_REPORT */
111
112
113	/**
114	* Inserts a CPU ID leaf, replacing any existing ones.
115	*
116	* When inserting a simple leaf where we already got a series of sub-leaves with
117	* the same leaf number (eax), the simple leaf will replace the whole series.
118	*
119	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
120	* host-context heap and has only been allocated/reallocated by the
121	* cpumCpuIdEnsureSpace function.
122	*
123	* @returns VBox status code.
124	* @param pVM The cross context VM structure. If NULL, use
125	* the process heap, otherwise the VM's hyper heap.
126	* @param ppaLeaves Pointer to the pointer to the array of sorted
127	* CPUID leaves and sub-leaves. Must be NULL if using
128	* the hyper heap.
129	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
130	* be NULL if using the hyper heap.
131	* @param pNewLeaf Pointer to the data of the new leaf we're about to
132	* insert.
133	*/
134	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
135	{
136	/*
137	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
138	*/
139	if (pVM)
140	{
141	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
142	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
143	AssertReturn(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 == pVM->cpum.s.GuestInfo.aCpuIdLeaves, VERR_INVALID_PARAMETER);
144
145	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
146	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
147	}
148
149	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
150	uint32_t cLeaves = *pcLeaves;
151
152	/*
153	* Validate the new leaf a little.
154	*/
155	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
156	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
157	VERR_INVALID_FLAGS);
158	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
159	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
160	VERR_INVALID_PARAMETER);
161	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
162	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
163	VERR_INVALID_PARAMETER);
164	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
165	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
166	VERR_INVALID_PARAMETER);
167
168	/*
169	* Find insertion point. The lazy bird uses the same excuse as in
170	* cpumCpuIdGetLeaf(), but optimizes for linear insertion (saved state).
171	*/
172	uint32_t i;
173	if ( cLeaves > 0
174	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
175	{
176	/* Add at end. */
177	i = cLeaves;
178	}
179	else if ( cLeaves > 0
180	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
181	{
182	/* Either replacing the last leaf or dealing with sub-leaves. Spool
183	back to the first sub-leaf to pretend we did the linear search. */
184	i = cLeaves - 1;
185	while ( i > 0
186	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
187	i--;
188	}
189	else
190	{
191	/* Linear search from the start. */
192	i = 0;
193	while ( i < cLeaves
194	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
195	i++;
196	}
197	if ( i < cLeaves
198	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
199	{
200	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
201	{
202	/*
203	* The sub-leaf mask differs, replace all existing leaves with the
204	* same leaf number.
205	*/
206	uint32_t c = 1;
207	while ( i + c < cLeaves
208	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
209	c++;
210	if (c > 1 && i + c < cLeaves)
211	{
212	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
213	*pcLeaves = cLeaves -= c - 1;
214	}
215
216	paLeaves[i] = *pNewLeaf;
217	#ifdef VBOX_STRICT
218	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
219	#endif
220	return VINF_SUCCESS;
221	}
222
223	/* Find sub-leaf insertion point. */
224	while ( i < cLeaves
225	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
226	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
227	i++;
228
229	/*
230	* If we've got an exactly matching leaf, replace it.
231	*/
232	if ( i < cLeaves
233	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
234	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
235	{
236	paLeaves[i] = *pNewLeaf;
237	#ifdef VBOX_STRICT
238	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
239	#endif
240	return VINF_SUCCESS;
241	}
242	}
243
244	/*
245	* Adding a new leaf at 'i'.
246	*/
247	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
248	paLeaves = cpumCpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
249	if (!paLeaves)
250	return VERR_NO_MEMORY;
251
252	if (i < cLeaves)
253	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
254	*pcLeaves += 1;
255	paLeaves[i] = *pNewLeaf;
256
257	#ifdef VBOX_STRICT
258	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
259	#endif
260	return VINF_SUCCESS;
261	}
262
263
264	#ifndef IN_VBOX_CPU_REPORT
265	/**
266	* Removes a range of CPUID leaves.
267	*
268	* This will not reallocate the array.
269	*
270	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
271	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
272	* @param uFirst The first leaf.
273	* @param uLast The last leaf.
274	*/
275	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
276	{
277	uint32_t cLeaves = *pcLeaves;
278
279	Assert(uFirst <= uLast);
280
281	/*
282	* Find the first one.
283	*/
284	uint32_t iFirst = 0;
285	while ( iFirst < cLeaves
286	&& paLeaves[iFirst].uLeaf < uFirst)
287	iFirst++;
288
289	/*
290	* Find the end (last + 1).
291	*/
292	uint32_t iEnd = iFirst;
293	while ( iEnd < cLeaves
294	&& paLeaves[iEnd].uLeaf <= uLast)
295	iEnd++;
296
297	/*
298	* Adjust the array if anything needs removing.
299	*/
300	if (iFirst < iEnd)
301	{
302	if (iEnd < cLeaves)
303	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
304	*pcLeaves = cLeaves -= (iEnd - iFirst);
305	}
306
307	# ifdef VBOX_STRICT
308	cpumCpuIdAssertOrder(paLeaves, *pcLeaves);
309	# endif
310	}
311	#endif /* IN_VBOX_CPU_REPORT */
312
313
314	/**
315	* Gets a CPU ID leaf.
316	*
317	* @returns VBox status code.
318	* @param pVM The cross context VM structure.
319	* @param pLeaf Where to store the found leaf.
320	* @param uLeaf The leaf to locate.
321	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
322	*/
323	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
324	{
325	PCPUMCPUIDLEAF pcLeaf = cpumCpuIdGetLeafInt(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
326	uLeaf, uSubLeaf);
327	if (pcLeaf)
328	{
329	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
330	return VINF_SUCCESS;
331	}
332
333	return VERR_NOT_FOUND;
334	}
335
336
337	/**
338	* Gets all the leaves.
339	*
340	* This only works after the CPUID leaves have been initialized. The interface
341	* is intended for NEM and configuring CPUID leaves for the native hypervisor.
342	*
343	* @returns Pointer to the array of leaves. NULL on failure.
344	* @param pVM The cross context VM structure.
345	* @param pcLeaves Where to return the number of leaves.
346	*/
347	VMMR3_INT_DECL(PCCPUMCPUIDLEAF) CPUMR3CpuIdGetPtr(PVM pVM, uint32_t *pcLeaves)
348	{
349	*pcLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
350	return pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
351	}
352
353
354	/**
355	* Inserts a CPU ID leaf, replacing any existing ones.
356	*
357	* @returns VBox status code.
358	* @param pVM The cross context VM structure.
359	* @param pNewLeaf Pointer to the leaf being inserted.
360	*/
361	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
362	{
363	/*
364	* Validate parameters.
365	*/
366	AssertReturn(pVM, VERR_INVALID_PARAMETER);
367	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
368
369	/*
370	* Disallow replacing CPU ID leaves that this API currently cannot manage.
371	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
372	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
373	*/
374	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
375	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
376	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
377	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
378	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
379	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
380	{
381	return VERR_NOT_SUPPORTED;
382	}
383
384	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
385	}
386
387
388	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
389	/**
390	* Determines the method the CPU uses to handle unknown CPUID leaves.
391	*
392	* @returns VBox status code.
393	* @param penmUnknownMethod Where to return the method.
394	* @param pDefUnknown Where to return default unknown values. This
395	* will be set, even if the resulting method
396	* doesn't actually needs it.
397	*/
398	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
399	{
400	uint32_t uLastStd = ASMCpuId_EAX(0);
401	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
402	if (!RTX86IsValidExtRange(uLastExt))
403	uLastExt = 0x80000000;
404
405	uint32_t auChecks[] =
406	{
407	uLastStd + 1,
408	uLastStd + 5,
409	uLastStd + 8,
410	uLastStd + 32,
411	uLastStd + 251,
412	uLastExt + 1,
413	uLastExt + 8,
414	uLastExt + 15,
415	uLastExt + 63,
416	uLastExt + 255,
417	0x7fbbffcc,
418	0x833f7872,
419	0xefff2353,
420	0x35779456,
421	0x1ef6d33e,
422	};
423
424	static const uint32_t s_auValues[] =
425	{
426	0xa95d2156,
427	0x00000001,
428	0x00000002,
429	0x00000008,
430	0x00000000,
431	0x55773399,
432	0x93401769,
433	0x12039587,
434	};
435
436	/*
437	* Simple method, all zeros.
438	*/
439	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
440	pDefUnknown->uEax = 0;
441	pDefUnknown->uEbx = 0;
442	pDefUnknown->uEcx = 0;
443	pDefUnknown->uEdx = 0;
444
445	/*
446	* Intel has been observed returning the last standard leaf.
447	*/
448	uint32_t auLast[4];
449	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
450
451	uint32_t cChecks = RT_ELEMENTS(auChecks);
452	while (cChecks > 0)
453	{
454	uint32_t auCur[4];
455	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
456	if (memcmp(auCur, auLast, sizeof(auCur)))
457	break;
458	cChecks--;
459	}
460	if (cChecks == 0)
461	{
462	/* Now, what happens when the input changes? Esp. ECX. */
463	uint32_t cTotal = 0;
464	uint32_t cSame = 0;
465	uint32_t cLastWithEcx = 0;
466	uint32_t cNeither = 0;
467	uint32_t cValues = RT_ELEMENTS(s_auValues);
468	while (cValues > 0)
469	{
470	uint32_t uValue = s_auValues[cValues - 1];
471	uint32_t auLastWithEcx[4];
472	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
473	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
474
475	cChecks = RT_ELEMENTS(auChecks);
476	while (cChecks > 0)
477	{
478	uint32_t auCur[4];
479	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
480	if (!memcmp(auCur, auLast, sizeof(auCur)))
481	{
482	cSame++;
483	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
484	cLastWithEcx++;
485	}
486	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
487	cLastWithEcx++;
488	else
489	cNeither++;
490	cTotal++;
491	cChecks--;
492	}
493	cValues--;
494	}
495
496	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
497	if (cSame == cTotal)
498	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
499	else if (cLastWithEcx == cTotal)
500	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
501	else
502	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
503	pDefUnknown->uEax = auLast[0];
504	pDefUnknown->uEbx = auLast[1];
505	pDefUnknown->uEcx = auLast[2];
506	pDefUnknown->uEdx = auLast[3];
507	return VINF_SUCCESS;
508	}
509
510	/*
511	* Unchanged register values?
512	*/
513	cChecks = RT_ELEMENTS(auChecks);
514	while (cChecks > 0)
515	{
516	uint32_t const uLeaf = auChecks[cChecks - 1];
517	uint32_t cValues = RT_ELEMENTS(s_auValues);
518	while (cValues > 0)
519	{
520	uint32_t uValue = s_auValues[cValues - 1];
521	uint32_t auCur[4];
522	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
523	if ( auCur[0] != uLeaf
524	\|\| auCur[1] != uValue
525	\|\| auCur[2] != uValue
526	\|\| auCur[3] != uValue)
527	break;
528	cValues--;
529	}
530	if (cValues != 0)
531	break;
532	cChecks--;
533	}
534	if (cChecks == 0)
535	{
536	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
537	return VINF_SUCCESS;
538	}
539
540	/*
541	* Just go with the simple method.
542	*/
543	return VINF_SUCCESS;
544	}
545	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
546
547
548	/**
549	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
550	*
551	* @returns Read only name string.
552	* @param enmUnknownMethod The method to translate.
553	*/
554	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
555	{
556	switch (enmUnknownMethod)
557	{
558	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
559	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
560	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
561	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
562
563	case CPUMUNKNOWNCPUID_INVALID:
564	case CPUMUNKNOWNCPUID_END:
565	case CPUMUNKNOWNCPUID_32BIT_HACK:
566	break;
567	}
568	return "Invalid-unknown-CPUID-method";
569	}
570
571
572	/*
573	*
574	* Init related code.
575	* Init related code.
576	* Init related code.
577	*
578	*
579	*/
580	#ifndef IN_VBOX_CPU_REPORT
581
582
583	/**
584	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
585	*
586	* This ignores the fSubLeafMask.
587	*
588	* @returns Pointer to the matching leaf, or NULL if not found.
589	* @param pCpum The CPUM instance data.
590	* @param uLeaf The leaf to locate.
591	* @param uSubLeaf The subleaf to locate.
592	*/
593	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
594	{
595	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
596	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
597	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
598	if (iEnd)
599	{
600	uint32_t iBegin = 0;
601	for (;;)
602	{
603	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
604	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
605	if (uNeedle < uCur)
606	{
607	if (i > iBegin)
608	iEnd = i;
609	else
610	break;
611	}
612	else if (uNeedle > uCur)
613	{
614	if (i + 1 < iEnd)
615	iBegin = i + 1;
616	else
617	break;
618	}
619	else
620	return &paLeaves[i];
621	}
622	}
623	return NULL;
624	}
625
626
627	/**
628	* Loads MSR range overrides.
629	*
630	* This must be called before the MSR ranges are moved from the normal heap to
631	* the hyper heap!
632	*
633	* @returns VBox status code (VMSetError called).
634	* @param pVM The cross context VM structure.
635	* @param pMsrNode The CFGM node with the MSR overrides.
636	*/
637	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
638	{
639	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
640	{
641	/*
642	* Assemble a valid MSR range.
643	*/
644	CPUMMSRRANGE MsrRange;
645	MsrRange.offCpumCpu = 0;
646	MsrRange.fReserved = 0;
647
648	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
649	if (RT_FAILURE(rc))
650	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
651
652	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
653	if (RT_FAILURE(rc))
654	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
655	MsrRange.szName, rc);
656
657	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
658	if (RT_FAILURE(rc))
659	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
660	MsrRange.szName, rc);
661
662	char szType[32];
663	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
664	if (RT_FAILURE(rc))
665	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
666	MsrRange.szName, rc);
667	if (!RTStrICmp(szType, "FixedValue"))
668	{
669	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
670	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
671
672	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
673	if (RT_FAILURE(rc))
674	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
675	MsrRange.szName, rc);
676
677	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
678	if (RT_FAILURE(rc))
679	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
680	MsrRange.szName, rc);
681
682	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
683	if (RT_FAILURE(rc))
684	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
685	MsrRange.szName, rc);
686	}
687	else
688	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
689	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
690
691	/*
692	* Insert the range into the table (replaces/splits/shrinks existing
693	* MSR ranges).
694	*/
695	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
696	&MsrRange);
697	if (RT_FAILURE(rc))
698	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
699	}
700
701	return VINF_SUCCESS;
702	}
703
704
705	/**
706	* Loads CPUID leaf overrides.
707	*
708	* This must be called before the CPUID leaves are moved from the normal
709	* heap to the hyper heap!
710	*
711	* @returns VBox status code (VMSetError called).
712	* @param pVM The cross context VM structure.
713	* @param pParentNode The CFGM node with the CPUID leaves.
714	* @param pszLabel How to label the overrides we're loading.
715	*/
716	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
717	{
718	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
719	{
720	/*
721	* Get the leaf and subleaf numbers.
722	*/
723	char szName[128];
724	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
725	if (RT_FAILURE(rc))
726	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
727
728	/* The leaf number is either specified directly or thru the node name. */
729	uint32_t uLeaf;
730	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
731	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
732	{
733	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
734	if (rc != VINF_SUCCESS)
735	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
736	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
737	}
738	else if (RT_FAILURE(rc))
739	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
740	pszLabel, szName, rc);
741
742	uint32_t uSubLeaf;
743	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
744	if (RT_FAILURE(rc))
745	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
746	pszLabel, szName, rc);
747
748	uint32_t fSubLeafMask;
749	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
750	if (RT_FAILURE(rc))
751	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
752	pszLabel, szName, rc);
753
754	/*
755	* Look up the specified leaf, since the output register values
756	* defaults to any existing values. This allows overriding a single
757	* register, without needing to know the other values.
758	*/
759	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
760	CPUMCPUIDLEAF Leaf;
761	if (pLeaf)
762	Leaf = *pLeaf;
763	else
764	RT_ZERO(Leaf);
765	Leaf.uLeaf = uLeaf;
766	Leaf.uSubLeaf = uSubLeaf;
767	Leaf.fSubLeafMask = fSubLeafMask;
768
769	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
770	if (RT_FAILURE(rc))
771	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
772	pszLabel, szName, rc);
773	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
774	if (RT_FAILURE(rc))
775	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
776	pszLabel, szName, rc);
777	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
778	if (RT_FAILURE(rc))
779	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
780	pszLabel, szName, rc);
781	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
782	if (RT_FAILURE(rc))
783	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
784	pszLabel, szName, rc);
785
786	/*
787	* Insert the leaf into the table (replaces existing ones).
788	*/
789	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
790	&Leaf);
791	if (RT_FAILURE(rc))
792	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
793	}
794
795	return VINF_SUCCESS;
796	}
797
798
799
800	/**
801	* Fetches overrides for a CPUID leaf.
802	*
803	* @returns VBox status code.
804	* @param pLeaf The leaf to load the overrides into.
805	* @param pCfgNode The CFGM node containing the overrides
806	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
807	* @param iLeaf The CPUID leaf number.
808	*/
809	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
810	{
811	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
812	if (pLeafNode)
813	{
814	uint32_t u32;
815	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
816	if (RT_SUCCESS(rc))
817	pLeaf->uEax = u32;
818	else
819	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
820
821	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
822	if (RT_SUCCESS(rc))
823	pLeaf->uEbx = u32;
824	else
825	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
826
827	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
828	if (RT_SUCCESS(rc))
829	pLeaf->uEcx = u32;
830	else
831	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
832
833	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
834	if (RT_SUCCESS(rc))
835	pLeaf->uEdx = u32;
836	else
837	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
838
839	}
840	return VINF_SUCCESS;
841	}
842
843
844	/**
845	* Load the overrides for a set of CPUID leaves.
846	*
847	* @returns VBox status code.
848	* @param paLeaves The leaf array.
849	* @param cLeaves The number of leaves.
850	* @param uStart The start leaf number.
851	* @param pCfgNode The CFGM node containing the overrides
852	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
853	*/
854	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
855	{
856	for (uint32_t i = 0; i < cLeaves; i++)
857	{
858	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
859	if (RT_FAILURE(rc))
860	return rc;
861	}
862
863	return VINF_SUCCESS;
864	}
865
866
867	/**
868	* Installs the CPUID leaves and explods the data into structures like
869	* GuestFeatures and CPUMCTX::aoffXState.
870	*
871	* @returns VBox status code.
872	* @param pVM The cross context VM structure.
873	* @param pCpum The CPUM part of @a VM.
874	* @param paLeaves The leaves. These will be copied (but not freed).
875	* @param cLeaves The number of leaves.
876	* @param pMsrs The MSRs.
877	*/
878	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
879	{
880	# ifdef VBOX_STRICT
881	cpumCpuIdAssertOrder(paLeaves, cLeaves);
882	# endif
883
884	/*
885	* Install the CPUID information.
886	*/
887	AssertLogRelMsgReturn(cLeaves <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves),
888	("cLeaves=%u - max %u\n", cLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves)),
889	VERR_CPUM_IPE_1); /** @todo better status! */
890	if (paLeaves != pCpum->GuestInfo.aCpuIdLeaves)
891	memcpy(pCpum->GuestInfo.aCpuIdLeaves, paLeaves, cLeaves * sizeof(paLeaves[0]));
892	pCpum->GuestInfo.paCpuIdLeavesR3 = pCpum->GuestInfo.aCpuIdLeaves;
893	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
894
895	/*
896	* Update the default CPUID leaf if necessary.
897	*/
898	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
899	{
900	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
901	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
902	{
903	/* We don't use CPUID(0).eax here because of the NT hack that only
904	changes that value without actually removing any leaves. */
905	uint32_t i = 0;
906	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
907	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
908	{
909	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
910	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
911	i++;
912	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
913	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
914	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
915	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
916	}
917	break;
918	}
919	default:
920	break;
921	}
922
923	/*
924	* Explode the guest CPU features.
925	*/
926	int rc = cpumCpuIdExplodeFeaturesX86(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
927	&pCpum->GuestFeatures);
928	AssertLogRelRCReturn(rc, rc);
929
930	/*
931	* Adjust the scalable bus frequency according to the CPUID information
932	* we're now using.
933	*/
934	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
935	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
936	? UINT64_C(100000000) /* 100MHz */
937	: UINT64_C(133333333); /* 133MHz */
938
939	/*
940	* Populate the legacy arrays. Currently used for everything, later only
941	* for patch manager.
942	*/
943	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
944	{
945	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
946	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
947	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
948	};
949	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
950	{
951	uint32_t cLeft = aOldRanges[i].cCpuIds;
952	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
953	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
954	while (cLeft-- > 0)
955	{
956	uLeaf--;
957	pLegacyLeaf--;
958
959	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
960	if (pLeaf)
961	{
962	pLegacyLeaf->uEax = pLeaf->uEax;
963	pLegacyLeaf->uEbx = pLeaf->uEbx;
964	pLegacyLeaf->uEcx = pLeaf->uEcx;
965	pLegacyLeaf->uEdx = pLeaf->uEdx;
966	}
967	else
968	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
969	}
970	}
971
972	/*
973	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
974	*/
975	PVMCPU pVCpu0 = pVM->apCpusR3[0];
976	AssertCompile(sizeof(pVCpu0->cpum.s.Guest.abXState) == CPUM_MAX_XSAVE_AREA_SIZE);
977	memset(&pVCpu0->cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVCpu0->cpum.s.Guest.aoffXState));
978	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
979	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
980	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
981	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
982	{
983	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
984	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
985	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
986	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
987	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
988	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
989	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
990	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
991	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
992	pCpum->GuestFeatures.cbMaxExtendedState),
993	VERR_CPUM_IPE_1);
994	pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
995	}
996
997	/* Copy the CPU #0 data to the other CPUs. */
998	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
999	{
1000	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1001	memcpy(&pVCpu->cpum.s.Guest.aoffXState[0], &pVCpu0->cpum.s.Guest.aoffXState[0], sizeof(pVCpu0->cpum.s.Guest.aoffXState));
1002	}
1003
1004	return VINF_SUCCESS;
1005	}
1006
1007
1008	/** @name Instruction Set Extension Options
1009	* @{ */
1010	/** Configuration option type (extended boolean, really). */
1011	typedef uint8_t CPUMISAEXTCFG;
1012	/** Always disable the extension. */
1013	#define CPUMISAEXTCFG_DISABLED false
1014	/** Enable the extension if it's supported by the host CPU. */
1015	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
1016	/** Enable the extension if it's supported by the host CPU or when on ARM64. */
1017	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1018	# define CPUMISAEXTCFG_ENABLED_SUPPORTED_OR_NOT_AMD64 CPUMISAEXTCFG_ENABLED_SUPPORTED
1019	#else
1020	# define CPUMISAEXTCFG_ENABLED_SUPPORTED_OR_NOT_AMD64 CPUMISAEXTCFG_ENABLED_ALWAYS
1021	#endif
1022	/** Enable the extension if it's supported by the host CPU, but don't let
1023	* the portable CPUID feature disable it. */
1024	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
1025	/** Always enable the extension. */
1026	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
1027	/** @} */
1028
1029	/**
1030	* CPUID Configuration (from CFGM).
1031	*
1032	* @remarks The members aren't document since we would only be duplicating the
1033	* \@cfgm entries in cpumR3CpuIdReadConfig.
1034	*/
1035	typedef struct CPUMCPUIDCONFIG
1036	{
1037	bool fNt4LeafLimit;
1038	bool fInvariantTsc;
1039	bool fInvariantApic;
1040	bool fForceVme;
1041	bool fNestedHWVirt;
1042
1043	CPUMISAEXTCFG enmCmpXchg16b;
1044	CPUMISAEXTCFG enmMonitor;
1045	CPUMISAEXTCFG enmMWaitExtensions;
1046	CPUMISAEXTCFG enmSse41;
1047	CPUMISAEXTCFG enmSse42;
1048	CPUMISAEXTCFG enmAvx;
1049	CPUMISAEXTCFG enmAvx2;
1050	CPUMISAEXTCFG enmXSave;
1051	CPUMISAEXTCFG enmAesNi;
1052	CPUMISAEXTCFG enmPClMul;
1053	CPUMISAEXTCFG enmPopCnt;
1054	CPUMISAEXTCFG enmMovBe;
1055	CPUMISAEXTCFG enmRdRand;
1056	CPUMISAEXTCFG enmRdSeed;
1057	CPUMISAEXTCFG enmSha;
1058	CPUMISAEXTCFG enmAdx;
1059	CPUMISAEXTCFG enmCLFlushOpt;
1060	CPUMISAEXTCFG enmFsGsBase;
1061	CPUMISAEXTCFG enmPcid;
1062	CPUMISAEXTCFG enmInvpcid;
1063	CPUMISAEXTCFG enmFlushCmdMsr;
1064	CPUMISAEXTCFG enmMdsClear;
1065	CPUMISAEXTCFG enmArchCapMsr;
1066	CPUMISAEXTCFG enmFma;
1067	CPUMISAEXTCFG enmF16c;
1068
1069	CPUMISAEXTCFG enmAbm;
1070	CPUMISAEXTCFG enmSse4A;
1071	CPUMISAEXTCFG enmMisAlnSse;
1072	CPUMISAEXTCFG enm3dNowPrf;
1073	CPUMISAEXTCFG enmAmdExtMmx;
1074
1075	uint32_t uMaxStdLeaf;
1076	uint32_t uMaxExtLeaf;
1077	uint32_t uMaxCentaurLeaf;
1078	uint32_t uMaxIntelFamilyModelStep;
1079	char szCpuName[128];
1080	} CPUMCPUIDCONFIG;
1081	/** Pointer to CPUID config (from CFGM). */
1082	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
1083
1084
1085	/**
1086	* Mini CPU selection support for making Mac OS X happy.
1087	*
1088	* Executes the /CPUM/MaxIntelFamilyModelStep config.
1089	*
1090	* @param pCpum The CPUM instance data.
1091	* @param pConfig The CPUID configuration we've read from CFGM.
1092	*/
1093	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1094	{
1095	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1096	{
1097	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1098	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(RTX86GetCpuStepping(pStdFeatureLeaf->uEax),
1099	RTX86GetCpuModelIntel(pStdFeatureLeaf->uEax),
1100	RTX86GetCpuFamily(pStdFeatureLeaf->uEax),
1101	0);
1102	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
1103	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
1104	{
1105	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
1106	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
1107	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
1108	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
1109	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
1110	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
1111	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
1112	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
1113	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
1114	pStdFeatureLeaf->uEax = uNew;
1115	}
1116	}
1117	}
1118
1119
1120
1121	/**
1122	* Limit it the number of entries, zapping the remainder.
1123	*
1124	* The limits are masking off stuff about power saving and similar, this
1125	* is perhaps a bit crudely done as there is probably some relatively harmless
1126	* info too in these leaves (like words about having a constant TSC).
1127	*
1128	* @param pCpum The CPUM instance data.
1129	* @param pConfig The CPUID configuration we've read from CFGM.
1130	*/
1131	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1132	{
1133	/*
1134	* Standard leaves.
1135	*/
1136	uint32_t uSubLeaf = 0;
1137	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
1138	if (pCurLeaf)
1139	{
1140	uint32_t uLimit = pCurLeaf->uEax;
1141	if (uLimit <= UINT32_C(0x000fffff))
1142	{
1143	if (uLimit > pConfig->uMaxStdLeaf)
1144	{
1145	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
1146	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1147	uLimit + 1, UINT32_C(0x000fffff));
1148	}
1149
1150	/* NT4 hack, no zapping of extra leaves here. */
1151	if (pConfig->fNt4LeafLimit && uLimit > 3)
1152	pCurLeaf->uEax = uLimit = 3;
1153
1154	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
1155	pCurLeaf->uEax = uLimit;
1156	}
1157	else
1158	{
1159	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
1160	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1161	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
1162	}
1163	}
1164
1165	/*
1166	* Extended leaves.
1167	*/
1168	uSubLeaf = 0;
1169	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
1170	if (pCurLeaf)
1171	{
1172	uint32_t uLimit = pCurLeaf->uEax;
1173	if ( uLimit >= UINT32_C(0x80000000)
1174	&& uLimit <= UINT32_C(0x800fffff))
1175	{
1176	if (uLimit > pConfig->uMaxExtLeaf)
1177	{
1178	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
1179	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1180	uLimit + 1, UINT32_C(0x800fffff));
1181	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
1182	pCurLeaf->uEax = uLimit;
1183	}
1184	}
1185	else
1186	{
1187	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
1188	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1189	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
1190	}
1191	}
1192
1193	/*
1194	* Centaur leaves (VIA).
1195	*/
1196	uSubLeaf = 0;
1197	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
1198	if (pCurLeaf)
1199	{
1200	uint32_t uLimit = pCurLeaf->uEax;
1201	if ( uLimit >= UINT32_C(0xc0000000)
1202	&& uLimit <= UINT32_C(0xc00fffff))
1203	{
1204	if (uLimit > pConfig->uMaxCentaurLeaf)
1205	{
1206	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
1207	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1208	uLimit + 1, UINT32_C(0xcfffffff));
1209	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
1210	pCurLeaf->uEax = uLimit;
1211	}
1212	}
1213	else
1214	{
1215	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
1216	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1217	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
1218	}
1219	}
1220	}
1221
1222
1223	/**
1224	* Clears a CPUID leaf and all sub-leaves (to zero).
1225	*
1226	* @param pCpum The CPUM instance data.
1227	* @param uLeaf The leaf to clear.
1228	*/
1229	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
1230	{
1231	uint32_t uSubLeaf = 0;
1232	PCPUMCPUIDLEAF pCurLeaf;
1233	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
1234	{
1235	pCurLeaf->uEax = 0;
1236	pCurLeaf->uEbx = 0;
1237	pCurLeaf->uEcx = 0;
1238	pCurLeaf->uEdx = 0;
1239	uSubLeaf++;
1240	}
1241	}
1242
1243
1244	/**
1245	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
1246	* the given leaf.
1247	*
1248	* @returns pLeaf.
1249	* @param pCpum The CPUM instance data.
1250	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
1251	*/
1252	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
1253	{
1254	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
1255	if (pLeaf->fSubLeafMask != 0)
1256	{
1257	/*
1258	* Figure out how many sub-leaves in need of removal (we'll keep the first).
1259	* Log everything while we're at it.
1260	*/
1261	LogRel(("CPUM:\n"
1262	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
1263	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
1264	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
1265	for (;;)
1266	{
1267	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
1268	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
1269	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
1270	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
1271	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
1272	break;
1273	pSubLeaf++;
1274	}
1275	LogRel(("CPUM:\n"));
1276
1277	/*
1278	* Remove the offending sub-leaves.
1279	*/
1280	if (pSubLeaf != pLeaf)
1281	{
1282	if (pSubLeaf != pLast)
1283	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
1284	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
1285	}
1286
1287	/*
1288	* Convert the first sub-leaf into a single leaf.
1289	*/
1290	pLeaf->uSubLeaf = 0;
1291	pLeaf->fSubLeafMask = 0;
1292	}
1293	return pLeaf;
1294	}
1295
1296
1297	/**
1298	* Sanitizes and adjust the CPUID leaves.
1299	*
1300	* Drop features that aren't virtualized (or virtualizable). Adjust information
1301	* and capabilities to fit the virtualized hardware. Remove information the
1302	* guest shouldn't have (because it's wrong in the virtual world or because it
1303	* gives away host details) or that we don't have documentation for and no idea
1304	* what means.
1305	*
1306	* @returns VBox status code.
1307	* @param pVM The cross context VM structure (for cCpus).
1308	* @param pCpum The CPUM instance data.
1309	* @param pConfig The CPUID configuration we've read from CFGM.
1310	*/
1311	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1312	{
1313	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
1314	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
1315	{ \
1316	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
1317	(a_pLeafReg) &= ~(uint32_t)(fMask); \
1318	}
1319	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
1320	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
1321	{ \
1322	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
1323	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
1324	}
1325	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
1326	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
1327	&& ((a_pLeafReg) & (fBitMask)) \
1328	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
1329	{ \
1330	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
1331	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
1332	}
1333	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
1334
1335	/* The CPUID entries we start with here isn't necessarily the ones of the host, so we
1336	must consult HostFeatures when processing CPUMISAEXTCFG variables. */
1337	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1338	PCCPUMFEATURES const pHstFeat = &pCpum->HostFeatures.s;
1339	#else
1340	PCCPUMFEATURES const pHstFeat = &pCpum->GuestFeatures;
1341	#endif
1342	#define PASSTHRU_FEATURE(enmConfig, fHostFeature, fConst) \
1343	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) ? (fConst) : 0)
1344	#define PASSTHRU_FEATURE_EX(enmConfig, fHostFeature, fAndExpr, fConst) \
1345	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) && (fAndExpr) ? (fConst) : 0)
1346	#define PASSTHRU_FEATURE_NOT_IEM(enmConfig, fHostFeature, fConst) \
1347	PASSTHRU_FEATURE_EX(enmConfig, fHostFeature, !VM_IS_EXEC_ENGINE_IEM(pVM), fConst)
1348	#define PASSTHRU_FEATURE_TODO(enmConfig, fConst) ((enmConfig) ? (fConst) : 0)
1349
1350	/* Cpuid 1:
1351	* EAX: CPU model, family and stepping.
1352	*
1353	* ECX + EDX: Supported features. Only report features we can support.
1354	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1355	* options may require adjusting (i.e. stripping what was enabled).
1356	*
1357	* EBX: Branding, CLFLUSH line size, logical processors per package and
1358	* initial APIC ID.
1359	*/
1360	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
1361	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
1362	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
1363
1364	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
1365	\| X86_CPUID_FEATURE_EDX_VME
1366	\| X86_CPUID_FEATURE_EDX_DE
1367	\| X86_CPUID_FEATURE_EDX_PSE
1368	\| X86_CPUID_FEATURE_EDX_TSC
1369	\| X86_CPUID_FEATURE_EDX_MSR
1370	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
1371	\| X86_CPUID_FEATURE_EDX_MCE
1372	\| X86_CPUID_FEATURE_EDX_CX8
1373	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
1374	//\| RT_BIT_32(10) - not defined
1375	\| X86_CPUID_FEATURE_EDX_SEP
1376	\| X86_CPUID_FEATURE_EDX_MTRR
1377	\| X86_CPUID_FEATURE_EDX_PGE
1378	\| X86_CPUID_FEATURE_EDX_MCA
1379	\| X86_CPUID_FEATURE_EDX_CMOV
1380	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
1381	\| X86_CPUID_FEATURE_EDX_PSE36
1382	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
1383	\| X86_CPUID_FEATURE_EDX_CLFSH
1384	//\| RT_BIT_32(20) - not defined
1385	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
1386	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
1387	\| X86_CPUID_FEATURE_EDX_MMX
1388	\| X86_CPUID_FEATURE_EDX_FXSR
1389	\| X86_CPUID_FEATURE_EDX_SSE
1390	\| X86_CPUID_FEATURE_EDX_SSE2
1391	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
1392	\| X86_CPUID_FEATURE_EDX_HTT
1393	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
1394	//\| RT_BIT_32(30) - not defined
1395	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
1396	;
1397	pStdFeatureLeaf->uEcx &= X86_CPUID_FEATURE_ECX_SSE3
1398	\| PASSTHRU_FEATURE_TODO(pConfig->enmPClMul, X86_CPUID_FEATURE_ECX_PCLMUL)
1399	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
1400	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
1401	\| PASSTHRU_FEATURE_EX(pConfig->enmMonitor, pHstFeat->fMonitorMWait, pVM->cCpus == 1, X86_CPUID_FEATURE_ECX_MONITOR)
1402	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
1403	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
1404	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
1405	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
1406	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
1407	\| X86_CPUID_FEATURE_ECX_SSSE3
1408	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
1409	\| PASSTHRU_FEATURE(pConfig->enmFma, pHstFeat->fFma, X86_CPUID_FEATURE_ECX_FMA)
1410	\| PASSTHRU_FEATURE(pConfig->enmCmpXchg16b, pHstFeat->fCmpXchg16b, X86_CPUID_FEATURE_ECX_CX16)
1411	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
1412	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1413	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
1414	\| PASSTHRU_FEATURE_NOT_IEM(pConfig->enmPcid, pHstFeat->fPcid, X86_CPUID_FEATURE_ECX_PCID)
1415	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
1416	\| PASSTHRU_FEATURE(pConfig->enmSse41, pHstFeat->fSse41, X86_CPUID_FEATURE_ECX_SSE4_1)
1417	\| PASSTHRU_FEATURE(pConfig->enmSse42, pHstFeat->fSse42, X86_CPUID_FEATURE_ECX_SSE4_2)
1418	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
1419	\| PASSTHRU_FEATURE(pConfig->enmMovBe, pHstFeat->fMovBe, X86_CPUID_FEATURE_ECX_MOVBE)
1420	\| PASSTHRU_FEATURE(pConfig->enmPopCnt, pHstFeat->fPopCnt, X86_CPUID_FEATURE_ECX_POPCNT)
1421	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
1422	\| PASSTHRU_FEATURE_TODO(pConfig->enmAesNi, X86_CPUID_FEATURE_ECX_AES)
1423	\| PASSTHRU_FEATURE(pConfig->enmXSave, pHstFeat->fXSaveRstor, X86_CPUID_FEATURE_ECX_XSAVE)
1424	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
1425	\| PASSTHRU_FEATURE(pConfig->enmAvx, pHstFeat->fAvx, X86_CPUID_FEATURE_ECX_AVX)
1426	\| PASSTHRU_FEATURE(pConfig->enmF16c, pHstFeat->fF16c, X86_CPUID_FEATURE_ECX_F16C)
1427	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdRand, X86_CPUID_FEATURE_ECX_RDRAND)
1428	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
1429	;
1430
1431	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
1432	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
1433	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
1434	{
1435	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
1436	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
1437	}
1438
1439	if (pCpum->u8PortableCpuIdLevel > 0)
1440	{
1441	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
1442	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
1443	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
1444	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
1445	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
1446	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
1447	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
1448	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
1449	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
1450	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
1451	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
1452	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
1453	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
1454	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
1455	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
1456	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
1457	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
1458	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
1459	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
1460	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
1461
1462	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP ///??
1463	\| X86_CPUID_FEATURE_EDX_PSN
1464	\| X86_CPUID_FEATURE_EDX_DS
1465	\| X86_CPUID_FEATURE_EDX_ACPI
1466	\| X86_CPUID_FEATURE_EDX_SS
1467	\| X86_CPUID_FEATURE_EDX_TM
1468	\| X86_CPUID_FEATURE_EDX_PBE
1469	)));
1470	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
1471	\| X86_CPUID_FEATURE_ECX_CPLDS
1472	\| X86_CPUID_FEATURE_ECX_AES
1473	\| X86_CPUID_FEATURE_ECX_VMX
1474	\| X86_CPUID_FEATURE_ECX_SMX
1475	\| X86_CPUID_FEATURE_ECX_EST
1476	\| X86_CPUID_FEATURE_ECX_TM2
1477	\| X86_CPUID_FEATURE_ECX_CNTXID
1478	\| X86_CPUID_FEATURE_ECX_FMA
1479	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1480	\| X86_CPUID_FEATURE_ECX_PDCM
1481	\| X86_CPUID_FEATURE_ECX_DCA
1482	\| X86_CPUID_FEATURE_ECX_OSXSAVE
1483	)));
1484	}
1485
1486	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
1487	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
1488
1489	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
1490	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
1491	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
1492	*/
1493	#ifdef VBOX_WITH_MULTI_CORE
1494	if (pVM->cCpus > 1)
1495	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
1496	#endif
1497	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
1498	{
1499	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
1500	core times the number of CPU cores per processor */
1501	#ifdef VBOX_WITH_MULTI_CORE
1502	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
1503	#else
1504	/* Single logical processor in a package. */
1505	pStdFeatureLeaf->uEbx \|= (1 << 16);
1506	#endif
1507	}
1508
1509	uint32_t uMicrocodeRev;
1510	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
1511	if (RT_SUCCESS(rc))
1512	{
1513	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
1514	}
1515	else
1516	{
1517	uMicrocodeRev = 0;
1518	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
1519	}
1520
1521	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
1522	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
1523	*/
1524	if ( ( pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen
1525	/** @todo The following ASSUMES that Hygon uses the same version numbering
1526	* as AMD and that they shipped buggy firmware. */
1527	\|\| pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Hygon_Dhyana)
1528	&& uMicrocodeRev < 0x8001126
1529	&& !pConfig->fForceVme)
1530	{
1531	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
1532	LogRel(("CPUM: Zen VME workaround engaged\n"));
1533	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
1534	}
1535
1536	/* Force standard feature bits. */
1537	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
1538	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
1539	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
1540	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
1541	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
1542	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
1543	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1544	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
1545	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1546	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
1547	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
1548	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
1549	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
1550	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
1551	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
1552	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
1553	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
1554	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
1555	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1556	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
1557	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
1558	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
1559
1560	pStdFeatureLeaf = NULL; /* Must refetch! */
1561
1562	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
1563	* AMD:
1564	* EAX: CPU model, family and stepping.
1565	*
1566	* ECX + EDX: Supported features. Only report features we can support.
1567	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1568	* options may require adjusting (i.e. stripping what was enabled).
1569	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
1570	*
1571	* EBX: Branding ID and package type (or reserved).
1572	*
1573	* Intel and probably most others:
1574	* EAX: 0
1575	* EBX: 0
1576	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
1577	*/
1578	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
1579	if (pExtFeatureLeaf)
1580	{
1581	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
1582
1583	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
1584	\| X86_CPUID_AMD_FEATURE_EDX_VME
1585	\| X86_CPUID_AMD_FEATURE_EDX_DE
1586	\| X86_CPUID_AMD_FEATURE_EDX_PSE
1587	\| X86_CPUID_AMD_FEATURE_EDX_TSC
1588	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
1589	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
1590	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
1591	\| X86_CPUID_AMD_FEATURE_EDX_CX8
1592	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
1593	//\| RT_BIT_32(10) - reserved
1594	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1595	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
1596	\| X86_CPUID_AMD_FEATURE_EDX_PGE
1597	\| X86_CPUID_AMD_FEATURE_EDX_MCA
1598	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
1599	\| X86_CPUID_AMD_FEATURE_EDX_PAT
1600	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
1601	//\| RT_BIT_32(18) - reserved
1602	//\| RT_BIT_32(19) - reserved
1603	\| X86_CPUID_EXT_FEATURE_EDX_NX
1604	//\| RT_BIT_32(21) - reserved
1605	\| PASSTHRU_FEATURE(pConfig->enmAmdExtMmx, pHstFeat->fAmdMmxExts, X86_CPUID_AMD_FEATURE_EDX_AXMMX)
1606	\| X86_CPUID_AMD_FEATURE_EDX_MMX
1607	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
1608	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
1609	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1610	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
1611	//\| RT_BIT_32(28) - reserved
1612	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
1613	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
1614	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
1615	;
1616	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
1617	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
1618	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
1619	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1620	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
1621	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
1622	\| PASSTHRU_FEATURE(pConfig->enmAbm, pHstFeat->fAbm, X86_CPUID_AMD_FEATURE_ECX_ABM)
1623	\| PASSTHRU_FEATURE_TODO(pConfig->enmSse4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A)
1624	\| PASSTHRU_FEATURE_TODO(pConfig->enmMisAlnSse, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE)
1625	\| PASSTHRU_FEATURE(pConfig->enm3dNowPrf, pHstFeat->f3DNowPrefetch, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1626	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
1627	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
1628	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
1629	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1630	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
1631	//\| RT_BIT_32(14) - reserved
1632	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
1633	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
1634	//\| RT_BIT_32(17) - reserved
1635	//\| RT_BIT_32(18) - reserved
1636	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
1637	//\| RT_BIT_32(20) - reserved
1638	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
1639	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
1640	//\| RT_BIT_32(23) - reserved
1641	//\| RT_BIT_32(24) - reserved
1642	//\| RT_BIT_32(25) - reserved
1643	//\| RT_BIT_32(26) - reserved
1644	//\| RT_BIT_32(27) - reserved
1645	//\| RT_BIT_32(28) - reserved
1646	//\| RT_BIT_32(29) - reserved
1647	//\| RT_BIT_32(30) - reserved
1648	//\| RT_BIT_32(31) - reserved
1649	;
1650	#ifdef VBOX_WITH_MULTI_CORE
1651	if ( pVM->cCpus > 1
1652	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
1653	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
1654	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
1655	#endif
1656
1657	if (pCpum->u8PortableCpuIdLevel > 0)
1658	{
1659	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1660	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
1661	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
1662	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
1663	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
1664	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
1665	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
1666	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
1667	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
1668	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
1669	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1670	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1671	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1672	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1673	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1674	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1675
1676	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
1677	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1678	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
1679	\| X86_CPUID_AMD_FEATURE_ECX_IBS
1680	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1681	\| X86_CPUID_AMD_FEATURE_ECX_WDT
1682	\| X86_CPUID_AMD_FEATURE_ECX_LWP
1683	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
1684	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
1685	\| UINT32_C(0xff964000)
1686	)));
1687	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
1688	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1689	\| RT_BIT(18)
1690	\| RT_BIT(19)
1691	\| RT_BIT(21)
1692	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
1693	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1694	\| RT_BIT(28)
1695	)));
1696	}
1697
1698	/* Force extended feature bits. */
1699	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
1700	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
1701	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
1702	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
1703	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
1704	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
1705	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
1706	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
1707	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1708	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
1709	}
1710	pExtFeatureLeaf = NULL; /* Must refetch! */
1711
1712
1713	/* Cpuid 2:
1714	* Intel: (Nondeterministic) Cache and TLB information
1715	* AMD: Reserved
1716	* VIA: Reserved
1717	* Safe to expose.
1718	*/
1719	uint32_t uSubLeaf = 0;
1720	PCPUMCPUIDLEAF pCurLeaf;
1721	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
1722	{
1723	if ((pCurLeaf->uEax & 0xff) > 1)
1724	{
1725	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
1726	pCurLeaf->uEax &= UINT32_C(0xffffff01);
1727	}
1728	uSubLeaf++;
1729	}
1730
1731	/* Cpuid 3:
1732	* Intel: EAX, EBX - reserved (transmeta uses these)
1733	* ECX, EDX - Processor Serial Number if available, otherwise reserved
1734	* AMD: Reserved
1735	* VIA: Reserved
1736	* Safe to expose
1737	*/
1738	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1739	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
1740	{
1741	uSubLeaf = 0;
1742	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
1743	{
1744	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1745	if (pCpum->u8PortableCpuIdLevel > 0)
1746	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1747	uSubLeaf++;
1748	}
1749	}
1750
1751	/* Cpuid 4 + ECX:
1752	* Intel: Deterministic Cache Parameters Leaf.
1753	* AMD: Reserved
1754	* VIA: Reserved
1755	* Safe to expose, except for EAX:
1756	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1757	* Bits 31-26: Maximum number of processor cores in this physical package**
1758	* Note: These SMP values are constant regardless of ECX
1759	*/
1760	uSubLeaf = 0;
1761	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
1762	{
1763	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
1764	#ifdef VBOX_WITH_MULTI_CORE
1765	if ( pVM->cCpus > 1
1766	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1767	{
1768	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1769	/* One logical processor with possibly multiple cores. */
1770	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1771	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
1772	}
1773	#endif
1774	uSubLeaf++;
1775	}
1776
1777	/* Cpuid 5: Monitor/mwait Leaf
1778	* Intel: ECX, EDX - reserved
1779	* EAX, EBX - Smallest and largest monitor line size
1780	* AMD: EDX - reserved
1781	* EAX, EBX - Smallest and largest monitor line size
1782	* ECX - extensions (ignored for now)
1783	* VIA: Reserved
1784	* Safe to expose
1785	*/
1786	uSubLeaf = 0;
1787	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
1788	{
1789	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1790	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
1791	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1792
1793	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1794	if (pConfig->enmMWaitExtensions)
1795	{
1796	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1797	/** @todo for now we just expose host's MWAIT C-states, although conceptually
1798	it shall be part of our power management virtualization model */
1799	#if 0
1800	/* MWAIT sub C-states */
1801	pCurLeaf->uEdx =
1802	(0 << 0) /* 0 in C0 */ \|
1803	(2 << 4) /* 2 in C1 */ \|
1804	(2 << 8) /* 2 in C2 */ \|
1805	(2 << 12) /* 2 in C3 */ \|
1806	(0 << 16) /* 0 in C4 */
1807	;
1808	#endif
1809	}
1810	else
1811	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1812	uSubLeaf++;
1813	}
1814
1815	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
1816	* Intel: Various thermal and power management related stuff.
1817	* AMD: EBX, EDX - reserved.
1818	* EAX - Bit two is ARAT, indicating that APIC timers run at a constant
1819	* rate regardless of processor P-states. Same as Intel.
1820	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
1821	* present. Same as Intel.
1822	* VIA: ??
1823	*
1824	* We clear everything except for the ARAT bit which is important for Windows 11.
1825	*/
1826	uSubLeaf = 0;
1827	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 6, uSubLeaf)) != NULL)
1828	{
1829	pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1830	pCurLeaf->uEax &= 0
1831	\| X86_CPUID_POWER_EAX_ARAT
1832	;
1833
1834	/* Since we emulate the APIC timers, we can normally set the ARAT bit
1835	* regardless of whether the host CPU sets it or not. Intel sets the ARAT
1836	* bit circa since the Westmere generation, AMD probably only since Zen.
1837	* See @bugref{10567}.
1838	*/
1839	if (pConfig->fInvariantApic)
1840	pCurLeaf->uEax \|= X86_CPUID_POWER_EAX_ARAT;
1841
1842	uSubLeaf++;
1843	}
1844
1845	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
1846	* EAX: Number of sub leaves.
1847	* EBX+ECX+EDX: Feature flags
1848	*
1849	* We only have documentation for one sub-leaf, so clear all other (no need
1850	* to remove them as such, just set them to zero).
1851	*
1852	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1853	* options may require adjusting (i.e. stripping what was enabled).
1854	*/
1855	uSubLeaf = 0;
1856	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
1857	{
1858	switch (uSubLeaf)
1859	{
1860	case 0:
1861	{
1862	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
1863	pCurLeaf->uEbx &= 0
1864	\| PASSTHRU_FEATURE(pConfig->enmFsGsBase, pHstFeat->fFsGsBase, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE)
1865	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
1866	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
1867	\| X86_CPUID_STEXT_FEATURE_EBX_BMI1
1868	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
1869	\| PASSTHRU_FEATURE(pConfig->enmAvx2, pHstFeat->fAvx2, X86_CPUID_STEXT_FEATURE_EBX_AVX2)
1870	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
1871	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
1872	\| X86_CPUID_STEXT_FEATURE_EBX_BMI2
1873	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
1874	\| PASSTHRU_FEATURE_NOT_IEM(pConfig->enmInvpcid, pHstFeat->fInvpcid, X86_CPUID_STEXT_FEATURE_EBX_INVPCID)
1875	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
1876	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
1877	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
1878	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
1879	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
1880	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
1881	//\| RT_BIT(17) - reserved
1882	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdSeed, X86_CPUID_STEXT_FEATURE_EBX_RDSEED)
1883	\| PASSTHRU_FEATURE(pConfig->enmAdx, pHstFeat->fAdx, X86_CPUID_STEXT_FEATURE_EBX_ADX)
1884	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
1885	//\| RT_BIT(21) - reserved
1886	//\| RT_BIT(22) - reserved
1887	\| PASSTHRU_FEATURE(pConfig->enmCLFlushOpt, pHstFeat->fClFlushOpt, X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT)
1888	//\| RT_BIT(24) - reserved
1889	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
1890	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
1891	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
1892	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
1893	\| PASSTHRU_FEATURE(pConfig->enmSha, pHstFeat->fSha, X86_CPUID_STEXT_FEATURE_EBX_SHA)
1894	//\| RT_BIT(30) - reserved
1895	//\| RT_BIT(31) - reserved
1896	;
1897	pCurLeaf->uEcx &= 0
1898	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
1899	;
1900	pCurLeaf->uEdx &= 0
1901	\| PASSTHRU_FEATURE(pConfig->enmMdsClear, pHstFeat->fMdsClear, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR)
1902	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
1903	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
1904	\| PASSTHRU_FEATURE(pConfig->enmFlushCmdMsr, pHstFeat->fFlushCmd, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD)
1905	\| PASSTHRU_FEATURE(pConfig->enmArchCapMsr, pHstFeat->fArchCap, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
1906	;
1907
1908	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
1909	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
1910	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
1911	{
1912	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
1913	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
1914	}
1915
1916	if (pCpum->u8PortableCpuIdLevel > 0)
1917	{
1918	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
1919	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
1920	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
1921	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
1922	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
1923	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
1924	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1925	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
1926	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, ADX, X86_CPUID_STEXT_FEATURE_EBX_ADX, pConfig->enmAdx);
1927	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
1928	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
1929	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
1930	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
1931	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
1932	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA, pConfig->enmSha);
1933	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
1934	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
1935	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
1936	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
1937	}
1938
1939	/* Dependencies. */
1940	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
1941	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
1942
1943	/* Force standard feature bits. */
1944	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
1945	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
1946	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1947	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
1948	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
1949	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
1950	if (pConfig->enmAdx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1951	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_ADX;
1952	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
1953	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
1954	if (pConfig->enmSha == CPUMISAEXTCFG_ENABLED_ALWAYS)
1955	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_SHA;
1956	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
1957	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
1958	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
1959	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
1960	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
1961	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
1962	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
1963	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
1964	break;
1965	}
1966
1967	default:
1968	/* Invalid index, all values are zero. */
1969	pCurLeaf->uEax = 0;
1970	pCurLeaf->uEbx = 0;
1971	pCurLeaf->uEcx = 0;
1972	pCurLeaf->uEdx = 0;
1973	break;
1974	}
1975	uSubLeaf++;
1976	}
1977
1978	/* Cpuid 8: Marked as reserved by Intel and AMD.
1979	* We zero this since we don't know what it may have been used for.
1980	*/
1981	cpumR3CpuIdZeroLeaf(pCpum, 8);
1982
1983	/* Cpuid 9: Direct Cache Access (DCA) Parameters
1984	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
1985	* EBX, ECX, EDX - reserved.
1986	* AMD: Reserved
1987	* VIA: ??
1988	*
1989	* We zero this.
1990	*/
1991	cpumR3CpuIdZeroLeaf(pCpum, 9);
1992
1993	/* Cpuid 0xa: Architectural Performance Monitor Features
1994	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
1995	* EBX, ECX, EDX - reserved.
1996	* AMD: Reserved
1997	* VIA: ??
1998	*
1999	* We zero this, for now at least.
2000	*/
2001	cpumR3CpuIdZeroLeaf(pCpum, 10);
2002
2003	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
2004	* Intel: EAX - APCI ID shift right for next level.
2005	* EBX - Factory configured cores/threads at this level.
2006	* ECX - Level number (same as input) and level type (1,2,0).
2007	* EDX - Extended initial APIC ID.
2008	* AMD: Reserved
2009	* VIA: ??
2010	*/
2011	uSubLeaf = 0;
2012	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
2013	{
2014	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
2015	{
2016	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
2017	if (bLevelType == 1)
2018	{
2019	/* Thread level - we don't do threads at the moment. */
2020	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
2021	pCurLeaf->uEbx = 1;
2022	}
2023	else if (bLevelType == 2)
2024	{
2025	/* Core level. */
2026	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
2027	#ifdef VBOX_WITH_MULTI_CORE
2028	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
2029	pCurLeaf->uEax++;
2030	#endif
2031	pCurLeaf->uEbx = pVM->cCpus;
2032	}
2033	else
2034	{
2035	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
2036	pCurLeaf->uEax = 0;
2037	pCurLeaf->uEbx = 0;
2038	pCurLeaf->uEcx = 0;
2039	}
2040	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
2041	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
2042	}
2043	else
2044	{
2045	pCurLeaf->uEax = 0;
2046	pCurLeaf->uEbx = 0;
2047	pCurLeaf->uEcx = 0;
2048	pCurLeaf->uEdx = 0;
2049	}
2050	uSubLeaf++;
2051	}
2052
2053	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
2054	* We zero this since we don't know what it may have been used for.
2055	*/
2056	cpumR3CpuIdZeroLeaf(pCpum, 12);
2057
2058	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
2059	* ECX=0: EAX - Valid bits in XCR0[31:0].
2060	* EBX - Maximum state size as per current XCR0 value.
2061	* ECX - Maximum state size for all supported features.
2062	* EDX - Valid bits in XCR0[63:32].
2063	* ECX=1: EAX - Various X-features.
2064	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
2065	* ECX - Valid bits in IA32_XSS[31:0].
2066	* EDX - Valid bits in IA32_XSS[63:32].
2067	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
2068	* if the bit invalid all four registers are set to zero.
2069	* EAX - The state size for this feature.
2070	* EBX - The state byte offset of this feature.
2071	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
2072	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
2073	*
2074	* Clear them all as we don't currently implement extended CPU state.
2075	*/
2076	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
2077	uint64_t fGuestXcr0Mask = 0;
2078	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2079	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
2080	{
2081	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
2082	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
2083	fGuestXcr0Mask \|= XSAVE_C_YMM;
2084	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
2085	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
2086	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
2087	fGuestXcr0Mask &= pCpum->fXStateHostMask;
2088
2089	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
2090	}
2091	pStdFeatureLeaf = NULL;
2092	pCpum->fXStateGuestMask = fGuestXcr0Mask;
2093
2094	/* Work the sub-leaves. */
2095	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
2096	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
2097	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
2098	{
2099	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
2100	if (pCurLeaf)
2101	{
2102	if (fGuestXcr0Mask)
2103	{
2104	switch (uSubLeaf)
2105	{
2106	case 0:
2107	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
2108	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
2109	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2110	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
2111	VERR_CPUM_IPE_1);
2112	cbXSaveMaxActual = pCurLeaf->uEcx;
2113	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
2114	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
2115	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
2116	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
2117	VERR_CPUM_IPE_2);
2118	continue;
2119	case 1:
2120	pCurLeaf->uEax &= 0;
2121	pCurLeaf->uEcx &= 0;
2122	pCurLeaf->uEdx &= 0;
2123	/** @todo what about checking ebx? */
2124	continue;
2125	default:
2126	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
2127	{
2128	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
2129	&& pCurLeaf->uEax > 0
2130	&& pCurLeaf->uEbx < cbXSaveMaxActual
2131	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2132	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
2133	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
2134	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
2135	VERR_CPUM_IPE_2);
2136	AssertLogRel(!(pCurLeaf->uEcx & 1));
2137	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
2138	pCurLeaf->uEdx = 0; /* it's reserved... */
2139	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
2140	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
2141	continue;
2142	}
2143	break;
2144	}
2145	}
2146
2147	/* Clear the leaf. */
2148	pCurLeaf->uEax = 0;
2149	pCurLeaf->uEbx = 0;
2150	pCurLeaf->uEcx = 0;
2151	pCurLeaf->uEdx = 0;
2152	}
2153	}
2154
2155	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
2156	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
2157	{
2158	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
2159	if (pCurLeaf)
2160	{
2161	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
2162	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
2163	pCurLeaf->uEbx = cbXSaveMaxReport;
2164	pCurLeaf->uEcx = cbXSaveMaxReport;
2165	}
2166	}
2167
2168	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
2169	* We zero this since we don't know what it may have been used for.
2170	*/
2171	cpumR3CpuIdZeroLeaf(pCpum, 14);
2172
2173	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
2174	* also known as Intel Resource Director Technology (RDT) Monitoring
2175	* We zero this as we don't currently virtualize PQM.
2176	*/
2177	cpumR3CpuIdZeroLeaf(pCpum, 15);
2178
2179	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
2180	* also known as Intel Resource Director Technology (RDT) Allocation
2181	* We zero this as we don't currently virtualize PQE.
2182	*/
2183	cpumR3CpuIdZeroLeaf(pCpum, 16);
2184
2185	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
2186	* We zero this since we don't know what it may have been used for.
2187	*/
2188	cpumR3CpuIdZeroLeaf(pCpum, 17);
2189
2190	/* Cpuid 0x12 + ECX: SGX resource enumeration.
2191	* We zero this as we don't currently virtualize this.
2192	*/
2193	cpumR3CpuIdZeroLeaf(pCpum, 18);
2194
2195	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
2196	* We zero this since we don't know what it may have been used for.
2197	*/
2198	cpumR3CpuIdZeroLeaf(pCpum, 19);
2199
2200	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
2201	* We zero this as we don't currently virtualize this.
2202	*/
2203	cpumR3CpuIdZeroLeaf(pCpum, 20);
2204
2205	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
2206	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
2207	* EAX - denominator (unsigned).
2208	* EBX - numerator (unsigned).
2209	* ECX, EDX - reserved.
2210	* AMD: Reserved / undefined / not implemented.
2211	* VIA: Reserved / undefined / not implemented.
2212	* We zero this as we don't currently virtualize this.
2213	*/
2214	cpumR3CpuIdZeroLeaf(pCpum, 21);
2215
2216	/* Cpuid 0x16: Processor frequency info
2217	* Intel: EAX - Core base frequency in MHz.
2218	* EBX - Core maximum frequency in MHz.
2219	* ECX - Bus (reference) frequency in MHz.
2220	* EDX - Reserved.
2221	* AMD: Reserved / undefined / not implemented.
2222	* VIA: Reserved / undefined / not implemented.
2223	* We zero this as we don't currently virtualize this.
2224	*/
2225	cpumR3CpuIdZeroLeaf(pCpum, 22);
2226
2227	/* Cpuid 0x17..0x10000000: Unknown.
2228	* We don't know these and what they mean, so remove them. */
2229	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2230	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
2231
2232
2233	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
2234	* We remove all these as we're a hypervisor and must provide our own.
2235	*/
2236	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2237	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
2238
2239
2240	/* Cpuid 0x80000000 is harmless. */
2241
2242	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
2243
2244	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
2245
2246	/* Cpuid 0x80000005 & 0x80000006 contain information about L1, L2 & L3 cache and TLB identifiers.
2247	* Safe to pass on to the guest.
2248	*
2249	* AMD: 0x80000005 L1 cache information
2250	* 0x80000006 L2/L3 cache information
2251	* Intel: 0x80000005 reserved
2252	* 0x80000006 L2 cache information
2253	* VIA: 0x80000005 TLB and L1 cache information
2254	* 0x80000006 L2 cache information
2255	*/
2256
2257	uSubLeaf = 0;
2258	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000006), uSubLeaf)) != NULL)
2259	{
2260	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2261	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2262	{
2263	/*
2264	* Some AMD CPUs (e.g. Ryzen 7940HS) report zero L3 cache line size here and refer
2265	* to CPUID Fn8000_001D. This triggers division by zero in Linux if the
2266	* TopologyExtensions aka TOPOEXT bit in Fn8000_0001_ECX is not set, or if the kernel
2267	* is old enough (e.g. Linux 3.13) that it does not know about the topology extension
2268	* CPUID leaves.
2269	* We put a non-zero value in the cache line size here, if possible the actual value
2270	* gleaned from Fn8000_001D, or worst case a made-up valid number.
2271	*/
2272	PCPUMCPUIDLEAF pTopoLeaf;
2273	uint32_t uTopoSubLeaf;
2274	uint32_t uCacheLineSize;
2275
2276	if ((pCurLeaf->uEdx & 0xff) == 0)
2277	{
2278	uTopoSubLeaf = 0;
2279
2280	uCacheLineSize = 64; /* Use 64-byte line size as a fallback. */
2281
2282	/* Find L3 cache information. Have to check the cache level in EAX. */
2283	while ((pTopoLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uTopoSubLeaf)) != NULL)
2284	{
2285	if (((pTopoLeaf->uEax >> 5) & 0x07) == 3) {
2286	uCacheLineSize = (pTopoLeaf->uEbx & 0xfff) + 1;
2287	/* Fn8000_0006 can't report power of two line sizes greater than 128. */
2288	if (uCacheLineSize > 128)
2289	uCacheLineSize = 128;
2290
2291	break;
2292	}
2293	uTopoSubLeaf++;
2294	}
2295
2296	Assert(uCacheLineSize < 256);
2297	pCurLeaf->uEdx \|= uCacheLineSize;
2298	LogRel(("CPUM: AMD L3 cache line size in CPUID leaf 0x80000006 was zero, adjusting to %u\n", uCacheLineSize));
2299	}
2300	}
2301	uSubLeaf++;
2302	}
2303
2304	/* Cpuid 0x80000007: Advanced Power Management Information.
2305	* AMD: EAX: Processor feedback capabilities.
2306	* EBX: RAS capabilites.
2307	* ECX: Advanced power monitoring interface.
2308	* EDX: Enhanced power management capabilities.
2309	* Intel: EAX, EBX, ECX - reserved.
2310	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
2311	* VIA: Reserved
2312	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
2313	*/
2314	uSubLeaf = 0;
2315	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
2316	{
2317	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
2318	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2319	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2320	{
2321	/*
2322	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
2323	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
2324	* bit is now configurable.
2325	*/
2326	pCurLeaf->uEdx &= 0
2327	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
2328	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
2329	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
2330	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
2331	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
2332	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
2333	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
2334	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
2335	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
2336	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
2337	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
2338	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
2339	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
2340	\| 0;
2341	}
2342	else
2343	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2344	if (!pConfig->fInvariantTsc)
2345	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2346	uSubLeaf++;
2347	}
2348
2349	/* Cpuid 0x80000008:
2350	* AMD: EAX: Long Mode Size Identifiers
2351	* EBX: Extended Feature Identifiers
2352	* ECX: Number of cores + APICIdCoreIdSize
2353	* EDX: RDPRU Register Identifier Range
2354	* Intel: EAX: Virtual/Physical address Size
2355	* EBX, ECX, EDX - reserved
2356	* VIA: EAX: Virtual/Physical address Size
2357	* EBX, ECX, EDX - reserved
2358	*
2359	* We only expose the virtual+pysical address size to the guest atm.
2360	* On AMD we set the core count, but not the apic id stuff as we're
2361	* currently not doing the apic id assignments in a compatible manner.
2362	*/
2363	uSubLeaf = 0;
2364	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
2365	{
2366	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
2367	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2368	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2369	{
2370	/* Expose XSaveErPtr aka RstrFpErrPtrs to guest. */
2371	pCurLeaf->uEbx &= X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR; /* reserved - [12] == IBPB */
2372	}
2373	else
2374	pCurLeaf->uEbx = 0; /* reserved */
2375
2376	pCurLeaf->uEdx = 0; /* reserved */
2377
2378	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
2379	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
2380	pCurLeaf->uEcx = 0;
2381	#ifdef VBOX_WITH_MULTI_CORE
2382	if ( pVM->cCpus > 1
2383	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2384	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
2385	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
2386	#endif
2387	uSubLeaf++;
2388	}
2389
2390	/* Cpuid 0x80000009: Reserved
2391	* We zero this since we don't know what it may have been used for.
2392	*/
2393	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
2394
2395	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
2396	* AMD: EAX - SVM revision.
2397	* EBX - Number of ASIDs.
2398	* ECX - Reserved.
2399	* EDX - SVM Feature identification.
2400	*/
2401	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2402	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2403	{
2404	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2405	if ( pExtFeatureLeaf
2406	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
2407	{
2408	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
2409	if (pSvmFeatureLeaf)
2410	{
2411	pSvmFeatureLeaf->uEax = 0x1;
2412	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
2413	pSvmFeatureLeaf->uEcx = 0;
2414	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
2415	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
2416	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
2417	}
2418	else
2419	{
2420	/* Should never happen. */
2421	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
2422	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2423	}
2424	}
2425	else
2426	{
2427	/* If SVM is not supported, this is reserved, zero out. */
2428	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2429	}
2430	}
2431	else
2432	{
2433	/* Cpuid 0x8000000a: Reserved on Intel.
2434	* We zero this since we don't know what it may have been used for.
2435	*/
2436	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2437	}
2438
2439	/* Cpuid 0x8000000b thru 0x80000018: Reserved
2440	* We clear these as we don't know what purpose they might have. */
2441	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
2442	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
2443
2444	/* Cpuid 0x80000019: TLB configuration
2445	* Seems to be harmless, pass them thru as is. */
2446
2447	/* Cpuid 0x8000001a: Peformance optimization identifiers.
2448	* Strip anything we don't know what is or addresses feature we don't implement. */
2449	uSubLeaf = 0;
2450	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
2451	{
2452	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
2453	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
2454	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
2455	;
2456	pCurLeaf->uEbx = 0; /* reserved */
2457	pCurLeaf->uEcx = 0; /* reserved */
2458	pCurLeaf->uEdx = 0; /* reserved */
2459	uSubLeaf++;
2460	}
2461
2462	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
2463	* Clear this as we don't currently virtualize this feature. */
2464	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
2465
2466	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
2467	* Clear this as we don't currently virtualize this feature. */
2468	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
2469
2470	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
2471	* We need to sanitize the cores per cache (EAX[25:14]).
2472	*
2473	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
2474	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
2475	* slightly different meaning.
2476	*/
2477	uSubLeaf = 0;
2478	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
2479	{
2480	#ifdef VBOX_WITH_MULTI_CORE
2481	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
2482	if (cCores > pVM->cCpus)
2483	cCores = pVM->cCpus;
2484	pCurLeaf->uEax &= UINT32_C(0x00003fff);
2485	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
2486	#else
2487	pCurLeaf->uEax &= UINT32_C(0x00003fff);
2488	#endif
2489	uSubLeaf++;
2490	}
2491
2492	/* Cpuid 0x8000001e: Get APIC / unit / node information.
2493	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
2494	* setup, we have one compute unit with all the cores in it. Single node.
2495	*/
2496	uSubLeaf = 0;
2497	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
2498	{
2499	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
2500	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
2501	{
2502	#ifdef VBOX_WITH_MULTI_CORE
2503	pCurLeaf->uEbx = pVM->cCpus < 0x100
2504	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
2505	#else
2506	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
2507	#endif
2508	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
2509	}
2510	else
2511	{
2512	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
2513	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_HYGON);
2514	pCurLeaf->uEbx = 0; /* Reserved. */
2515	pCurLeaf->uEcx = 0; /* Reserved. */
2516	}
2517	pCurLeaf->uEdx = 0; /* Reserved. */
2518	uSubLeaf++;
2519	}
2520
2521	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
2522	* We don't know these and what they mean, so remove them. */
2523	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2524	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
2525
2526	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
2527	* Just pass it thru for now. */
2528
2529	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
2530	* Just pass it thru for now. */
2531
2532	/* Cpuid 0xc0000000: Centaur stuff.
2533	* Harmless, pass it thru. */
2534
2535	/* Cpuid 0xc0000001: Centaur features.
2536	* VIA: EAX - Family, model, stepping.
2537	* EDX - Centaur extended feature flags. Nothing interesting, except may
2538	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
2539	* EBX, ECX - reserved.
2540	* We keep EAX but strips the rest.
2541	*/
2542	uSubLeaf = 0;
2543	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
2544	{
2545	pCurLeaf->uEbx = 0;
2546	pCurLeaf->uEcx = 0;
2547	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
2548	uSubLeaf++;
2549	}
2550
2551	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
2552	* We only have fixed stale values, but should be harmless. */
2553
2554	/* Cpuid 0xc0000003: Reserved.
2555	* We zero this since we don't know what it may have been used for.
2556	*/
2557	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
2558
2559	/* Cpuid 0xc0000004: Centaur Performance Info.
2560	* We only have fixed stale values, but should be harmless. */
2561
2562
2563	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
2564	* We don't know these and what they mean, so remove them. */
2565	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2566	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
2567
2568	return VINF_SUCCESS;
2569	#undef PORTABLE_DISABLE_FEATURE_BIT
2570	#undef PORTABLE_CLEAR_BITS_WHEN
2571	}
2572
2573
2574	/**
2575	* Reads a value in /CPUM/IsaExts/ node.
2576	*
2577	* @returns VBox status code (error message raised).
2578	* @param pVM The cross context VM structure. (For errors.)
2579	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2580	* @param pszValueName The value / extension name.
2581	* @param penmValue Where to return the choice.
2582	* @param enmDefault The default choice.
2583	*/
2584	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
2585	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
2586	{
2587	/*
2588	* Try integer encoding first.
2589	*/
2590	uint64_t uValue;
2591	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
2592	if (RT_SUCCESS(rc))
2593	switch (uValue)
2594	{
2595	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
2596	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
2597	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
2598	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
2599	default:
2600	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
2601	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
2602	pszValueName, uValue);
2603	}
2604	/*
2605	* If missing, use default.
2606	*/
2607	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
2608	*penmValue = enmDefault;
2609	else
2610	{
2611	if (rc == VERR_CFGM_NOT_INTEGER)
2612	{
2613	/*
2614	* Not an integer, try read it as a string.
2615	*/
2616	char szValue[32];
2617	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
2618	if (RT_SUCCESS(rc))
2619	{
2620	RTStrToLower(szValue);
2621	size_t cchValue = strlen(szValue);
2622	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
2623	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
2624	*penmValue = CPUMISAEXTCFG_DISABLED;
2625	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
2626	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
2627	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
2628	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
2629	else if (EQ("portable"))
2630	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
2631	else if (EQ("default") \|\| EQ("def"))
2632	*penmValue = enmDefault;
2633	else
2634	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
2635	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
2636	pszValueName, uValue);
2637	#undef EQ
2638	}
2639	}
2640	if (RT_FAILURE(rc))
2641	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
2642	}
2643	return VINF_SUCCESS;
2644	}
2645
2646
2647	/**
2648	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
2649	*
2650	* @returns VBox status code (error message raised).
2651	* @param pVM The cross context VM structure. (For errors.)
2652	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2653	* @param pszValueName The value / extension name.
2654	* @param penmValue Where to return the choice.
2655	* @param enmDefault The default choice.
2656	* @param fAllowed Allowed choice. Applied both to the result and to
2657	* the default value.
2658	*/
2659	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
2660	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
2661	{
2662	int rc;
2663	if (fAllowed)
2664	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
2665	else
2666	{
2667	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
2668	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
2669	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
2670	*penmValue = CPUMISAEXTCFG_DISABLED;
2671	}
2672	return rc;
2673	}
2674
2675
2676	/**
2677	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
2678	*
2679	* @returns VBox status code (error message raised).
2680	* @param pVM The cross context VM structure. (For errors.)
2681	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2682	* @param pCpumCfg The /CPUM node (can be NULL).
2683	* @param pszValueName The value / extension name.
2684	* @param penmValue Where to return the choice.
2685	* @param enmDefault The default choice.
2686	*/
2687	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
2688	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
2689	{
2690	if (CFGMR3Exists(pCpumCfg, pszValueName))
2691	{
2692	if (!CFGMR3Exists(pIsaExts, pszValueName))
2693	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
2694	else
2695	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
2696	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
2697	pszValueName, pszValueName);
2698
2699	bool fLegacy;
2700	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
2701	if (RT_SUCCESS(rc))
2702	{
2703	*penmValue = fLegacy;
2704	return VINF_SUCCESS;
2705	}
2706	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
2707	}
2708
2709	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
2710	}
2711
2712
2713	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
2714	{
2715	int rc;
2716
2717	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
2718	* When non-zero CPUID features that could cause portability issues will be
2719	* stripped. The higher the value the more features gets stripped. Higher
2720	* values should only be used when older CPUs are involved since it may
2721	* harm performance and maybe also cause problems with specific guests. */
2722	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
2723	AssertLogRelRCReturn(rc, rc);
2724
2725	/** @cfgm{/CPUM/GuestCpuName, string}
2726	* The name of the CPU we're to emulate. The default is the host CPU.
2727	* Note! CPUs other than "host" one is currently unsupported. */
2728	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
2729	AssertLogRelRCReturn(rc, rc);
2730
2731	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
2732	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
2733	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
2734	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
2735	*/
2736	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
2737	AssertLogRelRCReturn(rc, rc);
2738
2739	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
2740	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
2741	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
2742	* 64-bit linux guests which assume the presence of AMD performance counters
2743	* that we do not virtualize.
2744	*/
2745	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
2746	AssertLogRelRCReturn(rc, rc);
2747
2748	/** @cfgm{/CPUM/InvariantApic, boolean, true}
2749	* Set the Always Running APIC Timer (ARAT) flag in lea if true; otherwise
2750	* pass through the host setting. The Windows 10/11 HAL won't use APIC timers
2751	* unless the ARAT bit is set. Note that both Intel and AMD set this bit.
2752	*/
2753	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantApic", &pConfig->fInvariantApic, true);
2754	AssertLogRelRCReturn(rc, rc);
2755
2756	/** @cfgm{/CPUM/ForceVme, boolean, false}
2757	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
2758	* By default the flag is passed thru as is from the host CPU, except
2759	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
2760	* guests and DOS boxes in general.
2761	*/
2762	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
2763	AssertLogRelRCReturn(rc, rc);
2764
2765	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
2766	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
2767	* probably going to be a temporary hack, so don't depend on this.
2768	* The 1st byte of the value is the stepping, the 2nd byte value is the model
2769	* number and the 3rd byte value is the family, and the 4th value must be zero.
2770	*/
2771	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
2772	AssertLogRelRCReturn(rc, rc);
2773
2774	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
2775	* The last standard leaf to keep. The actual last value that is stored in EAX
2776	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
2777	* removed. (This works independently of and differently from NT4LeafLimit.)
2778	* The default is usually set to what we're able to reasonably sanitize.
2779	*/
2780	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
2781	AssertLogRelRCReturn(rc, rc);
2782
2783	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
2784	* The last extended leaf to keep. The actual last value that is stored in EAX
2785	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
2786	* leaf are removed. The default is set to what we're able to sanitize.
2787	*/
2788	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
2789	AssertLogRelRCReturn(rc, rc);
2790
2791	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
2792	* The last extended leaf to keep. The actual last value that is stored in EAX
2793	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
2794	* leaf are removed. The default is set to what we're able to sanitize.
2795	*/
2796	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
2797	AssertLogRelRCReturn(rc, rc);
2798
2799	#ifdef RT_ARCH_AMD64 /** @todo next VT-x/AMD-V on non-AMD64 hosts */
2800	bool fQueryNestedHwvirt = false
2801	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2802	\|\| pVM->cpum.s.HostFeatures.s.enmCpuVendor == CPUMCPUVENDOR_AMD
2803	\|\| pVM->cpum.s.HostFeatures.s.enmCpuVendor == CPUMCPUVENDOR_HYGON
2804	#endif
2805	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2806	\|\| pVM->cpum.s.HostFeatures.s.enmCpuVendor == CPUMCPUVENDOR_INTEL
2807	\|\| pVM->cpum.s.HostFeatures.s.enmCpuVendor == CPUMCPUVENDOR_VIA
2808	#endif
2809	;
2810	if (fQueryNestedHwvirt)
2811	{
2812	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
2813	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
2814	* The default is false, and when enabled requires a 64-bit CPU with support for
2815	* nested-paging and AMD-V or unrestricted guest mode.
2816	*/
2817	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
2818	AssertLogRelRCReturn(rc, rc);
2819	if (pConfig->fNestedHWVirt)
2820	{
2821	/** @todo Think about enabling this later with NEM/KVM. */
2822	if (VM_IS_NEM_ENABLED(pVM))
2823	{
2824	LogRel(("CPUM: Warning! Can't turn on nested VT-x/AMD-V when NEM is used! (later)\n"));
2825	pConfig->fNestedHWVirt = false;
2826	}
2827	else if (!fNestedPagingAndFullGuestExec)
2828	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
2829	"Cannot enable nested VT-x/AMD-V without nested-paging and unrestricted guest execution!\n");
2830	}
2831	}
2832	#endif /** @todo */
2833
2834	/*
2835	* Instruction Set Architecture (ISA) Extensions.
2836	*/
2837	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
2838	if (pIsaExts)
2839	{
2840	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
2841	"CMPXCHG16B"
2842	"\|MONITOR"
2843	"\|MWaitExtensions"
2844	"\|SSE4.1"
2845	"\|SSE4.2"
2846	"\|XSAVE"
2847	"\|AVX"
2848	"\|AVX2"
2849	"\|AESNI"
2850	"\|PCLMUL"
2851	"\|POPCNT"
2852	"\|MOVBE"
2853	"\|RDRAND"
2854	"\|RDSEED"
2855	"\|ADX"
2856	"\|CLFLUSHOPT"
2857	"\|SHA"
2858	"\|FSGSBASE"
2859	"\|PCID"
2860	"\|INVPCID"
2861	"\|FlushCmdMsr"
2862	"\|MdsClear"
2863	"\|ArchCapMsr"
2864	"\|FMA"
2865	"\|F16C"
2866	"\|ABM"
2867	"\|SSE4A"
2868	"\|MISALNSSE"
2869	"\|3DNOWPRF"
2870	"\|AXMMX"
2871	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
2872	if (RT_FAILURE(rc))
2873	return rc;
2874	}
2875
2876	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, true}
2877	* Expose CMPXCHG16B to the guest if available. All host CPUs which support
2878	* hardware virtualization have it.
2879	*/
2880	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, true);
2881	AssertLogRelRCReturn(rc, rc);
2882
2883	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
2884	* Expose MONITOR/MWAIT instructions to the guest.
2885	*/
2886	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
2887	AssertLogRelRCReturn(rc, rc);
2888
2889	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
2890	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
2891	* break on interrupt feature (bit 1).
2892	*/
2893	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
2894	AssertLogRelRCReturn(rc, rc);
2895
2896	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
2897	* Expose SSE4.1 to the guest if available.
2898	*/
2899	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
2900	AssertLogRelRCReturn(rc, rc);
2901
2902	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
2903	* Expose SSE4.2 to the guest if available.
2904	*/
2905	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
2906	AssertLogRelRCReturn(rc, rc);
2907
2908	#ifdef RT_ARCH_AMD64
2909	bool const fMayHaveXSave = pVM->cpum.s.HostFeatures.s.fXSaveRstor
2910	&& pVM->cpum.s.HostFeatures.s.fOpSysXSaveRstor
2911	&& ( VM_IS_NEM_ENABLED(pVM)
2912	? NEMHCGetFeatures(pVM) & NEM_FEAT_F_XSAVE_XRSTOR
2913	: VM_IS_EXEC_ENGINE_IEM(pVM)
2914	? true
2915	: fNestedPagingAndFullGuestExec);
2916	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
2917	#else
2918	bool const fMayHaveXSave = true;
2919	uint64_t const fXStateHostMask = XSAVE_C_YMM \| XSAVE_C_SSE \| XSAVE_C_X87;
2920	#endif
2921
2922	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
2923	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
2924	* default is to only expose this to VMs with nested paging and AMD-V or
2925	* unrestricted guest execution mode. Not possible to force this one without
2926	* host support at the moment.
2927	*/
2928	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, true,
2929	fMayHaveXSave /fAllowed/);
2930	AssertLogRelRCReturn(rc, rc);
2931
2932	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
2933	* Expose the AVX instruction set extensions to the guest if available and
2934	* XSAVE is exposed too. For the time being the default is to only expose this
2935	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
2936	*/
2937	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
2938	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
2939	AssertLogRelRCReturn(rc, rc);
2940
2941	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
2942	* Expose the AVX2 instruction set extensions to the guest if available and
2943	* XSAVE is exposed too. For the time being the default is to only expose this
2944	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
2945	*/
2946	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
2947	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
2948	AssertLogRelRCReturn(rc, rc);
2949
2950	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
2951	* Whether to expose the AES instructions to the guest. For the time being the
2952	* default is to only do this for VMs with nested paging and AMD-V or
2953	* unrestricted guest mode.
2954	*/
2955	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
2956	AssertLogRelRCReturn(rc, rc);
2957
2958	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
2959	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
2960	* being the default is to only do this for VMs with nested paging and AMD-V or
2961	* unrestricted guest mode.
2962	*/
2963	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
2964	AssertLogRelRCReturn(rc, rc);
2965
2966	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, true}
2967	* Whether to expose the POPCNT instructions to the guest.
2968	*/
2969	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, CPUMISAEXTCFG_ENABLED_SUPPORTED);
2970	AssertLogRelRCReturn(rc, rc);
2971
2972	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
2973	* Whether to expose the MOVBE instructions to the guest. For the time
2974	* being the default is to only do this for VMs with nested paging and AMD-V or
2975	* unrestricted guest mode.
2976	*/
2977	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, true);
2978	AssertLogRelRCReturn(rc, rc);
2979
2980	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
2981	* Whether to expose the RDRAND instructions to the guest. For the time being
2982	* the default is to only do this for VMs with nested paging and AMD-V or
2983	* unrestricted guest mode.
2984	*/
2985	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
2986	AssertLogRelRCReturn(rc, rc);
2987
2988	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
2989	* Whether to expose the RDSEED instructions to the guest. For the time being
2990	* the default is to only do this for VMs with nested paging and AMD-V or
2991	* unrestricted guest mode.
2992	*/
2993	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
2994	AssertLogRelRCReturn(rc, rc);
2995
2996	/** @cfgm{/CPUM/IsaExts/ADX, isaextcfg, depends}
2997	* Whether to expose the ADX instructions to the guest. For the time being
2998	* the default is to only do this for VMs with nested paging and AMD-V or
2999	* unrestricted guest mode.
3000	*/
3001	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ADX", &pConfig->enmAdx, fNestedPagingAndFullGuestExec);
3002	AssertLogRelRCReturn(rc, rc);
3003
3004	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
3005	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
3006	* being the default is to only do this for VMs with nested paging and AMD-V or
3007	* unrestricted guest mode.
3008	*/
3009	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
3010	AssertLogRelRCReturn(rc, rc);
3011
3012	/** @cfgm{/CPUM/IsaExts/SHA, isaextcfg, depends}
3013	* Whether to expose the SHA instructions to the guest. For the time being
3014	* the default is to only do this for VMs with nested paging and AMD-V or
3015	* unrestricted guest mode.
3016	*/
3017	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SHA", &pConfig->enmSha, fNestedPagingAndFullGuestExec);
3018	AssertLogRelRCReturn(rc, rc);
3019
3020	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
3021	* Whether to expose the read/write FSGSBASE instructions to the guest.
3022	*/
3023	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
3024	AssertLogRelRCReturn(rc, rc);
3025
3026	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
3027	* Whether to expose the PCID feature to the guest.
3028	*/
3029	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
3030	AssertLogRelRCReturn(rc, rc);
3031
3032	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
3033	* Whether to expose the INVPCID instruction to the guest.
3034	*/
3035	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
3036	AssertLogRelRCReturn(rc, rc);
3037
3038	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
3039	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
3040	*/
3041	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
3042	AssertLogRelRCReturn(rc, rc);
3043
3044	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
3045	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
3046	* the guest. Requires FlushCmdMsr to be present too.
3047	*/
3048	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
3049	AssertLogRelRCReturn(rc, rc);
3050
3051	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
3052	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
3053	*/
3054	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED_OR_NOT_AMD64);
3055	AssertLogRelRCReturn(rc, rc);
3056
3057	/** @cfgm{/CPUM/IsaExts/FMA, boolean, depends}
3058	* Expose the FMA instruction set extensions to the guest if available and
3059	* XSAVE is exposed too. For the time being the default is to only expose this
3060	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3061	*/
3062	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "FMA", &pConfig->enmFma, fNestedPagingAndFullGuestExec /* temporarily */,
3063	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3064	AssertLogRelRCReturn(rc, rc);
3065
3066	/** @cfgm{/CPUM/IsaExts/F16C, boolean, depends}
3067	* Expose the F16C instruction set extensions to the guest if available and
3068	* XSAVE is exposed too. For the time being the default is to only expose this
3069	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3070	*/
3071	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "F16C", &pConfig->enmF16c, fNestedPagingAndFullGuestExec /* temporarily */,
3072	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3073	AssertLogRelRCReturn(rc, rc);
3074
3075
3076	/* AMD: */
3077
3078	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, true}
3079	* Whether to expose the AMD ABM instructions to the guest.
3080	*/
3081	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, CPUMISAEXTCFG_ENABLED_SUPPORTED);
3082	AssertLogRelRCReturn(rc, rc);
3083
3084	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
3085	* Whether to expose the AMD SSE4A instructions to the guest. For the time
3086	* being the default is to only do this for VMs with nested paging and AMD-V or
3087	* unrestricted guest mode.
3088	*/
3089	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
3090	AssertLogRelRCReturn(rc, rc);
3091
3092	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
3093	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
3094	* the time being the default is to only do this for VMs with nested paging and
3095	* AMD-V or unrestricted guest mode.
3096	*/
3097	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
3098	AssertLogRelRCReturn(rc, rc);
3099
3100	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
3101	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
3102	* For the time being the default is to only do this for VMs with nested paging
3103	* and AMD-V or unrestricted guest mode.
3104	*/
3105	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
3106	AssertLogRelRCReturn(rc, rc);
3107
3108	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
3109	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
3110	* the default is to only do this for VMs with nested paging and AMD-V or
3111	* unrestricted guest mode.
3112	*/
3113	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
3114	AssertLogRelRCReturn(rc, rc);
3115
3116	return VINF_SUCCESS;
3117	}
3118
3119
3120	/**
3121	* Checks and fixes the maximum physical address width supported by the
3122	* variable-range MTRR MSRs to be consistent with what is reported in CPUID.
3123	*
3124	* @returns VBox status code.
3125	* @param pVM The cross context VM structure.
3126	* @param cVarMtrrs The number of variable-range MTRRs reported to the guest.
3127	*/
3128	static int cpumR3FixVarMtrrPhysAddrWidths(PVM pVM, uint8_t const cVarMtrrs)
3129	{
3130	AssertLogRelMsgReturn(cVarMtrrs <= RT_ELEMENTS(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr.aMtrrVarMsrs),
3131	("Invalid number of variable range MTRRs reported (%u)\n", cVarMtrrs),
3132	VERR_CPUM_IPE_2);
3133
3134	/*
3135	* CPUID determines the actual maximum physical address width reported and supported.
3136	* If the CPU DB profile reported fewer address bits, we must correct it here by
3137	* updating the MSR write #GP masks of all the variable-range MTRR MSRs. Otherwise,
3138	* they cause problems when guests write to these MTRR MSRs, see @bugref{10498#c32}.
3139	*/
3140	PCPUMMSRRANGE pBaseRange0 = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_PHYSBASE0);
3141	AssertLogRelMsgReturn(pBaseRange0, ("Failed to lookup the IA32_MTRR_PHYSBASE[0] MSR range\n"), VERR_NOT_FOUND);
3142
3143	PCPUMMSRRANGE pMaskRange0 = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_PHYSMASK0);
3144	AssertLogRelMsgReturn(pMaskRange0, ("Failed to lookup the IA32_MTRR_PHYSMASK[0] MSR range\n"), VERR_NOT_FOUND);
3145
3146	uint64_t const fPhysBaseWrGpMask = pBaseRange0->fWrGpMask;
3147	uint64_t const fPhysMaskWrGpMask = pMaskRange0->fWrGpMask;
3148
3149	uint8_t const cGuestMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
3150	uint8_t const cProfilePhysBaseMaxPhysAddrWidth = ASMBitLastSetU64(~fPhysBaseWrGpMask);
3151	uint8_t const cProfilePhysMaskMaxPhysAddrWidth = ASMBitLastSetU64(~fPhysMaskWrGpMask);
3152
3153	AssertLogRelMsgReturn(cProfilePhysBaseMaxPhysAddrWidth == cProfilePhysMaskMaxPhysAddrWidth,
3154	("IA32_MTRR_PHYSBASE and IA32_MTRR_PHYSMASK report different physical address widths (%u and %u)\n",
3155	cProfilePhysBaseMaxPhysAddrWidth, cProfilePhysMaskMaxPhysAddrWidth),
3156	VERR_CPUM_IPE_2);
3157	AssertLogRelMsgReturn(cProfilePhysBaseMaxPhysAddrWidth > 12 && cProfilePhysBaseMaxPhysAddrWidth <= 64,
3158	("IA32_MTRR_PHYSBASE and IA32_MTRR_PHYSMASK reports an invalid physical address width of %u bits\n",
3159	cProfilePhysBaseMaxPhysAddrWidth), VERR_CPUM_IPE_2);
3160
3161	if (cProfilePhysBaseMaxPhysAddrWidth < cGuestMaxPhysAddrWidth)
3162	{
3163	uint64_t fNewPhysBaseWrGpMask = fPhysBaseWrGpMask;
3164	uint64_t fNewPhysMaskWrGpMask = fPhysMaskWrGpMask;
3165	int8_t cBits = cGuestMaxPhysAddrWidth - cProfilePhysBaseMaxPhysAddrWidth;
3166	while (cBits)
3167	{
3168	uint64_t const fWrGpAndMask = ~(uint64_t)RT_BIT_64(cProfilePhysBaseMaxPhysAddrWidth + cBits - 1);
3169	fNewPhysBaseWrGpMask &= fWrGpAndMask;
3170	fNewPhysMaskWrGpMask &= fWrGpAndMask;
3171	--cBits;
3172	}
3173
3174	for (uint8_t iVarMtrr = 1; iVarMtrr < cVarMtrrs; iVarMtrr++)
3175	{
3176	PCPUMMSRRANGE pBaseRange = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_PHYSBASE0 + (iVarMtrr * 2));
3177	AssertLogRelMsgReturn(pBaseRange, ("Failed to lookup the IA32_MTRR_PHYSBASE[%u] MSR range\n", iVarMtrr),
3178	VERR_NOT_FOUND);
3179
3180	PCPUMMSRRANGE pMaskRange = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_PHYSMASK0 + (iVarMtrr * 2));
3181	AssertLogRelMsgReturn(pMaskRange, ("Failed to lookup the IA32_MTRR_PHYSMASK[%u] MSR range\n", iVarMtrr),
3182	VERR_NOT_FOUND);
3183
3184	AssertLogRelMsgReturn(pBaseRange->fWrGpMask == fPhysBaseWrGpMask,
3185	("IA32_MTRR_PHYSBASE[%u] write GP mask (%#016RX64) differs from IA32_MTRR_PHYSBASE[0] write GP mask (%#016RX64)\n",
3186	iVarMtrr, pBaseRange->fWrGpMask, fPhysBaseWrGpMask),
3187	VERR_CPUM_IPE_1);
3188	AssertLogRelMsgReturn(pMaskRange->fWrGpMask == fPhysMaskWrGpMask,
3189	("IA32_MTRR_PHYSMASK[%u] write GP mask (%#016RX64) differs from IA32_MTRR_PHYSMASK[0] write GP mask (%#016RX64)\n",
3190	iVarMtrr, pMaskRange->fWrGpMask, fPhysMaskWrGpMask),
3191	VERR_CPUM_IPE_1);
3192
3193	pBaseRange->fWrGpMask = fNewPhysBaseWrGpMask;
3194	pMaskRange->fWrGpMask = fNewPhysMaskWrGpMask;
3195	}
3196
3197	pBaseRange0->fWrGpMask = fNewPhysBaseWrGpMask;
3198	pMaskRange0->fWrGpMask = fNewPhysMaskWrGpMask;
3199
3200	LogRel(("CPUM: Updated IA32_MTRR_PHYSBASE[0..%u] MSR write #GP mask (old=%#016RX64 new=%#016RX64)\n",
3201	cVarMtrrs - 1, fPhysBaseWrGpMask, fNewPhysBaseWrGpMask));
3202	LogRel(("CPUM: Updated IA32_MTRR_PHYSMASK[0..%u] MSR write #GP mask (old=%#016RX64 new=%#016RX64)\n",
3203	cVarMtrrs - 1, fPhysMaskWrGpMask, fNewPhysMaskWrGpMask));
3204	}
3205
3206	return VINF_SUCCESS;
3207	}
3208
3209
3210	/**
3211	* Inserts variable-range MTRR MSR ranges based on the given count.
3212	*
3213	* Since we need to insert the MSRs beyond what the CPU profile has inserted, we
3214	* reinsert the whole range here since the variable-range MTRR MSR read+write
3215	* functions handle ranges as well as the \#GP checking.
3216	*
3217	* @returns VBox status code.
3218	* @param pVM The cross context VM structure.
3219	* @param cVarMtrrs The number of variable-range MTRRs to insert. This must be
3220	* less than or equal to CPUMCTX_MAX_MTRRVAR_COUNT.
3221	*/
3222	static int cpumR3VarMtrrMsrRangeInsert(PVM pVM, uint8_t const cVarMtrrs)
3223	{
3224	#ifdef VBOX_WITH_STATISTICS
3225	# define CPUM_MTRR_PHYSBASE_MSRRANGE(a_uMsr, a_uValue, a_szName) \
3226	{ (a_uMsr), (a_uMsr), kCpumMsrRdFn_Ia32MtrrPhysBaseN, kCpumMsrWrFn_Ia32MtrrPhysBaseN, 0, 0, a_uValue, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
3227	# define CPUM_MTRR_PHYSMASK_MSRRANGE(a_uMsr, a_uValue, a_szName) \
3228	{ (a_uMsr), (a_uMsr), kCpumMsrRdFn_Ia32MtrrPhysMaskN, kCpumMsrWrFn_Ia32MtrrPhysMaskN, 0, 0, a_uValue, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
3229	#else
3230	# define CPUM_MTRR_PHYSBASE_MSRRANGE(a_uMsr, a_uValue, a_szName) \
3231	{ (a_uMsr), (a_uMsr), kCpumMsrRdFn_Ia32MtrrPhysBaseN, kCpumMsrWrFn_Ia32MtrrPhysBaseN, 0, 0, a_uValue, 0, 0, a_szName }
3232	# define CPUM_MTRR_PHYSMASK_MSRRANGE(a_uMsr, a_uValue, a_szName) \
3233	{ (a_uMsr), (a_uMsr), kCpumMsrRdFn_Ia32MtrrPhysMaskN, kCpumMsrWrFn_Ia32MtrrPhysMaskN, 0, 0, a_uValue, 0, 0, a_szName }
3234	#endif
3235	static CPUMMSRRANGE const s_aMsrRanges_MtrrPhysBase[CPUMCTX_MAX_MTRRVAR_COUNT] =
3236	{
3237	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE0, 0, "MSR_IA32_MTRR_PHYSBASE0"),
3238	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE1, 1, "MSR_IA32_MTRR_PHYSBASE1"),
3239	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE2, 2, "MSR_IA32_MTRR_PHYSBASE2"),
3240	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE3, 3, "MSR_IA32_MTRR_PHYSBASE3"),
3241	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE4, 4, "MSR_IA32_MTRR_PHYSBASE4"),
3242	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE5, 5, "MSR_IA32_MTRR_PHYSBASE5"),
3243	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE6, 6, "MSR_IA32_MTRR_PHYSBASE6"),
3244	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE7, 7, "MSR_IA32_MTRR_PHYSBASE7"),
3245	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE8, 8, "MSR_IA32_MTRR_PHYSBASE8"),
3246	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9, 9, "MSR_IA32_MTRR_PHYSBASE9"),
3247	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 2, 10, "MSR_IA32_MTRR_PHYSBASE10"),
3248	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 4, 11, "MSR_IA32_MTRR_PHYSBASE11"),
3249	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 6, 12, "MSR_IA32_MTRR_PHYSBASE12"),
3250	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 8, 13, "MSR_IA32_MTRR_PHYSBASE13"),
3251	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 10, 14, "MSR_IA32_MTRR_PHYSBASE14"),
3252	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 12, 15, "MSR_IA32_MTRR_PHYSBASE15"),
3253	};
3254	static CPUMMSRRANGE const s_aMsrRanges_MtrrPhysMask[CPUMCTX_MAX_MTRRVAR_COUNT] =
3255	{
3256	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK0, 0, "MSR_IA32_MTRR_PHYSMASK0"),
3257	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK1, 1, "MSR_IA32_MTRR_PHYSMASK1"),
3258	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK2, 2, "MSR_IA32_MTRR_PHYSMASK2"),
3259	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK3, 3, "MSR_IA32_MTRR_PHYSMASK3"),
3260	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK4, 4, "MSR_IA32_MTRR_PHYSMASK4"),
3261	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK5, 5, "MSR_IA32_MTRR_PHYSMASK5"),
3262	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK6, 6, "MSR_IA32_MTRR_PHYSMASK6"),
3263	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK7, 7, "MSR_IA32_MTRR_PHYSMASK7"),
3264	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK8, 8, "MSR_IA32_MTRR_PHYSMASK8"),
3265	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9, 9, "MSR_IA32_MTRR_PHYSMASK9"),
3266	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 2, 10, "MSR_IA32_MTRR_PHYSMASK10"),
3267	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 4, 11, "MSR_IA32_MTRR_PHYSMASK11"),
3268	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 6, 12, "MSR_IA32_MTRR_PHYSMASK12"),
3269	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 8, 13, "MSR_IA32_MTRR_PHYSMASK13"),
3270	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 10, 14, "MSR_IA32_MTRR_PHYSMASK14"),
3271	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 12, 15, "MSR_IA32_MTRR_PHYSMASK15"),
3272	};
3273	AssertCompile(RT_ELEMENTS(s_aMsrRanges_MtrrPhysBase) == RT_ELEMENTS(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr.aMtrrVarMsrs));
3274	AssertCompile(RT_ELEMENTS(s_aMsrRanges_MtrrPhysMask) == RT_ELEMENTS(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr.aMtrrVarMsrs));
3275
3276	Assert(cVarMtrrs <= RT_ELEMENTS(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr.aMtrrVarMsrs));
3277	for (unsigned i = 0; i < cVarMtrrs; i++)
3278	{
3279	int rc = CPUMR3MsrRangesInsert(pVM, &s_aMsrRanges_MtrrPhysBase[i]);
3280	AssertLogRelRCReturn(rc, rc);
3281	rc = CPUMR3MsrRangesInsert(pVM, &s_aMsrRanges_MtrrPhysMask[i]);
3282	AssertLogRelRCReturn(rc, rc);
3283	}
3284	return VINF_SUCCESS;
3285
3286	#undef CPUM_MTRR_PHYSBASE_MSRRANGE
3287	#undef CPUM_MTRR_PHYSMASK_MSRRANGE
3288	}
3289
3290
3291	/**
3292	* Initialize MTRR capability based on what the guest CPU profile (typically host)
3293	* supports.
3294	*
3295	* @returns VBox status code.
3296	* @param pVM The cross context VM structure.
3297	* @param fMtrrVarCountIsVirt Whether the variable-range MTRR count is fully
3298	* virtualized (@c true) or derived from the CPU
3299	* profile (@c false).
3300	*/
3301	static int cpumR3InitMtrrCap(PVM pVM, bool fMtrrVarCountIsVirt)
3302	{
3303	#ifdef RT_ARCH_AMD64
3304	Assert(pVM->cpum.s.HostFeatures.s.fMtrr);
3305	#endif
3306
3307	/* Lookup the number of variable-range MTRRs supported by the CPU profile. */
3308	PCCPUMMSRRANGE pMtrrCapRange = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_CAP);
3309	AssertLogRelMsgReturn(pMtrrCapRange, ("Failed to lookup IA32_MTRR_CAP MSR range\n"), VERR_NOT_FOUND);
3310	uint8_t const cProfileVarRangeRegs = pMtrrCapRange->uValue & MSR_IA32_MTRR_CAP_VCNT_MASK;
3311
3312	/* Construct guest MTRR support capabilities. */
3313	uint8_t const cGuestVarRangeRegs = fMtrrVarCountIsVirt ? CPUMCTX_MAX_MTRRVAR_COUNT
3314	: RT_MIN(cProfileVarRangeRegs, CPUMCTX_MAX_MTRRVAR_COUNT);
3315	uint64_t const uGstMtrrCap = cGuestVarRangeRegs
3316	\| MSR_IA32_MTRR_CAP_FIX
3317	\| MSR_IA32_MTRR_CAP_WC;
3318	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3319	{
3320	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3321	pVCpu->cpum.s.GuestMsrs.msr.MtrrCap = uGstMtrrCap;
3322	pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = MSR_IA32_MTRR_DEF_TYPE_FIXED_EN
3323	\| MSR_IA32_MTRR_DEF_TYPE_MTRR_EN
3324	\| X86_MTRR_MT_UC;
3325	}
3326
3327	if (fMtrrVarCountIsVirt)
3328	{
3329	/*
3330	* Insert the full variable-range MTRR MSR range ourselves so it extends beyond what is
3331	* typically reported by the hardware CPU profile.
3332	*/
3333	LogRel(("CPUM: Enabled fixed-range MTRRs and %u (virtualized) variable-range MTRRs\n", cGuestVarRangeRegs));
3334	return cpumR3VarMtrrMsrRangeInsert(pVM, cGuestVarRangeRegs);
3335	}
3336
3337	/*
3338	* Ensure that the maximum physical address width supported by the variable-range MTRRs
3339	* are consistent with what is reported to the guest via CPUID.
3340	*/
3341	LogRel(("CPUM: Enabled fixed-range MTRRs and %u (CPU profile derived) variable-range MTRRs\n", cGuestVarRangeRegs));
3342	return cpumR3FixVarMtrrPhysAddrWidths(pVM, cGuestVarRangeRegs);
3343	}
3344
3345
3346	/**
3347	* Initializes the emulated CPU's CPUID & MSR information.
3348	*
3349	* @returns VBox status code.
3350	* @param pVM The cross context VM structure.
3351	* @param pHostMsrs Pointer to the host MSRs.
3352	*/
3353	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
3354	{
3355	Assert(pHostMsrs);
3356
3357	PCPUM pCpum = &pVM->cpum.s;
3358	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
3359
3360	/*
3361	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
3362	* on construction and manage everything from here on.
3363	*/
3364	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3365	{
3366	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3367	pVCpu->cpum.s.fCpuIdApicFeatureVisible = true;
3368	}
3369
3370	/*
3371	* Read the configuration.
3372	*/
3373	CPUMCPUIDCONFIG Config;
3374	RT_ZERO(Config);
3375
3376	bool const fNestedPagingAndFullGuestExec = VM_IS_NEM_ENABLED(pVM)
3377	\|\| HMAreNestedPagingAndFullGuestExecEnabled(pVM);
3378	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, fNestedPagingAndFullGuestExec);
3379	AssertRCReturn(rc, rc);
3380
3381	/*
3382	* Get the guest CPU data from the database and/or the host.
3383	*
3384	* The CPUID and MSRs are currently living on the regular heap to avoid
3385	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
3386	* API for the hyper heap). This means special cleanup considerations.
3387	*/
3388	/** @todo The hyper heap will be removed ASAP, so the final destination is
3389	* now a fixed sized arrays in the VM structure. Maybe we can simplify
3390	* this allocation fun a little now? Or maybe it's too convenient for
3391	* the CPU reporter code... No time to figure that out now. */
3392	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
3393	if (RT_FAILURE(rc))
3394	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
3395	? VMSetError(pVM, rc, RT_SRC_POS,
3396	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
3397	: rc;
3398
3399	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
3400	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
3401	{
3402	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
3403	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
3404	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
3405	}
3406	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
3407	#else
3408	LogRel(("CPUM: MXCSR_MASK=%#x\n", pCpum->GuestInfo.fMxCsrMask));
3409	#endif
3410
3411	/** @cfgm{/CPUM/GuestMicrocodeRev,32-bit}
3412	* CPU microcode revision number to use. If UINT32_MAX we use the host
3413	* revision of the host CPU for the host-cpu profile and the database entry if a
3414	* specific one is selected (amd64 host only). */
3415	rc = CFGMR3QueryU32Def(pCpumCfg, "GuestMicrocodeRevision", &pCpum->GuestInfo.uMicrocodeRevision, UINT32_MAX);
3416	AssertLogRelRCReturn(rc, rc);
3417	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
3418	if ( pCpum->GuestInfo.uMicrocodeRevision == UINT32_MAX
3419	&& strcmp(Config.szCpuName, "host") == 0)
3420	{
3421	rc = SUPR3QueryMicrocodeRev(&pCpum->GuestInfo.uMicrocodeRevision);
3422	if (RT_FAILURE(rc))
3423	pCpum->GuestInfo.uMicrocodeRevision = UINT32_MAX;
3424	}
3425	#endif
3426
3427	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
3428	* Overrides the guest MSRs.
3429	*/
3430	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
3431
3432	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
3433	* Overrides the CPUID leaf values (from the host CPU usually) used for
3434	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
3435	* values when moving a VM to a different machine. Another use is restricting
3436	* (or extending) the feature set exposed to the guest. */
3437	if (RT_SUCCESS(rc))
3438	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
3439
3440	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
3441	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
3442	"Found unsupported configuration node '/CPUM/CPUID/'. "
3443	"Please use IMachine::setCPUIDLeaf() instead.");
3444
3445	CPUMMSRS GuestMsrs;
3446	RT_ZERO(GuestMsrs);
3447
3448	/*
3449	* Pre-explode the CPUID info.
3450	*/
3451	if (RT_SUCCESS(rc))
3452	rc = cpumCpuIdExplodeFeaturesX86(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
3453	&pCpum->GuestFeatures);
3454
3455	/*
3456	* Sanitize the cpuid information passed on to the guest.
3457	*/
3458	if (RT_SUCCESS(rc))
3459	{
3460	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
3461	if (RT_SUCCESS(rc))
3462	{
3463	cpumR3CpuIdLimitLeaves(pCpum, &Config);
3464	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
3465	}
3466	}
3467
3468	/*
3469	* Move the CPUID array over to the static VM structure allocation
3470	* and explode guest CPU features again. We must do this before
3471	* reconciling MSRs with CPUIDs and applying any fudging (esp on ARM64).
3472	*/
3473	if (RT_SUCCESS(rc))
3474	{
3475	void * const pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
3476	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
3477	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
3478	AssertLogRelRC(rc);
3479	RTMemFree(pvFree);
3480	if (RT_SUCCESS(rc))
3481	{
3482	/*
3483	* Setup MSRs introduced in microcode updates or that are otherwise not in
3484	* the CPU profile, but are advertised in the CPUID info we just sanitized.
3485	*/
3486	if (RT_SUCCESS(rc))
3487	rc = cpumR3MsrReconcileWithCpuId(pVM);
3488	/*
3489	* MSR fudging.
3490	*/
3491	if (RT_SUCCESS(rc))
3492	{
3493	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
3494	* Fudges some common MSRs if not present in the selected CPU database entry.
3495	* This is for trying to keep VMs running when moved between different hosts
3496	* and different CPU vendors. */
3497	bool fEnable;
3498	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
3499	if (RT_SUCCESS(rc) && fEnable)
3500	{
3501	rc = cpumR3MsrApplyFudge(pVM);
3502	AssertLogRelRC(rc);
3503	}
3504	}
3505	if (RT_SUCCESS(rc))
3506	{
3507	/*
3508	* Move the MSR arrays over to the static VM structure allocation.
3509	*/
3510	AssertFatalMsg(pCpum->GuestInfo.cMsrRanges <= RT_ELEMENTS(pCpum->GuestInfo.aMsrRanges),
3511	("%u\n", pCpum->GuestInfo.cMsrRanges));
3512	memcpy(pCpum->GuestInfo.aMsrRanges, pCpum->GuestInfo.paMsrRangesR3,
3513	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges);
3514	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3515	pCpum->GuestInfo.paMsrRangesR3 = pCpum->GuestInfo.aMsrRanges;
3516
3517	/*
3518	* Some more configuration that we're applying at the end of everything
3519	* via the CPUMR3SetGuestCpuIdFeature API.
3520	*/
3521
3522	/* Check if 64-bit guest supported was enabled. */
3523	bool fEnable64bit;
3524	rc = CFGMR3QueryBoolDef(pCpumCfg, "Enable64bit", &fEnable64bit, false);
3525	AssertRCReturn(rc, rc);
3526	if (fEnable64bit)
3527	{
3528	/* In case of a CPU upgrade: */
3529	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
3530	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* (Long mode only on Intel CPUs.) */
3531	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3532	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
3533	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3534
3535	/* The actual feature: */
3536	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
3537	}
3538
3539	/* Check if PAE was explicitely enabled by the user. */
3540	bool fEnable;
3541	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, fEnable64bit);
3542	AssertRCReturn(rc, rc);
3543	if (fEnable && !pVM->cpum.s.GuestFeatures.fPae)
3544	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3545
3546	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
3547	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, fEnable64bit);
3548	AssertRCReturn(rc, rc);
3549	if (fEnable && !pVM->cpum.s.GuestFeatures.fNoExecute)
3550	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3551
3552	/* Check if speculation control is enabled. */
3553	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
3554	AssertRCReturn(rc, rc);
3555	if (fEnable)
3556	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
3557	else
3558	{
3559	/*
3560	* Set the "SSBD-not-needed" flag to work around a bug in some Linux kernels when the VIRT_SPEC_CTL
3561	* feature is not exposed on AMD CPUs and there is only 1 vCPU configured.
3562	* This was observed with kernel "4.15.0-29-generic #31~16.04.1-Ubuntu" but more versions are likely affected.
3563	*
3564	* The kernel doesn't initialize a lock and causes a NULL pointer exception later on when configuring SSBD:
3565	* EIP: _raw_spin_lock+0x14/0x30
3566	* EFLAGS: 00010046 CPU: 0
3567	* EAX: 00000000 EBX: 00000001 ECX: 00000004 EDX: 00000000
3568	* ESI: 00000000 EDI: 00000000 EBP: ee023f1c ESP: ee023f18
3569	* DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
3570	* CR0: 80050033 CR2: 00000004 CR3: 3671c180 CR4: 000006f0
3571	* Call Trace:
3572	* speculative_store_bypass_update+0x8e/0x180
3573	* ssb_prctl_set+0xc0/0xe0
3574	* arch_seccomp_spec_mitigate+0x1d/0x20
3575	* do_seccomp+0x3cb/0x610
3576	* SyS_seccomp+0x16/0x20
3577	* do_fast_syscall_32+0x7f/0x1d0
3578	* entry_SYSENTER_32+0x4e/0x7c
3579	*
3580	* The lock would've been initialized in process.c:speculative_store_bypass_ht_init() called from two places in smpboot.c.
3581	* First when a secondary CPU is started and second in native_smp_prepare_cpus() which is not called in a single vCPU environment.
3582	*
3583	* As spectre control features are completely disabled anyway when we arrived here there is no harm done in informing the
3584	* guest to not even try.
3585	*/
3586	if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3587	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3588	{
3589	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x80000008), 0);
3590	if (pLeaf)
3591	{
3592	pLeaf->uEbx \|= X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED;
3593	LogRel(("CPUM: Set SSBD not required flag for AMD to work around some buggy Linux kernels!\n"));
3594	}
3595	}
3596	}
3597
3598	/*
3599	* MTRR support.
3600	* We've always reported the MTRR feature bit in CPUID.
3601	* Here we allow exposing MTRRs with reasonable default values (especially required
3602	* by Windows 10 guests with Hyper-V enabled). The MTRR support isn't feature
3603	* complete, see @bugref{10318} and bugref{10498}.
3604	*/
3605	if (pVM->cpum.s.GuestFeatures.fMtrr)
3606	{
3607	/** @cfgm{/CPUM/MtrrWrite, boolean, true}
3608	* Whether to enable MTRR read-write support. This overrides the MTRR read-only CFGM
3609	* setting. */
3610	bool fEnableMtrrReadWrite;
3611	rc = CFGMR3QueryBoolDef(pCpumCfg, "MtrrReadWrite", &fEnableMtrrReadWrite, true);
3612	AssertRCReturn(rc, rc);
3613	if (fEnableMtrrReadWrite)
3614	{
3615	pVM->cpum.s.fMtrrRead = true;
3616	pVM->cpum.s.fMtrrWrite = true;
3617	LogRel(("CPUM: Enabled MTRR read-write support\n"));
3618	}
3619	else
3620	{
3621	/** @cfgm{/CPUM/MtrrReadOnly, boolean, false}
3622	* Whether to enable MTRR read-only support and to initialize mapping of guest
3623	* memory via MTRRs. When disabled, MTRRs are left blank, returns 0 on reads and
3624	* ignores writes. Some guests like GNU/Linux recognize a virtual system when MTRRs
3625	* are left blank but some guests may expect their RAM to be mapped via MTRRs
3626	* similar to real hardware. */
3627	rc = CFGMR3QueryBoolDef(pCpumCfg, "MtrrReadOnly", &pVM->cpum.s.fMtrrRead, false);
3628	AssertRCReturn(rc, rc);
3629	LogRel(("CPUM: Enabled MTRR read-only support\n"));
3630	}
3631
3632	/* Setup MTRR capability based on what the guest CPU profile (typically host) supports. */
3633	Assert(!pVM->cpum.s.fMtrrWrite \|\| pVM->cpum.s.fMtrrRead);
3634	if (pVM->cpum.s.fMtrrRead)
3635	{
3636	/** @cfgm{/CPUM/MtrrVarCountIsVirtual, boolean, true}
3637	* When enabled, the number of variable-range MTRRs are virtualized. When disabled,
3638	* the number of variable-range MTRRs are derived from the CPU profile. Unless
3639	* guests have problems with a virtualized number of variable-range MTRRs, it is
3640	* recommended to keep this enabled so that there are sufficient MTRRs to fully
3641	* describe all regions of the guest RAM. */
3642	bool fMtrrVarCountIsVirt;
3643	rc = CFGMR3QueryBoolDef(pCpumCfg, "MtrrVarCountIsVirtual", &fMtrrVarCountIsVirt, true);
3644	AssertRCReturn(rc, rc);
3645
3646	rc = cpumR3InitMtrrCap(pVM, fMtrrVarCountIsVirt);
3647	if (RT_SUCCESS(rc))
3648	{ /* likely */ }
3649	else
3650	return rc;
3651	}
3652	}
3653
3654	/*
3655	* Finally, initialize guest VMX MSRs.
3656	*
3657	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
3658	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
3659	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
3660	*/
3661	/** @todo r=bird: given that long mode never used to be enabled before the
3662	* VMINITCOMPLETED_RING0 state, and we're a lot earlier here in ring-3
3663	* init, the above comment cannot be entirely accurate. */
3664	if (pVM->cpum.s.GuestFeatures.fVmx)
3665	{
3666	Assert(Config.fNestedHWVirt);
3667	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, pCpumCfg, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
3668
3669	/* Copy MSRs to all VCPUs */
3670	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
3671	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3672	{
3673	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3674	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
3675	}
3676	}
3677
3678	return VINF_SUCCESS;
3679	}
3680
3681	/*
3682	* Failed before/while switching to internal VM structure storage.
3683	*/
3684	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
3685	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
3686	}
3687	}
3688	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3689	pCpum->GuestInfo.paMsrRangesR3 = NULL;
3690	return rc;
3691	}
3692
3693
3694	/**
3695	* Sets a CPUID feature bit during VM initialization.
3696	*
3697	* Since the CPUID feature bits are generally related to CPU features, other
3698	* CPUM configuration like MSRs can also be modified by calls to this API.
3699	*
3700	* @param pVM The cross context VM structure.
3701	* @param enmFeature The feature to set.
3702	*/
3703	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
3704	{
3705	PCPUMCPUIDLEAF pLeaf;
3706	PCPUMMSRRANGE pMsrRange;
3707
3708	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
3709	# define CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) \
3710	if (!pVM->cpum.s.HostFeatures.s. a_fFeature) \
3711	{ \
3712	LogRel(("CPUM: WARNING! Can't turn on " a_szFeature " when the host doesn't support it!\n")); \
3713	return; \
3714	} else do { } while (0)
3715	#else
3716	# define CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) do { } while (0)
3717	#endif
3718
3719	#define GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) \
3720	do \
3721	{ \
3722	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001)); \
3723	if (!pLeaf) \
3724	{ \
3725	LogRel(("CPUM: WARNING! Can't turn on " a_szFeature " when no 0x80000001 CPUID leaf!\n")); \
3726	return; \
3727	} \
3728	CHECK_X86_HOST_FEATURE_RET(a_fFeature,a_szFeature); \
3729	} while (0)
3730
3731	switch (enmFeature)
3732	{
3733	/*
3734	* Set the APIC bit in both feature masks.
3735	*/
3736	case CPUMCPUIDFEATURE_APIC:
3737	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3738	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3739	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
3740
3741	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3742	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3743	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
3744
3745	pVM->cpum.s.GuestFeatures.fApic = 1;
3746
3747	/* Make sure we've got the APICBASE MSR present. */
3748	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
3749	if (!pMsrRange)
3750	{
3751	static CPUMMSRRANGE const s_ApicBase =
3752	{
3753	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
3754	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
3755	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3756	/.szName = / "IA32_APIC_BASE"
3757	};
3758	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
3759	AssertLogRelRC(rc);
3760	}
3761
3762	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
3763	break;
3764
3765	/*
3766	* Set the x2APIC bit in the standard feature mask.
3767	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
3768	*/
3769	case CPUMCPUIDFEATURE_X2APIC:
3770	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3771	if (pLeaf)
3772	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
3773	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
3774
3775	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
3776	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
3777	if (pMsrRange)
3778	{
3779	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
3780	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
3781	}
3782
3783	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
3784	break;
3785
3786	/*
3787	* Set the sysenter/sysexit bit in the standard feature mask.
3788	* Assumes the caller knows what it's doing! (host must support these)
3789	*/
3790	case CPUMCPUIDFEATURE_SEP:
3791	CHECK_X86_HOST_FEATURE_RET(fSysEnter, "SEP");
3792	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3793	if (pLeaf)
3794	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
3795	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
3796	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
3797	break;
3798
3799	/*
3800	* Set the syscall/sysret bit in the extended feature mask.
3801	* Assumes the caller knows what it's doing! (host must support these)
3802	*/
3803	case CPUMCPUIDFEATURE_SYSCALL:
3804	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fSysCall, "SYSCALL/SYSRET");
3805
3806	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
3807	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
3808	pVM->cpum.s.GuestFeatures.fSysCall = 1;
3809	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
3810	break;
3811
3812	/*
3813	* Set the PAE bit in both feature masks.
3814	* Assumes the caller knows what it's doing! (host must support these)
3815	*/
3816	case CPUMCPUIDFEATURE_PAE:
3817	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3818	if (pLeaf)
3819	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
3820
3821	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3822	if ( pLeaf
3823	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3824	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3825	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
3826
3827	pVM->cpum.s.GuestFeatures.fPae = 1;
3828	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
3829	break;
3830
3831	/*
3832	* Set the LONG MODE bit in the extended feature mask.
3833	* Assumes the caller knows what it's doing! (host must support these)
3834	*/
3835	case CPUMCPUIDFEATURE_LONG_MODE:
3836	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fLongMode, "LONG MODE");
3837
3838	/* Valid for both Intel and AMD. */
3839	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
3840	pVM->cpum.s.GuestFeatures.fLongMode = 1;
3841	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
3842	if (pVM->cpum.s.GuestFeatures.fVmx)
3843	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3844	{
3845	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3846	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic &= ~VMX_BASIC_PHYSADDR_WIDTH_32BIT;
3847	}
3848	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
3849	break;
3850
3851	/*
3852	* Set the NX/XD bit in the extended feature mask.
3853	* Assumes the caller knows what it's doing! (host must support these)
3854	*/
3855	case CPUMCPUIDFEATURE_NX:
3856	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fNoExecute, "NX/XD");
3857
3858	/* Valid for both Intel and AMD. */
3859	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
3860	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
3861	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
3862	break;
3863
3864
3865	/*
3866	* Set the LAHF/SAHF support in 64-bit mode.
3867	* Assumes the caller knows what it's doing! (host must support this)
3868	*/
3869	case CPUMCPUIDFEATURE_LAHF:
3870	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fLahfSahf, "LAHF/SAHF");
3871
3872	/* Valid for both Intel and AMD. */
3873	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
3874	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
3875	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
3876	break;
3877
3878	/*
3879	* Set the RDTSCP support bit.
3880	* Assumes the caller knows what it's doing! (host must support this)
3881	*/
3882	case CPUMCPUIDFEATURE_RDTSCP:
3883	if (pVM->cpum.s.u8PortableCpuIdLevel > 0)
3884	return;
3885	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fRdTscP, "RDTSCP");
3886	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3887
3888	/* Valid for both Intel and AMD. */
3889	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
3890	pVM->cpum.s.GuestFeatures.fRdTscP = 1;
3891	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
3892	break;
3893
3894	/*
3895	* Set the Hypervisor Present bit in the standard feature mask.
3896	*/
3897	case CPUMCPUIDFEATURE_HVP:
3898	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3899	if (pLeaf)
3900	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
3901	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
3902	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
3903	break;
3904
3905	/*
3906	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
3907	* on Intel CPUs, and different on AMDs.
3908	*/
3909	case CPUMCPUIDFEATURE_SPEC_CTRL:
3910	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3911	{
3912	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
3913	#ifdef RT_ARCH_AMD64
3914	if ( !pLeaf
3915	\|\| !(pVM->cpum.s.HostFeatures.s.fIbpb \|\| pVM->cpum.s.HostFeatures.s.fIbrs))
3916	{
3917	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
3918	return;
3919	}
3920	#else
3921	if (!pLeaf)
3922	{
3923	LogRel(("CPUM: WARNING! Can't turn on Speculation Control without leaf 0x00000007!\n"));
3924	return;
3925	}
3926	#endif
3927
3928	/* The feature can be enabled. Let's see what we can actually do. */
3929	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
3930
3931	#ifdef RT_ARCH_AMD64
3932	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
3933	if (pVM->cpum.s.HostFeatures.s.fIbrs)
3934	#endif
3935	{
3936	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
3937	pVM->cpum.s.GuestFeatures.fIbrs = 1;
3938	#ifdef RT_ARCH_AMD64
3939	if (pVM->cpum.s.HostFeatures.s.fStibp)
3940	#endif
3941	{
3942	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
3943	pVM->cpum.s.GuestFeatures.fStibp = 1;
3944	}
3945
3946	/* Make sure we have the speculation control MSR... */
3947	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
3948	if (!pMsrRange)
3949	{
3950	static CPUMMSRRANGE const s_SpecCtrl =
3951	{
3952	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
3953	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
3954	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3955	/.szName = / "IA32_SPEC_CTRL"
3956	};
3957	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
3958	AssertLogRelRC(rc);
3959	}
3960
3961	/* ... and the predictor command MSR. */
3962	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
3963	if (!pMsrRange)
3964	{
3965	/** @todo incorrect fWrGpMask. */
3966	static CPUMMSRRANGE const s_SpecCtrl =
3967	{
3968	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
3969	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
3970	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3971	/.szName = / "IA32_PRED_CMD"
3972	};
3973	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
3974	AssertLogRelRC(rc);
3975	}
3976
3977	}
3978
3979	#ifdef RT_ARCH_AMD64
3980	if (pVM->cpum.s.HostFeatures.s.fArchCap)
3981	#endif
3982	{
3983	/* Install the architectural capabilities MSR. */
3984	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
3985	if (!pMsrRange)
3986	{
3987	static CPUMMSRRANGE const s_ArchCaps =
3988	{
3989	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
3990	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
3991	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
3992	/.szName = / "IA32_ARCH_CAPABILITIES"
3993	};
3994	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
3995	AssertLogRelRC(rc);
3996	}
3997
3998	/* Advertise IBRS_ALL if present at this point... */
3999	#ifdef RT_ARCH_AMD64
4000	if (pVM->cpum.s.HostFeatures.s.fArchCap & MSR_IA32_ARCH_CAP_F_IBRS_ALL)
4001	#endif
4002	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps \|= MSR_IA32_ARCH_CAP_F_IBRS_ALL);
4003	}
4004
4005	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
4006	}
4007	else if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4008	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
4009	{
4010	/* The precise details of AMD's implementation are not yet clear. */
4011	}
4012	break;
4013
4014	default:
4015	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4016	break;
4017	}
4018
4019	/** @todo can probably kill this as this API is now init time only... */
4020	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4021	{
4022	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4023	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4024	}
4025
4026	#undef GET_8000_0001_CHECK_X86_HOST_FEATURE_RET
4027	#undef CHECK_X86_HOST_FEATURE_RET
4028	}
4029
4030
4031	/**
4032	* Queries a CPUID feature bit.
4033	*
4034	* @returns boolean for feature presence
4035	* @param pVM The cross context VM structure.
4036	* @param enmFeature The feature to query.
4037	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4038	*/
4039	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4040	{
4041	switch (enmFeature)
4042	{
4043	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4044	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4045	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4046	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4047	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4048	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4049	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4050	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4051	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4052	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4053	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
4054	case CPUMCPUIDFEATURE_INVALID:
4055	case CPUMCPUIDFEATURE_32BIT_HACK:
4056	break;
4057	}
4058	AssertFailed();
4059	return false;
4060	}
4061
4062
4063	/**
4064	* Clears a CPUID feature bit.
4065	*
4066	* @param pVM The cross context VM structure.
4067	* @param enmFeature The feature to clear.
4068	*
4069	* @deprecated Probably better to default the feature to disabled and only allow
4070	* setting (enabling) it during construction.
4071	*/
4072	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4073	{
4074	PCPUMCPUIDLEAF pLeaf;
4075	switch (enmFeature)
4076	{
4077	case CPUMCPUIDFEATURE_APIC:
4078	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
4079	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4080	if (pLeaf)
4081	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
4082
4083	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4084	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4085	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4086
4087	pVM->cpum.s.GuestFeatures.fApic = 0;
4088	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4089	break;
4090
4091	case CPUMCPUIDFEATURE_X2APIC:
4092	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4093	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4094	if (pLeaf)
4095	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
4096	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
4097	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
4098	break;
4099
4100	#if 0
4101	case CPUMCPUIDFEATURE_PAE:
4102	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4103	if (pLeaf)
4104	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
4105
4106	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4107	if ( pLeaf
4108	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4109	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
4110	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
4111
4112	pVM->cpum.s.GuestFeatures.fPae = 0;
4113	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
4114	break;
4115
4116	case CPUMCPUIDFEATURE_LONG_MODE:
4117	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4118	if (pLeaf)
4119	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4120	pVM->cpum.s.GuestFeatures.fLongMode = 0;
4121	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
4122	if (pVM->cpum.s.GuestFeatures.fVmx)
4123	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4124	{
4125	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4126	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic \|= VMX_BASIC_PHYSADDR_WIDTH_32BIT;
4127	}
4128	break;
4129
4130	case CPUMCPUIDFEATURE_LAHF:
4131	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4132	if (pLeaf)
4133	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4134	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
4135	break;
4136	#endif
4137	case CPUMCPUIDFEATURE_RDTSCP:
4138	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4139	if (pLeaf)
4140	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4141	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
4142	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
4143	break;
4144
4145	#if 0
4146	case CPUMCPUIDFEATURE_HVP:
4147	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4148	if (pLeaf)
4149	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
4150	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
4151	break;
4152
4153	case CPUMCPUIDFEATURE_SPEC_CTRL:
4154	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4155	if (pLeaf)
4156	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
4157	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL);
4158	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
4159	break;
4160	#endif
4161	default:
4162	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4163	break;
4164	}
4165
4166	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4167	{
4168	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4169	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4170	}
4171	}
4172
4173
4174	/**
4175	* Do some final polishing after all calls to CPUMR3SetGuestCpuIdFeature and
4176	* CPUMR3ClearGuestCpuIdFeature are (probably) done.
4177	*
4178	* @param pVM The cross context VM structure.
4179	*/
4180	void cpumR3CpuIdRing3InitDone(PVM pVM)
4181	{
4182	/*
4183	* Do not advertise NX w/o PAE, seems to confuse windows 7 (black screen very
4184	* early in real mode).
4185	*/
4186	PCPUMCPUIDLEAF pStdLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4187	PCPUMCPUIDLEAF pExtLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4188	if (pStdLeaf && pExtLeaf)
4189	{
4190	if ( !(pStdLeaf->uEdx & X86_CPUID_FEATURE_EDX_PAE)
4191	&& (pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX))
4192	pExtLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_NX;
4193	}
4194	}
4195
4196
4197	/*
4198	*
4199	*
4200	* Saved state related code.
4201	* Saved state related code.
4202	* Saved state related code.
4203	*
4204	*
4205	*/
4206
4207	/**
4208	* Called both in pass 0 and the final pass.
4209	*
4210	* @param pVM The cross context VM structure.
4211	* @param pSSM The saved state handle.
4212	*/
4213	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4214	{
4215	/*
4216	* Save all the CPU ID leaves.
4217	*/
4218	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4219	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4220	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4221	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4222
4223	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4224
4225	/*
4226	* Save a good portion of the raw CPU IDs as well as they may come in
4227	* handy when validating features for raw mode.
4228	*/
4229	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4230	CPUMCPUID aRawStd[16];
4231	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4232	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4233	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4234	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4235
4236	CPUMCPUID aRawExt[32];
4237	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4238	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4239	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4240	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4241
4242	#else
4243	/* Two zero counts on non-x86 hosts. */
4244	SSMR3PutU32(pSSM, 0);
4245	SSMR3PutU32(pSSM, 0);
4246	#endif
4247	}
4248
4249
4250	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4251	{
4252	uint32_t cCpuIds;
4253	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4254	if (RT_SUCCESS(rc))
4255	{
4256	if (cCpuIds < 64)
4257	{
4258	for (uint32_t i = 0; i < cCpuIds; i++)
4259	{
4260	CPUMCPUID CpuId;
4261	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4262	if (RT_FAILURE(rc))
4263	break;
4264
4265	CPUMCPUIDLEAF NewLeaf;
4266	NewLeaf.uLeaf = uBase + i;
4267	NewLeaf.uSubLeaf = 0;
4268	NewLeaf.fSubLeafMask = 0;
4269	NewLeaf.uEax = CpuId.uEax;
4270	NewLeaf.uEbx = CpuId.uEbx;
4271	NewLeaf.uEcx = CpuId.uEcx;
4272	NewLeaf.uEdx = CpuId.uEdx;
4273	NewLeaf.fFlags = 0;
4274	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4275	}
4276	}
4277	else
4278	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4279	}
4280	if (RT_FAILURE(rc))
4281	{
4282	RTMemFree(*ppaLeaves);
4283	*ppaLeaves = NULL;
4284	*pcLeaves = 0;
4285	}
4286	return rc;
4287	}
4288
4289
4290	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4291	{
4292	*ppaLeaves = NULL;
4293	*pcLeaves = 0;
4294
4295	int rc;
4296	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4297	{
4298	/*
4299	* The new format. Starts by declaring the leave size and count.
4300	*/
4301	uint32_t cbLeaf;
4302	SSMR3GetU32(pSSM, &cbLeaf);
4303	uint32_t cLeaves;
4304	rc = SSMR3GetU32(pSSM, &cLeaves);
4305	if (RT_SUCCESS(rc))
4306	{
4307	if (cbLeaf == sizeof(**ppaLeaves))
4308	{
4309	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4310	{
4311	/*
4312	* Load the leaves one by one.
4313	*
4314	* The uPrev stuff is a kludge for working around a week worth of bad saved
4315	* states during the CPUID revamp in March 2015. We saved too many leaves
4316	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4317	* garbage entires at the end of the array when restoring. We also had
4318	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
4319	* this kludge doesn't deal correctly with that, but who cares...
4320	*/
4321	uint32_t uPrev = 0;
4322	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4323	{
4324	CPUMCPUIDLEAF Leaf;
4325	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
4326	if (RT_SUCCESS(rc))
4327	{
4328	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
4329	\|\| Leaf.uLeaf >= uPrev)
4330	{
4331	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4332	uPrev = Leaf.uLeaf;
4333	}
4334	else
4335	uPrev = UINT32_MAX;
4336	}
4337	}
4338	}
4339	else
4340	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
4341	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
4342	}
4343	else
4344	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
4345	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
4346	}
4347	}
4348	else
4349	{
4350	/*
4351	* The old format with its three inflexible arrays.
4352	*/
4353	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
4354	if (RT_SUCCESS(rc))
4355	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
4356	if (RT_SUCCESS(rc))
4357	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
4358	if (RT_SUCCESS(rc))
4359	{
4360	/*
4361	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
4362	*/
4363	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(ppaLeaves, pcLeaves, 0, 0);
4364	if ( pLeaf
4365	&& RTX86IsIntelCpu(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
4366	{
4367	CPUMCPUIDLEAF Leaf;
4368	Leaf.uLeaf = 4;
4369	Leaf.fSubLeafMask = UINT32_MAX;
4370	Leaf.uSubLeaf = 0;
4371	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
4372	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
4373	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
4374	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
4375	\| UINT32_C(63); /* system coherency line size - 1 */
4376	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
4377	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
4378	\| (UINT32_C(1) << 5) /* cache level */
4379	\| UINT32_C(1); /* cache type (data) */
4380	Leaf.fFlags = 0;
4381	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4382	if (RT_SUCCESS(rc))
4383	{
4384	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
4385	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4386	}
4387	if (RT_SUCCESS(rc))
4388	{
4389	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
4390	Leaf.uEcx = 4095; /* sets - 1 */
4391	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
4392	Leaf.uEbx \|= UINT32_C(23) << 22;
4393	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
4394	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
4395	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
4396	Leaf.uEax \|= UINT32_C(2) << 5;
4397	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4398	}
4399	}
4400	}
4401	}
4402	return rc;
4403	}
4404
4405
4406	/**
4407	* Loads the CPU ID leaves saved by pass 0, inner worker.
4408	*
4409	* @returns VBox status code.
4410	* @param pVM The cross context VM structure.
4411	* @param pSSM The saved state handle.
4412	* @param uVersion The format version.
4413	* @param paLeaves Guest CPUID leaves loaded from the state.
4414	* @param cLeaves The number of leaves in @a paLeaves.
4415	* @param pMsrs The guest MSRs.
4416	*/
4417	static int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
4418	{
4419	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4420	#if !defined(RT_ARCH_AMD64) && !defined(RT_ARCH_X86)
4421	AssertMsgFailed(("Port me!"));
4422	#endif
4423
4424	/*
4425	* Continue loading the state into stack buffers.
4426	*/
4427	CPUMCPUID GuestDefCpuId;
4428	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
4429	AssertRCReturn(rc, rc);
4430
4431	CPUMCPUID aRawStd[16];
4432	uint32_t cRawStd;
4433	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
4434	if (cRawStd > RT_ELEMENTS(aRawStd))
4435	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4436	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
4437	AssertRCReturn(rc, rc);
4438	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
4439	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4440	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4441	#else
4442	RT_ZERO(aRawStd[i]);
4443	#endif
4444
4445	CPUMCPUID aRawExt[32];
4446	uint32_t cRawExt;
4447	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
4448	if (cRawExt > RT_ELEMENTS(aRawExt))
4449	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4450	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
4451	AssertRCReturn(rc, rc);
4452	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
4453	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4454	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4455	#else
4456	RT_ZERO(aRawExt[i]);
4457	#endif
4458
4459	/*
4460	* Get the raw CPU IDs for the current host.
4461	*/
4462	CPUMCPUID aHostRawStd[16];
4463	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4464	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
4465	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
4466	#else
4467	RT_ZERO(aHostRawStd);
4468	#endif
4469
4470	CPUMCPUID aHostRawExt[32];
4471	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4472	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
4473	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
4474	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4475	#else
4476	RT_ZERO(aHostRawExt);
4477	#endif
4478
4479	/*
4480	* Get the host and guest overrides so we don't reject the state because
4481	* some feature was enabled thru these interfaces.
4482	* Note! We currently only need the feature leaves, so skip rest.
4483	*/
4484	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4485	CPUMCPUID aHostOverrideStd[2];
4486	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4487	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4488
4489	CPUMCPUID aHostOverrideExt[2];
4490	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4491	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4492
4493	/*
4494	* This can be skipped.
4495	*
4496	* @note On ARM we disable the strict checks for now because we can't verify with what the host supports
4497	* and just assume the interpreter/recompiler supports everything what was exposed earlier.
4498	*/
4499	bool fStrictCpuIdChecks;
4500	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks,
4501	#ifdef RT_ARCH_ARM64
4502	false
4503	#else
4504	true
4505	#endif
4506	);
4507
4508	/*
4509	* Define a bunch of macros for simplifying the santizing/checking code below.
4510	*/
4511	/* Generic expression + failure message. */
4512	#define CPUID_CHECK_RET(expr, fmt) \
4513	do { \
4514	if (!(expr)) \
4515	{ \
4516	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
4517	if (fStrictCpuIdChecks) \
4518	{ \
4519	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4520	RTStrFree(pszMsg); \
4521	return rcCpuid; \
4522	} \
4523	LogRel(("CPUM: %s\n", pszMsg)); \
4524	RTStrFree(pszMsg); \
4525	} \
4526	} while (0)
4527	#define CPUID_CHECK_WRN(expr, fmt) \
4528	do { \
4529	if (!(expr)) \
4530	LogRel(fmt); \
4531	} while (0)
4532
4533	/* For comparing two values and bitch if they differs. */
4534	#define CPUID_CHECK2_RET(what, host, saved) \
4535	do { \
4536	if ((host) != (saved)) \
4537	{ \
4538	if (fStrictCpuIdChecks) \
4539	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4540	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
4541	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4542	} \
4543	} while (0)
4544	#define CPUID_CHECK2_WRN(what, host, saved) \
4545	do { \
4546	if ((host) != (saved)) \
4547	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4548	} while (0)
4549
4550	/* For checking raw cpu features (raw mode). */
4551	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
4552	do { \
4553	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4554	{ \
4555	if (fStrictCpuIdChecks) \
4556	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4557	N_(#bit " mismatch: host=%d saved=%d"), \
4558	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
4559	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4560	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4561	} \
4562	} while (0)
4563	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
4564	do { \
4565	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4566	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4567	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4568	} while (0)
4569	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
4570
4571	/* For checking guest features. */
4572	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
4573	do { \
4574	if ( (aGuestCpuId##set [1].reg & bit) \
4575	&& !(aHostRaw##set [1].reg & bit) \
4576	&& !(aHostOverride##set [1].reg & bit) \
4577	) \
4578	{ \
4579	if (fStrictCpuIdChecks) \
4580	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4581	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4582	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4583	} \
4584	} while (0)
4585	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
4586	do { \
4587	if ( (aGuestCpuId##set [1].reg & bit) \
4588	&& !(aHostRaw##set [1].reg & bit) \
4589	&& !(aHostOverride##set [1].reg & bit) \
4590	) \
4591	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4592	} while (0)
4593	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
4594	do { \
4595	if ( (aGuestCpuId##set [1].reg & bit) \
4596	&& !(aHostRaw##set [1].reg & bit) \
4597	&& !(aHostOverride##set [1].reg & bit) \
4598	) \
4599	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4600	} while (0)
4601	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
4602
4603	/* For checking guest features if AMD guest CPU. */
4604	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
4605	do { \
4606	if ( (aGuestCpuId##set [1].reg & bit) \
4607	&& fGuestAmd \
4608	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4609	&& !(aHostOverride##set [1].reg & bit) \
4610	) \
4611	{ \
4612	if (fStrictCpuIdChecks) \
4613	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4614	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4615	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4616	} \
4617	} while (0)
4618	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
4619	do { \
4620	if ( (aGuestCpuId##set [1].reg & bit) \
4621	&& fGuestAmd \
4622	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4623	&& !(aHostOverride##set [1].reg & bit) \
4624	) \
4625	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4626	} while (0)
4627	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
4628	do { \
4629	if ( (aGuestCpuId##set [1].reg & bit) \
4630	&& fGuestAmd \
4631	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4632	&& !(aHostOverride##set [1].reg & bit) \
4633	) \
4634	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4635	} while (0)
4636	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
4637
4638	/* For checking AMD features which have a corresponding bit in the standard
4639	range. (Intel defines very few bits in the extended feature sets.) */
4640	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
4641	do { \
4642	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4643	&& !(fHostAmd \
4644	? aHostRawExt[1].reg & (ExtBit) \
4645	: aHostRawStd[1].reg & (StdBit)) \
4646	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4647	) \
4648	{ \
4649	if (fStrictCpuIdChecks) \
4650	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4651	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
4652	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4653	} \
4654	} while (0)
4655	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
4656	do { \
4657	if ( (aGuestCpuId[1].reg & (ExtBit)) \
4658	&& !(fHostAmd \
4659	? aHostRawExt[1].reg & (ExtBit) \
4660	: aHostRawStd[1].reg & (StdBit)) \
4661	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4662	) \
4663	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4664	} while (0)
4665	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
4666	do { \
4667	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4668	&& !(fHostAmd \
4669	? aHostRawExt[1].reg & (ExtBit) \
4670	: aHostRawStd[1].reg & (StdBit)) \
4671	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4672	) \
4673	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4674	} while (0)
4675	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
4676
4677
4678	/*
4679	* Verify that we can support the features already exposed to the guest on
4680	* this host.
4681	*
4682	* Most of the features we're emulating requires intercepting instruction
4683	* and doing it the slow way, so there is no need to warn when they aren't
4684	* present in the host CPU. Thus we use IGN instead of EMU on these.
4685	*
4686	* Trailing comments:
4687	* "EMU" - Possible to emulate, could be lots of work and very slow.
4688	* "EMU?" - Can this be emulated?
4689	*/
4690	CPUMCPUID aGuestCpuIdStd[2];
4691	RT_ZERO(aGuestCpuIdStd);
4692	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
4693
4694	/* CPUID(1).ecx */
4695	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
4696	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
4697	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
4698	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4699	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
4700	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
4701	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
4702	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
4703	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
4704	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
4705	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
4706	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
4707	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
4708	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
4709	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
4710	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
4711	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
4712	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4713	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
4714	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
4715	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
4716	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4717	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
4718	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
4719	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4720	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
4721	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
4722	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4723	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
4724	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4725	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4726	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
4727
4728	/* CPUID(1).edx */
4729	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4730	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4731	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
4732	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4733	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4734	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4735	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4736	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4737	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4738	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4739	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
4740	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4741	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4742	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4743	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4744	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4745	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4746	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4747	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4748	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
4749	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
4750	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
4751	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
4752	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4753	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4754	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
4755	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
4756	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
4757	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
4758	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
4759	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
4760	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
4761
4762	/* CPUID(0x80000000). */
4763	CPUMCPUID aGuestCpuIdExt[2];
4764	RT_ZERO(aGuestCpuIdExt);
4765	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
4766	{
4767	/** @todo deal with no 0x80000001 on the host. */
4768	bool const fHostAmd = RTX86IsAmdCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx)
4769	\|\| RTX86IsHygonCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
4770	bool const fGuestAmd = RTX86IsAmdCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx)
4771	\|\| RTX86IsHygonCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
4772
4773	/* CPUID(0x80000001).ecx */
4774	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
4775	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
4776	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
4777	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
4778	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
4779	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
4780	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
4781	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
4782	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
4783	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
4784	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
4785	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
4786	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
4787	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
4788	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4789	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4790	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4791	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4792	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4793	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4794	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4795	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4796	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4797	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4798	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4799	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4800	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4801	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4802	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4803	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4804	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4805	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4806
4807	/* CPUID(0x80000001).edx */
4808	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
4809	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
4810	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
4811	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
4812	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4813	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4814	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
4815	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
4816	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4817	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
4818	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4819	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
4820	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
4821	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
4822	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
4823	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4824	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
4825	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
4826	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4827	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4828	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4829	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
4830	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4831	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4832	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4833	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4834	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4835	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4836	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
4837	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4838	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4839	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4840	}
4841
4842	/** @todo check leaf 7 */
4843
4844	/* CPUID(d) - XCR0 stuff - takes ECX as input.
4845	* ECX=0: EAX - Valid bits in XCR0[31:0].
4846	* EBX - Maximum state size as per current XCR0 value.
4847	* ECX - Maximum state size for all supported features.
4848	* EDX - Valid bits in XCR0[63:32].
4849	* ECX=1: EAX - Various X-features.
4850	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
4851	* ECX - Valid bits in IA32_XSS[31:0].
4852	* EDX - Valid bits in IA32_XSS[63:32].
4853	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
4854	* if the bit invalid all four registers are set to zero.
4855	* EAX - The state size for this feature.
4856	* EBX - The state byte offset of this feature.
4857	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
4858	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
4859	*/
4860	uint64_t fGuestXcr0Mask = 0;
4861	PCPUMCPUIDLEAF pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
4862	if ( pCurLeaf
4863	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
4864	&& ( pCurLeaf->uEax
4865	\|\| pCurLeaf->uEbx
4866	\|\| pCurLeaf->uEcx
4867	\|\| pCurLeaf->uEdx) )
4868	{
4869	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
4870	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
4871	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4872	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
4873	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
4874	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
4875	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4876	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
4877
4878	/* We don't support any additional features yet. */
4879	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
4880	if (pCurLeaf && pCurLeaf->uEax)
4881	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4882	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
4883	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
4884	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4885	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
4886	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
4887
4888
4889	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4890	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
4891	{
4892	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4893	if (pCurLeaf)
4894	{
4895	/* If advertised, the state component offset and size must match the one used by host. */
4896	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
4897	{
4898	CPUMCPUID RawHost;
4899	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
4900	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
4901	if ( RawHost.uEbx != pCurLeaf->uEbx
4902	\|\| RawHost.uEax != pCurLeaf->uEax)
4903	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4904	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
4905	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
4906	}
4907	}
4908	}
4909	#endif
4910	}
4911	/* Clear leaf 0xd just in case we're loading an old state... */
4912	else if (pCurLeaf)
4913	{
4914	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
4915	{
4916	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4917	if (pCurLeaf)
4918	{
4919	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
4920	\|\| ( pCurLeaf->uEax == 0
4921	&& pCurLeaf->uEbx == 0
4922	&& pCurLeaf->uEcx == 0
4923	&& pCurLeaf->uEdx == 0),
4924	("uVersion=%#x; %#x %#x %#x %#x\n",
4925	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
4926	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
4927	}
4928	}
4929	}
4930
4931	/* Update the fXStateGuestMask value for the VM. */
4932	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
4933	{
4934	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
4935	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
4936	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
4937	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4938	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
4939	}
4940
4941	#undef CPUID_CHECK_RET
4942	#undef CPUID_CHECK_WRN
4943	#undef CPUID_CHECK2_RET
4944	#undef CPUID_CHECK2_WRN
4945	#undef CPUID_RAW_FEATURE_RET
4946	#undef CPUID_RAW_FEATURE_WRN
4947	#undef CPUID_RAW_FEATURE_IGN
4948	#undef CPUID_GST_FEATURE_RET
4949	#undef CPUID_GST_FEATURE_WRN
4950	#undef CPUID_GST_FEATURE_EMU
4951	#undef CPUID_GST_FEATURE_IGN
4952	#undef CPUID_GST_FEATURE2_RET
4953	#undef CPUID_GST_FEATURE2_WRN
4954	#undef CPUID_GST_FEATURE2_EMU
4955	#undef CPUID_GST_FEATURE2_IGN
4956	#undef CPUID_GST_AMD_FEATURE_RET
4957	#undef CPUID_GST_AMD_FEATURE_WRN
4958	#undef CPUID_GST_AMD_FEATURE_EMU
4959	#undef CPUID_GST_AMD_FEATURE_IGN
4960
4961	/*
4962	* We're good, commit the CPU ID leaves.
4963	*/
4964	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
4965	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
4966	AssertLogRelRCReturn(rc, rc);
4967
4968	return VINF_SUCCESS;
4969	}
4970
4971
4972	/**
4973	* Loads the CPU ID leaves saved by pass 0, x86 targets.
4974	*
4975	* @returns VBox status code.
4976	* @param pVM The cross context VM structure.
4977	* @param pSSM The saved state handle.
4978	* @param uVersion The format version.
4979	* @param pMsrs The guest MSRs.
4980	*/
4981	int cpumR3LoadCpuIdX86(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
4982	{
4983	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4984
4985	/*
4986	* Load the CPUID leaves array first and call worker to do the rest, just so
4987	* we can free the memory when we need to without ending up in column 1000.
4988	*/
4989	PCPUMCPUIDLEAF paLeaves;
4990	uint32_t cLeaves;
4991	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
4992	AssertRC(rc);
4993	if (RT_SUCCESS(rc))
4994	{
4995	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
4996	RTMemFree(paLeaves);
4997	}
4998	return rc;
4999	}
5000
5001
5002
5003	/**
5004	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5005	*
5006	* @returns VBox status code.
5007	* @param pVM The cross context VM structure.
5008	* @param pSSM The saved state handle.
5009	* @param uVersion The format version.
5010	*/
5011	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5012	{
5013	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5014
5015	/*
5016	* Restore the CPUID leaves.
5017	*
5018	* Note that we support restoring less than the current amount of standard
5019	* leaves because we've been allowed more is newer version of VBox.
5020	*/
5021	uint32_t cElements;
5022	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5023	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5024	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5025	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5026
5027	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5028	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5029	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5030	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5031
5032	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5033	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5034	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5035	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5036
5037	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5038
5039	/*
5040	* Check that the basic cpuid id information is unchanged.
5041	*/
5042	/** @todo we should check the 64 bits capabilities too! */
5043	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5044	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5045	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5046	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5047	#endif
5048	uint32_t au32CpuIdSaved[8];
5049	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5050	if (RT_SUCCESS(rc))
5051	{
5052	/* Ignore CPU stepping. */
5053	au32CpuId[4] &= 0xfffffff0;
5054	au32CpuIdSaved[4] &= 0xfffffff0;
5055
5056	/* Ignore APIC ID (AMD specs). */
5057	au32CpuId[5] &= ~0xff000000;
5058	au32CpuIdSaved[5] &= ~0xff000000;
5059
5060	/* Ignore the number of Logical CPUs (AMD specs). */
5061	au32CpuId[5] &= ~0x00ff0000;
5062	au32CpuIdSaved[5] &= ~0x00ff0000;
5063
5064	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5065	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5066	\| X86_CPUID_FEATURE_ECX_VMX
5067	\| X86_CPUID_FEATURE_ECX_SMX
5068	\| X86_CPUID_FEATURE_ECX_EST
5069	\| X86_CPUID_FEATURE_ECX_TM2
5070	\| X86_CPUID_FEATURE_ECX_CNTXID
5071	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5072	\| X86_CPUID_FEATURE_ECX_PDCM
5073	\| X86_CPUID_FEATURE_ECX_DCA
5074	\| X86_CPUID_FEATURE_ECX_X2APIC
5075	);
5076	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5077	\| X86_CPUID_FEATURE_ECX_VMX
5078	\| X86_CPUID_FEATURE_ECX_SMX
5079	\| X86_CPUID_FEATURE_ECX_EST
5080	\| X86_CPUID_FEATURE_ECX_TM2
5081	\| X86_CPUID_FEATURE_ECX_CNTXID
5082	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5083	\| X86_CPUID_FEATURE_ECX_PDCM
5084	\| X86_CPUID_FEATURE_ECX_DCA
5085	\| X86_CPUID_FEATURE_ECX_X2APIC
5086	);
5087
5088	/* Make sure we don't forget to update the masks when enabling
5089	* features in the future.
5090	*/
5091	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5092	( X86_CPUID_FEATURE_ECX_DTES64
5093	\| X86_CPUID_FEATURE_ECX_VMX
5094	\| X86_CPUID_FEATURE_ECX_SMX
5095	\| X86_CPUID_FEATURE_ECX_EST
5096	\| X86_CPUID_FEATURE_ECX_TM2
5097	\| X86_CPUID_FEATURE_ECX_CNTXID
5098	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5099	\| X86_CPUID_FEATURE_ECX_PDCM
5100	\| X86_CPUID_FEATURE_ECX_DCA
5101	\| X86_CPUID_FEATURE_ECX_X2APIC
5102	)));
5103	/* do the compare */
5104	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5105	{
5106	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5107	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5108	"Saved=%.*Rhxs\n"
5109	"Real =%.*Rhxs\n",
5110	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5111	sizeof(au32CpuId), au32CpuId));
5112	else
5113	{
5114	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5115	"Saved=%.*Rhxs\n"
5116	"Real =%.*Rhxs\n",
5117	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5118	sizeof(au32CpuId), au32CpuId));
5119	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5120	}
5121	}
5122	}
5123
5124	return rc;
5125	}
5126
5127
5128
5129	/*
5130	*
5131	*
5132	* CPUID Info Handler.
5133	* CPUID Info Handler.
5134	* CPUID Info Handler.
5135	*
5136	*
5137	*/
5138
5139
5140
5141	/**
5142	* Get L1 cache / TLS associativity.
5143	*/
5144	static const char getCacheAss(unsigned u, char pszBuf)
5145	{
5146	if (u == 0)
5147	return "res0 ";
5148	if (u == 1)
5149	return "direct";
5150	if (u == 255)
5151	return "fully";
5152	if (u >= 256)
5153	return "???";
5154
5155	RTStrPrintf(pszBuf, 16, "%d way", u);
5156	return pszBuf;
5157	}
5158
5159
5160	/**
5161	* Get L2/L3 cache associativity.
5162	*/
5163	static const char *getL23CacheAss(unsigned u)
5164	{
5165	switch (u)
5166	{
5167	case 0: return "off ";
5168	case 1: return "direct";
5169	case 2: return "2 way ";
5170	case 3: return "3 way ";
5171	case 4: return "4 way ";
5172	case 5: return "6 way ";
5173	case 6: return "8 way ";
5174	case 7: return "res7 ";
5175	case 8: return "16 way";
5176	case 9: return "tpoext"; /* Overridden by Fn8000_001D */
5177	case 10: return "32 way";
5178	case 11: return "48 way";
5179	case 12: return "64 way";
5180	case 13: return "96 way";
5181	case 14: return "128way";
5182	case 15: return "fully ";
5183	default: return "????";
5184	}
5185	}
5186
5187
5188	/** CPUID(1).EDX field descriptions. */
5189	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
5190	{
5191	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5192	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5193	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5194	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5195	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5196	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
5197	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5198	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5199	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5200	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5201	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
5202	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5203	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5204	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5205	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5206	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5207	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5208	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
5209	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
5210	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
5211	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
5212	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5213	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
5214	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
5215	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
5216	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
5217	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
5218	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
5219	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
5220	DBGFREGSUBFIELD_TERMINATOR()
5221	};
5222
5223	/** CPUID(1).ECX field descriptions. */
5224	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
5225	{
5226	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
5227	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
5228	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
5229	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
5230	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
5231	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
5232	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
5233	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
5234	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
5235	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
5236	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
5237	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
5238	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
5239	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
5240	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
5241	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
5242	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
5243	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
5244	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
5245	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
5246	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
5247	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
5248	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
5249	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
5250	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
5251	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
5252	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
5253	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
5254	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
5255	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
5256	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
5257	DBGFREGSUBFIELD_TERMINATOR()
5258	};
5259
5260	/** CPUID(7,0).EBX field descriptions. */
5261	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
5262	{
5263	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
5264	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
5265	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
5266	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
5267	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
5268	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
5269	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
5270	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
5271	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
5272	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
5273	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
5274	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
5275	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
5276	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
5277	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
5278	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
5279	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
5280	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
5281	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
5282	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
5283	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
5284	DBGFREGSUBFIELD_RO("CLWB\0" "CLWB instruction", 24, 1, 0),
5285	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
5286	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
5287	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
5288	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
5289	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
5290	DBGFREGSUBFIELD_TERMINATOR()
5291	};
5292
5293	/** CPUID(7,0).ECX field descriptions. */
5294	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
5295	{
5296	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
5297	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
5298	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
5299	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
5300	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
5301	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
5302	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
5303	DBGFREGSUBFIELD_TERMINATOR()
5304	};
5305
5306	/** CPUID(7,0).EDX field descriptions. */
5307	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
5308	{
5309	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
5310	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
5311	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
5312	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
5313	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
5314	DBGFREGSUBFIELD_RO("CORECAP\0" "Supports IA32_CORE_CAP", 30, 1, 0),
5315	DBGFREGSUBFIELD_RO("SSBD\0" "Supports IA32_SPEC_CTRL.SSBD", 31, 1, 0),
5316	DBGFREGSUBFIELD_TERMINATOR()
5317	};
5318
5319
5320	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
5321	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
5322	{
5323	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
5324	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
5325	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
5326	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
5327	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
5328	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
5329	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
5330	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
5331	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
5332	DBGFREGSUBFIELD_TERMINATOR()
5333	};
5334
5335	/** CPUID(13,1).EAX field descriptions. */
5336	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
5337	{
5338	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
5339	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
5340	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
5341	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
5342	DBGFREGSUBFIELD_TERMINATOR()
5343	};
5344
5345
5346	/** CPUID(0x80000001,0).EDX field descriptions. */
5347	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
5348	{
5349	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5350	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5351	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5352	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5353	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5354	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
5355	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5356	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5357	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5358	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5359	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
5360	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5361	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5362	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5363	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5364	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5365	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5366	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
5367	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
5368	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5369	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
5370	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
5371	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
5372	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
5373	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
5374	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
5375	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
5376	DBGFREGSUBFIELD_TERMINATOR()
5377	};
5378
5379	/** CPUID(0x80000001,0).ECX field descriptions. */
5380	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
5381	{
5382	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
5383	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
5384	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
5385	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
5386	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
5387	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
5388	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
5389	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
5390	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
5391	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
5392	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
5393	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
5394	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
5395	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
5396	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
5397	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
5398	DBGFREGSUBFIELD_RO("TCE\0" "Translation Cache Extension support", 17, 1, 0),
5399	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
5400	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
5401	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
5402	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
5403	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
5404	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
5405	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
5406	DBGFREGSUBFIELD_RO("PCX_L2I\0" "L2I/L3 Performance Counter Extensions", 28, 1, 0),
5407	DBGFREGSUBFIELD_RO("MONITORX\0" "MWAITX and MONITORX instructions", 29, 1, 0),
5408	DBGFREGSUBFIELD_RO("AddrMaskExt\0" "BP Addressing masking extended to bit 31", 30, 1, 0),
5409	DBGFREGSUBFIELD_TERMINATOR()
5410	};
5411
5412	/** CPUID(0x8000000a,0).EDX field descriptions. */
5413	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
5414	{
5415	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
5416	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
5417	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
5418	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
5419	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
5420	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
5421	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
5422	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
5423	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
5424	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
5425	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
5426	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
5427	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
5428	DBGFREGSUBFIELD_RO("GMET\0" "Guest Mode Execute Trap Extension", 17, 1, 0),
5429	DBGFREGSUBFIELD_RO("x2AVIC\0" "AVIC support for x2APIC mode", 18, 1, 0),
5430	DBGFREGSUBFIELD_RO("SSSCheck\0" "SVM supervisor shadow stack restrictions", 19, 1, 0),
5431	DBGFREGSUBFIELD_RO("SpecCtrl\0" "SPEC_CTRL virtualization", 20, 1, 0),
5432	DBGFREGSUBFIELD_RO("ROGPT\0" "Read-Only Guest Page Table feature support", 21, 1, 0),
5433	DBGFREGSUBFIELD_RO("HOST_MCE_OVERRIDE\0" "Guest #MC can be intercepted", 23, 1, 0),
5434	DBGFREGSUBFIELD_RO("TlbiCtl\0" "INVLPGB/TLBSYNC enable and intercept", 24, 1, 0),
5435	DBGFREGSUBFIELD_RO("VNMI\0" "NMI Virtualization", 25, 1, 0),
5436	DBGFREGSUBFIELD_RO("IbsVirt\0" "IBS Virtualization", 26, 1, 0),
5437	DBGFREGSUBFIELD_RO("ExtLvtAvicAccessChg\0" "Extended LVT AVIC access changes", 27, 1, 0),
5438	DBGFREGSUBFIELD_RO("NestedVirtVmcbAddrChk\0""Guest VMCB address check", 28, 1, 0),
5439	DBGFREGSUBFIELD_RO("BusLockThreshold\0" "Bus Lock Threshold", 29, 1, 0),
5440	DBGFREGSUBFIELD_TERMINATOR()
5441	};
5442
5443
5444	/** CPUID(0x80000007,0).EDX field descriptions. */
5445	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
5446	{
5447	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
5448	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
5449	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
5450	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
5451	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
5452	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
5453	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
5454	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
5455	DBGFREGSUBFIELD_RO("CPB\0" "Core Performance Boost", 9, 1, 0),
5456	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
5457	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
5458	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
5459	DBGFREGSUBFIELD_RO("ConnectedStandby\0" "Connected Standby", 13, 1, 0),
5460	DBGFREGSUBFIELD_RO("RAPL\0" "Running average power limit", 14, 1, 0),
5461	DBGFREGSUBFIELD_TERMINATOR()
5462	};
5463
5464	/** CPUID(0x80000008,0).EBX field descriptions. */
5465	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
5466	{
5467	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
5468	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
5469	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR)", 2, 1, 0),
5470	DBGFREGSUBFIELD_RO("INVLPGB\0" "INVLPGB and TLBSYNC instructions", 3, 1, 0),
5471	DBGFREGSUBFIELD_RO("RDPRU\0" "RDPRU instruction", 4, 1, 0),
5472	DBGFREGSUBFIELD_RO("BE\0" "Bandwidth Enforcement extension", 6, 1, 0),
5473	DBGFREGSUBFIELD_RO("MCOMMIT\0" "MCOMMIT instruction", 8, 1, 0),
5474	DBGFREGSUBFIELD_RO("WBNOINVD\0" "WBNOINVD instruction", 9, 1, 0),
5475	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
5476	DBGFREGSUBFIELD_RO("INT_WBINVD\0" "WBINVD/WBNOINVD interruptible", 13, 1, 0),
5477	DBGFREGSUBFIELD_RO("IBRS\0" "Indirect Branch Restricted Speculation", 14, 1, 0),
5478	DBGFREGSUBFIELD_RO("STIBP\0" "Single Thread Indirect Branch Prediction", 15, 1, 0),
5479	DBGFREGSUBFIELD_RO("IbrsAlwaysOn\0" "Processor prefers that IBRS be left on", 16, 1, 0),
5480	DBGFREGSUBFIELD_RO("StibpAlwaysOn\0""Processor prefers that STIBP be left on", 17, 1, 0),
5481	DBGFREGSUBFIELD_RO("IbrsPreferred\0""IBRS preferred over software solution", 18, 1, 0),
5482	DBGFREGSUBFIELD_RO("IbrsSameMode\0" "IBRS limits same mode speculation", 19, 1, 0),
5483	DBGFREGSUBFIELD_RO("EferLmsleUnsupported\0" "EFER.LMSLE is unsupported", 20, 1, 0),
5484	DBGFREGSUBFIELD_RO("INVLPGBnestedPages\0" "INVLPGB for nested translation", 21, 1, 0),
5485	DBGFREGSUBFIELD_RO("SSBD\0" "Speculative Store Bypass Disable", 24, 1, 0),
5486	DBGFREGSUBFIELD_RO("SsbdVirtSpecCtrl\0" "Use VIRT_SPEC_CTL for SSBD", 25, 1, 0),
5487	DBGFREGSUBFIELD_RO("SsbdNotRequired\0" "SSBD not needed on this processor", 26, 1, 0),
5488	DBGFREGSUBFIELD_RO("CPPC\0" "Collaborative Processor Performance Control", 27, 1, 0),
5489	DBGFREGSUBFIELD_RO("PSFD\0" "Predictive Store Forward Disable", 28, 1, 0),
5490	DBGFREGSUBFIELD_RO("BTC_NO\0" "Unaffected by branch type confusion", 29, 1, 0),
5491	DBGFREGSUBFIELD_RO("IBPB_RET\0" "Clears RA predictor when PRED_CMD.IBPB set", 30, 1, 0),
5492	DBGFREGSUBFIELD_TERMINATOR()
5493	};
5494
5495
5496	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
5497	const char *pszLeadIn, uint32_t cchWidth)
5498	{
5499	if (pszLeadIn)
5500	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5501
5502	for (uint32_t iBit = 0; iBit < 32; iBit++)
5503	if (RT_BIT_32(iBit) & uVal)
5504	{
5505	while ( pDesc->pszName != NULL
5506	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5507	pDesc++;
5508	if ( pDesc->pszName != NULL
5509	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5510	{
5511	if (pDesc->cBits == 1)
5512	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5513	else
5514	{
5515	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
5516	if (pDesc->cBits < 32)
5517	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5518	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
5519	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5520	}
5521	}
5522	else
5523	pHlp->pfnPrintf(pHlp, " %u", iBit);
5524	}
5525	if (pszLeadIn)
5526	pHlp->pfnPrintf(pHlp, "\n");
5527	}
5528
5529
5530	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5531	const char *pszLeadIn, uint32_t cchWidth)
5532	{
5533	if (pszLeadIn)
5534	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5535
5536	for (uint32_t iBit = 0; iBit < 64; iBit++)
5537	if (RT_BIT_64(iBit) & uVal)
5538	{
5539	while ( pDesc->pszName != NULL
5540	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5541	pDesc++;
5542	if ( pDesc->pszName != NULL
5543	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5544	{
5545	if (pDesc->cBits == 1)
5546	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5547	else
5548	{
5549	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
5550	if (pDesc->cBits < 64)
5551	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
5552	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
5553	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5554	}
5555	}
5556	else
5557	pHlp->pfnPrintf(pHlp, " %u", iBit);
5558	}
5559	if (pszLeadIn)
5560	pHlp->pfnPrintf(pHlp, "\n");
5561	}
5562
5563
5564	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5565	const char *pszLeadIn, uint32_t cchWidth)
5566	{
5567	if (!uVal)
5568	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5569	else
5570	{
5571	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5572	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
5573	pHlp->pfnPrintf(pHlp, " )\n");
5574	}
5575	}
5576
5577
5578	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
5579	uint32_t cchWidth)
5580	{
5581	uint32_t uCombined = uVal1 \| uVal2;
5582	for (uint32_t iBit = 0; iBit < 32; iBit++)
5583	if ( (RT_BIT_32(iBit) & uCombined)
5584	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
5585	{
5586	while ( pDesc->pszName != NULL
5587	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5588	pDesc++;
5589
5590	if ( pDesc->pszName != NULL
5591	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5592	{
5593	size_t cchMnemonic = strlen(pDesc->pszName);
5594	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
5595	size_t cchDesc = strlen(pszDesc);
5596	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
5597	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
5598	if (pDesc->cBits < 32)
5599	{
5600	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5601	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5602	}
5603
5604	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
5605	pDesc->pszName, pszDesc,
5606	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
5607	uFieldValue1, uFieldValue2);
5608
5609	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
5610	pDesc++;
5611	}
5612	else
5613	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
5614	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
5615	}
5616	}
5617
5618
5619	/**
5620	* Produces a detailed summary of standard leaf 0x00000001.
5621	*
5622	* @param pHlp The info helper functions.
5623	* @param pCurLeaf The 0x00000001 leaf.
5624	* @param fVerbose Whether to be very verbose or not.
5625	* @param fIntel Set if intel CPU.
5626	*/
5627	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
5628	{
5629	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
5630	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
5631	uint32_t uEAX = pCurLeaf->uEax;
5632	uint32_t uEBX = pCurLeaf->uEbx;
5633
5634	pHlp->pfnPrintf(pHlp,
5635	"%36s %2d \tExtended: %d \tEffective: %d\n"
5636	"%36s %2d \tExtended: %d \tEffective: %d\n"
5637	"%36s %d\n"
5638	"%36s %d (%s)\n"
5639	"%36s %#04x\n"
5640	"%36s %d\n"
5641	"%36s %d\n"
5642	"%36s %#04x\n"
5643	,
5644	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
5645	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
5646	"Stepping:", RTX86GetCpuStepping(uEAX),
5647	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
5648	"APIC ID:", (uEBX >> 24) & 0xff,
5649	"Logical CPUs:",(uEBX >> 16) & 0xff,
5650	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
5651	"Brand ID:", (uEBX >> 0) & 0xff);
5652	if (fVerbose)
5653	{
5654	CPUMCPUID Host = {0};
5655	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5656	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5657	#endif
5658	pHlp->pfnPrintf(pHlp, "Features\n");
5659	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5660	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
5661	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
5662	}
5663	else
5664	{
5665	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
5666	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
5667	}
5668	}
5669
5670
5671	/**
5672	* Produces a detailed summary of standard leaf 0x00000007.
5673	*
5674	* @param pHlp The info helper functions.
5675	* @param paLeaves The CPUID leaves array.
5676	* @param cLeaves The number of leaves in the array.
5677	* @param pCurLeaf The first 0x00000007 leaf.
5678	* @param fVerbose Whether to be very verbose or not.
5679	*/
5680	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5681	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5682	{
5683	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
5684	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
5685	for (;;)
5686	{
5687	CPUMCPUID Host = {0};
5688	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5689	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5690	#endif
5691
5692	switch (pCurLeaf->uSubLeaf)
5693	{
5694	case 0:
5695	if (fVerbose)
5696	{
5697	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5698	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
5699	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
5700	if (pCurLeaf->uEdx \|\| Host.uEdx)
5701	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
5702	}
5703	else
5704	{
5705	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
5706	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
5707	if (pCurLeaf->uEdx)
5708	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
5709	}
5710	break;
5711
5712	default:
5713	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
5714	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
5715	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
5716	break;
5717
5718	}
5719
5720	/* advance. */
5721	pCurLeaf++;
5722	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5723	\|\| pCurLeaf->uLeaf != 0x7)
5724	break;
5725	}
5726	}
5727
5728
5729	/**
5730	* Produces a detailed summary of standard leaf 0x0000000d.
5731	*
5732	* @param pHlp The info helper functions.
5733	* @param paLeaves The CPUID leaves array.
5734	* @param cLeaves The number of leaves in the array.
5735	* @param pCurLeaf The first 0x00000007 leaf.
5736	* @param fVerbose Whether to be very verbose or not.
5737	*/
5738	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5739	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5740	{
5741	RT_NOREF_PV(fVerbose);
5742	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
5743	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
5744	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5745	{
5746	CPUMCPUID Host = {0};
5747	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5748	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5749	#endif
5750
5751	switch (uSubLeaf)
5752	{
5753	case 0:
5754	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5755	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
5756	pCurLeaf->uEbx, pCurLeaf->uEcx);
5757	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
5758
5759	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5760	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
5761	"Valid XCR0 bits, guest:", 42);
5762	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
5763	"Valid XCR0 bits, host:", 42);
5764	break;
5765
5766	case 1:
5767	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5768	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
5769	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
5770
5771	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5772	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
5773	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
5774
5775	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5776	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
5777	" Valid IA32_XSS bits, guest:", 42);
5778	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
5779	" Valid IA32_XSS bits, host:", 42);
5780	break;
5781
5782	default:
5783	if ( pCurLeaf
5784	&& pCurLeaf->uSubLeaf == uSubLeaf
5785	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
5786	{
5787	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
5788	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5789	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
5790	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
5791	if (pCurLeaf->uEdx)
5792	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
5793	pHlp->pfnPrintf(pHlp, " --");
5794	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5795	pHlp->pfnPrintf(pHlp, "\n");
5796	}
5797	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
5798	{
5799	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
5800	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5801	if (Host.uEcx & ~RT_BIT_32(0))
5802	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
5803	if (Host.uEdx)
5804	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
5805	pHlp->pfnPrintf(pHlp, " --");
5806	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5807	pHlp->pfnPrintf(pHlp, "\n");
5808	}
5809	break;
5810
5811	}
5812
5813	/* advance. */
5814	if (pCurLeaf)
5815	{
5816	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5817	&& pCurLeaf->uSubLeaf <= uSubLeaf
5818	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
5819	pCurLeaf++;
5820	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5821	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
5822	pCurLeaf = NULL;
5823	}
5824	}
5825	}
5826
5827
5828	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5829	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
5830	{
5831	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5832	&& pCurLeaf->uLeaf <= uUpToLeaf)
5833	{
5834	pHlp->pfnPrintf(pHlp,
5835	" %s\n"
5836	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
5837	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5838	&& pCurLeaf->uLeaf <= uUpToLeaf)
5839	{
5840	CPUMCPUID Host = {0};
5841	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5842	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5843	#endif
5844	pHlp->pfnPrintf(pHlp,
5845	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5846	"Hst: %08x %08x %08x %08x\n",
5847	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5848	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5849	pCurLeaf++;
5850	}
5851	}
5852
5853	return pCurLeaf;
5854	}
5855
5856
5857	/**
5858	* Display the guest CpuId leaves.
5859	*
5860	* @param pVM The cross context VM structure.
5861	* @param pHlp The info helper functions.
5862	* @param pszArgs "terse", "default" or "verbose".
5863	*/
5864	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
5865	{
5866	/*
5867	* Parse the argument.
5868	*/
5869	unsigned iVerbosity = 1;
5870	if (pszArgs)
5871	{
5872	pszArgs = RTStrStripL(pszArgs);
5873	if (!strcmp(pszArgs, "terse"))
5874	iVerbosity--;
5875	else if (!strcmp(pszArgs, "verbose"))
5876	iVerbosity++;
5877	}
5878
5879	uint32_t uLeaf;
5880	CPUMCPUID Host = {0};
5881	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
5882	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
5883	PCCPUMCPUIDLEAF pCurLeaf;
5884	PCCPUMCPUIDLEAF pNextLeaf;
5885	bool const fIntel = RTX86IsIntelCpu(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
5886	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
5887	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
5888
5889	/*
5890	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
5891	*/
5892	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5893	uint32_t cHstMax = ASMCpuId_EAX(0);
5894	#else
5895	uint32_t cHstMax = 0;
5896	#endif
5897	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
5898	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
5899	pHlp->pfnPrintf(pHlp,
5900	" Raw Standard CPUID Leaves\n"
5901	" Leaf/sub-leaf eax ebx ecx edx\n");
5902	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
5903	{
5904	uint32_t cMaxSubLeaves = 1;
5905	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
5906	cMaxSubLeaves = 16;
5907	else if (uLeaf == 0xd)
5908	cMaxSubLeaves = 128;
5909
5910	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5911	{
5912	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5913	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5914	#endif
5915	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5916	&& pCurLeaf->uLeaf == uLeaf
5917	&& pCurLeaf->uSubLeaf == uSubLeaf)
5918	{
5919	pHlp->pfnPrintf(pHlp,
5920	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5921	"Hst: %08x %08x %08x %08x\n",
5922	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5923	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5924	pCurLeaf++;
5925	}
5926	else if ( uLeaf != 0xd
5927	\|\| uSubLeaf <= 1
5928	\|\| Host.uEbx != 0 )
5929	pHlp->pfnPrintf(pHlp,
5930	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5931	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5932
5933	/* Done? */
5934	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5935	\|\| pCurLeaf->uLeaf != uLeaf)
5936	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
5937	\|\| (uLeaf == 0x7 && Host.uEax == 0)
5938	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
5939	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
5940	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
5941	)
5942	)
5943	break;
5944	}
5945	}
5946	pNextLeaf = pCurLeaf;
5947
5948	/*
5949	* If verbose, decode it.
5950	*/
5951	if (iVerbosity && paLeaves[0].uLeaf == 0)
5952	pHlp->pfnPrintf(pHlp,
5953	"%36s %.04s%.04s%.04s\n"
5954	"%36s 0x00000000-%#010x\n"
5955	,
5956	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
5957	"Supports:", paLeaves[0].uEax);
5958
5959	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
5960	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
5961
5962	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
5963	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5964
5965	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
5966	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5967
5968	pCurLeaf = pNextLeaf;
5969
5970	/*
5971	* Hypervisor leaves.
5972	*
5973	* Unlike most of the other leaves reported, the guest hypervisor leaves
5974	* aren't a subset of the host CPUID bits.
5975	*/
5976	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
5977
5978	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5979	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5980	#endif
5981	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
5982	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
5983	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
5984	cMax = RT_MAX(cHstMax, cGstMax);
5985	if (cMax >= UINT32_C(0x40000000))
5986	{
5987	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
5988
5989	/** @todo dump these in more detail. */
5990
5991	pCurLeaf = pNextLeaf;
5992	}
5993
5994
5995	/*
5996	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
5997	* Implemented after AMD specs.
5998	*/
5999	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6000
6001	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6002	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6003	#endif
6004	cHstMax = RTX86IsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6005	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6006	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6007	cMax = RT_MAX(cHstMax, cGstMax);
6008	if (cMax >= UINT32_C(0x80000000))
6009	{
6010
6011	pHlp->pfnPrintf(pHlp,
6012	" Raw Extended CPUID Leaves\n"
6013	" Leaf/sub-leaf eax ebx ecx edx\n");
6014	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6015	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6016	{
6017	uint32_t cMaxSubLeaves = 1;
6018	if (uLeaf == UINT32_C(0x8000001d))
6019	cMaxSubLeaves = 16;
6020
6021	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6022	{
6023	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6024	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6025	#endif
6026	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6027	&& pCurLeaf->uLeaf == uLeaf
6028	&& pCurLeaf->uSubLeaf == uSubLeaf)
6029	{
6030	pHlp->pfnPrintf(pHlp,
6031	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6032	"Hst: %08x %08x %08x %08x\n",
6033	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6034	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6035	pCurLeaf++;
6036	}
6037	else if ( uLeaf != 0xd
6038	\|\| uSubLeaf <= 1
6039	\|\| Host.uEbx != 0 )
6040	pHlp->pfnPrintf(pHlp,
6041	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6042	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6043
6044	/* Done? */
6045	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6046	\|\| pCurLeaf->uLeaf != uLeaf)
6047	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6048	break;
6049	}
6050	}
6051	pNextLeaf = pCurLeaf;
6052
6053	/*
6054	* Understandable output
6055	*/
6056	if (iVerbosity)
6057	pHlp->pfnPrintf(pHlp,
6058	"Ext Name: %.4s%.4s%.4s\n"
6059	"Ext Supports: 0x80000000-%#010x\n",
6060	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6061
6062	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6063	if (iVerbosity && pCurLeaf)
6064	{
6065	uint32_t uEAX = pCurLeaf->uEax;
6066	pHlp->pfnPrintf(pHlp,
6067	"Family: %d \tExtended: %d \tEffective: %d\n"
6068	"Model: %d \tExtended: %d \tEffective: %d\n"
6069	"Stepping: %d\n"
6070	"Brand ID: %#05x\n",
6071	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
6072	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
6073	RTX86GetCpuStepping(uEAX),
6074	pCurLeaf->uEbx & 0xfff);
6075
6076	if (iVerbosity == 1)
6077	{
6078	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6079	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6080	}
6081	else
6082	{
6083	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6084	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6085	#endif
6086	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6087	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6088	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6089	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6090	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
6091	{
6092	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
6093	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6094	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6095	#endif
6096	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
6097	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
6098	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
6099	}
6100	}
6101	}
6102
6103	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6104	{
6105	char szString[443+1] = {0};
6106	uint32_t pu32 = (uint32_t )szString;
6107	*pu32++ = pCurLeaf->uEax;
6108	*pu32++ = pCurLeaf->uEbx;
6109	*pu32++ = pCurLeaf->uEcx;
6110	*pu32++ = pCurLeaf->uEdx;
6111	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6112	if (pCurLeaf)
6113	{
6114	*pu32++ = pCurLeaf->uEax;
6115	*pu32++ = pCurLeaf->uEbx;
6116	*pu32++ = pCurLeaf->uEcx;
6117	*pu32++ = pCurLeaf->uEdx;
6118	}
6119	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6120	if (pCurLeaf)
6121	{
6122	*pu32++ = pCurLeaf->uEax;
6123	*pu32++ = pCurLeaf->uEbx;
6124	*pu32++ = pCurLeaf->uEcx;
6125	*pu32++ = pCurLeaf->uEdx;
6126	}
6127	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6128	}
6129
6130	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6131	{
6132	uint32_t uEAX = pCurLeaf->uEax;
6133	uint32_t uEBX = pCurLeaf->uEbx;
6134	uint32_t uECX = pCurLeaf->uEcx;
6135	uint32_t uEDX = pCurLeaf->uEdx;
6136	char sz1[32];
6137	char sz2[32];
6138
6139	pHlp->pfnPrintf(pHlp,
6140	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6141	"TLB 2/4M Data: %s %3d entries\n",
6142	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6143	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6144	pHlp->pfnPrintf(pHlp,
6145	"TLB 4K Instr/Uni: %s %3d entries\n"
6146	"TLB 4K Data: %s %3d entries\n",
6147	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6148	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6149	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6150	"L1 Instr Cache Lines Per Tag: %d\n"
6151	"L1 Instr Cache Associativity: %s\n"
6152	"L1 Instr Cache Size: %d KB\n",
6153	(uEDX >> 0) & 0xff,
6154	(uEDX >> 8) & 0xff,
6155	getCacheAss((uEDX >> 16) & 0xff, sz1),
6156	(uEDX >> 24) & 0xff);
6157	pHlp->pfnPrintf(pHlp,
6158	"L1 Data Cache Line Size: %d bytes\n"
6159	"L1 Data Cache Lines Per Tag: %d\n"
6160	"L1 Data Cache Associativity: %s\n"
6161	"L1 Data Cache Size: %d KB\n",
6162	(uECX >> 0) & 0xff,
6163	(uECX >> 8) & 0xff,
6164	getCacheAss((uECX >> 16) & 0xff, sz1),
6165	(uECX >> 24) & 0xff);
6166	}
6167
6168	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6169	{
6170	uint32_t uEAX = pCurLeaf->uEax;
6171	uint32_t uEBX = pCurLeaf->uEbx;
6172	uint32_t uECX = pCurLeaf->uEcx;
6173	uint32_t uEDX = pCurLeaf->uEdx;
6174
6175	pHlp->pfnPrintf(pHlp,
6176	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6177	"L2 TLB 2/4M Data: %s %4d entries\n",
6178	getL23CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6179	getL23CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6180	pHlp->pfnPrintf(pHlp,
6181	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6182	"L2 TLB 4K Data: %s %4d entries\n",
6183	getL23CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6184	getL23CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6185	pHlp->pfnPrintf(pHlp,
6186	"L2 Cache Line Size: %d bytes\n"
6187	"L2 Cache Lines Per Tag: %d\n"
6188	"L2 Cache Associativity: %s\n"
6189	"L2 Cache Size: %d KB\n",
6190	(uECX >> 0) & 0xff,
6191	(uECX >> 8) & 0xf,
6192	getL23CacheAss((uECX >> 12) & 0xf),
6193	(uECX >> 16) & 0xffff);
6194	pHlp->pfnPrintf(pHlp,
6195	"L3 Cache Line Size: %d bytes\n"
6196	"L3 Cache Lines Per Tag: %d\n"
6197	"L3 Cache Associativity: %s\n"
6198	"L3 Cache Size: %d KB\n",
6199	(uEDX >> 0) & 0xff,
6200	(uEDX >> 8) & 0xf,
6201	getL23CacheAss((uEDX >> 12) & 0xf),
6202	((uEDX >> 18) & 0x3fff) * 512);
6203	}
6204
6205	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
6206	{
6207	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6208	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6209	#endif
6210	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
6211	{
6212	if (iVerbosity < 1)
6213	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
6214	else
6215	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
6216	}
6217	}
6218
6219	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
6220	if (pCurLeaf != NULL)
6221	{
6222	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6223	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6224	#endif
6225	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
6226	{
6227	if (iVerbosity < 1)
6228	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
6229	else
6230	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
6231	}
6232
6233	if (iVerbosity)
6234	{
6235	uint32_t uEAX = pCurLeaf->uEax;
6236	uint32_t uECX = pCurLeaf->uEcx;
6237
6238	/** @todo 0x80000008:EAX[23:16] is only defined for AMD. We'll get 0 on Intel. On
6239	* AMD if we get 0, the guest physical address width should be taken from
6240	* 0x80000008:EAX[7:0] instead. Guest Physical address width is relevant
6241	* for guests using nested paging. */
6242	pHlp->pfnPrintf(pHlp,
6243	"Physical Address Width: %d bits\n"
6244	"Virtual Address Width: %d bits\n"
6245	"Guest Physical Address Width: %d bits\n",
6246	(uEAX >> 0) & 0xff,
6247	(uEAX >> 8) & 0xff,
6248	(uEAX >> 16) & 0xff);
6249
6250	/** @todo 0x80000008:ECX is reserved on Intel (we'll get incorrect physical core
6251	* count here). */
6252	pHlp->pfnPrintf(pHlp,
6253	"Physical Core Count: %d\n",
6254	((uECX >> 0) & 0xff) + 1);
6255	}
6256	}
6257
6258	pCurLeaf = pNextLeaf;
6259	}
6260
6261
6262
6263	/*
6264	* Centaur.
6265	*/
6266	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
6267
6268	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6269	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6270	#endif
6271	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
6272	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
6273	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
6274	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
6275	cMax = RT_MAX(cHstMax, cGstMax);
6276	if (cMax >= UINT32_C(0xc0000000))
6277	{
6278	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
6279
6280	/*
6281	* Understandable output
6282	*/
6283	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
6284	pHlp->pfnPrintf(pHlp,
6285	"Centaur Supports: 0xc0000000-%#010x\n",
6286	pCurLeaf->uEax);
6287
6288	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
6289	{
6290	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6291	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6292	#endif
6293	uint32_t uEdxGst = pCurLeaf->uEdx;
6294	uint32_t uEdxHst = Host.uEdx;
6295
6296	if (iVerbosity == 1)
6297	{
6298	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
6299	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
6300	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
6301	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
6302	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
6303	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
6304	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
6305	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
6306	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
6307	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6308	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
6309	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
6310	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
6311	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
6312	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
6313	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
6314	for (unsigned iBit = 14; iBit < 32; iBit++)
6315	if (uEdxGst & RT_BIT(iBit))
6316	pHlp->pfnPrintf(pHlp, " %d", iBit);
6317	pHlp->pfnPrintf(pHlp, "\n");
6318	}
6319	else
6320	{
6321	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
6322	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
6323	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
6324	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
6325	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
6326	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
6327	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
6328	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
6329	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
6330	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6331	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
6332	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
6333	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
6334	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
6335	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
6336	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
6337	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
6338	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
6339	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
6340	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
6341	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
6342	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
6343	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
6344	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
6345	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
6346	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
6347	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
6348	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
6349	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
6350	for (unsigned iBit = 27; iBit < 32; iBit++)
6351	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
6352	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
6353	pHlp->pfnPrintf(pHlp, "\n");
6354	}
6355	}
6356
6357	pCurLeaf = pNextLeaf;
6358	}
6359
6360	/*
6361	* The remainder.
6362	*/
6363	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
6364	}
6365
6366	#endif /* !IN_VBOX_CPU_REPORT */
6367

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 107650

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