CPUMR3CpuId.cpp@ 50087

Last change on this file since 50087 was 50087, checked in by vboxsync, 11 years ago
VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES: Dump some potentially useful info in the release log.
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File size: 51.6 KB

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1	/* $Id: CPUMR3CpuId.cpp 50087 2014-01-16 18:15:44Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2014 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_CPUM
22	#include <VBox/vmm/cpum.h>
23	#include "CPUMInternal.h"
24	#include <VBox/vmm/vm.h>
25
26	#include <VBox/err.h>
27	#include <iprt/asm-amd64-x86.h>
28	#include <iprt/ctype.h>
29	#include <iprt/mem.h>
30	#include <iprt/string.h>
31
32
33	/*******************************************************************************
34	* Global Variables *
35	*******************************************************************************/
36	/**
37	* The intel pentium family.
38	*/
39	static const CPUMMICROARCH g_aenmIntelFamily06[] =
40	{
41	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
42	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
43	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
44	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
45	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
46	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
47	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
48	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
49	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
50	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
51	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
52	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
53	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
54	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
55	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
56	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
57	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
58	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
59	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
60	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
61	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
63	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
64	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
65	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
66	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
67	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
68	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
69	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
70	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
71	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
72	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
73	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
74	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
79	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
80	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
81	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
82	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
83	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
84	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
86	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
87	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
88	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
89	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
90	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
91	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
95	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
96	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
97	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
98	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
99	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
100	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
102	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
103	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
104	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
105	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
106	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
107	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
111	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
112	/* [71(0x47)] = */ kCpumMicroarch_Intel_Unknown,
113	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
114	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
115	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
116	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Unknown,
118	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
119	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Unknown,
120	/* [79(0x4f)] = */ kCpumMicroarch_Intel_Unknown,
121	};
122
123
124
125	/**
126	* Figures out the (sub-)micro architecture given a bit of CPUID info.
127	*
128	* @returns Micro architecture.
129	* @param enmVendor The CPU vendor .
130	* @param bFamily The CPU family.
131	* @param bModel The CPU model.
132	* @param bStepping The CPU stepping.
133	*/
134	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
135	uint8_t bModel, uint8_t bStepping)
136	{
137	if (enmVendor == CPUMCPUVENDOR_AMD)
138	{
139	switch (bFamily)
140	{
141	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
142	case 0x03: return kCpumMicroarch_AMD_Am386;
143	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
144	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
145	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
146	case 0x06:
147	switch (bModel)
148	{
149	case 0: kCpumMicroarch_AMD_K7_Palomino;
150	case 1: kCpumMicroarch_AMD_K7_Palomino;
151	case 2: kCpumMicroarch_AMD_K7_Palomino;
152	case 3: kCpumMicroarch_AMD_K7_Spitfire;
153	case 4: kCpumMicroarch_AMD_K7_Thunderbird;
154	case 6: kCpumMicroarch_AMD_K7_Palomino;
155	case 7: kCpumMicroarch_AMD_K7_Morgan;
156	case 8: kCpumMicroarch_AMD_K7_Thoroughbred;
157	case 10: kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
158	}
159	return kCpumMicroarch_AMD_K7_Unknown;
160	case 0x0f:
161	/*
162	* This family is a friggin mess. Trying my best to make some
163	* sense out of it. Too much happened in the 0x0f family to
164	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
165	*
166	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
167	* cpu-world.com, and other places:
168	* - 130nm:
169	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
170	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
171	* - Newcastle: FC0/DH-CG (errum #180: FE0/DH-CG), FF0/DH-CG
172	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
173	* - Odessa: FC0/DH-CG (errum #180: FE0/DH-CG)
174	* - Paris: FF0/DH-CG, FC0/DH-CG (errum #180: FE0/DH-CG),
175	* - 90nm:
176	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
177	* - Oakville: 10FC0/DH-D0.
178	* - Georgetown: 10FC0/DH-D0.
179	* - Sonora: 10FC0/DH-D0.
180	* - Venus: 20F71/SH-E4
181	* - Troy: 20F51/SH-E4
182	* - Athens: 20F51/SH-E4
183	* - San Diego: 20F71/SH-E4.
184	* - Lancaster: 20F42/SH-E5
185	* - Newark: 20F42/SH-E5.
186	* - Albany: 20FC2/DH-E6.
187	* - Roma: 20FC2/DH-E6.
188	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
189	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
190	* - 90nm introducing Dual core:
191	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
192	* - Italy: 20F10/JH-E1, 20F12/JH-E6
193	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
194	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
195	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
196	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheeper models):
197	* - Santa Ana: 40F32/JH-F2, /-F3
198	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
199	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
200	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
201	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
202	* - Keene: 40FC2/DH-F2.
203	* - Richmond: 40FC2/DH-F2
204	* - Taylor: 40F82/BH-F2
205	* - Trinidad: 40F82/BH-F2
206	*
207	* - 65nm:
208	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
209	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
210	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
211	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
212	* - Sherman: /-G1, 70FC2/DH-G2.
213	* - Huron: 70FF2/DH-G2.
214	*/
215	if (bModel < 0x10)
216	return kCpumMicroarch_AMD_K8_130nm;
217	if (bModel >= 0x60 && bModel < 0x80)
218	return kCpumMicroarch_AMD_K8_65nm;
219	if (bModel >= 0x40)
220	return kCpumMicroarch_AMD_K8_90nm_AMDV;
221	switch (bModel)
222	{
223	case 0x21:
224	case 0x23:
225	case 0x2b:
226	case 0x2f:
227	case 0x37:
228	case 0x3f:
229	return kCpumMicroarch_AMD_K8_90nm_DualCore;
230	}
231	return kCpumMicroarch_AMD_K8_90nm;
232	case 0x10:
233	return kCpumMicroarch_AMD_K10;
234	case 0x11:
235	return kCpumMicroarch_AMD_K10_Lion;
236	case 0x12:
237	return kCpumMicroarch_AMD_K10_Llano;
238	case 0x14:
239	return kCpumMicroarch_AMD_Bobcat;
240	case 0x15:
241	switch (bModel)
242	{
243	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
244	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
245	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
246	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
247	case 0x11: /* ?? */
248	case 0x12: /* ?? */
249	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
250	}
251	return kCpumMicroarch_AMD_15h_Unknown;
252	case 0x16:
253	return kCpumMicroarch_AMD_Jaguar;
254
255	}
256	return kCpumMicroarch_AMD_Unknown;
257	}
258
259	if (enmVendor == CPUMCPUVENDOR_INTEL)
260	{
261	switch (bFamily)
262	{
263	case 3:
264	return kCpumMicroarch_Intel_80386;
265	case 4:
266	return kCpumMicroarch_Intel_80486;
267	case 5:
268	return kCpumMicroarch_Intel_P5;
269	case 6:
270	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
271	return g_aenmIntelFamily06[bModel];
272	return kCpumMicroarch_Intel_Atom_Unknown;
273	case 15:
274	switch (bModel)
275	{
276	case 0: return kCpumMicroarch_Intel_NB_Willamette;
277	case 1: return kCpumMicroarch_Intel_NB_Willamette;
278	case 2: return kCpumMicroarch_Intel_NB_Northwood;
279	case 3: return kCpumMicroarch_Intel_NB_Prescott;
280	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
281	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
282	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
283	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
284	default: return kCpumMicroarch_Intel_NB_Unknown;
285	}
286	break;
287	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
288	case 1:
289	return kCpumMicroarch_Intel_8086;
290	case 2:
291	return kCpumMicroarch_Intel_80286;
292	}
293	return kCpumMicroarch_Intel_Unknown;
294	}
295
296	if (enmVendor == CPUMCPUVENDOR_VIA)
297	{
298	switch (bFamily)
299	{
300	case 5:
301	switch (bModel)
302	{
303	case 1: return kCpumMicroarch_Centaur_C6;
304	case 4: return kCpumMicroarch_Centaur_C6;
305	case 8: return kCpumMicroarch_Centaur_C2;
306	case 9: return kCpumMicroarch_Centaur_C3;
307	}
308	break;
309
310	case 6:
311	switch (bModel)
312	{
313	case 5: return kCpumMicroarch_VIA_C3_M2;
314	case 6: return kCpumMicroarch_VIA_C3_C5A;
315	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
316	case 8: return kCpumMicroarch_VIA_C3_C5N;
317	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
318	case 10: return kCpumMicroarch_VIA_C7_C5J;
319	case 15: return kCpumMicroarch_VIA_Isaiah;
320	}
321	break;
322	}
323	return kCpumMicroarch_VIA_Unknown;
324	}
325
326	if (enmVendor == CPUMCPUVENDOR_CYRIX)
327	{
328	switch (bFamily)
329	{
330	case 4:
331	switch (bModel)
332	{
333	case 9: return kCpumMicroarch_Cyrix_5x86;
334	}
335	break;
336
337	case 5:
338	switch (bModel)
339	{
340	case 2: return kCpumMicroarch_Cyrix_M1;
341	case 4: return kCpumMicroarch_Cyrix_MediaGX;
342	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
343	}
344	break;
345
346	case 6:
347	switch (bModel)
348	{
349	case 0: return kCpumMicroarch_Cyrix_M2;
350	}
351	break;
352
353	}
354	return kCpumMicroarch_Cyrix_Unknown;
355	}
356
357	return kCpumMicroarch_Unknown;
358	}
359
360
361	/**
362	* Translates a microarchitecture enum value to the corresponding string
363	* constant.
364	*
365	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
366	* NULL if the value is invalid.
367	*
368	* @param enmMicroarch The enum value to convert.
369	*/
370	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
371	{
372	switch (enmMicroarch)
373	{
374	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
375	CASE_RET_STR(kCpumMicroarch_Intel_8086);
376	CASE_RET_STR(kCpumMicroarch_Intel_80186);
377	CASE_RET_STR(kCpumMicroarch_Intel_80286);
378	CASE_RET_STR(kCpumMicroarch_Intel_80386);
379	CASE_RET_STR(kCpumMicroarch_Intel_80486);
380	CASE_RET_STR(kCpumMicroarch_Intel_P5);
381
382	CASE_RET_STR(kCpumMicroarch_Intel_P6);
383	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
384	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
385
386	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
387	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
388	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
389
390	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
391	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
392
393	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
394	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
395	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
396	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
397	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
398	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
399	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
400	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Cannonlake);
401
402	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
403	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
404	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
405	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
406	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
407	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
408	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
409
410	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
411	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
412	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
413	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
414	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
415	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
416	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
417
418	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
419
420	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
421	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
422	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
423	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
424	CASE_RET_STR(kCpumMicroarch_AMD_K5);
425	CASE_RET_STR(kCpumMicroarch_AMD_K6);
426
427	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
428	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
429	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
430	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
431	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
432	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
433	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
434
435	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
436	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
437	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
438	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
439	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
440
441	CASE_RET_STR(kCpumMicroarch_AMD_K10);
442	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
443	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
444	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
445	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
446
447	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
448	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
449	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
450	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
451	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
452
453	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
454
455	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
456
457	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
458	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
459	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
460	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
461	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
462	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
463	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
464	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
465	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
466	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
467	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
468	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
469	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
470
471	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
472	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
473	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
474	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
475	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
476	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
477
478	CASE_RET_STR(kCpumMicroarch_Unknown);
479
480	#undef CASE_RET_STR
481	case kCpumMicroarch_Invalid:
482	case kCpumMicroarch_Intel_End:
483	case kCpumMicroarch_Intel_Core7_End:
484	case kCpumMicroarch_Intel_Atom_End:
485	case kCpumMicroarch_Intel_P6_Core_Atom_End:
486	case kCpumMicroarch_Intel_NB_End:
487	case kCpumMicroarch_AMD_K7_End:
488	case kCpumMicroarch_AMD_K8_End:
489	case kCpumMicroarch_AMD_15h_End:
490	case kCpumMicroarch_AMD_16h_End:
491	case kCpumMicroarch_AMD_End:
492	case kCpumMicroarch_VIA_End:
493	case kCpumMicroarch_Cyrix_End:
494	case kCpumMicroarch_32BitHack:
495	break;
496	/* no default! */
497	}
498
499	return NULL;
500	}
501
502
503
504	/**
505	* Gets a matching leaf in the CPUID leaf array.
506	*
507	* @returns Pointer to the matching leaf, or NULL if not found.
508	* @param paLeaves The CPUID leaves to search. This is sorted.
509	* @param cLeaves The number of leaves in the array.
510	* @param uLeaf The leaf to locate.
511	* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
512	*/
513	PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
514	{
515	/* Lazy bird does linear lookup here since this is only used for the
516	occational CPUID overrides. */
517	for (uint32_t i = 0; i < cLeaves; i++)
518	if ( paLeaves[i].uLeaf == uLeaf
519	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
520	return &paLeaves[i];
521	return NULL;
522	}
523
524
525	/**
526	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
527	*
528	* @returns true if found, false it not.
529	* @param paLeaves The CPUID leaves to search. This is sorted.
530	* @param cLeaves The number of leaves in the array.
531	* @param uLeaf The leaf to locate.
532	* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
533	* @param pLegacy The legacy output leaf.
534	*/
535	bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf, PCPUMCPUID pLeagcy)
536	{
537	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
538	if (pLeaf)
539	{
540	pLeagcy->eax = pLeaf->uEax;
541	pLeagcy->ebx = pLeaf->uEbx;
542	pLeagcy->ecx = pLeaf->uEcx;
543	pLeagcy->edx = pLeaf->uEdx;
544	return true;
545	}
546	return false;
547	}
548
549
550	/**
551	* Ensures that the CPUID leaf array can hold one more leaf.
552	*
553	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
554	* failure.
555	* @param ppaLeaves Pointer to the variable holding the array
556	* pointer (input/output).
557	* @param cLeaves The current array size.
558	*/
559	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
560	{
561	uint32_t cAllocated = RT_ALIGN(cLeaves, 16);
562	if (cLeaves + 1 > cAllocated)
563	{
564	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
565	if (!pvNew)
566	{
567	RTMemFree(*ppaLeaves);
568	*ppaLeaves = NULL;
569	return NULL;
570	}
571	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
572	}
573	return *ppaLeaves;
574	}
575
576
577	/**
578	* Append a CPUID leaf or sub-leaf.
579	*
580	* ASSUMES linear insertion order, so we'll won't need to do any searching or
581	* replace anything. Use cpumR3CpuIdInsert for those cases.
582	*
583	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
584	* the caller need do no more work.
585	* @param ppaLeaves Pointer to the the pointer to the array of sorted
586	* CPUID leaves and sub-leaves.
587	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
588	* @param uLeaf The leaf we're adding.
589	* @param uSubLeaf The sub-leaf number.
590	* @param fSubLeafMask The sub-leaf mask.
591	* @param uEax The EAX value.
592	* @param uEbx The EBX value.
593	* @param uEcx The ECX value.
594	* @param uEdx The EDX value.
595	* @param fFlags The flags.
596	*/
597	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
598	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
599	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
600	{
601	if (!cpumR3CpuIdEnsureSpace(ppaLeaves, *pcLeaves))
602	return VERR_NO_MEMORY;
603
604	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
605	Assert( *pcLeaves == 0
606	\|\| pNew[-1].uLeaf < uLeaf
607	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
608
609	pNew->uLeaf = uLeaf;
610	pNew->uSubLeaf = uSubLeaf;
611	pNew->fSubLeafMask = fSubLeafMask;
612	pNew->uEax = uEax;
613	pNew->uEbx = uEbx;
614	pNew->uEcx = uEcx;
615	pNew->uEdx = uEdx;
616	pNew->fFlags = fFlags;
617
618	*pcLeaves += 1;
619	return VINF_SUCCESS;
620	}
621
622
623	/**
624	* Inserts a CPU ID leaf, replacing any existing ones.
625	*
626	* When inserting a simple leaf where we already got a series of subleaves with
627	* the same leaf number (eax), the simple leaf will replace the whole series.
628	*
629	* This ASSUMES that the leave array is still on the normal heap and has only
630	* been allocated/reallocated by the cpumR3CpuIdEnsureSpace function.
631	*
632	* @returns VBox status code.
633	* @param ppaLeaves Pointer to the the pointer to the array of sorted
634	* CPUID leaves and sub-leaves.
635	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
636	* @param pNewLeaf Pointer to the data of the new leaf we're about to
637	* insert.
638	*/
639	int cpumR3CpuIdInsert(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
640	{
641	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
642	uint32_t cLeaves = *pcLeaves;
643
644	/*
645	* Validate the new leaf a little.
646	*/
647	AssertReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED), VERR_INVALID_FLAGS);
648	AssertReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0, VERR_INVALID_PARAMETER);
649	AssertReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1), VERR_INVALID_PARAMETER);
650	AssertReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf, VERR_INVALID_PARAMETER);
651
652
653	/*
654	* Find insertion point. The lazy bird uses the same excuse as in
655	* cpumR3CpuIdGetLeaf().
656	*/
657	uint32_t i = 0;
658	while ( i < cLeaves
659	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
660	i++;
661	if ( i < cLeaves
662	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
663	{
664	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
665	{
666	/*
667	* The subleaf mask differs, replace all existing leaves with the
668	* same leaf number.
669	*/
670	uint32_t c = 1;
671	while ( i + c < cLeaves
672	&& paLeaves[i + c].uSubLeaf == pNewLeaf->uLeaf)
673	c++;
674	if (c > 1 && i + c < cLeaves)
675	{
676	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
677	*pcLeaves = cLeaves -= c - 1;
678	}
679
680	paLeaves[i] = *pNewLeaf;
681	return VINF_SUCCESS;
682	}
683
684	/* Find subleaf insertion point. */
685	while ( i < cLeaves
686	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf)
687	i++;
688
689	/*
690	* If we've got an exactly matching leaf, replace it.
691	*/
692	if ( paLeaves[i].uLeaf == pNewLeaf->uLeaf
693	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
694	{
695	paLeaves[i] = *pNewLeaf;
696	return VINF_SUCCESS;
697	}
698	}
699
700	/*
701	* Adding a new leaf at 'i'.
702	*/
703	paLeaves = cpumR3CpuIdEnsureSpace(ppaLeaves, cLeaves);
704	if (!paLeaves)
705	return VERR_NO_MEMORY;
706
707	if (i < cLeaves)
708	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
709	*pcLeaves += 1;
710	paLeaves[i] = *pNewLeaf;
711	return VINF_SUCCESS;
712	}
713
714
715	/**
716	* Removes a range of CPUID leaves.
717	*
718	* This will not reallocate the array.
719	*
720	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
721	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
722	* @param uFirst The first leaf.
723	* @param uLast The last leaf.
724	*/
725	void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
726	{
727	uint32_t cLeaves = *pcLeaves;
728
729	Assert(uFirst <= uLast);
730
731	/*
732	* Find the first one.
733	*/
734	uint32_t iFirst = 0;
735	while ( iFirst < cLeaves
736	&& paLeaves[iFirst].uLeaf < uFirst)
737	iFirst++;
738
739	/*
740	* Find the end (last + 1).
741	*/
742	uint32_t iEnd = iFirst;
743	while ( iEnd < cLeaves
744	&& paLeaves[iEnd].uLeaf <= uLast)
745	iEnd++;
746
747	/*
748	* Adjust the array if anything needs removing.
749	*/
750	if (iFirst < iEnd)
751	{
752	if (iEnd < cLeaves)
753	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
754	*pcLeaves = cLeaves -= (iEnd - iFirst);
755	}
756	}
757
758
759
760	/**
761	* Checks if ECX make a difference when reading a given CPUID leaf.
762	*
763	* @returns @c true if it does, @c false if it doesn't.
764	* @param uLeaf The leaf we're reading.
765	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
766	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
767	* final sub-leaf.
768	*/
769	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
770	{
771	*pfFinalEcxUnchanged = false;
772
773	uint32_t auPrev[4];
774	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
775
776	/* Look for sub-leaves. */
777	uint32_t uSubLeaf = 1;
778	for (;;)
779	{
780	uint32_t auCur[4];
781	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
782	if (memcmp(auCur, auPrev, sizeof(auCur)))
783	break;
784
785	/* Advance / give up. */
786	uSubLeaf++;
787	if (uSubLeaf >= 64)
788	{
789	*pcSubLeaves = 1;
790	return false;
791	}
792	}
793
794	/* Count sub-leaves. */
795	uSubLeaf = 0;
796	for (;;)
797	{
798	uint32_t auCur[4];
799	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
800
801	/* Exactly when this terminates isn't quite consistent. When working
802	0xb, we should probably only check if ebx == 0... */
803	if ( auCur[0] == 0
804	&& auCur[1] == 0
805	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
806	&& (auCur[3] == 0 \|\| uLeaf == 0xb) )
807	{
808	if (auCur[2] == uSubLeaf)
809	*pfFinalEcxUnchanged = true;
810	*pcSubLeaves = uSubLeaf + 1;
811	return true;
812	}
813
814	/* Advance / give up. */
815	uSubLeaf++;
816	if (uSubLeaf >= 128)
817	{
818	*pcSubLeaves = UINT32_MAX;
819	return true;
820	}
821	}
822	}
823
824
825	/**
826	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
827	*
828	* @returns VBox status code.
829	* @param ppaLeaves Where to return the array pointer on success.
830	* Use RTMemFree to release.
831	* @param pcLeaves Where to return the size of the array on
832	* success.
833	*/
834	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
835	{
836	*ppaLeaves = NULL;
837	*pcLeaves = 0;
838
839	/*
840	* Try out various candidates. This must be sorted!
841	*/
842	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
843	{
844	{ UINT32_C(0x00000000), false },
845	{ UINT32_C(0x10000000), false },
846	{ UINT32_C(0x20000000), false },
847	{ UINT32_C(0x30000000), false },
848	{ UINT32_C(0x40000000), false },
849	{ UINT32_C(0x50000000), false },
850	{ UINT32_C(0x60000000), false },
851	{ UINT32_C(0x70000000), false },
852	{ UINT32_C(0x80000000), false },
853	{ UINT32_C(0x80860000), false },
854	{ UINT32_C(0x8ffffffe), true },
855	{ UINT32_C(0x8fffffff), true },
856	{ UINT32_C(0x90000000), false },
857	{ UINT32_C(0xa0000000), false },
858	{ UINT32_C(0xb0000000), false },
859	{ UINT32_C(0xc0000000), false },
860	{ UINT32_C(0xd0000000), false },
861	{ UINT32_C(0xe0000000), false },
862	{ UINT32_C(0xf0000000), false },
863	};
864
865	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
866	{
867	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
868	uint32_t uEax, uEbx, uEcx, uEdx;
869	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
870
871	/*
872	* Does EAX look like a typical leaf count value?
873	*/
874	if ( uEax > uLeaf
875	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
876	{
877	/* Yes, dump them. */
878	uint32_t cLeaves = uEax - uLeaf + 1;
879	while (cLeaves-- > 0)
880	{
881	/* Check three times here to reduce the chance of CPU migration
882	resulting in false positives with things like the APIC ID. */
883	uint32_t cSubLeaves;
884	bool fFinalEcxUnchanged;
885	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
886	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
887	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
888	{
889	if (cSubLeaves > 16)
890	{
891	/* This shouldn't happen. But in case it does, file all
892	relevant details in the release log. */
893	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
894	LogRel(("------------------ dump of problematic subleaves ------------------\n"));
895	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
896	{
897	uint32_t auTmp[4];
898	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
899	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
900	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
901	}
902	LogRel(("----------------- dump of what we've found so far -----------------\n"));
903	for (uint32_t i = 0 ; i < *pcLeaves; i++)
904	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
905	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
906	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
907	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
908	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
909	}
910
911	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
912	{
913	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
914	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
915	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx,
916	uSubLeaf + 1 == cSubLeaves && fFinalEcxUnchanged
917	? CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED : 0);
918	if (RT_FAILURE(rc))
919	return rc;
920	}
921	}
922	else
923	{
924	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
925	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
926	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
927	if (RT_FAILURE(rc))
928	return rc;
929	}
930
931	/* next */
932	uLeaf++;
933	}
934	}
935	/*
936	* Special CPUIDs needs special handling as they don't follow the
937	* leaf count principle used above.
938	*/
939	else if (s_aCandidates[iOuter].fSpecial)
940	{
941	bool fKeep = false;
942	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
943	fKeep = true;
944	else if ( uLeaf == 0x8fffffff
945	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
946	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
947	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
948	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
949	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
950	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
951	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
952	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
953	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
954	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
955	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
956	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
957	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
958	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
959	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
960	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
961	fKeep = true;
962	if (fKeep)
963	{
964	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
965	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
966	if (RT_FAILURE(rc))
967	return rc;
968	}
969	}
970	}
971
972	return VINF_SUCCESS;
973	}
974
975
976	/**
977	* Determines the method the CPU uses to handle unknown CPUID leaves.
978	*
979	* @returns VBox status code.
980	* @param penmUnknownMethod Where to return the method.
981	* @param pDefUnknown Where to return default unknown values. This
982	* will be set, even if the resulting method
983	* doesn't actually needs it.
984	*/
985	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
986	{
987	uint32_t uLastStd = ASMCpuId_EAX(0);
988	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
989	if (!ASMIsValidExtRange(uLastExt))
990	uLastExt = 0x80000000;
991
992	uint32_t auChecks[] =
993	{
994	uLastStd + 1,
995	uLastStd + 5,
996	uLastStd + 8,
997	uLastStd + 32,
998	uLastStd + 251,
999	uLastExt + 1,
1000	uLastExt + 8,
1001	uLastExt + 15,
1002	uLastExt + 63,
1003	uLastExt + 255,
1004	0x7fbbffcc,
1005	0x833f7872,
1006	0xefff2353,
1007	0x35779456,
1008	0x1ef6d33e,
1009	};
1010
1011	static const uint32_t s_auValues[] =
1012	{
1013	0xa95d2156,
1014	0x00000001,
1015	0x00000002,
1016	0x00000008,
1017	0x00000000,
1018	0x55773399,
1019	0x93401769,
1020	0x12039587,
1021	};
1022
1023	/*
1024	* Simple method, all zeros.
1025	*/
1026	*penmUnknownMethod = CPUMUKNOWNCPUID_DEFAULTS;
1027	pDefUnknown->eax = 0;
1028	pDefUnknown->ebx = 0;
1029	pDefUnknown->ecx = 0;
1030	pDefUnknown->edx = 0;
1031
1032	/*
1033	* Intel has been observed returning the last standard leaf.
1034	*/
1035	uint32_t auLast[4];
1036	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1037
1038	uint32_t cChecks = RT_ELEMENTS(auChecks);
1039	while (cChecks > 0)
1040	{
1041	uint32_t auCur[4];
1042	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1043	if (memcmp(auCur, auLast, sizeof(auCur)))
1044	break;
1045	cChecks--;
1046	}
1047	if (cChecks == 0)
1048	{
1049	/* Now, what happens when the input changes? Esp. ECX. */
1050	uint32_t cTotal = 0;
1051	uint32_t cSame = 0;
1052	uint32_t cLastWithEcx = 0;
1053	uint32_t cNeither = 0;
1054	uint32_t cValues = RT_ELEMENTS(s_auValues);
1055	while (cValues > 0)
1056	{
1057	uint32_t uValue = s_auValues[cValues - 1];
1058	uint32_t auLastWithEcx[4];
1059	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1060	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1061
1062	cChecks = RT_ELEMENTS(auChecks);
1063	while (cChecks > 0)
1064	{
1065	uint32_t auCur[4];
1066	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1067	if (!memcmp(auCur, auLast, sizeof(auCur)))
1068	{
1069	cSame++;
1070	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1071	cLastWithEcx++;
1072	}
1073	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1074	cLastWithEcx++;
1075	else
1076	cNeither++;
1077	cTotal++;
1078	cChecks--;
1079	}
1080	cValues--;
1081	}
1082
1083	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1084	if (cSame == cTotal)
1085	*penmUnknownMethod = CPUMUKNOWNCPUID_LAST_STD_LEAF;
1086	else if (cLastWithEcx == cTotal)
1087	*penmUnknownMethod = CPUMUKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1088	else
1089	*penmUnknownMethod = CPUMUKNOWNCPUID_LAST_STD_LEAF;
1090	pDefUnknown->eax = auLast[0];
1091	pDefUnknown->ebx = auLast[1];
1092	pDefUnknown->ecx = auLast[2];
1093	pDefUnknown->edx = auLast[3];
1094	return VINF_SUCCESS;
1095	}
1096
1097	/*
1098	* Unchanged register values?
1099	*/
1100	cChecks = RT_ELEMENTS(auChecks);
1101	while (cChecks > 0)
1102	{
1103	uint32_t const uLeaf = auChecks[cChecks - 1];
1104	uint32_t cValues = RT_ELEMENTS(s_auValues);
1105	while (cValues > 0)
1106	{
1107	uint32_t uValue = s_auValues[cValues - 1];
1108	uint32_t auCur[4];
1109	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1110	if ( auCur[0] != uLeaf
1111	\|\| auCur[1] != uValue
1112	\|\| auCur[2] != uValue
1113	\|\| auCur[3] != uValue)
1114	break;
1115	cValues--;
1116	}
1117	if (cValues != 0)
1118	break;
1119	cChecks--;
1120	}
1121	if (cChecks == 0)
1122	{
1123	*penmUnknownMethod = CPUMUKNOWNCPUID_PASSTHRU;
1124	return VINF_SUCCESS;
1125	}
1126
1127	/*
1128	* Just go with the simple method.
1129	*/
1130	return VINF_SUCCESS;
1131	}
1132
1133
1134	/**
1135	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1136	*
1137	* @returns Read only name string.
1138	* @param enmUnknownMethod The method to translate.
1139	*/
1140	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUKNOWNCPUID enmUnknownMethod)
1141	{
1142	switch (enmUnknownMethod)
1143	{
1144	case CPUMUKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1145	case CPUMUKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1146	case CPUMUKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1147	case CPUMUKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1148
1149	case CPUMUKNOWNCPUID_INVALID:
1150	case CPUMUKNOWNCPUID_END:
1151	case CPUMUKNOWNCPUID_32BIT_HACK:
1152	break;
1153	}
1154	return "Invalid-unknown-CPUID-method";
1155	}
1156
1157
1158	/**
1159	* Detect the CPU vendor give n the
1160	*
1161	* @returns The vendor.
1162	* @param uEAX EAX from CPUID(0).
1163	* @param uEBX EBX from CPUID(0).
1164	* @param uECX ECX from CPUID(0).
1165	* @param uEDX EDX from CPUID(0).
1166	*/
1167	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1168	{
1169	if (ASMIsValidStdRange(uEAX))
1170	{
1171	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1172	return CPUMCPUVENDOR_AMD;
1173
1174	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1175	return CPUMCPUVENDOR_INTEL;
1176
1177	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1178	return CPUMCPUVENDOR_VIA;
1179
1180	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1181	&& uECX == UINT32_C(0x64616574)
1182	&& uEDX == UINT32_C(0x736E4978))
1183	return CPUMCPUVENDOR_CYRIX;
1184
1185	/* "Geode by NSC", example: family 5, model 9. */
1186
1187	/** @todo detect the other buggers... */
1188	}
1189
1190	return CPUMCPUVENDOR_UNKNOWN;
1191	}
1192
1193
1194	/**
1195	* Translates a CPU vendor enum value into the corresponding string constant.
1196	*
1197	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1198	* value name. This can be useful when generating code.
1199	*
1200	* @returns Read only name string.
1201	* @param enmVendor The CPU vendor value.
1202	*/
1203	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1204	{
1205	switch (enmVendor)
1206	{
1207	case CPUMCPUVENDOR_INTEL: return "INTEL";
1208	case CPUMCPUVENDOR_AMD: return "AMD";
1209	case CPUMCPUVENDOR_VIA: return "VIA";
1210	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1211	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1212
1213	case CPUMCPUVENDOR_INVALID:
1214	case CPUMCPUVENDOR_32BIT_HACK:
1215	break;
1216	}
1217	return "Invalid-cpu-vendor";
1218	}
1219
1220
1221	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1222	{
1223	/* Could do binary search, doing linear now because I'm lazy. */
1224	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1225	while (cLeaves-- > 0)
1226	{
1227	if (pLeaf->uLeaf == uLeaf)
1228	return pLeaf;
1229	pLeaf++;
1230	}
1231	return NULL;
1232	}
1233
1234
1235	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1236	{
1237	RT_ZERO(*pFeatures);
1238	if (cLeaves >= 2)
1239	{
1240	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1241	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1242
1243	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(paLeaves[0].uEax,
1244	paLeaves[0].uEbx,
1245	paLeaves[0].uEcx,
1246	paLeaves[0].uEdx);
1247	pFeatures->uFamily = ASMGetCpuFamily(paLeaves[1].uEax);
1248	pFeatures->uModel = ASMGetCpuModel(paLeaves[1].uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1249	pFeatures->uStepping = ASMGetCpuStepping(paLeaves[1].uEax);
1250	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1251	pFeatures->uFamily,
1252	pFeatures->uModel,
1253	pFeatures->uStepping);
1254
1255	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1256	if (pLeaf)
1257	pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff;
1258	else if (paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1259	pFeatures->cMaxPhysAddrWidth = 36;
1260	else
1261	pFeatures->cMaxPhysAddrWidth = 32;
1262
1263	/* Standard features. */
1264	pFeatures->fMsr = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_MSR);
1265	pFeatures->fApic = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_APIC);
1266	pFeatures->fX2Apic = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1267	pFeatures->fPse = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE);
1268	pFeatures->fPse36 = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1269	pFeatures->fPae = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PAE);
1270	pFeatures->fPat = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PAT);
1271	pFeatures->fFxSaveRstor = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1272	pFeatures->fSysEnter = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_SEP);
1273	pFeatures->fHypervisorPresent = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_HVP);
1274	pFeatures->fMonitorMWait = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1275
1276	/* Extended features. */
1277	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1278	if (pExtLeaf)
1279	{
1280	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1281	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1282	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1283	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1284	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1285	}
1286
1287	if ( pExtLeaf
1288	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1289	{
1290	/* AMD features. */
1291	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1292	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1293	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1294	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1295	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1296	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1297	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1298	}
1299
1300	/*
1301	* Quirks.
1302	*/
1303	pFeatures->fLeakyFxSR = pExtLeaf
1304	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1305	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1306	&& pFeatures->uFamily >= 6 /* K7 and up */;
1307	}
1308	else
1309	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1310	return VINF_SUCCESS;
1311	}
1312

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 50087

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