VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 54749

Last change on this file since 54749 was 54749, checked in by vboxsync, 10 years ago

CPUM: Increase the max cpuid leaves a lot. Fixed incorrect sanitizing of leaf 4.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 235.8 KB
Line 
1/* $Id: CPUMR3CpuId.cpp 54749 2015-03-13 16:40:01Z vboxsync $ */
2/** @file
3 * CPUM - CPU ID part.
4 */
5
6/*
7 * Copyright (C) 2013-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_CPUM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/dbgf.h>
24#include <VBox/vmm/hm.h>
25#include <VBox/vmm/ssm.h>
26#include "CPUMInternal.h"
27#include <VBox/vmm/vm.h>
28#include <VBox/vmm/mm.h>
29
30#include <VBox/err.h>
31#include <iprt/asm-amd64-x86.h>
32#include <iprt/ctype.h>
33#include <iprt/mem.h>
34#include <iprt/string.h>
35
36
37/*******************************************************************************
38* Defined Constants And Macros *
39*******************************************************************************/
40/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
41#define CPUM_CPUID_MAX_LEAVES 2048
42
43
44/*******************************************************************************
45* Global Variables *
46*******************************************************************************/
47/**
48 * The intel pentium family.
49 */
50static const CPUMMICROARCH g_aenmIntelFamily06[] =
51{
52 /* [ 0(0x00)] = */ kCpumMicroarch_Intel_P6, /* Pentium Pro A-step (says sandpile.org). */
53 /* [ 1(0x01)] = */ kCpumMicroarch_Intel_P6, /* Pentium Pro */
54 /* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
55 /* [ 3(0x03)] = */ kCpumMicroarch_Intel_P6_II, /* PII Klamath */
56 /* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
57 /* [ 5(0x05)] = */ kCpumMicroarch_Intel_P6_II, /* PII Deschutes */
58 /* [ 6(0x06)] = */ kCpumMicroarch_Intel_P6_II, /* Celeron Mendocino. */
59 /* [ 7(0x07)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Katmai. */
60 /* [ 8(0x08)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Coppermine (includes Celeron). */
61 /* [ 9(0x09)] = */ kCpumMicroarch_Intel_P6_M_Banias, /* Pentium/Celeron M Banias. */
62 /* [10(0x0a)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Xeon */
63 /* [11(0x0b)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Tualatin (includes Celeron). */
64 /* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
65 /* [13(0x0d)] = */ kCpumMicroarch_Intel_P6_M_Dothan, /* Pentium/Celeron M Dothan. */
66 /* [14(0x0e)] = */ kCpumMicroarch_Intel_Core_Yonah, /* Core Yonah (Enhanced Pentium M). */
67 /* [15(0x0f)] = */ kCpumMicroarch_Intel_Core2_Merom, /* Merom */
68 /* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
69 /* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
70 /* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
71 /* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
72 /* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
73 /* [21(0x15)] = */ kCpumMicroarch_Intel_P6_M_Dothan, /* Tolapai - System-on-a-chip. */
74 /* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
75 /* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
76 /* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
77 /* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
78 /* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
79 /* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
80 /* [28(0x1c)] = */ kCpumMicroarch_Intel_Atom_Bonnell, /* Diamonville, Pineview, */
81 /* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
82 /* [30(0x1e)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Clarksfield, Lynnfield, Jasper Forest. */
83 /* [31(0x1f)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
84 /* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
85 /* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
86 /* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
87 /* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
88 /* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
89 /* [37(0x25)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Arrandale, Clarksdale. */
90 /* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
91 /* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
92 /* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
93 /* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
94 /* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
95 /* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
96 /* [44(0x2c)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Gulftown, Westmere-EP. */
97 /* [45(0x2d)] = */ kCpumMicroarch_Intel_Core7_SandyBridge, /* SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
98 /* [46(0x2e)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Beckton (Xeon). */
99 /* [47(0x2f)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Westmere-EX. */
100 /* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
101 /* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
102 /* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
103 /* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
104 /* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
105 /* [53(0x35)] = */ kCpumMicroarch_Intel_Atom_Saltwell, /* ?? */
106 /* [54(0x36)] = */ kCpumMicroarch_Intel_Atom_Saltwell, /* Cedarview, ++ */
107 /* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
108 /* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
109 /* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
110 /* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
111 /* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
112 /* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
113 /* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
114 /* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
115 /* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
116 /* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
117 /* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
118 /* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
119 /* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
120 /* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
121 /* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
122 /* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123 /* [71(0x47)] = */ kCpumMicroarch_Intel_Unknown,
124 /* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
125 /* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
126 /* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
127 /* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
128 /* [76(0x4c)] = */ kCpumMicroarch_Intel_Unknown,
129 /* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
130 /* [78(0x4e)] = */ kCpumMicroarch_Intel_Unknown,
131 /* [79(0x4f)] = */ kCpumMicroarch_Intel_Unknown,
132};
133
134
135
136/**
137 * Figures out the (sub-)micro architecture given a bit of CPUID info.
138 *
139 * @returns Micro architecture.
140 * @param enmVendor The CPU vendor .
141 * @param bFamily The CPU family.
142 * @param bModel The CPU model.
143 * @param bStepping The CPU stepping.
144 */
145VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
146 uint8_t bModel, uint8_t bStepping)
147{
148 if (enmVendor == CPUMCPUVENDOR_AMD)
149 {
150 switch (bFamily)
151 {
152 case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
153 case 0x03: return kCpumMicroarch_AMD_Am386;
154 case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
155 case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
156 case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
157 case 0x06:
158 switch (bModel)
159 {
160 case 0: kCpumMicroarch_AMD_K7_Palomino;
161 case 1: kCpumMicroarch_AMD_K7_Palomino;
162 case 2: kCpumMicroarch_AMD_K7_Palomino;
163 case 3: kCpumMicroarch_AMD_K7_Spitfire;
164 case 4: kCpumMicroarch_AMD_K7_Thunderbird;
165 case 6: kCpumMicroarch_AMD_K7_Palomino;
166 case 7: kCpumMicroarch_AMD_K7_Morgan;
167 case 8: kCpumMicroarch_AMD_K7_Thoroughbred;
168 case 10: kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
169 }
170 return kCpumMicroarch_AMD_K7_Unknown;
171 case 0x0f:
172 /*
173 * This family is a friggin mess. Trying my best to make some
174 * sense out of it. Too much happened in the 0x0f family to
175 * lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
176 *
177 * Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
178 * cpu-world.com, and other places:
179 * - 130nm:
180 * - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
181 * - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
182 * - Newcastle: FC0/DH-CG (errum #180: FE0/DH-CG), FF0/DH-CG
183 * - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
184 * - Odessa: FC0/DH-CG (errum #180: FE0/DH-CG)
185 * - Paris: FF0/DH-CG, FC0/DH-CG (errum #180: FE0/DH-CG),
186 * - 90nm:
187 * - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
188 * - Oakville: 10FC0/DH-D0.
189 * - Georgetown: 10FC0/DH-D0.
190 * - Sonora: 10FC0/DH-D0.
191 * - Venus: 20F71/SH-E4
192 * - Troy: 20F51/SH-E4
193 * - Athens: 20F51/SH-E4
194 * - San Diego: 20F71/SH-E4.
195 * - Lancaster: 20F42/SH-E5
196 * - Newark: 20F42/SH-E5.
197 * - Albany: 20FC2/DH-E6.
198 * - Roma: 20FC2/DH-E6.
199 * - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
200 * - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
201 * - 90nm introducing Dual core:
202 * - Denmark: 20F30/JH-E1, 20F32/JH-E6
203 * - Italy: 20F10/JH-E1, 20F12/JH-E6
204 * - Egypt: 20F10/JH-E1, 20F12/JH-E6
205 * - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
206 * - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
207 * - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
208 * - Santa Ana: 40F32/JH-F2, /-F3
209 * - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
210 * - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
211 * - Manila: 50FF2/DH-F2, 40FF2/DH-F2
212 * - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
213 * - Keene: 40FC2/DH-F2.
214 * - Richmond: 40FC2/DH-F2
215 * - Taylor: 40F82/BH-F2
216 * - Trinidad: 40F82/BH-F2
217 *
218 * - 65nm:
219 * - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
220 * - Tyler: 60F81/BH-G1, 60F82/BH-G2.
221 * - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
222 * - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
223 * - Sherman: /-G1, 70FC2/DH-G2.
224 * - Huron: 70FF2/DH-G2.
225 */
226 if (bModel < 0x10)
227 return kCpumMicroarch_AMD_K8_130nm;
228 if (bModel >= 0x60 && bModel < 0x80)
229 return kCpumMicroarch_AMD_K8_65nm;
230 if (bModel >= 0x40)
231 return kCpumMicroarch_AMD_K8_90nm_AMDV;
232 switch (bModel)
233 {
234 case 0x21:
235 case 0x23:
236 case 0x2b:
237 case 0x2f:
238 case 0x37:
239 case 0x3f:
240 return kCpumMicroarch_AMD_K8_90nm_DualCore;
241 }
242 return kCpumMicroarch_AMD_K8_90nm;
243 case 0x10:
244 return kCpumMicroarch_AMD_K10;
245 case 0x11:
246 return kCpumMicroarch_AMD_K10_Lion;
247 case 0x12:
248 return kCpumMicroarch_AMD_K10_Llano;
249 case 0x14:
250 return kCpumMicroarch_AMD_Bobcat;
251 case 0x15:
252 switch (bModel)
253 {
254 case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
255 case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
256 case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
257 case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
258 case 0x11: /* ?? */
259 case 0x12: /* ?? */
260 case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
261 }
262 return kCpumMicroarch_AMD_15h_Unknown;
263 case 0x16:
264 return kCpumMicroarch_AMD_Jaguar;
265
266 }
267 return kCpumMicroarch_AMD_Unknown;
268 }
269
270 if (enmVendor == CPUMCPUVENDOR_INTEL)
271 {
272 switch (bFamily)
273 {
274 case 3:
275 return kCpumMicroarch_Intel_80386;
276 case 4:
277 return kCpumMicroarch_Intel_80486;
278 case 5:
279 return kCpumMicroarch_Intel_P5;
280 case 6:
281 if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
282 return g_aenmIntelFamily06[bModel];
283 return kCpumMicroarch_Intel_Atom_Unknown;
284 case 15:
285 switch (bModel)
286 {
287 case 0: return kCpumMicroarch_Intel_NB_Willamette;
288 case 1: return kCpumMicroarch_Intel_NB_Willamette;
289 case 2: return kCpumMicroarch_Intel_NB_Northwood;
290 case 3: return kCpumMicroarch_Intel_NB_Prescott;
291 case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
292 case 5: return kCpumMicroarch_Intel_NB_Unknown; /*??*/
293 case 6: return kCpumMicroarch_Intel_NB_CedarMill;
294 case 7: return kCpumMicroarch_Intel_NB_Gallatin;
295 default: return kCpumMicroarch_Intel_NB_Unknown;
296 }
297 break;
298 /* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
299 case 1:
300 return kCpumMicroarch_Intel_8086;
301 case 2:
302 return kCpumMicroarch_Intel_80286;
303 }
304 return kCpumMicroarch_Intel_Unknown;
305 }
306
307 if (enmVendor == CPUMCPUVENDOR_VIA)
308 {
309 switch (bFamily)
310 {
311 case 5:
312 switch (bModel)
313 {
314 case 1: return kCpumMicroarch_Centaur_C6;
315 case 4: return kCpumMicroarch_Centaur_C6;
316 case 8: return kCpumMicroarch_Centaur_C2;
317 case 9: return kCpumMicroarch_Centaur_C3;
318 }
319 break;
320
321 case 6:
322 switch (bModel)
323 {
324 case 5: return kCpumMicroarch_VIA_C3_M2;
325 case 6: return kCpumMicroarch_VIA_C3_C5A;
326 case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
327 case 8: return kCpumMicroarch_VIA_C3_C5N;
328 case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
329 case 10: return kCpumMicroarch_VIA_C7_C5J;
330 case 15: return kCpumMicroarch_VIA_Isaiah;
331 }
332 break;
333 }
334 return kCpumMicroarch_VIA_Unknown;
335 }
336
337 if (enmVendor == CPUMCPUVENDOR_CYRIX)
338 {
339 switch (bFamily)
340 {
341 case 4:
342 switch (bModel)
343 {
344 case 9: return kCpumMicroarch_Cyrix_5x86;
345 }
346 break;
347
348 case 5:
349 switch (bModel)
350 {
351 case 2: return kCpumMicroarch_Cyrix_M1;
352 case 4: return kCpumMicroarch_Cyrix_MediaGX;
353 case 5: return kCpumMicroarch_Cyrix_MediaGXm;
354 }
355 break;
356
357 case 6:
358 switch (bModel)
359 {
360 case 0: return kCpumMicroarch_Cyrix_M2;
361 }
362 break;
363
364 }
365 return kCpumMicroarch_Cyrix_Unknown;
366 }
367
368 return kCpumMicroarch_Unknown;
369}
370
371
372/**
373 * Translates a microarchitecture enum value to the corresponding string
374 * constant.
375 *
376 * @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
377 * NULL if the value is invalid.
378 *
379 * @param enmMicroarch The enum value to convert.
380 */
381VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
382{
383 switch (enmMicroarch)
384 {
385#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
386 CASE_RET_STR(kCpumMicroarch_Intel_8086);
387 CASE_RET_STR(kCpumMicroarch_Intel_80186);
388 CASE_RET_STR(kCpumMicroarch_Intel_80286);
389 CASE_RET_STR(kCpumMicroarch_Intel_80386);
390 CASE_RET_STR(kCpumMicroarch_Intel_80486);
391 CASE_RET_STR(kCpumMicroarch_Intel_P5);
392
393 CASE_RET_STR(kCpumMicroarch_Intel_P6);
394 CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
395 CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
396
397 CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
398 CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
399 CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
400
401 CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
402 CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
403
404 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
405 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
406 CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
407 CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
408 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
409 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
410 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
411 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Cannonlake);
412
413 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
414 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
415 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
416 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
417 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
418 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
419 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
420
421 CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
422 CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
423 CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
424 CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
425 CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
426 CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
427 CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
428
429 CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
430
431 CASE_RET_STR(kCpumMicroarch_AMD_Am286);
432 CASE_RET_STR(kCpumMicroarch_AMD_Am386);
433 CASE_RET_STR(kCpumMicroarch_AMD_Am486);
434 CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
435 CASE_RET_STR(kCpumMicroarch_AMD_K5);
436 CASE_RET_STR(kCpumMicroarch_AMD_K6);
437
438 CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
439 CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
440 CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
441 CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
442 CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
443 CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
444 CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
445
446 CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
447 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
448 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
449 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
450 CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
451
452 CASE_RET_STR(kCpumMicroarch_AMD_K10);
453 CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
454 CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
455 CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
456 CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
457
458 CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
459 CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
460 CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
461 CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
462 CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
463
464 CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
465
466 CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
467
468 CASE_RET_STR(kCpumMicroarch_Centaur_C6);
469 CASE_RET_STR(kCpumMicroarch_Centaur_C2);
470 CASE_RET_STR(kCpumMicroarch_Centaur_C3);
471 CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
472 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
473 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
474 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
475 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
476 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
477 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
478 CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
479 CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
480 CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
481
482 CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
483 CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
484 CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
485 CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
486 CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
487 CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
488
489 CASE_RET_STR(kCpumMicroarch_Unknown);
490
491#undef CASE_RET_STR
492 case kCpumMicroarch_Invalid:
493 case kCpumMicroarch_Intel_End:
494 case kCpumMicroarch_Intel_Core7_End:
495 case kCpumMicroarch_Intel_Atom_End:
496 case kCpumMicroarch_Intel_P6_Core_Atom_End:
497 case kCpumMicroarch_Intel_NB_End:
498 case kCpumMicroarch_AMD_K7_End:
499 case kCpumMicroarch_AMD_K8_End:
500 case kCpumMicroarch_AMD_15h_End:
501 case kCpumMicroarch_AMD_16h_End:
502 case kCpumMicroarch_AMD_End:
503 case kCpumMicroarch_VIA_End:
504 case kCpumMicroarch_Cyrix_End:
505 case kCpumMicroarch_32BitHack:
506 break;
507 /* no default! */
508 }
509
510 return NULL;
511}
512
513
514
515/**
516 * Gets a matching leaf in the CPUID leaf array.
517 *
518 * @returns Pointer to the matching leaf, or NULL if not found.
519 * @param paLeaves The CPUID leaves to search. This is sorted.
520 * @param cLeaves The number of leaves in the array.
521 * @param uLeaf The leaf to locate.
522 * @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
523 */
524static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
525{
526 /* Lazy bird does linear lookup here since this is only used for the
527 occational CPUID overrides. */
528 for (uint32_t i = 0; i < cLeaves; i++)
529 if ( paLeaves[i].uLeaf == uLeaf
530 && paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
531 return &paLeaves[i];
532 return NULL;
533}
534
535
536/**
537 * Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
538 *
539 * @returns true if found, false it not.
540 * @param paLeaves The CPUID leaves to search. This is sorted.
541 * @param cLeaves The number of leaves in the array.
542 * @param uLeaf The leaf to locate.
543 * @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
544 * @param pLegacy The legacy output leaf.
545 */
546static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
547 PCPUMCPUID pLegacy)
548{
549 PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
550 if (pLeaf)
551 {
552 pLegacy->uEax = pLeaf->uEax;
553 pLegacy->uEbx = pLeaf->uEbx;
554 pLegacy->uEcx = pLeaf->uEcx;
555 pLegacy->uEdx = pLeaf->uEdx;
556 return true;
557 }
558 return false;
559}
560
561
562/**
563 * Ensures that the CPUID leaf array can hold one more leaf.
564 *
565 * @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
566 * failure.
567 * @param pVM Pointer to the VM, used as the heap selector. Passing
568 * NULL uses the host-context heap, otherwise the VM's
569 * hyper heap is used.
570 * @param ppaLeaves Pointer to the variable holding the array pointer
571 * (input/output).
572 * @param cLeaves The current array size.
573 *
574 * @remarks This function will automatically update the R0 and RC pointers when
575 * using the hyper heap, which means @a ppaLeaves and @a cLeaves must
576 * be the corresponding VM's CPUID arrays (which is asserted).
577 */
578static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
579{
580 /*
581 * If pVM is not specified, we're on the regular heap and can waste a
582 * little space to speed things up.
583 */
584 uint32_t cAllocated;
585 if (!pVM)
586 {
587 cAllocated = RT_ALIGN(cLeaves, 16);
588 if (cLeaves + 1 > cAllocated)
589 {
590 void *pvNew = RTMemRealloc(*ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
591 if (pvNew)
592 *ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
593 else
594 {
595 RTMemFree(*ppaLeaves);
596 *ppaLeaves = NULL;
597 }
598 }
599 }
600 /*
601 * Otherwise, we're on the hyper heap and are probably just inserting
602 * one or two leaves and should conserve space.
603 */
604 else
605 {
606#ifdef IN_VBOX_CPU_REPORT
607 AssertReleaseFailed();
608#else
609 Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
610 Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
611
612 size_t cb = cLeaves * sizeof(**ppaLeaves);
613 size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
614 int rc = MMR3HyperRealloc(pVM, *ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void **)ppaLeaves);
615 if (RT_SUCCESS(rc))
616 {
617 /* Update the R0 and RC pointers. */
618 pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
619 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
620 }
621 else
622 {
623 *ppaLeaves = NULL;
624 pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
625 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
626 LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
627 }
628#endif
629 }
630 return *ppaLeaves;
631}
632
633
634/**
635 * Append a CPUID leaf or sub-leaf.
636 *
637 * ASSUMES linear insertion order, so we'll won't need to do any searching or
638 * replace anything. Use cpumR3CpuIdInsert() for those cases.
639 *
640 * @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
641 * the caller need do no more work.
642 * @param ppaLeaves Pointer to the the pointer to the array of sorted
643 * CPUID leaves and sub-leaves.
644 * @param pcLeaves Where we keep the leaf count for *ppaLeaves.
645 * @param uLeaf The leaf we're adding.
646 * @param uSubLeaf The sub-leaf number.
647 * @param fSubLeafMask The sub-leaf mask.
648 * @param uEax The EAX value.
649 * @param uEbx The EBX value.
650 * @param uEcx The ECX value.
651 * @param uEdx The EDX value.
652 * @param fFlags The flags.
653 */
654static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves,
655 uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
656 uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
657{
658 if (!cpumR3CpuIdEnsureSpace(NULL /* pVM */, ppaLeaves, *pcLeaves))
659 return VERR_NO_MEMORY;
660
661 PCPUMCPUIDLEAF pNew = &(*ppaLeaves)[*pcLeaves];
662 Assert( *pcLeaves == 0
663 || pNew[-1].uLeaf < uLeaf
664 || (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
665
666 pNew->uLeaf = uLeaf;
667 pNew->uSubLeaf = uSubLeaf;
668 pNew->fSubLeafMask = fSubLeafMask;
669 pNew->uEax = uEax;
670 pNew->uEbx = uEbx;
671 pNew->uEcx = uEcx;
672 pNew->uEdx = uEdx;
673 pNew->fFlags = fFlags;
674
675 *pcLeaves += 1;
676 return VINF_SUCCESS;
677}
678
679
680/**
681 * Inserts a CPU ID leaf, replacing any existing ones.
682 *
683 * When inserting a simple leaf where we already got a series of subleaves with
684 * the same leaf number (eax), the simple leaf will replace the whole series.
685 *
686 * When pVM is NULL, this ASSUMES that the leaves array is still on the normal
687 * host-context heap and has only been allocated/reallocated by the
688 * cpumR3CpuIdEnsureSpace function.
689 *
690 * @returns VBox status code.
691 * @param pVM Pointer to the VM, used as the heap selector.
692 * Passing NULL uses the host-context heap, otherwise
693 * the VM's hyper heap is used.
694 * @param ppaLeaves Pointer to the the pointer to the array of sorted
695 * CPUID leaves and sub-leaves. Must be NULL if using
696 * the hyper heap.
697 * @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must be
698 * NULL if using the hyper heap.
699 * @param pNewLeaf Pointer to the data of the new leaf we're about to
700 * insert.
701 */
702static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
703{
704 /*
705 * Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
706 */
707 if (pVM)
708 {
709 AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
710 AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
711
712 ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
713 pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
714 }
715
716 PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
717 uint32_t cLeaves = *pcLeaves;
718
719 /*
720 * Validate the new leaf a little.
721 */
722 AssertReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK), VERR_INVALID_FLAGS);
723 AssertReturn(pNewLeaf->fSubLeafMask != 0 || pNewLeaf->uSubLeaf == 0, VERR_INVALID_PARAMETER);
724 AssertReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1), VERR_INVALID_PARAMETER);
725 AssertReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf, VERR_INVALID_PARAMETER);
726
727 /*
728 * Find insertion point. The lazy bird uses the same excuse as in
729 * cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
730 */
731 uint32_t i;
732 if ( cLeaves > 0
733 && paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
734 {
735 /* Add at end. */
736 i = cLeaves;
737 }
738 else if ( cLeaves > 0
739 && paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
740 {
741 /* Either replacing the last leaf or dealing with sub-leaves. Spool
742 back to the first sub-leaf to pretend we did the linear search. */
743 i = cLeaves - 1;
744 while ( i > 0
745 && paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
746 i--;
747 }
748 else
749 {
750 /* Linear search from the start. */
751 i = 0;
752 while ( i < cLeaves
753 && paLeaves[i].uLeaf < pNewLeaf->uLeaf)
754 i++;
755 }
756 if ( i < cLeaves
757 && paLeaves[i].uLeaf == pNewLeaf->uLeaf)
758 {
759 if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
760 {
761 /*
762 * The sub-leaf mask differs, replace all existing leaves with the
763 * same leaf number.
764 */
765 uint32_t c = 1;
766 while ( i + c < cLeaves
767 && paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
768 c++;
769 if (c > 1 && i + c < cLeaves)
770 {
771 memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
772 *pcLeaves = cLeaves -= c - 1;
773 }
774
775 paLeaves[i] = *pNewLeaf;
776 return VINF_SUCCESS;
777 }
778
779 /* Find sub-leaf insertion point. */
780 while ( i < cLeaves
781 && paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf)
782 i++;
783
784 /*
785 * If we've got an exactly matching leaf, replace it.
786 */
787 if ( paLeaves[i].uLeaf == pNewLeaf->uLeaf
788 && paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
789 {
790 paLeaves[i] = *pNewLeaf;
791 return VINF_SUCCESS;
792 }
793 }
794
795 /*
796 * Adding a new leaf at 'i'.
797 */
798 AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
799 paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
800 if (!paLeaves)
801 return VERR_NO_MEMORY;
802
803 if (i < cLeaves)
804 memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
805 *pcLeaves += 1;
806 paLeaves[i] = *pNewLeaf;
807 return VINF_SUCCESS;
808}
809
810
811/**
812 * Removes a range of CPUID leaves.
813 *
814 * This will not reallocate the array.
815 *
816 * @param paLeaves The array of sorted CPUID leaves and sub-leaves.
817 * @param pcLeaves Where we keep the leaf count for @a paLeaves.
818 * @param uFirst The first leaf.
819 * @param uLast The last leaf.
820 */
821static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
822{
823 uint32_t cLeaves = *pcLeaves;
824
825 Assert(uFirst <= uLast);
826
827 /*
828 * Find the first one.
829 */
830 uint32_t iFirst = 0;
831 while ( iFirst < cLeaves
832 && paLeaves[iFirst].uLeaf < uFirst)
833 iFirst++;
834
835 /*
836 * Find the end (last + 1).
837 */
838 uint32_t iEnd = iFirst;
839 while ( iEnd < cLeaves
840 && paLeaves[iEnd].uLeaf <= uLast)
841 iEnd++;
842
843 /*
844 * Adjust the array if anything needs removing.
845 */
846 if (iFirst < iEnd)
847 {
848 if (iEnd < cLeaves)
849 memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
850 *pcLeaves = cLeaves -= (iEnd - iFirst);
851 }
852}
853
854
855
856/**
857 * Checks if ECX make a difference when reading a given CPUID leaf.
858 *
859 * @returns @c true if it does, @c false if it doesn't.
860 * @param uLeaf The leaf we're reading.
861 * @param pcSubLeaves Number of sub-leaves accessible via ECX.
862 * @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
863 * final sub-leaf (for leaf 0xb only).
864 */
865static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t *pcSubLeaves, bool *pfFinalEcxUnchanged)
866{
867 *pfFinalEcxUnchanged = false;
868
869 uint32_t auCur[4];
870 uint32_t auPrev[4];
871 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
872
873 /* Look for sub-leaves. */
874 uint32_t uSubLeaf = 1;
875 for (;;)
876 {
877 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
878 if (memcmp(auCur, auPrev, sizeof(auCur)))
879 break;
880
881 /* Advance / give up. */
882 uSubLeaf++;
883 if (uSubLeaf >= 64)
884 {
885 *pcSubLeaves = 1;
886 return false;
887 }
888 }
889
890 /* Count sub-leaves. */
891 uint32_t cRepeats = 0;
892 uSubLeaf = 0;
893 for (;;)
894 {
895 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
896
897 /* Figuring out when to stop isn't entirely straight forward as we need
898 to cover undocumented behavior up to a point and implementation shortcuts. */
899
900 /* 1. Look for zero values. */
901 if ( auCur[0] == 0
902 && auCur[1] == 0
903 && (auCur[2] == 0 || auCur[2] == uSubLeaf)
904 && (auCur[3] == 0 || uLeaf == 0xb /* edx is fixed */) )
905 break;
906
907 /* 2. Look for more than 4 repeating value sets. */
908 if ( auCur[0] == auPrev[0]
909 && auCur[1] == auPrev[1]
910 && ( auCur[2] == auPrev[2]
911 || ( auCur[2] == uSubLeaf
912 && auPrev[2] == uSubLeaf - 1) )
913 && auCur[3] == auPrev[3])
914 {
915 cRepeats++;
916 if (cRepeats > 4)
917 break;
918 }
919 else
920 cRepeats = 0;
921
922 /* 3. Leaf 0xb level type 0 check. */
923 if ( uLeaf == 0xb
924 && (auCur[3] & 0xff00) == 0
925 && (auPrev[3] & 0xff00) == 0)
926 break;
927
928 /* 99. Give up. */
929 if (uSubLeaf >= 128)
930 {
931#ifndef IN_VBOX_CPU_REPORT
932 /* Ok, limit it according to the documentation if possible just to
933 avoid annoying users with these detection issues. */
934 uint32_t cDocLimit = UINT32_MAX;
935 if (uLeaf == 0x4)
936 cDocLimit = 4;
937 else if (uLeaf == 0x7)
938 cDocLimit = 1;
939 else if (uLeaf == 0xf)
940 cDocLimit = 2;
941 if (cDocLimit != UINT32_MAX)
942 {
943 *pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
944 *pcSubLeaves = cDocLimit + 3;
945 return true;
946 }
947#endif
948 *pcSubLeaves = UINT32_MAX;
949 return true;
950 }
951
952 /* Advance. */
953 uSubLeaf++;
954 memcpy(auPrev, auCur, sizeof(auCur));
955 }
956
957 /* Standard exit. */
958 *pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
959 *pcSubLeaves = uSubLeaf + 1 - cRepeats;
960 return true;
961}
962
963
964/**
965 * Gets a CPU ID leaf.
966 *
967 * @returns VBox status code.
968 * @param pVM Pointer to the VM.
969 * @param pLeaf Where to store the found leaf.
970 * @param uLeaf The leaf to locate.
971 * @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
972 */
973VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
974{
975 PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
976 uLeaf, uSubLeaf);
977 if (pcLeaf)
978 {
979 memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
980 return VINF_SUCCESS;
981 }
982
983 return VERR_NOT_FOUND;
984}
985
986
987/**
988 * Inserts a CPU ID leaf, replacing any existing ones.
989 *
990 * @returns VBox status code.
991 * @param pVM Pointer to the VM.
992 * @param pNewLeaf Pointer to the leaf being inserted.
993 */
994VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
995{
996 /*
997 * Validate parameters.
998 */
999 AssertReturn(pVM, VERR_INVALID_PARAMETER);
1000 AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1001
1002 /*
1003 * Disallow replacing CPU ID leaves that this API currently cannot manage.
1004 * These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1005 * If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1006 */
1007 if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1008 || pNewLeaf->uLeaf == UINT32_C(0x00000001)
1009 || pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1010 || pNewLeaf->uLeaf == UINT32_C(0x80000001)
1011 || pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1012 || pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1013 {
1014 return VERR_NOT_SUPPORTED;
1015 }
1016
1017 return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves */, NULL /* pcLeaves */, pNewLeaf);
1018}
1019
1020/**
1021 * Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1022 *
1023 * @returns VBox status code.
1024 * @param ppaLeaves Where to return the array pointer on success.
1025 * Use RTMemFree to release.
1026 * @param pcLeaves Where to return the size of the array on
1027 * success.
1028 */
1029VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
1030{
1031 *ppaLeaves = NULL;
1032 *pcLeaves = 0;
1033
1034 /*
1035 * Try out various candidates. This must be sorted!
1036 */
1037 static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1038 {
1039 { UINT32_C(0x00000000), false },
1040 { UINT32_C(0x10000000), false },
1041 { UINT32_C(0x20000000), false },
1042 { UINT32_C(0x30000000), false },
1043 { UINT32_C(0x40000000), false },
1044 { UINT32_C(0x50000000), false },
1045 { UINT32_C(0x60000000), false },
1046 { UINT32_C(0x70000000), false },
1047 { UINT32_C(0x80000000), false },
1048 { UINT32_C(0x80860000), false },
1049 { UINT32_C(0x8ffffffe), true },
1050 { UINT32_C(0x8fffffff), true },
1051 { UINT32_C(0x90000000), false },
1052 { UINT32_C(0xa0000000), false },
1053 { UINT32_C(0xb0000000), false },
1054 { UINT32_C(0xc0000000), false },
1055 { UINT32_C(0xd0000000), false },
1056 { UINT32_C(0xe0000000), false },
1057 { UINT32_C(0xf0000000), false },
1058 };
1059
1060 for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1061 {
1062 uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1063 uint32_t uEax, uEbx, uEcx, uEdx;
1064 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1065
1066 /*
1067 * Does EAX look like a typical leaf count value?
1068 */
1069 if ( uEax > uLeaf
1070 && uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1071 {
1072 /* Yes, dump them. */
1073 uint32_t cLeaves = uEax - uLeaf + 1;
1074 while (cLeaves-- > 0)
1075 {
1076 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1077
1078 uint32_t fFlags = 0;
1079
1080 /* There are currently three known leaves containing an APIC ID
1081 that needs EMT specific attention */
1082 if (uLeaf == 1)
1083 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1084 else if (uLeaf == 0xb && uEcx != 0)
1085 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1086 else if ( uLeaf == UINT32_C(0x8000001e)
1087 && ( uEax
1088 || uEbx
1089 || uEdx
1090 || ASMIsAmdCpuEx((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1091 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1092
1093
1094 /* Check three times here to reduce the chance of CPU migration
1095 resulting in false positives with things like the APIC ID. */
1096 uint32_t cSubLeaves;
1097 bool fFinalEcxUnchanged;
1098 if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1099 && cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1100 && cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1101 {
1102 if (cSubLeaves > 16)
1103 {
1104 /* This shouldn't happen. But in case it does, file all
1105 relevant details in the release log. */
1106 LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1107 LogRel(("------------------ dump of problematic subleaves ------------------\n"));
1108 for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1109 {
1110 uint32_t auTmp[4];
1111 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1112 LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1113 uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1114 }
1115 LogRel(("----------------- dump of what we've found so far -----------------\n"));
1116 for (uint32_t i = 0 ; i < *pcLeaves; i++)
1117 LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1118 (*ppaLeaves)[i].uLeaf, (*ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1119 (*ppaLeaves)[i].uEax, (*ppaLeaves)[i].uEbx, (*ppaLeaves)[i].uEcx, (*ppaLeaves)[i].uEdx));
1120 LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1121 return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1122 }
1123
1124 if (fFinalEcxUnchanged)
1125 fFlags |= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1126
1127 for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1128 {
1129 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1130 int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1131 uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1132 if (RT_FAILURE(rc))
1133 return rc;
1134 }
1135 }
1136 else
1137 {
1138 int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1139 uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1140 if (RT_FAILURE(rc))
1141 return rc;
1142 }
1143
1144 /* next */
1145 uLeaf++;
1146 }
1147 }
1148 /*
1149 * Special CPUIDs needs special handling as they don't follow the
1150 * leaf count principle used above.
1151 */
1152 else if (s_aCandidates[iOuter].fSpecial)
1153 {
1154 bool fKeep = false;
1155 if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1156 fKeep = true;
1157 else if ( uLeaf == 0x8fffffff
1158 && RT_C_IS_PRINT(RT_BYTE1(uEax))
1159 && RT_C_IS_PRINT(RT_BYTE2(uEax))
1160 && RT_C_IS_PRINT(RT_BYTE3(uEax))
1161 && RT_C_IS_PRINT(RT_BYTE4(uEax))
1162 && RT_C_IS_PRINT(RT_BYTE1(uEbx))
1163 && RT_C_IS_PRINT(RT_BYTE2(uEbx))
1164 && RT_C_IS_PRINT(RT_BYTE3(uEbx))
1165 && RT_C_IS_PRINT(RT_BYTE4(uEbx))
1166 && RT_C_IS_PRINT(RT_BYTE1(uEcx))
1167 && RT_C_IS_PRINT(RT_BYTE2(uEcx))
1168 && RT_C_IS_PRINT(RT_BYTE3(uEcx))
1169 && RT_C_IS_PRINT(RT_BYTE4(uEcx))
1170 && RT_C_IS_PRINT(RT_BYTE1(uEdx))
1171 && RT_C_IS_PRINT(RT_BYTE2(uEdx))
1172 && RT_C_IS_PRINT(RT_BYTE3(uEdx))
1173 && RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1174 fKeep = true;
1175 if (fKeep)
1176 {
1177 int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1178 uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1179 if (RT_FAILURE(rc))
1180 return rc;
1181 }
1182 }
1183 }
1184
1185 return VINF_SUCCESS;
1186}
1187
1188
1189/**
1190 * Determines the method the CPU uses to handle unknown CPUID leaves.
1191 *
1192 * @returns VBox status code.
1193 * @param penmUnknownMethod Where to return the method.
1194 * @param pDefUnknown Where to return default unknown values. This
1195 * will be set, even if the resulting method
1196 * doesn't actually needs it.
1197 */
1198VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1199{
1200 uint32_t uLastStd = ASMCpuId_EAX(0);
1201 uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1202 if (!ASMIsValidExtRange(uLastExt))
1203 uLastExt = 0x80000000;
1204
1205 uint32_t auChecks[] =
1206 {
1207 uLastStd + 1,
1208 uLastStd + 5,
1209 uLastStd + 8,
1210 uLastStd + 32,
1211 uLastStd + 251,
1212 uLastExt + 1,
1213 uLastExt + 8,
1214 uLastExt + 15,
1215 uLastExt + 63,
1216 uLastExt + 255,
1217 0x7fbbffcc,
1218 0x833f7872,
1219 0xefff2353,
1220 0x35779456,
1221 0x1ef6d33e,
1222 };
1223
1224 static const uint32_t s_auValues[] =
1225 {
1226 0xa95d2156,
1227 0x00000001,
1228 0x00000002,
1229 0x00000008,
1230 0x00000000,
1231 0x55773399,
1232 0x93401769,
1233 0x12039587,
1234 };
1235
1236 /*
1237 * Simple method, all zeros.
1238 */
1239 *penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1240 pDefUnknown->uEax = 0;
1241 pDefUnknown->uEbx = 0;
1242 pDefUnknown->uEcx = 0;
1243 pDefUnknown->uEdx = 0;
1244
1245 /*
1246 * Intel has been observed returning the last standard leaf.
1247 */
1248 uint32_t auLast[4];
1249 ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1250
1251 uint32_t cChecks = RT_ELEMENTS(auChecks);
1252 while (cChecks > 0)
1253 {
1254 uint32_t auCur[4];
1255 ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1256 if (memcmp(auCur, auLast, sizeof(auCur)))
1257 break;
1258 cChecks--;
1259 }
1260 if (cChecks == 0)
1261 {
1262 /* Now, what happens when the input changes? Esp. ECX. */
1263 uint32_t cTotal = 0;
1264 uint32_t cSame = 0;
1265 uint32_t cLastWithEcx = 0;
1266 uint32_t cNeither = 0;
1267 uint32_t cValues = RT_ELEMENTS(s_auValues);
1268 while (cValues > 0)
1269 {
1270 uint32_t uValue = s_auValues[cValues - 1];
1271 uint32_t auLastWithEcx[4];
1272 ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1273 &auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1274
1275 cChecks = RT_ELEMENTS(auChecks);
1276 while (cChecks > 0)
1277 {
1278 uint32_t auCur[4];
1279 ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1280 if (!memcmp(auCur, auLast, sizeof(auCur)))
1281 {
1282 cSame++;
1283 if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1284 cLastWithEcx++;
1285 }
1286 else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1287 cLastWithEcx++;
1288 else
1289 cNeither++;
1290 cTotal++;
1291 cChecks--;
1292 }
1293 cValues--;
1294 }
1295
1296 Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1297 if (cSame == cTotal)
1298 *penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1299 else if (cLastWithEcx == cTotal)
1300 *penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1301 else
1302 *penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1303 pDefUnknown->uEax = auLast[0];
1304 pDefUnknown->uEbx = auLast[1];
1305 pDefUnknown->uEcx = auLast[2];
1306 pDefUnknown->uEdx = auLast[3];
1307 return VINF_SUCCESS;
1308 }
1309
1310 /*
1311 * Unchanged register values?
1312 */
1313 cChecks = RT_ELEMENTS(auChecks);
1314 while (cChecks > 0)
1315 {
1316 uint32_t const uLeaf = auChecks[cChecks - 1];
1317 uint32_t cValues = RT_ELEMENTS(s_auValues);
1318 while (cValues > 0)
1319 {
1320 uint32_t uValue = s_auValues[cValues - 1];
1321 uint32_t auCur[4];
1322 ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1323 if ( auCur[0] != uLeaf
1324 || auCur[1] != uValue
1325 || auCur[2] != uValue
1326 || auCur[3] != uValue)
1327 break;
1328 cValues--;
1329 }
1330 if (cValues != 0)
1331 break;
1332 cChecks--;
1333 }
1334 if (cChecks == 0)
1335 {
1336 *penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1337 return VINF_SUCCESS;
1338 }
1339
1340 /*
1341 * Just go with the simple method.
1342 */
1343 return VINF_SUCCESS;
1344}
1345
1346
1347/**
1348 * Translates a unknow CPUID leaf method into the constant name (sans prefix).
1349 *
1350 * @returns Read only name string.
1351 * @param enmUnknownMethod The method to translate.
1352 */
1353VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1354{
1355 switch (enmUnknownMethod)
1356 {
1357 case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1358 case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1359 case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1360 case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1361
1362 case CPUMUNKNOWNCPUID_INVALID:
1363 case CPUMUNKNOWNCPUID_END:
1364 case CPUMUNKNOWNCPUID_32BIT_HACK:
1365 break;
1366 }
1367 return "Invalid-unknown-CPUID-method";
1368}
1369
1370
1371/**
1372 * Detect the CPU vendor give n the
1373 *
1374 * @returns The vendor.
1375 * @param uEAX EAX from CPUID(0).
1376 * @param uEBX EBX from CPUID(0).
1377 * @param uECX ECX from CPUID(0).
1378 * @param uEDX EDX from CPUID(0).
1379 */
1380VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1381{
1382 if (ASMIsValidStdRange(uEAX))
1383 {
1384 if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1385 return CPUMCPUVENDOR_AMD;
1386
1387 if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1388 return CPUMCPUVENDOR_INTEL;
1389
1390 if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1391 return CPUMCPUVENDOR_VIA;
1392
1393 if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1394 && uECX == UINT32_C(0x64616574)
1395 && uEDX == UINT32_C(0x736E4978))
1396 return CPUMCPUVENDOR_CYRIX;
1397
1398 /* "Geode by NSC", example: family 5, model 9. */
1399
1400 /** @todo detect the other buggers... */
1401 }
1402
1403 return CPUMCPUVENDOR_UNKNOWN;
1404}
1405
1406
1407/**
1408 * Translates a CPU vendor enum value into the corresponding string constant.
1409 *
1410 * The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1411 * value name. This can be useful when generating code.
1412 *
1413 * @returns Read only name string.
1414 * @param enmVendor The CPU vendor value.
1415 */
1416VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1417{
1418 switch (enmVendor)
1419 {
1420 case CPUMCPUVENDOR_INTEL: return "INTEL";
1421 case CPUMCPUVENDOR_AMD: return "AMD";
1422 case CPUMCPUVENDOR_VIA: return "VIA";
1423 case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1424 case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1425
1426 case CPUMCPUVENDOR_INVALID:
1427 case CPUMCPUVENDOR_32BIT_HACK:
1428 break;
1429 }
1430 return "Invalid-cpu-vendor";
1431}
1432
1433
1434static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1435{
1436 /* Could do binary search, doing linear now because I'm lazy. */
1437 PCCPUMCPUIDLEAF pLeaf = paLeaves;
1438 while (cLeaves-- > 0)
1439 {
1440 if (pLeaf->uLeaf == uLeaf)
1441 return pLeaf;
1442 pLeaf++;
1443 }
1444 return NULL;
1445}
1446
1447
1448int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1449{
1450 RT_ZERO(*pFeatures);
1451 if (cLeaves >= 2)
1452 {
1453 AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1454 AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1455
1456 pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(paLeaves[0].uEax,
1457 paLeaves[0].uEbx,
1458 paLeaves[0].uEcx,
1459 paLeaves[0].uEdx);
1460 pFeatures->uFamily = ASMGetCpuFamily(paLeaves[1].uEax);
1461 pFeatures->uModel = ASMGetCpuModel(paLeaves[1].uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1462 pFeatures->uStepping = ASMGetCpuStepping(paLeaves[1].uEax);
1463 pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1464 pFeatures->uFamily,
1465 pFeatures->uModel,
1466 pFeatures->uStepping);
1467
1468 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1469 if (pLeaf)
1470 pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff;
1471 else if (paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1472 pFeatures->cMaxPhysAddrWidth = 36;
1473 else
1474 pFeatures->cMaxPhysAddrWidth = 32;
1475
1476 /* Standard features. */
1477 pFeatures->fMsr = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_MSR);
1478 pFeatures->fApic = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_APIC);
1479 pFeatures->fX2Apic = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1480 pFeatures->fPse = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE);
1481 pFeatures->fPse36 = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1482 pFeatures->fPae = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PAE);
1483 pFeatures->fPat = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PAT);
1484 pFeatures->fFxSaveRstor = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1485 pFeatures->fSysEnter = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_SEP);
1486 pFeatures->fHypervisorPresent = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_HVP);
1487 pFeatures->fMonitorMWait = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1488
1489 /* MWAIT/MONITOR leaf. */
1490 PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1491 if (pMWaitLeaf)
1492 {
1493 pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1494 == (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1495 }
1496
1497 /* Extended features. */
1498 PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1499 if (pExtLeaf)
1500 {
1501 pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1502 pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1503 pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1504 pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1505 pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1506 }
1507
1508 if ( pExtLeaf
1509 && pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1510 {
1511 /* AMD features. */
1512 pFeatures->fMsr |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1513 pFeatures->fApic |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1514 pFeatures->fPse |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1515 pFeatures->fPse36 |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1516 pFeatures->fPae |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1517 pFeatures->fPat |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1518 pFeatures->fFxSaveRstor |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1519 }
1520
1521 /*
1522 * Quirks.
1523 */
1524 pFeatures->fLeakyFxSR = pExtLeaf
1525 && (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1526 && pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1527 && pFeatures->uFamily >= 6 /* K7 and up */;
1528 }
1529 else
1530 AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1531 return VINF_SUCCESS;
1532}
1533
1534
1535/*
1536 *
1537 * Init related code.
1538 * Init related code.
1539 * Init related code.
1540 *
1541 *
1542 */
1543#ifdef VBOX_IN_VMM
1544
1545
1546/**
1547 * Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1548 *
1549 * This ignores the fSubLeafMask.
1550 *
1551 * @returns Pointer to the matching leaf, or NULL if not found.
1552 * @param paLeaves The CPUID leaves to search. This is sorted.
1553 * @param cLeaves The number of leaves in the array.
1554 * @param uLeaf The leaf to locate.
1555 * @param uSubLeaf The subleaf to locate.
1556 */
1557static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1558{
1559 uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1560 PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1561 uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1562 if (iEnd)
1563 {
1564 uint32_t iBegin = 0;
1565 for (;;)
1566 {
1567 uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1568 uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1569 if (uNeedle < uCur)
1570 {
1571 if (i > iBegin)
1572 iEnd = i;
1573 else
1574 break;
1575 }
1576 else if (uNeedle > uCur)
1577 {
1578 if (i + 1 < iEnd)
1579 iBegin = i + 1;
1580 else
1581 break;
1582 }
1583 else
1584 return &paLeaves[i];
1585 }
1586 }
1587 return NULL;
1588}
1589
1590
1591/**
1592 * Loads MSR range overrides.
1593 *
1594 * This must be called before the MSR ranges are moved from the normal heap to
1595 * the hyper heap!
1596 *
1597 * @returns VBox status code (VMSetError called).
1598 * @param pVM Pointer to the cross context VM structure
1599 * @param pMsrNode The CFGM node with the MSR overrides.
1600 */
1601static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1602{
1603 for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1604 {
1605 /*
1606 * Assemble a valid MSR range.
1607 */
1608 CPUMMSRRANGE MsrRange;
1609 MsrRange.offCpumCpu = 0;
1610 MsrRange.fReserved = 0;
1611
1612 int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1613 if (RT_FAILURE(rc))
1614 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1615
1616 rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1617 if (RT_FAILURE(rc))
1618 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1619 MsrRange.szName, rc);
1620
1621 rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1622 if (RT_FAILURE(rc))
1623 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1624 MsrRange.szName, rc);
1625
1626 char szType[32];
1627 rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1628 if (RT_FAILURE(rc))
1629 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1630 MsrRange.szName, rc);
1631 if (!RTStrICmp(szType, "FixedValue"))
1632 {
1633 MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1634 MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1635
1636 rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1637 if (RT_FAILURE(rc))
1638 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1639 MsrRange.szName, rc);
1640
1641 rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1642 if (RT_FAILURE(rc))
1643 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1644 MsrRange.szName, rc);
1645
1646 rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1647 if (RT_FAILURE(rc))
1648 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1649 MsrRange.szName, rc);
1650 }
1651 else
1652 return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1653 "Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1654
1655 /*
1656 * Insert the range into the table (replaces/splits/shrinks existing
1657 * MSR ranges).
1658 */
1659 rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1660 &MsrRange);
1661 if (RT_FAILURE(rc))
1662 return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
1663 }
1664
1665 return VINF_SUCCESS;
1666}
1667
1668
1669/**
1670 * Loads CPUID leaf overrides.
1671 *
1672 * This must be called before the CPUID leaves are moved from the normal
1673 * heap to the hyper heap!
1674 *
1675 * @returns VBox status code (VMSetError called).
1676 * @param pVM Pointer to the cross context VM structure
1677 * @param pParentNode The CFGM node with the CPUID leaves.
1678 * @param pszLabel How to label the overrides we're loading.
1679 */
1680static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
1681{
1682 for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1683 {
1684 /*
1685 * Get the leaf and subleaf numbers.
1686 */
1687 char szName[128];
1688 int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
1689 if (RT_FAILURE(rc))
1690 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
1691
1692 /* The leaf number is either specified directly or thru the node name. */
1693 uint32_t uLeaf;
1694 rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
1695 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1696 {
1697 rc = RTStrToUInt32Full(szName, 16, &uLeaf);
1698 if (rc != VINF_SUCCESS)
1699 return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
1700 "Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
1701 }
1702 else if (RT_FAILURE(rc))
1703 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
1704 pszLabel, szName, rc);
1705
1706 uint32_t uSubLeaf;
1707 rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
1708 if (RT_FAILURE(rc))
1709 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
1710 pszLabel, szName, rc);
1711
1712 uint32_t fSubLeafMask;
1713 rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
1714 if (RT_FAILURE(rc))
1715 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
1716 pszLabel, szName, rc);
1717
1718 /*
1719 * Look up the specified leaf, since the output register values
1720 * defaults to any existing values. This allows overriding a single
1721 * register, without needing to know the other values.
1722 */
1723 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
1724 CPUMCPUIDLEAF Leaf;
1725 if (pLeaf)
1726 Leaf = *pLeaf;
1727 else
1728 RT_ZERO(Leaf);
1729 Leaf.uLeaf = uLeaf;
1730 Leaf.uSubLeaf = uSubLeaf;
1731 Leaf.fSubLeafMask = fSubLeafMask;
1732
1733 rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
1734 if (RT_FAILURE(rc))
1735 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
1736 pszLabel, szName, rc);
1737 rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
1738 if (RT_FAILURE(rc))
1739 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
1740 pszLabel, szName, rc);
1741 rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
1742 if (RT_FAILURE(rc))
1743 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
1744 pszLabel, szName, rc);
1745 rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
1746 if (RT_FAILURE(rc))
1747 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
1748 pszLabel, szName, rc);
1749
1750 /*
1751 * Insert the leaf into the table (replaces existing ones).
1752 */
1753 rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1754 &Leaf);
1755 if (RT_FAILURE(rc))
1756 return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
1757 }
1758
1759 return VINF_SUCCESS;
1760}
1761
1762
1763
1764/**
1765 * Fetches overrides for a CPUID leaf.
1766 *
1767 * @returns VBox status code.
1768 * @param pLeaf The leaf to load the overrides into.
1769 * @param pCfgNode The CFGM node containing the overrides
1770 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
1771 * @param iLeaf The CPUID leaf number.
1772 */
1773static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
1774{
1775 PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
1776 if (pLeafNode)
1777 {
1778 uint32_t u32;
1779 int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
1780 if (RT_SUCCESS(rc))
1781 pLeaf->uEax = u32;
1782 else
1783 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1784
1785 rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
1786 if (RT_SUCCESS(rc))
1787 pLeaf->uEbx = u32;
1788 else
1789 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1790
1791 rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
1792 if (RT_SUCCESS(rc))
1793 pLeaf->uEcx = u32;
1794 else
1795 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1796
1797 rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
1798 if (RT_SUCCESS(rc))
1799 pLeaf->uEdx = u32;
1800 else
1801 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1802
1803 }
1804 return VINF_SUCCESS;
1805}
1806
1807
1808/**
1809 * Load the overrides for a set of CPUID leaves.
1810 *
1811 * @returns VBox status code.
1812 * @param paLeaves The leaf array.
1813 * @param cLeaves The number of leaves.
1814 * @param uStart The start leaf number.
1815 * @param pCfgNode The CFGM node containing the overrides
1816 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
1817 */
1818static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
1819{
1820 for (uint32_t i = 0; i < cLeaves; i++)
1821 {
1822 int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
1823 if (RT_FAILURE(rc))
1824 return rc;
1825 }
1826
1827 return VINF_SUCCESS;
1828}
1829
1830/**
1831 * Init a set of host CPUID leaves.
1832 *
1833 * @returns VBox status code.
1834 * @param paLeaves The leaf array.
1835 * @param cLeaves The number of leaves.
1836 * @param uStart The start leaf number.
1837 * @param pCfgNode The /CPUM/HostCPUID/ node.
1838 */
1839static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
1840{
1841 /* Using the ECX variant for all of them can't hurt... */
1842 for (uint32_t i = 0; i < cLeaves; i++)
1843 ASMCpuIdExSlow(uStart + i, 0, 0, 0, &paLeaves[i].uEax, &paLeaves[i].uEbx, &paLeaves[i].uEcx, &paLeaves[i].uEdx);
1844
1845 /* Load CPUID leaf override; we currently don't care if the user
1846 specifies features the host CPU doesn't support. */
1847 return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
1848}
1849
1850
1851static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
1852{
1853 /*
1854 * Install the CPUID information.
1855 */
1856 int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
1857 MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
1858
1859 AssertLogRelRCReturn(rc, rc);
1860
1861
1862 pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
1863 pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
1864 Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
1865 Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
1866
1867 /*
1868 * Update the default CPUID leaf if necessary.
1869 */
1870 switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
1871 {
1872 case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
1873 case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
1874 {
1875 /* We don't use CPUID(0).eax here because of the NT hack that only
1876 changes that value without actually removing any leaves. */
1877 uint32_t i = 0;
1878 if ( pCpum->GuestInfo.cCpuIdLeaves > 0
1879 && pCpum->GuestInfo.paCpuIdLeavesR3[0].uEax <= UINT32_C(0xff))
1880 {
1881 while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
1882 && pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uEax <= UINT32_C(0xff))
1883 i++;
1884 pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
1885 pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
1886 pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
1887 pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
1888 }
1889 break;
1890 }
1891 default:
1892 break;
1893 }
1894
1895 /*
1896 * Explode the guest CPU features.
1897 */
1898 rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
1899 AssertLogRelRCReturn(rc, rc);
1900
1901 /*
1902 * Adjust the scalable bus frequency according to the CPUID information
1903 * we're now using.
1904 */
1905 if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
1906 pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
1907 ? UINT64_C(100000000) /* 100MHz */
1908 : UINT64_C(133333333); /* 133MHz */
1909
1910 /*
1911 * Populate the legacy arrays. Currently used for everything, later only
1912 * for patch manager.
1913 */
1914 struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
1915 {
1916 { pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
1917 { pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
1918 { pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
1919 };
1920 for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
1921 {
1922 uint32_t cLeft = aOldRanges[i].cCpuIds;
1923 uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
1924 PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
1925 while (cLeft-- > 0)
1926 {
1927 uLeaf--;
1928 pLegacyLeaf--;
1929
1930 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
1931 if (pLeaf)
1932 {
1933 pLegacyLeaf->uEax = pLeaf->uEax;
1934 pLegacyLeaf->uEbx = pLeaf->uEbx;
1935 pLegacyLeaf->uEcx = pLeaf->uEcx;
1936 pLegacyLeaf->uEdx = pLeaf->uEdx;
1937 }
1938 else
1939 *pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
1940 }
1941 }
1942
1943 return VINF_SUCCESS;
1944}
1945
1946
1947/**
1948 * CPUID Configuration (from CFGM).
1949 *
1950 * @remarks The members aren't document since we would only be duplicating the
1951 * \@cfgm entries in cpumR3CpuIdReadConfig.
1952 */
1953typedef struct CPUMCPUIDCONFIG
1954{
1955 bool fSyntheticCpu;
1956 bool fCmpXchg16b;
1957 bool fMonitor;
1958 bool fMWaitExtensions;
1959 bool fSse41;
1960 bool fSse42;
1961 bool fNt4LeafLimit;
1962 bool fInvariantTsc;
1963 uint32_t uMaxStdLeaf;
1964 uint32_t uMaxExtLeaf;
1965 uint32_t uMaxCentaurLeaf;
1966 uint32_t uMaxIntelFamilyModelStep;
1967 char szCpuName[128];
1968} CPUMCPUIDCONFIG;
1969/** Pointer to CPUID config (from CFGM). */
1970typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
1971
1972
1973/**
1974 * Insert hypervisor identification leaves.
1975 *
1976 * We only return minimal information, primarily ensuring that the
1977 * 0x40000000 function returns 0x40000001 and identifying ourselves.
1978 * Hypervisor-specific interface is supported through GIM which will
1979 * modify these leaves if required depending on the GIM provider.
1980 *
1981 * @returns VBox status code.
1982 * @param pCpum The CPUM instance data.
1983 * @param pConfig The CPUID configuration we've read from CFGM.
1984 */
1985static int cpumR3CpuIdPlantHypervisorLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1986{
1987 CPUMCPUIDLEAF NewLeaf;
1988 NewLeaf.uLeaf = UINT32_C(0x40000000);
1989 NewLeaf.uSubLeaf = 0;
1990 NewLeaf.fSubLeafMask = 0;
1991 NewLeaf.uEax = UINT32_C(0x40000001);
1992 NewLeaf.uEbx = 0x786f4256 /* 'VBox' */;
1993 NewLeaf.uEcx = 0x786f4256 /* 'VBox' */;
1994 NewLeaf.uEdx = 0x786f4256 /* 'VBox' */;
1995 NewLeaf.fFlags = 0;
1996 int rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
1997 AssertLogRelRCReturn(rc, rc);
1998
1999 NewLeaf.uLeaf = UINT32_C(0x40000001);
2000 NewLeaf.uEax = 0x656e6f6e; /* 'none' */
2001 NewLeaf.uEbx = 0;
2002 NewLeaf.uEcx = 0;
2003 NewLeaf.uEdx = 0;
2004 NewLeaf.fFlags = 0;
2005 rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
2006 AssertLogRelRCReturn(rc, rc);
2007
2008 return VINF_SUCCESS;
2009}
2010
2011
2012/**
2013 * Mini CPU selection support for making Mac OS X happy.
2014 *
2015 * Executes the /CPUM/MaxIntelFamilyModelStep config.
2016 *
2017 * @param pCpum The CPUM instance data.
2018 * @param pConfig The CPUID configuration we've read from CFGM.
2019 */
2020static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2021{
2022 if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2023 {
2024 PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2025 uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2026 ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2027 ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2028 0);
2029 uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2030 if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2031 {
2032 uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2033 uNew |= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2034 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2035 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2036 uNew |= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2037 if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2038 uNew |= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2039 LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2040 pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2041 pStdFeatureLeaf->uEax = uNew;
2042 }
2043 }
2044}
2045
2046
2047
2048/**
2049 * Limit it the number of entries, zapping the remainder.
2050 *
2051 * The limits are masking off stuff about power saving and similar, this
2052 * is perhaps a bit crudely done as there is probably some relatively harmless
2053 * info too in these leaves (like words about having a constant TSC).
2054 *
2055 * @param pCpum The CPUM instance data.
2056 * @param pConfig The CPUID configuration we've read from CFGM.
2057 */
2058static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2059{
2060 /*
2061 * Standard leaves.
2062 */
2063 uint32_t uSubLeaf = 0;
2064 PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2065 if (pCurLeaf)
2066 {
2067 uint32_t uLimit = pCurLeaf->uEax;
2068 if (uLimit <= UINT32_C(0x000fffff))
2069 {
2070 if (uLimit > pConfig->uMaxStdLeaf)
2071 {
2072 pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2073 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2074 uLimit + 1, UINT32_C(0x000fffff));
2075 }
2076
2077 /* NT4 hack, no zapping of extra leaves here. */
2078 if (pConfig->fNt4LeafLimit && uLimit > 3)
2079 pCurLeaf->uEax = uLimit = 3;
2080
2081 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2082 pCurLeaf->uEax = uLimit;
2083 }
2084 else
2085 {
2086 LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2087 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2088 UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2089 }
2090 }
2091
2092 /*
2093 * Extended leaves.
2094 */
2095 uSubLeaf = 0;
2096 pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2097 if (pCurLeaf)
2098 {
2099 uint32_t uLimit = pCurLeaf->uEax;
2100 if ( uLimit >= UINT32_C(0x80000000)
2101 && uLimit <= UINT32_C(0x800fffff))
2102 {
2103 if (uLimit > pConfig->uMaxExtLeaf)
2104 {
2105 pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2106 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2107 uLimit + 1, UINT32_C(0x800fffff));
2108 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2109 pCurLeaf->uEax = uLimit;
2110 }
2111 }
2112 else
2113 {
2114 LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2115 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2116 UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2117 }
2118 }
2119
2120 /*
2121 * Centaur leaves (VIA).
2122 */
2123 uSubLeaf = 0;
2124 pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2125 if (pCurLeaf)
2126 {
2127 uint32_t uLimit = pCurLeaf->uEax;
2128 if ( uLimit >= UINT32_C(0xc0000000)
2129 && uLimit <= UINT32_C(0xc00fffff))
2130 {
2131 if (uLimit > pConfig->uMaxCentaurLeaf)
2132 {
2133 pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2134 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2135 uLimit + 1, UINT32_C(0xcfffffff));
2136 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2137 pCurLeaf->uEax = uLimit;
2138 }
2139 }
2140 else
2141 {
2142 LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2143 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2144 UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2145 }
2146 }
2147}
2148
2149
2150/**
2151 * Clears a CPUID leaf and all sub-leaves (to zero).
2152 *
2153 * @param pCpum The CPUM instance data.
2154 * @param uLeaf The leaf to clear.
2155 */
2156static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2157{
2158 uint32_t uSubLeaf = 0;
2159 PCPUMCPUIDLEAF pCurLeaf;
2160 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2161 {
2162 pCurLeaf->uEax = 0;
2163 pCurLeaf->uEbx = 0;
2164 pCurLeaf->uEcx = 0;
2165 pCurLeaf->uEdx = 0;
2166 uSubLeaf++;
2167 }
2168}
2169
2170
2171/**
2172 * Sanitizes and adjust the CPUID leaves.
2173 *
2174 * Drop features that aren't virtualized (or virtualizable). Adjust information
2175 * and capabilities to fit the virtualized hardware. Remove information the
2176 * guest shouldn't have (because it's wrong in the virtual world or because it
2177 * gives away host details) or that we don't have documentation for and no idea
2178 * what means.
2179 *
2180 * @returns VBox status code.
2181 * @param pVM Pointer to the cross context VM structure (for cCpus).
2182 * @param pCpum The CPUM instance data.
2183 * @param pConfig The CPUID configuration we've read from CFGM.
2184 */
2185static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2186{
2187#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2188 if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2189 { \
2190 LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2191 (a_pLeafReg) &= ~(uint32_t)(fMask); \
2192 }
2193#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2194 if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2195 { \
2196 LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2197 (a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2198 }
2199 Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2200
2201 /* Cpuid 1:
2202 * EAX: CPU model, family and stepping.
2203 *
2204 * ECX + EDX: Supported features. Only report features we can support.
2205 * Note! When enabling new features the Synthetic CPU and Portable CPUID
2206 * options may require adjusting (i.e. stripping what was enabled).
2207 *
2208 * EBX: Branding, CLFLUSH line size, logical processors per package and
2209 * initial APIC ID.
2210 */
2211 PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2212 AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2213 AssertLogRelReturn(pStdFeatureLeaf->fSubLeafMask == 0, VERR_CPUM_IPE_2);
2214
2215 pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2216 | X86_CPUID_FEATURE_EDX_VME
2217 | X86_CPUID_FEATURE_EDX_DE
2218 | X86_CPUID_FEATURE_EDX_PSE
2219 | X86_CPUID_FEATURE_EDX_TSC
2220 | X86_CPUID_FEATURE_EDX_MSR
2221 //| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2222 | X86_CPUID_FEATURE_EDX_MCE
2223 | X86_CPUID_FEATURE_EDX_CX8
2224 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2225 //| RT_BIT_32(10) - not defined
2226 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2227 //| X86_CPUID_FEATURE_EDX_SEP
2228 | X86_CPUID_FEATURE_EDX_MTRR
2229 | X86_CPUID_FEATURE_EDX_PGE
2230 | X86_CPUID_FEATURE_EDX_MCA
2231 | X86_CPUID_FEATURE_EDX_CMOV
2232 | X86_CPUID_FEATURE_EDX_PAT /* 16 */
2233 | X86_CPUID_FEATURE_EDX_PSE36
2234 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2235 | X86_CPUID_FEATURE_EDX_CLFSH
2236 //| RT_BIT_32(20) - not defined
2237 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
2238 //| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2239 | X86_CPUID_FEATURE_EDX_MMX
2240 | X86_CPUID_FEATURE_EDX_FXSR
2241 | X86_CPUID_FEATURE_EDX_SSE
2242 | X86_CPUID_FEATURE_EDX_SSE2
2243 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2244 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading/cores - see below.
2245 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2246 //| RT_BIT_32(30) - not defined
2247 //| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2248 ;
2249 pStdFeatureLeaf->uEcx &= 0
2250 | X86_CPUID_FEATURE_ECX_SSE3
2251 //| X86_CPUID_FEATURE_ECX_PCLMUL - not implemented yet.
2252 //| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2253 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2254 | ((pConfig->fMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2255 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2256 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized yet.
2257 //| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2258 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2259 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2260 | X86_CPUID_FEATURE_ECX_SSSE3
2261 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2262 //| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2263 | (pConfig->fCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2264 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2265 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
2266 //| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2267 //| X86_CPUID_FEATURE_ECX_PCID - not implemented yet.
2268 //| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2269 | (pConfig->fSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2270 | (pConfig->fSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2271 //| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2272 //| X86_CPUID_FEATURE_ECX_MOVBE - not implemented yet.
2273 //| X86_CPUID_FEATURE_ECX_POPCNT
2274 //| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2275 //| X86_CPUID_FEATURE_ECX_AES - not implemented yet.
2276 //| X86_CPUID_FEATURE_ECX_XSAVE - not implemented yet.
2277 //| X86_CPUID_FEATURE_ECX_OSXSAVE - not implemented yet.
2278 //| X86_CPUID_FEATURE_ECX_AVX - not implemented yet.
2279 //| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2280 //| X86_CPUID_FEATURE_ECX_RDRAND - not implemented yet.
2281 //| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2282 ;
2283
2284 if (pCpum->u8PortableCpuIdLevel > 0)
2285 {
2286 PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2287 PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2288 PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2289 PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1);
2290 PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2);
2291 PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16);
2292 PORTABLE_DISABLE_FEATURE_BIT(2, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2293 PORTABLE_DISABLE_FEATURE_BIT(3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2294 PORTABLE_DISABLE_FEATURE_BIT(3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2295 PORTABLE_DISABLE_FEATURE_BIT(3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2296
2297 Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2298 | X86_CPUID_FEATURE_EDX_PSN
2299 | X86_CPUID_FEATURE_EDX_DS
2300 | X86_CPUID_FEATURE_EDX_ACPI
2301 | X86_CPUID_FEATURE_EDX_SS
2302 | X86_CPUID_FEATURE_EDX_TM
2303 | X86_CPUID_FEATURE_EDX_PBE
2304 )));
2305 Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_PCLMUL
2306 | X86_CPUID_FEATURE_ECX_DTES64
2307 | X86_CPUID_FEATURE_ECX_CPLDS
2308 | X86_CPUID_FEATURE_ECX_VMX
2309 | X86_CPUID_FEATURE_ECX_SMX
2310 | X86_CPUID_FEATURE_ECX_EST
2311 | X86_CPUID_FEATURE_ECX_TM2
2312 | X86_CPUID_FEATURE_ECX_CNTXID
2313 | X86_CPUID_FEATURE_ECX_FMA
2314 | X86_CPUID_FEATURE_ECX_CX16
2315 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2316 | X86_CPUID_FEATURE_ECX_PDCM
2317 | X86_CPUID_FEATURE_ECX_DCA
2318 | X86_CPUID_FEATURE_ECX_MOVBE
2319 | X86_CPUID_FEATURE_ECX_AES
2320 | X86_CPUID_FEATURE_ECX_POPCNT
2321 | X86_CPUID_FEATURE_ECX_XSAVE
2322 | X86_CPUID_FEATURE_ECX_OSXSAVE
2323 | X86_CPUID_FEATURE_ECX_AVX
2324 )));
2325 }
2326
2327 /* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2328 pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2329#ifdef VBOX_WITH_MULTI_CORE
2330 if (pVM->cCpus > 1)
2331 {
2332 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2333 core times the number of CPU cores per processor */
2334 pStdFeatureLeaf->uEbx |= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2335 pStdFeatureLeaf->uEdx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
2336 }
2337#endif
2338 pStdFeatureLeaf = NULL; /* Must refetch! */
2339
2340
2341 /* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2342 * AMD:
2343 * EAX: CPU model, family and stepping.
2344 *
2345 * ECX + EDX: Supported features. Only report features we can support.
2346 * Note! When enabling new features the Synthetic CPU and Portable CPUID
2347 * options may require adjusting (i.e. stripping what was enabled).
2348 * ASSUMES that this is ALWAYS the AMD defined feature set if present.
2349 *
2350 * EBX: Branding ID and package type (or reserved).
2351 *
2352 * Intel and probably most others:
2353 * EAX: 0
2354 * EBX: 0
2355 * ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2356 */
2357 PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2358 if (pExtFeatureLeaf)
2359 {
2360 AssertLogRelReturn(pExtFeatureLeaf->fSubLeafMask == 0, VERR_CPUM_IPE_2);
2361
2362 pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2363 | X86_CPUID_AMD_FEATURE_EDX_VME
2364 | X86_CPUID_AMD_FEATURE_EDX_DE
2365 | X86_CPUID_AMD_FEATURE_EDX_PSE
2366 | X86_CPUID_AMD_FEATURE_EDX_TSC
2367 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2368 //| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2369 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2370 | X86_CPUID_AMD_FEATURE_EDX_CX8
2371 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2372 //| RT_BIT_32(10) - reserved
2373 /* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2374 eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2375 //| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2376 | X86_CPUID_AMD_FEATURE_EDX_MTRR
2377 | X86_CPUID_AMD_FEATURE_EDX_PGE
2378 | X86_CPUID_AMD_FEATURE_EDX_MCA
2379 | X86_CPUID_AMD_FEATURE_EDX_CMOV
2380 | X86_CPUID_AMD_FEATURE_EDX_PAT
2381 | X86_CPUID_AMD_FEATURE_EDX_PSE36
2382 //| RT_BIT_32(18) - reserved
2383 //| RT_BIT_32(19) - reserved
2384 //| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2385 //| RT_BIT_32(21) - reserved
2386 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2387 | X86_CPUID_AMD_FEATURE_EDX_MMX
2388 | X86_CPUID_AMD_FEATURE_EDX_FXSR
2389 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
2390 //| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2391 | X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2392 //| RT_BIT_32(28) - reserved
2393 //| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2394 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2395 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
2396 ;
2397 pExtFeatureLeaf->uEcx &= 0
2398 //| X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2399 //| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2400 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
2401 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2402 /* Note: This could prevent teleporting from AMD to Intel CPUs! */
2403 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2404 //| X86_CPUID_AMD_FEATURE_ECX_ABM
2405 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
2406 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
2407 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
2408 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
2409 //| X86_CPUID_AMD_FEATURE_ECX_IBS
2410 //| X86_CPUID_AMD_FEATURE_ECX_SSE5
2411 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2412 //| X86_CPUID_AMD_FEATURE_ECX_WDT
2413 //| RT_BIT_32(14) - reserved
2414 //| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2415 //| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2416 //| RT_BIT_32(17) - reserved
2417 //| RT_BIT_32(18) - reserved
2418 //| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2419 //| RT_BIT_32(20) - reserved
2420 //| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2421 //| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2422 //| RT_BIT_32(23) - reserved
2423 //| RT_BIT_32(24) - reserved
2424 //| RT_BIT_32(25) - reserved
2425 //| RT_BIT_32(26) - reserved
2426 //| RT_BIT_32(27) - reserved
2427 //| RT_BIT_32(28) - reserved
2428 //| RT_BIT_32(29) - reserved
2429 //| RT_BIT_32(30) - reserved
2430 //| RT_BIT_32(31) - reserved
2431 ;
2432#ifdef VBOX_WITH_MULTI_CORE
2433 if ( pVM->cCpus > 1
2434 && pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2435 pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2436#endif
2437
2438 if (pCpum->u8PortableCpuIdLevel > 0)
2439 {
2440 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2441 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2442 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2443 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2444 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2445 PORTABLE_DISABLE_FEATURE_BIT(2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2446 PORTABLE_DISABLE_FEATURE_BIT(3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2447
2448 Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2449 | X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2450 | X86_CPUID_AMD_FEATURE_ECX_CR8L
2451 | X86_CPUID_AMD_FEATURE_ECX_ABM
2452 | X86_CPUID_AMD_FEATURE_ECX_SSE4A
2453 | X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
2454 | X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
2455 | X86_CPUID_AMD_FEATURE_ECX_OSVW
2456 | X86_CPUID_AMD_FEATURE_ECX_IBS
2457 | X86_CPUID_AMD_FEATURE_ECX_SSE5
2458 | X86_CPUID_AMD_FEATURE_ECX_SKINIT
2459 | X86_CPUID_AMD_FEATURE_ECX_WDT
2460 | UINT32_C(0xffffc000)
2461 )));
2462 Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2463 | X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2464 | RT_BIT(18)
2465 | RT_BIT(19)
2466 | RT_BIT(21)
2467 | X86_CPUID_AMD_FEATURE_EDX_AXMMX
2468 | X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2469 | RT_BIT(28)
2470 )));
2471 }
2472 }
2473 pExtFeatureLeaf = NULL; /* Must refetch! */
2474
2475
2476 /* Cpuid 2:
2477 * Intel: (Nondeterministic) Cache and TLB information
2478 * AMD: Reserved
2479 * VIA: Reserved
2480 * Safe to expose. Restrict the number of calls to 1 since we don't
2481 * implement this kind of subleaves (is there hardware that does??).
2482 */
2483 uint32_t uSubLeaf = 0;
2484 PCPUMCPUIDLEAF pCurLeaf;
2485 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2486 {
2487 if ((pCurLeaf->uEax & 0xff) > 1)
2488 {
2489 LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2490 pCurLeaf->uEax &= UINT32_C(0xffffff01);
2491 }
2492 uSubLeaf++;
2493 }
2494
2495 /* Cpuid 3:
2496 * Intel: EAX, EBX - reserved (transmeta uses these)
2497 * ECX, EDX - Processor Serial Number if available, otherwise reserved
2498 * AMD: Reserved
2499 * VIA: Reserved
2500 * Safe to expose
2501 */
2502 pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2503 if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
2504 {
2505 uSubLeaf = 0;
2506 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
2507 {
2508 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2509 if (pCpum->u8PortableCpuIdLevel > 0)
2510 pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2511 uSubLeaf++;
2512 }
2513 }
2514
2515 /* Cpuid 4 + ECX:
2516 * Intel: Deterministic Cache Parameters Leaf.
2517 * AMD: Reserved
2518 * VIA: Reserved
2519 * Safe to expose, except for EAX:
2520 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
2521 * Bits 31-26: Maximum number of processor cores in this physical package**
2522 * Note: These SMP values are constant regardless of ECX
2523 */
2524 uSubLeaf = 0;
2525 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
2526 {
2527 pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
2528#ifdef VBOX_WITH_MULTI_CORE
2529 if ( pVM->cCpus > 1
2530 && pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2531 {
2532 AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
2533 /* One logical processor with possibly multiple cores. */
2534 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
2535 pCurLeaf->uEax |= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
2536 }
2537#endif
2538 uSubLeaf++;
2539 }
2540
2541 /* Cpuid 5: Monitor/mwait Leaf
2542 * Intel: ECX, EDX - reserved
2543 * EAX, EBX - Smallest and largest monitor line size
2544 * AMD: EDX - reserved
2545 * EAX, EBX - Smallest and largest monitor line size
2546 * ECX - extensions (ignored for now)
2547 * VIA: Reserved
2548 * Safe to expose
2549 */
2550 uSubLeaf = 0;
2551 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
2552 {
2553 pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2554 if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
2555 pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2556
2557 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2558 if (pConfig->fMWaitExtensions)
2559 {
2560 pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
2561 /** @todo: for now we just expose host's MWAIT C-states, although conceptually
2562 it shall be part of our power management virtualization model */
2563#if 0
2564 /* MWAIT sub C-states */
2565 pCurLeaf->uEdx =
2566 (0 << 0) /* 0 in C0 */ |
2567 (2 << 4) /* 2 in C1 */ |
2568 (2 << 8) /* 2 in C2 */ |
2569 (2 << 12) /* 2 in C3 */ |
2570 (0 << 16) /* 0 in C4 */
2571 ;
2572#endif
2573 }
2574 else
2575 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2576 uSubLeaf++;
2577 }
2578
2579 /* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
2580 * Intel: Various stuff.
2581 * AMD: EAX, EBX, EDX - reserved.
2582 * ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
2583 * present. Same as intel.
2584 * VIA: ??
2585 *
2586 * We clear everything here for now.
2587 */
2588 cpumR3CpuIdZeroLeaf(pCpum, 6);
2589
2590 /* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
2591 * EAX: Number of sub leaves.
2592 * EBX+ECX+EDX: Feature flags
2593 *
2594 * We only have documentation for one sub-leaf, so clear all other (no need
2595 * to remove them as such, just set them to zero).
2596 *
2597 * Note! When enabling new features the Synthetic CPU and Portable CPUID
2598 * options may require adjusting (i.e. stripping what was enabled).
2599 */
2600 uSubLeaf = 0;
2601 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
2602 {
2603 switch (uSubLeaf)
2604 {
2605 case 0:
2606 {
2607 pCurLeaf->uEax = 0; /* Max ECX input is 0. */
2608 pCurLeaf->uEbx &= 0
2609 //| X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
2610 //| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
2611 //| RT_BIT(2) - reserved
2612 //| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
2613 //| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
2614 //| X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT(5)
2615 //| RT_BIT(6) - reserved
2616 //| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
2617 //| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
2618 //| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
2619 //| X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
2620 //| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
2621 //| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
2622 //| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT(13)
2623 //| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
2624 //| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
2625 //| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
2626 //| RT_BIT(17) - reserved
2627 //| X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT(18)
2628 //| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
2629 //| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
2630 //| RT_BIT(21) - reserved
2631 //| RT_BIT(22) - reserved
2632 //| X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT(23)
2633 //| RT_BIT(24) - reserved
2634 //| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
2635 //| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
2636 //| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
2637 //| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
2638 //| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
2639 //| RT_BIT(30) - reserved
2640 //| RT_BIT(31) - reserved
2641 ;
2642 pCurLeaf->uEcx &= 0
2643 //| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
2644 ;
2645 pCurLeaf->uEdx &= 0;
2646
2647 if (pCpum->u8PortableCpuIdLevel > 0)
2648 {
2649 PORTABLE_DISABLE_FEATURE_BIT(2, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
2650 }
2651 break;
2652 }
2653
2654 default:
2655 /* Invalid index, all values are zero. */
2656 pCurLeaf->uEax = 0;
2657 pCurLeaf->uEbx = 0;
2658 pCurLeaf->uEcx = 0;
2659 pCurLeaf->uEdx = 0;
2660 break;
2661 }
2662 uSubLeaf++;
2663 }
2664
2665 /* Cpuid 8: Marked as reserved by Intel and AMD.
2666 * We zero this since we don't know what it may have been used for.
2667 */
2668 cpumR3CpuIdZeroLeaf(pCpum, 8);
2669
2670 /* Cpuid 9: Direct Cache Access (DCA) Parameters
2671 * Intel: EAX - Value of PLATFORM_DCA_CAP bits.
2672 * EBX, ECX, EDX - reserved.
2673 * AMD: Reserved
2674 * VIA: ??
2675 *
2676 * We zero this.
2677 */
2678 cpumR3CpuIdZeroLeaf(pCpum, 9);
2679
2680 /* Cpuid 0xa: Architectural Performance Monitor Features
2681 * Intel: EAX - Value of PLATFORM_DCA_CAP bits.
2682 * EBX, ECX, EDX - reserved.
2683 * AMD: Reserved
2684 * VIA: ??
2685 *
2686 * We zero this, for now at least.
2687 */
2688 cpumR3CpuIdZeroLeaf(pCpum, 10);
2689
2690 /* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
2691 * Intel: EAX - APCI ID shift right for next level.
2692 * EBX - Factory configured cores/threads at this level.
2693 * ECX - Level number (same as input) and level type (1,2,0).
2694 * EDX - Extended initial APIC ID.
2695 * AMD: Reserved
2696 * VIA: ??
2697 */
2698 uSubLeaf = 0;
2699 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
2700 {
2701 if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
2702 {
2703 uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
2704 if (bLevelType == 1)
2705 {
2706 /* Thread level - we don't do threads at the moment. */
2707 pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
2708 pCurLeaf->uEbx = 1;
2709 }
2710 else if (bLevelType == 2)
2711 {
2712 /* Core level. */
2713 pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
2714#ifdef VBOX_WITH_MULTI_CORE
2715 while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
2716 pCurLeaf->uEax++;
2717#endif
2718 pCurLeaf->uEbx = pVM->cCpus;
2719 }
2720 else
2721 {
2722 AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
2723 pCurLeaf->uEax = 0;
2724 pCurLeaf->uEbx = 0;
2725 pCurLeaf->uEcx = 0;
2726 }
2727 pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) | (uSubLeaf & 0xff);
2728 pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
2729 }
2730 else
2731 {
2732 Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INTEL);
2733 pCurLeaf->uEax = 0;
2734 pCurLeaf->uEbx = 0;
2735 pCurLeaf->uEcx = 0;
2736 pCurLeaf->uEdx = 0;
2737 }
2738 uSubLeaf++;
2739 }
2740
2741 /* Cpuid 0xc: Marked as reserved by Intel and AMD.
2742 * We zero this since we don't know what it may have been used for.
2743 */
2744 cpumR3CpuIdZeroLeaf(pCpum, 12);
2745
2746 /* Cpuid 0xd + ECX: Processor Extended State Enumeration
2747 * ECX=0: EAX - Valid bits in XCR0[31:0].
2748 * EBX - Maximum state size as per current XCR0 value.
2749 * ECX - Maximum state size for all supported features.
2750 * EDX - Valid bits in XCR0[63:32].
2751 * ECX=1: EAX - Various X-features.
2752 * EBX - Maximum state size as per current XCR0|IA32_XSS value.
2753 * ECX - Valid bits in IA32_XSS[31:0].
2754 * EDX - Valid bits in IA32_XSS[63:32].
2755 * ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
2756 * if the bit invalid all four registers are set to zero.
2757 * EAX - The state size for this feature.
2758 * EBX - The state byte offset of this feature.
2759 * ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
2760 * EDX - Reserved, but is set to zero if invalid sub-leaf index.
2761 *
2762 * Clear them all as we don't currently implement extended CPU state.
2763 */
2764 uSubLeaf = 0;
2765 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf)) != NULL)
2766 {
2767 pCurLeaf->uEax = 0;
2768 pCurLeaf->uEbx = 0;
2769 pCurLeaf->uEcx = 0;
2770 pCurLeaf->uEdx = 0;
2771 uSubLeaf++;
2772 }
2773
2774 /* Cpuid 0xe: Marked as reserved by Intel and AMD.
2775 * We zero this since we don't know what it may have been used for.
2776 */
2777 cpumR3CpuIdZeroLeaf(pCpum, 14);
2778
2779 /* Cpuid 0xf + ECX: Platform qualifity of service monitoring (PQM).
2780 * We zero this as we don't currently virtualize PQM.
2781 */
2782 cpumR3CpuIdZeroLeaf(pCpum, 15);
2783
2784 /* Cpuid 0x10 + ECX: Platform qualifity of service enforcement (PQE).
2785 * We zero this as we don't currently virtualize PQE.
2786 */
2787 cpumR3CpuIdZeroLeaf(pCpum, 16);
2788
2789 /* Cpuid 0x11: Marked as reserved by Intel and AMD.
2790 * We zero this since we don't know what it may have been used for.
2791 */
2792 cpumR3CpuIdZeroLeaf(pCpum, 17);
2793
2794 /* Cpuid 0x12 + ECX: SGX resource enumeration.
2795 * We zero this as we don't currently virtualize this.
2796 */
2797 cpumR3CpuIdZeroLeaf(pCpum, 18);
2798
2799 /* Cpuid 0x13: Marked as reserved by Intel and AMD.
2800 * We zero this since we don't know what it may have been used for.
2801 */
2802 cpumR3CpuIdZeroLeaf(pCpum, 19);
2803
2804 /* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
2805 * We zero this as we don't currently virtualize this.
2806 */
2807 cpumR3CpuIdZeroLeaf(pCpum, 20);
2808
2809 /* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
2810 * Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
2811 * EAX - denominator (unsigned).
2812 * EBX - numerator (unsigned).
2813 * ECX, EDX - reserved.
2814 * AMD: Reserved / undefined / not implemented.
2815 * VIA: Reserved / undefined / not implemented.
2816 * We zero this as we don't currently virtualize this.
2817 */
2818 cpumR3CpuIdZeroLeaf(pCpum, 21);
2819
2820 /* Cpuid 0x16: Processor frequency info
2821 * Intel: EAX - Core base frequency in MHz.
2822 * EBX - Core maximum frequency in MHz.
2823 * ECX - Bus (reference) frequency in MHz.
2824 * EDX - Reserved.
2825 * AMD: Reserved / undefined / not implemented.
2826 * VIA: Reserved / undefined / not implemented.
2827 * We zero this as we don't currently virtualize this.
2828 */
2829 cpumR3CpuIdZeroLeaf(pCpum, 22);
2830
2831 /* Cpuid 0x17..0x10000000: Unknown.
2832 * We don't know these and what they mean, so remove them. */
2833 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2834 UINT32_C(0x00000017), UINT32_C(0x0fffffff));
2835
2836
2837 /* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
2838 * We remove all these as we're a hypervisor and must provide our own.
2839 */
2840 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2841 UINT32_C(0x40000000), UINT32_C(0x4fffffff));
2842
2843
2844 /* Cpuid 0x80000000 is harmless. */
2845
2846 /* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
2847
2848 /* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
2849
2850 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
2851 * Safe to pass on to the guest.
2852 *
2853 * AMD: 0x800000005 L1 cache information
2854 * 0x800000006 L2/L3 cache information
2855 * Intel: 0x800000005 reserved
2856 * 0x800000006 L2 cache information
2857 * VIA: 0x800000005 TLB and L1 cache information
2858 * 0x800000006 L2 cache information
2859 */
2860
2861 /* Cpuid 0x800000007: Advanced Power Management Information.
2862 * AMD: EAX: Processor feedback capabilities.
2863 * EBX: RAS capabilites.
2864 * ECX: Advanced power monitoring interface.
2865 * EDX: Enhanced power management capabilities.
2866 * Intel: EAX, EBX, ECX - reserved.
2867 * EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
2868 * VIA: Reserved
2869 * We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
2870 */
2871 uSubLeaf = 0;
2872 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
2873 {
2874 pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
2875 if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2876 {
2877 pCurLeaf->uEdx &= 0
2878 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
2879 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
2880 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
2881 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
2882 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
2883 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
2884 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
2885 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
2886#if 0 /*
2887 * We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
2888 * Linux kernels blindly assume that the AMD performance counters work
2889 * if this is set for 64 bits guests. (Can't really find a CPUID feature
2890 * bit for them though.)
2891 */
2892 /** @todo need to recheck this with new MSR emulation. */
2893 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
2894#endif
2895 //| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
2896 //| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
2897 //| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
2898 //| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
2899 | 0;
2900 }
2901 else
2902 pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2903 if (pConfig->fInvariantTsc)
2904 pCurLeaf->uEdx |= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2905 uSubLeaf++;
2906 }
2907
2908 /* Cpuid 0x80000008:
2909 * AMD: EBX, EDX - reserved
2910 * EAX: Virtual/Physical/Guest address Size
2911 * ECX: Number of cores + APICIdCoreIdSize
2912 * Intel: EAX: Virtual/Physical address Size
2913 * EBX, ECX, EDX - reserved
2914 * VIA: EAX: Virtual/Physical address Size
2915 * EBX, ECX, EDX - reserved
2916 *
2917 * We only expose the virtual+pysical address size to the guest atm.
2918 * On AMD we set the core count, but not the apic id stuff as we're
2919 * currently not doing the apic id assignments in a complatible manner.
2920 */
2921 uSubLeaf = 0;
2922 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
2923 {
2924 pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
2925 pCurLeaf->uEbx = 0; /* reserved */
2926 pCurLeaf->uEdx = 0; /* reserved */
2927
2928 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
2929 * Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
2930 pCurLeaf->uEcx = 0;
2931#ifdef VBOX_WITH_MULTI_CORE
2932 if ( pVM->cCpus > 1
2933 && pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2934 pCurLeaf->uEcx |= (pVM->cCpus - 1) & UINT32_C(0xff);
2935#endif
2936 uSubLeaf++;
2937 }
2938
2939 /* Cpuid 0x80000009: Reserved
2940 * We zero this since we don't know what it may have been used for.
2941 */
2942 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
2943
2944 /* Cpuid 0x8000000a: SVM Information
2945 * AMD: EAX - SVM revision.
2946 * EBX - Number of ASIDs.
2947 * ECX - Reserved.
2948 * EDX - SVM Feature identification.
2949 * We clear all as we currently does not virtualize SVM.
2950 */
2951 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2952
2953 /* Cpuid 0x8000000b thru 0x80000018: Reserved
2954 * We clear these as we don't know what purpose they might have. */
2955 for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
2956 cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
2957
2958 /* Cpuid 0x80000019: TLB configuration
2959 * Seems to be harmless, pass them thru as is. */
2960
2961 /* Cpuid 0x8000001a: Peformance optimization identifiers.
2962 * Strip anything we don't know what is or addresses feature we don't implement. */
2963 uSubLeaf = 0;
2964 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
2965 {
2966 pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
2967 | RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
2968 //| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
2969 ;
2970 pCurLeaf->uEbx = 0; /* reserved */
2971 pCurLeaf->uEcx = 0; /* reserved */
2972 pCurLeaf->uEdx = 0; /* reserved */
2973 uSubLeaf++;
2974 }
2975
2976 /* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
2977 * Clear this as we don't currently virtualize this feature. */
2978 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
2979
2980 /* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
2981 * Clear this as we don't currently virtualize this feature. */
2982 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
2983
2984 /* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
2985 * We need to sanitize the cores per cache (EAX[25:14]).
2986 *
2987 * This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
2988 * and EDX[2] are reserved here, and EAX[14:25] is documented having a
2989 * slightly different meaning.
2990 */
2991 uSubLeaf = 0;
2992 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
2993 {
2994#ifdef VBOX_WITH_MULTI_CORE
2995 uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
2996 if (cCores > pVM->cCpus)
2997 cCores = pVM->cCpus;
2998 pCurLeaf->uEax &= UINT32_C(0x00003fff);
2999 pCurLeaf->uEax |= ((cCores - 1) & 0xfff) << 14;
3000#else
3001 pCurLeaf->uEax &= UINT32_C(0x00003fff);
3002#endif
3003 uSubLeaf++;
3004 }
3005
3006 /* Cpuid 0x8000001e: Get APIC / unit / node information.
3007 * If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3008 * setup, we have one compute unit with all the cores in it. Single node.
3009 */
3010 uSubLeaf = 0;
3011 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3012 {
3013 pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3014 if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3015 {
3016#ifdef VBOX_WITH_MULTI_CORE
3017 pCurLeaf->uEbx = pVM->cCpus < 0x100
3018 ? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3019#else
3020 pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3021#endif
3022 pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3023 }
3024 else
3025 {
3026 Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3027 pCurLeaf->uEbx = 0; /* Reserved. */
3028 pCurLeaf->uEcx = 0; /* Reserved. */
3029 }
3030 pCurLeaf->uEdx = 0; /* Reserved. */
3031 uSubLeaf++;
3032 }
3033
3034 /* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3035 * We don't know these and what they mean, so remove them. */
3036 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3037 UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3038
3039 /* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3040 * Just pass it thru for now. */
3041
3042 /* Cpuid 0x8fffffff: Mystery hammer time leaf!
3043 * Just pass it thru for now. */
3044
3045 /* Cpuid 0xc0000000: Centaur stuff.
3046 * Harmless, pass it thru. */
3047
3048 /* Cpuid 0xc0000001: Centaur features.
3049 * VIA: EAX - Family, model, stepping.
3050 * EDX - Centaur extended feature flags. Nothing interesting, except may
3051 * FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3052 * EBX, ECX - reserved.
3053 * We keep EAX but strips the rest.
3054 */
3055 uSubLeaf = 0;
3056 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3057 {
3058 pCurLeaf->uEbx = 0;
3059 pCurLeaf->uEcx = 0;
3060 pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3061 uSubLeaf++;
3062 }
3063
3064 /* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3065 * We only have fixed stale values, but should be harmless. */
3066
3067 /* Cpuid 0xc0000003: Reserved.
3068 * We zero this since we don't know what it may have been used for.
3069 */
3070 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3071
3072 /* Cpuid 0xc0000004: Centaur Performance Info.
3073 * We only have fixed stale values, but should be harmless. */
3074
3075
3076 /* Cpuid 0xc0000005...0xcfffffff: Unknown.
3077 * We don't know these and what they mean, so remove them. */
3078 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3079 UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3080
3081 return VINF_SUCCESS;
3082#undef PORTABLE_DISABLE_FEATURE_BIT
3083#undef PORTABLE_CLEAR_BITS_WHEN
3084}
3085
3086
3087static int cpumR3CpuIdReadConfig(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg)
3088{
3089 int rc;
3090
3091 /** @cfgm{/CPUM/SyntheticCpu, boolean, false}
3092 * Enables the Synthetic CPU. The Vendor ID and Processor Name are
3093 * completely overridden by VirtualBox custom strings. Some
3094 * CPUID information is withheld, like the cache info.
3095 *
3096 * This is obsoleted by PortableCpuIdLevel. */
3097 rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pConfig->fSyntheticCpu, false);
3098 AssertRCReturn(rc, rc);
3099
3100 /** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3101 * When non-zero CPUID features that could cause portability issues will be
3102 * stripped. The higher the value the more features gets stripped. Higher
3103 * values should only be used when older CPUs are involved since it may
3104 * harm performance and maybe also cause problems with specific guests. */
3105 rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCpum->u8PortableCpuIdLevel, pConfig->fSyntheticCpu ? 1 : 0);
3106 AssertLogRelRCReturn(rc, rc);
3107
3108 /** @cfgm{/CPUM/GuestCpuName, string}
3109 * The name of the CPU we're to emulate. The default is the host CPU.
3110 * Note! CPUs other than "host" one is currently unsupported. */
3111 rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3112 AssertLogRelRCReturn(rc, rc);
3113
3114 /** @cfgm{/CPUM/CMPXCHG16B, boolean, false}
3115 * Expose CMPXCHG16B to the guest if supported by the host.
3116 */
3117 rc = CFGMR3QueryBoolDef(pCpumCfg, "CMPXCHG16B", &pConfig->fCmpXchg16b, false);
3118 AssertLogRelRCReturn(rc, rc);
3119
3120 /** @cfgm{/CPUM/MONITOR, boolean, true}
3121 * Expose MONITOR/MWAIT instructions to the guest.
3122 */
3123 rc = CFGMR3QueryBoolDef(pCpumCfg, "MONITOR", &pConfig->fMonitor, true);
3124 AssertLogRelRCReturn(rc, rc);
3125
3126 /** @cfgm{/CPUM/MWaitExtensions, boolean, false}
3127 * Expose MWAIT extended features to the guest. For now we expose just MWAIT
3128 * break on interrupt feature (bit 1).
3129 */
3130 rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &pConfig->fMWaitExtensions, false);
3131 AssertLogRelRCReturn(rc, rc);
3132
3133 /** @cfgm{/CPUM/SSE4.1, boolean, true}
3134 * Expose SSE4.1 to the guest if available.
3135 */
3136 rc = CFGMR3QueryBoolDef(pCpumCfg, "SSE4.1", &pConfig->fSse41, true);
3137 AssertLogRelRCReturn(rc, rc);
3138
3139 /** @cfgm{/CPUM/SSE4.2, boolean, true}
3140 * Expose SSE4.2 to the guest if available.
3141 */
3142 rc = CFGMR3QueryBoolDef(pCpumCfg, "SSE4.2", &pConfig->fSse42, true);
3143 AssertLogRelRCReturn(rc, rc);
3144
3145 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3146 * Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3147 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3148 * This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3149 */
3150 rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3151 AssertLogRelRCReturn(rc, rc);
3152
3153 /** @cfgm{/CPUM/InvariantTsc, boolean, complicated}
3154 * Set the invariant TSC flag in 0x80000007 if true, otherwas take default
3155 * action. By default the flag is passed thru as is from the host CPU, except
3156 * on AMD CPUs where it's suppressed to avoid trouble from linux assuming we
3157 * virtualize performance counters.
3158 */
3159 rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, false);
3160 AssertLogRelRCReturn(rc, rc);
3161
3162 /** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3163 * Restrict the reported CPU family+model+stepping of intel CPUs. This is
3164 * probably going to be a temporary hack, so don't depend on this.
3165 * The 1st byte of the value is the stepping, the 2nd byte value is the model
3166 * number and the 3rd byte value is the family, and the 4th value must be zero.
3167 */
3168 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3169 AssertLogRelRCReturn(rc, rc);
3170
3171 /** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3172 * The last standard leaf to keep. The actual last value that is stored in EAX
3173 * is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3174 * removed. (This works independently of and differently from NT4LeafLimit.)
3175 * The default is usually set to what we're able to reasonably sanitize.
3176 */
3177 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3178 AssertLogRelRCReturn(rc, rc);
3179
3180 /** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3181 * The last extended leaf to keep. The actual last value that is stored in EAX
3182 * is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3183 * leaf are removed. The default is set to what we're able to sanitize.
3184 */
3185 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3186 AssertLogRelRCReturn(rc, rc);
3187
3188 /** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3189 * The last extended leaf to keep. The actual last value that is stored in EAX
3190 * is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3191 * leaf are removed. The default is set to what we're able to sanitize.
3192 */
3193 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3194 AssertLogRelRCReturn(rc, rc);
3195
3196 return VINF_SUCCESS;
3197}
3198
3199
3200/**
3201 * Initializes the emulated CPU's CPUID & MSR information.
3202 *
3203 * @returns VBox status code.
3204 * @param pVM Pointer to the VM.
3205 */
3206int cpumR3InitCpuIdAndMsrs(PVM pVM)
3207{
3208 PCPUM pCpum = &pVM->cpum.s;
3209 PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
3210
3211 /*
3212 * Read the configuration.
3213 */
3214 CPUMCPUIDCONFIG Config;
3215 RT_ZERO(Config);
3216 int rc = cpumR3CpuIdReadConfig(pCpum, &Config, pCpumCfg);
3217 AssertRCReturn(rc, rc);
3218
3219 /*
3220 * Get the guest CPU data from the database and/or the host.
3221 *
3222 * The CPUID and MSRs are currently living on the regular heap to avoid
3223 * fragmenting the hyper heap (and because there isn't/wasn't any realloc
3224 * API for the hyper heap). This means special cleanup considerations.
3225 */
3226 rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
3227 if (RT_FAILURE(rc))
3228 return rc == VERR_CPUM_DB_CPU_NOT_FOUND
3229 ? VMSetError(pVM, rc, RT_SRC_POS,
3230 "Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
3231 : rc;
3232
3233 /** @cfgm{/CPUM/MSRs/[Name]/[First|Last|Type|Value|...],}
3234 * Overrides the guest MSRs.
3235 */
3236 rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
3237
3238 /** @cfgm{/CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
3239 * Overrides the CPUID leaf values (from the host CPU usually) used for
3240 * calculating the guest CPUID leaves. This can be used to preserve the CPUID
3241 * values when moving a VM to a different machine. Another use is restricting
3242 * (or extending) the feature set exposed to the guest. */
3243 if (RT_SUCCESS(rc))
3244 rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
3245
3246 if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
3247 rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
3248 "Found unsupported configuration node '/CPUM/CPUID/'. "
3249 "Please use IMachine::setCPUIDLeaf() instead.");
3250
3251 /*
3252 * Pre-explode the CPUID info.
3253 */
3254 if (RT_SUCCESS(rc))
3255 rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
3256
3257 /*
3258 * Sanitize the cpuid information passed on to the guest.
3259 */
3260 if (RT_SUCCESS(rc))
3261 {
3262 rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
3263 if (RT_SUCCESS(rc))
3264 {
3265 cpumR3CpuIdLimitLeaves(pCpum, &Config);
3266 cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
3267 }
3268 }
3269
3270 /*
3271 * Plant our own hypervisor CPUID leaves.
3272 */
3273 if (RT_SUCCESS(rc))
3274 rc = cpumR3CpuIdPlantHypervisorLeaves(pCpum, &Config);
3275
3276 /*
3277 * MSR fudging.
3278 */
3279 if (RT_SUCCESS(rc))
3280 {
3281 /** @cfgm{/CPUM/FudgeMSRs, boolean, true}
3282 * Fudges some common MSRs if not present in the selected CPU database entry.
3283 * This is for trying to keep VMs running when moved between different hosts
3284 * and different CPU vendors. */
3285 bool fEnable;
3286 rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
3287 if (RT_SUCCESS(rc) && fEnable)
3288 {
3289 rc = cpumR3MsrApplyFudge(pVM);
3290 AssertLogRelRC(rc);
3291 }
3292 }
3293 if (RT_SUCCESS(rc))
3294 {
3295 /*
3296 * Move the MSR and CPUID arrays over on the hypervisor heap, and explode
3297 * guest CPU features again.
3298 */
3299 void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
3300 int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
3301 pCpum->GuestInfo.cCpuIdLeaves);
3302 RTMemFree(pvFree);
3303
3304 pvFree = pCpum->GuestInfo.paMsrRangesR3;
3305 int rc2 = MMHyperDupMem(pVM, pvFree,
3306 sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
3307 MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
3308 RTMemFree(pvFree);
3309 AssertLogRelRCReturn(rc1, rc1);
3310 AssertLogRelRCReturn(rc2, rc2);
3311
3312 pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
3313 pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
3314 cpumR3MsrRegStats(pVM);
3315
3316
3317 /*
3318 * Some more configuration that we're applying at the end of everything
3319 * via the CPUMSetGuestCpuIdFeature API.
3320 */
3321
3322 /* Check if PAE was explicitely enabled by the user. */
3323 bool fEnable;
3324 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
3325 AssertRCReturn(rc, rc);
3326 if (fEnable)
3327 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3328
3329 /* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
3330 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
3331 AssertRCReturn(rc, rc);
3332 if (fEnable)
3333 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3334
3335 /* We don't enable the Hypervisor Present bit by default, but it may be needed by some guests. */
3336 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false);
3337 AssertRCReturn(rc, rc);
3338 if (fEnable)
3339 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
3340
3341 return VINF_SUCCESS;
3342 }
3343
3344 /*
3345 * Failed before switching to hyper heap.
3346 */
3347 RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
3348 pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
3349 RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3350 pCpum->GuestInfo.paMsrRangesR3 = NULL;
3351 return rc;
3352}
3353
3354
3355
3356/*
3357 *
3358 *
3359 * Saved state related code.
3360 * Saved state related code.
3361 * Saved state related code.
3362 *
3363 *
3364 */
3365
3366/**
3367 * Called both in pass 0 and the final pass.
3368 *
3369 * @param pVM Pointer to the VM.
3370 * @param pSSM The saved state handle.
3371 */
3372void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
3373{
3374 /*
3375 * Save all the CPU ID leaves.
3376 */
3377 SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
3378 SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
3379 SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
3380 sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
3381
3382 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
3383
3384 /*
3385 * Save a good portion of the raw CPU IDs as well as they may come in
3386 * handy when validating features for raw mode.
3387 */
3388 CPUMCPUID aRawStd[16];
3389 for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
3390 ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
3391 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
3392 SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
3393
3394 CPUMCPUID aRawExt[32];
3395 for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
3396 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
3397 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
3398 SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
3399}
3400
3401
3402static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
3403{
3404 uint32_t cCpuIds;
3405 int rc = SSMR3GetU32(pSSM, &cCpuIds);
3406 if (RT_SUCCESS(rc))
3407 {
3408 if (cCpuIds < 64)
3409 {
3410 for (uint32_t i = 0; i < cCpuIds; i++)
3411 {
3412 CPUMCPUID CpuId;
3413 rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
3414 if (RT_FAILURE(rc))
3415 break;
3416
3417 CPUMCPUIDLEAF NewLeaf;
3418 NewLeaf.uLeaf = uBase + i;
3419 NewLeaf.uSubLeaf = 0;
3420 NewLeaf.fSubLeafMask = 0;
3421 NewLeaf.uEax = CpuId.uEax;
3422 NewLeaf.uEbx = CpuId.uEbx;
3423 NewLeaf.uEcx = CpuId.uEcx;
3424 NewLeaf.uEdx = CpuId.uEdx;
3425 NewLeaf.fFlags = 0;
3426 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
3427 }
3428 }
3429 else
3430 rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3431 }
3432 if (RT_FAILURE(rc))
3433 {
3434 RTMemFree(*ppaLeaves);
3435 *ppaLeaves = NULL;
3436 *pcLeaves = 0;
3437 }
3438 return rc;
3439}
3440
3441
3442static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
3443{
3444 *ppaLeaves = NULL;
3445 *pcLeaves = 0;
3446
3447 int rc;
3448 if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
3449 {
3450 /*
3451 * The new format. Starts by declaring the leave size and count.
3452 */
3453 uint32_t cbLeaf;
3454 SSMR3GetU32(pSSM, &cbLeaf);
3455 uint32_t cLeaves;
3456 rc = SSMR3GetU32(pSSM, &cLeaves);
3457 if (RT_SUCCESS(rc))
3458 {
3459 if (cbLeaf == sizeof(**ppaLeaves))
3460 {
3461 if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
3462 {
3463 /*
3464 * Load the leaves one by one.
3465 */
3466 for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
3467 {
3468 CPUMCPUIDLEAF Leaf;
3469 rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
3470 if (RT_SUCCESS(rc))
3471 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3472 }
3473 }
3474 else
3475 rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
3476 "Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
3477 }
3478 else
3479 rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
3480 "CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
3481 }
3482 }
3483 else
3484 {
3485 /*
3486 * The old format with its three inflexible arrays.
3487 */
3488 rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
3489 if (RT_SUCCESS(rc))
3490 rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
3491 if (RT_SUCCESS(rc))
3492 rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
3493 if (RT_SUCCESS(rc))
3494 {
3495 /*
3496 * Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
3497 */
3498 PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(*ppaLeaves, *pcLeaves, 0, 0);
3499 if ( pLeaf
3500 && ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
3501 {
3502 CPUMCPUIDLEAF Leaf;
3503 Leaf.uLeaf = 4;
3504 Leaf.fSubLeafMask = UINT32_MAX;
3505 Leaf.uSubLeaf = 0;
3506 Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
3507 Leaf.uEcx = UINT32_C(63); /* sets - 1 */
3508 Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
3509 | (UINT32_C(0) << 12) /* phys line partitions - 1 */
3510 | UINT32_C(63); /* system coherency line size - 1 */
3511 Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
3512 | (UINT32_C(0) << 14) /* threads per cache - 1 */
3513 | (UINT32_C(1) << 5) /* cache level */
3514 | UINT32_C(1); /* cache type (data) */
3515 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3516 if (RT_SUCCESS(rc))
3517 {
3518 Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
3519 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3520 }
3521 if (RT_SUCCESS(rc))
3522 {
3523 Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
3524 Leaf.uEcx = 4095; /* sets - 1 */
3525 Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
3526 Leaf.uEbx |= UINT32_C(23) << 22;
3527 Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
3528 Leaf.uEax |= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
3529 Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
3530 Leaf.uEax |= UINT32_C(2) << 5;
3531 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3532 }
3533 }
3534 }
3535 }
3536 return rc;
3537}
3538
3539
3540/**
3541 * Loads the CPU ID leaves saved by pass 0, inner worker.
3542 *
3543 * @returns VBox status code.
3544 * @param pVM Pointer to the VM.
3545 * @param pSSM The saved state handle.
3546 * @param uVersion The format version.
3547 * @param paLeaves Guest CPUID leaves loaded from the state.
3548 * @param cLeaves The number of leaves in @a paLeaves.
3549 */
3550int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
3551{
3552 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
3553
3554 /*
3555 * Continue loading the state into stack buffers.
3556 */
3557 CPUMCPUID GuestDefCpuId;
3558 int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
3559 AssertRCReturn(rc, rc);
3560
3561 CPUMCPUID aRawStd[16];
3562 uint32_t cRawStd;
3563 rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
3564 if (cRawStd > RT_ELEMENTS(aRawStd))
3565 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3566 rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
3567 AssertRCReturn(rc, rc);
3568 for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
3569 ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
3570
3571 CPUMCPUID aRawExt[32];
3572 uint32_t cRawExt;
3573 rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
3574 if (cRawExt > RT_ELEMENTS(aRawExt))
3575 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3576 rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
3577 AssertRCReturn(rc, rc);
3578 for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
3579 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
3580
3581 /*
3582 * Get the raw CPU IDs for the current host.
3583 */
3584 CPUMCPUID aHostRawStd[16];
3585 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
3586 ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
3587
3588 CPUMCPUID aHostRawExt[32];
3589 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
3590 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0,
3591 &aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
3592
3593 /*
3594 * Get the host and guest overrides so we don't reject the state because
3595 * some feature was enabled thru these interfaces.
3596 * Note! We currently only need the feature leaves, so skip rest.
3597 */
3598 PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
3599 CPUMCPUID aHostOverrideStd[2];
3600 memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
3601 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
3602
3603 CPUMCPUID aHostOverrideExt[2];
3604 memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
3605 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
3606
3607 /*
3608 * This can be skipped.
3609 */
3610 bool fStrictCpuIdChecks;
3611 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
3612
3613 /*
3614 * Define a bunch of macros for simplifying the santizing/checking code below.
3615 */
3616 /* Generic expression + failure message. */
3617#define CPUID_CHECK_RET(expr, fmt) \
3618 do { \
3619 if (!(expr)) \
3620 { \
3621 char *pszMsg = RTStrAPrintf2 fmt; /* lack of variadic macros sucks */ \
3622 if (fStrictCpuIdChecks) \
3623 { \
3624 int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
3625 RTStrFree(pszMsg); \
3626 return rcCpuid; \
3627 } \
3628 LogRel(("CPUM: %s\n", pszMsg)); \
3629 RTStrFree(pszMsg); \
3630 } \
3631 } while (0)
3632#define CPUID_CHECK_WRN(expr, fmt) \
3633 do { \
3634 if (!(expr)) \
3635 LogRel(fmt); \
3636 } while (0)
3637
3638 /* For comparing two values and bitch if they differs. */
3639#define CPUID_CHECK2_RET(what, host, saved) \
3640 do { \
3641 if ((host) != (saved)) \
3642 { \
3643 if (fStrictCpuIdChecks) \
3644 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
3645 N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
3646 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
3647 } \
3648 } while (0)
3649#define CPUID_CHECK2_WRN(what, host, saved) \
3650 do { \
3651 if ((host) != (saved)) \
3652 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
3653 } while (0)
3654
3655 /* For checking raw cpu features (raw mode). */
3656#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
3657 do { \
3658 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
3659 { \
3660 if (fStrictCpuIdChecks) \
3661 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
3662 N_(#bit " mismatch: host=%d saved=%d"), \
3663 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
3664 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
3665 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
3666 } \
3667 } while (0)
3668#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
3669 do { \
3670 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
3671 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
3672 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
3673 } while (0)
3674#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
3675
3676 /* For checking guest features. */
3677#define CPUID_GST_FEATURE_RET(set, reg, bit) \
3678 do { \
3679 if ( (aGuestCpuId##set [1].reg & bit) \
3680 && !(aHostRaw##set [1].reg & bit) \
3681 && !(aHostOverride##set [1].reg & bit) \
3682 ) \
3683 { \
3684 if (fStrictCpuIdChecks) \
3685 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
3686 N_(#bit " is not supported by the host but has already exposed to the guest")); \
3687 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
3688 } \
3689 } while (0)
3690#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
3691 do { \
3692 if ( (aGuestCpuId##set [1].reg & bit) \
3693 && !(aHostRaw##set [1].reg & bit) \
3694 && !(aHostOverride##set [1].reg & bit) \
3695 ) \
3696 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
3697 } while (0)
3698#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
3699 do { \
3700 if ( (aGuestCpuId##set [1].reg & bit) \
3701 && !(aHostRaw##set [1].reg & bit) \
3702 && !(aHostOverride##set [1].reg & bit) \
3703 ) \
3704 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
3705 } while (0)
3706#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
3707
3708 /* For checking guest features if AMD guest CPU. */
3709#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
3710 do { \
3711 if ( (aGuestCpuId##set [1].reg & bit) \
3712 && fGuestAmd \
3713 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
3714 && !(aHostOverride##set [1].reg & bit) \
3715 ) \
3716 { \
3717 if (fStrictCpuIdChecks) \
3718 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
3719 N_(#bit " is not supported by the host but has already exposed to the guest")); \
3720 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
3721 } \
3722 } while (0)
3723#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
3724 do { \
3725 if ( (aGuestCpuId##set [1].reg & bit) \
3726 && fGuestAmd \
3727 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
3728 && !(aHostOverride##set [1].reg & bit) \
3729 ) \
3730 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
3731 } while (0)
3732#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
3733 do { \
3734 if ( (aGuestCpuId##set [1].reg & bit) \
3735 && fGuestAmd \
3736 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
3737 && !(aHostOverride##set [1].reg & bit) \
3738 ) \
3739 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
3740 } while (0)
3741#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
3742
3743 /* For checking AMD features which have a corresponding bit in the standard
3744 range. (Intel defines very few bits in the extended feature sets.) */
3745#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
3746 do { \
3747 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
3748 && !(fHostAmd \
3749 ? aHostRawExt[1].reg & (ExtBit) \
3750 : aHostRawStd[1].reg & (StdBit)) \
3751 && !(aHostOverrideExt[1].reg & (ExtBit)) \
3752 ) \
3753 { \
3754 if (fStrictCpuIdChecks) \
3755 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
3756 N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
3757 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
3758 } \
3759 } while (0)
3760#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
3761 do { \
3762 if ( (aGuestCpuId[1].reg & (ExtBit)) \
3763 && !(fHostAmd \
3764 ? aHostRawExt[1].reg & (ExtBit) \
3765 : aHostRawStd[1].reg & (StdBit)) \
3766 && !(aHostOverrideExt[1].reg & (ExtBit)) \
3767 ) \
3768 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
3769 } while (0)
3770#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
3771 do { \
3772 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
3773 && !(fHostAmd \
3774 ? aHostRawExt[1].reg & (ExtBit) \
3775 : aHostRawStd[1].reg & (StdBit)) \
3776 && !(aHostOverrideExt[1].reg & (ExtBit)) \
3777 ) \
3778 LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
3779 } while (0)
3780#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
3781
3782 /*
3783 * For raw-mode we'll require that the CPUs are very similar since we don't
3784 * intercept CPUID instructions for user mode applications.
3785 */
3786 if (!HMIsEnabled(pVM))
3787 {
3788 /* CPUID(0) */
3789 CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
3790 && aHostRawStd[0].uEcx == aRawStd[0].uEcx
3791 && aHostRawStd[0].uEdx == aRawStd[0].uEdx,
3792 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
3793 &aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
3794 &aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
3795 CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
3796 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
3797 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
3798
3799 bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
3800
3801 /* CPUID(1).eax */
3802 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
3803 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
3804 CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
3805
3806 /* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
3807 CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
3808 CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
3809
3810 /* CPUID(1).ecx */
3811 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
3812 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
3813 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
3814 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
3815 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
3816 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
3817 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
3818 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
3819 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
3820 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
3821 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
3822 CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /*reserved*/ );
3823 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
3824 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
3825 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
3826 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
3827 CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /*reserved*/);
3828 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
3829 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
3830 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
3831 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
3832 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
3833 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
3834 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
3835 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
3836 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
3837 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
3838 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
3839 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
3840 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
3841 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
3842 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
3843
3844 /* CPUID(1).edx */
3845 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
3846 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
3847 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
3848 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
3849 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
3850 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
3851 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
3852 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
3853 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
3854 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
3855 CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /*reserved*/);
3856 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
3857 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
3858 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
3859 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
3860 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
3861 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
3862 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
3863 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
3864 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
3865 CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /*reserved*/);
3866 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
3867 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
3868 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
3869 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
3870 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
3871 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
3872 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
3873 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
3874 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
3875 CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /*JMPE/IA64*/);
3876 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
3877
3878 /* CPUID(2) - config, mostly about caches. ignore. */
3879 /* CPUID(3) - processor serial number. ignore. */
3880 /* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
3881 /* CPUID(5) - mwait/monitor config. ignore. */
3882 /* CPUID(6) - power management. ignore. */
3883 /* CPUID(7) - ???. ignore. */
3884 /* CPUID(8) - ???. ignore. */
3885 /* CPUID(9) - DCA. ignore for now. */
3886 /* CPUID(a) - PeMo info. ignore for now. */
3887 /* CPUID(b) - topology info - takes ECX as input. ignore. */
3888
3889 /* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
3890 CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
3891 || aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
3892 ("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
3893 if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
3894 && aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
3895 {
3896 CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
3897 CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
3898 CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
3899 CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
3900 }
3901
3902 /* CPUID(0x80000000) - same as CPUID(0) except for eax.
3903 Note! Intel have/is marking many of the fields here as reserved. We
3904 will verify them as if it's an AMD CPU. */
3905 CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
3906 || !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
3907 (N_("Extended leaves was present on saved state host, but is missing on the current\n")));
3908 if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
3909 {
3910 CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
3911 && aHostRawExt[0].uEcx == aRawExt[0].uEcx
3912 && aHostRawExt[0].uEdx == aRawExt[0].uEdx,
3913 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
3914 &aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
3915 &aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
3916 CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
3917
3918 /* CPUID(0x80000001).eax - same as CPUID(0).eax. */
3919 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
3920 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
3921 CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
3922 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
3923 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
3924
3925 /* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
3926 CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
3927 CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
3928 CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
3929
3930 /* CPUID(0x80000001).ecx */
3931 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
3932 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
3933 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
3934 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
3935 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
3936 CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
3937 CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
3938 CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
3939 CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
3940 CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
3941 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
3942 CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
3943 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
3944 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
3945 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
3946 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
3947 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
3948 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
3949 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
3950 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
3951 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
3952 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
3953 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
3954 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
3955 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
3956 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
3957 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
3958 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
3959 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
3960 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
3961 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
3962 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
3963
3964 /* CPUID(0x80000001).edx */
3965 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
3966 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
3967 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
3968 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
3969 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
3970 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
3971 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
3972 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
3973 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
3974 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
3975 CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /*reserved*/);
3976 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
3977 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
3978 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
3979 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
3980 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
3981 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
3982 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
3983 CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /*reserved*/);
3984 CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /*reserved*/);
3985 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
3986 CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /*reserved*/);
3987 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
3988 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
3989 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
3990 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
3991 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
3992 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
3993 CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /*reserved*/);
3994 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
3995 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
3996 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
3997
3998 /** @todo verify the rest as well. */
3999 }
4000 }
4001
4002
4003
4004 /*
4005 * Verify that we can support the features already exposed to the guest on
4006 * this host.
4007 *
4008 * Most of the features we're emulating requires intercepting instruction
4009 * and doing it the slow way, so there is no need to warn when they aren't
4010 * present in the host CPU. Thus we use IGN instead of EMU on these.
4011 *
4012 * Trailing comments:
4013 * "EMU" - Possible to emulate, could be lots of work and very slow.
4014 * "EMU?" - Can this be emulated?
4015 */
4016 CPUMCPUID aGuestCpuIdStd[2];
4017 RT_ZERO(aGuestCpuIdStd);
4018 cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
4019
4020 /* CPUID(1).ecx */
4021 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
4022 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
4023 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
4024 CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4025 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
4026 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
4027 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
4028 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
4029 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
4030 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
4031 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
4032 CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /*reserved*/ );
4033 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
4034 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
4035 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
4036 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
4037 CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /*reserved*/);
4038 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4039 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
4040 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
4041 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
4042 CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4043 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
4044 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
4045 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4046 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
4047 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
4048 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
4049 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
4050 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4051 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4052 CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
4053
4054 /* CPUID(1).edx */
4055 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4056 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4057 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
4058 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4059 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4060 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4061 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4062 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4063 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4064 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4065 CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /*reserved*/);
4066 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4067 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4068 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4069 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4070 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4071 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4072 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4073 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4074 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
4075 CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /*reserved*/);
4076 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
4077 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
4078 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4079 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4080 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
4081 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
4082 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
4083 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
4084 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
4085 CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /*JMPE/IA64*/); // -> EMU
4086 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
4087
4088 /* CPUID(0x80000000). */
4089 CPUMCPUID aGuestCpuIdExt[2];
4090 RT_ZERO(aGuestCpuIdExt);
4091 if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
4092 {
4093 /** @todo deal with no 0x80000001 on the host. */
4094 bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
4095 bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
4096
4097 /* CPUID(0x80000001).ecx */
4098 CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
4099 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
4100 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
4101 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
4102 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
4103 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
4104 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
4105 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
4106 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
4107 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
4108 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
4109 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
4110 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
4111 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
4112 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4113 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4114 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4115 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4116 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4117 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4118 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4119 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4120 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4121 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4122 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4123 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4124 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4125 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4126 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4127 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4128 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4129 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4130
4131 /* CPUID(0x80000001).edx */
4132 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
4133 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
4134 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
4135 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
4136 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4137 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4138 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
4139 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
4140 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4141 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
4142 CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /*reserved*/);
4143 CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
4144 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
4145 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
4146 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
4147 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4148 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
4149 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
4150 CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /*reserved*/);
4151 CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /*reserved*/);
4152 CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4153 CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /*reserved*/);
4154 CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4155 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4156 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4157 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4158 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4159 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4160 CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /*reserved*/);
4161 CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4162 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4163 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4164 }
4165
4166#undef CPUID_CHECK_RET
4167#undef CPUID_CHECK_WRN
4168#undef CPUID_CHECK2_RET
4169#undef CPUID_CHECK2_WRN
4170#undef CPUID_RAW_FEATURE_RET
4171#undef CPUID_RAW_FEATURE_WRN
4172#undef CPUID_RAW_FEATURE_IGN
4173#undef CPUID_GST_FEATURE_RET
4174#undef CPUID_GST_FEATURE_WRN
4175#undef CPUID_GST_FEATURE_EMU
4176#undef CPUID_GST_FEATURE_IGN
4177#undef CPUID_GST_FEATURE2_RET
4178#undef CPUID_GST_FEATURE2_WRN
4179#undef CPUID_GST_FEATURE2_EMU
4180#undef CPUID_GST_FEATURE2_IGN
4181#undef CPUID_GST_AMD_FEATURE_RET
4182#undef CPUID_GST_AMD_FEATURE_WRN
4183#undef CPUID_GST_AMD_FEATURE_EMU
4184#undef CPUID_GST_AMD_FEATURE_IGN
4185
4186 /*
4187 * We're good, commit the CPU ID leaves.
4188 */
4189 MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
4190 pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
4191 pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
4192 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
4193 pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
4194 rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
4195 AssertLogRelRCReturn(rc, rc);
4196
4197 return VINF_SUCCESS;
4198}
4199
4200
4201/**
4202 * Loads the CPU ID leaves saved by pass 0.
4203 *
4204 * @returns VBox status code.
4205 * @param pVM Pointer to the VM.
4206 * @param pSSM The saved state handle.
4207 * @param uVersion The format version.
4208 */
4209int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
4210{
4211 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4212
4213 /*
4214 * Load the CPUID leaves array first and call worker to do the rest, just so
4215 * we can free the memory when we need to without ending up in column 1000.
4216 */
4217 PCPUMCPUIDLEAF paLeaves;
4218 uint32_t cLeaves;
4219 int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
4220 AssertRC(rc);
4221 if (RT_SUCCESS(rc))
4222 {
4223 rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
4224 RTMemFree(paLeaves);
4225 }
4226 return rc;
4227}
4228
4229
4230
4231
4232/*
4233 *
4234 *
4235 * CPUID Info Handler.
4236 * CPUID Info Handler.
4237 * CPUID Info Handler.
4238 *
4239 *
4240 */
4241
4242
4243
4244/**
4245 * Get L1 cache / TLS associativity.
4246 */
4247static const char *getCacheAss(unsigned u, char *pszBuf)
4248{
4249 if (u == 0)
4250 return "res0 ";
4251 if (u == 1)
4252 return "direct";
4253 if (u == 255)
4254 return "fully";
4255 if (u >= 256)
4256 return "???";
4257
4258 RTStrPrintf(pszBuf, 16, "%d way", u);
4259 return pszBuf;
4260}
4261
4262
4263/**
4264 * Get L2 cache associativity.
4265 */
4266const char *getL2CacheAss(unsigned u)
4267{
4268 switch (u)
4269 {
4270 case 0: return "off ";
4271 case 1: return "direct";
4272 case 2: return "2 way ";
4273 case 3: return "res3 ";
4274 case 4: return "4 way ";
4275 case 5: return "res5 ";
4276 case 6: return "8 way ";
4277 case 7: return "res7 ";
4278 case 8: return "16 way";
4279 case 9: return "res9 ";
4280 case 10: return "res10 ";
4281 case 11: return "res11 ";
4282 case 12: return "res12 ";
4283 case 13: return "res13 ";
4284 case 14: return "res14 ";
4285 case 15: return "fully ";
4286 default: return "????";
4287 }
4288}
4289
4290
4291/**
4292 * Display the guest CpuId leaves.
4293 *
4294 * @param pVM Pointer to the VM.
4295 * @param pHlp The info helper functions.
4296 * @param pszArgs "terse", "default" or "verbose".
4297 */
4298DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4299{
4300 /*
4301 * Parse the argument.
4302 */
4303 unsigned iVerbosity = 1;
4304 if (pszArgs)
4305 {
4306 pszArgs = RTStrStripL(pszArgs);
4307 if (!strcmp(pszArgs, "terse"))
4308 iVerbosity--;
4309 else if (!strcmp(pszArgs, "verbose"))
4310 iVerbosity++;
4311 }
4312
4313 /*
4314 * Start cracking.
4315 */
4316 CPUMCPUID Host;
4317 CPUMCPUID Guest;
4318 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax;
4319
4320 uint32_t cStdHstMax;
4321 uint32_t dummy;
4322 ASMCpuIdExSlow(0, 0, 0, 0, &cStdHstMax, &dummy, &dummy, &dummy);
4323
4324 unsigned cStdLstMax = RT_MAX(RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd), cStdHstMax);
4325
4326 pHlp->pfnPrintf(pHlp,
4327 " RAW Standard CPUIDs\n"
4328 " Function eax ebx ecx edx\n");
4329 for (unsigned i = 0; i <= cStdLstMax ; i++)
4330 {
4331 if (i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
4332 {
4333 Guest = pVM->cpum.s.aGuestCpuIdPatmStd[i];
4334 ASMCpuIdExSlow(i, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
4335
4336 pHlp->pfnPrintf(pHlp,
4337 "Gst: %08x %08x %08x %08x %08x%s\n"
4338 "Hst: %08x %08x %08x %08x\n",
4339 i, Guest.uEax, Guest.uEbx, Guest.uEcx, Guest.uEdx,
4340 i <= cStdMax ? "" : "*",
4341 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
4342 }
4343 else
4344 {
4345 ASMCpuIdExSlow(i, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
4346
4347 pHlp->pfnPrintf(pHlp,
4348 "Hst: %08x %08x %08x %08x %08x\n",
4349 i, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
4350 }
4351 }
4352
4353 /*
4354 * If verbose, decode it.
4355 */
4356 if (iVerbosity)
4357 {
4358 Guest = pVM->cpum.s.aGuestCpuIdPatmStd[0];
4359 pHlp->pfnPrintf(pHlp,
4360 "Name: %.04s%.04s%.04s\n"
4361 "Supports: 0-%x\n",
4362 &Guest.uEbx, &Guest.uEdx, &Guest.uEcx, Guest.uEax);
4363 }
4364
4365 /*
4366 * Get Features.
4367 */
4368 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
4369 pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
4370 pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
4371 if (cStdMax >= 1 && iVerbosity)
4372 {
4373 static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
4374
4375 Guest = pVM->cpum.s.aGuestCpuIdPatmStd[1];
4376 uint32_t uEAX = Guest.uEax;
4377
4378 pHlp->pfnPrintf(pHlp,
4379 "Family: %d \tExtended: %d \tEffective: %d\n"
4380 "Model: %d \tExtended: %d \tEffective: %d\n"
4381 "Stepping: %d\n"
4382 "Type: %d (%s)\n"
4383 "APIC ID: %#04x\n"
4384 "Logical CPUs: %d\n"
4385 "CLFLUSH Size: %d\n"
4386 "Brand ID: %#04x\n",
4387 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
4388 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
4389 ASMGetCpuStepping(uEAX),
4390 (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
4391 (Guest.uEbx >> 24) & 0xff,
4392 (Guest.uEbx >> 16) & 0xff,
4393 (Guest.uEbx >> 8) & 0xff,
4394 (Guest.uEbx >> 0) & 0xff);
4395 if (iVerbosity == 1)
4396 {
4397 uint32_t uEDX = Guest.uEdx;
4398 pHlp->pfnPrintf(pHlp, "Features EDX: ");
4399 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
4400 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
4401 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
4402 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
4403 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
4404 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
4405 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
4406 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
4407 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
4408 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
4409 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
4410 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
4411 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
4412 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
4413 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
4414 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
4415 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
4416 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
4417 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
4418 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
4419 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
4420 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
4421 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
4422 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
4423 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
4424 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
4425 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
4426 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
4427 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
4428 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
4429 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
4430 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
4431 pHlp->pfnPrintf(pHlp, "\n");
4432
4433 uint32_t uECX = Guest.uEcx;
4434 pHlp->pfnPrintf(pHlp, "Features ECX: ");
4435 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
4436 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
4437 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
4438 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
4439 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
4440 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
4441 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
4442 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
4443 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
4444 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
4445 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
4446 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
4447 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
4448 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
4449 if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
4450 if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
4451 if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
4452 if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
4453 if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
4454 if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
4455 if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
4456 if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
4457 if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
4458 if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
4459 if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
4460 if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
4461 if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
4462 if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
4463 if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
4464 if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " F16C");
4465 if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " RDRAND");
4466 if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " HVP");
4467 pHlp->pfnPrintf(pHlp, "\n");
4468 }
4469 else
4470 {
4471 ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
4472
4473 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.uEdx;
4474 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.uEcx;
4475 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.uEdx;
4476 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.uEcx;
4477
4478 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
4479 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
4480 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
4481 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
4482 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
4483 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
4484 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
4485 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
4486 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
4487 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
4488 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
4489 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
4490 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
4491 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
4492 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
4493 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
4494 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
4495 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
4496 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
4497 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
4498 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
4499 pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
4500 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
4501 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
4502 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
4503 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
4504 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
4505 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
4506 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
4507 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
4508 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
4509 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
4510 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
4511
4512 pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
4513 pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
4514 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
4515 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
4516 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
4517 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
4518 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
4519 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
4520 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
4521 pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
4522 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
4523 pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
4524 pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
4525 pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
4526 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
4527 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
4528 pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
4529 pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
4530 pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
4531 pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
4532 pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
4533 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
4534 pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
4535 pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
4536 pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
4537 pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
4538 pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
4539 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
4540 pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
4541 pHlp->pfnPrintf(pHlp, "16-bit floating point conversion instr = %d (%d)\n", EcxGuest.u1F16C, EcxHost.u1F16C);
4542 pHlp->pfnPrintf(pHlp, "RDRAND instruction = %d (%d)\n", EcxGuest.u1RDRAND, EcxHost.u1RDRAND);
4543 pHlp->pfnPrintf(pHlp, "Hypervisor Present (we're a guest) = %d (%d)\n", EcxGuest.u1HVP, EcxHost.u1HVP);
4544 }
4545 }
4546 if (cStdMax >= 2 && iVerbosity)
4547 {
4548 /** @todo */
4549 }
4550
4551 /*
4552 * Extended.
4553 * Implemented after AMD specs.
4554 */
4555 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdPatmExt[0].uEax & 0xffff;
4556
4557 pHlp->pfnPrintf(pHlp,
4558 "\n"
4559 " RAW Extended CPUIDs\n"
4560 " Function eax ebx ecx edx\n");
4561 bool fSupportsInvariantTsc = false;
4562 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt); i++)
4563 {
4564 Guest = pVM->cpum.s.aGuestCpuIdPatmExt[i];
4565 ASMCpuIdExSlow(0x80000000 | i, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
4566
4567 if ( i == 7
4568 && (Host.uEdx & X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR))
4569 {
4570 fSupportsInvariantTsc = true;
4571 }
4572 pHlp->pfnPrintf(pHlp,
4573 "Gst: %08x %08x %08x %08x %08x%s\n"
4574 "Hst: %08x %08x %08x %08x\n",
4575 0x80000000 | i, Guest.uEax, Guest.uEbx, Guest.uEcx, Guest.uEdx,
4576 i <= cExtMax ? "" : "*",
4577 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
4578 }
4579
4580 /*
4581 * Understandable output
4582 */
4583 if (iVerbosity)
4584 {
4585 Guest = pVM->cpum.s.aGuestCpuIdPatmExt[0];
4586 pHlp->pfnPrintf(pHlp,
4587 "Ext Name: %.4s%.4s%.4s\n"
4588 "Ext Supports: 0x80000000-%#010x\n",
4589 &Guest.uEbx, &Guest.uEdx, &Guest.uEcx, Guest.uEax);
4590 }
4591
4592 if (iVerbosity && cExtMax >= 1)
4593 {
4594 Guest = pVM->cpum.s.aGuestCpuIdPatmExt[1];
4595 uint32_t uEAX = Guest.uEax;
4596 pHlp->pfnPrintf(pHlp,
4597 "Family: %d \tExtended: %d \tEffective: %d\n"
4598 "Model: %d \tExtended: %d \tEffective: %d\n"
4599 "Stepping: %d\n"
4600 "Brand ID: %#05x\n",
4601 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
4602 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
4603 ASMGetCpuStepping(uEAX),
4604 Guest.uEbx & 0xfff);
4605
4606 if (iVerbosity == 1)
4607 {
4608 uint32_t uEDX = Guest.uEdx;
4609 pHlp->pfnPrintf(pHlp, "Features EDX: ");
4610 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
4611 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
4612 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
4613 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
4614 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
4615 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
4616 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
4617 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
4618 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
4619 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
4620 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
4621 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
4622 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
4623 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
4624 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
4625 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
4626 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
4627 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
4628 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
4629 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
4630 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
4631 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
4632 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
4633 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
4634 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
4635 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
4636 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
4637 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
4638 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
4639 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
4640 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
4641 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
4642 pHlp->pfnPrintf(pHlp, "\n");
4643
4644 uint32_t uECX = Guest.uEcx;
4645 pHlp->pfnPrintf(pHlp, "Features ECX: ");
4646 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
4647 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
4648 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
4649 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
4650 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
4651 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
4652 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
4653 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
4654 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
4655 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
4656 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
4657 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
4658 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
4659 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
4660 for (unsigned iBit = 5; iBit < 32; iBit++)
4661 if (uECX & RT_BIT(iBit))
4662 pHlp->pfnPrintf(pHlp, " %d", iBit);
4663 pHlp->pfnPrintf(pHlp, "\n");
4664 }
4665 else
4666 {
4667 ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
4668
4669 uint32_t uEdxGst = Guest.uEdx;
4670 uint32_t uEdxHst = Host.uEdx;
4671 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
4672 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
4673 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
4674 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
4675 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
4676 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
4677 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
4678 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
4679 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
4680 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
4681 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
4682 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
4683 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
4684 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
4685 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
4686 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
4687 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
4688 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
4689 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
4690 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
4691 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
4692 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
4693 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
4694 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
4695 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
4696 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
4697 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
4698 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
4699 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
4700 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
4701 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
4702 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
4703 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
4704
4705 uint32_t uEcxGst = Guest.uEcx;
4706 uint32_t uEcxHst = Host.uEcx;
4707 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
4708 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
4709 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
4710 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
4711 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
4712 pHlp->pfnPrintf(pHlp, "5 - Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
4713 pHlp->pfnPrintf(pHlp, "6 - SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
4714 pHlp->pfnPrintf(pHlp, "7 - Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
4715 pHlp->pfnPrintf(pHlp, "8 - PREFETCH and PREFETCHW instruction= %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
4716 pHlp->pfnPrintf(pHlp, "9 - OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
4717 pHlp->pfnPrintf(pHlp, "10 - Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
4718 pHlp->pfnPrintf(pHlp, "11 - SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
4719 pHlp->pfnPrintf(pHlp, "12 - SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
4720 pHlp->pfnPrintf(pHlp, "13 - Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
4721 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
4722 }
4723 }
4724
4725 if (iVerbosity && cExtMax >= 2)
4726 {
4727 char szString[4*4*3+1] = {0};
4728 uint32_t *pu32 = (uint32_t *)szString;
4729 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[2].uEax;
4730 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[2].uEbx;
4731 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[2].uEcx;
4732 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[2].uEdx;
4733 if (cExtMax >= 3)
4734 {
4735 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[3].uEax;
4736 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[3].uEbx;
4737 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[3].uEcx;
4738 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[3].uEdx;
4739 }
4740 if (cExtMax >= 4)
4741 {
4742 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[4].uEax;
4743 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[4].uEbx;
4744 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[4].uEcx;
4745 *pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[4].uEdx;
4746 }
4747 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
4748 }
4749
4750 if (iVerbosity && cExtMax >= 5)
4751 {
4752 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdPatmExt[5].uEax;
4753 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdPatmExt[5].uEbx;
4754 uint32_t uECX = pVM->cpum.s.aGuestCpuIdPatmExt[5].uEcx;
4755 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdPatmExt[5].uEdx;
4756 char sz1[32];
4757 char sz2[32];
4758
4759 pHlp->pfnPrintf(pHlp,
4760 "TLB 2/4M Instr/Uni: %s %3d entries\n"
4761 "TLB 2/4M Data: %s %3d entries\n",
4762 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
4763 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
4764 pHlp->pfnPrintf(pHlp,
4765 "TLB 4K Instr/Uni: %s %3d entries\n"
4766 "TLB 4K Data: %s %3d entries\n",
4767 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
4768 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
4769 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
4770 "L1 Instr Cache Lines Per Tag: %d\n"
4771 "L1 Instr Cache Associativity: %s\n"
4772 "L1 Instr Cache Size: %d KB\n",
4773 (uEDX >> 0) & 0xff,
4774 (uEDX >> 8) & 0xff,
4775 getCacheAss((uEDX >> 16) & 0xff, sz1),
4776 (uEDX >> 24) & 0xff);
4777 pHlp->pfnPrintf(pHlp,
4778 "L1 Data Cache Line Size: %d bytes\n"
4779 "L1 Data Cache Lines Per Tag: %d\n"
4780 "L1 Data Cache Associativity: %s\n"
4781 "L1 Data Cache Size: %d KB\n",
4782 (uECX >> 0) & 0xff,
4783 (uECX >> 8) & 0xff,
4784 getCacheAss((uECX >> 16) & 0xff, sz1),
4785 (uECX >> 24) & 0xff);
4786 }
4787
4788 if (iVerbosity && cExtMax >= 6)
4789 {
4790 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdPatmExt[6].uEax;
4791 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdPatmExt[6].uEbx;
4792 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdPatmExt[6].uEdx;
4793
4794 pHlp->pfnPrintf(pHlp,
4795 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
4796 "L2 TLB 2/4M Data: %s %4d entries\n",
4797 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
4798 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
4799 pHlp->pfnPrintf(pHlp,
4800 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
4801 "L2 TLB 4K Data: %s %4d entries\n",
4802 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
4803 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
4804 pHlp->pfnPrintf(pHlp,
4805 "L2 Cache Line Size: %d bytes\n"
4806 "L2 Cache Lines Per Tag: %d\n"
4807 "L2 Cache Associativity: %s\n"
4808 "L2 Cache Size: %d KB\n",
4809 (uEDX >> 0) & 0xff,
4810 (uEDX >> 8) & 0xf,
4811 getL2CacheAss((uEDX >> 12) & 0xf),
4812 (uEDX >> 16) & 0xffff);
4813 }
4814
4815 if (iVerbosity && cExtMax >= 7)
4816 {
4817 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdPatmExt[7].uEdx;
4818
4819 pHlp->pfnPrintf(pHlp, "Host Invariant-TSC support: %RTbool\n", fSupportsInvariantTsc);
4820 pHlp->pfnPrintf(pHlp, "APM Features: ");
4821 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
4822 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
4823 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
4824 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
4825 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
4826 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
4827 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " MC");
4828 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " HWPSTATE");
4829 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TscInvariant");
4830 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " CPB");
4831 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " EffFreqRO");
4832 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PFI");
4833 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PA");
4834 for (unsigned iBit = 13; iBit < 32; iBit++)
4835 if (uEDX & RT_BIT(iBit))
4836 pHlp->pfnPrintf(pHlp, " %d", iBit);
4837 pHlp->pfnPrintf(pHlp, "\n");
4838 }
4839
4840 if (iVerbosity && cExtMax >= 8)
4841 {
4842 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdPatmExt[8].uEax;
4843 uint32_t uECX = pVM->cpum.s.aGuestCpuIdPatmExt[8].uEcx;
4844
4845 pHlp->pfnPrintf(pHlp,
4846 "Physical Address Width: %d bits\n"
4847 "Virtual Address Width: %d bits\n"
4848 "Guest Physical Address Width: %d bits\n",
4849 (uEAX >> 0) & 0xff,
4850 (uEAX >> 8) & 0xff,
4851 (uEAX >> 16) & 0xff);
4852 pHlp->pfnPrintf(pHlp,
4853 "Physical Core Count: %d\n",
4854 (uECX >> 0) & 0xff);
4855 }
4856
4857
4858 /*
4859 * Hypervisor leaves.
4860 *
4861 * Unlike most of the other leaves reported, the guest hypervisor leaves
4862 * aren't a subset of the host CPUID bits.
4863 */
4864 RT_ZERO(Host);
4865 if (cStdHstMax >= 1)
4866 ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
4867 bool fHostHvp = RT_BOOL(Host.uEcx & X86_CPUID_FEATURE_ECX_HVP);
4868 bool fGuestHvp = false;
4869 if (cStdMax >= 1)
4870 {
4871 Guest = pVM->cpum.s.aGuestCpuIdPatmStd[1];
4872 fGuestHvp = RT_BOOL(Guest.uEcx & X86_CPUID_FEATURE_ECX_HVP);
4873 }
4874
4875 if ( fHostHvp
4876 || fGuestHvp)
4877 {
4878 uint32_t const uHyperLeaf = 0x40000000;
4879 pHlp->pfnPrintf(pHlp,
4880 "\n"
4881 " Hypervisor CPUIDs\n"
4882 " Function eax ebx ecx edx\n");
4883
4884 PCCPUMCPUIDLEAF pHyperLeafGst = NULL;
4885 if (fGuestHvp)
4886 {
4887 pHyperLeafGst = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
4888 uHyperLeaf, 0 /* uSubLeaf */);
4889 }
4890
4891 RT_ZERO(Host);
4892 if (fHostHvp)
4893 ASMCpuIdExSlow(uHyperLeaf, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
4894
4895 CPUMCPUIDLEAF GuestLeaf;
4896 uint32_t const cHyperGstMax = pHyperLeafGst ? pHyperLeafGst->uEax : 0;
4897 uint32_t const cHyperHstMax = Host.uEax;
4898 uint32_t const cHyperMax = RT_MAX(cHyperHstMax, cHyperGstMax);
4899 for (uint32_t i = uHyperLeaf; i <= cHyperMax; i++)
4900 {
4901 RT_ZERO(Host);
4902 RT_ZERO(GuestLeaf);
4903 if (i <= cHyperHstMax)
4904 ASMCpuIdExSlow(i, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
4905 CPUMR3CpuIdGetLeaf(pVM, &GuestLeaf, i, 0 /* uSubLeaf */);
4906 if (!fHostHvp)
4907 {
4908 pHlp->pfnPrintf(pHlp,
4909 "Gst: %08x %08x %08x %08x %08x\n",
4910 i, GuestLeaf.uEax, GuestLeaf.uEbx, GuestLeaf.uEcx, GuestLeaf.uEdx);
4911 }
4912 else
4913 {
4914 pHlp->pfnPrintf(pHlp,
4915 "Gst: %08x %08x %08x %08x %08x%s\n"
4916 "Hst: %08x %08x %08x %08x%s\n",
4917 i, GuestLeaf.uEax, GuestLeaf.uEbx, GuestLeaf.uEcx, GuestLeaf.uEdx,
4918 i <= cHyperGstMax ? "" : "*",
4919 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx, i <= cHyperHstMax ? "" : "*");
4920 }
4921 }
4922 }
4923
4924 /*
4925 * Centaur.
4926 */
4927 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdPatmCentaur[0].uEax & 0xffff;
4928
4929 pHlp->pfnPrintf(pHlp,
4930 "\n"
4931 " RAW Centaur CPUIDs\n"
4932 " Function eax ebx ecx edx\n");
4933 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur); i++)
4934 {
4935 Guest = pVM->cpum.s.aGuestCpuIdPatmCentaur[i];
4936 ASMCpuIdExSlow(0xc0000000 | i, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
4937
4938 pHlp->pfnPrintf(pHlp,
4939 "Gst: %08x %08x %08x %08x %08x%s\n"
4940 "Hst: %08x %08x %08x %08x\n",
4941 0xc0000000 | i, Guest.uEax, Guest.uEbx, Guest.uEcx, Guest.uEdx,
4942 i <= cCentaurMax ? "" : "*",
4943 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
4944 }
4945
4946 /*
4947 * Understandable output
4948 */
4949 if (iVerbosity)
4950 {
4951 Guest = pVM->cpum.s.aGuestCpuIdPatmCentaur[0];
4952 pHlp->pfnPrintf(pHlp,
4953 "Centaur Supports: 0xc0000000-%#010x\n",
4954 Guest.uEax);
4955 }
4956
4957 if (iVerbosity && cCentaurMax >= 1)
4958 {
4959 ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
4960 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdPatmCentaur[1].uEdx;
4961 uint32_t uEdxHst = Host.uEdx;
4962
4963 if (iVerbosity == 1)
4964 {
4965 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
4966 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
4967 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
4968 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
4969 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
4970 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
4971 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
4972 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
4973 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
4974 /* possibly indicating MM/HE and MM/HE-E on older chips... */
4975 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
4976 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
4977 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
4978 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
4979 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
4980 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
4981 for (unsigned iBit = 14; iBit < 32; iBit++)
4982 if (uEdxGst & RT_BIT(iBit))
4983 pHlp->pfnPrintf(pHlp, " %d", iBit);
4984 pHlp->pfnPrintf(pHlp, "\n");
4985 }
4986 else
4987 {
4988 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
4989 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
4990 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
4991 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
4992 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
4993 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
4994 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
4995 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
4996 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
4997 /* possibly indicating MM/HE and MM/HE-E on older chips... */
4998 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
4999 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
5000 pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
5001 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
5002 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
5003 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
5004 pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
5005 pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
5006 pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
5007 pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
5008 pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
5009 pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
5010 pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
5011 pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
5012 pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
5013 pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
5014 pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
5015 pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
5016 pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
5017 for (unsigned iBit = 27; iBit < 32; iBit++)
5018 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
5019 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
5020 pHlp->pfnPrintf(pHlp, "\n");
5021 }
5022 }
5023}
5024
5025
5026
5027
5028
5029/*
5030 *
5031 *
5032 * PATM interfaces.
5033 * PATM interfaces.
5034 * PATM interfaces.
5035 *
5036 *
5037 */
5038
5039
5040# if defined(VBOX_WITH_RAW_MODE) || defined(DOXYGEN_RUNNING)
5041/** @name Patchmanager CPUID legacy table APIs
5042 * @{
5043 */
5044
5045/**
5046 * Gets a pointer to the default CPUID leaf.
5047 *
5048 * @returns Raw-mode pointer to the default CPUID leaf (read-only).
5049 * @param pVM Pointer to the VM.
5050 * @remark Intended for PATM only.
5051 */
5052VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
5053{
5054 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
5055}
5056
5057
5058/**
5059 * Gets a pointer to the CPUID leaf array.
5060 *
5061 * @returns Raw-mode pointer to the CPUID leaf array.
5062 * @param pVM Pointer to the VM.
5063 * @remark Intended for PATM only.
5064 */
5065VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUIDLEAF)) CPUMR3GetGuestCpuIdPatmArrayRCPtr(PVM pVM)
5066{
5067 Assert(MMHyperRCToR3(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesRC) == pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5068 return pVM->cpum.s.GuestInfo.paCpuIdLeavesRC;
5069}
5070
5071
5072/**
5073 * Gets a pointer to the CPUID leaf array.
5074 *
5075 * @returns Raw-mode pointer to the end of CPUID leaf array (exclusive).
5076 * @param pVM Pointer to the VM.
5077 * @remark Intended for PATM only.
5078 */
5079VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUIDLEAF)) CPUMR3GetGuestCpuIdPatmArrayEndRCPtr(PVM pVM)
5080{
5081 Assert(MMHyperRCToR3(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesRC) == pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5082 return pVM->cpum.s.GuestInfo.paCpuIdLeavesRC
5083 + pVM->cpum.s.GuestInfo.cCpuIdLeaves * sizeof(CPUMCPUIDLEAF);
5084}
5085
5086
5087/**
5088 * Gets the unknown CPUID leaf method.
5089 *
5090 * @returns Unknown CPUID leaf method.
5091 * @param pVM Pointer to the VM.
5092 * @remark Intended for PATM only.
5093 */
5094VMMR3_INT_DECL(CPUMUNKNOWNCPUID) CPUMR3GetGuestCpuIdPatmUnknownLeafMethod(PVM pVM)
5095{
5096 return pVM->cpum.s.GuestInfo.enmUnknownCpuIdMethod;
5097}
5098
5099
5100
5101/**
5102 * Gets a number of standard CPUID leaves (PATM only).
5103 *
5104 * @returns Number of leaves.
5105 * @param pVM Pointer to the VM.
5106 * @remark Intended for PATM - legacy, don't use in new code.
5107 */
5108VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
5109{
5110 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
5111}
5112
5113
5114/**
5115 * Gets a number of extended CPUID leaves (PATM only).
5116 *
5117 * @returns Number of leaves.
5118 * @param pVM Pointer to the VM.
5119 * @remark Intended for PATM - legacy, don't use in new code.
5120 */
5121VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
5122{
5123 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
5124}
5125
5126
5127/**
5128 * Gets a number of centaur CPUID leaves.
5129 *
5130 * @returns Number of leaves.
5131 * @param pVM Pointer to the VM.
5132 * @remark Intended for PATM - legacy, don't use in new code.
5133 */
5134VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
5135{
5136 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
5137}
5138
5139
5140/**
5141 * Gets a pointer to the array of standard CPUID leaves.
5142 *
5143 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
5144 *
5145 * @returns Raw-mode pointer to the standard CPUID leaves (read-only).
5146 * @param pVM Pointer to the VM.
5147 * @remark Intended for PATM - legacy, don't use in new code.
5148 */
5149VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
5150{
5151 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
5152}
5153
5154
5155/**
5156 * Gets a pointer to the array of extended CPUID leaves.
5157 *
5158 * CPUMGetGuestCpuIdExtMax() give the size of the array.
5159 *
5160 * @returns Raw-mode pointer to the extended CPUID leaves (read-only).
5161 * @param pVM Pointer to the VM.
5162 * @remark Intended for PATM - legacy, don't use in new code.
5163 */
5164VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
5165{
5166 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
5167}
5168
5169
5170/**
5171 * Gets a pointer to the array of centaur CPUID leaves.
5172 *
5173 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
5174 *
5175 * @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
5176 * @param pVM Pointer to the VM.
5177 * @remark Intended for PATM - legacy, don't use in new code.
5178 */
5179VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
5180{
5181 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
5182}
5183
5184/** @} */
5185# endif /* VBOX_WITH_RAW_MODE || DOXYGEN_RUNNING */
5186
5187#endif /* VBOX_IN_VMM */
5188
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