CPUMR3CpuId.cpp@ 54799

Last change on this file since 54799 was 54799, checked in by vboxsync, 10 years ago
CPUM: Fixed two problems with the CPUID code. cLeaves wasn't updated in cpumR3CpuIdInstallAndExplodeLeaves leading to garbage entries at the end of the array. And when the CPUID insertion code had a bug when inserting subleafs that triggered when doing the cache leaf (4) fake up during old saved state loading.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 237.8 KB

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1	/* $Id: CPUMR3CpuId.cpp 54799 2015-03-16 21:23:03Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_CPUM
22	#include <VBox/vmm/cpum.h>
23	#include <VBox/vmm/dbgf.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/vmm/ssm.h>
26	#include "CPUMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/vmm/mm.h>
29
30	#include <VBox/err.h>
31	#include <iprt/asm-amd64-x86.h>
32	#include <iprt/ctype.h>
33	#include <iprt/mem.h>
34	#include <iprt/string.h>
35
36
37	/*******************************************************************************
38	* Defined Constants And Macros *
39	*******************************************************************************/
40	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
41	#define CPUM_CPUID_MAX_LEAVES 2048
42
43
44	/*******************************************************************************
45	* Global Variables *
46	*******************************************************************************/
47	/**
48	* The intel pentium family.
49	*/
50	static const CPUMMICROARCH g_aenmIntelFamily06[] =
51	{
52	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
53	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
54	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
55	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
56	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
57	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
58	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
59	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
60	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
61	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
62	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
63	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
64	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
65	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
66	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
67	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
68	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
69	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
70	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
71	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
72	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
73	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
74	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
75	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
76	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
79	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
81	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
82	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
83	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
84	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
86	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
88	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
89	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
90	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
91	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
92	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
95	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
97	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
98	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
99	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
100	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
102	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
104	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
105	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
106	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
107	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
108	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
111	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
113	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
114	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
115	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
116	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
118	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
120	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
121	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
122	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [71(0x47)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
127	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Unknown,
129	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
130	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Unknown,
131	/* [79(0x4f)] = */ kCpumMicroarch_Intel_Unknown,
132	};
133
134
135
136	/**
137	* Figures out the (sub-)micro architecture given a bit of CPUID info.
138	*
139	* @returns Micro architecture.
140	* @param enmVendor The CPU vendor .
141	* @param bFamily The CPU family.
142	* @param bModel The CPU model.
143	* @param bStepping The CPU stepping.
144	*/
145	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
146	uint8_t bModel, uint8_t bStepping)
147	{
148	if (enmVendor == CPUMCPUVENDOR_AMD)
149	{
150	switch (bFamily)
151	{
152	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
153	case 0x03: return kCpumMicroarch_AMD_Am386;
154	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
155	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
156	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
157	case 0x06:
158	switch (bModel)
159	{
160	case 0: kCpumMicroarch_AMD_K7_Palomino;
161	case 1: kCpumMicroarch_AMD_K7_Palomino;
162	case 2: kCpumMicroarch_AMD_K7_Palomino;
163	case 3: kCpumMicroarch_AMD_K7_Spitfire;
164	case 4: kCpumMicroarch_AMD_K7_Thunderbird;
165	case 6: kCpumMicroarch_AMD_K7_Palomino;
166	case 7: kCpumMicroarch_AMD_K7_Morgan;
167	case 8: kCpumMicroarch_AMD_K7_Thoroughbred;
168	case 10: kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
169	}
170	return kCpumMicroarch_AMD_K7_Unknown;
171	case 0x0f:
172	/*
173	* This family is a friggin mess. Trying my best to make some
174	* sense out of it. Too much happened in the 0x0f family to
175	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
176	*
177	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
178	* cpu-world.com, and other places:
179	* - 130nm:
180	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
181	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
182	* - Newcastle: FC0/DH-CG (errum #180: FE0/DH-CG), FF0/DH-CG
183	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
184	* - Odessa: FC0/DH-CG (errum #180: FE0/DH-CG)
185	* - Paris: FF0/DH-CG, FC0/DH-CG (errum #180: FE0/DH-CG),
186	* - 90nm:
187	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
188	* - Oakville: 10FC0/DH-D0.
189	* - Georgetown: 10FC0/DH-D0.
190	* - Sonora: 10FC0/DH-D0.
191	* - Venus: 20F71/SH-E4
192	* - Troy: 20F51/SH-E4
193	* - Athens: 20F51/SH-E4
194	* - San Diego: 20F71/SH-E4.
195	* - Lancaster: 20F42/SH-E5
196	* - Newark: 20F42/SH-E5.
197	* - Albany: 20FC2/DH-E6.
198	* - Roma: 20FC2/DH-E6.
199	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
200	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
201	* - 90nm introducing Dual core:
202	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
203	* - Italy: 20F10/JH-E1, 20F12/JH-E6
204	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
205	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
206	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
207	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
208	* - Santa Ana: 40F32/JH-F2, /-F3
209	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
210	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
211	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
212	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
213	* - Keene: 40FC2/DH-F2.
214	* - Richmond: 40FC2/DH-F2
215	* - Taylor: 40F82/BH-F2
216	* - Trinidad: 40F82/BH-F2
217	*
218	* - 65nm:
219	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
220	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
221	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
222	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
223	* - Sherman: /-G1, 70FC2/DH-G2.
224	* - Huron: 70FF2/DH-G2.
225	*/
226	if (bModel < 0x10)
227	return kCpumMicroarch_AMD_K8_130nm;
228	if (bModel >= 0x60 && bModel < 0x80)
229	return kCpumMicroarch_AMD_K8_65nm;
230	if (bModel >= 0x40)
231	return kCpumMicroarch_AMD_K8_90nm_AMDV;
232	switch (bModel)
233	{
234	case 0x21:
235	case 0x23:
236	case 0x2b:
237	case 0x2f:
238	case 0x37:
239	case 0x3f:
240	return kCpumMicroarch_AMD_K8_90nm_DualCore;
241	}
242	return kCpumMicroarch_AMD_K8_90nm;
243	case 0x10:
244	return kCpumMicroarch_AMD_K10;
245	case 0x11:
246	return kCpumMicroarch_AMD_K10_Lion;
247	case 0x12:
248	return kCpumMicroarch_AMD_K10_Llano;
249	case 0x14:
250	return kCpumMicroarch_AMD_Bobcat;
251	case 0x15:
252	switch (bModel)
253	{
254	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
255	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
256	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
257	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
258	case 0x11: /* ?? */
259	case 0x12: /* ?? */
260	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
261	}
262	return kCpumMicroarch_AMD_15h_Unknown;
263	case 0x16:
264	return kCpumMicroarch_AMD_Jaguar;
265
266	}
267	return kCpumMicroarch_AMD_Unknown;
268	}
269
270	if (enmVendor == CPUMCPUVENDOR_INTEL)
271	{
272	switch (bFamily)
273	{
274	case 3:
275	return kCpumMicroarch_Intel_80386;
276	case 4:
277	return kCpumMicroarch_Intel_80486;
278	case 5:
279	return kCpumMicroarch_Intel_P5;
280	case 6:
281	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
282	return g_aenmIntelFamily06[bModel];
283	return kCpumMicroarch_Intel_Atom_Unknown;
284	case 15:
285	switch (bModel)
286	{
287	case 0: return kCpumMicroarch_Intel_NB_Willamette;
288	case 1: return kCpumMicroarch_Intel_NB_Willamette;
289	case 2: return kCpumMicroarch_Intel_NB_Northwood;
290	case 3: return kCpumMicroarch_Intel_NB_Prescott;
291	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
292	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
293	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
294	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
295	default: return kCpumMicroarch_Intel_NB_Unknown;
296	}
297	break;
298	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
299	case 1:
300	return kCpumMicroarch_Intel_8086;
301	case 2:
302	return kCpumMicroarch_Intel_80286;
303	}
304	return kCpumMicroarch_Intel_Unknown;
305	}
306
307	if (enmVendor == CPUMCPUVENDOR_VIA)
308	{
309	switch (bFamily)
310	{
311	case 5:
312	switch (bModel)
313	{
314	case 1: return kCpumMicroarch_Centaur_C6;
315	case 4: return kCpumMicroarch_Centaur_C6;
316	case 8: return kCpumMicroarch_Centaur_C2;
317	case 9: return kCpumMicroarch_Centaur_C3;
318	}
319	break;
320
321	case 6:
322	switch (bModel)
323	{
324	case 5: return kCpumMicroarch_VIA_C3_M2;
325	case 6: return kCpumMicroarch_VIA_C3_C5A;
326	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
327	case 8: return kCpumMicroarch_VIA_C3_C5N;
328	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
329	case 10: return kCpumMicroarch_VIA_C7_C5J;
330	case 15: return kCpumMicroarch_VIA_Isaiah;
331	}
332	break;
333	}
334	return kCpumMicroarch_VIA_Unknown;
335	}
336
337	if (enmVendor == CPUMCPUVENDOR_CYRIX)
338	{
339	switch (bFamily)
340	{
341	case 4:
342	switch (bModel)
343	{
344	case 9: return kCpumMicroarch_Cyrix_5x86;
345	}
346	break;
347
348	case 5:
349	switch (bModel)
350	{
351	case 2: return kCpumMicroarch_Cyrix_M1;
352	case 4: return kCpumMicroarch_Cyrix_MediaGX;
353	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
354	}
355	break;
356
357	case 6:
358	switch (bModel)
359	{
360	case 0: return kCpumMicroarch_Cyrix_M2;
361	}
362	break;
363
364	}
365	return kCpumMicroarch_Cyrix_Unknown;
366	}
367
368	return kCpumMicroarch_Unknown;
369	}
370
371
372	/**
373	* Translates a microarchitecture enum value to the corresponding string
374	* constant.
375	*
376	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
377	* NULL if the value is invalid.
378	*
379	* @param enmMicroarch The enum value to convert.
380	*/
381	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
382	{
383	switch (enmMicroarch)
384	{
385	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
386	CASE_RET_STR(kCpumMicroarch_Intel_8086);
387	CASE_RET_STR(kCpumMicroarch_Intel_80186);
388	CASE_RET_STR(kCpumMicroarch_Intel_80286);
389	CASE_RET_STR(kCpumMicroarch_Intel_80386);
390	CASE_RET_STR(kCpumMicroarch_Intel_80486);
391	CASE_RET_STR(kCpumMicroarch_Intel_P5);
392
393	CASE_RET_STR(kCpumMicroarch_Intel_P6);
394	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
395	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
396
397	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
398	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
399	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
400
401	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
402	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
403
404	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
405	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
406	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
407	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
408	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
409	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
410	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
411	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Cannonlake);
412
413	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
414	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
415	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
416	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
417	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
418	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
419	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
420
421	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
422	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
423	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
424	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
425	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
426	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
427	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
428
429	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
430
431	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
432	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
433	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
434	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
435	CASE_RET_STR(kCpumMicroarch_AMD_K5);
436	CASE_RET_STR(kCpumMicroarch_AMD_K6);
437
438	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
439	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
440	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
441	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
442	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
443	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
444	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
445
446	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
447	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
448	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
449	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
450	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
451
452	CASE_RET_STR(kCpumMicroarch_AMD_K10);
453	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
454	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
455	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
456	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
457
458	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
459	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
460	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
461	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
462	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
463
464	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
465
466	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
467
468	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
469	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
470	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
471	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
472	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
473	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
474	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
475	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
476	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
477	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
478	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
479	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
480	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
481
482	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
483	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
484	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
485	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
486	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
487	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
488
489	CASE_RET_STR(kCpumMicroarch_Unknown);
490
491	#undef CASE_RET_STR
492	case kCpumMicroarch_Invalid:
493	case kCpumMicroarch_Intel_End:
494	case kCpumMicroarch_Intel_Core7_End:
495	case kCpumMicroarch_Intel_Atom_End:
496	case kCpumMicroarch_Intel_P6_Core_Atom_End:
497	case kCpumMicroarch_Intel_NB_End:
498	case kCpumMicroarch_AMD_K7_End:
499	case kCpumMicroarch_AMD_K8_End:
500	case kCpumMicroarch_AMD_15h_End:
501	case kCpumMicroarch_AMD_16h_End:
502	case kCpumMicroarch_AMD_End:
503	case kCpumMicroarch_VIA_End:
504	case kCpumMicroarch_Cyrix_End:
505	case kCpumMicroarch_32BitHack:
506	break;
507	/* no default! */
508	}
509
510	return NULL;
511	}
512
513
514
515	/**
516	* Gets a matching leaf in the CPUID leaf array.
517	*
518	* @returns Pointer to the matching leaf, or NULL if not found.
519	* @param paLeaves The CPUID leaves to search. This is sorted.
520	* @param cLeaves The number of leaves in the array.
521	* @param uLeaf The leaf to locate.
522	* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
523	*/
524	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
525	{
526	/* Lazy bird does linear lookup here since this is only used for the
527	occational CPUID overrides. */
528	for (uint32_t i = 0; i < cLeaves; i++)
529	if ( paLeaves[i].uLeaf == uLeaf
530	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
531	return &paLeaves[i];
532	return NULL;
533	}
534
535
536	/**
537	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
538	*
539	* @returns true if found, false it not.
540	* @param paLeaves The CPUID leaves to search. This is sorted.
541	* @param cLeaves The number of leaves in the array.
542	* @param uLeaf The leaf to locate.
543	* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
544	* @param pLegacy The legacy output leaf.
545	*/
546	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
547	PCPUMCPUID pLegacy)
548	{
549	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
550	if (pLeaf)
551	{
552	pLegacy->uEax = pLeaf->uEax;
553	pLegacy->uEbx = pLeaf->uEbx;
554	pLegacy->uEcx = pLeaf->uEcx;
555	pLegacy->uEdx = pLeaf->uEdx;
556	return true;
557	}
558	return false;
559	}
560
561
562	/**
563	* Ensures that the CPUID leaf array can hold one more leaf.
564	*
565	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
566	* failure.
567	* @param pVM Pointer to the VM, used as the heap selector. Passing
568	* NULL uses the host-context heap, otherwise the VM's
569	* hyper heap is used.
570	* @param ppaLeaves Pointer to the variable holding the array pointer
571	* (input/output).
572	* @param cLeaves The current array size.
573	*
574	* @remarks This function will automatically update the R0 and RC pointers when
575	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
576	* be the corresponding VM's CPUID arrays (which is asserted).
577	*/
578	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
579	{
580	/*
581	* If pVM is not specified, we're on the regular heap and can waste a
582	* little space to speed things up.
583	*/
584	uint32_t cAllocated;
585	if (!pVM)
586	{
587	cAllocated = RT_ALIGN(cLeaves, 16);
588	if (cLeaves + 1 > cAllocated)
589	{
590	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
591	if (pvNew)
592	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
593	else
594	{
595	RTMemFree(*ppaLeaves);
596	*ppaLeaves = NULL;
597	}
598	}
599	}
600	/*
601	* Otherwise, we're on the hyper heap and are probably just inserting
602	* one or two leaves and should conserve space.
603	*/
604	else
605	{
606	#ifdef IN_VBOX_CPU_REPORT
607	AssertReleaseFailed();
608	#else
609	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
610	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
611
612	size_t cb = cLeaves * sizeof(**ppaLeaves);
613	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
614	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
615	if (RT_SUCCESS(rc))
616	{
617	/* Update the R0 and RC pointers. */
618	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
619	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
620	}
621	else
622	{
623	*ppaLeaves = NULL;
624	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
625	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
626	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
627	}
628	#endif
629	}
630	return *ppaLeaves;
631	}
632
633
634	/**
635	* Append a CPUID leaf or sub-leaf.
636	*
637	* ASSUMES linear insertion order, so we'll won't need to do any searching or
638	* replace anything. Use cpumR3CpuIdInsert() for those cases.
639	*
640	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
641	* the caller need do no more work.
642	* @param ppaLeaves Pointer to the the pointer to the array of sorted
643	* CPUID leaves and sub-leaves.
644	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
645	* @param uLeaf The leaf we're adding.
646	* @param uSubLeaf The sub-leaf number.
647	* @param fSubLeafMask The sub-leaf mask.
648	* @param uEax The EAX value.
649	* @param uEbx The EBX value.
650	* @param uEcx The ECX value.
651	* @param uEdx The EDX value.
652	* @param fFlags The flags.
653	*/
654	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
655	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
656	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
657	{
658	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
659	return VERR_NO_MEMORY;
660
661	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
662	Assert( *pcLeaves == 0
663	\|\| pNew[-1].uLeaf < uLeaf
664	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
665
666	pNew->uLeaf = uLeaf;
667	pNew->uSubLeaf = uSubLeaf;
668	pNew->fSubLeafMask = fSubLeafMask;
669	pNew->uEax = uEax;
670	pNew->uEbx = uEbx;
671	pNew->uEcx = uEcx;
672	pNew->uEdx = uEdx;
673	pNew->fFlags = fFlags;
674
675	*pcLeaves += 1;
676	return VINF_SUCCESS;
677	}
678
679
680	/**
681	* Checks that we've updated the CPUID leaves array correctly.
682	*
683	* This is a no-op in non-strict builds.
684	*
685	* @param paLeaves The leaves array.
686	* @param cLeaves The number of leaves.
687	*/
688	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
689	{
690	#ifdef VBOX_STRICT
691	for (uint32_t i = 1; i < cLeaves; i++)
692	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
693	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
694	else
695	{
696	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
697	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
698	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
699	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
700	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
701	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
702	}
703	#else
704	NOREF(paLeaves);
705	NOREF(cLeaves);
706	#endif
707	}
708
709
710	/**
711	* Inserts a CPU ID leaf, replacing any existing ones.
712	*
713	* When inserting a simple leaf where we already got a series of subleaves with
714	* the same leaf number (eax), the simple leaf will replace the whole series.
715	*
716	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
717	* host-context heap and has only been allocated/reallocated by the
718	* cpumR3CpuIdEnsureSpace function.
719	*
720	* @returns VBox status code.
721	* @param pVM Pointer to the VM, used as the heap selector.
722	* Passing NULL uses the host-context heap, otherwise
723	* the VM's hyper heap is used.
724	* @param ppaLeaves Pointer to the the pointer to the array of sorted
725	* CPUID leaves and sub-leaves. Must be NULL if using
726	* the hyper heap.
727	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must be
728	* NULL if using the hyper heap.
729	* @param pNewLeaf Pointer to the data of the new leaf we're about to
730	* insert.
731	*/
732	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
733	{
734	/*
735	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
736	*/
737	if (pVM)
738	{
739	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
740	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
741
742	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
743	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
744	}
745
746	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
747	uint32_t cLeaves = *pcLeaves;
748
749	/*
750	* Validate the new leaf a little.
751	*/
752	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
753	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
754	VERR_INVALID_FLAGS);
755	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
756	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
757	VERR_INVALID_PARAMETER);
758	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
759	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
760	VERR_INVALID_PARAMETER);
761	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
762	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
763	VERR_INVALID_PARAMETER);
764
765	/*
766	* Find insertion point. The lazy bird uses the same excuse as in
767	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
768	*/
769	uint32_t i;
770	if ( cLeaves > 0
771	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
772	{
773	/* Add at end. */
774	i = cLeaves;
775	}
776	else if ( cLeaves > 0
777	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
778	{
779	/* Either replacing the last leaf or dealing with sub-leaves. Spool
780	back to the first sub-leaf to pretend we did the linear search. */
781	i = cLeaves - 1;
782	while ( i > 0
783	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
784	i--;
785	}
786	else
787	{
788	/* Linear search from the start. */
789	i = 0;
790	while ( i < cLeaves
791	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
792	i++;
793	}
794	if ( i < cLeaves
795	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
796	{
797	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
798	{
799	/*
800	* The sub-leaf mask differs, replace all existing leaves with the
801	* same leaf number.
802	*/
803	uint32_t c = 1;
804	while ( i + c < cLeaves
805	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
806	c++;
807	if (c > 1 && i + c < cLeaves)
808	{
809	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
810	*pcLeaves = cLeaves -= c - 1;
811	}
812
813	paLeaves[i] = *pNewLeaf;
814	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
815	return VINF_SUCCESS;
816	}
817
818	/* Find sub-leaf insertion point. */
819	while ( i < cLeaves
820	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
821	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
822	i++;
823
824	/*
825	* If we've got an exactly matching leaf, replace it.
826	*/
827	if ( i < cLeaves
828	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
829	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
830	{
831	paLeaves[i] = *pNewLeaf;
832	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
833	return VINF_SUCCESS;
834	}
835	}
836
837	/*
838	* Adding a new leaf at 'i'.
839	*/
840	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
841	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
842	if (!paLeaves)
843	return VERR_NO_MEMORY;
844
845	if (i < cLeaves)
846	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
847	*pcLeaves += 1;
848	paLeaves[i] = *pNewLeaf;
849
850	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
851	return VINF_SUCCESS;
852	}
853
854
855	/**
856	* Removes a range of CPUID leaves.
857	*
858	* This will not reallocate the array.
859	*
860	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
861	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
862	* @param uFirst The first leaf.
863	* @param uLast The last leaf.
864	*/
865	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
866	{
867	uint32_t cLeaves = *pcLeaves;
868
869	Assert(uFirst <= uLast);
870
871	/*
872	* Find the first one.
873	*/
874	uint32_t iFirst = 0;
875	while ( iFirst < cLeaves
876	&& paLeaves[iFirst].uLeaf < uFirst)
877	iFirst++;
878
879	/*
880	* Find the end (last + 1).
881	*/
882	uint32_t iEnd = iFirst;
883	while ( iEnd < cLeaves
884	&& paLeaves[iEnd].uLeaf <= uLast)
885	iEnd++;
886
887	/*
888	* Adjust the array if anything needs removing.
889	*/
890	if (iFirst < iEnd)
891	{
892	if (iEnd < cLeaves)
893	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
894	*pcLeaves = cLeaves -= (iEnd - iFirst);
895	}
896
897	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
898	}
899
900
901
902	/**
903	* Checks if ECX make a difference when reading a given CPUID leaf.
904	*
905	* @returns @c true if it does, @c false if it doesn't.
906	* @param uLeaf The leaf we're reading.
907	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
908	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
909	* final sub-leaf (for leaf 0xb only).
910	*/
911	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
912	{
913	*pfFinalEcxUnchanged = false;
914
915	uint32_t auCur[4];
916	uint32_t auPrev[4];
917	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
918
919	/* Look for sub-leaves. */
920	uint32_t uSubLeaf = 1;
921	for (;;)
922	{
923	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
924	if (memcmp(auCur, auPrev, sizeof(auCur)))
925	break;
926
927	/* Advance / give up. */
928	uSubLeaf++;
929	if (uSubLeaf >= 64)
930	{
931	*pcSubLeaves = 1;
932	return false;
933	}
934	}
935
936	/* Count sub-leaves. */
937	uint32_t cRepeats = 0;
938	uSubLeaf = 0;
939	for (;;)
940	{
941	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
942
943	/* Figuring out when to stop isn't entirely straight forward as we need
944	to cover undocumented behavior up to a point and implementation shortcuts. */
945
946	/* 1. Look for zero values. */
947	if ( auCur[0] == 0
948	&& auCur[1] == 0
949	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
950	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */) )
951	break;
952
953	/* 2. Look for more than 4 repeating value sets. */
954	if ( auCur[0] == auPrev[0]
955	&& auCur[1] == auPrev[1]
956	&& ( auCur[2] == auPrev[2]
957	\|\| ( auCur[2] == uSubLeaf
958	&& auPrev[2] == uSubLeaf - 1) )
959	&& auCur[3] == auPrev[3])
960	{
961	cRepeats++;
962	if (cRepeats > 4)
963	break;
964	}
965	else
966	cRepeats = 0;
967
968	/* 3. Leaf 0xb level type 0 check. */
969	if ( uLeaf == 0xb
970	&& (auCur[3] & 0xff00) == 0
971	&& (auPrev[3] & 0xff00) == 0)
972	break;
973
974	/* 99. Give up. */
975	if (uSubLeaf >= 128)
976	{
977	#ifndef IN_VBOX_CPU_REPORT
978	/* Ok, limit it according to the documentation if possible just to
979	avoid annoying users with these detection issues. */
980	uint32_t cDocLimit = UINT32_MAX;
981	if (uLeaf == 0x4)
982	cDocLimit = 4;
983	else if (uLeaf == 0x7)
984	cDocLimit = 1;
985	else if (uLeaf == 0xf)
986	cDocLimit = 2;
987	if (cDocLimit != UINT32_MAX)
988	{
989	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
990	*pcSubLeaves = cDocLimit + 3;
991	return true;
992	}
993	#endif
994	*pcSubLeaves = UINT32_MAX;
995	return true;
996	}
997
998	/* Advance. */
999	uSubLeaf++;
1000	memcpy(auPrev, auCur, sizeof(auCur));
1001	}
1002
1003	/* Standard exit. */
1004	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1005	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1006	return true;
1007	}
1008
1009
1010	/**
1011	* Gets a CPU ID leaf.
1012	*
1013	* @returns VBox status code.
1014	* @param pVM Pointer to the VM.
1015	* @param pLeaf Where to store the found leaf.
1016	* @param uLeaf The leaf to locate.
1017	* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
1018	*/
1019	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1020	{
1021	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1022	uLeaf, uSubLeaf);
1023	if (pcLeaf)
1024	{
1025	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1026	return VINF_SUCCESS;
1027	}
1028
1029	return VERR_NOT_FOUND;
1030	}
1031
1032
1033	/**
1034	* Inserts a CPU ID leaf, replacing any existing ones.
1035	*
1036	* @returns VBox status code.
1037	* @param pVM Pointer to the VM.
1038	* @param pNewLeaf Pointer to the leaf being inserted.
1039	*/
1040	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1041	{
1042	/*
1043	* Validate parameters.
1044	*/
1045	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1046	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1047
1048	/*
1049	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1050	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1051	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1052	*/
1053	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1054	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1055	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1056	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1057	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1058	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1059	{
1060	return VERR_NOT_SUPPORTED;
1061	}
1062
1063	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1064	}
1065
1066	/**
1067	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1068	*
1069	* @returns VBox status code.
1070	* @param ppaLeaves Where to return the array pointer on success.
1071	* Use RTMemFree to release.
1072	* @param pcLeaves Where to return the size of the array on
1073	* success.
1074	*/
1075	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1076	{
1077	*ppaLeaves = NULL;
1078	*pcLeaves = 0;
1079
1080	/*
1081	* Try out various candidates. This must be sorted!
1082	*/
1083	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1084	{
1085	{ UINT32_C(0x00000000), false },
1086	{ UINT32_C(0x10000000), false },
1087	{ UINT32_C(0x20000000), false },
1088	{ UINT32_C(0x30000000), false },
1089	{ UINT32_C(0x40000000), false },
1090	{ UINT32_C(0x50000000), false },
1091	{ UINT32_C(0x60000000), false },
1092	{ UINT32_C(0x70000000), false },
1093	{ UINT32_C(0x80000000), false },
1094	{ UINT32_C(0x80860000), false },
1095	{ UINT32_C(0x8ffffffe), true },
1096	{ UINT32_C(0x8fffffff), true },
1097	{ UINT32_C(0x90000000), false },
1098	{ UINT32_C(0xa0000000), false },
1099	{ UINT32_C(0xb0000000), false },
1100	{ UINT32_C(0xc0000000), false },
1101	{ UINT32_C(0xd0000000), false },
1102	{ UINT32_C(0xe0000000), false },
1103	{ UINT32_C(0xf0000000), false },
1104	};
1105
1106	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1107	{
1108	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1109	uint32_t uEax, uEbx, uEcx, uEdx;
1110	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1111
1112	/*
1113	* Does EAX look like a typical leaf count value?
1114	*/
1115	if ( uEax > uLeaf
1116	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1117	{
1118	/* Yes, dump them. */
1119	uint32_t cLeaves = uEax - uLeaf + 1;
1120	while (cLeaves-- > 0)
1121	{
1122	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1123
1124	uint32_t fFlags = 0;
1125
1126	/* There are currently three known leaves containing an APIC ID
1127	that needs EMT specific attention */
1128	if (uLeaf == 1)
1129	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1130	else if (uLeaf == 0xb && uEcx != 0)
1131	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1132	else if ( uLeaf == UINT32_C(0x8000001e)
1133	&& ( uEax
1134	\|\| uEbx
1135	\|\| uEdx
1136	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1137	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1138
1139
1140	/* Check three times here to reduce the chance of CPU migration
1141	resulting in false positives with things like the APIC ID. */
1142	uint32_t cSubLeaves;
1143	bool fFinalEcxUnchanged;
1144	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1145	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1146	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1147	{
1148	if (cSubLeaves > 16)
1149	{
1150	/* This shouldn't happen. But in case it does, file all
1151	relevant details in the release log. */
1152	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1153	LogRel(("------------------ dump of problematic subleaves ------------------\n"));
1154	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1155	{
1156	uint32_t auTmp[4];
1157	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1158	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1159	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1160	}
1161	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1162	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1163	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1164	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1165	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1166	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1167	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1168	}
1169
1170	if (fFinalEcxUnchanged)
1171	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1172
1173	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1174	{
1175	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1176	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1177	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1178	if (RT_FAILURE(rc))
1179	return rc;
1180	}
1181	}
1182	else
1183	{
1184	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1185	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1186	if (RT_FAILURE(rc))
1187	return rc;
1188	}
1189
1190	/* next */
1191	uLeaf++;
1192	}
1193	}
1194	/*
1195	* Special CPUIDs needs special handling as they don't follow the
1196	* leaf count principle used above.
1197	*/
1198	else if (s_aCandidates[iOuter].fSpecial)
1199	{
1200	bool fKeep = false;
1201	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1202	fKeep = true;
1203	else if ( uLeaf == 0x8fffffff
1204	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1205	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1206	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1207	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1208	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1209	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1210	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1211	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1212	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1213	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1214	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1215	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1216	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1217	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1218	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1219	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1220	fKeep = true;
1221	if (fKeep)
1222	{
1223	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1224	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1225	if (RT_FAILURE(rc))
1226	return rc;
1227	}
1228	}
1229	}
1230
1231	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1232	return VINF_SUCCESS;
1233	}
1234
1235
1236	/**
1237	* Determines the method the CPU uses to handle unknown CPUID leaves.
1238	*
1239	* @returns VBox status code.
1240	* @param penmUnknownMethod Where to return the method.
1241	* @param pDefUnknown Where to return default unknown values. This
1242	* will be set, even if the resulting method
1243	* doesn't actually needs it.
1244	*/
1245	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1246	{
1247	uint32_t uLastStd = ASMCpuId_EAX(0);
1248	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1249	if (!ASMIsValidExtRange(uLastExt))
1250	uLastExt = 0x80000000;
1251
1252	uint32_t auChecks[] =
1253	{
1254	uLastStd + 1,
1255	uLastStd + 5,
1256	uLastStd + 8,
1257	uLastStd + 32,
1258	uLastStd + 251,
1259	uLastExt + 1,
1260	uLastExt + 8,
1261	uLastExt + 15,
1262	uLastExt + 63,
1263	uLastExt + 255,
1264	0x7fbbffcc,
1265	0x833f7872,
1266	0xefff2353,
1267	0x35779456,
1268	0x1ef6d33e,
1269	};
1270
1271	static const uint32_t s_auValues[] =
1272	{
1273	0xa95d2156,
1274	0x00000001,
1275	0x00000002,
1276	0x00000008,
1277	0x00000000,
1278	0x55773399,
1279	0x93401769,
1280	0x12039587,
1281	};
1282
1283	/*
1284	* Simple method, all zeros.
1285	*/
1286	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1287	pDefUnknown->uEax = 0;
1288	pDefUnknown->uEbx = 0;
1289	pDefUnknown->uEcx = 0;
1290	pDefUnknown->uEdx = 0;
1291
1292	/*
1293	* Intel has been observed returning the last standard leaf.
1294	*/
1295	uint32_t auLast[4];
1296	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1297
1298	uint32_t cChecks = RT_ELEMENTS(auChecks);
1299	while (cChecks > 0)
1300	{
1301	uint32_t auCur[4];
1302	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1303	if (memcmp(auCur, auLast, sizeof(auCur)))
1304	break;
1305	cChecks--;
1306	}
1307	if (cChecks == 0)
1308	{
1309	/* Now, what happens when the input changes? Esp. ECX. */
1310	uint32_t cTotal = 0;
1311	uint32_t cSame = 0;
1312	uint32_t cLastWithEcx = 0;
1313	uint32_t cNeither = 0;
1314	uint32_t cValues = RT_ELEMENTS(s_auValues);
1315	while (cValues > 0)
1316	{
1317	uint32_t uValue = s_auValues[cValues - 1];
1318	uint32_t auLastWithEcx[4];
1319	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1320	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1321
1322	cChecks = RT_ELEMENTS(auChecks);
1323	while (cChecks > 0)
1324	{
1325	uint32_t auCur[4];
1326	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1327	if (!memcmp(auCur, auLast, sizeof(auCur)))
1328	{
1329	cSame++;
1330	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1331	cLastWithEcx++;
1332	}
1333	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1334	cLastWithEcx++;
1335	else
1336	cNeither++;
1337	cTotal++;
1338	cChecks--;
1339	}
1340	cValues--;
1341	}
1342
1343	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1344	if (cSame == cTotal)
1345	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1346	else if (cLastWithEcx == cTotal)
1347	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1348	else
1349	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1350	pDefUnknown->uEax = auLast[0];
1351	pDefUnknown->uEbx = auLast[1];
1352	pDefUnknown->uEcx = auLast[2];
1353	pDefUnknown->uEdx = auLast[3];
1354	return VINF_SUCCESS;
1355	}
1356
1357	/*
1358	* Unchanged register values?
1359	*/
1360	cChecks = RT_ELEMENTS(auChecks);
1361	while (cChecks > 0)
1362	{
1363	uint32_t const uLeaf = auChecks[cChecks - 1];
1364	uint32_t cValues = RT_ELEMENTS(s_auValues);
1365	while (cValues > 0)
1366	{
1367	uint32_t uValue = s_auValues[cValues - 1];
1368	uint32_t auCur[4];
1369	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1370	if ( auCur[0] != uLeaf
1371	\|\| auCur[1] != uValue
1372	\|\| auCur[2] != uValue
1373	\|\| auCur[3] != uValue)
1374	break;
1375	cValues--;
1376	}
1377	if (cValues != 0)
1378	break;
1379	cChecks--;
1380	}
1381	if (cChecks == 0)
1382	{
1383	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1384	return VINF_SUCCESS;
1385	}
1386
1387	/*
1388	* Just go with the simple method.
1389	*/
1390	return VINF_SUCCESS;
1391	}
1392
1393
1394	/**
1395	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1396	*
1397	* @returns Read only name string.
1398	* @param enmUnknownMethod The method to translate.
1399	*/
1400	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1401	{
1402	switch (enmUnknownMethod)
1403	{
1404	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1405	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1406	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1407	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1408
1409	case CPUMUNKNOWNCPUID_INVALID:
1410	case CPUMUNKNOWNCPUID_END:
1411	case CPUMUNKNOWNCPUID_32BIT_HACK:
1412	break;
1413	}
1414	return "Invalid-unknown-CPUID-method";
1415	}
1416
1417
1418	/**
1419	* Detect the CPU vendor give n the
1420	*
1421	* @returns The vendor.
1422	* @param uEAX EAX from CPUID(0).
1423	* @param uEBX EBX from CPUID(0).
1424	* @param uECX ECX from CPUID(0).
1425	* @param uEDX EDX from CPUID(0).
1426	*/
1427	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1428	{
1429	if (ASMIsValidStdRange(uEAX))
1430	{
1431	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1432	return CPUMCPUVENDOR_AMD;
1433
1434	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1435	return CPUMCPUVENDOR_INTEL;
1436
1437	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1438	return CPUMCPUVENDOR_VIA;
1439
1440	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1441	&& uECX == UINT32_C(0x64616574)
1442	&& uEDX == UINT32_C(0x736E4978))
1443	return CPUMCPUVENDOR_CYRIX;
1444
1445	/* "Geode by NSC", example: family 5, model 9. */
1446
1447	/** @todo detect the other buggers... */
1448	}
1449
1450	return CPUMCPUVENDOR_UNKNOWN;
1451	}
1452
1453
1454	/**
1455	* Translates a CPU vendor enum value into the corresponding string constant.
1456	*
1457	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1458	* value name. This can be useful when generating code.
1459	*
1460	* @returns Read only name string.
1461	* @param enmVendor The CPU vendor value.
1462	*/
1463	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1464	{
1465	switch (enmVendor)
1466	{
1467	case CPUMCPUVENDOR_INTEL: return "INTEL";
1468	case CPUMCPUVENDOR_AMD: return "AMD";
1469	case CPUMCPUVENDOR_VIA: return "VIA";
1470	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1471	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1472
1473	case CPUMCPUVENDOR_INVALID:
1474	case CPUMCPUVENDOR_32BIT_HACK:
1475	break;
1476	}
1477	return "Invalid-cpu-vendor";
1478	}
1479
1480
1481	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1482	{
1483	/* Could do binary search, doing linear now because I'm lazy. */
1484	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1485	while (cLeaves-- > 0)
1486	{
1487	if (pLeaf->uLeaf == uLeaf)
1488	return pLeaf;
1489	pLeaf++;
1490	}
1491	return NULL;
1492	}
1493
1494
1495	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1496	{
1497	RT_ZERO(*pFeatures);
1498	if (cLeaves >= 2)
1499	{
1500	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1501	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1502
1503	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(paLeaves[0].uEax,
1504	paLeaves[0].uEbx,
1505	paLeaves[0].uEcx,
1506	paLeaves[0].uEdx);
1507	pFeatures->uFamily = ASMGetCpuFamily(paLeaves[1].uEax);
1508	pFeatures->uModel = ASMGetCpuModel(paLeaves[1].uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1509	pFeatures->uStepping = ASMGetCpuStepping(paLeaves[1].uEax);
1510	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1511	pFeatures->uFamily,
1512	pFeatures->uModel,
1513	pFeatures->uStepping);
1514
1515	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1516	if (pLeaf)
1517	pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff;
1518	else if (paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1519	pFeatures->cMaxPhysAddrWidth = 36;
1520	else
1521	pFeatures->cMaxPhysAddrWidth = 32;
1522
1523	/* Standard features. */
1524	pFeatures->fMsr = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_MSR);
1525	pFeatures->fApic = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_APIC);
1526	pFeatures->fX2Apic = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1527	pFeatures->fPse = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE);
1528	pFeatures->fPse36 = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1529	pFeatures->fPae = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PAE);
1530	pFeatures->fPat = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PAT);
1531	pFeatures->fFxSaveRstor = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1532	pFeatures->fSysEnter = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_SEP);
1533	pFeatures->fHypervisorPresent = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_HVP);
1534	pFeatures->fMonitorMWait = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1535
1536	/* MWAIT/MONITOR leaf. */
1537	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1538	if (pMWaitLeaf)
1539	{
1540	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1541	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1542	}
1543
1544	/* Extended features. */
1545	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1546	if (pExtLeaf)
1547	{
1548	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1549	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1550	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1551	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1552	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1553	}
1554
1555	if ( pExtLeaf
1556	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1557	{
1558	/* AMD features. */
1559	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1560	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1561	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1562	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1563	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1564	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1565	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1566	}
1567
1568	/*
1569	* Quirks.
1570	*/
1571	pFeatures->fLeakyFxSR = pExtLeaf
1572	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1573	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1574	&& pFeatures->uFamily >= 6 /* K7 and up */;
1575	}
1576	else
1577	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1578	return VINF_SUCCESS;
1579	}
1580
1581
1582	/*
1583	*
1584	* Init related code.
1585	* Init related code.
1586	* Init related code.
1587	*
1588	*
1589	*/
1590	#ifdef VBOX_IN_VMM
1591
1592
1593	/**
1594	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1595	*
1596	* This ignores the fSubLeafMask.
1597	*
1598	* @returns Pointer to the matching leaf, or NULL if not found.
1599	* @param paLeaves The CPUID leaves to search. This is sorted.
1600	* @param cLeaves The number of leaves in the array.
1601	* @param uLeaf The leaf to locate.
1602	* @param uSubLeaf The subleaf to locate.
1603	*/
1604	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1605	{
1606	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1607	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1608	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1609	if (iEnd)
1610	{
1611	uint32_t iBegin = 0;
1612	for (;;)
1613	{
1614	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1615	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1616	if (uNeedle < uCur)
1617	{
1618	if (i > iBegin)
1619	iEnd = i;
1620	else
1621	break;
1622	}
1623	else if (uNeedle > uCur)
1624	{
1625	if (i + 1 < iEnd)
1626	iBegin = i + 1;
1627	else
1628	break;
1629	}
1630	else
1631	return &paLeaves[i];
1632	}
1633	}
1634	return NULL;
1635	}
1636
1637
1638	/**
1639	* Loads MSR range overrides.
1640	*
1641	* This must be called before the MSR ranges are moved from the normal heap to
1642	* the hyper heap!
1643	*
1644	* @returns VBox status code (VMSetError called).
1645	* @param pVM Pointer to the cross context VM structure
1646	* @param pMsrNode The CFGM node with the MSR overrides.
1647	*/
1648	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1649	{
1650	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1651	{
1652	/*
1653	* Assemble a valid MSR range.
1654	*/
1655	CPUMMSRRANGE MsrRange;
1656	MsrRange.offCpumCpu = 0;
1657	MsrRange.fReserved = 0;
1658
1659	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1660	if (RT_FAILURE(rc))
1661	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1662
1663	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1664	if (RT_FAILURE(rc))
1665	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1666	MsrRange.szName, rc);
1667
1668	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1669	if (RT_FAILURE(rc))
1670	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1671	MsrRange.szName, rc);
1672
1673	char szType[32];
1674	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1675	if (RT_FAILURE(rc))
1676	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1677	MsrRange.szName, rc);
1678	if (!RTStrICmp(szType, "FixedValue"))
1679	{
1680	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1681	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1682
1683	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1684	if (RT_FAILURE(rc))
1685	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1686	MsrRange.szName, rc);
1687
1688	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1689	if (RT_FAILURE(rc))
1690	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1691	MsrRange.szName, rc);
1692
1693	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1694	if (RT_FAILURE(rc))
1695	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1696	MsrRange.szName, rc);
1697	}
1698	else
1699	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1700	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1701
1702	/*
1703	* Insert the range into the table (replaces/splits/shrinks existing
1704	* MSR ranges).
1705	*/
1706	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1707	&MsrRange);
1708	if (RT_FAILURE(rc))
1709	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
1710	}
1711
1712	return VINF_SUCCESS;
1713	}
1714
1715
1716	/**
1717	* Loads CPUID leaf overrides.
1718	*
1719	* This must be called before the CPUID leaves are moved from the normal
1720	* heap to the hyper heap!
1721	*
1722	* @returns VBox status code (VMSetError called).
1723	* @param pVM Pointer to the cross context VM structure
1724	* @param pParentNode The CFGM node with the CPUID leaves.
1725	* @param pszLabel How to label the overrides we're loading.
1726	*/
1727	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
1728	{
1729	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1730	{
1731	/*
1732	* Get the leaf and subleaf numbers.
1733	*/
1734	char szName[128];
1735	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
1736	if (RT_FAILURE(rc))
1737	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
1738
1739	/* The leaf number is either specified directly or thru the node name. */
1740	uint32_t uLeaf;
1741	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
1742	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1743	{
1744	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
1745	if (rc != VINF_SUCCESS)
1746	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
1747	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
1748	}
1749	else if (RT_FAILURE(rc))
1750	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
1751	pszLabel, szName, rc);
1752
1753	uint32_t uSubLeaf;
1754	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
1755	if (RT_FAILURE(rc))
1756	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
1757	pszLabel, szName, rc);
1758
1759	uint32_t fSubLeafMask;
1760	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
1761	if (RT_FAILURE(rc))
1762	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
1763	pszLabel, szName, rc);
1764
1765	/*
1766	* Look up the specified leaf, since the output register values
1767	* defaults to any existing values. This allows overriding a single
1768	* register, without needing to know the other values.
1769	*/
1770	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
1771	CPUMCPUIDLEAF Leaf;
1772	if (pLeaf)
1773	Leaf = *pLeaf;
1774	else
1775	RT_ZERO(Leaf);
1776	Leaf.uLeaf = uLeaf;
1777	Leaf.uSubLeaf = uSubLeaf;
1778	Leaf.fSubLeafMask = fSubLeafMask;
1779
1780	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
1781	if (RT_FAILURE(rc))
1782	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
1783	pszLabel, szName, rc);
1784	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
1785	if (RT_FAILURE(rc))
1786	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
1787	pszLabel, szName, rc);
1788	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
1789	if (RT_FAILURE(rc))
1790	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
1791	pszLabel, szName, rc);
1792	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
1793	if (RT_FAILURE(rc))
1794	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
1795	pszLabel, szName, rc);
1796
1797	/*
1798	* Insert the leaf into the table (replaces existing ones).
1799	*/
1800	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1801	&Leaf);
1802	if (RT_FAILURE(rc))
1803	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
1804	}
1805
1806	return VINF_SUCCESS;
1807	}
1808
1809
1810
1811	/**
1812	* Fetches overrides for a CPUID leaf.
1813	*
1814	* @returns VBox status code.
1815	* @param pLeaf The leaf to load the overrides into.
1816	* @param pCfgNode The CFGM node containing the overrides
1817	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
1818	* @param iLeaf The CPUID leaf number.
1819	*/
1820	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
1821	{
1822	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
1823	if (pLeafNode)
1824	{
1825	uint32_t u32;
1826	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
1827	if (RT_SUCCESS(rc))
1828	pLeaf->uEax = u32;
1829	else
1830	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1831
1832	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
1833	if (RT_SUCCESS(rc))
1834	pLeaf->uEbx = u32;
1835	else
1836	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1837
1838	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
1839	if (RT_SUCCESS(rc))
1840	pLeaf->uEcx = u32;
1841	else
1842	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1843
1844	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
1845	if (RT_SUCCESS(rc))
1846	pLeaf->uEdx = u32;
1847	else
1848	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1849
1850	}
1851	return VINF_SUCCESS;
1852	}
1853
1854
1855	/**
1856	* Load the overrides for a set of CPUID leaves.
1857	*
1858	* @returns VBox status code.
1859	* @param paLeaves The leaf array.
1860	* @param cLeaves The number of leaves.
1861	* @param uStart The start leaf number.
1862	* @param pCfgNode The CFGM node containing the overrides
1863	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
1864	*/
1865	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
1866	{
1867	for (uint32_t i = 0; i < cLeaves; i++)
1868	{
1869	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
1870	if (RT_FAILURE(rc))
1871	return rc;
1872	}
1873
1874	return VINF_SUCCESS;
1875	}
1876
1877	/**
1878	* Init a set of host CPUID leaves.
1879	*
1880	* @returns VBox status code.
1881	* @param paLeaves The leaf array.
1882	* @param cLeaves The number of leaves.
1883	* @param uStart The start leaf number.
1884	* @param pCfgNode The /CPUM/HostCPUID/ node.
1885	*/
1886	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
1887	{
1888	/* Using the ECX variant for all of them can't hurt... */
1889	for (uint32_t i = 0; i < cLeaves; i++)
1890	ASMCpuIdExSlow(uStart + i, 0, 0, 0, &paLeaves[i].uEax, &paLeaves[i].uEbx, &paLeaves[i].uEcx, &paLeaves[i].uEdx);
1891
1892	/* Load CPUID leaf override; we currently don't care if the user
1893	specifies features the host CPU doesn't support. */
1894	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
1895	}
1896
1897
1898	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
1899	{
1900	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
1901
1902	/*
1903	* Install the CPUID information.
1904	*/
1905	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
1906	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
1907
1908	AssertLogRelRCReturn(rc, rc);
1909	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
1910	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
1911	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
1912	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
1913	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
1914
1915	/*
1916	* Update the default CPUID leaf if necessary.
1917	*/
1918	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
1919	{
1920	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
1921	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
1922	{
1923	/* We don't use CPUID(0).eax here because of the NT hack that only
1924	changes that value without actually removing any leaves. */
1925	uint32_t i = 0;
1926	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
1927	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uEax <= UINT32_C(0xff))
1928	{
1929	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
1930	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uEax <= UINT32_C(0xff))
1931	i++;
1932	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
1933	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
1934	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
1935	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
1936	}
1937	break;
1938	}
1939	default:
1940	break;
1941	}
1942
1943	/*
1944	* Explode the guest CPU features.
1945	*/
1946	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
1947	AssertLogRelRCReturn(rc, rc);
1948
1949	/*
1950	* Adjust the scalable bus frequency according to the CPUID information
1951	* we're now using.
1952	*/
1953	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
1954	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
1955	? UINT64_C(100000000) /* 100MHz */
1956	: UINT64_C(133333333); /* 133MHz */
1957
1958	/*
1959	* Populate the legacy arrays. Currently used for everything, later only
1960	* for patch manager.
1961	*/
1962	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
1963	{
1964	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
1965	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
1966	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
1967	};
1968	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
1969	{
1970	uint32_t cLeft = aOldRanges[i].cCpuIds;
1971	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
1972	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
1973	while (cLeft-- > 0)
1974	{
1975	uLeaf--;
1976	pLegacyLeaf--;
1977
1978	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
1979	if (pLeaf)
1980	{
1981	pLegacyLeaf->uEax = pLeaf->uEax;
1982	pLegacyLeaf->uEbx = pLeaf->uEbx;
1983	pLegacyLeaf->uEcx = pLeaf->uEcx;
1984	pLegacyLeaf->uEdx = pLeaf->uEdx;
1985	}
1986	else
1987	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
1988	}
1989	}
1990
1991	return VINF_SUCCESS;
1992	}
1993
1994
1995	/**
1996	* CPUID Configuration (from CFGM).
1997	*
1998	* @remarks The members aren't document since we would only be duplicating the
1999	* \@cfgm entries in cpumR3CpuIdReadConfig.
2000	*/
2001	typedef struct CPUMCPUIDCONFIG
2002	{
2003	bool fSyntheticCpu;
2004	bool fCmpXchg16b;
2005	bool fMonitor;
2006	bool fMWaitExtensions;
2007	bool fSse41;
2008	bool fSse42;
2009	bool fNt4LeafLimit;
2010	bool fInvariantTsc;
2011	uint32_t uMaxStdLeaf;
2012	uint32_t uMaxExtLeaf;
2013	uint32_t uMaxCentaurLeaf;
2014	uint32_t uMaxIntelFamilyModelStep;
2015	char szCpuName[128];
2016	} CPUMCPUIDCONFIG;
2017	/** Pointer to CPUID config (from CFGM). */
2018	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2019
2020
2021	/**
2022	* Insert hypervisor identification leaves.
2023	*
2024	* We only return minimal information, primarily ensuring that the
2025	* 0x40000000 function returns 0x40000001 and identifying ourselves.
2026	* Hypervisor-specific interface is supported through GIM which will
2027	* modify these leaves if required depending on the GIM provider.
2028	*
2029	* @returns VBox status code.
2030	* @param pCpum The CPUM instance data.
2031	* @param pConfig The CPUID configuration we've read from CFGM.
2032	*/
2033	static int cpumR3CpuIdPlantHypervisorLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2034	{
2035	CPUMCPUIDLEAF NewLeaf;
2036	NewLeaf.uLeaf = UINT32_C(0x40000000);
2037	NewLeaf.uSubLeaf = 0;
2038	NewLeaf.fSubLeafMask = 0;
2039	NewLeaf.uEax = UINT32_C(0x40000001);
2040	NewLeaf.uEbx = 0x786f4256 /* 'VBox' */;
2041	NewLeaf.uEcx = 0x786f4256 /* 'VBox' */;
2042	NewLeaf.uEdx = 0x786f4256 /* 'VBox' */;
2043	NewLeaf.fFlags = 0;
2044	int rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
2045	AssertLogRelRCReturn(rc, rc);
2046
2047	NewLeaf.uLeaf = UINT32_C(0x40000001);
2048	NewLeaf.uEax = 0x656e6f6e; /* 'none' */
2049	NewLeaf.uEbx = 0;
2050	NewLeaf.uEcx = 0;
2051	NewLeaf.uEdx = 0;
2052	NewLeaf.fFlags = 0;
2053	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
2054	AssertLogRelRCReturn(rc, rc);
2055
2056	return VINF_SUCCESS;
2057	}
2058
2059
2060	/**
2061	* Mini CPU selection support for making Mac OS X happy.
2062	*
2063	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2064	*
2065	* @param pCpum The CPUM instance data.
2066	* @param pConfig The CPUID configuration we've read from CFGM.
2067	*/
2068	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2069	{
2070	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2071	{
2072	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2073	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2074	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2075	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2076	0);
2077	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2078	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2079	{
2080	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2081	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2082	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2083	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2084	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2085	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2086	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2087	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2088	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2089	pStdFeatureLeaf->uEax = uNew;
2090	}
2091	}
2092	}
2093
2094
2095
2096	/**
2097	* Limit it the number of entries, zapping the remainder.
2098	*
2099	* The limits are masking off stuff about power saving and similar, this
2100	* is perhaps a bit crudely done as there is probably some relatively harmless
2101	* info too in these leaves (like words about having a constant TSC).
2102	*
2103	* @param pCpum The CPUM instance data.
2104	* @param pConfig The CPUID configuration we've read from CFGM.
2105	*/
2106	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2107	{
2108	/*
2109	* Standard leaves.
2110	*/
2111	uint32_t uSubLeaf = 0;
2112	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2113	if (pCurLeaf)
2114	{
2115	uint32_t uLimit = pCurLeaf->uEax;
2116	if (uLimit <= UINT32_C(0x000fffff))
2117	{
2118	if (uLimit > pConfig->uMaxStdLeaf)
2119	{
2120	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2121	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2122	uLimit + 1, UINT32_C(0x000fffff));
2123	}
2124
2125	/* NT4 hack, no zapping of extra leaves here. */
2126	if (pConfig->fNt4LeafLimit && uLimit > 3)
2127	pCurLeaf->uEax = uLimit = 3;
2128
2129	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2130	pCurLeaf->uEax = uLimit;
2131	}
2132	else
2133	{
2134	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2135	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2136	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2137	}
2138	}
2139
2140	/*
2141	* Extended leaves.
2142	*/
2143	uSubLeaf = 0;
2144	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2145	if (pCurLeaf)
2146	{
2147	uint32_t uLimit = pCurLeaf->uEax;
2148	if ( uLimit >= UINT32_C(0x80000000)
2149	&& uLimit <= UINT32_C(0x800fffff))
2150	{
2151	if (uLimit > pConfig->uMaxExtLeaf)
2152	{
2153	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2154	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2155	uLimit + 1, UINT32_C(0x800fffff));
2156	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2157	pCurLeaf->uEax = uLimit;
2158	}
2159	}
2160	else
2161	{
2162	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2163	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2164	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2165	}
2166	}
2167
2168	/*
2169	* Centaur leaves (VIA).
2170	*/
2171	uSubLeaf = 0;
2172	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2173	if (pCurLeaf)
2174	{
2175	uint32_t uLimit = pCurLeaf->uEax;
2176	if ( uLimit >= UINT32_C(0xc0000000)
2177	&& uLimit <= UINT32_C(0xc00fffff))
2178	{
2179	if (uLimit > pConfig->uMaxCentaurLeaf)
2180	{
2181	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2182	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2183	uLimit + 1, UINT32_C(0xcfffffff));
2184	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2185	pCurLeaf->uEax = uLimit;
2186	}
2187	}
2188	else
2189	{
2190	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2191	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2192	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2193	}
2194	}
2195	}
2196
2197
2198	/**
2199	* Clears a CPUID leaf and all sub-leaves (to zero).
2200	*
2201	* @param pCpum The CPUM instance data.
2202	* @param uLeaf The leaf to clear.
2203	*/
2204	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2205	{
2206	uint32_t uSubLeaf = 0;
2207	PCPUMCPUIDLEAF pCurLeaf;
2208	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2209	{
2210	pCurLeaf->uEax = 0;
2211	pCurLeaf->uEbx = 0;
2212	pCurLeaf->uEcx = 0;
2213	pCurLeaf->uEdx = 0;
2214	uSubLeaf++;
2215	}
2216	}
2217
2218
2219	/**
2220	* Sanitizes and adjust the CPUID leaves.
2221	*
2222	* Drop features that aren't virtualized (or virtualizable). Adjust information
2223	* and capabilities to fit the virtualized hardware. Remove information the
2224	* guest shouldn't have (because it's wrong in the virtual world or because it
2225	* gives away host details) or that we don't have documentation for and no idea
2226	* what means.
2227	*
2228	* @returns VBox status code.
2229	* @param pVM Pointer to the cross context VM structure (for cCpus).
2230	* @param pCpum The CPUM instance data.
2231	* @param pConfig The CPUID configuration we've read from CFGM.
2232	*/
2233	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2234	{
2235	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2236	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2237	{ \
2238	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2239	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2240	}
2241	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2242	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2243	{ \
2244	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2245	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2246	}
2247	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2248
2249	/* Cpuid 1:
2250	* EAX: CPU model, family and stepping.
2251	*
2252	* ECX + EDX: Supported features. Only report features we can support.
2253	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2254	* options may require adjusting (i.e. stripping what was enabled).
2255	*
2256	* EBX: Branding, CLFLUSH line size, logical processors per package and
2257	* initial APIC ID.
2258	*/
2259	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2260	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2261	AssertLogRelReturn(pStdFeatureLeaf->fSubLeafMask == 0, VERR_CPUM_IPE_2);
2262
2263	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2264	\| X86_CPUID_FEATURE_EDX_VME
2265	\| X86_CPUID_FEATURE_EDX_DE
2266	\| X86_CPUID_FEATURE_EDX_PSE
2267	\| X86_CPUID_FEATURE_EDX_TSC
2268	\| X86_CPUID_FEATURE_EDX_MSR
2269	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2270	\| X86_CPUID_FEATURE_EDX_MCE
2271	\| X86_CPUID_FEATURE_EDX_CX8
2272	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2273	//\| RT_BIT_32(10) - not defined
2274	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2275	//\| X86_CPUID_FEATURE_EDX_SEP
2276	\| X86_CPUID_FEATURE_EDX_MTRR
2277	\| X86_CPUID_FEATURE_EDX_PGE
2278	\| X86_CPUID_FEATURE_EDX_MCA
2279	\| X86_CPUID_FEATURE_EDX_CMOV
2280	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2281	\| X86_CPUID_FEATURE_EDX_PSE36
2282	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2283	\| X86_CPUID_FEATURE_EDX_CLFSH
2284	//\| RT_BIT_32(20) - not defined
2285	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2286	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2287	\| X86_CPUID_FEATURE_EDX_MMX
2288	\| X86_CPUID_FEATURE_EDX_FXSR
2289	\| X86_CPUID_FEATURE_EDX_SSE
2290	\| X86_CPUID_FEATURE_EDX_SSE2
2291	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2292	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading/cores - see below.
2293	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2294	//\| RT_BIT_32(30) - not defined
2295	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2296	;
2297	pStdFeatureLeaf->uEcx &= 0
2298	\| X86_CPUID_FEATURE_ECX_SSE3
2299	//\| X86_CPUID_FEATURE_ECX_PCLMUL - not implemented yet.
2300	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2301	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2302	\| ((pConfig->fMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2303	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2304	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized yet.
2305	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2306	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2307	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2308	\| X86_CPUID_FEATURE_ECX_SSSE3
2309	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2310	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2311	\| (pConfig->fCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2312	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2313	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2314	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2315	//\| X86_CPUID_FEATURE_ECX_PCID - not implemented yet.
2316	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2317	\| (pConfig->fSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2318	\| (pConfig->fSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2319	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2320	//\| X86_CPUID_FEATURE_ECX_MOVBE - not implemented yet.
2321	//\| X86_CPUID_FEATURE_ECX_POPCNT
2322	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2323	//\| X86_CPUID_FEATURE_ECX_AES - not implemented yet.
2324	//\| X86_CPUID_FEATURE_ECX_XSAVE - not implemented yet.
2325	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - not implemented yet.
2326	//\| X86_CPUID_FEATURE_ECX_AVX - not implemented yet.
2327	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2328	//\| X86_CPUID_FEATURE_ECX_RDRAND - not implemented yet.
2329	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2330	;
2331
2332	if (pCpum->u8PortableCpuIdLevel > 0)
2333	{
2334	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2335	PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2336	PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2337	PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1);
2338	PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2);
2339	PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16);
2340	PORTABLE_DISABLE_FEATURE_BIT(2, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2341	PORTABLE_DISABLE_FEATURE_BIT(3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2342	PORTABLE_DISABLE_FEATURE_BIT(3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2343	PORTABLE_DISABLE_FEATURE_BIT(3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2344
2345	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2346	\| X86_CPUID_FEATURE_EDX_PSN
2347	\| X86_CPUID_FEATURE_EDX_DS
2348	\| X86_CPUID_FEATURE_EDX_ACPI
2349	\| X86_CPUID_FEATURE_EDX_SS
2350	\| X86_CPUID_FEATURE_EDX_TM
2351	\| X86_CPUID_FEATURE_EDX_PBE
2352	)));
2353	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_PCLMUL
2354	\| X86_CPUID_FEATURE_ECX_DTES64
2355	\| X86_CPUID_FEATURE_ECX_CPLDS
2356	\| X86_CPUID_FEATURE_ECX_VMX
2357	\| X86_CPUID_FEATURE_ECX_SMX
2358	\| X86_CPUID_FEATURE_ECX_EST
2359	\| X86_CPUID_FEATURE_ECX_TM2
2360	\| X86_CPUID_FEATURE_ECX_CNTXID
2361	\| X86_CPUID_FEATURE_ECX_FMA
2362	\| X86_CPUID_FEATURE_ECX_CX16
2363	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2364	\| X86_CPUID_FEATURE_ECX_PDCM
2365	\| X86_CPUID_FEATURE_ECX_DCA
2366	\| X86_CPUID_FEATURE_ECX_MOVBE
2367	\| X86_CPUID_FEATURE_ECX_AES
2368	\| X86_CPUID_FEATURE_ECX_POPCNT
2369	\| X86_CPUID_FEATURE_ECX_XSAVE
2370	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2371	\| X86_CPUID_FEATURE_ECX_AVX
2372	)));
2373	}
2374
2375	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2376	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2377	#ifdef VBOX_WITH_MULTI_CORE
2378	if (pVM->cCpus > 1)
2379	{
2380	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2381	core times the number of CPU cores per processor */
2382	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2383	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
2384	}
2385	#endif
2386	pStdFeatureLeaf = NULL; /* Must refetch! */
2387
2388
2389	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2390	* AMD:
2391	* EAX: CPU model, family and stepping.
2392	*
2393	* ECX + EDX: Supported features. Only report features we can support.
2394	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2395	* options may require adjusting (i.e. stripping what was enabled).
2396	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2397	*
2398	* EBX: Branding ID and package type (or reserved).
2399	*
2400	* Intel and probably most others:
2401	* EAX: 0
2402	* EBX: 0
2403	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2404	*/
2405	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2406	if (pExtFeatureLeaf)
2407	{
2408	AssertLogRelReturn(pExtFeatureLeaf->fSubLeafMask == 0, VERR_CPUM_IPE_2);
2409
2410	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2411	\| X86_CPUID_AMD_FEATURE_EDX_VME
2412	\| X86_CPUID_AMD_FEATURE_EDX_DE
2413	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2414	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2415	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2416	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2417	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2418	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2419	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2420	//\| RT_BIT_32(10) - reserved
2421	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2422	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2423	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2424	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2425	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2426	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2427	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2428	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2429	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2430	//\| RT_BIT_32(18) - reserved
2431	//\| RT_BIT_32(19) - reserved
2432	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2433	//\| RT_BIT_32(21) - reserved
2434	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2435	\| X86_CPUID_AMD_FEATURE_EDX_MMX
2436	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
2437	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
2438	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2439	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2440	//\| RT_BIT_32(28) - reserved
2441	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2442	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2443	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
2444	;
2445	pExtFeatureLeaf->uEcx &= 0
2446	//\| X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2447	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2448	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
2449	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2450	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
2451	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2452	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
2453	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
2454	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
2455	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
2456	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2457	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
2458	//\| X86_CPUID_AMD_FEATURE_ECX_SSE5
2459	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2460	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
2461	//\| RT_BIT_32(14) - reserved
2462	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2463	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2464	//\| RT_BIT_32(17) - reserved
2465	//\| RT_BIT_32(18) - reserved
2466	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2467	//\| RT_BIT_32(20) - reserved
2468	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2469	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2470	//\| RT_BIT_32(23) - reserved
2471	//\| RT_BIT_32(24) - reserved
2472	//\| RT_BIT_32(25) - reserved
2473	//\| RT_BIT_32(26) - reserved
2474	//\| RT_BIT_32(27) - reserved
2475	//\| RT_BIT_32(28) - reserved
2476	//\| RT_BIT_32(29) - reserved
2477	//\| RT_BIT_32(30) - reserved
2478	//\| RT_BIT_32(31) - reserved
2479	;
2480	#ifdef VBOX_WITH_MULTI_CORE
2481	if ( pVM->cCpus > 1
2482	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2483	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2484	#endif
2485
2486	if (pCpum->u8PortableCpuIdLevel > 0)
2487	{
2488	PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2489	PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2490	PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2491	PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2492	PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2493	PORTABLE_DISABLE_FEATURE_BIT(2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2494	PORTABLE_DISABLE_FEATURE_BIT(3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2495
2496	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2497	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2498	\| X86_CPUID_AMD_FEATURE_ECX_CR8L
2499	\| X86_CPUID_AMD_FEATURE_ECX_ABM
2500	\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
2501	\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
2502	\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
2503	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2504	\| X86_CPUID_AMD_FEATURE_ECX_IBS
2505	\| X86_CPUID_AMD_FEATURE_ECX_SSE5
2506	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2507	\| X86_CPUID_AMD_FEATURE_ECX_WDT
2508	\| UINT32_C(0xffffc000)
2509	)));
2510	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2511	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2512	\| RT_BIT(18)
2513	\| RT_BIT(19)
2514	\| RT_BIT(21)
2515	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2516	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2517	\| RT_BIT(28)
2518	)));
2519	}
2520	}
2521	pExtFeatureLeaf = NULL; /* Must refetch! */
2522
2523
2524	/* Cpuid 2:
2525	* Intel: (Nondeterministic) Cache and TLB information
2526	* AMD: Reserved
2527	* VIA: Reserved
2528	* Safe to expose. Restrict the number of calls to 1 since we don't
2529	* implement this kind of subleaves (is there hardware that does??).
2530	*/
2531	uint32_t uSubLeaf = 0;
2532	PCPUMCPUIDLEAF pCurLeaf;
2533	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2534	{
2535	if ((pCurLeaf->uEax & 0xff) > 1)
2536	{
2537	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2538	pCurLeaf->uEax &= UINT32_C(0xffffff01);
2539	}
2540	uSubLeaf++;
2541	}
2542
2543	/* Cpuid 3:
2544	* Intel: EAX, EBX - reserved (transmeta uses these)
2545	* ECX, EDX - Processor Serial Number if available, otherwise reserved
2546	* AMD: Reserved
2547	* VIA: Reserved
2548	* Safe to expose
2549	*/
2550	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2551	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
2552	{
2553	uSubLeaf = 0;
2554	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
2555	{
2556	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2557	if (pCpum->u8PortableCpuIdLevel > 0)
2558	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2559	uSubLeaf++;
2560	}
2561	}
2562
2563	/* Cpuid 4 + ECX:
2564	* Intel: Deterministic Cache Parameters Leaf.
2565	* AMD: Reserved
2566	* VIA: Reserved
2567	* Safe to expose, except for EAX:
2568	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
2569	* Bits 31-26: Maximum number of processor cores in this physical package**
2570	* Note: These SMP values are constant regardless of ECX
2571	*/
2572	uSubLeaf = 0;
2573	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
2574	{
2575	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
2576	#ifdef VBOX_WITH_MULTI_CORE
2577	if ( pVM->cCpus > 1
2578	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2579	{
2580	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
2581	/* One logical processor with possibly multiple cores. */
2582	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
2583	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
2584	}
2585	#endif
2586	uSubLeaf++;
2587	}
2588
2589	/* Cpuid 5: Monitor/mwait Leaf
2590	* Intel: ECX, EDX - reserved
2591	* EAX, EBX - Smallest and largest monitor line size
2592	* AMD: EDX - reserved
2593	* EAX, EBX - Smallest and largest monitor line size
2594	* ECX - extensions (ignored for now)
2595	* VIA: Reserved
2596	* Safe to expose
2597	*/
2598	uSubLeaf = 0;
2599	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
2600	{
2601	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2602	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
2603	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2604
2605	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2606	if (pConfig->fMWaitExtensions)
2607	{
2608	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
2609	/** @todo: for now we just expose host's MWAIT C-states, although conceptually
2610	it shall be part of our power management virtualization model */
2611	#if 0
2612	/* MWAIT sub C-states */
2613	pCurLeaf->uEdx =
2614	(0 << 0) /* 0 in C0 */ \|
2615	(2 << 4) /* 2 in C1 */ \|
2616	(2 << 8) /* 2 in C2 */ \|
2617	(2 << 12) /* 2 in C3 */ \|
2618	(0 << 16) /* 0 in C4 */
2619	;
2620	#endif
2621	}
2622	else
2623	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2624	uSubLeaf++;
2625	}
2626
2627	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
2628	* Intel: Various stuff.
2629	* AMD: EAX, EBX, EDX - reserved.
2630	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
2631	* present. Same as intel.
2632	* VIA: ??
2633	*
2634	* We clear everything here for now.
2635	*/
2636	cpumR3CpuIdZeroLeaf(pCpum, 6);
2637
2638	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
2639	* EAX: Number of sub leaves.
2640	* EBX+ECX+EDX: Feature flags
2641	*
2642	* We only have documentation for one sub-leaf, so clear all other (no need
2643	* to remove them as such, just set them to zero).
2644	*
2645	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2646	* options may require adjusting (i.e. stripping what was enabled).
2647	*/
2648	uSubLeaf = 0;
2649	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
2650	{
2651	switch (uSubLeaf)
2652	{
2653	case 0:
2654	{
2655	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
2656	pCurLeaf->uEbx &= 0
2657	//\| X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
2658	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
2659	//\| RT_BIT(2) - reserved
2660	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
2661	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
2662	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT(5)
2663	//\| RT_BIT(6) - reserved
2664	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
2665	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
2666	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
2667	//\| X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
2668	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
2669	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
2670	//\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT(13)
2671	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
2672	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
2673	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
2674	//\| RT_BIT(17) - reserved
2675	//\| X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT(18)
2676	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
2677	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
2678	//\| RT_BIT(21) - reserved
2679	//\| RT_BIT(22) - reserved
2680	//\| X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT(23)
2681	//\| RT_BIT(24) - reserved
2682	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
2683	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
2684	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
2685	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
2686	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
2687	//\| RT_BIT(30) - reserved
2688	//\| RT_BIT(31) - reserved
2689	;
2690	pCurLeaf->uEcx &= 0
2691	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
2692	;
2693	pCurLeaf->uEdx &= 0;
2694
2695	if (pCpum->u8PortableCpuIdLevel > 0)
2696	{
2697	PORTABLE_DISABLE_FEATURE_BIT(2, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
2698	}
2699	break;
2700	}
2701
2702	default:
2703	/* Invalid index, all values are zero. */
2704	pCurLeaf->uEax = 0;
2705	pCurLeaf->uEbx = 0;
2706	pCurLeaf->uEcx = 0;
2707	pCurLeaf->uEdx = 0;
2708	break;
2709	}
2710	uSubLeaf++;
2711	}
2712
2713	/* Cpuid 8: Marked as reserved by Intel and AMD.
2714	* We zero this since we don't know what it may have been used for.
2715	*/
2716	cpumR3CpuIdZeroLeaf(pCpum, 8);
2717
2718	/* Cpuid 9: Direct Cache Access (DCA) Parameters
2719	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
2720	* EBX, ECX, EDX - reserved.
2721	* AMD: Reserved
2722	* VIA: ??
2723	*
2724	* We zero this.
2725	*/
2726	cpumR3CpuIdZeroLeaf(pCpum, 9);
2727
2728	/* Cpuid 0xa: Architectural Performance Monitor Features
2729	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
2730	* EBX, ECX, EDX - reserved.
2731	* AMD: Reserved
2732	* VIA: ??
2733	*
2734	* We zero this, for now at least.
2735	*/
2736	cpumR3CpuIdZeroLeaf(pCpum, 10);
2737
2738	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
2739	* Intel: EAX - APCI ID shift right for next level.
2740	* EBX - Factory configured cores/threads at this level.
2741	* ECX - Level number (same as input) and level type (1,2,0).
2742	* EDX - Extended initial APIC ID.
2743	* AMD: Reserved
2744	* VIA: ??
2745	*/
2746	uSubLeaf = 0;
2747	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
2748	{
2749	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
2750	{
2751	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
2752	if (bLevelType == 1)
2753	{
2754	/* Thread level - we don't do threads at the moment. */
2755	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
2756	pCurLeaf->uEbx = 1;
2757	}
2758	else if (bLevelType == 2)
2759	{
2760	/* Core level. */
2761	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
2762	#ifdef VBOX_WITH_MULTI_CORE
2763	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
2764	pCurLeaf->uEax++;
2765	#endif
2766	pCurLeaf->uEbx = pVM->cCpus;
2767	}
2768	else
2769	{
2770	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
2771	pCurLeaf->uEax = 0;
2772	pCurLeaf->uEbx = 0;
2773	pCurLeaf->uEcx = 0;
2774	}
2775	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
2776	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
2777	}
2778	else
2779	{
2780	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INTEL);
2781	pCurLeaf->uEax = 0;
2782	pCurLeaf->uEbx = 0;
2783	pCurLeaf->uEcx = 0;
2784	pCurLeaf->uEdx = 0;
2785	}
2786	uSubLeaf++;
2787	}
2788
2789	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
2790	* We zero this since we don't know what it may have been used for.
2791	*/
2792	cpumR3CpuIdZeroLeaf(pCpum, 12);
2793
2794	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
2795	* ECX=0: EAX - Valid bits in XCR0[31:0].
2796	* EBX - Maximum state size as per current XCR0 value.
2797	* ECX - Maximum state size for all supported features.
2798	* EDX - Valid bits in XCR0[63:32].
2799	* ECX=1: EAX - Various X-features.
2800	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
2801	* ECX - Valid bits in IA32_XSS[31:0].
2802	* EDX - Valid bits in IA32_XSS[63:32].
2803	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
2804	* if the bit invalid all four registers are set to zero.
2805	* EAX - The state size for this feature.
2806	* EBX - The state byte offset of this feature.
2807	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
2808	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
2809	*
2810	* Clear them all as we don't currently implement extended CPU state.
2811	*/
2812	uSubLeaf = 0;
2813	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf)) != NULL)
2814	{
2815	pCurLeaf->uEax = 0;
2816	pCurLeaf->uEbx = 0;
2817	pCurLeaf->uEcx = 0;
2818	pCurLeaf->uEdx = 0;
2819	uSubLeaf++;
2820	}
2821
2822	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
2823	* We zero this since we don't know what it may have been used for.
2824	*/
2825	cpumR3CpuIdZeroLeaf(pCpum, 14);
2826
2827	/* Cpuid 0xf + ECX: Platform qualifity of service monitoring (PQM).
2828	* We zero this as we don't currently virtualize PQM.
2829	*/
2830	cpumR3CpuIdZeroLeaf(pCpum, 15);
2831
2832	/* Cpuid 0x10 + ECX: Platform qualifity of service enforcement (PQE).
2833	* We zero this as we don't currently virtualize PQE.
2834	*/
2835	cpumR3CpuIdZeroLeaf(pCpum, 16);
2836
2837	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
2838	* We zero this since we don't know what it may have been used for.
2839	*/
2840	cpumR3CpuIdZeroLeaf(pCpum, 17);
2841
2842	/* Cpuid 0x12 + ECX: SGX resource enumeration.
2843	* We zero this as we don't currently virtualize this.
2844	*/
2845	cpumR3CpuIdZeroLeaf(pCpum, 18);
2846
2847	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
2848	* We zero this since we don't know what it may have been used for.
2849	*/
2850	cpumR3CpuIdZeroLeaf(pCpum, 19);
2851
2852	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
2853	* We zero this as we don't currently virtualize this.
2854	*/
2855	cpumR3CpuIdZeroLeaf(pCpum, 20);
2856
2857	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
2858	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
2859	* EAX - denominator (unsigned).
2860	* EBX - numerator (unsigned).
2861	* ECX, EDX - reserved.
2862	* AMD: Reserved / undefined / not implemented.
2863	* VIA: Reserved / undefined / not implemented.
2864	* We zero this as we don't currently virtualize this.
2865	*/
2866	cpumR3CpuIdZeroLeaf(pCpum, 21);
2867
2868	/* Cpuid 0x16: Processor frequency info
2869	* Intel: EAX - Core base frequency in MHz.
2870	* EBX - Core maximum frequency in MHz.
2871	* ECX - Bus (reference) frequency in MHz.
2872	* EDX - Reserved.
2873	* AMD: Reserved / undefined / not implemented.
2874	* VIA: Reserved / undefined / not implemented.
2875	* We zero this as we don't currently virtualize this.
2876	*/
2877	cpumR3CpuIdZeroLeaf(pCpum, 22);
2878
2879	/* Cpuid 0x17..0x10000000: Unknown.
2880	* We don't know these and what they mean, so remove them. */
2881	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2882	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
2883
2884
2885	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
2886	* We remove all these as we're a hypervisor and must provide our own.
2887	*/
2888	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2889	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
2890
2891
2892	/* Cpuid 0x80000000 is harmless. */
2893
2894	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
2895
2896	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
2897
2898	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
2899	* Safe to pass on to the guest.
2900	*
2901	* AMD: 0x800000005 L1 cache information
2902	* 0x800000006 L2/L3 cache information
2903	* Intel: 0x800000005 reserved
2904	* 0x800000006 L2 cache information
2905	* VIA: 0x800000005 TLB and L1 cache information
2906	* 0x800000006 L2 cache information
2907	*/
2908
2909	/* Cpuid 0x800000007: Advanced Power Management Information.
2910	* AMD: EAX: Processor feedback capabilities.
2911	* EBX: RAS capabilites.
2912	* ECX: Advanced power monitoring interface.
2913	* EDX: Enhanced power management capabilities.
2914	* Intel: EAX, EBX, ECX - reserved.
2915	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
2916	* VIA: Reserved
2917	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
2918	*/
2919	uSubLeaf = 0;
2920	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
2921	{
2922	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
2923	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2924	{
2925	pCurLeaf->uEdx &= 0
2926	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
2927	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
2928	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
2929	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
2930	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
2931	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
2932	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
2933	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
2934	#if 0 /*
2935	* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
2936	* Linux kernels blindly assume that the AMD performance counters work
2937	* if this is set for 64 bits guests. (Can't really find a CPUID feature
2938	* bit for them though.)
2939	*/
2940	/** @todo need to recheck this with new MSR emulation. */
2941	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
2942	#endif
2943	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
2944	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
2945	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
2946	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
2947	\| 0;
2948	}
2949	else
2950	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2951	if (pConfig->fInvariantTsc)
2952	pCurLeaf->uEdx \|= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2953	uSubLeaf++;
2954	}
2955
2956	/* Cpuid 0x80000008:
2957	* AMD: EBX, EDX - reserved
2958	* EAX: Virtual/Physical/Guest address Size
2959	* ECX: Number of cores + APICIdCoreIdSize
2960	* Intel: EAX: Virtual/Physical address Size
2961	* EBX, ECX, EDX - reserved
2962	* VIA: EAX: Virtual/Physical address Size
2963	* EBX, ECX, EDX - reserved
2964	*
2965	* We only expose the virtual+pysical address size to the guest atm.
2966	* On AMD we set the core count, but not the apic id stuff as we're
2967	* currently not doing the apic id assignments in a complatible manner.
2968	*/
2969	uSubLeaf = 0;
2970	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
2971	{
2972	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
2973	pCurLeaf->uEbx = 0; /* reserved */
2974	pCurLeaf->uEdx = 0; /* reserved */
2975
2976	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
2977	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
2978	pCurLeaf->uEcx = 0;
2979	#ifdef VBOX_WITH_MULTI_CORE
2980	if ( pVM->cCpus > 1
2981	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2982	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
2983	#endif
2984	uSubLeaf++;
2985	}
2986
2987	/* Cpuid 0x80000009: Reserved
2988	* We zero this since we don't know what it may have been used for.
2989	*/
2990	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
2991
2992	/* Cpuid 0x8000000a: SVM Information
2993	* AMD: EAX - SVM revision.
2994	* EBX - Number of ASIDs.
2995	* ECX - Reserved.
2996	* EDX - SVM Feature identification.
2997	* We clear all as we currently does not virtualize SVM.
2998	*/
2999	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3000
3001	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3002	* We clear these as we don't know what purpose they might have. */
3003	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3004	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3005
3006	/* Cpuid 0x80000019: TLB configuration
3007	* Seems to be harmless, pass them thru as is. */
3008
3009	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3010	* Strip anything we don't know what is or addresses feature we don't implement. */
3011	uSubLeaf = 0;
3012	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3013	{
3014	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3015	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3016	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3017	;
3018	pCurLeaf->uEbx = 0; /* reserved */
3019	pCurLeaf->uEcx = 0; /* reserved */
3020	pCurLeaf->uEdx = 0; /* reserved */
3021	uSubLeaf++;
3022	}
3023
3024	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3025	* Clear this as we don't currently virtualize this feature. */
3026	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3027
3028	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3029	* Clear this as we don't currently virtualize this feature. */
3030	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3031
3032	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3033	* We need to sanitize the cores per cache (EAX[25:14]).
3034	*
3035	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3036	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3037	* slightly different meaning.
3038	*/
3039	uSubLeaf = 0;
3040	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3041	{
3042	#ifdef VBOX_WITH_MULTI_CORE
3043	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3044	if (cCores > pVM->cCpus)
3045	cCores = pVM->cCpus;
3046	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3047	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3048	#else
3049	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3050	#endif
3051	uSubLeaf++;
3052	}
3053
3054	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3055	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3056	* setup, we have one compute unit with all the cores in it. Single node.
3057	*/
3058	uSubLeaf = 0;
3059	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3060	{
3061	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3062	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3063	{
3064	#ifdef VBOX_WITH_MULTI_CORE
3065	pCurLeaf->uEbx = pVM->cCpus < 0x100
3066	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3067	#else
3068	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3069	#endif
3070	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3071	}
3072	else
3073	{
3074	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3075	pCurLeaf->uEbx = 0; /* Reserved. */
3076	pCurLeaf->uEcx = 0; /* Reserved. */
3077	}
3078	pCurLeaf->uEdx = 0; /* Reserved. */
3079	uSubLeaf++;
3080	}
3081
3082	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3083	* We don't know these and what they mean, so remove them. */
3084	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3085	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3086
3087	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3088	* Just pass it thru for now. */
3089
3090	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3091	* Just pass it thru for now. */
3092
3093	/* Cpuid 0xc0000000: Centaur stuff.
3094	* Harmless, pass it thru. */
3095
3096	/* Cpuid 0xc0000001: Centaur features.
3097	* VIA: EAX - Family, model, stepping.
3098	* EDX - Centaur extended feature flags. Nothing interesting, except may
3099	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3100	* EBX, ECX - reserved.
3101	* We keep EAX but strips the rest.
3102	*/
3103	uSubLeaf = 0;
3104	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3105	{
3106	pCurLeaf->uEbx = 0;
3107	pCurLeaf->uEcx = 0;
3108	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3109	uSubLeaf++;
3110	}
3111
3112	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3113	* We only have fixed stale values, but should be harmless. */
3114
3115	/* Cpuid 0xc0000003: Reserved.
3116	* We zero this since we don't know what it may have been used for.
3117	*/
3118	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3119
3120	/* Cpuid 0xc0000004: Centaur Performance Info.
3121	* We only have fixed stale values, but should be harmless. */
3122
3123
3124	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3125	* We don't know these and what they mean, so remove them. */
3126	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3127	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3128
3129	return VINF_SUCCESS;
3130	#undef PORTABLE_DISABLE_FEATURE_BIT
3131	#undef PORTABLE_CLEAR_BITS_WHEN
3132	}
3133
3134
3135	static int cpumR3CpuIdReadConfig(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg)
3136	{
3137	int rc;
3138
3139	/** @cfgm{/CPUM/SyntheticCpu, boolean, false}
3140	* Enables the Synthetic CPU. The Vendor ID and Processor Name are
3141	* completely overridden by VirtualBox custom strings. Some
3142	* CPUID information is withheld, like the cache info.
3143	*
3144	* This is obsoleted by PortableCpuIdLevel. */
3145	rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pConfig->fSyntheticCpu, false);
3146	AssertRCReturn(rc, rc);
3147
3148	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3149	* When non-zero CPUID features that could cause portability issues will be
3150	* stripped. The higher the value the more features gets stripped. Higher
3151	* values should only be used when older CPUs are involved since it may
3152	* harm performance and maybe also cause problems with specific guests. */
3153	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCpum->u8PortableCpuIdLevel, pConfig->fSyntheticCpu ? 1 : 0);
3154	AssertLogRelRCReturn(rc, rc);
3155
3156	/** @cfgm{/CPUM/GuestCpuName, string}
3157	* The name of the CPU we're to emulate. The default is the host CPU.
3158	* Note! CPUs other than "host" one is currently unsupported. */
3159	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3160	AssertLogRelRCReturn(rc, rc);
3161
3162	/** @cfgm{/CPUM/CMPXCHG16B, boolean, false}
3163	* Expose CMPXCHG16B to the guest if supported by the host.
3164	*/
3165	rc = CFGMR3QueryBoolDef(pCpumCfg, "CMPXCHG16B", &pConfig->fCmpXchg16b, false);
3166	AssertLogRelRCReturn(rc, rc);
3167
3168	/** @cfgm{/CPUM/MONITOR, boolean, true}
3169	* Expose MONITOR/MWAIT instructions to the guest.
3170	*/
3171	rc = CFGMR3QueryBoolDef(pCpumCfg, "MONITOR", &pConfig->fMonitor, true);
3172	AssertLogRelRCReturn(rc, rc);
3173
3174	/** @cfgm{/CPUM/MWaitExtensions, boolean, false}
3175	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
3176	* break on interrupt feature (bit 1).
3177	*/
3178	rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &pConfig->fMWaitExtensions, false);
3179	AssertLogRelRCReturn(rc, rc);
3180
3181	/** @cfgm{/CPUM/SSE4.1, boolean, true}
3182	* Expose SSE4.1 to the guest if available.
3183	*/
3184	rc = CFGMR3QueryBoolDef(pCpumCfg, "SSE4.1", &pConfig->fSse41, true);
3185	AssertLogRelRCReturn(rc, rc);
3186
3187	/** @cfgm{/CPUM/SSE4.2, boolean, true}
3188	* Expose SSE4.2 to the guest if available.
3189	*/
3190	rc = CFGMR3QueryBoolDef(pCpumCfg, "SSE4.2", &pConfig->fSse42, true);
3191	AssertLogRelRCReturn(rc, rc);
3192
3193	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3194	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3195	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3196	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3197	*/
3198	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3199	AssertLogRelRCReturn(rc, rc);
3200
3201	/** @cfgm{/CPUM/InvariantTsc, boolean, complicated}
3202	* Set the invariant TSC flag in 0x80000007 if true, otherwas take default
3203	* action. By default the flag is passed thru as is from the host CPU, except
3204	* on AMD CPUs where it's suppressed to avoid trouble from linux assuming we
3205	* virtualize performance counters.
3206	*/
3207	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, false);
3208	AssertLogRelRCReturn(rc, rc);
3209
3210	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3211	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
3212	* probably going to be a temporary hack, so don't depend on this.
3213	* The 1st byte of the value is the stepping, the 2nd byte value is the model
3214	* number and the 3rd byte value is the family, and the 4th value must be zero.
3215	*/
3216	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3217	AssertLogRelRCReturn(rc, rc);
3218
3219	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3220	* The last standard leaf to keep. The actual last value that is stored in EAX
3221	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3222	* removed. (This works independently of and differently from NT4LeafLimit.)
3223	* The default is usually set to what we're able to reasonably sanitize.
3224	*/
3225	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3226	AssertLogRelRCReturn(rc, rc);
3227
3228	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3229	* The last extended leaf to keep. The actual last value that is stored in EAX
3230	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3231	* leaf are removed. The default is set to what we're able to sanitize.
3232	*/
3233	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3234	AssertLogRelRCReturn(rc, rc);
3235
3236	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3237	* The last extended leaf to keep. The actual last value that is stored in EAX
3238	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3239	* leaf are removed. The default is set to what we're able to sanitize.
3240	*/
3241	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3242	AssertLogRelRCReturn(rc, rc);
3243
3244	return VINF_SUCCESS;
3245	}
3246
3247
3248	/**
3249	* Initializes the emulated CPU's CPUID & MSR information.
3250	*
3251	* @returns VBox status code.
3252	* @param pVM Pointer to the VM.
3253	*/
3254	int cpumR3InitCpuIdAndMsrs(PVM pVM)
3255	{
3256	PCPUM pCpum = &pVM->cpum.s;
3257	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
3258
3259	/*
3260	* Read the configuration.
3261	*/
3262	CPUMCPUIDCONFIG Config;
3263	RT_ZERO(Config);
3264	int rc = cpumR3CpuIdReadConfig(pCpum, &Config, pCpumCfg);
3265	AssertRCReturn(rc, rc);
3266
3267	/*
3268	* Get the guest CPU data from the database and/or the host.
3269	*
3270	* The CPUID and MSRs are currently living on the regular heap to avoid
3271	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
3272	* API for the hyper heap). This means special cleanup considerations.
3273	*/
3274	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
3275	if (RT_FAILURE(rc))
3276	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
3277	? VMSetError(pVM, rc, RT_SRC_POS,
3278	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
3279	: rc;
3280
3281	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
3282	* Overrides the guest MSRs.
3283	*/
3284	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
3285
3286	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
3287	* Overrides the CPUID leaf values (from the host CPU usually) used for
3288	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
3289	* values when moving a VM to a different machine. Another use is restricting
3290	* (or extending) the feature set exposed to the guest. */
3291	if (RT_SUCCESS(rc))
3292	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
3293
3294	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
3295	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
3296	"Found unsupported configuration node '/CPUM/CPUID/'. "
3297	"Please use IMachine::setCPUIDLeaf() instead.");
3298
3299	/*
3300	* Pre-explode the CPUID info.
3301	*/
3302	if (RT_SUCCESS(rc))
3303	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
3304
3305	/*
3306	* Sanitize the cpuid information passed on to the guest.
3307	*/
3308	if (RT_SUCCESS(rc))
3309	{
3310	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
3311	if (RT_SUCCESS(rc))
3312	{
3313	cpumR3CpuIdLimitLeaves(pCpum, &Config);
3314	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
3315	}
3316	}
3317
3318	/*
3319	* Plant our own hypervisor CPUID leaves.
3320	*/
3321	if (RT_SUCCESS(rc))
3322	rc = cpumR3CpuIdPlantHypervisorLeaves(pCpum, &Config);
3323
3324	/*
3325	* MSR fudging.
3326	*/
3327	if (RT_SUCCESS(rc))
3328	{
3329	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
3330	* Fudges some common MSRs if not present in the selected CPU database entry.
3331	* This is for trying to keep VMs running when moved between different hosts
3332	* and different CPU vendors. */
3333	bool fEnable;
3334	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
3335	if (RT_SUCCESS(rc) && fEnable)
3336	{
3337	rc = cpumR3MsrApplyFudge(pVM);
3338	AssertLogRelRC(rc);
3339	}
3340	}
3341	if (RT_SUCCESS(rc))
3342	{
3343	/*
3344	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
3345	* guest CPU features again.
3346	*/
3347	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
3348	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
3349	pCpum->GuestInfo.cCpuIdLeaves);
3350	RTMemFree(pvFree);
3351
3352	pvFree = pCpum->GuestInfo.paMsrRangesR3;
3353	int rc2 = MMHyperDupMem(pVM, pvFree,
3354	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
3355	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
3356	RTMemFree(pvFree);
3357	AssertLogRelRCReturn(rc1, rc1);
3358	AssertLogRelRCReturn(rc2, rc2);
3359
3360	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
3361	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
3362	cpumR3MsrRegStats(pVM);
3363
3364
3365	/*
3366	* Some more configuration that we're applying at the end of everything
3367	* via the CPUMSetGuestCpuIdFeature API.
3368	*/
3369
3370	/* Check if PAE was explicitely enabled by the user. */
3371	bool fEnable;
3372	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
3373	AssertRCReturn(rc, rc);
3374	if (fEnable)
3375	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3376
3377	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
3378	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
3379	AssertRCReturn(rc, rc);
3380	if (fEnable)
3381	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3382
3383	/* We don't enable the Hypervisor Present bit by default, but it may be needed by some guests. */
3384	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false);
3385	AssertRCReturn(rc, rc);
3386	if (fEnable)
3387	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
3388
3389	return VINF_SUCCESS;
3390	}
3391
3392	/*
3393	* Failed before switching to hyper heap.
3394	*/
3395	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
3396	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
3397	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3398	pCpum->GuestInfo.paMsrRangesR3 = NULL;
3399	return rc;
3400	}
3401
3402
3403
3404	/*
3405	*
3406	*
3407	* Saved state related code.
3408	* Saved state related code.
3409	* Saved state related code.
3410	*
3411	*
3412	*/
3413
3414	/**
3415	* Called both in pass 0 and the final pass.
3416	*
3417	* @param pVM Pointer to the VM.
3418	* @param pSSM The saved state handle.
3419	*/
3420	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
3421	{
3422	/*
3423	* Save all the CPU ID leaves.
3424	*/
3425	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
3426	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
3427	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
3428	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
3429
3430	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
3431
3432	/*
3433	* Save a good portion of the raw CPU IDs as well as they may come in
3434	* handy when validating features for raw mode.
3435	*/
3436	CPUMCPUID aRawStd[16];
3437	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
3438	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
3439	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
3440	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
3441
3442	CPUMCPUID aRawExt[32];
3443	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
3444	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
3445	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
3446	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
3447	}
3448
3449
3450	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
3451	{
3452	uint32_t cCpuIds;
3453	int rc = SSMR3GetU32(pSSM, &cCpuIds);
3454	if (RT_SUCCESS(rc))
3455	{
3456	if (cCpuIds < 64)
3457	{
3458	for (uint32_t i = 0; i < cCpuIds; i++)
3459	{
3460	CPUMCPUID CpuId;
3461	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
3462	if (RT_FAILURE(rc))
3463	break;
3464
3465	CPUMCPUIDLEAF NewLeaf;
3466	NewLeaf.uLeaf = uBase + i;
3467	NewLeaf.uSubLeaf = 0;
3468	NewLeaf.fSubLeafMask = 0;
3469	NewLeaf.uEax = CpuId.uEax;
3470	NewLeaf.uEbx = CpuId.uEbx;
3471	NewLeaf.uEcx = CpuId.uEcx;
3472	NewLeaf.uEdx = CpuId.uEdx;
3473	NewLeaf.fFlags = 0;
3474	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
3475	}
3476	}
3477	else
3478	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3479	}
3480	if (RT_FAILURE(rc))
3481	{
3482	RTMemFree(*ppaLeaves);
3483	*ppaLeaves = NULL;
3484	*pcLeaves = 0;
3485	}
3486	return rc;
3487	}
3488
3489
3490	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
3491	{
3492	*ppaLeaves = NULL;
3493	*pcLeaves = 0;
3494
3495	int rc;
3496	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
3497	{
3498	/*
3499	* The new format. Starts by declaring the leave size and count.
3500	*/
3501	uint32_t cbLeaf;
3502	SSMR3GetU32(pSSM, &cbLeaf);
3503	uint32_t cLeaves;
3504	rc = SSMR3GetU32(pSSM, &cLeaves);
3505	if (RT_SUCCESS(rc))
3506	{
3507	if (cbLeaf == sizeof(**ppaLeaves))
3508	{
3509	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
3510	{
3511	/*
3512	* Load the leaves one by one.
3513	*
3514	* The uPrev stuff is a kludge for working around a week worth of bad saved
3515	* states during the CPUID revamp in March 2015. We saved too many leaves
3516	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
3517	* garbage entires at the end of the array when restoring. We also had
3518	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
3519	* this kludge doesn't deal correctly with that, but who cares...
3520	*/
3521	uint32_t uPrev = 0;
3522	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
3523	{
3524	CPUMCPUIDLEAF Leaf;
3525	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
3526	if (RT_SUCCESS(rc))
3527	{
3528	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
3529	\|\| Leaf.uLeaf >= uPrev)
3530	{
3531	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3532	uPrev = Leaf.uLeaf;
3533	}
3534	else
3535	uPrev = UINT32_MAX;
3536	}
3537	}
3538	}
3539	else
3540	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
3541	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
3542	}
3543	else
3544	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
3545	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
3546	}
3547	}
3548	else
3549	{
3550	/*
3551	* The old format with its three inflexible arrays.
3552	*/
3553	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
3554	if (RT_SUCCESS(rc))
3555	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
3556	if (RT_SUCCESS(rc))
3557	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
3558	if (RT_SUCCESS(rc))
3559	{
3560	/*
3561	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
3562	*/
3563	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
3564	if ( pLeaf
3565	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
3566	{
3567	CPUMCPUIDLEAF Leaf;
3568	Leaf.uLeaf = 4;
3569	Leaf.fSubLeafMask = UINT32_MAX;
3570	Leaf.uSubLeaf = 0;
3571	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
3572	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
3573	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
3574	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
3575	\| UINT32_C(63); /* system coherency line size - 1 */
3576	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
3577	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
3578	\| (UINT32_C(1) << 5) /* cache level */
3579	\| UINT32_C(1); /* cache type (data) */
3580	Leaf.fFlags = 0;
3581	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3582	if (RT_SUCCESS(rc))
3583	{
3584	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
3585	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3586	}
3587	if (RT_SUCCESS(rc))
3588	{
3589	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
3590	Leaf.uEcx = 4095; /* sets - 1 */
3591	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
3592	Leaf.uEbx \|= UINT32_C(23) << 22;
3593	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
3594	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
3595	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
3596	Leaf.uEax \|= UINT32_C(2) << 5;
3597	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3598	}
3599	}
3600	}
3601	}
3602	return rc;
3603	}
3604
3605
3606	/**
3607	* Loads the CPU ID leaves saved by pass 0, inner worker.
3608	*
3609	* @returns VBox status code.
3610	* @param pVM Pointer to the VM.
3611	* @param pSSM The saved state handle.
3612	* @param uVersion The format version.
3613	* @param paLeaves Guest CPUID leaves loaded from the state.
3614	* @param cLeaves The number of leaves in @a paLeaves.
3615	*/
3616	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
3617	{
3618	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
3619
3620	/*
3621	* Continue loading the state into stack buffers.
3622	*/
3623	CPUMCPUID GuestDefCpuId;
3624	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
3625	AssertRCReturn(rc, rc);
3626
3627	CPUMCPUID aRawStd[16];
3628	uint32_t cRawStd;
3629	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
3630	if (cRawStd > RT_ELEMENTS(aRawStd))
3631	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3632	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
3633	AssertRCReturn(rc, rc);
3634	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
3635	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
3636
3637	CPUMCPUID aRawExt[32];
3638	uint32_t cRawExt;
3639	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
3640	if (cRawExt > RT_ELEMENTS(aRawExt))
3641	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3642	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
3643	AssertRCReturn(rc, rc);
3644	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
3645	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
3646
3647	/*
3648	* Get the raw CPU IDs for the current host.
3649	*/
3650	CPUMCPUID aHostRawStd[16];
3651	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
3652	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
3653
3654	CPUMCPUID aHostRawExt[32];
3655	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
3656	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
3657	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
3658
3659	/*
3660	* Get the host and guest overrides so we don't reject the state because
3661	* some feature was enabled thru these interfaces.
3662	* Note! We currently only need the feature leaves, so skip rest.
3663	*/
3664	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
3665	CPUMCPUID aHostOverrideStd[2];
3666	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
3667	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
3668
3669	CPUMCPUID aHostOverrideExt[2];
3670	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
3671	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
3672
3673	/*
3674	* This can be skipped.
3675	*/
3676	bool fStrictCpuIdChecks;
3677	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
3678
3679	/*
3680	* Define a bunch of macros for simplifying the santizing/checking code below.
3681	*/
3682	/* Generic expression + failure message. */
3683	#define CPUID_CHECK_RET(expr, fmt) \
3684	do { \
3685	if (!(expr)) \
3686	{ \
3687	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
3688	if (fStrictCpuIdChecks) \
3689	{ \
3690	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
3691	RTStrFree(pszMsg); \
3692	return rcCpuid; \
3693	} \
3694	LogRel(("CPUM: %s\n", pszMsg)); \
3695	RTStrFree(pszMsg); \
3696	} \
3697	} while (0)
3698	#define CPUID_CHECK_WRN(expr, fmt) \
3699	do { \
3700	if (!(expr)) \
3701	LogRel(fmt); \
3702	} while (0)
3703
3704	/* For comparing two values and bitch if they differs. */
3705	#define CPUID_CHECK2_RET(what, host, saved) \
3706	do { \
3707	if ((host) != (saved)) \
3708	{ \
3709	if (fStrictCpuIdChecks) \
3710	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
3711	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
3712	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
3713	} \
3714	} while (0)
3715	#define CPUID_CHECK2_WRN(what, host, saved) \
3716	do { \
3717	if ((host) != (saved)) \
3718	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
3719	} while (0)
3720
3721	/* For checking raw cpu features (raw mode). */
3722	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
3723	do { \
3724	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
3725	{ \
3726	if (fStrictCpuIdChecks) \
3727	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
3728	N_(#bit " mismatch: host=%d saved=%d"), \
3729	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
3730	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
3731	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
3732	} \
3733	} while (0)
3734	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
3735	do { \
3736	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
3737	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
3738	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
3739	} while (0)
3740	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
3741
3742	/* For checking guest features. */
3743	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
3744	do { \
3745	if ( (aGuestCpuId##set [1].reg & bit) \
3746	&& !(aHostRaw##set [1].reg & bit) \
3747	&& !(aHostOverride##set [1].reg & bit) \
3748	) \
3749	{ \
3750	if (fStrictCpuIdChecks) \
3751	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
3752	N_(#bit " is not supported by the host but has already exposed to the guest")); \
3753	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
3754	} \
3755	} while (0)
3756	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
3757	do { \
3758	if ( (aGuestCpuId##set [1].reg & bit) \
3759	&& !(aHostRaw##set [1].reg & bit) \
3760	&& !(aHostOverride##set [1].reg & bit) \
3761	) \
3762	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
3763	} while (0)
3764	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
3765	do { \
3766	if ( (aGuestCpuId##set [1].reg & bit) \
3767	&& !(aHostRaw##set [1].reg & bit) \
3768	&& !(aHostOverride##set [1].reg & bit) \
3769	) \
3770	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
3771	} while (0)
3772	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
3773
3774	/* For checking guest features if AMD guest CPU. */
3775	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
3776	do { \
3777	if ( (aGuestCpuId##set [1].reg & bit) \
3778	&& fGuestAmd \
3779	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
3780	&& !(aHostOverride##set [1].reg & bit) \
3781	) \
3782	{ \
3783	if (fStrictCpuIdChecks) \
3784	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
3785	N_(#bit " is not supported by the host but has already exposed to the guest")); \
3786	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
3787	} \
3788	} while (0)
3789	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
3790	do { \
3791	if ( (aGuestCpuId##set [1].reg & bit) \
3792	&& fGuestAmd \
3793	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
3794	&& !(aHostOverride##set [1].reg & bit) \
3795	) \
3796	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
3797	} while (0)
3798	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
3799	do { \
3800	if ( (aGuestCpuId##set [1].reg & bit) \
3801	&& fGuestAmd \
3802	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
3803	&& !(aHostOverride##set [1].reg & bit) \
3804	) \
3805	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
3806	} while (0)
3807	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
3808
3809	/* For checking AMD features which have a corresponding bit in the standard
3810	range. (Intel defines very few bits in the extended feature sets.) */
3811	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
3812	do { \
3813	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
3814	&& !(fHostAmd \
3815	? aHostRawExt[1].reg & (ExtBit) \
3816	: aHostRawStd[1].reg & (StdBit)) \
3817	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
3818	) \
3819	{ \
3820	if (fStrictCpuIdChecks) \
3821	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
3822	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
3823	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
3824	} \
3825	} while (0)
3826	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
3827	do { \
3828	if ( (aGuestCpuId[1].reg & (ExtBit)) \
3829	&& !(fHostAmd \
3830	? aHostRawExt[1].reg & (ExtBit) \
3831	: aHostRawStd[1].reg & (StdBit)) \
3832	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
3833	) \
3834	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
3835	} while (0)
3836	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
3837	do { \
3838	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
3839	&& !(fHostAmd \
3840	? aHostRawExt[1].reg & (ExtBit) \
3841	: aHostRawStd[1].reg & (StdBit)) \
3842	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
3843	) \
3844	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
3845	} while (0)
3846	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
3847
3848	/*
3849	* For raw-mode we'll require that the CPUs are very similar since we don't
3850	* intercept CPUID instructions for user mode applications.
3851	*/
3852	if (!HMIsEnabled(pVM))
3853	{
3854	/* CPUID(0) */
3855	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
3856	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
3857	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
3858	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
3859	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
3860	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
3861	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
3862	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
3863	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
3864
3865	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
3866
3867	/* CPUID(1).eax */
3868	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
3869	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
3870	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
3871
3872	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
3873	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
3874	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
3875
3876	/* CPUID(1).ecx */
3877	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
3878	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
3879	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
3880	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
3881	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
3882	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
3883	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
3884	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
3885	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
3886	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
3887	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
3888	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
3889	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
3890	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
3891	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
3892	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
3893	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
3894	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
3895	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
3896	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
3897	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
3898	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
3899	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
3900	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
3901	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
3902	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
3903	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
3904	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
3905	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
3906	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
3907	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
3908	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
3909
3910	/* CPUID(1).edx */
3911	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
3912	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
3913	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
3914	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
3915	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
3916	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
3917	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
3918	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
3919	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
3920	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
3921	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
3922	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
3923	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
3924	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
3925	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
3926	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
3927	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
3928	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
3929	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
3930	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
3931	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
3932	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
3933	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
3934	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
3935	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
3936	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
3937	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
3938	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
3939	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
3940	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
3941	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
3942	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
3943
3944	/* CPUID(2) - config, mostly about caches. ignore. */
3945	/* CPUID(3) - processor serial number. ignore. */
3946	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
3947	/* CPUID(5) - mwait/monitor config. ignore. */
3948	/* CPUID(6) - power management. ignore. */
3949	/* CPUID(7) - ???. ignore. */
3950	/* CPUID(8) - ???. ignore. */
3951	/* CPUID(9) - DCA. ignore for now. */
3952	/* CPUID(a) - PeMo info. ignore for now. */
3953	/* CPUID(b) - topology info - takes ECX as input. ignore. */
3954
3955	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
3956	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
3957	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
3958	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
3959	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
3960	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
3961	{
3962	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
3963	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
3964	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
3965	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
3966	}
3967
3968	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
3969	Note! Intel have/is marking many of the fields here as reserved. We
3970	will verify them as if it's an AMD CPU. */
3971	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
3972	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
3973	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
3974	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
3975	{
3976	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
3977	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
3978	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
3979	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
3980	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
3981	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
3982	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
3983
3984	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
3985	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
3986	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
3987	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
3988	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
3989	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
3990
3991	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
3992	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
3993	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
3994	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
3995
3996	/* CPUID(0x80000001).ecx */
3997	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
3998	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
3999	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
4000	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
4001	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
4002	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
4003	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
4004	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
4005	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
4006	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
4007	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
4008	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
4009	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
4010	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
4011	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4012	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4013	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4014	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4015	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4016	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4017	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4018	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4019	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4020	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4021	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4022	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4023	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4024	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4025	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4026	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4027	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4028	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4029
4030	/* CPUID(0x80000001).edx */
4031	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
4032	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
4033	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
4034	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
4035	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
4036	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
4037	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
4038	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
4039	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
4040	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
4041	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4042	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
4043	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
4044	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
4045	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
4046	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
4047	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
4048	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
4049	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4050	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4051	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4052	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
4053	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4054	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
4055	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
4056	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4057	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4058	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4059	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
4060	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4061	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4062	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4063
4064	/** @todo verify the rest as well. */
4065	}
4066	}
4067
4068
4069
4070	/*
4071	* Verify that we can support the features already exposed to the guest on
4072	* this host.
4073	*
4074	* Most of the features we're emulating requires intercepting instruction
4075	* and doing it the slow way, so there is no need to warn when they aren't
4076	* present in the host CPU. Thus we use IGN instead of EMU on these.
4077	*
4078	* Trailing comments:
4079	* "EMU" - Possible to emulate, could be lots of work and very slow.
4080	* "EMU?" - Can this be emulated?
4081	*/
4082	CPUMCPUID aGuestCpuIdStd[2];
4083	RT_ZERO(aGuestCpuIdStd);
4084	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
4085
4086	/* CPUID(1).ecx */
4087	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
4088	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
4089	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
4090	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4091	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
4092	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
4093	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
4094	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
4095	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
4096	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
4097	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
4098	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
4099	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
4100	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
4101	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
4102	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
4103	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
4104	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4105	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
4106	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
4107	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
4108	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4109	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
4110	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
4111	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4112	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
4113	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
4114	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
4115	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
4116	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4117	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4118	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
4119
4120	/* CPUID(1).edx */
4121	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4122	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4123	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
4124	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4125	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4126	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4127	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4128	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4129	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4130	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4131	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
4132	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4133	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4134	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4135	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4136	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4137	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4138	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4139	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4140	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
4141	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
4142	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
4143	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
4144	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4145	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4146	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
4147	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
4148	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
4149	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
4150	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
4151	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
4152	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
4153
4154	/* CPUID(0x80000000). */
4155	CPUMCPUID aGuestCpuIdExt[2];
4156	RT_ZERO(aGuestCpuIdExt);
4157	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
4158	{
4159	/** @todo deal with no 0x80000001 on the host. */
4160	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
4161	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
4162
4163	/* CPUID(0x80000001).ecx */
4164	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
4165	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
4166	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
4167	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
4168	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
4169	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
4170	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
4171	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
4172	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
4173	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
4174	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
4175	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
4176	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
4177	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
4178	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4179	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4180	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4181	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4182	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4183	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4184	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4185	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4186	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4187	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4188	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4189	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4190	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4191	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4192	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4193	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4194	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4195	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4196
4197	/* CPUID(0x80000001).edx */
4198	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
4199	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
4200	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
4201	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
4202	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4203	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4204	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
4205	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
4206	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4207	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
4208	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4209	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
4210	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
4211	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
4212	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
4213	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4214	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
4215	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
4216	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4217	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4218	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4219	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
4220	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4221	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4222	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4223	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4224	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4225	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4226	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
4227	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4228	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4229	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4230	}
4231
4232	#undef CPUID_CHECK_RET
4233	#undef CPUID_CHECK_WRN
4234	#undef CPUID_CHECK2_RET
4235	#undef CPUID_CHECK2_WRN
4236	#undef CPUID_RAW_FEATURE_RET
4237	#undef CPUID_RAW_FEATURE_WRN
4238	#undef CPUID_RAW_FEATURE_IGN
4239	#undef CPUID_GST_FEATURE_RET
4240	#undef CPUID_GST_FEATURE_WRN
4241	#undef CPUID_GST_FEATURE_EMU
4242	#undef CPUID_GST_FEATURE_IGN
4243	#undef CPUID_GST_FEATURE2_RET
4244	#undef CPUID_GST_FEATURE2_WRN
4245	#undef CPUID_GST_FEATURE2_EMU
4246	#undef CPUID_GST_FEATURE2_IGN
4247	#undef CPUID_GST_AMD_FEATURE_RET
4248	#undef CPUID_GST_AMD_FEATURE_WRN
4249	#undef CPUID_GST_AMD_FEATURE_EMU
4250	#undef CPUID_GST_AMD_FEATURE_IGN
4251
4252	/*
4253	* We're good, commit the CPU ID leaves.
4254	*/
4255	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
4256	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
4257	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
4258	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
4259	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
4260	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
4261	AssertLogRelRCReturn(rc, rc);
4262
4263	return VINF_SUCCESS;
4264	}
4265
4266
4267	/**
4268	* Loads the CPU ID leaves saved by pass 0.
4269	*
4270	* @returns VBox status code.
4271	* @param pVM Pointer to the VM.
4272	* @param pSSM The saved state handle.
4273	* @param uVersion The format version.
4274	*/
4275	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
4276	{
4277	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4278
4279	/*
4280	* Load the CPUID leaves array first and call worker to do the rest, just so
4281	* we can free the memory when we need to without ending up in column 1000.
4282	*/
4283	PCPUMCPUIDLEAF paLeaves;
4284	uint32_t cLeaves;
4285	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
4286	AssertRC(rc);
4287	if (RT_SUCCESS(rc))
4288	{
4289	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
4290	RTMemFree(paLeaves);
4291	}
4292	return rc;
4293	}
4294
4295
4296
4297
4298	/*
4299	*
4300	*
4301	* CPUID Info Handler.
4302	* CPUID Info Handler.
4303	* CPUID Info Handler.
4304	*
4305	*
4306	*/
4307
4308
4309
4310	/**
4311	* Get L1 cache / TLS associativity.
4312	*/
4313	static const char getCacheAss(unsigned u, char pszBuf)
4314	{
4315	if (u == 0)
4316	return "res0 ";
4317	if (u == 1)
4318	return "direct";
4319	if (u == 255)
4320	return "fully";
4321	if (u >= 256)
4322	return "???";
4323
4324	RTStrPrintf(pszBuf, 16, "%d way", u);
4325	return pszBuf;
4326	}
4327
4328
4329	/**
4330	* Get L2 cache associativity.
4331	*/
4332	const char *getL2CacheAss(unsigned u)
4333	{
4334	switch (u)
4335	{
4336	case 0: return "off ";
4337	case 1: return "direct";
4338	case 2: return "2 way ";
4339	case 3: return "res3 ";
4340	case 4: return "4 way ";
4341	case 5: return "res5 ";
4342	case 6: return "8 way ";
4343	case 7: return "res7 ";
4344	case 8: return "16 way";
4345	case 9: return "res9 ";
4346	case 10: return "res10 ";
4347	case 11: return "res11 ";
4348	case 12: return "res12 ";
4349	case 13: return "res13 ";
4350	case 14: return "res14 ";
4351	case 15: return "fully ";
4352	default: return "????";
4353	}
4354	}
4355
4356
4357	/**
4358	* Display the guest CpuId leaves.
4359	*
4360	* @param pVM Pointer to the VM.
4361	* @param pHlp The info helper functions.
4362	* @param pszArgs "terse", "default" or "verbose".
4363	*/
4364	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4365	{
4366	/*
4367	* Parse the argument.
4368	*/
4369	unsigned iVerbosity = 1;
4370	if (pszArgs)
4371	{
4372	pszArgs = RTStrStripL(pszArgs);
4373	if (!strcmp(pszArgs, "terse"))
4374	iVerbosity--;
4375	else if (!strcmp(pszArgs, "verbose"))
4376	iVerbosity++;
4377	}
4378
4379	/*
4380	* Start cracking.
4381	*/
4382	CPUMCPUID Host;
4383	CPUMCPUID Guest;
4384	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax;
4385
4386	uint32_t cStdHstMax;
4387	uint32_t dummy;
4388	ASMCpuIdExSlow(0, 0, 0, 0, &cStdHstMax, &dummy, &dummy, &dummy);
4389
4390	unsigned cStdLstMax = RT_MAX(RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd), cStdHstMax);
4391
4392	pHlp->pfnPrintf(pHlp,
4393	" RAW Standard CPUIDs\n"
4394	" Function eax ebx ecx edx\n");
4395	for (unsigned i = 0; i <= cStdLstMax ; i++)
4396	{
4397	if (i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
4398	{
4399	Guest = pVM->cpum.s.aGuestCpuIdPatmStd[i];
4400	ASMCpuIdExSlow(i, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
4401
4402	pHlp->pfnPrintf(pHlp,
4403	"Gst: %08x %08x %08x %08x %08x%s\n"
4404	"Hst: %08x %08x %08x %08x\n",
4405	i, Guest.uEax, Guest.uEbx, Guest.uEcx, Guest.uEdx,
4406	i <= cStdMax ? "" : "*",
4407	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
4408	}
4409	else
4410	{
4411	ASMCpuIdExSlow(i, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
4412
4413	pHlp->pfnPrintf(pHlp,
4414	"Hst: %08x %08x %08x %08x %08x\n",
4415	i, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
4416	}
4417	}
4418
4419	/*
4420	* If verbose, decode it.
4421	*/
4422	if (iVerbosity)
4423	{
4424	Guest = pVM->cpum.s.aGuestCpuIdPatmStd[0];
4425	pHlp->pfnPrintf(pHlp,
4426	"Name: %.04s%.04s%.04s\n"
4427	"Supports: 0-%x\n",
4428	&Guest.uEbx, &Guest.uEdx, &Guest.uEcx, Guest.uEax);
4429	}
4430
4431	/*
4432	* Get Features.
4433	*/
4434	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
4435	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
4436	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
4437	if (cStdMax >= 1 && iVerbosity)
4438	{
4439	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
4440
4441	Guest = pVM->cpum.s.aGuestCpuIdPatmStd[1];
4442	uint32_t uEAX = Guest.uEax;
4443
4444	pHlp->pfnPrintf(pHlp,
4445	"Family: %d \tExtended: %d \tEffective: %d\n"
4446	"Model: %d \tExtended: %d \tEffective: %d\n"
4447	"Stepping: %d\n"
4448	"Type: %d (%s)\n"
4449	"APIC ID: %#04x\n"
4450	"Logical CPUs: %d\n"
4451	"CLFLUSH Size: %d\n"
4452	"Brand ID: %#04x\n",
4453	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
4454	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
4455	ASMGetCpuStepping(uEAX),
4456	(uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
4457	(Guest.uEbx >> 24) & 0xff,
4458	(Guest.uEbx >> 16) & 0xff,
4459	(Guest.uEbx >> 8) & 0xff,
4460	(Guest.uEbx >> 0) & 0xff);
4461	if (iVerbosity == 1)
4462	{
4463	uint32_t uEDX = Guest.uEdx;
4464	pHlp->pfnPrintf(pHlp, "Features EDX: ");
4465	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
4466	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
4467	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
4468	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
4469	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
4470	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
4471	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
4472	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
4473	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
4474	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
4475	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
4476	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
4477	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
4478	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
4479	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
4480	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
4481	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
4482	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
4483	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
4484	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
4485	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
4486	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
4487	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
4488	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
4489	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
4490	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
4491	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
4492	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
4493	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
4494	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
4495	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
4496	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
4497	pHlp->pfnPrintf(pHlp, "\n");
4498
4499	uint32_t uECX = Guest.uEcx;
4500	pHlp->pfnPrintf(pHlp, "Features ECX: ");
4501	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
4502	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
4503	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
4504	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
4505	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
4506	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
4507	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
4508	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
4509	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
4510	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
4511	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
4512	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
4513	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
4514	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
4515	if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
4516	if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
4517	if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
4518	if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
4519	if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
4520	if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
4521	if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
4522	if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
4523	if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
4524	if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
4525	if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
4526	if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
4527	if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
4528	if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
4529	if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
4530	if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " F16C");
4531	if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " RDRAND");
4532	if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " HVP");
4533	pHlp->pfnPrintf(pHlp, "\n");
4534	}
4535	else
4536	{
4537	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
4538
4539	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.uEdx;
4540	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.uEcx;
4541	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.uEdx;
4542	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.uEcx;
4543
4544	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
4545	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
4546	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
4547	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
4548	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
4549	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
4550	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
4551	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
4552	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
4553	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
4554	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
4555	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
4556	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
4557	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
4558	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
4559	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
4560	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
4561	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
4562	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
4563	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
4564	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
4565	pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
4566	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
4567	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
4568	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
4569	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
4570	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
4571	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
4572	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
4573	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
4574	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
4575	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
4576	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
4577
4578	pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
4579	pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
4580	pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
4581	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
4582	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
4583	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
4584	pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
4585	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
4586	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
4587	pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
4588	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
4589	pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
4590	pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
4591	pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
4592	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
4593	pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
4594	pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
4595	pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
4596	pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
4597	pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
4598	pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
4599	pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
4600	pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
4601	pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
4602	pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
4603	pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
4604	pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
4605	pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
4606	pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
4607	pHlp->pfnPrintf(pHlp, "16-bit floating point conversion instr = %d (%d)\n", EcxGuest.u1F16C, EcxHost.u1F16C);
4608	pHlp->pfnPrintf(pHlp, "RDRAND instruction = %d (%d)\n", EcxGuest.u1RDRAND, EcxHost.u1RDRAND);
4609	pHlp->pfnPrintf(pHlp, "Hypervisor Present (we're a guest) = %d (%d)\n", EcxGuest.u1HVP, EcxHost.u1HVP);
4610	}
4611	}
4612	if (cStdMax >= 2 && iVerbosity)
4613	{
4614	/** @todo */
4615	}
4616
4617	/*
4618	* Extended.
4619	* Implemented after AMD specs.
4620	*/
4621	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdPatmExt[0].uEax & 0xffff;
4622
4623	pHlp->pfnPrintf(pHlp,
4624	"\n"
4625	" RAW Extended CPUIDs\n"
4626	" Function eax ebx ecx edx\n");
4627	bool fSupportsInvariantTsc = false;
4628	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt); i++)
4629	{
4630	Guest = pVM->cpum.s.aGuestCpuIdPatmExt[i];
4631	ASMCpuIdExSlow(0x80000000 \| i, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
4632
4633	if ( i == 7
4634	&& (Host.uEdx & X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR))
4635	{
4636	fSupportsInvariantTsc = true;
4637	}
4638	pHlp->pfnPrintf(pHlp,
4639	"Gst: %08x %08x %08x %08x %08x%s\n"
4640	"Hst: %08x %08x %08x %08x\n",
4641	0x80000000 \| i, Guest.uEax, Guest.uEbx, Guest.uEcx, Guest.uEdx,
4642	i <= cExtMax ? "" : "*",
4643	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
4644	}
4645
4646	/*
4647	* Understandable output
4648	*/
4649	if (iVerbosity)
4650	{
4651	Guest = pVM->cpum.s.aGuestCpuIdPatmExt[0];
4652	pHlp->pfnPrintf(pHlp,
4653	"Ext Name: %.4s%.4s%.4s\n"
4654	"Ext Supports: 0x80000000-%#010x\n",
4655	&Guest.uEbx, &Guest.uEdx, &Guest.uEcx, Guest.uEax);
4656	}
4657
4658	if (iVerbosity && cExtMax >= 1)
4659	{
4660	Guest = pVM->cpum.s.aGuestCpuIdPatmExt[1];
4661	uint32_t uEAX = Guest.uEax;
4662	pHlp->pfnPrintf(pHlp,
4663	"Family: %d \tExtended: %d \tEffective: %d\n"
4664	"Model: %d \tExtended: %d \tEffective: %d\n"
4665	"Stepping: %d\n"
4666	"Brand ID: %#05x\n",
4667	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
4668	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
4669	ASMGetCpuStepping(uEAX),
4670	Guest.uEbx & 0xfff);
4671
4672	if (iVerbosity == 1)
4673	{
4674	uint32_t uEDX = Guest.uEdx;
4675	pHlp->pfnPrintf(pHlp, "Features EDX: ");
4676	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
4677	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
4678	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
4679	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
4680	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
4681	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
4682	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
4683	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
4684	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
4685	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
4686	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
4687	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
4688	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
4689	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
4690	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
4691	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
4692	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
4693	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
4694	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
4695	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
4696	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
4697	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
4698	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
4699	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
4700	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
4701	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
4702	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
4703	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
4704	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
4705	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
4706	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
4707	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
4708	pHlp->pfnPrintf(pHlp, "\n");
4709
4710	uint32_t uECX = Guest.uEcx;
4711	pHlp->pfnPrintf(pHlp, "Features ECX: ");
4712	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
4713	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
4714	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
4715	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
4716	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
4717	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
4718	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
4719	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
4720	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
4721	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
4722	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
4723	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
4724	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
4725	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
4726	for (unsigned iBit = 5; iBit < 32; iBit++)
4727	if (uECX & RT_BIT(iBit))
4728	pHlp->pfnPrintf(pHlp, " %d", iBit);
4729	pHlp->pfnPrintf(pHlp, "\n");
4730	}
4731	else
4732	{
4733	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
4734
4735	uint32_t uEdxGst = Guest.uEdx;
4736	uint32_t uEdxHst = Host.uEdx;
4737	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
4738	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
4739	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
4740	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
4741	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
4742	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
4743	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
4744	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
4745	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
4746	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
4747	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
4748	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
4749	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
4750	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
4751	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
4752	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
4753	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
4754	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
4755	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
4756	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
4757	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
4758	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
4759	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
4760	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
4761	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
4762	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
4763	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
4764	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
4765	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
4766	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
4767	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
4768	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
4769	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
4770
4771	uint32_t uEcxGst = Guest.uEcx;
4772	uint32_t uEcxHst = Host.uEcx;
4773	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
4774	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
4775	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
4776	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
4777	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
4778	pHlp->pfnPrintf(pHlp, "5 - Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
4779	pHlp->pfnPrintf(pHlp, "6 - SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
4780	pHlp->pfnPrintf(pHlp, "7 - Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
4781	pHlp->pfnPrintf(pHlp, "8 - PREFETCH and PREFETCHW instruction= %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
4782	pHlp->pfnPrintf(pHlp, "9 - OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
4783	pHlp->pfnPrintf(pHlp, "10 - Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
4784	pHlp->pfnPrintf(pHlp, "11 - SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
4785	pHlp->pfnPrintf(pHlp, "12 - SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
4786	pHlp->pfnPrintf(pHlp, "13 - Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
4787	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
4788	}
4789	}
4790
4791	if (iVerbosity && cExtMax >= 2)
4792	{
4793	char szString[443+1] = {0};
4794	uint32_t pu32 = (uint32_t )szString;
4795	*pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[2].uEax;
4796	*pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[2].uEbx;
4797	*pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[2].uEcx;
4798	*pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[2].uEdx;
4799	if (cExtMax >= 3)
4800	{
4801	*pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[3].uEax;
4802	*pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[3].uEbx;
4803	*pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[3].uEcx;
4804	*pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[3].uEdx;
4805	}
4806	if (cExtMax >= 4)
4807	{
4808	*pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[4].uEax;
4809	*pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[4].uEbx;
4810	*pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[4].uEcx;
4811	*pu32++ = pVM->cpum.s.aGuestCpuIdPatmExt[4].uEdx;
4812	}
4813	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
4814	}
4815
4816	if (iVerbosity && cExtMax >= 5)
4817	{
4818	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdPatmExt[5].uEax;
4819	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdPatmExt[5].uEbx;
4820	uint32_t uECX = pVM->cpum.s.aGuestCpuIdPatmExt[5].uEcx;
4821	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdPatmExt[5].uEdx;
4822	char sz1[32];
4823	char sz2[32];
4824
4825	pHlp->pfnPrintf(pHlp,
4826	"TLB 2/4M Instr/Uni: %s %3d entries\n"
4827	"TLB 2/4M Data: %s %3d entries\n",
4828	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
4829	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
4830	pHlp->pfnPrintf(pHlp,
4831	"TLB 4K Instr/Uni: %s %3d entries\n"
4832	"TLB 4K Data: %s %3d entries\n",
4833	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
4834	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
4835	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
4836	"L1 Instr Cache Lines Per Tag: %d\n"
4837	"L1 Instr Cache Associativity: %s\n"
4838	"L1 Instr Cache Size: %d KB\n",
4839	(uEDX >> 0) & 0xff,
4840	(uEDX >> 8) & 0xff,
4841	getCacheAss((uEDX >> 16) & 0xff, sz1),
4842	(uEDX >> 24) & 0xff);
4843	pHlp->pfnPrintf(pHlp,
4844	"L1 Data Cache Line Size: %d bytes\n"
4845	"L1 Data Cache Lines Per Tag: %d\n"
4846	"L1 Data Cache Associativity: %s\n"
4847	"L1 Data Cache Size: %d KB\n",
4848	(uECX >> 0) & 0xff,
4849	(uECX >> 8) & 0xff,
4850	getCacheAss((uECX >> 16) & 0xff, sz1),
4851	(uECX >> 24) & 0xff);
4852	}
4853
4854	if (iVerbosity && cExtMax >= 6)
4855	{
4856	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdPatmExt[6].uEax;
4857	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdPatmExt[6].uEbx;
4858	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdPatmExt[6].uEdx;
4859
4860	pHlp->pfnPrintf(pHlp,
4861	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
4862	"L2 TLB 2/4M Data: %s %4d entries\n",
4863	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
4864	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
4865	pHlp->pfnPrintf(pHlp,
4866	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
4867	"L2 TLB 4K Data: %s %4d entries\n",
4868	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
4869	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
4870	pHlp->pfnPrintf(pHlp,
4871	"L2 Cache Line Size: %d bytes\n"
4872	"L2 Cache Lines Per Tag: %d\n"
4873	"L2 Cache Associativity: %s\n"
4874	"L2 Cache Size: %d KB\n",
4875	(uEDX >> 0) & 0xff,
4876	(uEDX >> 8) & 0xf,
4877	getL2CacheAss((uEDX >> 12) & 0xf),
4878	(uEDX >> 16) & 0xffff);
4879	}
4880
4881	if (iVerbosity && cExtMax >= 7)
4882	{
4883	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdPatmExt[7].uEdx;
4884
4885	pHlp->pfnPrintf(pHlp, "Host Invariant-TSC support: %RTbool\n", fSupportsInvariantTsc);
4886	pHlp->pfnPrintf(pHlp, "APM Features: ");
4887	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
4888	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
4889	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
4890	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
4891	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
4892	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
4893	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " MC");
4894	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " HWPSTATE");
4895	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TscInvariant");
4896	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " CPB");
4897	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " EffFreqRO");
4898	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PFI");
4899	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PA");
4900	for (unsigned iBit = 13; iBit < 32; iBit++)
4901	if (uEDX & RT_BIT(iBit))
4902	pHlp->pfnPrintf(pHlp, " %d", iBit);
4903	pHlp->pfnPrintf(pHlp, "\n");
4904	}
4905
4906	if (iVerbosity && cExtMax >= 8)
4907	{
4908	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdPatmExt[8].uEax;
4909	uint32_t uECX = pVM->cpum.s.aGuestCpuIdPatmExt[8].uEcx;
4910
4911	pHlp->pfnPrintf(pHlp,
4912	"Physical Address Width: %d bits\n"
4913	"Virtual Address Width: %d bits\n"
4914	"Guest Physical Address Width: %d bits\n",
4915	(uEAX >> 0) & 0xff,
4916	(uEAX >> 8) & 0xff,
4917	(uEAX >> 16) & 0xff);
4918	pHlp->pfnPrintf(pHlp,
4919	"Physical Core Count: %d\n",
4920	(uECX >> 0) & 0xff);
4921	}
4922
4923
4924	/*
4925	* Hypervisor leaves.
4926	*
4927	* Unlike most of the other leaves reported, the guest hypervisor leaves
4928	* aren't a subset of the host CPUID bits.
4929	*/
4930	RT_ZERO(Host);
4931	if (cStdHstMax >= 1)
4932	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
4933	bool fHostHvp = RT_BOOL(Host.uEcx & X86_CPUID_FEATURE_ECX_HVP);
4934	bool fGuestHvp = false;
4935	if (cStdMax >= 1)
4936	{
4937	Guest = pVM->cpum.s.aGuestCpuIdPatmStd[1];
4938	fGuestHvp = RT_BOOL(Guest.uEcx & X86_CPUID_FEATURE_ECX_HVP);
4939	}
4940
4941	if ( fHostHvp
4942	\|\| fGuestHvp)
4943	{
4944	uint32_t const uHyperLeaf = 0x40000000;
4945	pHlp->pfnPrintf(pHlp,
4946	"\n"
4947	" Hypervisor CPUIDs\n"
4948	" Function eax ebx ecx edx\n");
4949
4950	PCCPUMCPUIDLEAF pHyperLeafGst = NULL;
4951	if (fGuestHvp)
4952	{
4953	pHyperLeafGst = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
4954	uHyperLeaf, 0 /* uSubLeaf */);
4955	}
4956
4957	RT_ZERO(Host);
4958	if (fHostHvp)
4959	ASMCpuIdExSlow(uHyperLeaf, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
4960
4961	CPUMCPUIDLEAF GuestLeaf;
4962	uint32_t const cHyperGstMax = pHyperLeafGst ? pHyperLeafGst->uEax : 0;
4963	uint32_t const cHyperHstMax = Host.uEax;
4964	uint32_t const cHyperMax = RT_MAX(cHyperHstMax, cHyperGstMax);
4965	for (uint32_t i = uHyperLeaf; i <= cHyperMax; i++)
4966	{
4967	RT_ZERO(Host);
4968	RT_ZERO(GuestLeaf);
4969	if (i <= cHyperHstMax)
4970	ASMCpuIdExSlow(i, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
4971	CPUMR3CpuIdGetLeaf(pVM, &GuestLeaf, i, 0 /* uSubLeaf */);
4972	if (!fHostHvp)
4973	{
4974	pHlp->pfnPrintf(pHlp,
4975	"Gst: %08x %08x %08x %08x %08x\n",
4976	i, GuestLeaf.uEax, GuestLeaf.uEbx, GuestLeaf.uEcx, GuestLeaf.uEdx);
4977	}
4978	else
4979	{
4980	pHlp->pfnPrintf(pHlp,
4981	"Gst: %08x %08x %08x %08x %08x%s\n"
4982	"Hst: %08x %08x %08x %08x%s\n",
4983	i, GuestLeaf.uEax, GuestLeaf.uEbx, GuestLeaf.uEcx, GuestLeaf.uEdx,
4984	i <= cHyperGstMax ? "" : "*",
4985	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx, i <= cHyperHstMax ? "" : "*");
4986	}
4987	}
4988	}
4989
4990	/*
4991	* Centaur.
4992	*/
4993	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdPatmCentaur[0].uEax & 0xffff;
4994
4995	pHlp->pfnPrintf(pHlp,
4996	"\n"
4997	" RAW Centaur CPUIDs\n"
4998	" Function eax ebx ecx edx\n");
4999	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur); i++)
5000	{
5001	Guest = pVM->cpum.s.aGuestCpuIdPatmCentaur[i];
5002	ASMCpuIdExSlow(0xc0000000 \| i, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5003
5004	pHlp->pfnPrintf(pHlp,
5005	"Gst: %08x %08x %08x %08x %08x%s\n"
5006	"Hst: %08x %08x %08x %08x\n",
5007	0xc0000000 \| i, Guest.uEax, Guest.uEbx, Guest.uEcx, Guest.uEdx,
5008	i <= cCentaurMax ? "" : "*",
5009	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5010	}
5011
5012	/*
5013	* Understandable output
5014	*/
5015	if (iVerbosity)
5016	{
5017	Guest = pVM->cpum.s.aGuestCpuIdPatmCentaur[0];
5018	pHlp->pfnPrintf(pHlp,
5019	"Centaur Supports: 0xc0000000-%#010x\n",
5020	Guest.uEax);
5021	}
5022
5023	if (iVerbosity && cCentaurMax >= 1)
5024	{
5025	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5026	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdPatmCentaur[1].uEdx;
5027	uint32_t uEdxHst = Host.uEdx;
5028
5029	if (iVerbosity == 1)
5030	{
5031	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
5032	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
5033	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
5034	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
5035	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
5036	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
5037	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
5038	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
5039	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
5040	/* possibly indicating MM/HE and MM/HE-E on older chips... */
5041	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
5042	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
5043	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
5044	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
5045	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
5046	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
5047	for (unsigned iBit = 14; iBit < 32; iBit++)
5048	if (uEdxGst & RT_BIT(iBit))
5049	pHlp->pfnPrintf(pHlp, " %d", iBit);
5050	pHlp->pfnPrintf(pHlp, "\n");
5051	}
5052	else
5053	{
5054	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
5055	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
5056	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
5057	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
5058	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
5059	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
5060	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
5061	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
5062	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
5063	/* possibly indicating MM/HE and MM/HE-E on older chips... */
5064	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
5065	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
5066	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
5067	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
5068	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
5069	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
5070	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
5071	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
5072	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
5073	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
5074	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
5075	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
5076	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
5077	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
5078	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
5079	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
5080	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
5081	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
5082	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
5083	for (unsigned iBit = 27; iBit < 32; iBit++)
5084	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
5085	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
5086	pHlp->pfnPrintf(pHlp, "\n");
5087	}
5088	}
5089	}
5090
5091
5092
5093
5094
5095	/*
5096	*
5097	*
5098	* PATM interfaces.
5099	* PATM interfaces.
5100	* PATM interfaces.
5101	*
5102	*
5103	*/
5104
5105
5106	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
5107	/** @name Patchmanager CPUID legacy table APIs
5108	* @{
5109	*/
5110
5111	/**
5112	* Gets a pointer to the default CPUID leaf.
5113	*
5114	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
5115	* @param pVM Pointer to the VM.
5116	* @remark Intended for PATM only.
5117	*/
5118	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
5119	{
5120	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
5121	}
5122
5123
5124	/**
5125	* Gets a number of standard CPUID leaves (PATM only).
5126	*
5127	* @returns Number of leaves.
5128	* @param pVM Pointer to the VM.
5129	* @remark Intended for PATM - legacy, don't use in new code.
5130	*/
5131	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
5132	{
5133	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
5134	}
5135
5136
5137	/**
5138	* Gets a number of extended CPUID leaves (PATM only).
5139	*
5140	* @returns Number of leaves.
5141	* @param pVM Pointer to the VM.
5142	* @remark Intended for PATM - legacy, don't use in new code.
5143	*/
5144	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
5145	{
5146	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
5147	}
5148
5149
5150	/**
5151	* Gets a number of centaur CPUID leaves.
5152	*
5153	* @returns Number of leaves.
5154	* @param pVM Pointer to the VM.
5155	* @remark Intended for PATM - legacy, don't use in new code.
5156	*/
5157	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
5158	{
5159	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
5160	}
5161
5162
5163	/**
5164	* Gets a pointer to the array of standard CPUID leaves.
5165	*
5166	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
5167	*
5168	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
5169	* @param pVM Pointer to the VM.
5170	* @remark Intended for PATM - legacy, don't use in new code.
5171	*/
5172	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
5173	{
5174	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
5175	}
5176
5177
5178	/**
5179	* Gets a pointer to the array of extended CPUID leaves.
5180	*
5181	* CPUMGetGuestCpuIdExtMax() give the size of the array.
5182	*
5183	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
5184	* @param pVM Pointer to the VM.
5185	* @remark Intended for PATM - legacy, don't use in new code.
5186	*/
5187	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
5188	{
5189	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
5190	}
5191
5192
5193	/**
5194	* Gets a pointer to the array of centaur CPUID leaves.
5195	*
5196	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
5197	*
5198	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
5199	* @param pVM Pointer to the VM.
5200	* @remark Intended for PATM - legacy, don't use in new code.
5201	*/
5202	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
5203	{
5204	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
5205	}
5206
5207	/** @} */
5208	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
5209
5210	#endif /* VBOX_IN_VMM */
5211

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 54799

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