VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 54985

Last change on this file since 54985 was 54958, checked in by vboxsync, 10 years ago

CPUMR3CpuId: Fixed typos. Thank you Jung-uk Kim.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 265.4 KB
Line 
1/* $Id: CPUMR3CpuId.cpp 54958 2015-03-26 07:59:06Z vboxsync $ */
2/** @file
3 * CPUM - CPU ID part.
4 */
5
6/*
7 * Copyright (C) 2013-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_CPUM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/dbgf.h>
24#include <VBox/vmm/hm.h>
25#include <VBox/vmm/ssm.h>
26#include "CPUMInternal.h"
27#include <VBox/vmm/vm.h>
28#include <VBox/vmm/mm.h>
29
30#include <VBox/err.h>
31#include <iprt/asm-amd64-x86.h>
32#include <iprt/ctype.h>
33#include <iprt/mem.h>
34#include <iprt/string.h>
35
36
37/*******************************************************************************
38* Defined Constants And Macros *
39*******************************************************************************/
40/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
41#define CPUM_CPUID_MAX_LEAVES 2048
42
43
44/*******************************************************************************
45* Global Variables *
46*******************************************************************************/
47/**
48 * The intel pentium family.
49 */
50static const CPUMMICROARCH g_aenmIntelFamily06[] =
51{
52 /* [ 0(0x00)] = */ kCpumMicroarch_Intel_P6, /* Pentium Pro A-step (says sandpile.org). */
53 /* [ 1(0x01)] = */ kCpumMicroarch_Intel_P6, /* Pentium Pro */
54 /* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
55 /* [ 3(0x03)] = */ kCpumMicroarch_Intel_P6_II, /* PII Klamath */
56 /* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
57 /* [ 5(0x05)] = */ kCpumMicroarch_Intel_P6_II, /* PII Deschutes */
58 /* [ 6(0x06)] = */ kCpumMicroarch_Intel_P6_II, /* Celeron Mendocino. */
59 /* [ 7(0x07)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Katmai. */
60 /* [ 8(0x08)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Coppermine (includes Celeron). */
61 /* [ 9(0x09)] = */ kCpumMicroarch_Intel_P6_M_Banias, /* Pentium/Celeron M Banias. */
62 /* [10(0x0a)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Xeon */
63 /* [11(0x0b)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Tualatin (includes Celeron). */
64 /* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
65 /* [13(0x0d)] = */ kCpumMicroarch_Intel_P6_M_Dothan, /* Pentium/Celeron M Dothan. */
66 /* [14(0x0e)] = */ kCpumMicroarch_Intel_Core_Yonah, /* Core Yonah (Enhanced Pentium M). */
67 /* [15(0x0f)] = */ kCpumMicroarch_Intel_Core2_Merom, /* Merom */
68 /* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
69 /* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
70 /* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
71 /* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
72 /* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
73 /* [21(0x15)] = */ kCpumMicroarch_Intel_P6_M_Dothan, /* Tolapai - System-on-a-chip. */
74 /* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
75 /* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
76 /* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
77 /* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
78 /* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
79 /* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
80 /* [28(0x1c)] = */ kCpumMicroarch_Intel_Atom_Bonnell, /* Diamonville, Pineview, */
81 /* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
82 /* [30(0x1e)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Clarksfield, Lynnfield, Jasper Forest. */
83 /* [31(0x1f)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
84 /* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
85 /* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
86 /* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
87 /* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
88 /* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
89 /* [37(0x25)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Arrandale, Clarksdale. */
90 /* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
91 /* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
92 /* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
93 /* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
94 /* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
95 /* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
96 /* [44(0x2c)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Gulftown, Westmere-EP. */
97 /* [45(0x2d)] = */ kCpumMicroarch_Intel_Core7_SandyBridge, /* SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
98 /* [46(0x2e)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Beckton (Xeon). */
99 /* [47(0x2f)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Westmere-EX. */
100 /* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
101 /* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
102 /* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
103 /* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
104 /* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
105 /* [53(0x35)] = */ kCpumMicroarch_Intel_Atom_Saltwell, /* ?? */
106 /* [54(0x36)] = */ kCpumMicroarch_Intel_Atom_Saltwell, /* Cedarview, ++ */
107 /* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
108 /* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
109 /* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
110 /* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
111 /* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
112 /* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
113 /* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
114 /* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
115 /* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
116 /* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
117 /* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
118 /* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
119 /* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
120 /* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
121 /* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
122 /* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123 /* [71(0x47)] = */ kCpumMicroarch_Intel_Unknown,
124 /* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
125 /* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
126 /* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
127 /* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
128 /* [76(0x4c)] = */ kCpumMicroarch_Intel_Unknown,
129 /* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
130 /* [78(0x4e)] = */ kCpumMicroarch_Intel_Unknown,
131 /* [79(0x4f)] = */ kCpumMicroarch_Intel_Unknown,
132};
133
134
135
136/**
137 * Figures out the (sub-)micro architecture given a bit of CPUID info.
138 *
139 * @returns Micro architecture.
140 * @param enmVendor The CPU vendor .
141 * @param bFamily The CPU family.
142 * @param bModel The CPU model.
143 * @param bStepping The CPU stepping.
144 */
145VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
146 uint8_t bModel, uint8_t bStepping)
147{
148 if (enmVendor == CPUMCPUVENDOR_AMD)
149 {
150 switch (bFamily)
151 {
152 case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
153 case 0x03: return kCpumMicroarch_AMD_Am386;
154 case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
155 case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
156 case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
157 case 0x06:
158 switch (bModel)
159 {
160 case 0: return kCpumMicroarch_AMD_K7_Palomino;
161 case 1: return kCpumMicroarch_AMD_K7_Palomino;
162 case 2: return kCpumMicroarch_AMD_K7_Palomino;
163 case 3: return kCpumMicroarch_AMD_K7_Spitfire;
164 case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
165 case 6: return kCpumMicroarch_AMD_K7_Palomino;
166 case 7: return kCpumMicroarch_AMD_K7_Morgan;
167 case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
168 case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
169 }
170 return kCpumMicroarch_AMD_K7_Unknown;
171 case 0x0f:
172 /*
173 * This family is a friggin mess. Trying my best to make some
174 * sense out of it. Too much happened in the 0x0f family to
175 * lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
176 *
177 * Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
178 * cpu-world.com, and other places:
179 * - 130nm:
180 * - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
181 * - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
182 * - Newcastle: FC0/DH-CG (errum #180: FE0/DH-CG), FF0/DH-CG
183 * - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
184 * - Odessa: FC0/DH-CG (errum #180: FE0/DH-CG)
185 * - Paris: FF0/DH-CG, FC0/DH-CG (errum #180: FE0/DH-CG),
186 * - 90nm:
187 * - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
188 * - Oakville: 10FC0/DH-D0.
189 * - Georgetown: 10FC0/DH-D0.
190 * - Sonora: 10FC0/DH-D0.
191 * - Venus: 20F71/SH-E4
192 * - Troy: 20F51/SH-E4
193 * - Athens: 20F51/SH-E4
194 * - San Diego: 20F71/SH-E4.
195 * - Lancaster: 20F42/SH-E5
196 * - Newark: 20F42/SH-E5.
197 * - Albany: 20FC2/DH-E6.
198 * - Roma: 20FC2/DH-E6.
199 * - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
200 * - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
201 * - 90nm introducing Dual core:
202 * - Denmark: 20F30/JH-E1, 20F32/JH-E6
203 * - Italy: 20F10/JH-E1, 20F12/JH-E6
204 * - Egypt: 20F10/JH-E1, 20F12/JH-E6
205 * - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
206 * - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
207 * - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
208 * - Santa Ana: 40F32/JH-F2, /-F3
209 * - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
210 * - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
211 * - Manila: 50FF2/DH-F2, 40FF2/DH-F2
212 * - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
213 * - Keene: 40FC2/DH-F2.
214 * - Richmond: 40FC2/DH-F2
215 * - Taylor: 40F82/BH-F2
216 * - Trinidad: 40F82/BH-F2
217 *
218 * - 65nm:
219 * - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
220 * - Tyler: 60F81/BH-G1, 60F82/BH-G2.
221 * - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
222 * - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
223 * - Sherman: /-G1, 70FC2/DH-G2.
224 * - Huron: 70FF2/DH-G2.
225 */
226 if (bModel < 0x10)
227 return kCpumMicroarch_AMD_K8_130nm;
228 if (bModel >= 0x60 && bModel < 0x80)
229 return kCpumMicroarch_AMD_K8_65nm;
230 if (bModel >= 0x40)
231 return kCpumMicroarch_AMD_K8_90nm_AMDV;
232 switch (bModel)
233 {
234 case 0x21:
235 case 0x23:
236 case 0x2b:
237 case 0x2f:
238 case 0x37:
239 case 0x3f:
240 return kCpumMicroarch_AMD_K8_90nm_DualCore;
241 }
242 return kCpumMicroarch_AMD_K8_90nm;
243 case 0x10:
244 return kCpumMicroarch_AMD_K10;
245 case 0x11:
246 return kCpumMicroarch_AMD_K10_Lion;
247 case 0x12:
248 return kCpumMicroarch_AMD_K10_Llano;
249 case 0x14:
250 return kCpumMicroarch_AMD_Bobcat;
251 case 0x15:
252 switch (bModel)
253 {
254 case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
255 case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
256 case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
257 case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
258 case 0x11: /* ?? */
259 case 0x12: /* ?? */
260 case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
261 }
262 return kCpumMicroarch_AMD_15h_Unknown;
263 case 0x16:
264 return kCpumMicroarch_AMD_Jaguar;
265
266 }
267 return kCpumMicroarch_AMD_Unknown;
268 }
269
270 if (enmVendor == CPUMCPUVENDOR_INTEL)
271 {
272 switch (bFamily)
273 {
274 case 3:
275 return kCpumMicroarch_Intel_80386;
276 case 4:
277 return kCpumMicroarch_Intel_80486;
278 case 5:
279 return kCpumMicroarch_Intel_P5;
280 case 6:
281 if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
282 return g_aenmIntelFamily06[bModel];
283 return kCpumMicroarch_Intel_Atom_Unknown;
284 case 15:
285 switch (bModel)
286 {
287 case 0: return kCpumMicroarch_Intel_NB_Willamette;
288 case 1: return kCpumMicroarch_Intel_NB_Willamette;
289 case 2: return kCpumMicroarch_Intel_NB_Northwood;
290 case 3: return kCpumMicroarch_Intel_NB_Prescott;
291 case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
292 case 5: return kCpumMicroarch_Intel_NB_Unknown; /*??*/
293 case 6: return kCpumMicroarch_Intel_NB_CedarMill;
294 case 7: return kCpumMicroarch_Intel_NB_Gallatin;
295 default: return kCpumMicroarch_Intel_NB_Unknown;
296 }
297 break;
298 /* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
299 case 1:
300 return kCpumMicroarch_Intel_8086;
301 case 2:
302 return kCpumMicroarch_Intel_80286;
303 }
304 return kCpumMicroarch_Intel_Unknown;
305 }
306
307 if (enmVendor == CPUMCPUVENDOR_VIA)
308 {
309 switch (bFamily)
310 {
311 case 5:
312 switch (bModel)
313 {
314 case 1: return kCpumMicroarch_Centaur_C6;
315 case 4: return kCpumMicroarch_Centaur_C6;
316 case 8: return kCpumMicroarch_Centaur_C2;
317 case 9: return kCpumMicroarch_Centaur_C3;
318 }
319 break;
320
321 case 6:
322 switch (bModel)
323 {
324 case 5: return kCpumMicroarch_VIA_C3_M2;
325 case 6: return kCpumMicroarch_VIA_C3_C5A;
326 case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
327 case 8: return kCpumMicroarch_VIA_C3_C5N;
328 case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
329 case 10: return kCpumMicroarch_VIA_C7_C5J;
330 case 15: return kCpumMicroarch_VIA_Isaiah;
331 }
332 break;
333 }
334 return kCpumMicroarch_VIA_Unknown;
335 }
336
337 if (enmVendor == CPUMCPUVENDOR_CYRIX)
338 {
339 switch (bFamily)
340 {
341 case 4:
342 switch (bModel)
343 {
344 case 9: return kCpumMicroarch_Cyrix_5x86;
345 }
346 break;
347
348 case 5:
349 switch (bModel)
350 {
351 case 2: return kCpumMicroarch_Cyrix_M1;
352 case 4: return kCpumMicroarch_Cyrix_MediaGX;
353 case 5: return kCpumMicroarch_Cyrix_MediaGXm;
354 }
355 break;
356
357 case 6:
358 switch (bModel)
359 {
360 case 0: return kCpumMicroarch_Cyrix_M2;
361 }
362 break;
363
364 }
365 return kCpumMicroarch_Cyrix_Unknown;
366 }
367
368 return kCpumMicroarch_Unknown;
369}
370
371
372/**
373 * Translates a microarchitecture enum value to the corresponding string
374 * constant.
375 *
376 * @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
377 * NULL if the value is invalid.
378 *
379 * @param enmMicroarch The enum value to convert.
380 */
381VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
382{
383 switch (enmMicroarch)
384 {
385#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
386 CASE_RET_STR(kCpumMicroarch_Intel_8086);
387 CASE_RET_STR(kCpumMicroarch_Intel_80186);
388 CASE_RET_STR(kCpumMicroarch_Intel_80286);
389 CASE_RET_STR(kCpumMicroarch_Intel_80386);
390 CASE_RET_STR(kCpumMicroarch_Intel_80486);
391 CASE_RET_STR(kCpumMicroarch_Intel_P5);
392
393 CASE_RET_STR(kCpumMicroarch_Intel_P6);
394 CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
395 CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
396
397 CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
398 CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
399 CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
400
401 CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
402 CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
403
404 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
405 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
406 CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
407 CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
408 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
409 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
410 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
411 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Cannonlake);
412
413 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
414 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
415 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
416 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
417 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
418 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
419 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
420
421 CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
422 CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
423 CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
424 CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
425 CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
426 CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
427 CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
428
429 CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
430
431 CASE_RET_STR(kCpumMicroarch_AMD_Am286);
432 CASE_RET_STR(kCpumMicroarch_AMD_Am386);
433 CASE_RET_STR(kCpumMicroarch_AMD_Am486);
434 CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
435 CASE_RET_STR(kCpumMicroarch_AMD_K5);
436 CASE_RET_STR(kCpumMicroarch_AMD_K6);
437
438 CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
439 CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
440 CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
441 CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
442 CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
443 CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
444 CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
445
446 CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
447 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
448 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
449 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
450 CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
451
452 CASE_RET_STR(kCpumMicroarch_AMD_K10);
453 CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
454 CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
455 CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
456 CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
457
458 CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
459 CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
460 CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
461 CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
462 CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
463
464 CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
465
466 CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
467
468 CASE_RET_STR(kCpumMicroarch_Centaur_C6);
469 CASE_RET_STR(kCpumMicroarch_Centaur_C2);
470 CASE_RET_STR(kCpumMicroarch_Centaur_C3);
471 CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
472 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
473 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
474 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
475 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
476 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
477 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
478 CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
479 CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
480 CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
481
482 CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
483 CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
484 CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
485 CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
486 CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
487 CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
488
489 CASE_RET_STR(kCpumMicroarch_Unknown);
490
491#undef CASE_RET_STR
492 case kCpumMicroarch_Invalid:
493 case kCpumMicroarch_Intel_End:
494 case kCpumMicroarch_Intel_Core7_End:
495 case kCpumMicroarch_Intel_Atom_End:
496 case kCpumMicroarch_Intel_P6_Core_Atom_End:
497 case kCpumMicroarch_Intel_NB_End:
498 case kCpumMicroarch_AMD_K7_End:
499 case kCpumMicroarch_AMD_K8_End:
500 case kCpumMicroarch_AMD_15h_End:
501 case kCpumMicroarch_AMD_16h_End:
502 case kCpumMicroarch_AMD_End:
503 case kCpumMicroarch_VIA_End:
504 case kCpumMicroarch_Cyrix_End:
505 case kCpumMicroarch_32BitHack:
506 break;
507 /* no default! */
508 }
509
510 return NULL;
511}
512
513
514
515/**
516 * Gets a matching leaf in the CPUID leaf array.
517 *
518 * @returns Pointer to the matching leaf, or NULL if not found.
519 * @param paLeaves The CPUID leaves to search. This is sorted.
520 * @param cLeaves The number of leaves in the array.
521 * @param uLeaf The leaf to locate.
522 * @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
523 */
524static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
525{
526 /* Lazy bird does linear lookup here since this is only used for the
527 occational CPUID overrides. */
528 for (uint32_t i = 0; i < cLeaves; i++)
529 if ( paLeaves[i].uLeaf == uLeaf
530 && paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
531 return &paLeaves[i];
532 return NULL;
533}
534
535
536/**
537 * Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
538 *
539 * @returns true if found, false it not.
540 * @param paLeaves The CPUID leaves to search. This is sorted.
541 * @param cLeaves The number of leaves in the array.
542 * @param uLeaf The leaf to locate.
543 * @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
544 * @param pLegacy The legacy output leaf.
545 */
546static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
547 PCPUMCPUID pLegacy)
548{
549 PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
550 if (pLeaf)
551 {
552 pLegacy->uEax = pLeaf->uEax;
553 pLegacy->uEbx = pLeaf->uEbx;
554 pLegacy->uEcx = pLeaf->uEcx;
555 pLegacy->uEdx = pLeaf->uEdx;
556 return true;
557 }
558 return false;
559}
560
561
562/**
563 * Ensures that the CPUID leaf array can hold one more leaf.
564 *
565 * @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
566 * failure.
567 * @param pVM Pointer to the VM, used as the heap selector. Passing
568 * NULL uses the host-context heap, otherwise the VM's
569 * hyper heap is used.
570 * @param ppaLeaves Pointer to the variable holding the array pointer
571 * (input/output).
572 * @param cLeaves The current array size.
573 *
574 * @remarks This function will automatically update the R0 and RC pointers when
575 * using the hyper heap, which means @a ppaLeaves and @a cLeaves must
576 * be the corresponding VM's CPUID arrays (which is asserted).
577 */
578static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
579{
580 /*
581 * If pVM is not specified, we're on the regular heap and can waste a
582 * little space to speed things up.
583 */
584 uint32_t cAllocated;
585 if (!pVM)
586 {
587 cAllocated = RT_ALIGN(cLeaves, 16);
588 if (cLeaves + 1 > cAllocated)
589 {
590 void *pvNew = RTMemRealloc(*ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
591 if (pvNew)
592 *ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
593 else
594 {
595 RTMemFree(*ppaLeaves);
596 *ppaLeaves = NULL;
597 }
598 }
599 }
600 /*
601 * Otherwise, we're on the hyper heap and are probably just inserting
602 * one or two leaves and should conserve space.
603 */
604 else
605 {
606#ifdef IN_VBOX_CPU_REPORT
607 AssertReleaseFailed();
608#else
609 Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
610 Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
611
612 size_t cb = cLeaves * sizeof(**ppaLeaves);
613 size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
614 int rc = MMR3HyperRealloc(pVM, *ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void **)ppaLeaves);
615 if (RT_SUCCESS(rc))
616 {
617 /* Update the R0 and RC pointers. */
618 pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
619 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
620 }
621 else
622 {
623 *ppaLeaves = NULL;
624 pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
625 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
626 LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
627 }
628#endif
629 }
630 return *ppaLeaves;
631}
632
633
634/**
635 * Append a CPUID leaf or sub-leaf.
636 *
637 * ASSUMES linear insertion order, so we'll won't need to do any searching or
638 * replace anything. Use cpumR3CpuIdInsert() for those cases.
639 *
640 * @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
641 * the caller need do no more work.
642 * @param ppaLeaves Pointer to the the pointer to the array of sorted
643 * CPUID leaves and sub-leaves.
644 * @param pcLeaves Where we keep the leaf count for *ppaLeaves.
645 * @param uLeaf The leaf we're adding.
646 * @param uSubLeaf The sub-leaf number.
647 * @param fSubLeafMask The sub-leaf mask.
648 * @param uEax The EAX value.
649 * @param uEbx The EBX value.
650 * @param uEcx The ECX value.
651 * @param uEdx The EDX value.
652 * @param fFlags The flags.
653 */
654static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves,
655 uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
656 uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
657{
658 if (!cpumR3CpuIdEnsureSpace(NULL /* pVM */, ppaLeaves, *pcLeaves))
659 return VERR_NO_MEMORY;
660
661 PCPUMCPUIDLEAF pNew = &(*ppaLeaves)[*pcLeaves];
662 Assert( *pcLeaves == 0
663 || pNew[-1].uLeaf < uLeaf
664 || (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
665
666 pNew->uLeaf = uLeaf;
667 pNew->uSubLeaf = uSubLeaf;
668 pNew->fSubLeafMask = fSubLeafMask;
669 pNew->uEax = uEax;
670 pNew->uEbx = uEbx;
671 pNew->uEcx = uEcx;
672 pNew->uEdx = uEdx;
673 pNew->fFlags = fFlags;
674
675 *pcLeaves += 1;
676 return VINF_SUCCESS;
677}
678
679
680/**
681 * Checks that we've updated the CPUID leaves array correctly.
682 *
683 * This is a no-op in non-strict builds.
684 *
685 * @param paLeaves The leaves array.
686 * @param cLeaves The number of leaves.
687 */
688static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
689{
690#ifdef VBOX_STRICT
691 for (uint32_t i = 1; i < cLeaves; i++)
692 if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
693 AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
694 else
695 {
696 AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
697 ("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
698 AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
699 ("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
700 AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
701 ("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
702 }
703#else
704 NOREF(paLeaves);
705 NOREF(cLeaves);
706#endif
707}
708
709
710/**
711 * Inserts a CPU ID leaf, replacing any existing ones.
712 *
713 * When inserting a simple leaf where we already got a series of subleaves with
714 * the same leaf number (eax), the simple leaf will replace the whole series.
715 *
716 * When pVM is NULL, this ASSUMES that the leaves array is still on the normal
717 * host-context heap and has only been allocated/reallocated by the
718 * cpumR3CpuIdEnsureSpace function.
719 *
720 * @returns VBox status code.
721 * @param pVM Pointer to the VM, used as the heap selector.
722 * Passing NULL uses the host-context heap, otherwise
723 * the VM's hyper heap is used.
724 * @param ppaLeaves Pointer to the the pointer to the array of sorted
725 * CPUID leaves and sub-leaves. Must be NULL if using
726 * the hyper heap.
727 * @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must be
728 * NULL if using the hyper heap.
729 * @param pNewLeaf Pointer to the data of the new leaf we're about to
730 * insert.
731 */
732static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
733{
734 /*
735 * Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
736 */
737 if (pVM)
738 {
739 AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
740 AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
741
742 ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
743 pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
744 }
745
746 PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
747 uint32_t cLeaves = *pcLeaves;
748
749 /*
750 * Validate the new leaf a little.
751 */
752 AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
753 ("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
754 VERR_INVALID_FLAGS);
755 AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 || pNewLeaf->uSubLeaf == 0,
756 ("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
757 VERR_INVALID_PARAMETER);
758 AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
759 ("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
760 VERR_INVALID_PARAMETER);
761 AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
762 ("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
763 VERR_INVALID_PARAMETER);
764
765 /*
766 * Find insertion point. The lazy bird uses the same excuse as in
767 * cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
768 */
769 uint32_t i;
770 if ( cLeaves > 0
771 && paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
772 {
773 /* Add at end. */
774 i = cLeaves;
775 }
776 else if ( cLeaves > 0
777 && paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
778 {
779 /* Either replacing the last leaf or dealing with sub-leaves. Spool
780 back to the first sub-leaf to pretend we did the linear search. */
781 i = cLeaves - 1;
782 while ( i > 0
783 && paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
784 i--;
785 }
786 else
787 {
788 /* Linear search from the start. */
789 i = 0;
790 while ( i < cLeaves
791 && paLeaves[i].uLeaf < pNewLeaf->uLeaf)
792 i++;
793 }
794 if ( i < cLeaves
795 && paLeaves[i].uLeaf == pNewLeaf->uLeaf)
796 {
797 if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
798 {
799 /*
800 * The sub-leaf mask differs, replace all existing leaves with the
801 * same leaf number.
802 */
803 uint32_t c = 1;
804 while ( i + c < cLeaves
805 && paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
806 c++;
807 if (c > 1 && i + c < cLeaves)
808 {
809 memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
810 *pcLeaves = cLeaves -= c - 1;
811 }
812
813 paLeaves[i] = *pNewLeaf;
814 cpumR3CpuIdAssertOrder(*ppaLeaves, *pcLeaves);
815 return VINF_SUCCESS;
816 }
817
818 /* Find sub-leaf insertion point. */
819 while ( i < cLeaves
820 && paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
821 && paLeaves[i].uLeaf == pNewLeaf->uLeaf)
822 i++;
823
824 /*
825 * If we've got an exactly matching leaf, replace it.
826 */
827 if ( i < cLeaves
828 && paLeaves[i].uLeaf == pNewLeaf->uLeaf
829 && paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
830 {
831 paLeaves[i] = *pNewLeaf;
832 cpumR3CpuIdAssertOrder(*ppaLeaves, *pcLeaves);
833 return VINF_SUCCESS;
834 }
835 }
836
837 /*
838 * Adding a new leaf at 'i'.
839 */
840 AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
841 paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
842 if (!paLeaves)
843 return VERR_NO_MEMORY;
844
845 if (i < cLeaves)
846 memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
847 *pcLeaves += 1;
848 paLeaves[i] = *pNewLeaf;
849
850 cpumR3CpuIdAssertOrder(*ppaLeaves, *pcLeaves);
851 return VINF_SUCCESS;
852}
853
854
855/**
856 * Removes a range of CPUID leaves.
857 *
858 * This will not reallocate the array.
859 *
860 * @param paLeaves The array of sorted CPUID leaves and sub-leaves.
861 * @param pcLeaves Where we keep the leaf count for @a paLeaves.
862 * @param uFirst The first leaf.
863 * @param uLast The last leaf.
864 */
865static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
866{
867 uint32_t cLeaves = *pcLeaves;
868
869 Assert(uFirst <= uLast);
870
871 /*
872 * Find the first one.
873 */
874 uint32_t iFirst = 0;
875 while ( iFirst < cLeaves
876 && paLeaves[iFirst].uLeaf < uFirst)
877 iFirst++;
878
879 /*
880 * Find the end (last + 1).
881 */
882 uint32_t iEnd = iFirst;
883 while ( iEnd < cLeaves
884 && paLeaves[iEnd].uLeaf <= uLast)
885 iEnd++;
886
887 /*
888 * Adjust the array if anything needs removing.
889 */
890 if (iFirst < iEnd)
891 {
892 if (iEnd < cLeaves)
893 memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
894 *pcLeaves = cLeaves -= (iEnd - iFirst);
895 }
896
897 cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
898}
899
900
901
902/**
903 * Checks if ECX make a difference when reading a given CPUID leaf.
904 *
905 * @returns @c true if it does, @c false if it doesn't.
906 * @param uLeaf The leaf we're reading.
907 * @param pcSubLeaves Number of sub-leaves accessible via ECX.
908 * @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
909 * final sub-leaf (for leaf 0xb only).
910 */
911static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t *pcSubLeaves, bool *pfFinalEcxUnchanged)
912{
913 *pfFinalEcxUnchanged = false;
914
915 uint32_t auCur[4];
916 uint32_t auPrev[4];
917 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
918
919 /* Look for sub-leaves. */
920 uint32_t uSubLeaf = 1;
921 for (;;)
922 {
923 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
924 if (memcmp(auCur, auPrev, sizeof(auCur)))
925 break;
926
927 /* Advance / give up. */
928 uSubLeaf++;
929 if (uSubLeaf >= 64)
930 {
931 *pcSubLeaves = 1;
932 return false;
933 }
934 }
935
936 /* Count sub-leaves. */
937 uint32_t cRepeats = 0;
938 uSubLeaf = 0;
939 for (;;)
940 {
941 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
942
943 /* Figuring out when to stop isn't entirely straight forward as we need
944 to cover undocumented behavior up to a point and implementation shortcuts. */
945
946 /* 1. Look for zero values. */
947 if ( auCur[0] == 0
948 && auCur[1] == 0
949 && (auCur[2] == 0 || auCur[2] == uSubLeaf)
950 && (auCur[3] == 0 || uLeaf == 0xb /* edx is fixed */) )
951 {
952 cRepeats = 0;
953 break;
954 }
955
956 /* 2. Look for more than 4 repeating value sets. */
957 if ( auCur[0] == auPrev[0]
958 && auCur[1] == auPrev[1]
959 && ( auCur[2] == auPrev[2]
960 || ( auCur[2] == uSubLeaf
961 && auPrev[2] == uSubLeaf - 1) )
962 && auCur[3] == auPrev[3])
963 {
964 cRepeats++;
965 if (cRepeats > 4)
966 break;
967 }
968 else
969 cRepeats = 0;
970
971 /* 3. Leaf 0xb level type 0 check. */
972 if ( uLeaf == 0xb
973 && (auCur[2] & 0xff00) == 0
974 && (auPrev[2] & 0xff00) == 0)
975 {
976 cRepeats = 0;
977 break;
978 }
979
980 /* 99. Give up. */
981 if (uSubLeaf >= 128)
982 {
983#ifndef IN_VBOX_CPU_REPORT
984 /* Ok, limit it according to the documentation if possible just to
985 avoid annoying users with these detection issues. */
986 uint32_t cDocLimit = UINT32_MAX;
987 if (uLeaf == 0x4)
988 cDocLimit = 4;
989 else if (uLeaf == 0x7)
990 cDocLimit = 1;
991 else if (uLeaf == 0xf)
992 cDocLimit = 2;
993 if (cDocLimit != UINT32_MAX)
994 {
995 *pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
996 *pcSubLeaves = cDocLimit + 3;
997 return true;
998 }
999#endif
1000 *pcSubLeaves = UINT32_MAX;
1001 return true;
1002 }
1003
1004 /* Advance. */
1005 uSubLeaf++;
1006 memcpy(auPrev, auCur, sizeof(auCur));
1007 }
1008
1009 /* Standard exit. */
1010 *pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1011 *pcSubLeaves = uSubLeaf + 1 - cRepeats;
1012 if (*pcSubLeaves == 0)
1013 *pcSubLeaves = 1;
1014 return true;
1015}
1016
1017
1018/**
1019 * Gets a CPU ID leaf.
1020 *
1021 * @returns VBox status code.
1022 * @param pVM Pointer to the VM.
1023 * @param pLeaf Where to store the found leaf.
1024 * @param uLeaf The leaf to locate.
1025 * @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
1026 */
1027VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1028{
1029 PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1030 uLeaf, uSubLeaf);
1031 if (pcLeaf)
1032 {
1033 memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1034 return VINF_SUCCESS;
1035 }
1036
1037 return VERR_NOT_FOUND;
1038}
1039
1040
1041/**
1042 * Inserts a CPU ID leaf, replacing any existing ones.
1043 *
1044 * @returns VBox status code.
1045 * @param pVM Pointer to the VM.
1046 * @param pNewLeaf Pointer to the leaf being inserted.
1047 */
1048VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1049{
1050 /*
1051 * Validate parameters.
1052 */
1053 AssertReturn(pVM, VERR_INVALID_PARAMETER);
1054 AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1055
1056 /*
1057 * Disallow replacing CPU ID leaves that this API currently cannot manage.
1058 * These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1059 * If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1060 */
1061 if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1062 || pNewLeaf->uLeaf == UINT32_C(0x00000001)
1063 || pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1064 || pNewLeaf->uLeaf == UINT32_C(0x80000001)
1065 || pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1066 || pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1067 {
1068 return VERR_NOT_SUPPORTED;
1069 }
1070
1071 return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves */, NULL /* pcLeaves */, pNewLeaf);
1072}
1073
1074/**
1075 * Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1076 *
1077 * @returns VBox status code.
1078 * @param ppaLeaves Where to return the array pointer on success.
1079 * Use RTMemFree to release.
1080 * @param pcLeaves Where to return the size of the array on
1081 * success.
1082 */
1083VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
1084{
1085 *ppaLeaves = NULL;
1086 *pcLeaves = 0;
1087
1088 /*
1089 * Try out various candidates. This must be sorted!
1090 */
1091 static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1092 {
1093 { UINT32_C(0x00000000), false },
1094 { UINT32_C(0x10000000), false },
1095 { UINT32_C(0x20000000), false },
1096 { UINT32_C(0x30000000), false },
1097 { UINT32_C(0x40000000), false },
1098 { UINT32_C(0x50000000), false },
1099 { UINT32_C(0x60000000), false },
1100 { UINT32_C(0x70000000), false },
1101 { UINT32_C(0x80000000), false },
1102 { UINT32_C(0x80860000), false },
1103 { UINT32_C(0x8ffffffe), true },
1104 { UINT32_C(0x8fffffff), true },
1105 { UINT32_C(0x90000000), false },
1106 { UINT32_C(0xa0000000), false },
1107 { UINT32_C(0xb0000000), false },
1108 { UINT32_C(0xc0000000), false },
1109 { UINT32_C(0xd0000000), false },
1110 { UINT32_C(0xe0000000), false },
1111 { UINT32_C(0xf0000000), false },
1112 };
1113
1114 for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1115 {
1116 uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1117 uint32_t uEax, uEbx, uEcx, uEdx;
1118 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1119
1120 /*
1121 * Does EAX look like a typical leaf count value?
1122 */
1123 if ( uEax > uLeaf
1124 && uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1125 {
1126 /* Yes, dump them. */
1127 uint32_t cLeaves = uEax - uLeaf + 1;
1128 while (cLeaves-- > 0)
1129 {
1130 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1131
1132 uint32_t fFlags = 0;
1133
1134 /* There are currently three known leaves containing an APIC ID
1135 that needs EMT specific attention */
1136 if (uLeaf == 1)
1137 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1138 else if (uLeaf == 0xb && uEcx != 0)
1139 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1140 else if ( uLeaf == UINT32_C(0x8000001e)
1141 && ( uEax
1142 || uEbx
1143 || uEdx
1144 || ASMIsAmdCpuEx((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1145 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1146
1147
1148 /* Check three times here to reduce the chance of CPU migration
1149 resulting in false positives with things like the APIC ID. */
1150 uint32_t cSubLeaves;
1151 bool fFinalEcxUnchanged;
1152 if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1153 && cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1154 && cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1155 {
1156 if (cSubLeaves > 16)
1157 {
1158 /* This shouldn't happen. But in case it does, file all
1159 relevant details in the release log. */
1160 LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1161 LogRel(("------------------ dump of problematic subleaves ------------------\n"));
1162 for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1163 {
1164 uint32_t auTmp[4];
1165 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1166 LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1167 uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1168 }
1169 LogRel(("----------------- dump of what we've found so far -----------------\n"));
1170 for (uint32_t i = 0 ; i < *pcLeaves; i++)
1171 LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1172 (*ppaLeaves)[i].uLeaf, (*ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1173 (*ppaLeaves)[i].uEax, (*ppaLeaves)[i].uEbx, (*ppaLeaves)[i].uEcx, (*ppaLeaves)[i].uEdx));
1174 LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1175 return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1176 }
1177
1178 if (fFinalEcxUnchanged)
1179 fFlags |= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1180
1181 for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1182 {
1183 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1184 int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1185 uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1186 if (RT_FAILURE(rc))
1187 return rc;
1188 }
1189 }
1190 else
1191 {
1192 int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1193 uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1194 if (RT_FAILURE(rc))
1195 return rc;
1196 }
1197
1198 /* next */
1199 uLeaf++;
1200 }
1201 }
1202 /*
1203 * Special CPUIDs needs special handling as they don't follow the
1204 * leaf count principle used above.
1205 */
1206 else if (s_aCandidates[iOuter].fSpecial)
1207 {
1208 bool fKeep = false;
1209 if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1210 fKeep = true;
1211 else if ( uLeaf == 0x8fffffff
1212 && RT_C_IS_PRINT(RT_BYTE1(uEax))
1213 && RT_C_IS_PRINT(RT_BYTE2(uEax))
1214 && RT_C_IS_PRINT(RT_BYTE3(uEax))
1215 && RT_C_IS_PRINT(RT_BYTE4(uEax))
1216 && RT_C_IS_PRINT(RT_BYTE1(uEbx))
1217 && RT_C_IS_PRINT(RT_BYTE2(uEbx))
1218 && RT_C_IS_PRINT(RT_BYTE3(uEbx))
1219 && RT_C_IS_PRINT(RT_BYTE4(uEbx))
1220 && RT_C_IS_PRINT(RT_BYTE1(uEcx))
1221 && RT_C_IS_PRINT(RT_BYTE2(uEcx))
1222 && RT_C_IS_PRINT(RT_BYTE3(uEcx))
1223 && RT_C_IS_PRINT(RT_BYTE4(uEcx))
1224 && RT_C_IS_PRINT(RT_BYTE1(uEdx))
1225 && RT_C_IS_PRINT(RT_BYTE2(uEdx))
1226 && RT_C_IS_PRINT(RT_BYTE3(uEdx))
1227 && RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1228 fKeep = true;
1229 if (fKeep)
1230 {
1231 int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1232 uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1233 if (RT_FAILURE(rc))
1234 return rc;
1235 }
1236 }
1237 }
1238
1239 cpumR3CpuIdAssertOrder(*ppaLeaves, *pcLeaves);
1240 return VINF_SUCCESS;
1241}
1242
1243
1244/**
1245 * Determines the method the CPU uses to handle unknown CPUID leaves.
1246 *
1247 * @returns VBox status code.
1248 * @param penmUnknownMethod Where to return the method.
1249 * @param pDefUnknown Where to return default unknown values. This
1250 * will be set, even if the resulting method
1251 * doesn't actually needs it.
1252 */
1253VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1254{
1255 uint32_t uLastStd = ASMCpuId_EAX(0);
1256 uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1257 if (!ASMIsValidExtRange(uLastExt))
1258 uLastExt = 0x80000000;
1259
1260 uint32_t auChecks[] =
1261 {
1262 uLastStd + 1,
1263 uLastStd + 5,
1264 uLastStd + 8,
1265 uLastStd + 32,
1266 uLastStd + 251,
1267 uLastExt + 1,
1268 uLastExt + 8,
1269 uLastExt + 15,
1270 uLastExt + 63,
1271 uLastExt + 255,
1272 0x7fbbffcc,
1273 0x833f7872,
1274 0xefff2353,
1275 0x35779456,
1276 0x1ef6d33e,
1277 };
1278
1279 static const uint32_t s_auValues[] =
1280 {
1281 0xa95d2156,
1282 0x00000001,
1283 0x00000002,
1284 0x00000008,
1285 0x00000000,
1286 0x55773399,
1287 0x93401769,
1288 0x12039587,
1289 };
1290
1291 /*
1292 * Simple method, all zeros.
1293 */
1294 *penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1295 pDefUnknown->uEax = 0;
1296 pDefUnknown->uEbx = 0;
1297 pDefUnknown->uEcx = 0;
1298 pDefUnknown->uEdx = 0;
1299
1300 /*
1301 * Intel has been observed returning the last standard leaf.
1302 */
1303 uint32_t auLast[4];
1304 ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1305
1306 uint32_t cChecks = RT_ELEMENTS(auChecks);
1307 while (cChecks > 0)
1308 {
1309 uint32_t auCur[4];
1310 ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1311 if (memcmp(auCur, auLast, sizeof(auCur)))
1312 break;
1313 cChecks--;
1314 }
1315 if (cChecks == 0)
1316 {
1317 /* Now, what happens when the input changes? Esp. ECX. */
1318 uint32_t cTotal = 0;
1319 uint32_t cSame = 0;
1320 uint32_t cLastWithEcx = 0;
1321 uint32_t cNeither = 0;
1322 uint32_t cValues = RT_ELEMENTS(s_auValues);
1323 while (cValues > 0)
1324 {
1325 uint32_t uValue = s_auValues[cValues - 1];
1326 uint32_t auLastWithEcx[4];
1327 ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1328 &auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1329
1330 cChecks = RT_ELEMENTS(auChecks);
1331 while (cChecks > 0)
1332 {
1333 uint32_t auCur[4];
1334 ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1335 if (!memcmp(auCur, auLast, sizeof(auCur)))
1336 {
1337 cSame++;
1338 if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1339 cLastWithEcx++;
1340 }
1341 else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1342 cLastWithEcx++;
1343 else
1344 cNeither++;
1345 cTotal++;
1346 cChecks--;
1347 }
1348 cValues--;
1349 }
1350
1351 Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1352 if (cSame == cTotal)
1353 *penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1354 else if (cLastWithEcx == cTotal)
1355 *penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1356 else
1357 *penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1358 pDefUnknown->uEax = auLast[0];
1359 pDefUnknown->uEbx = auLast[1];
1360 pDefUnknown->uEcx = auLast[2];
1361 pDefUnknown->uEdx = auLast[3];
1362 return VINF_SUCCESS;
1363 }
1364
1365 /*
1366 * Unchanged register values?
1367 */
1368 cChecks = RT_ELEMENTS(auChecks);
1369 while (cChecks > 0)
1370 {
1371 uint32_t const uLeaf = auChecks[cChecks - 1];
1372 uint32_t cValues = RT_ELEMENTS(s_auValues);
1373 while (cValues > 0)
1374 {
1375 uint32_t uValue = s_auValues[cValues - 1];
1376 uint32_t auCur[4];
1377 ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1378 if ( auCur[0] != uLeaf
1379 || auCur[1] != uValue
1380 || auCur[2] != uValue
1381 || auCur[3] != uValue)
1382 break;
1383 cValues--;
1384 }
1385 if (cValues != 0)
1386 break;
1387 cChecks--;
1388 }
1389 if (cChecks == 0)
1390 {
1391 *penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1392 return VINF_SUCCESS;
1393 }
1394
1395 /*
1396 * Just go with the simple method.
1397 */
1398 return VINF_SUCCESS;
1399}
1400
1401
1402/**
1403 * Translates a unknow CPUID leaf method into the constant name (sans prefix).
1404 *
1405 * @returns Read only name string.
1406 * @param enmUnknownMethod The method to translate.
1407 */
1408VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1409{
1410 switch (enmUnknownMethod)
1411 {
1412 case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1413 case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1414 case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1415 case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1416
1417 case CPUMUNKNOWNCPUID_INVALID:
1418 case CPUMUNKNOWNCPUID_END:
1419 case CPUMUNKNOWNCPUID_32BIT_HACK:
1420 break;
1421 }
1422 return "Invalid-unknown-CPUID-method";
1423}
1424
1425
1426/**
1427 * Detect the CPU vendor give n the
1428 *
1429 * @returns The vendor.
1430 * @param uEAX EAX from CPUID(0).
1431 * @param uEBX EBX from CPUID(0).
1432 * @param uECX ECX from CPUID(0).
1433 * @param uEDX EDX from CPUID(0).
1434 */
1435VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1436{
1437 if (ASMIsValidStdRange(uEAX))
1438 {
1439 if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1440 return CPUMCPUVENDOR_AMD;
1441
1442 if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1443 return CPUMCPUVENDOR_INTEL;
1444
1445 if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1446 return CPUMCPUVENDOR_VIA;
1447
1448 if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1449 && uECX == UINT32_C(0x64616574)
1450 && uEDX == UINT32_C(0x736E4978))
1451 return CPUMCPUVENDOR_CYRIX;
1452
1453 /* "Geode by NSC", example: family 5, model 9. */
1454
1455 /** @todo detect the other buggers... */
1456 }
1457
1458 return CPUMCPUVENDOR_UNKNOWN;
1459}
1460
1461
1462/**
1463 * Translates a CPU vendor enum value into the corresponding string constant.
1464 *
1465 * The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1466 * value name. This can be useful when generating code.
1467 *
1468 * @returns Read only name string.
1469 * @param enmVendor The CPU vendor value.
1470 */
1471VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1472{
1473 switch (enmVendor)
1474 {
1475 case CPUMCPUVENDOR_INTEL: return "INTEL";
1476 case CPUMCPUVENDOR_AMD: return "AMD";
1477 case CPUMCPUVENDOR_VIA: return "VIA";
1478 case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1479 case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1480
1481 case CPUMCPUVENDOR_INVALID:
1482 case CPUMCPUVENDOR_32BIT_HACK:
1483 break;
1484 }
1485 return "Invalid-cpu-vendor";
1486}
1487
1488
1489static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1490{
1491 /* Could do binary search, doing linear now because I'm lazy. */
1492 PCCPUMCPUIDLEAF pLeaf = paLeaves;
1493 while (cLeaves-- > 0)
1494 {
1495 if (pLeaf->uLeaf == uLeaf)
1496 return pLeaf;
1497 pLeaf++;
1498 }
1499 return NULL;
1500}
1501
1502
1503int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1504{
1505 RT_ZERO(*pFeatures);
1506 if (cLeaves >= 2)
1507 {
1508 AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1509 AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1510
1511 pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(paLeaves[0].uEax,
1512 paLeaves[0].uEbx,
1513 paLeaves[0].uEcx,
1514 paLeaves[0].uEdx);
1515 pFeatures->uFamily = ASMGetCpuFamily(paLeaves[1].uEax);
1516 pFeatures->uModel = ASMGetCpuModel(paLeaves[1].uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1517 pFeatures->uStepping = ASMGetCpuStepping(paLeaves[1].uEax);
1518 pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1519 pFeatures->uFamily,
1520 pFeatures->uModel,
1521 pFeatures->uStepping);
1522
1523 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1524 if (pLeaf)
1525 pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff;
1526 else if (paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1527 pFeatures->cMaxPhysAddrWidth = 36;
1528 else
1529 pFeatures->cMaxPhysAddrWidth = 32;
1530
1531 /* Standard features. */
1532 pFeatures->fMsr = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_MSR);
1533 pFeatures->fApic = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_APIC);
1534 pFeatures->fX2Apic = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1535 pFeatures->fPse = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE);
1536 pFeatures->fPse36 = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1537 pFeatures->fPae = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PAE);
1538 pFeatures->fPat = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PAT);
1539 pFeatures->fFxSaveRstor = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1540 pFeatures->fSysEnter = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_SEP);
1541 pFeatures->fHypervisorPresent = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_HVP);
1542 pFeatures->fMonitorMWait = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1543
1544 /* MWAIT/MONITOR leaf. */
1545 PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1546 if (pMWaitLeaf)
1547 {
1548 pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1549 == (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1550 }
1551
1552 /* Extended features. */
1553 PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1554 if (pExtLeaf)
1555 {
1556 pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1557 pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1558 pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1559 pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1560 pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1561 }
1562
1563 if ( pExtLeaf
1564 && pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1565 {
1566 /* AMD features. */
1567 pFeatures->fMsr |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1568 pFeatures->fApic |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1569 pFeatures->fPse |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1570 pFeatures->fPse36 |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1571 pFeatures->fPae |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1572 pFeatures->fPat |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1573 pFeatures->fFxSaveRstor |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1574 }
1575
1576 /*
1577 * Quirks.
1578 */
1579 pFeatures->fLeakyFxSR = pExtLeaf
1580 && (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1581 && pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1582 && pFeatures->uFamily >= 6 /* K7 and up */;
1583 }
1584 else
1585 AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1586 return VINF_SUCCESS;
1587}
1588
1589
1590/*
1591 *
1592 * Init related code.
1593 * Init related code.
1594 * Init related code.
1595 *
1596 *
1597 */
1598#ifdef VBOX_IN_VMM
1599
1600
1601/**
1602 * Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1603 *
1604 * This ignores the fSubLeafMask.
1605 *
1606 * @returns Pointer to the matching leaf, or NULL if not found.
1607 * @param paLeaves The CPUID leaves to search. This is sorted.
1608 * @param cLeaves The number of leaves in the array.
1609 * @param uLeaf The leaf to locate.
1610 * @param uSubLeaf The subleaf to locate.
1611 */
1612static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1613{
1614 uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1615 PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1616 uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1617 if (iEnd)
1618 {
1619 uint32_t iBegin = 0;
1620 for (;;)
1621 {
1622 uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1623 uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1624 if (uNeedle < uCur)
1625 {
1626 if (i > iBegin)
1627 iEnd = i;
1628 else
1629 break;
1630 }
1631 else if (uNeedle > uCur)
1632 {
1633 if (i + 1 < iEnd)
1634 iBegin = i + 1;
1635 else
1636 break;
1637 }
1638 else
1639 return &paLeaves[i];
1640 }
1641 }
1642 return NULL;
1643}
1644
1645
1646/**
1647 * Loads MSR range overrides.
1648 *
1649 * This must be called before the MSR ranges are moved from the normal heap to
1650 * the hyper heap!
1651 *
1652 * @returns VBox status code (VMSetError called).
1653 * @param pVM Pointer to the cross context VM structure
1654 * @param pMsrNode The CFGM node with the MSR overrides.
1655 */
1656static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1657{
1658 for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1659 {
1660 /*
1661 * Assemble a valid MSR range.
1662 */
1663 CPUMMSRRANGE MsrRange;
1664 MsrRange.offCpumCpu = 0;
1665 MsrRange.fReserved = 0;
1666
1667 int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1668 if (RT_FAILURE(rc))
1669 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1670
1671 rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1672 if (RT_FAILURE(rc))
1673 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1674 MsrRange.szName, rc);
1675
1676 rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1677 if (RT_FAILURE(rc))
1678 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1679 MsrRange.szName, rc);
1680
1681 char szType[32];
1682 rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1683 if (RT_FAILURE(rc))
1684 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1685 MsrRange.szName, rc);
1686 if (!RTStrICmp(szType, "FixedValue"))
1687 {
1688 MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1689 MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1690
1691 rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1692 if (RT_FAILURE(rc))
1693 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1694 MsrRange.szName, rc);
1695
1696 rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1697 if (RT_FAILURE(rc))
1698 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1699 MsrRange.szName, rc);
1700
1701 rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1702 if (RT_FAILURE(rc))
1703 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1704 MsrRange.szName, rc);
1705 }
1706 else
1707 return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1708 "Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1709
1710 /*
1711 * Insert the range into the table (replaces/splits/shrinks existing
1712 * MSR ranges).
1713 */
1714 rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1715 &MsrRange);
1716 if (RT_FAILURE(rc))
1717 return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
1718 }
1719
1720 return VINF_SUCCESS;
1721}
1722
1723
1724/**
1725 * Loads CPUID leaf overrides.
1726 *
1727 * This must be called before the CPUID leaves are moved from the normal
1728 * heap to the hyper heap!
1729 *
1730 * @returns VBox status code (VMSetError called).
1731 * @param pVM Pointer to the cross context VM structure
1732 * @param pParentNode The CFGM node with the CPUID leaves.
1733 * @param pszLabel How to label the overrides we're loading.
1734 */
1735static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
1736{
1737 for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1738 {
1739 /*
1740 * Get the leaf and subleaf numbers.
1741 */
1742 char szName[128];
1743 int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
1744 if (RT_FAILURE(rc))
1745 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
1746
1747 /* The leaf number is either specified directly or thru the node name. */
1748 uint32_t uLeaf;
1749 rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
1750 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1751 {
1752 rc = RTStrToUInt32Full(szName, 16, &uLeaf);
1753 if (rc != VINF_SUCCESS)
1754 return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
1755 "Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
1756 }
1757 else if (RT_FAILURE(rc))
1758 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
1759 pszLabel, szName, rc);
1760
1761 uint32_t uSubLeaf;
1762 rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
1763 if (RT_FAILURE(rc))
1764 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
1765 pszLabel, szName, rc);
1766
1767 uint32_t fSubLeafMask;
1768 rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
1769 if (RT_FAILURE(rc))
1770 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
1771 pszLabel, szName, rc);
1772
1773 /*
1774 * Look up the specified leaf, since the output register values
1775 * defaults to any existing values. This allows overriding a single
1776 * register, without needing to know the other values.
1777 */
1778 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
1779 CPUMCPUIDLEAF Leaf;
1780 if (pLeaf)
1781 Leaf = *pLeaf;
1782 else
1783 RT_ZERO(Leaf);
1784 Leaf.uLeaf = uLeaf;
1785 Leaf.uSubLeaf = uSubLeaf;
1786 Leaf.fSubLeafMask = fSubLeafMask;
1787
1788 rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
1789 if (RT_FAILURE(rc))
1790 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
1791 pszLabel, szName, rc);
1792 rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
1793 if (RT_FAILURE(rc))
1794 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
1795 pszLabel, szName, rc);
1796 rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
1797 if (RT_FAILURE(rc))
1798 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
1799 pszLabel, szName, rc);
1800 rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
1801 if (RT_FAILURE(rc))
1802 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
1803 pszLabel, szName, rc);
1804
1805 /*
1806 * Insert the leaf into the table (replaces existing ones).
1807 */
1808 rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1809 &Leaf);
1810 if (RT_FAILURE(rc))
1811 return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
1812 }
1813
1814 return VINF_SUCCESS;
1815}
1816
1817
1818
1819/**
1820 * Fetches overrides for a CPUID leaf.
1821 *
1822 * @returns VBox status code.
1823 * @param pLeaf The leaf to load the overrides into.
1824 * @param pCfgNode The CFGM node containing the overrides
1825 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
1826 * @param iLeaf The CPUID leaf number.
1827 */
1828static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
1829{
1830 PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
1831 if (pLeafNode)
1832 {
1833 uint32_t u32;
1834 int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
1835 if (RT_SUCCESS(rc))
1836 pLeaf->uEax = u32;
1837 else
1838 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1839
1840 rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
1841 if (RT_SUCCESS(rc))
1842 pLeaf->uEbx = u32;
1843 else
1844 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1845
1846 rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
1847 if (RT_SUCCESS(rc))
1848 pLeaf->uEcx = u32;
1849 else
1850 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1851
1852 rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
1853 if (RT_SUCCESS(rc))
1854 pLeaf->uEdx = u32;
1855 else
1856 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1857
1858 }
1859 return VINF_SUCCESS;
1860}
1861
1862
1863/**
1864 * Load the overrides for a set of CPUID leaves.
1865 *
1866 * @returns VBox status code.
1867 * @param paLeaves The leaf array.
1868 * @param cLeaves The number of leaves.
1869 * @param uStart The start leaf number.
1870 * @param pCfgNode The CFGM node containing the overrides
1871 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
1872 */
1873static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
1874{
1875 for (uint32_t i = 0; i < cLeaves; i++)
1876 {
1877 int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
1878 if (RT_FAILURE(rc))
1879 return rc;
1880 }
1881
1882 return VINF_SUCCESS;
1883}
1884
1885/**
1886 * Init a set of host CPUID leaves.
1887 *
1888 * @returns VBox status code.
1889 * @param paLeaves The leaf array.
1890 * @param cLeaves The number of leaves.
1891 * @param uStart The start leaf number.
1892 * @param pCfgNode The /CPUM/HostCPUID/ node.
1893 */
1894static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
1895{
1896 /* Using the ECX variant for all of them can't hurt... */
1897 for (uint32_t i = 0; i < cLeaves; i++)
1898 ASMCpuIdExSlow(uStart + i, 0, 0, 0, &paLeaves[i].uEax, &paLeaves[i].uEbx, &paLeaves[i].uEcx, &paLeaves[i].uEdx);
1899
1900 /* Load CPUID leaf override; we currently don't care if the user
1901 specifies features the host CPU doesn't support. */
1902 return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
1903}
1904
1905
1906static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
1907{
1908 cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
1909
1910 /*
1911 * Install the CPUID information.
1912 */
1913 int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
1914 MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
1915
1916 AssertLogRelRCReturn(rc, rc);
1917 pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
1918 pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
1919 pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
1920 Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
1921 Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
1922
1923 /*
1924 * Update the default CPUID leaf if necessary.
1925 */
1926 switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
1927 {
1928 case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
1929 case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
1930 {
1931 /* We don't use CPUID(0).eax here because of the NT hack that only
1932 changes that value without actually removing any leaves. */
1933 uint32_t i = 0;
1934 if ( pCpum->GuestInfo.cCpuIdLeaves > 0
1935 && pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
1936 {
1937 while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
1938 && pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
1939 i++;
1940 pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
1941 pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
1942 pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
1943 pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
1944 }
1945 break;
1946 }
1947 default:
1948 break;
1949 }
1950
1951 /*
1952 * Explode the guest CPU features.
1953 */
1954 rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
1955 AssertLogRelRCReturn(rc, rc);
1956
1957 /*
1958 * Adjust the scalable bus frequency according to the CPUID information
1959 * we're now using.
1960 */
1961 if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
1962 pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
1963 ? UINT64_C(100000000) /* 100MHz */
1964 : UINT64_C(133333333); /* 133MHz */
1965
1966 /*
1967 * Populate the legacy arrays. Currently used for everything, later only
1968 * for patch manager.
1969 */
1970 struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
1971 {
1972 { pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
1973 { pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
1974 { pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
1975 };
1976 for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
1977 {
1978 uint32_t cLeft = aOldRanges[i].cCpuIds;
1979 uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
1980 PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
1981 while (cLeft-- > 0)
1982 {
1983 uLeaf--;
1984 pLegacyLeaf--;
1985
1986 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
1987 if (pLeaf)
1988 {
1989 pLegacyLeaf->uEax = pLeaf->uEax;
1990 pLegacyLeaf->uEbx = pLeaf->uEbx;
1991 pLegacyLeaf->uEcx = pLeaf->uEcx;
1992 pLegacyLeaf->uEdx = pLeaf->uEdx;
1993 }
1994 else
1995 *pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
1996 }
1997 }
1998
1999 return VINF_SUCCESS;
2000}
2001
2002
2003/** @name Instruction Set Extension Options
2004 * @{ */
2005/** Configuration option type (extended boolean, really). */
2006typedef uint8_t CPUMISAEXTCFG;
2007/** Always disable the extension. */
2008#define CPUMISAEXTCFG_DISABLED false
2009/** Enable the extension if it's supported by the host CPU. */
2010#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2011/** Enable the extension if it's supported by the host CPU, but don't let
2012 * the portable CPUID feature disable it. */
2013#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2014/** Always enable the extension. */
2015#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2016/** @} */
2017
2018/**
2019 * CPUID Configuration (from CFGM).
2020 *
2021 * @remarks The members aren't document since we would only be duplicating the
2022 * \@cfgm entries in cpumR3CpuIdReadConfig.
2023 */
2024typedef struct CPUMCPUIDCONFIG
2025{
2026 bool fSyntheticCpu;
2027 bool fNt4LeafLimit;
2028 bool fInvariantTsc;
2029
2030 CPUMISAEXTCFG enmCmpXchg16b;
2031 CPUMISAEXTCFG enmMonitor;
2032 CPUMISAEXTCFG enmMWaitExtensions;
2033 CPUMISAEXTCFG enmSse41;
2034 CPUMISAEXTCFG enmSse42;
2035 CPUMISAEXTCFG enmAesNi;
2036 CPUMISAEXTCFG enmPClMul;
2037 CPUMISAEXTCFG enmPopCnt;
2038 CPUMISAEXTCFG enmMovBe;
2039 CPUMISAEXTCFG enmRdRand;
2040 CPUMISAEXTCFG enmRdSeed;
2041 CPUMISAEXTCFG enmCLFlushOpt;
2042
2043 CPUMISAEXTCFG enmAbm;
2044 CPUMISAEXTCFG enmSse4A;
2045 CPUMISAEXTCFG enmMisAlnSse;
2046 CPUMISAEXTCFG enm3dNowPrf;
2047 CPUMISAEXTCFG enmAmdExtMmx;
2048
2049 uint32_t uMaxStdLeaf;
2050 uint32_t uMaxExtLeaf;
2051 uint32_t uMaxCentaurLeaf;
2052 uint32_t uMaxIntelFamilyModelStep;
2053 char szCpuName[128];
2054} CPUMCPUIDCONFIG;
2055/** Pointer to CPUID config (from CFGM). */
2056typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2057
2058
2059/**
2060 * Insert hypervisor identification leaves.
2061 *
2062 * We only return minimal information, primarily ensuring that the
2063 * 0x40000000 function returns 0x40000001 and identifying ourselves.
2064 * Hypervisor-specific interface is supported through GIM which will
2065 * modify these leaves if required depending on the GIM provider.
2066 *
2067 * @returns VBox status code.
2068 * @param pCpum The CPUM instance data.
2069 * @param pConfig The CPUID configuration we've read from CFGM.
2070 */
2071static int cpumR3CpuIdPlantHypervisorLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2072{
2073 CPUMCPUIDLEAF NewLeaf;
2074 NewLeaf.uLeaf = UINT32_C(0x40000000);
2075 NewLeaf.uSubLeaf = 0;
2076 NewLeaf.fSubLeafMask = 0;
2077 NewLeaf.uEax = UINT32_C(0x40000001);
2078 NewLeaf.uEbx = 0x786f4256 /* 'VBox' */;
2079 NewLeaf.uEcx = 0x786f4256 /* 'VBox' */;
2080 NewLeaf.uEdx = 0x786f4256 /* 'VBox' */;
2081 NewLeaf.fFlags = 0;
2082 int rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
2083 AssertLogRelRCReturn(rc, rc);
2084
2085 NewLeaf.uLeaf = UINT32_C(0x40000001);
2086 NewLeaf.uEax = 0x656e6f6e; /* 'none' */
2087 NewLeaf.uEbx = 0;
2088 NewLeaf.uEcx = 0;
2089 NewLeaf.uEdx = 0;
2090 NewLeaf.fFlags = 0;
2091 rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
2092 AssertLogRelRCReturn(rc, rc);
2093
2094 return VINF_SUCCESS;
2095}
2096
2097
2098/**
2099 * Mini CPU selection support for making Mac OS X happy.
2100 *
2101 * Executes the /CPUM/MaxIntelFamilyModelStep config.
2102 *
2103 * @param pCpum The CPUM instance data.
2104 * @param pConfig The CPUID configuration we've read from CFGM.
2105 */
2106static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2107{
2108 if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2109 {
2110 PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2111 uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2112 ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2113 ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2114 0);
2115 uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2116 if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2117 {
2118 uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2119 uNew |= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2120 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2121 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2122 uNew |= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2123 if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2124 uNew |= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2125 LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2126 pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2127 pStdFeatureLeaf->uEax = uNew;
2128 }
2129 }
2130}
2131
2132
2133
2134/**
2135 * Limit it the number of entries, zapping the remainder.
2136 *
2137 * The limits are masking off stuff about power saving and similar, this
2138 * is perhaps a bit crudely done as there is probably some relatively harmless
2139 * info too in these leaves (like words about having a constant TSC).
2140 *
2141 * @param pCpum The CPUM instance data.
2142 * @param pConfig The CPUID configuration we've read from CFGM.
2143 */
2144static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2145{
2146 /*
2147 * Standard leaves.
2148 */
2149 uint32_t uSubLeaf = 0;
2150 PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2151 if (pCurLeaf)
2152 {
2153 uint32_t uLimit = pCurLeaf->uEax;
2154 if (uLimit <= UINT32_C(0x000fffff))
2155 {
2156 if (uLimit > pConfig->uMaxStdLeaf)
2157 {
2158 pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2159 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2160 uLimit + 1, UINT32_C(0x000fffff));
2161 }
2162
2163 /* NT4 hack, no zapping of extra leaves here. */
2164 if (pConfig->fNt4LeafLimit && uLimit > 3)
2165 pCurLeaf->uEax = uLimit = 3;
2166
2167 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2168 pCurLeaf->uEax = uLimit;
2169 }
2170 else
2171 {
2172 LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2173 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2174 UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2175 }
2176 }
2177
2178 /*
2179 * Extended leaves.
2180 */
2181 uSubLeaf = 0;
2182 pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2183 if (pCurLeaf)
2184 {
2185 uint32_t uLimit = pCurLeaf->uEax;
2186 if ( uLimit >= UINT32_C(0x80000000)
2187 && uLimit <= UINT32_C(0x800fffff))
2188 {
2189 if (uLimit > pConfig->uMaxExtLeaf)
2190 {
2191 pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2192 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2193 uLimit + 1, UINT32_C(0x800fffff));
2194 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2195 pCurLeaf->uEax = uLimit;
2196 }
2197 }
2198 else
2199 {
2200 LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2201 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2202 UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2203 }
2204 }
2205
2206 /*
2207 * Centaur leaves (VIA).
2208 */
2209 uSubLeaf = 0;
2210 pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2211 if (pCurLeaf)
2212 {
2213 uint32_t uLimit = pCurLeaf->uEax;
2214 if ( uLimit >= UINT32_C(0xc0000000)
2215 && uLimit <= UINT32_C(0xc00fffff))
2216 {
2217 if (uLimit > pConfig->uMaxCentaurLeaf)
2218 {
2219 pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2220 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2221 uLimit + 1, UINT32_C(0xcfffffff));
2222 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2223 pCurLeaf->uEax = uLimit;
2224 }
2225 }
2226 else
2227 {
2228 LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2229 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2230 UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2231 }
2232 }
2233}
2234
2235
2236/**
2237 * Clears a CPUID leaf and all sub-leaves (to zero).
2238 *
2239 * @param pCpum The CPUM instance data.
2240 * @param uLeaf The leaf to clear.
2241 */
2242static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2243{
2244 uint32_t uSubLeaf = 0;
2245 PCPUMCPUIDLEAF pCurLeaf;
2246 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2247 {
2248 pCurLeaf->uEax = 0;
2249 pCurLeaf->uEbx = 0;
2250 pCurLeaf->uEcx = 0;
2251 pCurLeaf->uEdx = 0;
2252 uSubLeaf++;
2253 }
2254}
2255
2256
2257/**
2258 * Sanitizes and adjust the CPUID leaves.
2259 *
2260 * Drop features that aren't virtualized (or virtualizable). Adjust information
2261 * and capabilities to fit the virtualized hardware. Remove information the
2262 * guest shouldn't have (because it's wrong in the virtual world or because it
2263 * gives away host details) or that we don't have documentation for and no idea
2264 * what means.
2265 *
2266 * @returns VBox status code.
2267 * @param pVM Pointer to the cross context VM structure (for cCpus).
2268 * @param pCpum The CPUM instance data.
2269 * @param pConfig The CPUID configuration we've read from CFGM.
2270 */
2271static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2272{
2273#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2274 if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2275 { \
2276 LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2277 (a_pLeafReg) &= ~(uint32_t)(fMask); \
2278 }
2279#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2280 if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2281 { \
2282 LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2283 (a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2284 }
2285#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2286 if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2287 && ((a_pLeafReg) & (fBitMask)) \
2288 && (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2289 { \
2290 LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2291 (a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2292 }
2293 Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2294
2295 /* Cpuid 1:
2296 * EAX: CPU model, family and stepping.
2297 *
2298 * ECX + EDX: Supported features. Only report features we can support.
2299 * Note! When enabling new features the Synthetic CPU and Portable CPUID
2300 * options may require adjusting (i.e. stripping what was enabled).
2301 *
2302 * EBX: Branding, CLFLUSH line size, logical processors per package and
2303 * initial APIC ID.
2304 */
2305 PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2306 AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2307 AssertLogRelReturn(pStdFeatureLeaf->fSubLeafMask == 0, VERR_CPUM_IPE_2);
2308
2309 pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2310 | X86_CPUID_FEATURE_EDX_VME
2311 | X86_CPUID_FEATURE_EDX_DE
2312 | X86_CPUID_FEATURE_EDX_PSE
2313 | X86_CPUID_FEATURE_EDX_TSC
2314 | X86_CPUID_FEATURE_EDX_MSR
2315 //| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2316 | X86_CPUID_FEATURE_EDX_MCE
2317 | X86_CPUID_FEATURE_EDX_CX8
2318 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2319 //| RT_BIT_32(10) - not defined
2320 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2321 //| X86_CPUID_FEATURE_EDX_SEP
2322 | X86_CPUID_FEATURE_EDX_MTRR
2323 | X86_CPUID_FEATURE_EDX_PGE
2324 | X86_CPUID_FEATURE_EDX_MCA
2325 | X86_CPUID_FEATURE_EDX_CMOV
2326 | X86_CPUID_FEATURE_EDX_PAT /* 16 */
2327 | X86_CPUID_FEATURE_EDX_PSE36
2328 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2329 | X86_CPUID_FEATURE_EDX_CLFSH
2330 //| RT_BIT_32(20) - not defined
2331 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
2332 //| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2333 | X86_CPUID_FEATURE_EDX_MMX
2334 | X86_CPUID_FEATURE_EDX_FXSR
2335 | X86_CPUID_FEATURE_EDX_SSE
2336 | X86_CPUID_FEATURE_EDX_SSE2
2337 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2338 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading/cores - see below.
2339 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2340 //| RT_BIT_32(30) - not defined
2341 //| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2342 ;
2343 pStdFeatureLeaf->uEcx &= 0
2344 | X86_CPUID_FEATURE_ECX_SSE3
2345 | (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2346 //| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2347 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2348 | ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2349 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2350 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized yet.
2351 //| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2352 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2353 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2354 | X86_CPUID_FEATURE_ECX_SSSE3
2355 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2356 //| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2357 | (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2358 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2359 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
2360 //| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2361 //| X86_CPUID_FEATURE_ECX_PCID - not implemented yet.
2362 //| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2363 | (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2364 | (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2365 //| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2366 | (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2367 | (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2368 //| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2369 | (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2370 //| X86_CPUID_FEATURE_ECX_XSAVE - not implemented yet.
2371 //| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state
2372 //| X86_CPUID_FEATURE_ECX_AVX - not implemented yet.
2373 //| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2374 | (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2375 //| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2376 ;
2377
2378 if (pCpum->u8PortableCpuIdLevel > 0)
2379 {
2380 PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2381 PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2382 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2383 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2384 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2385 PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2386 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2387 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2388 PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2389 PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE);
2390 PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX);
2391 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2392 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2393 PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2394 PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2395 PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2396 PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2397 PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2398
2399 Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2400 | X86_CPUID_FEATURE_EDX_PSN
2401 | X86_CPUID_FEATURE_EDX_DS
2402 | X86_CPUID_FEATURE_EDX_ACPI
2403 | X86_CPUID_FEATURE_EDX_SS
2404 | X86_CPUID_FEATURE_EDX_TM
2405 | X86_CPUID_FEATURE_EDX_PBE
2406 )));
2407 Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2408 | X86_CPUID_FEATURE_ECX_CPLDS
2409 | X86_CPUID_FEATURE_ECX_VMX
2410 | X86_CPUID_FEATURE_ECX_SMX
2411 | X86_CPUID_FEATURE_ECX_EST
2412 | X86_CPUID_FEATURE_ECX_TM2
2413 | X86_CPUID_FEATURE_ECX_CNTXID
2414 | X86_CPUID_FEATURE_ECX_FMA
2415 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2416 | X86_CPUID_FEATURE_ECX_PDCM
2417 | X86_CPUID_FEATURE_ECX_DCA
2418 | X86_CPUID_FEATURE_ECX_XSAVE
2419 | X86_CPUID_FEATURE_ECX_OSXSAVE
2420 | X86_CPUID_FEATURE_ECX_AVX
2421 )));
2422 }
2423
2424 /* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2425 pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2426#ifdef VBOX_WITH_MULTI_CORE
2427 if (pVM->cCpus > 1)
2428 {
2429 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2430 core times the number of CPU cores per processor */
2431 pStdFeatureLeaf->uEbx |= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2432 pStdFeatureLeaf->uEdx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
2433 }
2434#endif
2435
2436 /* Force standard feature bits. */
2437 if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2438 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_PCLMUL;
2439 if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2440 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_MONITOR;
2441 if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2442 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_CX16;
2443 if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2444 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_SSE4_1;
2445 if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2446 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_SSE4_2;
2447 if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2448 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_MOVBE;
2449 if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2450 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_POPCNT;
2451 if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2452 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_AES;
2453 if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2454 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_RDRAND;
2455
2456 pStdFeatureLeaf = NULL; /* Must refetch! */
2457
2458 /* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2459 * AMD:
2460 * EAX: CPU model, family and stepping.
2461 *
2462 * ECX + EDX: Supported features. Only report features we can support.
2463 * Note! When enabling new features the Synthetic CPU and Portable CPUID
2464 * options may require adjusting (i.e. stripping what was enabled).
2465 * ASSUMES that this is ALWAYS the AMD defined feature set if present.
2466 *
2467 * EBX: Branding ID and package type (or reserved).
2468 *
2469 * Intel and probably most others:
2470 * EAX: 0
2471 * EBX: 0
2472 * ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2473 */
2474 PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2475 if (pExtFeatureLeaf)
2476 {
2477 AssertLogRelReturn(pExtFeatureLeaf->fSubLeafMask == 0, VERR_CPUM_IPE_2);
2478
2479 pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2480 | X86_CPUID_AMD_FEATURE_EDX_VME
2481 | X86_CPUID_AMD_FEATURE_EDX_DE
2482 | X86_CPUID_AMD_FEATURE_EDX_PSE
2483 | X86_CPUID_AMD_FEATURE_EDX_TSC
2484 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2485 //| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2486 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2487 | X86_CPUID_AMD_FEATURE_EDX_CX8
2488 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2489 //| RT_BIT_32(10) - reserved
2490 /* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2491 eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2492 //| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2493 | X86_CPUID_AMD_FEATURE_EDX_MTRR
2494 | X86_CPUID_AMD_FEATURE_EDX_PGE
2495 | X86_CPUID_AMD_FEATURE_EDX_MCA
2496 | X86_CPUID_AMD_FEATURE_EDX_CMOV
2497 | X86_CPUID_AMD_FEATURE_EDX_PAT
2498 | X86_CPUID_AMD_FEATURE_EDX_PSE36
2499 //| RT_BIT_32(18) - reserved
2500 //| RT_BIT_32(19) - reserved
2501 //| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2502 //| RT_BIT_32(21) - reserved
2503 | (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2504 | X86_CPUID_AMD_FEATURE_EDX_MMX
2505 | X86_CPUID_AMD_FEATURE_EDX_FXSR
2506 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
2507 //| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2508 | X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2509 //| RT_BIT_32(28) - reserved
2510 //| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2511 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2512 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
2513 ;
2514 pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2515 //| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2516 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
2517 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2518 /* Note: This could prevent teleporting from AMD to Intel CPUs! */
2519 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2520 | (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2521 | (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2522 | (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2523 | (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2524 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
2525 //| X86_CPUID_AMD_FEATURE_ECX_IBS
2526 //| X86_CPUID_AMD_FEATURE_ECX_XOP
2527 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2528 //| X86_CPUID_AMD_FEATURE_ECX_WDT
2529 //| RT_BIT_32(14) - reserved
2530 //| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2531 //| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2532 //| RT_BIT_32(17) - reserved
2533 //| RT_BIT_32(18) - reserved
2534 //| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2535 //| RT_BIT_32(20) - reserved
2536 //| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2537 //| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2538 //| RT_BIT_32(23) - reserved
2539 //| RT_BIT_32(24) - reserved
2540 //| RT_BIT_32(25) - reserved
2541 //| RT_BIT_32(26) - reserved
2542 //| RT_BIT_32(27) - reserved
2543 //| RT_BIT_32(28) - reserved
2544 //| RT_BIT_32(29) - reserved
2545 //| RT_BIT_32(30) - reserved
2546 //| RT_BIT_32(31) - reserved
2547 ;
2548#ifdef VBOX_WITH_MULTI_CORE
2549 if ( pVM->cCpus > 1
2550 && pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2551 pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2552#endif
2553
2554 if (pCpum->u8PortableCpuIdLevel > 0)
2555 {
2556 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2557 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2558 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2559 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2560 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2561 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2562 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2563 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2564 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2565 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2566 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2567 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2568 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2569 PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2570 PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2571
2572 Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2573 | X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2574 | X86_CPUID_AMD_FEATURE_ECX_OSVW
2575 | X86_CPUID_AMD_FEATURE_ECX_IBS
2576 | X86_CPUID_AMD_FEATURE_ECX_SKINIT
2577 | X86_CPUID_AMD_FEATURE_ECX_WDT
2578 | X86_CPUID_AMD_FEATURE_ECX_LWP
2579 | X86_CPUID_AMD_FEATURE_ECX_NODEID
2580 | X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2581 | UINT32_C(0xff964000)
2582 )));
2583 Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2584 | X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2585 | RT_BIT(18)
2586 | RT_BIT(19)
2587 | RT_BIT(21)
2588 | X86_CPUID_AMD_FEATURE_EDX_AXMMX
2589 | X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2590 | RT_BIT(28)
2591 )));
2592 }
2593
2594 /* Force extended feature bits. */
2595 if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2596 pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_ABM;
2597 if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2598 pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2599 if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2600 pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2601 if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2602 pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2603 if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2604 pExtFeatureLeaf->uEdx |= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2605 }
2606 pExtFeatureLeaf = NULL; /* Must refetch! */
2607
2608
2609 /* Cpuid 2:
2610 * Intel: (Nondeterministic) Cache and TLB information
2611 * AMD: Reserved
2612 * VIA: Reserved
2613 * Safe to expose. Restrict the number of calls to 1 since we don't
2614 * implement this kind of subleaves (is there hardware that does??).
2615 */
2616 uint32_t uSubLeaf = 0;
2617 PCPUMCPUIDLEAF pCurLeaf;
2618 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2619 {
2620 if ((pCurLeaf->uEax & 0xff) > 1)
2621 {
2622 LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2623 pCurLeaf->uEax &= UINT32_C(0xffffff01);
2624 }
2625 uSubLeaf++;
2626 }
2627
2628 /* Cpuid 3:
2629 * Intel: EAX, EBX - reserved (transmeta uses these)
2630 * ECX, EDX - Processor Serial Number if available, otherwise reserved
2631 * AMD: Reserved
2632 * VIA: Reserved
2633 * Safe to expose
2634 */
2635 pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2636 if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
2637 {
2638 uSubLeaf = 0;
2639 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
2640 {
2641 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2642 if (pCpum->u8PortableCpuIdLevel > 0)
2643 pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2644 uSubLeaf++;
2645 }
2646 }
2647
2648 /* Cpuid 4 + ECX:
2649 * Intel: Deterministic Cache Parameters Leaf.
2650 * AMD: Reserved
2651 * VIA: Reserved
2652 * Safe to expose, except for EAX:
2653 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
2654 * Bits 31-26: Maximum number of processor cores in this physical package**
2655 * Note: These SMP values are constant regardless of ECX
2656 */
2657 uSubLeaf = 0;
2658 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
2659 {
2660 pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
2661#ifdef VBOX_WITH_MULTI_CORE
2662 if ( pVM->cCpus > 1
2663 && pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2664 {
2665 AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
2666 /* One logical processor with possibly multiple cores. */
2667 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
2668 pCurLeaf->uEax |= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
2669 }
2670#endif
2671 uSubLeaf++;
2672 }
2673
2674 /* Cpuid 5: Monitor/mwait Leaf
2675 * Intel: ECX, EDX - reserved
2676 * EAX, EBX - Smallest and largest monitor line size
2677 * AMD: EDX - reserved
2678 * EAX, EBX - Smallest and largest monitor line size
2679 * ECX - extensions (ignored for now)
2680 * VIA: Reserved
2681 * Safe to expose
2682 */
2683 uSubLeaf = 0;
2684 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
2685 {
2686 pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2687 if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
2688 pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2689
2690 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2691 if (pConfig->enmMWaitExtensions)
2692 {
2693 pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
2694 /** @todo: for now we just expose host's MWAIT C-states, although conceptually
2695 it shall be part of our power management virtualization model */
2696#if 0
2697 /* MWAIT sub C-states */
2698 pCurLeaf->uEdx =
2699 (0 << 0) /* 0 in C0 */ |
2700 (2 << 4) /* 2 in C1 */ |
2701 (2 << 8) /* 2 in C2 */ |
2702 (2 << 12) /* 2 in C3 */ |
2703 (0 << 16) /* 0 in C4 */
2704 ;
2705#endif
2706 }
2707 else
2708 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2709 uSubLeaf++;
2710 }
2711
2712 /* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
2713 * Intel: Various stuff.
2714 * AMD: EAX, EBX, EDX - reserved.
2715 * ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
2716 * present. Same as intel.
2717 * VIA: ??
2718 *
2719 * We clear everything here for now.
2720 */
2721 cpumR3CpuIdZeroLeaf(pCpum, 6);
2722
2723 /* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
2724 * EAX: Number of sub leaves.
2725 * EBX+ECX+EDX: Feature flags
2726 *
2727 * We only have documentation for one sub-leaf, so clear all other (no need
2728 * to remove them as such, just set them to zero).
2729 *
2730 * Note! When enabling new features the Synthetic CPU and Portable CPUID
2731 * options may require adjusting (i.e. stripping what was enabled).
2732 */
2733 uSubLeaf = 0;
2734 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
2735 {
2736 switch (uSubLeaf)
2737 {
2738 case 0:
2739 {
2740 pCurLeaf->uEax = 0; /* Max ECX input is 0. */
2741 pCurLeaf->uEbx &= 0
2742 //| X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
2743 //| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
2744 //| RT_BIT(2) - reserved
2745 //| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
2746 //| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
2747 //| X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT(5)
2748 //| RT_BIT(6) - reserved
2749 //| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
2750 //| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
2751 //| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
2752 //| X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
2753 //| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
2754 //| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
2755 | X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
2756 //| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
2757 //| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
2758 //| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
2759 //| RT_BIT(17) - reserved
2760 | (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
2761 //| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
2762 //| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
2763 //| RT_BIT(21) - reserved
2764 //| RT_BIT(22) - reserved
2765 | (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
2766 //| RT_BIT(24) - reserved
2767 //| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
2768 //| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
2769 //| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
2770 //| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
2771 //| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
2772 //| RT_BIT(30) - reserved
2773 //| RT_BIT(31) - reserved
2774 ;
2775 pCurLeaf->uEcx &= 0
2776 //| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
2777 ;
2778 pCurLeaf->uEdx &= 0;
2779
2780 if (pCpum->u8PortableCpuIdLevel > 0)
2781 {
2782 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
2783 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2);
2784 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
2785 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
2786 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
2787 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
2788 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
2789 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
2790 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
2791 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
2792 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
2793 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
2794 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
2795 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
2796 }
2797
2798 /* Force standard feature bits. */
2799 if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
2800 pCurLeaf->uEbx |= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
2801 if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2802 pCurLeaf->uEbx |= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
2803 break;
2804 }
2805
2806 default:
2807 /* Invalid index, all values are zero. */
2808 pCurLeaf->uEax = 0;
2809 pCurLeaf->uEbx = 0;
2810 pCurLeaf->uEcx = 0;
2811 pCurLeaf->uEdx = 0;
2812 break;
2813 }
2814 uSubLeaf++;
2815 }
2816
2817 /* Cpuid 8: Marked as reserved by Intel and AMD.
2818 * We zero this since we don't know what it may have been used for.
2819 */
2820 cpumR3CpuIdZeroLeaf(pCpum, 8);
2821
2822 /* Cpuid 9: Direct Cache Access (DCA) Parameters
2823 * Intel: EAX - Value of PLATFORM_DCA_CAP bits.
2824 * EBX, ECX, EDX - reserved.
2825 * AMD: Reserved
2826 * VIA: ??
2827 *
2828 * We zero this.
2829 */
2830 cpumR3CpuIdZeroLeaf(pCpum, 9);
2831
2832 /* Cpuid 0xa: Architectural Performance Monitor Features
2833 * Intel: EAX - Value of PLATFORM_DCA_CAP bits.
2834 * EBX, ECX, EDX - reserved.
2835 * AMD: Reserved
2836 * VIA: ??
2837 *
2838 * We zero this, for now at least.
2839 */
2840 cpumR3CpuIdZeroLeaf(pCpum, 10);
2841
2842 /* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
2843 * Intel: EAX - APCI ID shift right for next level.
2844 * EBX - Factory configured cores/threads at this level.
2845 * ECX - Level number (same as input) and level type (1,2,0).
2846 * EDX - Extended initial APIC ID.
2847 * AMD: Reserved
2848 * VIA: ??
2849 */
2850 uSubLeaf = 0;
2851 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
2852 {
2853 if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
2854 {
2855 uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
2856 if (bLevelType == 1)
2857 {
2858 /* Thread level - we don't do threads at the moment. */
2859 pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
2860 pCurLeaf->uEbx = 1;
2861 }
2862 else if (bLevelType == 2)
2863 {
2864 /* Core level. */
2865 pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
2866#ifdef VBOX_WITH_MULTI_CORE
2867 while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
2868 pCurLeaf->uEax++;
2869#endif
2870 pCurLeaf->uEbx = pVM->cCpus;
2871 }
2872 else
2873 {
2874 AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
2875 pCurLeaf->uEax = 0;
2876 pCurLeaf->uEbx = 0;
2877 pCurLeaf->uEcx = 0;
2878 }
2879 pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) | (uSubLeaf & 0xff);
2880 pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
2881 }
2882 else
2883 {
2884 Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INTEL);
2885 pCurLeaf->uEax = 0;
2886 pCurLeaf->uEbx = 0;
2887 pCurLeaf->uEcx = 0;
2888 pCurLeaf->uEdx = 0;
2889 }
2890 uSubLeaf++;
2891 }
2892
2893 /* Cpuid 0xc: Marked as reserved by Intel and AMD.
2894 * We zero this since we don't know what it may have been used for.
2895 */
2896 cpumR3CpuIdZeroLeaf(pCpum, 12);
2897
2898 /* Cpuid 0xd + ECX: Processor Extended State Enumeration
2899 * ECX=0: EAX - Valid bits in XCR0[31:0].
2900 * EBX - Maximum state size as per current XCR0 value.
2901 * ECX - Maximum state size for all supported features.
2902 * EDX - Valid bits in XCR0[63:32].
2903 * ECX=1: EAX - Various X-features.
2904 * EBX - Maximum state size as per current XCR0|IA32_XSS value.
2905 * ECX - Valid bits in IA32_XSS[31:0].
2906 * EDX - Valid bits in IA32_XSS[63:32].
2907 * ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
2908 * if the bit invalid all four registers are set to zero.
2909 * EAX - The state size for this feature.
2910 * EBX - The state byte offset of this feature.
2911 * ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
2912 * EDX - Reserved, but is set to zero if invalid sub-leaf index.
2913 *
2914 * Clear them all as we don't currently implement extended CPU state.
2915 */
2916 uSubLeaf = 0;
2917 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf)) != NULL)
2918 {
2919 pCurLeaf->uEax = 0;
2920 pCurLeaf->uEbx = 0;
2921 pCurLeaf->uEcx = 0;
2922 pCurLeaf->uEdx = 0;
2923 uSubLeaf++;
2924 }
2925
2926 /* Cpuid 0xe: Marked as reserved by Intel and AMD.
2927 * We zero this since we don't know what it may have been used for.
2928 */
2929 cpumR3CpuIdZeroLeaf(pCpum, 14);
2930
2931 /* Cpuid 0xf + ECX: Platform qualifity of service monitoring (PQM).
2932 * We zero this as we don't currently virtualize PQM.
2933 */
2934 cpumR3CpuIdZeroLeaf(pCpum, 15);
2935
2936 /* Cpuid 0x10 + ECX: Platform qualifity of service enforcement (PQE).
2937 * We zero this as we don't currently virtualize PQE.
2938 */
2939 cpumR3CpuIdZeroLeaf(pCpum, 16);
2940
2941 /* Cpuid 0x11: Marked as reserved by Intel and AMD.
2942 * We zero this since we don't know what it may have been used for.
2943 */
2944 cpumR3CpuIdZeroLeaf(pCpum, 17);
2945
2946 /* Cpuid 0x12 + ECX: SGX resource enumeration.
2947 * We zero this as we don't currently virtualize this.
2948 */
2949 cpumR3CpuIdZeroLeaf(pCpum, 18);
2950
2951 /* Cpuid 0x13: Marked as reserved by Intel and AMD.
2952 * We zero this since we don't know what it may have been used for.
2953 */
2954 cpumR3CpuIdZeroLeaf(pCpum, 19);
2955
2956 /* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
2957 * We zero this as we don't currently virtualize this.
2958 */
2959 cpumR3CpuIdZeroLeaf(pCpum, 20);
2960
2961 /* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
2962 * Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
2963 * EAX - denominator (unsigned).
2964 * EBX - numerator (unsigned).
2965 * ECX, EDX - reserved.
2966 * AMD: Reserved / undefined / not implemented.
2967 * VIA: Reserved / undefined / not implemented.
2968 * We zero this as we don't currently virtualize this.
2969 */
2970 cpumR3CpuIdZeroLeaf(pCpum, 21);
2971
2972 /* Cpuid 0x16: Processor frequency info
2973 * Intel: EAX - Core base frequency in MHz.
2974 * EBX - Core maximum frequency in MHz.
2975 * ECX - Bus (reference) frequency in MHz.
2976 * EDX - Reserved.
2977 * AMD: Reserved / undefined / not implemented.
2978 * VIA: Reserved / undefined / not implemented.
2979 * We zero this as we don't currently virtualize this.
2980 */
2981 cpumR3CpuIdZeroLeaf(pCpum, 22);
2982
2983 /* Cpuid 0x17..0x10000000: Unknown.
2984 * We don't know these and what they mean, so remove them. */
2985 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2986 UINT32_C(0x00000017), UINT32_C(0x0fffffff));
2987
2988
2989 /* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
2990 * We remove all these as we're a hypervisor and must provide our own.
2991 */
2992 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2993 UINT32_C(0x40000000), UINT32_C(0x4fffffff));
2994
2995
2996 /* Cpuid 0x80000000 is harmless. */
2997
2998 /* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
2999
3000 /* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3001
3002 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3003 * Safe to pass on to the guest.
3004 *
3005 * AMD: 0x800000005 L1 cache information
3006 * 0x800000006 L2/L3 cache information
3007 * Intel: 0x800000005 reserved
3008 * 0x800000006 L2 cache information
3009 * VIA: 0x800000005 TLB and L1 cache information
3010 * 0x800000006 L2 cache information
3011 */
3012
3013 /* Cpuid 0x800000007: Advanced Power Management Information.
3014 * AMD: EAX: Processor feedback capabilities.
3015 * EBX: RAS capabilites.
3016 * ECX: Advanced power monitoring interface.
3017 * EDX: Enhanced power management capabilities.
3018 * Intel: EAX, EBX, ECX - reserved.
3019 * EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3020 * VIA: Reserved
3021 * We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3022 */
3023 uSubLeaf = 0;
3024 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3025 {
3026 pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3027 if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3028 {
3029 pCurLeaf->uEdx &= 0
3030 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
3031 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
3032 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
3033 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3034 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
3035 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
3036 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
3037 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3038#if 0 /*
3039 * We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
3040 * Linux kernels blindly assume that the AMD performance counters work
3041 * if this is set for 64 bits guests. (Can't really find a CPUID feature
3042 * bit for them though.)
3043 */
3044 /** @todo need to recheck this with new MSR emulation. */
3045 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3046#endif
3047 //| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3048 //| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3049 //| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3050 //| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3051 | 0;
3052 }
3053 else
3054 pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3055 if (pConfig->fInvariantTsc)
3056 pCurLeaf->uEdx |= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3057 uSubLeaf++;
3058 }
3059
3060 /* Cpuid 0x80000008:
3061 * AMD: EBX, EDX - reserved
3062 * EAX: Virtual/Physical/Guest address Size
3063 * ECX: Number of cores + APICIdCoreIdSize
3064 * Intel: EAX: Virtual/Physical address Size
3065 * EBX, ECX, EDX - reserved
3066 * VIA: EAX: Virtual/Physical address Size
3067 * EBX, ECX, EDX - reserved
3068 *
3069 * We only expose the virtual+pysical address size to the guest atm.
3070 * On AMD we set the core count, but not the apic id stuff as we're
3071 * currently not doing the apic id assignments in a complatible manner.
3072 */
3073 uSubLeaf = 0;
3074 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3075 {
3076 pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3077 pCurLeaf->uEbx = 0; /* reserved */
3078 pCurLeaf->uEdx = 0; /* reserved */
3079
3080 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3081 * Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3082 pCurLeaf->uEcx = 0;
3083#ifdef VBOX_WITH_MULTI_CORE
3084 if ( pVM->cCpus > 1
3085 && pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3086 pCurLeaf->uEcx |= (pVM->cCpus - 1) & UINT32_C(0xff);
3087#endif
3088 uSubLeaf++;
3089 }
3090
3091 /* Cpuid 0x80000009: Reserved
3092 * We zero this since we don't know what it may have been used for.
3093 */
3094 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3095
3096 /* Cpuid 0x8000000a: SVM Information
3097 * AMD: EAX - SVM revision.
3098 * EBX - Number of ASIDs.
3099 * ECX - Reserved.
3100 * EDX - SVM Feature identification.
3101 * We clear all as we currently does not virtualize SVM.
3102 */
3103 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3104
3105 /* Cpuid 0x8000000b thru 0x80000018: Reserved
3106 * We clear these as we don't know what purpose they might have. */
3107 for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3108 cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3109
3110 /* Cpuid 0x80000019: TLB configuration
3111 * Seems to be harmless, pass them thru as is. */
3112
3113 /* Cpuid 0x8000001a: Peformance optimization identifiers.
3114 * Strip anything we don't know what is or addresses feature we don't implement. */
3115 uSubLeaf = 0;
3116 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3117 {
3118 pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3119 | RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3120 //| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3121 ;
3122 pCurLeaf->uEbx = 0; /* reserved */
3123 pCurLeaf->uEcx = 0; /* reserved */
3124 pCurLeaf->uEdx = 0; /* reserved */
3125 uSubLeaf++;
3126 }
3127
3128 /* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3129 * Clear this as we don't currently virtualize this feature. */
3130 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3131
3132 /* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3133 * Clear this as we don't currently virtualize this feature. */
3134 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3135
3136 /* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3137 * We need to sanitize the cores per cache (EAX[25:14]).
3138 *
3139 * This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3140 * and EDX[2] are reserved here, and EAX[14:25] is documented having a
3141 * slightly different meaning.
3142 */
3143 uSubLeaf = 0;
3144 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3145 {
3146#ifdef VBOX_WITH_MULTI_CORE
3147 uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3148 if (cCores > pVM->cCpus)
3149 cCores = pVM->cCpus;
3150 pCurLeaf->uEax &= UINT32_C(0x00003fff);
3151 pCurLeaf->uEax |= ((cCores - 1) & 0xfff) << 14;
3152#else
3153 pCurLeaf->uEax &= UINT32_C(0x00003fff);
3154#endif
3155 uSubLeaf++;
3156 }
3157
3158 /* Cpuid 0x8000001e: Get APIC / unit / node information.
3159 * If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3160 * setup, we have one compute unit with all the cores in it. Single node.
3161 */
3162 uSubLeaf = 0;
3163 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3164 {
3165 pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3166 if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3167 {
3168#ifdef VBOX_WITH_MULTI_CORE
3169 pCurLeaf->uEbx = pVM->cCpus < 0x100
3170 ? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3171#else
3172 pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3173#endif
3174 pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3175 }
3176 else
3177 {
3178 Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3179 pCurLeaf->uEbx = 0; /* Reserved. */
3180 pCurLeaf->uEcx = 0; /* Reserved. */
3181 }
3182 pCurLeaf->uEdx = 0; /* Reserved. */
3183 uSubLeaf++;
3184 }
3185
3186 /* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3187 * We don't know these and what they mean, so remove them. */
3188 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3189 UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3190
3191 /* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3192 * Just pass it thru for now. */
3193
3194 /* Cpuid 0x8fffffff: Mystery hammer time leaf!
3195 * Just pass it thru for now. */
3196
3197 /* Cpuid 0xc0000000: Centaur stuff.
3198 * Harmless, pass it thru. */
3199
3200 /* Cpuid 0xc0000001: Centaur features.
3201 * VIA: EAX - Family, model, stepping.
3202 * EDX - Centaur extended feature flags. Nothing interesting, except may
3203 * FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3204 * EBX, ECX - reserved.
3205 * We keep EAX but strips the rest.
3206 */
3207 uSubLeaf = 0;
3208 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3209 {
3210 pCurLeaf->uEbx = 0;
3211 pCurLeaf->uEcx = 0;
3212 pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3213 uSubLeaf++;
3214 }
3215
3216 /* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3217 * We only have fixed stale values, but should be harmless. */
3218
3219 /* Cpuid 0xc0000003: Reserved.
3220 * We zero this since we don't know what it may have been used for.
3221 */
3222 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3223
3224 /* Cpuid 0xc0000004: Centaur Performance Info.
3225 * We only have fixed stale values, but should be harmless. */
3226
3227
3228 /* Cpuid 0xc0000005...0xcfffffff: Unknown.
3229 * We don't know these and what they mean, so remove them. */
3230 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3231 UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3232
3233 return VINF_SUCCESS;
3234#undef PORTABLE_DISABLE_FEATURE_BIT
3235#undef PORTABLE_CLEAR_BITS_WHEN
3236}
3237
3238
3239/**
3240 * Reads a value in /CPUM/IsaExts/ node.
3241 *
3242 * @returns VBox status code (error message raised).
3243 * @param pVM The VM handle (for errors).
3244 * @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3245 * @param pszValueName The value / extension name.
3246 * @param penmValue Where to return the choice.
3247 * @param enmDefault The default choice.
3248 */
3249static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3250 CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3251{
3252 /*
3253 * Try integer encoding first.
3254 */
3255 uint64_t uValue;
3256 int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3257 if (RT_SUCCESS(rc))
3258 switch (uValue)
3259 {
3260 case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3261 case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3262 case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3263 case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3264 default:
3265 return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3266 "Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3267 pszValueName, uValue);
3268 }
3269 /*
3270 * If missing, use default.
3271 */
3272 else if (rc == VERR_CFGM_VALUE_NOT_FOUND || rc == VERR_CFGM_NO_PARENT)
3273 *penmValue = enmDefault;
3274 else
3275 {
3276 if (rc == VERR_CFGM_NOT_INTEGER)
3277 {
3278 /*
3279 * Not an integer, try read it as a string.
3280 */
3281 char szValue[32];
3282 rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3283 if (RT_SUCCESS(rc))
3284 {
3285 RTStrToLower(szValue);
3286 size_t cchValue = strlen(szValue);
3287#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3288 if ( EQ("disabled") || EQ("disable") || EQ("off") || EQ("no"))
3289 *penmValue = CPUMISAEXTCFG_DISABLED;
3290 else if (EQ("enabled") || EQ("enable") || EQ("on") || EQ("yes"))
3291 *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3292 else if (EQ("forced") || EQ("force") || EQ("always"))
3293 *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3294 else if (EQ("portable"))
3295 *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3296 else if (EQ("default") || EQ("def"))
3297 *penmValue = enmDefault;
3298 else
3299 return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3300 "Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3301 pszValueName, uValue);
3302#undef EQ
3303 }
3304 }
3305 if (RT_FAILURE(rc))
3306 return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3307 }
3308 return VINF_SUCCESS;
3309}
3310
3311
3312/**
3313 * Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3314 *
3315 * @returns VBox status code (error message raised).
3316 * @param pVM The VM handle (for errors).
3317 * @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3318 * @param pCpumCfg The /CPUM node (can be NULL).
3319 * @param pszValueName The value / extension name.
3320 * @param penmValue Where to return the choice.
3321 * @param enmDefault The default choice.
3322 */
3323static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3324 CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3325{
3326 if (CFGMR3Exists(pCpumCfg, pszValueName))
3327 {
3328 if (!CFGMR3Exists(pIsaExts, pszValueName))
3329 LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3330 else
3331 return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3332 "Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3333 pszValueName, pszValueName);
3334
3335 bool fLegacy;
3336 int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3337 if (RT_SUCCESS(rc))
3338 {
3339 *penmValue = fLegacy;
3340 return VINF_SUCCESS;
3341 }
3342 return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3343 }
3344
3345 return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3346}
3347
3348
3349static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3350{
3351 int rc;
3352
3353 /** @cfgm{/CPUM/SyntheticCpu, boolean, false}
3354 * Enables the Synthetic CPU. The Vendor ID and Processor Name are
3355 * completely overridden by VirtualBox custom strings. Some
3356 * CPUID information is withheld, like the cache info.
3357 *
3358 * This is obsoleted by PortableCpuIdLevel. */
3359 rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pConfig->fSyntheticCpu, false);
3360 AssertRCReturn(rc, rc);
3361
3362 /** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3363 * When non-zero CPUID features that could cause portability issues will be
3364 * stripped. The higher the value the more features gets stripped. Higher
3365 * values should only be used when older CPUs are involved since it may
3366 * harm performance and maybe also cause problems with specific guests. */
3367 rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, pConfig->fSyntheticCpu ? 1 : 0);
3368 AssertLogRelRCReturn(rc, rc);
3369
3370 /** @cfgm{/CPUM/GuestCpuName, string}
3371 * The name of the CPU we're to emulate. The default is the host CPU.
3372 * Note! CPUs other than "host" one is currently unsupported. */
3373 rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3374 AssertLogRelRCReturn(rc, rc);
3375
3376 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3377 * Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3378 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3379 * This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3380 */
3381 rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3382 AssertLogRelRCReturn(rc, rc);
3383
3384 /** @cfgm{/CPUM/InvariantTsc, boolean, complicated}
3385 * Set the invariant TSC flag in 0x80000007 if true, otherwas take default
3386 * action. By default the flag is passed thru as is from the host CPU, except
3387 * on AMD CPUs where it's suppressed to avoid trouble from linux assuming we
3388 * virtualize performance counters.
3389 */
3390 rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, false);
3391 AssertLogRelRCReturn(rc, rc);
3392
3393 /** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3394 * Restrict the reported CPU family+model+stepping of intel CPUs. This is
3395 * probably going to be a temporary hack, so don't depend on this.
3396 * The 1st byte of the value is the stepping, the 2nd byte value is the model
3397 * number and the 3rd byte value is the family, and the 4th value must be zero.
3398 */
3399 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3400 AssertLogRelRCReturn(rc, rc);
3401
3402 /** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3403 * The last standard leaf to keep. The actual last value that is stored in EAX
3404 * is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3405 * removed. (This works independently of and differently from NT4LeafLimit.)
3406 * The default is usually set to what we're able to reasonably sanitize.
3407 */
3408 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3409 AssertLogRelRCReturn(rc, rc);
3410
3411 /** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3412 * The last extended leaf to keep. The actual last value that is stored in EAX
3413 * is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3414 * leaf are removed. The default is set to what we're able to sanitize.
3415 */
3416 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3417 AssertLogRelRCReturn(rc, rc);
3418
3419 /** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3420 * The last extended leaf to keep. The actual last value that is stored in EAX
3421 * is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3422 * leaf are removed. The default is set to what we're able to sanitize.
3423 */
3424 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3425 AssertLogRelRCReturn(rc, rc);
3426
3427
3428 /*
3429 * Instruction Set Architecture (ISA) Extensions.
3430 */
3431 PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3432 if (pIsaExts)
3433 {
3434 rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3435 "CMPXCHG16B"
3436 "|MONITOR"
3437 "|MWaitExtensions"
3438 "|SSE4.1"
3439 "|SSE4.2"
3440 "|AESNI"
3441 "|PCLMUL"
3442 "|POPCNT"
3443 "|MOVBE"
3444 "|RDRAND"
3445 "|RDSEED"
3446 "|CLFLUSHOPT"
3447 , "" /*pszValidNodes*/, "CPUM" /*pszWho*/, 0 /*uInstance*/);
3448 if (RT_FAILURE(rc))
3449 return rc;
3450 }
3451
3452 /** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
3453 * Expose CMPXCHG16B to the guest if supported by the host. For the time
3454 * being the default is to only do this for VMs with nested paging and AMD-V or
3455 * unrestricted guest mode.
3456 */
3457 rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
3458 AssertLogRelRCReturn(rc, rc);
3459
3460 /** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
3461 * Expose MONITOR/MWAIT instructions to the guest.
3462 */
3463 rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
3464 AssertLogRelRCReturn(rc, rc);
3465
3466 /** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
3467 * Expose MWAIT extended features to the guest. For now we expose just MWAIT
3468 * break on interrupt feature (bit 1).
3469 */
3470 rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
3471 AssertLogRelRCReturn(rc, rc);
3472
3473 /** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
3474 * Expose SSE4.1 to the guest if available.
3475 */
3476 rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
3477 AssertLogRelRCReturn(rc, rc);
3478
3479 /** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
3480 * Expose SSE4.2 to the guest if available.
3481 */
3482 rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
3483 AssertLogRelRCReturn(rc, rc);
3484
3485 /** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
3486 * Whether to expose the AES instructions to the guest. For the time being the
3487 * default is to only do this for VMs with nested paging and AMD-V or
3488 * unrestricted guest mode.
3489 */
3490 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
3491 AssertLogRelRCReturn(rc, rc);
3492
3493 /** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
3494 * Whether to expose the PCLMULQDQ instructions to the guest. For the time
3495 * being the default is to only do this for VMs with nested paging and AMD-V or
3496 * unrestricted guest mode.
3497 */
3498 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
3499 AssertLogRelRCReturn(rc, rc);
3500
3501 /** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
3502 * Whether to expose the POPCNT instructions to the guest. For the time
3503 * being the default is to only do this for VMs with nested paging and AMD-V or
3504 * unrestricted guest mode.
3505 */
3506 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
3507 AssertLogRelRCReturn(rc, rc);
3508
3509 /** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
3510 * Whether to expose the MOVBE instructions to the guest. For the time
3511 * being the default is to only do this for VMs with nested paging and AMD-V or
3512 * unrestricted guest mode.
3513 */
3514 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
3515 AssertLogRelRCReturn(rc, rc);
3516
3517 /** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
3518 * Whether to expose the RDRAND instructions to the guest. For the time being
3519 * the default is to only do this for VMs with nested paging and AMD-V or
3520 * unrestricted guest mode.
3521 */
3522 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
3523 AssertLogRelRCReturn(rc, rc);
3524
3525 /** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
3526 * Whether to expose the RDSEED instructions to the guest. For the time being
3527 * the default is to only do this for VMs with nested paging and AMD-V or
3528 * unrestricted guest mode.
3529 */
3530 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
3531 AssertLogRelRCReturn(rc, rc);
3532
3533 /** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
3534 * Whether to expose the CLFLUSHOPT instructions to the guest. For the time
3535 * being the default is to only do this for VMs with nested paging and AMD-V or
3536 * unrestricted guest mode.
3537 */
3538 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
3539 AssertLogRelRCReturn(rc, rc);
3540
3541
3542 /* AMD: */
3543
3544 /** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
3545 * Whether to expose the AMD ABM instructions to the guest. For the time
3546 * being the default is to only do this for VMs with nested paging and AMD-V or
3547 * unrestricted guest mode.
3548 */
3549 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
3550 AssertLogRelRCReturn(rc, rc);
3551
3552 /** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
3553 * Whether to expose the AMD SSE4A instructions to the guest. For the time
3554 * being the default is to only do this for VMs with nested paging and AMD-V or
3555 * unrestricted guest mode.
3556 */
3557 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
3558 AssertLogRelRCReturn(rc, rc);
3559
3560 /** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
3561 * Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
3562 * the time being the default is to only do this for VMs with nested paging and
3563 * AMD-V or unrestricted guest mode.
3564 */
3565 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
3566 AssertLogRelRCReturn(rc, rc);
3567
3568 /** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
3569 * Whether to expose the AMD 3D Now! prefetch instructions to the guest.
3570 * For the time being the default is to only do this for VMs with nested paging
3571 * and AMD-V or unrestricted guest mode.
3572 */
3573 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
3574 AssertLogRelRCReturn(rc, rc);
3575
3576 /** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
3577 * Whether to expose the AMD's MMX Extensions to the guest. For the time being
3578 * the default is to only do this for VMs with nested paging and AMD-V or
3579 * unrestricted guest mode.
3580 */
3581 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
3582 AssertLogRelRCReturn(rc, rc);
3583
3584 return VINF_SUCCESS;
3585}
3586
3587
3588/**
3589 * Initializes the emulated CPU's CPUID & MSR information.
3590 *
3591 * @returns VBox status code.
3592 * @param pVM Pointer to the VM.
3593 */
3594int cpumR3InitCpuIdAndMsrs(PVM pVM)
3595{
3596 PCPUM pCpum = &pVM->cpum.s;
3597 PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
3598
3599 /*
3600 * Read the configuration.
3601 */
3602 CPUMCPUIDCONFIG Config;
3603 RT_ZERO(Config);
3604
3605 int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
3606 AssertRCReturn(rc, rc);
3607
3608 /*
3609 * Get the guest CPU data from the database and/or the host.
3610 *
3611 * The CPUID and MSRs are currently living on the regular heap to avoid
3612 * fragmenting the hyper heap (and because there isn't/wasn't any realloc
3613 * API for the hyper heap). This means special cleanup considerations.
3614 */
3615 rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
3616 if (RT_FAILURE(rc))
3617 return rc == VERR_CPUM_DB_CPU_NOT_FOUND
3618 ? VMSetError(pVM, rc, RT_SRC_POS,
3619 "Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
3620 : rc;
3621
3622 /** @cfgm{/CPUM/MSRs/[Name]/[First|Last|Type|Value|...],}
3623 * Overrides the guest MSRs.
3624 */
3625 rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
3626
3627 /** @cfgm{/CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
3628 * Overrides the CPUID leaf values (from the host CPU usually) used for
3629 * calculating the guest CPUID leaves. This can be used to preserve the CPUID
3630 * values when moving a VM to a different machine. Another use is restricting
3631 * (or extending) the feature set exposed to the guest. */
3632 if (RT_SUCCESS(rc))
3633 rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
3634
3635 if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
3636 rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
3637 "Found unsupported configuration node '/CPUM/CPUID/'. "
3638 "Please use IMachine::setCPUIDLeaf() instead.");
3639
3640 /*
3641 * Pre-explode the CPUID info.
3642 */
3643 if (RT_SUCCESS(rc))
3644 rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
3645
3646 /*
3647 * Sanitize the cpuid information passed on to the guest.
3648 */
3649 if (RT_SUCCESS(rc))
3650 {
3651 rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
3652 if (RT_SUCCESS(rc))
3653 {
3654 cpumR3CpuIdLimitLeaves(pCpum, &Config);
3655 cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
3656 }
3657 }
3658
3659 /*
3660 * Plant our own hypervisor CPUID leaves.
3661 */
3662 if (RT_SUCCESS(rc))
3663 rc = cpumR3CpuIdPlantHypervisorLeaves(pCpum, &Config);
3664
3665 /*
3666 * MSR fudging.
3667 */
3668 if (RT_SUCCESS(rc))
3669 {
3670 /** @cfgm{/CPUM/FudgeMSRs, boolean, true}
3671 * Fudges some common MSRs if not present in the selected CPU database entry.
3672 * This is for trying to keep VMs running when moved between different hosts
3673 * and different CPU vendors. */
3674 bool fEnable;
3675 rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
3676 if (RT_SUCCESS(rc) && fEnable)
3677 {
3678 rc = cpumR3MsrApplyFudge(pVM);
3679 AssertLogRelRC(rc);
3680 }
3681 }
3682 if (RT_SUCCESS(rc))
3683 {
3684 /*
3685 * Move the MSR and CPUID arrays over on the hypervisor heap, and explode
3686 * guest CPU features again.
3687 */
3688 void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
3689 int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
3690 pCpum->GuestInfo.cCpuIdLeaves);
3691 RTMemFree(pvFree);
3692
3693 pvFree = pCpum->GuestInfo.paMsrRangesR3;
3694 int rc2 = MMHyperDupMem(pVM, pvFree,
3695 sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
3696 MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
3697 RTMemFree(pvFree);
3698 AssertLogRelRCReturn(rc1, rc1);
3699 AssertLogRelRCReturn(rc2, rc2);
3700
3701 pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
3702 pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
3703 cpumR3MsrRegStats(pVM);
3704
3705
3706 /*
3707 * Some more configuration that we're applying at the end of everything
3708 * via the CPUMSetGuestCpuIdFeature API.
3709 */
3710
3711 /* Check if PAE was explicitely enabled by the user. */
3712 bool fEnable;
3713 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
3714 AssertRCReturn(rc, rc);
3715 if (fEnable)
3716 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3717
3718 /* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
3719 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
3720 AssertRCReturn(rc, rc);
3721 if (fEnable)
3722 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3723
3724 /* We don't enable the Hypervisor Present bit by default, but it may be needed by some guests. */
3725 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false);
3726 AssertRCReturn(rc, rc);
3727 if (fEnable)
3728 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
3729
3730 return VINF_SUCCESS;
3731 }
3732
3733 /*
3734 * Failed before switching to hyper heap.
3735 */
3736 RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
3737 pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
3738 RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3739 pCpum->GuestInfo.paMsrRangesR3 = NULL;
3740 return rc;
3741}
3742
3743
3744
3745/*
3746 *
3747 *
3748 * Saved state related code.
3749 * Saved state related code.
3750 * Saved state related code.
3751 *
3752 *
3753 */
3754
3755/**
3756 * Called both in pass 0 and the final pass.
3757 *
3758 * @param pVM Pointer to the VM.
3759 * @param pSSM The saved state handle.
3760 */
3761void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
3762{
3763 /*
3764 * Save all the CPU ID leaves.
3765 */
3766 SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
3767 SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
3768 SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
3769 sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
3770
3771 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
3772
3773 /*
3774 * Save a good portion of the raw CPU IDs as well as they may come in
3775 * handy when validating features for raw mode.
3776 */
3777 CPUMCPUID aRawStd[16];
3778 for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
3779 ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
3780 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
3781 SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
3782
3783 CPUMCPUID aRawExt[32];
3784 for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
3785 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
3786 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
3787 SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
3788}
3789
3790
3791static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
3792{
3793 uint32_t cCpuIds;
3794 int rc = SSMR3GetU32(pSSM, &cCpuIds);
3795 if (RT_SUCCESS(rc))
3796 {
3797 if (cCpuIds < 64)
3798 {
3799 for (uint32_t i = 0; i < cCpuIds; i++)
3800 {
3801 CPUMCPUID CpuId;
3802 rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
3803 if (RT_FAILURE(rc))
3804 break;
3805
3806 CPUMCPUIDLEAF NewLeaf;
3807 NewLeaf.uLeaf = uBase + i;
3808 NewLeaf.uSubLeaf = 0;
3809 NewLeaf.fSubLeafMask = 0;
3810 NewLeaf.uEax = CpuId.uEax;
3811 NewLeaf.uEbx = CpuId.uEbx;
3812 NewLeaf.uEcx = CpuId.uEcx;
3813 NewLeaf.uEdx = CpuId.uEdx;
3814 NewLeaf.fFlags = 0;
3815 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
3816 }
3817 }
3818 else
3819 rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3820 }
3821 if (RT_FAILURE(rc))
3822 {
3823 RTMemFree(*ppaLeaves);
3824 *ppaLeaves = NULL;
3825 *pcLeaves = 0;
3826 }
3827 return rc;
3828}
3829
3830
3831static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
3832{
3833 *ppaLeaves = NULL;
3834 *pcLeaves = 0;
3835
3836 int rc;
3837 if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
3838 {
3839 /*
3840 * The new format. Starts by declaring the leave size and count.
3841 */
3842 uint32_t cbLeaf;
3843 SSMR3GetU32(pSSM, &cbLeaf);
3844 uint32_t cLeaves;
3845 rc = SSMR3GetU32(pSSM, &cLeaves);
3846 if (RT_SUCCESS(rc))
3847 {
3848 if (cbLeaf == sizeof(**ppaLeaves))
3849 {
3850 if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
3851 {
3852 /*
3853 * Load the leaves one by one.
3854 *
3855 * The uPrev stuff is a kludge for working around a week worth of bad saved
3856 * states during the CPUID revamp in March 2015. We saved too many leaves
3857 * due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
3858 * garbage entires at the end of the array when restoring. We also had
3859 * a subleaf insertion bug that triggered with the leaf 4 stuff below,
3860 * this kludge doesn't deal correctly with that, but who cares...
3861 */
3862 uint32_t uPrev = 0;
3863 for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
3864 {
3865 CPUMCPUIDLEAF Leaf;
3866 rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
3867 if (RT_SUCCESS(rc))
3868 {
3869 if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
3870 || Leaf.uLeaf >= uPrev)
3871 {
3872 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3873 uPrev = Leaf.uLeaf;
3874 }
3875 else
3876 uPrev = UINT32_MAX;
3877 }
3878 }
3879 }
3880 else
3881 rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
3882 "Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
3883 }
3884 else
3885 rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
3886 "CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
3887 }
3888 }
3889 else
3890 {
3891 /*
3892 * The old format with its three inflexible arrays.
3893 */
3894 rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
3895 if (RT_SUCCESS(rc))
3896 rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
3897 if (RT_SUCCESS(rc))
3898 rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
3899 if (RT_SUCCESS(rc))
3900 {
3901 /*
3902 * Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
3903 */
3904 PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(*ppaLeaves, *pcLeaves, 0, 0);
3905 if ( pLeaf
3906 && ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
3907 {
3908 CPUMCPUIDLEAF Leaf;
3909 Leaf.uLeaf = 4;
3910 Leaf.fSubLeafMask = UINT32_MAX;
3911 Leaf.uSubLeaf = 0;
3912 Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
3913 Leaf.uEcx = UINT32_C(63); /* sets - 1 */
3914 Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
3915 | (UINT32_C(0) << 12) /* phys line partitions - 1 */
3916 | UINT32_C(63); /* system coherency line size - 1 */
3917 Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
3918 | (UINT32_C(0) << 14) /* threads per cache - 1 */
3919 | (UINT32_C(1) << 5) /* cache level */
3920 | UINT32_C(1); /* cache type (data) */
3921 Leaf.fFlags = 0;
3922 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3923 if (RT_SUCCESS(rc))
3924 {
3925 Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
3926 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3927 }
3928 if (RT_SUCCESS(rc))
3929 {
3930 Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
3931 Leaf.uEcx = 4095; /* sets - 1 */
3932 Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
3933 Leaf.uEbx |= UINT32_C(23) << 22;
3934 Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
3935 Leaf.uEax |= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
3936 Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
3937 Leaf.uEax |= UINT32_C(2) << 5;
3938 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3939 }
3940 }
3941 }
3942 }
3943 return rc;
3944}
3945
3946
3947/**
3948 * Loads the CPU ID leaves saved by pass 0, inner worker.
3949 *
3950 * @returns VBox status code.
3951 * @param pVM Pointer to the VM.
3952 * @param pSSM The saved state handle.
3953 * @param uVersion The format version.
3954 * @param paLeaves Guest CPUID leaves loaded from the state.
3955 * @param cLeaves The number of leaves in @a paLeaves.
3956 */
3957int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
3958{
3959 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
3960
3961 /*
3962 * Continue loading the state into stack buffers.
3963 */
3964 CPUMCPUID GuestDefCpuId;
3965 int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
3966 AssertRCReturn(rc, rc);
3967
3968 CPUMCPUID aRawStd[16];
3969 uint32_t cRawStd;
3970 rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
3971 if (cRawStd > RT_ELEMENTS(aRawStd))
3972 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3973 rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
3974 AssertRCReturn(rc, rc);
3975 for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
3976 ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
3977
3978 CPUMCPUID aRawExt[32];
3979 uint32_t cRawExt;
3980 rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
3981 if (cRawExt > RT_ELEMENTS(aRawExt))
3982 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3983 rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
3984 AssertRCReturn(rc, rc);
3985 for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
3986 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
3987
3988 /*
3989 * Get the raw CPU IDs for the current host.
3990 */
3991 CPUMCPUID aHostRawStd[16];
3992 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
3993 ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
3994
3995 CPUMCPUID aHostRawExt[32];
3996 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
3997 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0,
3998 &aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
3999
4000 /*
4001 * Get the host and guest overrides so we don't reject the state because
4002 * some feature was enabled thru these interfaces.
4003 * Note! We currently only need the feature leaves, so skip rest.
4004 */
4005 PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4006 CPUMCPUID aHostOverrideStd[2];
4007 memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4008 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4009
4010 CPUMCPUID aHostOverrideExt[2];
4011 memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4012 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4013
4014 /*
4015 * This can be skipped.
4016 */
4017 bool fStrictCpuIdChecks;
4018 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
4019
4020 /*
4021 * Define a bunch of macros for simplifying the santizing/checking code below.
4022 */
4023 /* Generic expression + failure message. */
4024#define CPUID_CHECK_RET(expr, fmt) \
4025 do { \
4026 if (!(expr)) \
4027 { \
4028 char *pszMsg = RTStrAPrintf2 fmt; /* lack of variadic macros sucks */ \
4029 if (fStrictCpuIdChecks) \
4030 { \
4031 int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4032 RTStrFree(pszMsg); \
4033 return rcCpuid; \
4034 } \
4035 LogRel(("CPUM: %s\n", pszMsg)); \
4036 RTStrFree(pszMsg); \
4037 } \
4038 } while (0)
4039#define CPUID_CHECK_WRN(expr, fmt) \
4040 do { \
4041 if (!(expr)) \
4042 LogRel(fmt); \
4043 } while (0)
4044
4045 /* For comparing two values and bitch if they differs. */
4046#define CPUID_CHECK2_RET(what, host, saved) \
4047 do { \
4048 if ((host) != (saved)) \
4049 { \
4050 if (fStrictCpuIdChecks) \
4051 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4052 N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
4053 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4054 } \
4055 } while (0)
4056#define CPUID_CHECK2_WRN(what, host, saved) \
4057 do { \
4058 if ((host) != (saved)) \
4059 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4060 } while (0)
4061
4062 /* For checking raw cpu features (raw mode). */
4063#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
4064 do { \
4065 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4066 { \
4067 if (fStrictCpuIdChecks) \
4068 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4069 N_(#bit " mismatch: host=%d saved=%d"), \
4070 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
4071 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4072 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4073 } \
4074 } while (0)
4075#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
4076 do { \
4077 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4078 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4079 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4080 } while (0)
4081#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
4082
4083 /* For checking guest features. */
4084#define CPUID_GST_FEATURE_RET(set, reg, bit) \
4085 do { \
4086 if ( (aGuestCpuId##set [1].reg & bit) \
4087 && !(aHostRaw##set [1].reg & bit) \
4088 && !(aHostOverride##set [1].reg & bit) \
4089 ) \
4090 { \
4091 if (fStrictCpuIdChecks) \
4092 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4093 N_(#bit " is not supported by the host but has already exposed to the guest")); \
4094 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4095 } \
4096 } while (0)
4097#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
4098 do { \
4099 if ( (aGuestCpuId##set [1].reg & bit) \
4100 && !(aHostRaw##set [1].reg & bit) \
4101 && !(aHostOverride##set [1].reg & bit) \
4102 ) \
4103 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4104 } while (0)
4105#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
4106 do { \
4107 if ( (aGuestCpuId##set [1].reg & bit) \
4108 && !(aHostRaw##set [1].reg & bit) \
4109 && !(aHostOverride##set [1].reg & bit) \
4110 ) \
4111 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4112 } while (0)
4113#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
4114
4115 /* For checking guest features if AMD guest CPU. */
4116#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
4117 do { \
4118 if ( (aGuestCpuId##set [1].reg & bit) \
4119 && fGuestAmd \
4120 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
4121 && !(aHostOverride##set [1].reg & bit) \
4122 ) \
4123 { \
4124 if (fStrictCpuIdChecks) \
4125 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4126 N_(#bit " is not supported by the host but has already exposed to the guest")); \
4127 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4128 } \
4129 } while (0)
4130#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
4131 do { \
4132 if ( (aGuestCpuId##set [1].reg & bit) \
4133 && fGuestAmd \
4134 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
4135 && !(aHostOverride##set [1].reg & bit) \
4136 ) \
4137 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4138 } while (0)
4139#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
4140 do { \
4141 if ( (aGuestCpuId##set [1].reg & bit) \
4142 && fGuestAmd \
4143 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
4144 && !(aHostOverride##set [1].reg & bit) \
4145 ) \
4146 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4147 } while (0)
4148#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
4149
4150 /* For checking AMD features which have a corresponding bit in the standard
4151 range. (Intel defines very few bits in the extended feature sets.) */
4152#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
4153 do { \
4154 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4155 && !(fHostAmd \
4156 ? aHostRawExt[1].reg & (ExtBit) \
4157 : aHostRawStd[1].reg & (StdBit)) \
4158 && !(aHostOverrideExt[1].reg & (ExtBit)) \
4159 ) \
4160 { \
4161 if (fStrictCpuIdChecks) \
4162 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4163 N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
4164 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4165 } \
4166 } while (0)
4167#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
4168 do { \
4169 if ( (aGuestCpuId[1].reg & (ExtBit)) \
4170 && !(fHostAmd \
4171 ? aHostRawExt[1].reg & (ExtBit) \
4172 : aHostRawStd[1].reg & (StdBit)) \
4173 && !(aHostOverrideExt[1].reg & (ExtBit)) \
4174 ) \
4175 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4176 } while (0)
4177#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
4178 do { \
4179 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4180 && !(fHostAmd \
4181 ? aHostRawExt[1].reg & (ExtBit) \
4182 : aHostRawStd[1].reg & (StdBit)) \
4183 && !(aHostOverrideExt[1].reg & (ExtBit)) \
4184 ) \
4185 LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4186 } while (0)
4187#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
4188
4189 /*
4190 * For raw-mode we'll require that the CPUs are very similar since we don't
4191 * intercept CPUID instructions for user mode applications.
4192 */
4193 if (!HMIsEnabled(pVM))
4194 {
4195 /* CPUID(0) */
4196 CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
4197 && aHostRawStd[0].uEcx == aRawStd[0].uEcx
4198 && aHostRawStd[0].uEdx == aRawStd[0].uEdx,
4199 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
4200 &aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
4201 &aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
4202 CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
4203 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
4204 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
4205
4206 bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
4207
4208 /* CPUID(1).eax */
4209 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
4210 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
4211 CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
4212
4213 /* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
4214 CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
4215 CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
4216
4217 /* CPUID(1).ecx */
4218 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
4219 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
4220 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
4221 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4222 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
4223 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
4224 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
4225 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
4226 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
4227 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
4228 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
4229 CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /*reserved*/ );
4230 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
4231 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
4232 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
4233 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
4234 CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /*reserved*/);
4235 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4236 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
4237 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
4238 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
4239 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4240 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
4241 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
4242 CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4243 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
4244 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
4245 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4246 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
4247 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4248 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4249 CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
4250
4251 /* CPUID(1).edx */
4252 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4253 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4254 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
4255 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4256 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
4257 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
4258 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4259 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4260 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
4261 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4262 CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /*reserved*/);
4263 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4264 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4265 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4266 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4267 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
4268 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4269 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4270 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4271 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
4272 CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /*reserved*/);
4273 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
4274 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
4275 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
4276 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
4277 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
4278 CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
4279 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
4280 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
4281 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
4282 CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /*JMPE/IA64*/);
4283 CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
4284
4285 /* CPUID(2) - config, mostly about caches. ignore. */
4286 /* CPUID(3) - processor serial number. ignore. */
4287 /* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
4288 /* CPUID(5) - mwait/monitor config. ignore. */
4289 /* CPUID(6) - power management. ignore. */
4290 /* CPUID(7) - ???. ignore. */
4291 /* CPUID(8) - ???. ignore. */
4292 /* CPUID(9) - DCA. ignore for now. */
4293 /* CPUID(a) - PeMo info. ignore for now. */
4294 /* CPUID(b) - topology info - takes ECX as input. ignore. */
4295
4296 /* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
4297 CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
4298 || aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
4299 ("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
4300 if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
4301 && aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
4302 {
4303 CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
4304 CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
4305 CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
4306/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
4307 CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
4308 }
4309
4310 /* CPUID(0x80000000) - same as CPUID(0) except for eax.
4311 Note! Intel have/is marking many of the fields here as reserved. We
4312 will verify them as if it's an AMD CPU. */
4313 CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
4314 || !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
4315 (N_("Extended leaves was present on saved state host, but is missing on the current\n")));
4316 if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
4317 {
4318 CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
4319 && aHostRawExt[0].uEcx == aRawExt[0].uEcx
4320 && aHostRawExt[0].uEdx == aRawExt[0].uEdx,
4321 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
4322 &aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
4323 &aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
4324 CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
4325
4326 /* CPUID(0x80000001).eax - same as CPUID(0).eax. */
4327 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
4328 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
4329 CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
4330 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
4331 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
4332
4333 /* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
4334 CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
4335 CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
4336 CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
4337
4338 /* CPUID(0x80000001).ecx */
4339 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
4340 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
4341 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
4342 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
4343 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
4344 CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
4345 CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
4346 CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
4347 CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
4348 CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
4349 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
4350 CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
4351 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
4352 CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
4353 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4354 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4355 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4356 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4357 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4358 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4359 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4360 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4361 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4362 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4363 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4364 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4365 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4366 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4367 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4368 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4369 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4370 CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4371
4372 /* CPUID(0x80000001).edx */
4373 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
4374 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
4375 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
4376 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
4377 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
4378 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
4379 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
4380 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
4381 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
4382 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
4383 CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /*reserved*/);
4384 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
4385 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
4386 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
4387 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
4388 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
4389 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
4390 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
4391 CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /*reserved*/);
4392 CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /*reserved*/);
4393 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4394 CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /*reserved*/);
4395 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4396 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
4397 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
4398 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4399 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4400 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4401 CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /*reserved*/);
4402 CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4403 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4404 CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4405
4406 /** @todo verify the rest as well. */
4407 }
4408 }
4409
4410
4411
4412 /*
4413 * Verify that we can support the features already exposed to the guest on
4414 * this host.
4415 *
4416 * Most of the features we're emulating requires intercepting instruction
4417 * and doing it the slow way, so there is no need to warn when they aren't
4418 * present in the host CPU. Thus we use IGN instead of EMU on these.
4419 *
4420 * Trailing comments:
4421 * "EMU" - Possible to emulate, could be lots of work and very slow.
4422 * "EMU?" - Can this be emulated?
4423 */
4424 CPUMCPUID aGuestCpuIdStd[2];
4425 RT_ZERO(aGuestCpuIdStd);
4426 cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
4427
4428 /* CPUID(1).ecx */
4429 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
4430 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
4431 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
4432 CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4433 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
4434 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
4435 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
4436 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
4437 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
4438 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
4439 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
4440 CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
4441 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
4442 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
4443 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
4444 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
4445 CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /*reserved*/);
4446 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4447 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
4448 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
4449 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
4450 CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4451 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
4452 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
4453 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4454 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
4455 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
4456 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
4457 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
4458 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4459 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4460 CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
4461
4462 /* CPUID(1).edx */
4463 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4464 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4465 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
4466 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4467 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4468 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4469 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4470 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4471 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4472 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4473 CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /*reserved*/);
4474 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4475 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4476 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4477 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4478 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4479 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4480 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4481 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4482 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
4483 CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /*reserved*/);
4484 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
4485 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
4486 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4487 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4488 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
4489 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
4490 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
4491 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
4492 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
4493 CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /*JMPE/IA64*/); // -> EMU
4494 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
4495
4496 /* CPUID(0x80000000). */
4497 CPUMCPUID aGuestCpuIdExt[2];
4498 RT_ZERO(aGuestCpuIdExt);
4499 if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
4500 {
4501 /** @todo deal with no 0x80000001 on the host. */
4502 bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
4503 bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
4504
4505 /* CPUID(0x80000001).ecx */
4506 CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
4507 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
4508 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
4509 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
4510 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
4511 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
4512 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
4513 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
4514 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
4515 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
4516 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
4517 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
4518 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
4519 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
4520 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4521 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4522 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4523 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4524 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4525 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4526 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4527 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4528 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4529 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4530 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4531 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4532 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4533 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4534 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4535 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4536 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4537 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4538
4539 /* CPUID(0x80000001).edx */
4540 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
4541 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
4542 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
4543 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
4544 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4545 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4546 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
4547 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
4548 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4549 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
4550 CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /*reserved*/);
4551 CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
4552 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
4553 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
4554 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
4555 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4556 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
4557 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
4558 CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /*reserved*/);
4559 CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /*reserved*/);
4560 CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4561 CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /*reserved*/);
4562 CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4563 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4564 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4565 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4566 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4567 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4568 CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /*reserved*/);
4569 CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4570 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4571 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4572 }
4573
4574 /** @todo check leaf 7 */
4575
4576 /** @todo XSAVE: Stricter XSAVE feature checks for all modes. */
4577
4578#undef CPUID_CHECK_RET
4579#undef CPUID_CHECK_WRN
4580#undef CPUID_CHECK2_RET
4581#undef CPUID_CHECK2_WRN
4582#undef CPUID_RAW_FEATURE_RET
4583#undef CPUID_RAW_FEATURE_WRN
4584#undef CPUID_RAW_FEATURE_IGN
4585#undef CPUID_GST_FEATURE_RET
4586#undef CPUID_GST_FEATURE_WRN
4587#undef CPUID_GST_FEATURE_EMU
4588#undef CPUID_GST_FEATURE_IGN
4589#undef CPUID_GST_FEATURE2_RET
4590#undef CPUID_GST_FEATURE2_WRN
4591#undef CPUID_GST_FEATURE2_EMU
4592#undef CPUID_GST_FEATURE2_IGN
4593#undef CPUID_GST_AMD_FEATURE_RET
4594#undef CPUID_GST_AMD_FEATURE_WRN
4595#undef CPUID_GST_AMD_FEATURE_EMU
4596#undef CPUID_GST_AMD_FEATURE_IGN
4597
4598 /*
4599 * We're good, commit the CPU ID leaves.
4600 */
4601 MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
4602 pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
4603 pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
4604 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
4605 pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
4606 rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
4607 AssertLogRelRCReturn(rc, rc);
4608
4609 return VINF_SUCCESS;
4610}
4611
4612
4613/**
4614 * Loads the CPU ID leaves saved by pass 0.
4615 *
4616 * @returns VBox status code.
4617 * @param pVM Pointer to the VM.
4618 * @param pSSM The saved state handle.
4619 * @param uVersion The format version.
4620 */
4621int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
4622{
4623 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4624
4625 /*
4626 * Load the CPUID leaves array first and call worker to do the rest, just so
4627 * we can free the memory when we need to without ending up in column 1000.
4628 */
4629 PCPUMCPUIDLEAF paLeaves;
4630 uint32_t cLeaves;
4631 int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
4632 AssertRC(rc);
4633 if (RT_SUCCESS(rc))
4634 {
4635 rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
4636 RTMemFree(paLeaves);
4637 }
4638 return rc;
4639}
4640
4641
4642
4643
4644/*
4645 *
4646 *
4647 * CPUID Info Handler.
4648 * CPUID Info Handler.
4649 * CPUID Info Handler.
4650 *
4651 *
4652 */
4653
4654
4655
4656/**
4657 * Get L1 cache / TLS associativity.
4658 */
4659static const char *getCacheAss(unsigned u, char *pszBuf)
4660{
4661 if (u == 0)
4662 return "res0 ";
4663 if (u == 1)
4664 return "direct";
4665 if (u == 255)
4666 return "fully";
4667 if (u >= 256)
4668 return "???";
4669
4670 RTStrPrintf(pszBuf, 16, "%d way", u);
4671 return pszBuf;
4672}
4673
4674
4675/**
4676 * Get L2 cache associativity.
4677 */
4678const char *getL2CacheAss(unsigned u)
4679{
4680 switch (u)
4681 {
4682 case 0: return "off ";
4683 case 1: return "direct";
4684 case 2: return "2 way ";
4685 case 3: return "res3 ";
4686 case 4: return "4 way ";
4687 case 5: return "res5 ";
4688 case 6: return "8 way ";
4689 case 7: return "res7 ";
4690 case 8: return "16 way";
4691 case 9: return "res9 ";
4692 case 10: return "res10 ";
4693 case 11: return "res11 ";
4694 case 12: return "res12 ";
4695 case 13: return "res13 ";
4696 case 14: return "res14 ";
4697 case 15: return "fully ";
4698 default: return "????";
4699 }
4700}
4701
4702
4703/** CPUID(1).EDX field descriptions. */
4704static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
4705{
4706 DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
4707 DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
4708 DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
4709 DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
4710 DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
4711 DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
4712 DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
4713 DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
4714 DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
4715 DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
4716 DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
4717 DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
4718 DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
4719 DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
4720 DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
4721 DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
4722 DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
4723 DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
4724 DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
4725 DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
4726 DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
4727 DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
4728 DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
4729 DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
4730 DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
4731 DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
4732 DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
4733 DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
4734 DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
4735 DBGFREGSUBFIELD_TERMINATOR()
4736};
4737
4738/** CPUID(1).ECX field descriptions. */
4739static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
4740{
4741 DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
4742 DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
4743 DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
4744 DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
4745 DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
4746 DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
4747 DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
4748 DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
4749 DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
4750 DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
4751 DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
4752 DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
4753 DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
4754 DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
4755 DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
4756 DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
4757 DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
4758 DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
4759 DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
4760 DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
4761 DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
4762 DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
4763 DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
4764 DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
4765 DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
4766 DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
4767 DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
4768 DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
4769 DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
4770 DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
4771 DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
4772 DBGFREGSUBFIELD_TERMINATOR()
4773};
4774
4775/** CPUID(7,0).EBX field descriptions. */
4776static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
4777{
4778 DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
4779 DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
4780 DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
4781 DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
4782 DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
4783 DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
4784 DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
4785 DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
4786 DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
4787 DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
4788 DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
4789 DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
4790 DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
4791 DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
4792 DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
4793 DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
4794 DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
4795 DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
4796 DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
4797 DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
4798 DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
4799 DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
4800 DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
4801 DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
4802 DBGFREGSUBFIELD_TERMINATOR()
4803};
4804
4805/** CPUID(7,0).ECX field descriptions. */
4806static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
4807{
4808 DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
4809 DBGFREGSUBFIELD_TERMINATOR()
4810};
4811
4812
4813/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
4814static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
4815{
4816 DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
4817 DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
4818 DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
4819 DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
4820 DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
4821 DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
4822 DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
4823 DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
4824 DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
4825 DBGFREGSUBFIELD_TERMINATOR()
4826};
4827
4828/** CPUID(13,1).EAX field descriptions. */
4829static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
4830{
4831 DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
4832 DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
4833 DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
4834 DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
4835 DBGFREGSUBFIELD_TERMINATOR()
4836};
4837
4838
4839/** CPUID(0x80000001,0).EDX field descriptions. */
4840static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
4841{
4842 DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
4843 DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
4844 DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
4845 DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
4846 DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
4847 DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
4848 DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
4849 DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
4850 DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
4851 DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
4852 DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
4853 DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
4854 DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
4855 DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
4856 DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
4857 DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
4858 DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
4859 DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
4860 DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
4861 DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
4862 DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
4863 DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
4864 DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
4865 DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
4866 DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
4867 DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
4868 DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
4869 DBGFREGSUBFIELD_TERMINATOR()
4870};
4871
4872/** CPUID(0x80000001,0).ECX field descriptions. */
4873static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
4874{
4875 DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
4876 DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
4877 DBGFREGSUBFIELD_RO("SVM\0" "AMD VM extensions", 2, 1, 0),
4878 DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
4879 DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
4880 DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
4881 DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
4882 DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
4883 DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
4884 DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
4885 DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
4886 DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
4887 DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
4888 DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
4889 DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
4890 DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
4891 DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
4892 DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
4893 DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
4894 DBGFREGSUBFIELD_TERMINATOR()
4895};
4896
4897
4898static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
4899 const char *pszLeadIn, uint32_t cchWidth)
4900{
4901 if (pszLeadIn)
4902 pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
4903
4904 for (uint32_t iBit = 0; iBit < 32; iBit++)
4905 if (RT_BIT_32(iBit) & uVal)
4906 {
4907 while ( pDesc->pszName != NULL
4908 && iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
4909 pDesc++;
4910 if ( pDesc->pszName != NULL
4911 && iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
4912 {
4913 if (pDesc->cBits == 1)
4914 pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
4915 else
4916 {
4917 uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
4918 if (pDesc->cBits < 32)
4919 uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
4920 pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
4921 iBit = pDesc->iFirstBit + pDesc->cBits - 1;
4922 }
4923 }
4924 else
4925 pHlp->pfnPrintf(pHlp, " %u", iBit);
4926 }
4927 if (pszLeadIn)
4928 pHlp->pfnPrintf(pHlp, "\n");
4929}
4930
4931
4932static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
4933 const char *pszLeadIn, uint32_t cchWidth)
4934{
4935 if (pszLeadIn)
4936 pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
4937
4938 for (uint32_t iBit = 0; iBit < 64; iBit++)
4939 if (RT_BIT_64(iBit) & uVal)
4940 {
4941 while ( pDesc->pszName != NULL
4942 && iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
4943 pDesc++;
4944 if ( pDesc->pszName != NULL
4945 && iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
4946 {
4947 if (pDesc->cBits == 1)
4948 pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
4949 else
4950 {
4951 uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
4952 if (pDesc->cBits < 64)
4953 uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
4954 pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
4955 iBit = pDesc->iFirstBit + pDesc->cBits - 1;
4956 }
4957 }
4958 else
4959 pHlp->pfnPrintf(pHlp, " %u", iBit);
4960 }
4961 if (pszLeadIn)
4962 pHlp->pfnPrintf(pHlp, "\n");
4963}
4964
4965
4966static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
4967 const char *pszLeadIn, uint32_t cchWidth)
4968{
4969 if (!uVal)
4970 pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
4971 else
4972 {
4973 pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
4974 cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
4975 pHlp->pfnPrintf(pHlp, " )\n");
4976 }
4977}
4978
4979
4980static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
4981 uint32_t cchWidth)
4982{
4983 uint32_t uCombined = uVal1 | uVal2;
4984 for (uint32_t iBit = 0; iBit < 32; iBit++)
4985 if ( (RT_BIT_32(iBit) & uCombined)
4986 || (iBit == pDesc->iFirstBit && pDesc->pszName) )
4987 {
4988 while ( pDesc->pszName != NULL
4989 && iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
4990 pDesc++;
4991
4992 if ( pDesc->pszName != NULL
4993 && iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
4994 {
4995 size_t cchMnemonic = strlen(pDesc->pszName);
4996 const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
4997 size_t cchDesc = strlen(pszDesc);
4998 uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
4999 uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
5000 if (pDesc->cBits < 32)
5001 {
5002 uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5003 uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5004 }
5005
5006 pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%*s= %u (%u)\n" : " %s - %s%*s= %#x (%#x)\n",
5007 pDesc->pszName, pszDesc,
5008 cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
5009 uFieldValue1, uFieldValue2);
5010
5011 iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
5012 pDesc++;
5013 }
5014 else
5015 pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
5016 RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
5017 }
5018}
5019
5020
5021/**
5022 * Produces a detailed summary of standard leaf 0x00000001.
5023 *
5024 * @param pHlp The info helper functions.
5025 * @param paLeaves The CPUID leaves array.
5026 * @param cLeaves The number of leaves in the array.
5027 * @param pCurLeaf The 0x00000001 leaf.
5028 * @param fVerbose Whether to be very verbose or not.
5029 * @param fIntel Set if intel CPU.
5030 */
5031static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5032 PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
5033{
5034 Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
5035 static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
5036 uint32_t uEAX = pCurLeaf->uEax;
5037 uint32_t uEBX = pCurLeaf->uEbx;
5038
5039 pHlp->pfnPrintf(pHlp,
5040 "%36s %2d \tExtended: %d \tEffective: %d\n"
5041 "%36s %2d \tExtended: %d \tEffective: %d\n"
5042 "%36s %d\n"
5043 "%36s %d (%s)\n"
5044 "%36s %#04x\n"
5045 "%36s %d\n"
5046 "%36s %d\n"
5047 "%36s %#04x\n"
5048 ,
5049 "Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
5050 "Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
5051 "Stepping:", ASMGetCpuStepping(uEAX),
5052 "Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
5053 "APIC ID:", (uEBX >> 24) & 0xff,
5054 "Logical CPUs:",(uEBX >> 16) & 0xff,
5055 "CLFLUSH Size:",(uEBX >> 8) & 0xff,
5056 "Brand ID:", (uEBX >> 0) & 0xff);
5057 if (fVerbose)
5058 {
5059 CPUMCPUID Host;
5060 ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5061 pHlp->pfnPrintf(pHlp, "Features\n");
5062 pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5063 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
5064 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
5065 }
5066 else
5067 {
5068 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
5069 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
5070 }
5071}
5072
5073
5074/**
5075 * Produces a detailed summary of standard leaf 0x00000007.
5076 *
5077 * @param pHlp The info helper functions.
5078 * @param paLeaves The CPUID leaves array.
5079 * @param cLeaves The number of leaves in the array.
5080 * @param pCurLeaf The first 0x00000007 leaf.
5081 * @param fVerbose Whether to be very verbose or not.
5082 */
5083static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5084 PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5085{
5086 Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
5087 pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
5088 for (;;)
5089 {
5090 CPUMCPUID Host;
5091 ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5092
5093 switch (pCurLeaf->uSubLeaf)
5094 {
5095 case 0:
5096 if (fVerbose)
5097 {
5098 pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5099 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
5100 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
5101 if (pCurLeaf->uEdx || Host.uEdx)
5102 pHlp->pfnPrintf(pHlp, "%36 %#x (%#x)\n", "Ext Features EDX:", pCurLeaf->uEdx, Host.uEdx);
5103 }
5104 else
5105 {
5106 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
5107 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
5108 if (pCurLeaf->uEdx)
5109 pHlp->pfnPrintf(pHlp, "%36 %#x\n", "Ext Features EDX:", pCurLeaf->uEdx);
5110 }
5111 break;
5112
5113 default:
5114 if (pCurLeaf->uEdx || pCurLeaf->uEcx || pCurLeaf->uEbx)
5115 pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
5116 pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
5117 break;
5118
5119 }
5120
5121 /* advance. */
5122 pCurLeaf++;
5123 if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5124 || pCurLeaf->uLeaf != 0x7)
5125 break;
5126 }
5127}
5128
5129
5130/**
5131 * Produces a detailed summary of standard leaf 0x0000000d.
5132 *
5133 * @param pHlp The info helper functions.
5134 * @param paLeaves The CPUID leaves array.
5135 * @param cLeaves The number of leaves in the array.
5136 * @param pCurLeaf The first 0x00000007 leaf.
5137 * @param fVerbose Whether to be very verbose or not.
5138 */
5139static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5140 PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5141{
5142 Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
5143 pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
5144 for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5145 {
5146 CPUMCPUID Host;
5147 ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5148
5149 switch (uSubLeaf)
5150 {
5151 case 0:
5152 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5153 pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
5154 pCurLeaf->uEbx, pCurLeaf->uEcx);
5155 pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
5156
5157 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5158 cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
5159 "Valid XCR0 bits, guest:", 42);
5160 cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
5161 "Valid XCR0 bits, host:", 42);
5162 break;
5163
5164 case 1:
5165 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5166 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
5167 cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
5168
5169 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5170 pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0|XSS, guest:", pCurLeaf->uEbx);
5171 pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0|XSS, host:", Host.uEbx);
5172
5173 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5174 cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
5175 " Valid IA32_XSS bits, guest:", 42);
5176 cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
5177 " Valid IA32_XSS bits, host:", 42);
5178 break;
5179
5180 default:
5181 if ( pCurLeaf
5182 && pCurLeaf->uSubLeaf == uSubLeaf
5183 && (pCurLeaf->uEax || pCurLeaf->uEbx || pCurLeaf->uEcx || pCurLeaf->uEdx) )
5184 {
5185 pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
5186 pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5187 if (pCurLeaf->uEcx & ~RT_BIT_32(0))
5188 pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
5189 if (pCurLeaf->uEdx)
5190 pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
5191 pHlp->pfnPrintf(pHlp, " --");
5192 cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5193 pHlp->pfnPrintf(pHlp, "\n");
5194 }
5195 if (Host.uEax || Host.uEbx || Host.uEcx || Host.uEdx)
5196 {
5197 pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
5198 Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5199 if (Host.uEcx & ~RT_BIT_32(0))
5200 pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
5201 if (Host.uEdx)
5202 pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
5203 pHlp->pfnPrintf(pHlp, " --");
5204 cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5205 pHlp->pfnPrintf(pHlp, "\n");
5206 }
5207 break;
5208
5209 }
5210
5211 /* advance. */
5212 if (pCurLeaf)
5213 {
5214 while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5215 && pCurLeaf->uSubLeaf <= uSubLeaf
5216 && pCurLeaf->uLeaf == UINT32_C(0x0000000d))
5217 pCurLeaf++;
5218 if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5219 || pCurLeaf->uLeaf != UINT32_C(0x0000000d))
5220 pCurLeaf = NULL;
5221 }
5222 }
5223}
5224
5225
5226static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5227 PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
5228{
5229 if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5230 && pCurLeaf->uLeaf <= uUpToLeaf)
5231 {
5232 pHlp->pfnPrintf(pHlp,
5233 " %s\n"
5234 " Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
5235 while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5236 && pCurLeaf->uLeaf <= uUpToLeaf)
5237 {
5238 CPUMCPUID Host;
5239 ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5240 pHlp->pfnPrintf(pHlp,
5241 "Gst: %08x/%04x %08x %08x %08x %08x\n"
5242 "Hst: %08x %08x %08x %08x\n",
5243 pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5244 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5245 pCurLeaf++;
5246 }
5247 }
5248
5249 return pCurLeaf;
5250}
5251
5252
5253/**
5254 * Display the guest CpuId leaves.
5255 *
5256 * @param pVM Pointer to the VM.
5257 * @param pHlp The info helper functions.
5258 * @param pszArgs "terse", "default" or "verbose".
5259 */
5260DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
5261{
5262 /*
5263 * Parse the argument.
5264 */
5265 unsigned iVerbosity = 1;
5266 if (pszArgs)
5267 {
5268 pszArgs = RTStrStripL(pszArgs);
5269 if (!strcmp(pszArgs, "terse"))
5270 iVerbosity--;
5271 else if (!strcmp(pszArgs, "verbose"))
5272 iVerbosity++;
5273 }
5274
5275 uint32_t uLeaf;
5276 CPUMCPUID Host;
5277 uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
5278 PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
5279 PCCPUMCPUIDLEAF pCurLeaf;
5280 PCCPUMCPUIDLEAF pNextLeaf;
5281 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
5282 pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
5283 pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
5284
5285 /*
5286 * Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
5287 */
5288 uint32_t cHstMax = ASMCpuId_EAX(0);
5289 uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
5290 uint32_t cMax = RT_MAX(cGstMax, cHstMax);
5291 pHlp->pfnPrintf(pHlp,
5292 " Raw Standard CPUID Leaves\n"
5293 " Leaf/sub-leaf eax ebx ecx edx\n");
5294 for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
5295 {
5296 uint32_t cMaxSubLeaves = 1;
5297 if (uLeaf == 4 || uLeaf == 7 || uLeaf == 0xb)
5298 cMaxSubLeaves = 16;
5299 else if (uLeaf == 0xd)
5300 cMaxSubLeaves = 128;
5301
5302 for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5303 {
5304 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5305 if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5306 && pCurLeaf->uLeaf == uLeaf
5307 && pCurLeaf->uSubLeaf == uSubLeaf)
5308 {
5309 pHlp->pfnPrintf(pHlp,
5310 "Gst: %08x/%04x %08x %08x %08x %08x\n"
5311 "Hst: %08x %08x %08x %08x\n",
5312 uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5313 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5314 pCurLeaf++;
5315 }
5316 else if ( uLeaf != 0xd
5317 || uSubLeaf <= 1
5318 || Host.uEbx != 0 )
5319 pHlp->pfnPrintf(pHlp,
5320 "Hst: %08x/%04x %08x %08x %08x %08x\n",
5321 uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5322
5323 /* Done? */
5324 if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5325 || pCurLeaf->uLeaf != uLeaf)
5326 && ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 || (Host.uEax & 0x000f) >= 8))
5327 || (uLeaf == 0x7 && Host.uEax == 0)
5328 || (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 || (Host.uEcx & 0xff00) >= 8))
5329 || (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
5330 || (uLeaf == 0xd && uSubLeaf >= 128)
5331 )
5332 )
5333 break;
5334 }
5335 }
5336 pNextLeaf = pCurLeaf;
5337
5338 /*
5339 * If verbose, decode it.
5340 */
5341 if (iVerbosity && paLeaves[0].uLeaf == 0)
5342 pHlp->pfnPrintf(pHlp,
5343 "%36s %.04s%.04s%.04s\n"
5344 "%36s 0x00000000-%#010x\n"
5345 ,
5346 "Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
5347 "Supports:", paLeaves[0].uEax);
5348
5349 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
5350 cpumR3CpuIdInfoStdLeaf1Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1, fIntel);
5351
5352 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
5353 cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5354
5355 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
5356 cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5357
5358 pCurLeaf = pNextLeaf;
5359
5360 /*
5361 * Hypervisor leaves.
5362 *
5363 * Unlike most of the other leaves reported, the guest hypervisor leaves
5364 * aren't a subset of the host CPUID bits.
5365 */
5366 pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
5367
5368 ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5369 cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
5370 cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
5371 ? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
5372 cMax = RT_MAX(cHstMax, cGstMax);
5373 if (cMax >= UINT32_C(0x40000000))
5374 {
5375 pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
5376
5377 /** @todo dump these in more detail. */
5378
5379 pCurLeaf = pNextLeaf;
5380 }
5381
5382
5383 /*
5384 * Extended. Custom raw dump here due to ECX sub-leaves host handling.
5385 * Implemented after AMD specs.
5386 */
5387 pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
5388
5389 ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5390 cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
5391 cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
5392 ? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
5393 cMax = RT_MAX(cHstMax, cGstMax);
5394 if (cMax >= UINT32_C(0x80000000))
5395 {
5396
5397 pHlp->pfnPrintf(pHlp,
5398 " Raw Extended CPUID Leaves\n"
5399 " Leaf/sub-leaf eax ebx ecx edx\n");
5400 PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
5401 for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
5402 {
5403 uint32_t cMaxSubLeaves = 1;
5404 if (uLeaf == UINT32_C(0x8000001d))
5405 cMaxSubLeaves = 16;
5406
5407 for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5408 {
5409 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5410 if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5411 && pCurLeaf->uLeaf == uLeaf
5412 && pCurLeaf->uSubLeaf == uSubLeaf)
5413 {
5414 pHlp->pfnPrintf(pHlp,
5415 "Gst: %08x/%04x %08x %08x %08x %08x\n"
5416 "Hst: %08x %08x %08x %08x\n",
5417 uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5418 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5419 pCurLeaf++;
5420 }
5421 else if ( uLeaf != 0xd
5422 || uSubLeaf <= 1
5423 || Host.uEbx != 0 )
5424 pHlp->pfnPrintf(pHlp,
5425 "Hst: %08x/%04x %08x %08x %08x %08x\n",
5426 uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5427
5428 /* Done? */
5429 if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5430 || pCurLeaf->uLeaf != uLeaf)
5431 && (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 || (Host.uEax & 0x000f) >= 8)) )
5432 break;
5433 }
5434 }
5435 pNextLeaf = pCurLeaf;
5436
5437 /*
5438 * Understandable output
5439 */
5440 if (iVerbosity)
5441 pHlp->pfnPrintf(pHlp,
5442 "Ext Name: %.4s%.4s%.4s\n"
5443 "Ext Supports: 0x80000000-%#010x\n",
5444 &pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
5445
5446 pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
5447 if (iVerbosity && pCurLeaf)
5448 {
5449 uint32_t uEAX = pCurLeaf->uEax;
5450 pHlp->pfnPrintf(pHlp,
5451 "Family: %d \tExtended: %d \tEffective: %d\n"
5452 "Model: %d \tExtended: %d \tEffective: %d\n"
5453 "Stepping: %d\n"
5454 "Brand ID: %#05x\n",
5455 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
5456 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
5457 ASMGetCpuStepping(uEAX),
5458 pCurLeaf->uEbx & 0xfff);
5459
5460 if (iVerbosity == 1)
5461 {
5462 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
5463 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
5464 }
5465 else
5466 {
5467 ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5468 pHlp->pfnPrintf(pHlp, "Ext Features\n");
5469 pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5470 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
5471 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
5472 }
5473 }
5474
5475 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
5476 {
5477 char szString[4*4*3+1] = {0};
5478 uint32_t *pu32 = (uint32_t *)szString;
5479 *pu32++ = pCurLeaf->uEax;
5480 *pu32++ = pCurLeaf->uEbx;
5481 *pu32++ = pCurLeaf->uEcx;
5482 *pu32++ = pCurLeaf->uEdx;
5483 pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
5484 if (pCurLeaf)
5485 {
5486 *pu32++ = pCurLeaf->uEax;
5487 *pu32++ = pCurLeaf->uEbx;
5488 *pu32++ = pCurLeaf->uEcx;
5489 *pu32++ = pCurLeaf->uEdx;
5490 }
5491 pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
5492 if (pCurLeaf)
5493 {
5494 *pu32++ = pCurLeaf->uEax;
5495 *pu32++ = pCurLeaf->uEbx;
5496 *pu32++ = pCurLeaf->uEcx;
5497 *pu32++ = pCurLeaf->uEdx;
5498 }
5499 pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
5500 }
5501
5502 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
5503 {
5504 uint32_t uEAX = pCurLeaf->uEax;
5505 uint32_t uEBX = pCurLeaf->uEbx;
5506 uint32_t uECX = pCurLeaf->uEcx;
5507 uint32_t uEDX = pCurLeaf->uEdx;
5508 char sz1[32];
5509 char sz2[32];
5510
5511 pHlp->pfnPrintf(pHlp,
5512 "TLB 2/4M Instr/Uni: %s %3d entries\n"
5513 "TLB 2/4M Data: %s %3d entries\n",
5514 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
5515 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
5516 pHlp->pfnPrintf(pHlp,
5517 "TLB 4K Instr/Uni: %s %3d entries\n"
5518 "TLB 4K Data: %s %3d entries\n",
5519 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
5520 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
5521 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
5522 "L1 Instr Cache Lines Per Tag: %d\n"
5523 "L1 Instr Cache Associativity: %s\n"
5524 "L1 Instr Cache Size: %d KB\n",
5525 (uEDX >> 0) & 0xff,
5526 (uEDX >> 8) & 0xff,
5527 getCacheAss((uEDX >> 16) & 0xff, sz1),
5528 (uEDX >> 24) & 0xff);
5529 pHlp->pfnPrintf(pHlp,
5530 "L1 Data Cache Line Size: %d bytes\n"
5531 "L1 Data Cache Lines Per Tag: %d\n"
5532 "L1 Data Cache Associativity: %s\n"
5533 "L1 Data Cache Size: %d KB\n",
5534 (uECX >> 0) & 0xff,
5535 (uECX >> 8) & 0xff,
5536 getCacheAss((uECX >> 16) & 0xff, sz1),
5537 (uECX >> 24) & 0xff);
5538 }
5539
5540 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
5541 {
5542 uint32_t uEAX = pCurLeaf->uEax;
5543 uint32_t uEBX = pCurLeaf->uEbx;
5544 uint32_t uEDX = pCurLeaf->uEdx;
5545
5546 pHlp->pfnPrintf(pHlp,
5547 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
5548 "L2 TLB 2/4M Data: %s %4d entries\n",
5549 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
5550 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
5551 pHlp->pfnPrintf(pHlp,
5552 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
5553 "L2 TLB 4K Data: %s %4d entries\n",
5554 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
5555 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
5556 pHlp->pfnPrintf(pHlp,
5557 "L2 Cache Line Size: %d bytes\n"
5558 "L2 Cache Lines Per Tag: %d\n"
5559 "L2 Cache Associativity: %s\n"
5560 "L2 Cache Size: %d KB\n",
5561 (uEDX >> 0) & 0xff,
5562 (uEDX >> 8) & 0xf,
5563 getL2CacheAss((uEDX >> 12) & 0xf),
5564 (uEDX >> 16) & 0xffff);
5565 }
5566
5567 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
5568 {
5569 uint32_t uEDX = pCurLeaf->uEdx;
5570
5571 pHlp->pfnPrintf(pHlp, "APM Features: ");
5572 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
5573 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
5574 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
5575 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
5576 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
5577 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
5578 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " MC");
5579 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " HWPSTATE");
5580 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TscInvariant");
5581 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " CPB");
5582 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " EffFreqRO");
5583 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PFI");
5584 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PA");
5585 for (unsigned iBit = 13; iBit < 32; iBit++)
5586 if (uEDX & RT_BIT(iBit))
5587 pHlp->pfnPrintf(pHlp, " %d", iBit);
5588 pHlp->pfnPrintf(pHlp, "\n");
5589
5590 ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5591 pHlp->pfnPrintf(pHlp, "Host Invariant-TSC support: %RTbool\n",
5592 cHstMax >= UINT32_C(0x80000007) && (Host.uEdx & RT_BIT(8)));
5593
5594 }
5595
5596 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0)) != NULL)
5597 {
5598 uint32_t uEAX = pCurLeaf->uEax;
5599 uint32_t uECX = pCurLeaf->uEcx;
5600
5601 pHlp->pfnPrintf(pHlp,
5602 "Physical Address Width: %d bits\n"
5603 "Virtual Address Width: %d bits\n"
5604 "Guest Physical Address Width: %d bits\n",
5605 (uEAX >> 0) & 0xff,
5606 (uEAX >> 8) & 0xff,
5607 (uEAX >> 16) & 0xff);
5608 pHlp->pfnPrintf(pHlp,
5609 "Physical Core Count: %d\n",
5610 (uECX >> 0) & 0xff);
5611 }
5612
5613 pCurLeaf = pNextLeaf;
5614 }
5615
5616
5617
5618 /*
5619 * Centaur.
5620 */
5621 pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
5622
5623 ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5624 cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
5625 ? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
5626 cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
5627 ? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
5628 cMax = RT_MAX(cHstMax, cGstMax);
5629 if (cMax >= UINT32_C(0xc0000000))
5630 {
5631 pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
5632
5633 /*
5634 * Understandable output
5635 */
5636 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
5637 pHlp->pfnPrintf(pHlp,
5638 "Centaur Supports: 0xc0000000-%#010x\n",
5639 pCurLeaf->uEax);
5640
5641 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
5642 {
5643 ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5644 uint32_t uEdxGst = pCurLeaf->uEdx;
5645 uint32_t uEdxHst = Host.uEdx;
5646
5647 if (iVerbosity == 1)
5648 {
5649 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
5650 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
5651 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
5652 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
5653 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
5654 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
5655 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
5656 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
5657 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
5658 /* possibly indicating MM/HE and MM/HE-E on older chips... */
5659 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
5660 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
5661 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
5662 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
5663 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
5664 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
5665 for (unsigned iBit = 14; iBit < 32; iBit++)
5666 if (uEdxGst & RT_BIT(iBit))
5667 pHlp->pfnPrintf(pHlp, " %d", iBit);
5668 pHlp->pfnPrintf(pHlp, "\n");
5669 }
5670 else
5671 {
5672 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
5673 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
5674 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
5675 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
5676 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
5677 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
5678 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
5679 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
5680 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
5681 /* possibly indicating MM/HE and MM/HE-E on older chips... */
5682 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
5683 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
5684 pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
5685 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
5686 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
5687 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
5688 pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
5689 pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
5690 pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
5691 pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
5692 pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
5693 pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
5694 pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
5695 pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
5696 pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
5697 pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
5698 pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
5699 pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
5700 pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
5701 for (unsigned iBit = 27; iBit < 32; iBit++)
5702 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
5703 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
5704 pHlp->pfnPrintf(pHlp, "\n");
5705 }
5706 }
5707
5708 pCurLeaf = pNextLeaf;
5709 }
5710
5711 /*
5712 * The remainder.
5713 */
5714 pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
5715}
5716
5717
5718
5719
5720
5721/*
5722 *
5723 *
5724 * PATM interfaces.
5725 * PATM interfaces.
5726 * PATM interfaces.
5727 *
5728 *
5729 */
5730
5731
5732# if defined(VBOX_WITH_RAW_MODE) || defined(DOXYGEN_RUNNING)
5733/** @name Patchmanager CPUID legacy table APIs
5734 * @{
5735 */
5736
5737/**
5738 * Gets a pointer to the default CPUID leaf.
5739 *
5740 * @returns Raw-mode pointer to the default CPUID leaf (read-only).
5741 * @param pVM Pointer to the VM.
5742 * @remark Intended for PATM only.
5743 */
5744VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
5745{
5746 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
5747}
5748
5749
5750/**
5751 * Gets a number of standard CPUID leaves (PATM only).
5752 *
5753 * @returns Number of leaves.
5754 * @param pVM Pointer to the VM.
5755 * @remark Intended for PATM - legacy, don't use in new code.
5756 */
5757VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
5758{
5759 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
5760}
5761
5762
5763/**
5764 * Gets a number of extended CPUID leaves (PATM only).
5765 *
5766 * @returns Number of leaves.
5767 * @param pVM Pointer to the VM.
5768 * @remark Intended for PATM - legacy, don't use in new code.
5769 */
5770VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
5771{
5772 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
5773}
5774
5775
5776/**
5777 * Gets a number of centaur CPUID leaves.
5778 *
5779 * @returns Number of leaves.
5780 * @param pVM Pointer to the VM.
5781 * @remark Intended for PATM - legacy, don't use in new code.
5782 */
5783VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
5784{
5785 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
5786}
5787
5788
5789/**
5790 * Gets a pointer to the array of standard CPUID leaves.
5791 *
5792 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
5793 *
5794 * @returns Raw-mode pointer to the standard CPUID leaves (read-only).
5795 * @param pVM Pointer to the VM.
5796 * @remark Intended for PATM - legacy, don't use in new code.
5797 */
5798VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
5799{
5800 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
5801}
5802
5803
5804/**
5805 * Gets a pointer to the array of extended CPUID leaves.
5806 *
5807 * CPUMGetGuestCpuIdExtMax() give the size of the array.
5808 *
5809 * @returns Raw-mode pointer to the extended CPUID leaves (read-only).
5810 * @param pVM Pointer to the VM.
5811 * @remark Intended for PATM - legacy, don't use in new code.
5812 */
5813VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
5814{
5815 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
5816}
5817
5818
5819/**
5820 * Gets a pointer to the array of centaur CPUID leaves.
5821 *
5822 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
5823 *
5824 * @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
5825 * @param pVM Pointer to the VM.
5826 * @remark Intended for PATM - legacy, don't use in new code.
5827 */
5828VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
5829{
5830 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
5831}
5832
5833/** @} */
5834# endif /* VBOX_WITH_RAW_MODE || DOXYGEN_RUNNING */
5835
5836#endif /* VBOX_IN_VMM */
5837
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