CPUMR3CpuId.cpp@ 56716

Last change on this file since 56716 was 56094, checked in by vboxsync, 10 years ago
cpumR3LoadCpuIdInner: More correct assertion as we don't actually remove leaf 0xd if XSAVE is disabled, we just zero it.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 290.4 KB

Line
1	/* $Id: CPUMR3CpuId.cpp 56094 2015-05-27 12:08:47Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_CPUM
22	#include <VBox/vmm/cpum.h>
23	#include <VBox/vmm/dbgf.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/vmm/ssm.h>
26	#include "CPUMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/vmm/mm.h>
29
30	#include <VBox/err.h>
31	#include <iprt/asm-amd64-x86.h>
32	#include <iprt/ctype.h>
33	#include <iprt/mem.h>
34	#include <iprt/string.h>
35
36
37	/*******************************************************************************
38	* Defined Constants And Macros *
39	*******************************************************************************/
40	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
41	#define CPUM_CPUID_MAX_LEAVES 2048
42	/* Max size we accept for the XSAVE area. */
43	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
44	/* Min size we accept for the XSAVE area. */
45	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
46
47
48	/*******************************************************************************
49	* Global Variables *
50	*******************************************************************************/
51	/**
52	* The intel pentium family.
53	*/
54	static const CPUMMICROARCH g_aenmIntelFamily06[] =
55	{
56	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
57	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
58	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
59	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
60	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
61	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
62	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
63	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
64	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
65	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
66	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
67	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
68	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
69	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
70	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
71	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
72	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
73	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
74	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
78	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
79	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
80	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
81	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
82	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
83	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
85	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
86	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
87	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
88	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
89	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
90	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
91	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
94	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
95	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
96	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
97	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
98	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
99	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
101	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
102	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
103	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
104	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
105	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
106	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
107	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
110	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
111	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
112	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
113	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
114	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
115	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
117	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
118	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
119	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
121	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
122	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
123	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
126	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
127	/* [71(0x47)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
129	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
130	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
131	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [79(0x4f)] = */ kCpumMicroarch_Intel_Unknown,
136	};
137
138
139
140	/**
141	* Figures out the (sub-)micro architecture given a bit of CPUID info.
142	*
143	* @returns Micro architecture.
144	* @param enmVendor The CPU vendor .
145	* @param bFamily The CPU family.
146	* @param bModel The CPU model.
147	* @param bStepping The CPU stepping.
148	*/
149	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
150	uint8_t bModel, uint8_t bStepping)
151	{
152	if (enmVendor == CPUMCPUVENDOR_AMD)
153	{
154	switch (bFamily)
155	{
156	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
157	case 0x03: return kCpumMicroarch_AMD_Am386;
158	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
159	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
160	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
161	case 0x06:
162	switch (bModel)
163	{
164	case 0: return kCpumMicroarch_AMD_K7_Palomino;
165	case 1: return kCpumMicroarch_AMD_K7_Palomino;
166	case 2: return kCpumMicroarch_AMD_K7_Palomino;
167	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
168	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
169	case 6: return kCpumMicroarch_AMD_K7_Palomino;
170	case 7: return kCpumMicroarch_AMD_K7_Morgan;
171	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
172	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
173	}
174	return kCpumMicroarch_AMD_K7_Unknown;
175	case 0x0f:
176	/*
177	* This family is a friggin mess. Trying my best to make some
178	* sense out of it. Too much happened in the 0x0f family to
179	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
180	*
181	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
182	* cpu-world.com, and other places:
183	* - 130nm:
184	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
185	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
186	* - Newcastle: FC0/DH-CG (errum #180: FE0/DH-CG), FF0/DH-CG
187	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
188	* - Odessa: FC0/DH-CG (errum #180: FE0/DH-CG)
189	* - Paris: FF0/DH-CG, FC0/DH-CG (errum #180: FE0/DH-CG),
190	* - 90nm:
191	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
192	* - Oakville: 10FC0/DH-D0.
193	* - Georgetown: 10FC0/DH-D0.
194	* - Sonora: 10FC0/DH-D0.
195	* - Venus: 20F71/SH-E4
196	* - Troy: 20F51/SH-E4
197	* - Athens: 20F51/SH-E4
198	* - San Diego: 20F71/SH-E4.
199	* - Lancaster: 20F42/SH-E5
200	* - Newark: 20F42/SH-E5.
201	* - Albany: 20FC2/DH-E6.
202	* - Roma: 20FC2/DH-E6.
203	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
204	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
205	* - 90nm introducing Dual core:
206	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
207	* - Italy: 20F10/JH-E1, 20F12/JH-E6
208	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
209	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
210	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
211	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
212	* - Santa Ana: 40F32/JH-F2, /-F3
213	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
214	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
215	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
216	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
217	* - Keene: 40FC2/DH-F2.
218	* - Richmond: 40FC2/DH-F2
219	* - Taylor: 40F82/BH-F2
220	* - Trinidad: 40F82/BH-F2
221	*
222	* - 65nm:
223	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
224	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
225	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
226	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
227	* - Sherman: /-G1, 70FC2/DH-G2.
228	* - Huron: 70FF2/DH-G2.
229	*/
230	if (bModel < 0x10)
231	return kCpumMicroarch_AMD_K8_130nm;
232	if (bModel >= 0x60 && bModel < 0x80)
233	return kCpumMicroarch_AMD_K8_65nm;
234	if (bModel >= 0x40)
235	return kCpumMicroarch_AMD_K8_90nm_AMDV;
236	switch (bModel)
237	{
238	case 0x21:
239	case 0x23:
240	case 0x2b:
241	case 0x2f:
242	case 0x37:
243	case 0x3f:
244	return kCpumMicroarch_AMD_K8_90nm_DualCore;
245	}
246	return kCpumMicroarch_AMD_K8_90nm;
247	case 0x10:
248	return kCpumMicroarch_AMD_K10;
249	case 0x11:
250	return kCpumMicroarch_AMD_K10_Lion;
251	case 0x12:
252	return kCpumMicroarch_AMD_K10_Llano;
253	case 0x14:
254	return kCpumMicroarch_AMD_Bobcat;
255	case 0x15:
256	switch (bModel)
257	{
258	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
259	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
260	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
261	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
262	case 0x11: /* ?? */
263	case 0x12: /* ?? */
264	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
265	}
266	return kCpumMicroarch_AMD_15h_Unknown;
267	case 0x16:
268	return kCpumMicroarch_AMD_Jaguar;
269
270	}
271	return kCpumMicroarch_AMD_Unknown;
272	}
273
274	if (enmVendor == CPUMCPUVENDOR_INTEL)
275	{
276	switch (bFamily)
277	{
278	case 3:
279	return kCpumMicroarch_Intel_80386;
280	case 4:
281	return kCpumMicroarch_Intel_80486;
282	case 5:
283	return kCpumMicroarch_Intel_P5;
284	case 6:
285	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
286	return g_aenmIntelFamily06[bModel];
287	return kCpumMicroarch_Intel_Atom_Unknown;
288	case 15:
289	switch (bModel)
290	{
291	case 0: return kCpumMicroarch_Intel_NB_Willamette;
292	case 1: return kCpumMicroarch_Intel_NB_Willamette;
293	case 2: return kCpumMicroarch_Intel_NB_Northwood;
294	case 3: return kCpumMicroarch_Intel_NB_Prescott;
295	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
296	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
297	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
298	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
299	default: return kCpumMicroarch_Intel_NB_Unknown;
300	}
301	break;
302	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
303	case 1:
304	return kCpumMicroarch_Intel_8086;
305	case 2:
306	return kCpumMicroarch_Intel_80286;
307	}
308	return kCpumMicroarch_Intel_Unknown;
309	}
310
311	if (enmVendor == CPUMCPUVENDOR_VIA)
312	{
313	switch (bFamily)
314	{
315	case 5:
316	switch (bModel)
317	{
318	case 1: return kCpumMicroarch_Centaur_C6;
319	case 4: return kCpumMicroarch_Centaur_C6;
320	case 8: return kCpumMicroarch_Centaur_C2;
321	case 9: return kCpumMicroarch_Centaur_C3;
322	}
323	break;
324
325	case 6:
326	switch (bModel)
327	{
328	case 5: return kCpumMicroarch_VIA_C3_M2;
329	case 6: return kCpumMicroarch_VIA_C3_C5A;
330	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
331	case 8: return kCpumMicroarch_VIA_C3_C5N;
332	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
333	case 10: return kCpumMicroarch_VIA_C7_C5J;
334	case 15: return kCpumMicroarch_VIA_Isaiah;
335	}
336	break;
337	}
338	return kCpumMicroarch_VIA_Unknown;
339	}
340
341	if (enmVendor == CPUMCPUVENDOR_CYRIX)
342	{
343	switch (bFamily)
344	{
345	case 4:
346	switch (bModel)
347	{
348	case 9: return kCpumMicroarch_Cyrix_5x86;
349	}
350	break;
351
352	case 5:
353	switch (bModel)
354	{
355	case 2: return kCpumMicroarch_Cyrix_M1;
356	case 4: return kCpumMicroarch_Cyrix_MediaGX;
357	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
358	}
359	break;
360
361	case 6:
362	switch (bModel)
363	{
364	case 0: return kCpumMicroarch_Cyrix_M2;
365	}
366	break;
367
368	}
369	return kCpumMicroarch_Cyrix_Unknown;
370	}
371
372	return kCpumMicroarch_Unknown;
373	}
374
375
376	/**
377	* Translates a microarchitecture enum value to the corresponding string
378	* constant.
379	*
380	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
381	* NULL if the value is invalid.
382	*
383	* @param enmMicroarch The enum value to convert.
384	*/
385	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
386	{
387	switch (enmMicroarch)
388	{
389	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
390	CASE_RET_STR(kCpumMicroarch_Intel_8086);
391	CASE_RET_STR(kCpumMicroarch_Intel_80186);
392	CASE_RET_STR(kCpumMicroarch_Intel_80286);
393	CASE_RET_STR(kCpumMicroarch_Intel_80386);
394	CASE_RET_STR(kCpumMicroarch_Intel_80486);
395	CASE_RET_STR(kCpumMicroarch_Intel_P5);
396
397	CASE_RET_STR(kCpumMicroarch_Intel_P6);
398	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
399	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
400
401	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
402	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
403	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
404
405	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
406	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
407
408	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
409	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
410	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
411	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
412	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
413	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
414	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
415	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Cannonlake);
416
417	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
418	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
419	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
420	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
421	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
422	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
423	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
424
425	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
426	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
427	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
428	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
429	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
430	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
431	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
432
433	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
434
435	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
436	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
437	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
438	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
439	CASE_RET_STR(kCpumMicroarch_AMD_K5);
440	CASE_RET_STR(kCpumMicroarch_AMD_K6);
441
442	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
443	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
444	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
445	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
446	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
447	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
448	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
449
450	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
451	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
452	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
453	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
454	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
455
456	CASE_RET_STR(kCpumMicroarch_AMD_K10);
457	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
458	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
459	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
460	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
461
462	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
463	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
464	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
465	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
466	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
467
468	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
469
470	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
471
472	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
473	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
474	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
475	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
476	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
477	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
478	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
479	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
480	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
481	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
482	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
483	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
484	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
485
486	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
487	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
488	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
489	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
490	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
491	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
492
493	CASE_RET_STR(kCpumMicroarch_Unknown);
494
495	#undef CASE_RET_STR
496	case kCpumMicroarch_Invalid:
497	case kCpumMicroarch_Intel_End:
498	case kCpumMicroarch_Intel_Core7_End:
499	case kCpumMicroarch_Intel_Atom_End:
500	case kCpumMicroarch_Intel_P6_Core_Atom_End:
501	case kCpumMicroarch_Intel_NB_End:
502	case kCpumMicroarch_AMD_K7_End:
503	case kCpumMicroarch_AMD_K8_End:
504	case kCpumMicroarch_AMD_15h_End:
505	case kCpumMicroarch_AMD_16h_End:
506	case kCpumMicroarch_AMD_End:
507	case kCpumMicroarch_VIA_End:
508	case kCpumMicroarch_Cyrix_End:
509	case kCpumMicroarch_32BitHack:
510	break;
511	/* no default! */
512	}
513
514	return NULL;
515	}
516
517
518
519	/**
520	* Gets a matching leaf in the CPUID leaf array.
521	*
522	* @returns Pointer to the matching leaf, or NULL if not found.
523	* @param paLeaves The CPUID leaves to search. This is sorted.
524	* @param cLeaves The number of leaves in the array.
525	* @param uLeaf The leaf to locate.
526	* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
527	*/
528	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
529	{
530	/* Lazy bird does linear lookup here since this is only used for the
531	occational CPUID overrides. */
532	for (uint32_t i = 0; i < cLeaves; i++)
533	if ( paLeaves[i].uLeaf == uLeaf
534	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
535	return &paLeaves[i];
536	return NULL;
537	}
538
539
540	/**
541	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
542	*
543	* @returns true if found, false it not.
544	* @param paLeaves The CPUID leaves to search. This is sorted.
545	* @param cLeaves The number of leaves in the array.
546	* @param uLeaf The leaf to locate.
547	* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
548	* @param pLegacy The legacy output leaf.
549	*/
550	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
551	PCPUMCPUID pLegacy)
552	{
553	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
554	if (pLeaf)
555	{
556	pLegacy->uEax = pLeaf->uEax;
557	pLegacy->uEbx = pLeaf->uEbx;
558	pLegacy->uEcx = pLeaf->uEcx;
559	pLegacy->uEdx = pLeaf->uEdx;
560	return true;
561	}
562	return false;
563	}
564
565
566	/**
567	* Ensures that the CPUID leaf array can hold one more leaf.
568	*
569	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
570	* failure.
571	* @param pVM Pointer to the VM, used as the heap selector. Passing
572	* NULL uses the host-context heap, otherwise the VM's
573	* hyper heap is used.
574	* @param ppaLeaves Pointer to the variable holding the array pointer
575	* (input/output).
576	* @param cLeaves The current array size.
577	*
578	* @remarks This function will automatically update the R0 and RC pointers when
579	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
580	* be the corresponding VM's CPUID arrays (which is asserted).
581	*/
582	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
583	{
584	/*
585	* If pVM is not specified, we're on the regular heap and can waste a
586	* little space to speed things up.
587	*/
588	uint32_t cAllocated;
589	if (!pVM)
590	{
591	cAllocated = RT_ALIGN(cLeaves, 16);
592	if (cLeaves + 1 > cAllocated)
593	{
594	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
595	if (pvNew)
596	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
597	else
598	{
599	RTMemFree(*ppaLeaves);
600	*ppaLeaves = NULL;
601	}
602	}
603	}
604	/*
605	* Otherwise, we're on the hyper heap and are probably just inserting
606	* one or two leaves and should conserve space.
607	*/
608	else
609	{
610	#ifdef IN_VBOX_CPU_REPORT
611	AssertReleaseFailed();
612	#else
613	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
614	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
615
616	size_t cb = cLeaves * sizeof(**ppaLeaves);
617	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
618	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
619	if (RT_SUCCESS(rc))
620	{
621	/* Update the R0 and RC pointers. */
622	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
623	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
624	}
625	else
626	{
627	*ppaLeaves = NULL;
628	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
629	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
630	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
631	}
632	#endif
633	}
634	return *ppaLeaves;
635	}
636
637
638	/**
639	* Append a CPUID leaf or sub-leaf.
640	*
641	* ASSUMES linear insertion order, so we'll won't need to do any searching or
642	* replace anything. Use cpumR3CpuIdInsert() for those cases.
643	*
644	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
645	* the caller need do no more work.
646	* @param ppaLeaves Pointer to the the pointer to the array of sorted
647	* CPUID leaves and sub-leaves.
648	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
649	* @param uLeaf The leaf we're adding.
650	* @param uSubLeaf The sub-leaf number.
651	* @param fSubLeafMask The sub-leaf mask.
652	* @param uEax The EAX value.
653	* @param uEbx The EBX value.
654	* @param uEcx The ECX value.
655	* @param uEdx The EDX value.
656	* @param fFlags The flags.
657	*/
658	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
659	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
660	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
661	{
662	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
663	return VERR_NO_MEMORY;
664
665	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
666	Assert( *pcLeaves == 0
667	\|\| pNew[-1].uLeaf < uLeaf
668	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
669
670	pNew->uLeaf = uLeaf;
671	pNew->uSubLeaf = uSubLeaf;
672	pNew->fSubLeafMask = fSubLeafMask;
673	pNew->uEax = uEax;
674	pNew->uEbx = uEbx;
675	pNew->uEcx = uEcx;
676	pNew->uEdx = uEdx;
677	pNew->fFlags = fFlags;
678
679	*pcLeaves += 1;
680	return VINF_SUCCESS;
681	}
682
683
684	/**
685	* Checks that we've updated the CPUID leaves array correctly.
686	*
687	* This is a no-op in non-strict builds.
688	*
689	* @param paLeaves The leaves array.
690	* @param cLeaves The number of leaves.
691	*/
692	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
693	{
694	#ifdef VBOX_STRICT
695	for (uint32_t i = 1; i < cLeaves; i++)
696	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
697	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
698	else
699	{
700	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
701	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
702	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
703	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
704	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
705	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
706	}
707	#else
708	NOREF(paLeaves);
709	NOREF(cLeaves);
710	#endif
711	}
712
713
714	/**
715	* Inserts a CPU ID leaf, replacing any existing ones.
716	*
717	* When inserting a simple leaf where we already got a series of subleaves with
718	* the same leaf number (eax), the simple leaf will replace the whole series.
719	*
720	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
721	* host-context heap and has only been allocated/reallocated by the
722	* cpumR3CpuIdEnsureSpace function.
723	*
724	* @returns VBox status code.
725	* @param pVM Pointer to the VM, used as the heap selector.
726	* Passing NULL uses the host-context heap, otherwise
727	* the VM's hyper heap is used.
728	* @param ppaLeaves Pointer to the the pointer to the array of sorted
729	* CPUID leaves and sub-leaves. Must be NULL if using
730	* the hyper heap.
731	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must be
732	* NULL if using the hyper heap.
733	* @param pNewLeaf Pointer to the data of the new leaf we're about to
734	* insert.
735	*/
736	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
737	{
738	/*
739	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
740	*/
741	if (pVM)
742	{
743	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
744	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
745
746	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
747	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
748	}
749
750	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
751	uint32_t cLeaves = *pcLeaves;
752
753	/*
754	* Validate the new leaf a little.
755	*/
756	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
757	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
758	VERR_INVALID_FLAGS);
759	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
760	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
761	VERR_INVALID_PARAMETER);
762	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
763	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
764	VERR_INVALID_PARAMETER);
765	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
766	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
767	VERR_INVALID_PARAMETER);
768
769	/*
770	* Find insertion point. The lazy bird uses the same excuse as in
771	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
772	*/
773	uint32_t i;
774	if ( cLeaves > 0
775	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
776	{
777	/* Add at end. */
778	i = cLeaves;
779	}
780	else if ( cLeaves > 0
781	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
782	{
783	/* Either replacing the last leaf or dealing with sub-leaves. Spool
784	back to the first sub-leaf to pretend we did the linear search. */
785	i = cLeaves - 1;
786	while ( i > 0
787	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
788	i--;
789	}
790	else
791	{
792	/* Linear search from the start. */
793	i = 0;
794	while ( i < cLeaves
795	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
796	i++;
797	}
798	if ( i < cLeaves
799	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
800	{
801	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
802	{
803	/*
804	* The sub-leaf mask differs, replace all existing leaves with the
805	* same leaf number.
806	*/
807	uint32_t c = 1;
808	while ( i + c < cLeaves
809	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
810	c++;
811	if (c > 1 && i + c < cLeaves)
812	{
813	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
814	*pcLeaves = cLeaves -= c - 1;
815	}
816
817	paLeaves[i] = *pNewLeaf;
818	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
819	return VINF_SUCCESS;
820	}
821
822	/* Find sub-leaf insertion point. */
823	while ( i < cLeaves
824	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
825	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
826	i++;
827
828	/*
829	* If we've got an exactly matching leaf, replace it.
830	*/
831	if ( i < cLeaves
832	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
833	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
834	{
835	paLeaves[i] = *pNewLeaf;
836	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
837	return VINF_SUCCESS;
838	}
839	}
840
841	/*
842	* Adding a new leaf at 'i'.
843	*/
844	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
845	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
846	if (!paLeaves)
847	return VERR_NO_MEMORY;
848
849	if (i < cLeaves)
850	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
851	*pcLeaves += 1;
852	paLeaves[i] = *pNewLeaf;
853
854	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
855	return VINF_SUCCESS;
856	}
857
858
859	/**
860	* Removes a range of CPUID leaves.
861	*
862	* This will not reallocate the array.
863	*
864	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
865	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
866	* @param uFirst The first leaf.
867	* @param uLast The last leaf.
868	*/
869	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
870	{
871	uint32_t cLeaves = *pcLeaves;
872
873	Assert(uFirst <= uLast);
874
875	/*
876	* Find the first one.
877	*/
878	uint32_t iFirst = 0;
879	while ( iFirst < cLeaves
880	&& paLeaves[iFirst].uLeaf < uFirst)
881	iFirst++;
882
883	/*
884	* Find the end (last + 1).
885	*/
886	uint32_t iEnd = iFirst;
887	while ( iEnd < cLeaves
888	&& paLeaves[iEnd].uLeaf <= uLast)
889	iEnd++;
890
891	/*
892	* Adjust the array if anything needs removing.
893	*/
894	if (iFirst < iEnd)
895	{
896	if (iEnd < cLeaves)
897	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
898	*pcLeaves = cLeaves -= (iEnd - iFirst);
899	}
900
901	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
902	}
903
904
905
906	/**
907	* Checks if ECX make a difference when reading a given CPUID leaf.
908	*
909	* @returns @c true if it does, @c false if it doesn't.
910	* @param uLeaf The leaf we're reading.
911	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
912	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
913	* final sub-leaf (for leaf 0xb only).
914	*/
915	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
916	{
917	*pfFinalEcxUnchanged = false;
918
919	uint32_t auCur[4];
920	uint32_t auPrev[4];
921	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
922
923	/* Look for sub-leaves. */
924	uint32_t uSubLeaf = 1;
925	for (;;)
926	{
927	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
928	if (memcmp(auCur, auPrev, sizeof(auCur)))
929	break;
930
931	/* Advance / give up. */
932	uSubLeaf++;
933	if (uSubLeaf >= 64)
934	{
935	*pcSubLeaves = 1;
936	return false;
937	}
938	}
939
940	/* Count sub-leaves. */
941	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
942	uint32_t cRepeats = 0;
943	uSubLeaf = 0;
944	for (;;)
945	{
946	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
947
948	/* Figuring out when to stop isn't entirely straight forward as we need
949	to cover undocumented behavior up to a point and implementation shortcuts. */
950
951	/* 1. Look for more than 4 repeating value sets. */
952	if ( auCur[0] == auPrev[0]
953	&& auCur[1] == auPrev[1]
954	&& ( auCur[2] == auPrev[2]
955	\|\| ( auCur[2] == uSubLeaf
956	&& auPrev[2] == uSubLeaf - 1) )
957	&& auCur[3] == auPrev[3])
958	{
959	if ( uLeaf != 0xd
960	\|\| uSubLeaf >= 64
961	\|\| ( auCur[0] == 0
962	&& auCur[1] == 0
963	&& auCur[2] == 0
964	&& auCur[3] == 0
965	&& auPrev[2] == 0) )
966	cRepeats++;
967	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
968	break;
969	}
970	else
971	cRepeats = 0;
972
973	/* 2. Look for zero values. */
974	if ( auCur[0] == 0
975	&& auCur[1] == 0
976	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
977	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
978	&& uSubLeaf >= cMinLeaves)
979	{
980	cRepeats = 0;
981	break;
982	}
983
984	/* 3. Leaf 0xb level type 0 check. */
985	if ( uLeaf == 0xb
986	&& (auCur[2] & 0xff00) == 0
987	&& (auPrev[2] & 0xff00) == 0)
988	{
989	cRepeats = 0;
990	break;
991	}
992
993	/* 99. Give up. */
994	if (uSubLeaf >= 128)
995	{
996	#ifndef IN_VBOX_CPU_REPORT
997	/* Ok, limit it according to the documentation if possible just to
998	avoid annoying users with these detection issues. */
999	uint32_t cDocLimit = UINT32_MAX;
1000	if (uLeaf == 0x4)
1001	cDocLimit = 4;
1002	else if (uLeaf == 0x7)
1003	cDocLimit = 1;
1004	else if (uLeaf == 0xd)
1005	cDocLimit = 63;
1006	else if (uLeaf == 0xf)
1007	cDocLimit = 2;
1008	if (cDocLimit != UINT32_MAX)
1009	{
1010	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1011	*pcSubLeaves = cDocLimit + 3;
1012	return true;
1013	}
1014	#endif
1015	*pcSubLeaves = UINT32_MAX;
1016	return true;
1017	}
1018
1019	/* Advance. */
1020	uSubLeaf++;
1021	memcpy(auPrev, auCur, sizeof(auCur));
1022	}
1023
1024	/* Standard exit. */
1025	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1026	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1027	if (*pcSubLeaves == 0)
1028	*pcSubLeaves = 1;
1029	return true;
1030	}
1031
1032
1033	/**
1034	* Gets a CPU ID leaf.
1035	*
1036	* @returns VBox status code.
1037	* @param pVM Pointer to the VM.
1038	* @param pLeaf Where to store the found leaf.
1039	* @param uLeaf The leaf to locate.
1040	* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
1041	*/
1042	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1043	{
1044	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1045	uLeaf, uSubLeaf);
1046	if (pcLeaf)
1047	{
1048	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1049	return VINF_SUCCESS;
1050	}
1051
1052	return VERR_NOT_FOUND;
1053	}
1054
1055
1056	/**
1057	* Inserts a CPU ID leaf, replacing any existing ones.
1058	*
1059	* @returns VBox status code.
1060	* @param pVM Pointer to the VM.
1061	* @param pNewLeaf Pointer to the leaf being inserted.
1062	*/
1063	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1064	{
1065	/*
1066	* Validate parameters.
1067	*/
1068	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1069	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1070
1071	/*
1072	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1073	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1074	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1075	*/
1076	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1077	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1078	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1079	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1080	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1081	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1082	{
1083	return VERR_NOT_SUPPORTED;
1084	}
1085
1086	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1087	}
1088
1089	/**
1090	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1091	*
1092	* @returns VBox status code.
1093	* @param ppaLeaves Where to return the array pointer on success.
1094	* Use RTMemFree to release.
1095	* @param pcLeaves Where to return the size of the array on
1096	* success.
1097	*/
1098	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1099	{
1100	*ppaLeaves = NULL;
1101	*pcLeaves = 0;
1102
1103	/*
1104	* Try out various candidates. This must be sorted!
1105	*/
1106	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1107	{
1108	{ UINT32_C(0x00000000), false },
1109	{ UINT32_C(0x10000000), false },
1110	{ UINT32_C(0x20000000), false },
1111	{ UINT32_C(0x30000000), false },
1112	{ UINT32_C(0x40000000), false },
1113	{ UINT32_C(0x50000000), false },
1114	{ UINT32_C(0x60000000), false },
1115	{ UINT32_C(0x70000000), false },
1116	{ UINT32_C(0x80000000), false },
1117	{ UINT32_C(0x80860000), false },
1118	{ UINT32_C(0x8ffffffe), true },
1119	{ UINT32_C(0x8fffffff), true },
1120	{ UINT32_C(0x90000000), false },
1121	{ UINT32_C(0xa0000000), false },
1122	{ UINT32_C(0xb0000000), false },
1123	{ UINT32_C(0xc0000000), false },
1124	{ UINT32_C(0xd0000000), false },
1125	{ UINT32_C(0xe0000000), false },
1126	{ UINT32_C(0xf0000000), false },
1127	};
1128
1129	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1130	{
1131	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1132	uint32_t uEax, uEbx, uEcx, uEdx;
1133	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1134
1135	/*
1136	* Does EAX look like a typical leaf count value?
1137	*/
1138	if ( uEax > uLeaf
1139	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1140	{
1141	/* Yes, dump them. */
1142	uint32_t cLeaves = uEax - uLeaf + 1;
1143	while (cLeaves-- > 0)
1144	{
1145	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1146
1147	uint32_t fFlags = 0;
1148
1149	/* There are currently three known leaves containing an APIC ID
1150	that needs EMT specific attention */
1151	if (uLeaf == 1)
1152	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1153	else if (uLeaf == 0xb && uEcx != 0)
1154	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1155	else if ( uLeaf == UINT32_C(0x8000001e)
1156	&& ( uEax
1157	\|\| uEbx
1158	\|\| uEdx
1159	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1160	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1161
1162
1163	/* Check three times here to reduce the chance of CPU migration
1164	resulting in false positives with things like the APIC ID. */
1165	uint32_t cSubLeaves;
1166	bool fFinalEcxUnchanged;
1167	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1168	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1169	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1170	{
1171	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1172	{
1173	/* This shouldn't happen. But in case it does, file all
1174	relevant details in the release log. */
1175	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1176	LogRel(("------------------ dump of problematic subleaves ------------------\n"));
1177	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1178	{
1179	uint32_t auTmp[4];
1180	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1181	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1182	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1183	}
1184	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1185	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1186	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1187	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1188	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1189	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1190	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1191	}
1192
1193	if (fFinalEcxUnchanged)
1194	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1195
1196	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1197	{
1198	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1199	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1200	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1201	if (RT_FAILURE(rc))
1202	return rc;
1203	}
1204	}
1205	else
1206	{
1207	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1208	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1209	if (RT_FAILURE(rc))
1210	return rc;
1211	}
1212
1213	/* next */
1214	uLeaf++;
1215	}
1216	}
1217	/*
1218	* Special CPUIDs needs special handling as they don't follow the
1219	* leaf count principle used above.
1220	*/
1221	else if (s_aCandidates[iOuter].fSpecial)
1222	{
1223	bool fKeep = false;
1224	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1225	fKeep = true;
1226	else if ( uLeaf == 0x8fffffff
1227	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1228	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1229	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1230	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1231	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1232	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1233	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1234	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1235	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1236	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1237	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1238	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1239	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1240	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1241	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1242	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1243	fKeep = true;
1244	if (fKeep)
1245	{
1246	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1247	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1248	if (RT_FAILURE(rc))
1249	return rc;
1250	}
1251	}
1252	}
1253
1254	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1255	return VINF_SUCCESS;
1256	}
1257
1258
1259	/**
1260	* Determines the method the CPU uses to handle unknown CPUID leaves.
1261	*
1262	* @returns VBox status code.
1263	* @param penmUnknownMethod Where to return the method.
1264	* @param pDefUnknown Where to return default unknown values. This
1265	* will be set, even if the resulting method
1266	* doesn't actually needs it.
1267	*/
1268	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1269	{
1270	uint32_t uLastStd = ASMCpuId_EAX(0);
1271	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1272	if (!ASMIsValidExtRange(uLastExt))
1273	uLastExt = 0x80000000;
1274
1275	uint32_t auChecks[] =
1276	{
1277	uLastStd + 1,
1278	uLastStd + 5,
1279	uLastStd + 8,
1280	uLastStd + 32,
1281	uLastStd + 251,
1282	uLastExt + 1,
1283	uLastExt + 8,
1284	uLastExt + 15,
1285	uLastExt + 63,
1286	uLastExt + 255,
1287	0x7fbbffcc,
1288	0x833f7872,
1289	0xefff2353,
1290	0x35779456,
1291	0x1ef6d33e,
1292	};
1293
1294	static const uint32_t s_auValues[] =
1295	{
1296	0xa95d2156,
1297	0x00000001,
1298	0x00000002,
1299	0x00000008,
1300	0x00000000,
1301	0x55773399,
1302	0x93401769,
1303	0x12039587,
1304	};
1305
1306	/*
1307	* Simple method, all zeros.
1308	*/
1309	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1310	pDefUnknown->uEax = 0;
1311	pDefUnknown->uEbx = 0;
1312	pDefUnknown->uEcx = 0;
1313	pDefUnknown->uEdx = 0;
1314
1315	/*
1316	* Intel has been observed returning the last standard leaf.
1317	*/
1318	uint32_t auLast[4];
1319	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1320
1321	uint32_t cChecks = RT_ELEMENTS(auChecks);
1322	while (cChecks > 0)
1323	{
1324	uint32_t auCur[4];
1325	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1326	if (memcmp(auCur, auLast, sizeof(auCur)))
1327	break;
1328	cChecks--;
1329	}
1330	if (cChecks == 0)
1331	{
1332	/* Now, what happens when the input changes? Esp. ECX. */
1333	uint32_t cTotal = 0;
1334	uint32_t cSame = 0;
1335	uint32_t cLastWithEcx = 0;
1336	uint32_t cNeither = 0;
1337	uint32_t cValues = RT_ELEMENTS(s_auValues);
1338	while (cValues > 0)
1339	{
1340	uint32_t uValue = s_auValues[cValues - 1];
1341	uint32_t auLastWithEcx[4];
1342	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1343	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1344
1345	cChecks = RT_ELEMENTS(auChecks);
1346	while (cChecks > 0)
1347	{
1348	uint32_t auCur[4];
1349	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1350	if (!memcmp(auCur, auLast, sizeof(auCur)))
1351	{
1352	cSame++;
1353	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1354	cLastWithEcx++;
1355	}
1356	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1357	cLastWithEcx++;
1358	else
1359	cNeither++;
1360	cTotal++;
1361	cChecks--;
1362	}
1363	cValues--;
1364	}
1365
1366	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1367	if (cSame == cTotal)
1368	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1369	else if (cLastWithEcx == cTotal)
1370	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1371	else
1372	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1373	pDefUnknown->uEax = auLast[0];
1374	pDefUnknown->uEbx = auLast[1];
1375	pDefUnknown->uEcx = auLast[2];
1376	pDefUnknown->uEdx = auLast[3];
1377	return VINF_SUCCESS;
1378	}
1379
1380	/*
1381	* Unchanged register values?
1382	*/
1383	cChecks = RT_ELEMENTS(auChecks);
1384	while (cChecks > 0)
1385	{
1386	uint32_t const uLeaf = auChecks[cChecks - 1];
1387	uint32_t cValues = RT_ELEMENTS(s_auValues);
1388	while (cValues > 0)
1389	{
1390	uint32_t uValue = s_auValues[cValues - 1];
1391	uint32_t auCur[4];
1392	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1393	if ( auCur[0] != uLeaf
1394	\|\| auCur[1] != uValue
1395	\|\| auCur[2] != uValue
1396	\|\| auCur[3] != uValue)
1397	break;
1398	cValues--;
1399	}
1400	if (cValues != 0)
1401	break;
1402	cChecks--;
1403	}
1404	if (cChecks == 0)
1405	{
1406	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1407	return VINF_SUCCESS;
1408	}
1409
1410	/*
1411	* Just go with the simple method.
1412	*/
1413	return VINF_SUCCESS;
1414	}
1415
1416
1417	/**
1418	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1419	*
1420	* @returns Read only name string.
1421	* @param enmUnknownMethod The method to translate.
1422	*/
1423	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1424	{
1425	switch (enmUnknownMethod)
1426	{
1427	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1428	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1429	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1430	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1431
1432	case CPUMUNKNOWNCPUID_INVALID:
1433	case CPUMUNKNOWNCPUID_END:
1434	case CPUMUNKNOWNCPUID_32BIT_HACK:
1435	break;
1436	}
1437	return "Invalid-unknown-CPUID-method";
1438	}
1439
1440
1441	/**
1442	* Detect the CPU vendor give n the
1443	*
1444	* @returns The vendor.
1445	* @param uEAX EAX from CPUID(0).
1446	* @param uEBX EBX from CPUID(0).
1447	* @param uECX ECX from CPUID(0).
1448	* @param uEDX EDX from CPUID(0).
1449	*/
1450	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1451	{
1452	if (ASMIsValidStdRange(uEAX))
1453	{
1454	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1455	return CPUMCPUVENDOR_AMD;
1456
1457	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1458	return CPUMCPUVENDOR_INTEL;
1459
1460	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1461	return CPUMCPUVENDOR_VIA;
1462
1463	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1464	&& uECX == UINT32_C(0x64616574)
1465	&& uEDX == UINT32_C(0x736E4978))
1466	return CPUMCPUVENDOR_CYRIX;
1467
1468	/* "Geode by NSC", example: family 5, model 9. */
1469
1470	/** @todo detect the other buggers... */
1471	}
1472
1473	return CPUMCPUVENDOR_UNKNOWN;
1474	}
1475
1476
1477	/**
1478	* Translates a CPU vendor enum value into the corresponding string constant.
1479	*
1480	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1481	* value name. This can be useful when generating code.
1482	*
1483	* @returns Read only name string.
1484	* @param enmVendor The CPU vendor value.
1485	*/
1486	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1487	{
1488	switch (enmVendor)
1489	{
1490	case CPUMCPUVENDOR_INTEL: return "INTEL";
1491	case CPUMCPUVENDOR_AMD: return "AMD";
1492	case CPUMCPUVENDOR_VIA: return "VIA";
1493	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1494	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1495
1496	case CPUMCPUVENDOR_INVALID:
1497	case CPUMCPUVENDOR_32BIT_HACK:
1498	break;
1499	}
1500	return "Invalid-cpu-vendor";
1501	}
1502
1503
1504	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1505	{
1506	/* Could do binary search, doing linear now because I'm lazy. */
1507	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1508	while (cLeaves-- > 0)
1509	{
1510	if (pLeaf->uLeaf == uLeaf)
1511	return pLeaf;
1512	pLeaf++;
1513	}
1514	return NULL;
1515	}
1516
1517
1518	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1519	{
1520	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1521	if ( !pLeaf
1522	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1523	return pLeaf;
1524
1525	/* Linear sub-leaf search. Lazy as usual. */
1526	cLeaves -= pLeaf - paLeaves;
1527	while ( cLeaves-- > 0
1528	&& pLeaf->uLeaf == uLeaf)
1529	{
1530	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1531	return pLeaf;
1532	pLeaf++;
1533	}
1534
1535	return NULL;
1536	}
1537
1538
1539	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1540	{
1541	RT_ZERO(*pFeatures);
1542	if (cLeaves >= 2)
1543	{
1544	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1545	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1546	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1547	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1548	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1549	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1550
1551	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1552	pStd0Leaf->uEbx,
1553	pStd0Leaf->uEcx,
1554	pStd0Leaf->uEdx);
1555	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1556	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1557	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1558	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1559	pFeatures->uFamily,
1560	pFeatures->uModel,
1561	pFeatures->uStepping);
1562
1563	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1564	if (pLeaf)
1565	pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff;
1566	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1567	pFeatures->cMaxPhysAddrWidth = 36;
1568	else
1569	pFeatures->cMaxPhysAddrWidth = 32;
1570
1571	/* Standard features. */
1572	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1573	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1574	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1575	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1576	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1577	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1578	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1579	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1580	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1581	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1582	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1583	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1584	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1585	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1586	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1587	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1588	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1589	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1590	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1591	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1592	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1593	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1594
1595	/* Structured extended features. */
1596	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1597	if (pSxfLeaf0)
1598	{
1599	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEcx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1600	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEcx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1601	}
1602
1603	/* MWAIT/MONITOR leaf. */
1604	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1605	if (pMWaitLeaf)
1606	{
1607	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1608	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1609	}
1610
1611	/* Extended features. */
1612	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1613	if (pExtLeaf)
1614	{
1615	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1616	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1617	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1618	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1619	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1620	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1621	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1622	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1623	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1624	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1625	}
1626
1627	if ( pExtLeaf
1628	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1629	{
1630	/* AMD features. */
1631	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1632	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1633	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1634	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1635	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1636	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1637	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1638	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1639	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1640	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1641	}
1642
1643	/*
1644	* Quirks.
1645	*/
1646	pFeatures->fLeakyFxSR = pExtLeaf
1647	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1648	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1649	&& pFeatures->uFamily >= 6 /* K7 and up */;
1650
1651	/*
1652	* Max extended (/FPU) state.
1653	*/
1654	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1655	if (pFeatures->fXSaveRstor)
1656	{
1657	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1658	if (pXStateLeaf0)
1659	{
1660	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1661	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1662	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1663	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1664	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1665	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1666	{
1667	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1668
1669	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1670	if ( pXStateLeaf1
1671	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1672	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1673	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1674	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEbx;
1675	}
1676	else
1677	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1678	pFeatures->fXSaveRstor = 0);
1679	}
1680	else
1681	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1682	pFeatures->fXSaveRstor = 0);
1683	}
1684	}
1685	else
1686	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1687	return VINF_SUCCESS;
1688	}
1689
1690
1691	/*
1692	*
1693	* Init related code.
1694	* Init related code.
1695	* Init related code.
1696	*
1697	*
1698	*/
1699	#ifdef VBOX_IN_VMM
1700
1701
1702	/**
1703	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1704	*
1705	* This ignores the fSubLeafMask.
1706	*
1707	* @returns Pointer to the matching leaf, or NULL if not found.
1708	* @param paLeaves The CPUID leaves to search. This is sorted.
1709	* @param cLeaves The number of leaves in the array.
1710	* @param uLeaf The leaf to locate.
1711	* @param uSubLeaf The subleaf to locate.
1712	*/
1713	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1714	{
1715	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1716	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1717	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1718	if (iEnd)
1719	{
1720	uint32_t iBegin = 0;
1721	for (;;)
1722	{
1723	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1724	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1725	if (uNeedle < uCur)
1726	{
1727	if (i > iBegin)
1728	iEnd = i;
1729	else
1730	break;
1731	}
1732	else if (uNeedle > uCur)
1733	{
1734	if (i + 1 < iEnd)
1735	iBegin = i + 1;
1736	else
1737	break;
1738	}
1739	else
1740	return &paLeaves[i];
1741	}
1742	}
1743	return NULL;
1744	}
1745
1746
1747	/**
1748	* Loads MSR range overrides.
1749	*
1750	* This must be called before the MSR ranges are moved from the normal heap to
1751	* the hyper heap!
1752	*
1753	* @returns VBox status code (VMSetError called).
1754	* @param pVM Pointer to the cross context VM structure
1755	* @param pMsrNode The CFGM node with the MSR overrides.
1756	*/
1757	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1758	{
1759	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1760	{
1761	/*
1762	* Assemble a valid MSR range.
1763	*/
1764	CPUMMSRRANGE MsrRange;
1765	MsrRange.offCpumCpu = 0;
1766	MsrRange.fReserved = 0;
1767
1768	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1769	if (RT_FAILURE(rc))
1770	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1771
1772	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1773	if (RT_FAILURE(rc))
1774	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1775	MsrRange.szName, rc);
1776
1777	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1778	if (RT_FAILURE(rc))
1779	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1780	MsrRange.szName, rc);
1781
1782	char szType[32];
1783	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1784	if (RT_FAILURE(rc))
1785	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1786	MsrRange.szName, rc);
1787	if (!RTStrICmp(szType, "FixedValue"))
1788	{
1789	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1790	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1791
1792	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1793	if (RT_FAILURE(rc))
1794	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1795	MsrRange.szName, rc);
1796
1797	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1798	if (RT_FAILURE(rc))
1799	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1800	MsrRange.szName, rc);
1801
1802	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1803	if (RT_FAILURE(rc))
1804	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1805	MsrRange.szName, rc);
1806	}
1807	else
1808	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1809	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1810
1811	/*
1812	* Insert the range into the table (replaces/splits/shrinks existing
1813	* MSR ranges).
1814	*/
1815	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1816	&MsrRange);
1817	if (RT_FAILURE(rc))
1818	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
1819	}
1820
1821	return VINF_SUCCESS;
1822	}
1823
1824
1825	/**
1826	* Loads CPUID leaf overrides.
1827	*
1828	* This must be called before the CPUID leaves are moved from the normal
1829	* heap to the hyper heap!
1830	*
1831	* @returns VBox status code (VMSetError called).
1832	* @param pVM Pointer to the cross context VM structure
1833	* @param pParentNode The CFGM node with the CPUID leaves.
1834	* @param pszLabel How to label the overrides we're loading.
1835	*/
1836	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
1837	{
1838	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1839	{
1840	/*
1841	* Get the leaf and subleaf numbers.
1842	*/
1843	char szName[128];
1844	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
1845	if (RT_FAILURE(rc))
1846	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
1847
1848	/* The leaf number is either specified directly or thru the node name. */
1849	uint32_t uLeaf;
1850	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
1851	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1852	{
1853	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
1854	if (rc != VINF_SUCCESS)
1855	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
1856	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
1857	}
1858	else if (RT_FAILURE(rc))
1859	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
1860	pszLabel, szName, rc);
1861
1862	uint32_t uSubLeaf;
1863	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
1864	if (RT_FAILURE(rc))
1865	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
1866	pszLabel, szName, rc);
1867
1868	uint32_t fSubLeafMask;
1869	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
1870	if (RT_FAILURE(rc))
1871	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
1872	pszLabel, szName, rc);
1873
1874	/*
1875	* Look up the specified leaf, since the output register values
1876	* defaults to any existing values. This allows overriding a single
1877	* register, without needing to know the other values.
1878	*/
1879	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
1880	CPUMCPUIDLEAF Leaf;
1881	if (pLeaf)
1882	Leaf = *pLeaf;
1883	else
1884	RT_ZERO(Leaf);
1885	Leaf.uLeaf = uLeaf;
1886	Leaf.uSubLeaf = uSubLeaf;
1887	Leaf.fSubLeafMask = fSubLeafMask;
1888
1889	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
1890	if (RT_FAILURE(rc))
1891	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
1892	pszLabel, szName, rc);
1893	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
1894	if (RT_FAILURE(rc))
1895	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
1896	pszLabel, szName, rc);
1897	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
1898	if (RT_FAILURE(rc))
1899	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
1900	pszLabel, szName, rc);
1901	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
1902	if (RT_FAILURE(rc))
1903	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
1904	pszLabel, szName, rc);
1905
1906	/*
1907	* Insert the leaf into the table (replaces existing ones).
1908	*/
1909	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1910	&Leaf);
1911	if (RT_FAILURE(rc))
1912	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
1913	}
1914
1915	return VINF_SUCCESS;
1916	}
1917
1918
1919
1920	/**
1921	* Fetches overrides for a CPUID leaf.
1922	*
1923	* @returns VBox status code.
1924	* @param pLeaf The leaf to load the overrides into.
1925	* @param pCfgNode The CFGM node containing the overrides
1926	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
1927	* @param iLeaf The CPUID leaf number.
1928	*/
1929	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
1930	{
1931	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
1932	if (pLeafNode)
1933	{
1934	uint32_t u32;
1935	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
1936	if (RT_SUCCESS(rc))
1937	pLeaf->uEax = u32;
1938	else
1939	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1940
1941	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
1942	if (RT_SUCCESS(rc))
1943	pLeaf->uEbx = u32;
1944	else
1945	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1946
1947	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
1948	if (RT_SUCCESS(rc))
1949	pLeaf->uEcx = u32;
1950	else
1951	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1952
1953	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
1954	if (RT_SUCCESS(rc))
1955	pLeaf->uEdx = u32;
1956	else
1957	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1958
1959	}
1960	return VINF_SUCCESS;
1961	}
1962
1963
1964	/**
1965	* Load the overrides for a set of CPUID leaves.
1966	*
1967	* @returns VBox status code.
1968	* @param paLeaves The leaf array.
1969	* @param cLeaves The number of leaves.
1970	* @param uStart The start leaf number.
1971	* @param pCfgNode The CFGM node containing the overrides
1972	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
1973	*/
1974	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
1975	{
1976	for (uint32_t i = 0; i < cLeaves; i++)
1977	{
1978	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
1979	if (RT_FAILURE(rc))
1980	return rc;
1981	}
1982
1983	return VINF_SUCCESS;
1984	}
1985
1986	/**
1987	* Init a set of host CPUID leaves.
1988	*
1989	* @returns VBox status code.
1990	* @param paLeaves The leaf array.
1991	* @param cLeaves The number of leaves.
1992	* @param uStart The start leaf number.
1993	* @param pCfgNode The /CPUM/HostCPUID/ node.
1994	*/
1995	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
1996	{
1997	/* Using the ECX variant for all of them can't hurt... */
1998	for (uint32_t i = 0; i < cLeaves; i++)
1999	ASMCpuIdExSlow(uStart + i, 0, 0, 0, &paLeaves[i].uEax, &paLeaves[i].uEbx, &paLeaves[i].uEcx, &paLeaves[i].uEdx);
2000
2001	/* Load CPUID leaf override; we currently don't care if the user
2002	specifies features the host CPU doesn't support. */
2003	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
2004	}
2005
2006
2007	/**
2008	* Installs the CPUID leaves and explods the data into structures like
2009	* GuestFeatures and CPUMCTX::aoffXState.
2010	*
2011	* @returns VBox status code.
2012	* @param pVM The cross context VM handle.
2013	* @param pCpum The CPUM part of @a VM.
2014	* @param paLeaves The leaves. These will be copied (but not freed).
2015	* @param cLeaves The number of leaves.
2016	*/
2017	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
2018	{
2019	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2020
2021	/*
2022	* Install the CPUID information.
2023	*/
2024	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2025	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2026
2027	AssertLogRelRCReturn(rc, rc);
2028	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2029	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2030	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2031	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2032	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2033
2034	/*
2035	* Update the default CPUID leaf if necessary.
2036	*/
2037	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2038	{
2039	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2040	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2041	{
2042	/* We don't use CPUID(0).eax here because of the NT hack that only
2043	changes that value without actually removing any leaves. */
2044	uint32_t i = 0;
2045	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2046	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2047	{
2048	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2049	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2050	i++;
2051	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2052	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2053	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2054	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2055	}
2056	break;
2057	}
2058	default:
2059	break;
2060	}
2061
2062	/*
2063	* Explode the guest CPU features.
2064	*/
2065	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
2066	AssertLogRelRCReturn(rc, rc);
2067
2068	/*
2069	* Adjust the scalable bus frequency according to the CPUID information
2070	* we're now using.
2071	*/
2072	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2073	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2074	? UINT64_C(100000000) /* 100MHz */
2075	: UINT64_C(133333333); /* 133MHz */
2076
2077	/*
2078	* Populate the legacy arrays. Currently used for everything, later only
2079	* for patch manager.
2080	*/
2081	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2082	{
2083	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2084	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2085	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2086	};
2087	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2088	{
2089	uint32_t cLeft = aOldRanges[i].cCpuIds;
2090	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2091	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2092	while (cLeft-- > 0)
2093	{
2094	uLeaf--;
2095	pLegacyLeaf--;
2096
2097	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2098	if (pLeaf)
2099	{
2100	pLegacyLeaf->uEax = pLeaf->uEax;
2101	pLegacyLeaf->uEbx = pLeaf->uEbx;
2102	pLegacyLeaf->uEcx = pLeaf->uEcx;
2103	pLegacyLeaf->uEdx = pLeaf->uEdx;
2104	}
2105	else
2106	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2107	}
2108	}
2109
2110	/*
2111	* Configure XSAVE offsets according to the CPUID info.
2112	*/
2113	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2114	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2115	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2116	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2117	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2118	{
2119	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2120	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n"), VERR_CPUM_IPE_1);
2121	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n"), VERR_CPUM_IPE_1);
2122	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2123	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2124	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2125	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2126	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2127	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2128	pCpum->GuestFeatures.cbMaxExtendedState),
2129	VERR_CPUM_IPE_1);
2130	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2131	}
2132	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2133
2134	/* Copy the CPU #0 data to the other CPUs. */
2135	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2136	{
2137	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2138	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2139	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2140	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2141	}
2142
2143	return VINF_SUCCESS;
2144	}
2145
2146
2147	/** @name Instruction Set Extension Options
2148	* @{ */
2149	/** Configuration option type (extended boolean, really). */
2150	typedef uint8_t CPUMISAEXTCFG;
2151	/** Always disable the extension. */
2152	#define CPUMISAEXTCFG_DISABLED false
2153	/** Enable the extension if it's supported by the host CPU. */
2154	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2155	/** Enable the extension if it's supported by the host CPU, but don't let
2156	* the portable CPUID feature disable it. */
2157	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2158	/** Always enable the extension. */
2159	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2160	/** @} */
2161
2162	/**
2163	* CPUID Configuration (from CFGM).
2164	*
2165	* @remarks The members aren't document since we would only be duplicating the
2166	* \@cfgm entries in cpumR3CpuIdReadConfig.
2167	*/
2168	typedef struct CPUMCPUIDCONFIG
2169	{
2170	bool fNt4LeafLimit;
2171	bool fInvariantTsc;
2172
2173	CPUMISAEXTCFG enmCmpXchg16b;
2174	CPUMISAEXTCFG enmMonitor;
2175	CPUMISAEXTCFG enmMWaitExtensions;
2176	CPUMISAEXTCFG enmSse41;
2177	CPUMISAEXTCFG enmSse42;
2178	CPUMISAEXTCFG enmAvx;
2179	CPUMISAEXTCFG enmAvx2;
2180	CPUMISAEXTCFG enmXSave;
2181	CPUMISAEXTCFG enmAesNi;
2182	CPUMISAEXTCFG enmPClMul;
2183	CPUMISAEXTCFG enmPopCnt;
2184	CPUMISAEXTCFG enmMovBe;
2185	CPUMISAEXTCFG enmRdRand;
2186	CPUMISAEXTCFG enmRdSeed;
2187	CPUMISAEXTCFG enmCLFlushOpt;
2188
2189	CPUMISAEXTCFG enmAbm;
2190	CPUMISAEXTCFG enmSse4A;
2191	CPUMISAEXTCFG enmMisAlnSse;
2192	CPUMISAEXTCFG enm3dNowPrf;
2193	CPUMISAEXTCFG enmAmdExtMmx;
2194
2195	uint32_t uMaxStdLeaf;
2196	uint32_t uMaxExtLeaf;
2197	uint32_t uMaxCentaurLeaf;
2198	uint32_t uMaxIntelFamilyModelStep;
2199	char szCpuName[128];
2200	} CPUMCPUIDCONFIG;
2201	/** Pointer to CPUID config (from CFGM). */
2202	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2203
2204
2205	/**
2206	* Insert hypervisor identification leaves.
2207	*
2208	* We only return minimal information, primarily ensuring that the
2209	* 0x40000000 function returns 0x40000001 and identifying ourselves.
2210	* Hypervisor-specific interface is supported through GIM which will
2211	* modify these leaves if required depending on the GIM provider.
2212	*
2213	* @returns VBox status code.
2214	* @param pCpum The CPUM instance data.
2215	* @param pConfig The CPUID configuration we've read from CFGM.
2216	*/
2217	static int cpumR3CpuIdPlantHypervisorLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2218	{
2219	CPUMCPUIDLEAF NewLeaf;
2220	NewLeaf.uLeaf = UINT32_C(0x40000000);
2221	NewLeaf.uSubLeaf = 0;
2222	NewLeaf.fSubLeafMask = 0;
2223	NewLeaf.uEax = UINT32_C(0x40000001);
2224	NewLeaf.uEbx = 0x786f4256 /* 'VBox' */;
2225	NewLeaf.uEcx = 0x786f4256 /* 'VBox' */;
2226	NewLeaf.uEdx = 0x786f4256 /* 'VBox' */;
2227	NewLeaf.fFlags = 0;
2228	int rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
2229	AssertLogRelRCReturn(rc, rc);
2230
2231	NewLeaf.uLeaf = UINT32_C(0x40000001);
2232	NewLeaf.uEax = 0x656e6f6e; /* 'none' */
2233	NewLeaf.uEbx = 0;
2234	NewLeaf.uEcx = 0;
2235	NewLeaf.uEdx = 0;
2236	NewLeaf.fFlags = 0;
2237	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
2238	AssertLogRelRCReturn(rc, rc);
2239
2240	return VINF_SUCCESS;
2241	}
2242
2243
2244	/**
2245	* Mini CPU selection support for making Mac OS X happy.
2246	*
2247	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2248	*
2249	* @param pCpum The CPUM instance data.
2250	* @param pConfig The CPUID configuration we've read from CFGM.
2251	*/
2252	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2253	{
2254	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2255	{
2256	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2257	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2258	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2259	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2260	0);
2261	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2262	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2263	{
2264	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2265	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2266	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2267	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2268	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2269	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2270	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2271	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2272	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2273	pStdFeatureLeaf->uEax = uNew;
2274	}
2275	}
2276	}
2277
2278
2279
2280	/**
2281	* Limit it the number of entries, zapping the remainder.
2282	*
2283	* The limits are masking off stuff about power saving and similar, this
2284	* is perhaps a bit crudely done as there is probably some relatively harmless
2285	* info too in these leaves (like words about having a constant TSC).
2286	*
2287	* @param pCpum The CPUM instance data.
2288	* @param pConfig The CPUID configuration we've read from CFGM.
2289	*/
2290	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2291	{
2292	/*
2293	* Standard leaves.
2294	*/
2295	uint32_t uSubLeaf = 0;
2296	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2297	if (pCurLeaf)
2298	{
2299	uint32_t uLimit = pCurLeaf->uEax;
2300	if (uLimit <= UINT32_C(0x000fffff))
2301	{
2302	if (uLimit > pConfig->uMaxStdLeaf)
2303	{
2304	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2305	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2306	uLimit + 1, UINT32_C(0x000fffff));
2307	}
2308
2309	/* NT4 hack, no zapping of extra leaves here. */
2310	if (pConfig->fNt4LeafLimit && uLimit > 3)
2311	pCurLeaf->uEax = uLimit = 3;
2312
2313	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2314	pCurLeaf->uEax = uLimit;
2315	}
2316	else
2317	{
2318	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2319	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2320	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2321	}
2322	}
2323
2324	/*
2325	* Extended leaves.
2326	*/
2327	uSubLeaf = 0;
2328	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2329	if (pCurLeaf)
2330	{
2331	uint32_t uLimit = pCurLeaf->uEax;
2332	if ( uLimit >= UINT32_C(0x80000000)
2333	&& uLimit <= UINT32_C(0x800fffff))
2334	{
2335	if (uLimit > pConfig->uMaxExtLeaf)
2336	{
2337	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2338	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2339	uLimit + 1, UINT32_C(0x800fffff));
2340	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2341	pCurLeaf->uEax = uLimit;
2342	}
2343	}
2344	else
2345	{
2346	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2347	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2348	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2349	}
2350	}
2351
2352	/*
2353	* Centaur leaves (VIA).
2354	*/
2355	uSubLeaf = 0;
2356	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2357	if (pCurLeaf)
2358	{
2359	uint32_t uLimit = pCurLeaf->uEax;
2360	if ( uLimit >= UINT32_C(0xc0000000)
2361	&& uLimit <= UINT32_C(0xc00fffff))
2362	{
2363	if (uLimit > pConfig->uMaxCentaurLeaf)
2364	{
2365	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2366	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2367	uLimit + 1, UINT32_C(0xcfffffff));
2368	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2369	pCurLeaf->uEax = uLimit;
2370	}
2371	}
2372	else
2373	{
2374	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2375	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2376	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2377	}
2378	}
2379	}
2380
2381
2382	/**
2383	* Clears a CPUID leaf and all sub-leaves (to zero).
2384	*
2385	* @param pCpum The CPUM instance data.
2386	* @param uLeaf The leaf to clear.
2387	*/
2388	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2389	{
2390	uint32_t uSubLeaf = 0;
2391	PCPUMCPUIDLEAF pCurLeaf;
2392	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2393	{
2394	pCurLeaf->uEax = 0;
2395	pCurLeaf->uEbx = 0;
2396	pCurLeaf->uEcx = 0;
2397	pCurLeaf->uEdx = 0;
2398	uSubLeaf++;
2399	}
2400	}
2401
2402
2403	/**
2404	* Sanitizes and adjust the CPUID leaves.
2405	*
2406	* Drop features that aren't virtualized (or virtualizable). Adjust information
2407	* and capabilities to fit the virtualized hardware. Remove information the
2408	* guest shouldn't have (because it's wrong in the virtual world or because it
2409	* gives away host details) or that we don't have documentation for and no idea
2410	* what means.
2411	*
2412	* @returns VBox status code.
2413	* @param pVM Pointer to the cross context VM structure (for cCpus).
2414	* @param pCpum The CPUM instance data.
2415	* @param pConfig The CPUID configuration we've read from CFGM.
2416	*/
2417	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2418	{
2419	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2420	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2421	{ \
2422	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2423	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2424	}
2425	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2426	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2427	{ \
2428	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2429	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2430	}
2431	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2432	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2433	&& ((a_pLeafReg) & (fBitMask)) \
2434	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2435	{ \
2436	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2437	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2438	}
2439	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2440
2441	/* Cpuid 1:
2442	* EAX: CPU model, family and stepping.
2443	*
2444	* ECX + EDX: Supported features. Only report features we can support.
2445	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2446	* options may require adjusting (i.e. stripping what was enabled).
2447	*
2448	* EBX: Branding, CLFLUSH line size, logical processors per package and
2449	* initial APIC ID.
2450	*/
2451	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2452	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2453	AssertLogRelReturn(pStdFeatureLeaf->fSubLeafMask == 0, VERR_CPUM_IPE_2);
2454
2455	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2456	\| X86_CPUID_FEATURE_EDX_VME
2457	\| X86_CPUID_FEATURE_EDX_DE
2458	\| X86_CPUID_FEATURE_EDX_PSE
2459	\| X86_CPUID_FEATURE_EDX_TSC
2460	\| X86_CPUID_FEATURE_EDX_MSR
2461	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2462	\| X86_CPUID_FEATURE_EDX_MCE
2463	\| X86_CPUID_FEATURE_EDX_CX8
2464	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2465	//\| RT_BIT_32(10) - not defined
2466	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2467	//\| X86_CPUID_FEATURE_EDX_SEP
2468	\| X86_CPUID_FEATURE_EDX_MTRR
2469	\| X86_CPUID_FEATURE_EDX_PGE
2470	\| X86_CPUID_FEATURE_EDX_MCA
2471	\| X86_CPUID_FEATURE_EDX_CMOV
2472	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2473	\| X86_CPUID_FEATURE_EDX_PSE36
2474	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2475	\| X86_CPUID_FEATURE_EDX_CLFSH
2476	//\| RT_BIT_32(20) - not defined
2477	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2478	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2479	\| X86_CPUID_FEATURE_EDX_MMX
2480	\| X86_CPUID_FEATURE_EDX_FXSR
2481	\| X86_CPUID_FEATURE_EDX_SSE
2482	\| X86_CPUID_FEATURE_EDX_SSE2
2483	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2484	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading/cores - see below.
2485	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2486	//\| RT_BIT_32(30) - not defined
2487	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2488	;
2489	pStdFeatureLeaf->uEcx &= 0
2490	\| X86_CPUID_FEATURE_ECX_SSE3
2491	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2492	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2493	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2494	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2495	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2496	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized yet.
2497	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2498	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2499	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2500	\| X86_CPUID_FEATURE_ECX_SSSE3
2501	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2502	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2503	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2504	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2505	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2506	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2507	//\| X86_CPUID_FEATURE_ECX_PCID - not implemented yet.
2508	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2509	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2510	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2511	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2512	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2513	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2514	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2515	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2516	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2517	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2518	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2519	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2520	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2521	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2522	;
2523
2524	if (pCpum->u8PortableCpuIdLevel > 0)
2525	{
2526	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2527	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2528	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2529	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2530	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2531	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2532	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2533	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2534	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2535	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2536	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2537	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2538	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2539	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2540	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2541	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2542	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2543	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2544
2545	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2546	\| X86_CPUID_FEATURE_EDX_PSN
2547	\| X86_CPUID_FEATURE_EDX_DS
2548	\| X86_CPUID_FEATURE_EDX_ACPI
2549	\| X86_CPUID_FEATURE_EDX_SS
2550	\| X86_CPUID_FEATURE_EDX_TM
2551	\| X86_CPUID_FEATURE_EDX_PBE
2552	)));
2553	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2554	\| X86_CPUID_FEATURE_ECX_CPLDS
2555	\| X86_CPUID_FEATURE_ECX_VMX
2556	\| X86_CPUID_FEATURE_ECX_SMX
2557	\| X86_CPUID_FEATURE_ECX_EST
2558	\| X86_CPUID_FEATURE_ECX_TM2
2559	\| X86_CPUID_FEATURE_ECX_CNTXID
2560	\| X86_CPUID_FEATURE_ECX_FMA
2561	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2562	\| X86_CPUID_FEATURE_ECX_PDCM
2563	\| X86_CPUID_FEATURE_ECX_DCA
2564	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2565	)));
2566	}
2567
2568	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2569	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2570	#ifdef VBOX_WITH_MULTI_CORE
2571	if (pVM->cCpus > 1)
2572	{
2573	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2574	core times the number of CPU cores per processor */
2575	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2576	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
2577	}
2578	#endif
2579
2580	/* Force standard feature bits. */
2581	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2582	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2583	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2584	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2585	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2586	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2587	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2588	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2589	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2590	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2591	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2592	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2593	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2594	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2595	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2596	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2597	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2598	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2599	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2600	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2601	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2602	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2603
2604	pStdFeatureLeaf = NULL; /* Must refetch! */
2605
2606	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2607	* AMD:
2608	* EAX: CPU model, family and stepping.
2609	*
2610	* ECX + EDX: Supported features. Only report features we can support.
2611	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2612	* options may require adjusting (i.e. stripping what was enabled).
2613	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2614	*
2615	* EBX: Branding ID and package type (or reserved).
2616	*
2617	* Intel and probably most others:
2618	* EAX: 0
2619	* EBX: 0
2620	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2621	*/
2622	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2623	if (pExtFeatureLeaf)
2624	{
2625	AssertLogRelReturn(pExtFeatureLeaf->fSubLeafMask == 0, VERR_CPUM_IPE_2);
2626
2627	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2628	\| X86_CPUID_AMD_FEATURE_EDX_VME
2629	\| X86_CPUID_AMD_FEATURE_EDX_DE
2630	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2631	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2632	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2633	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2634	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2635	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2636	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2637	//\| RT_BIT_32(10) - reserved
2638	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2639	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2640	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2641	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2642	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2643	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2644	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2645	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2646	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2647	//\| RT_BIT_32(18) - reserved
2648	//\| RT_BIT_32(19) - reserved
2649	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2650	//\| RT_BIT_32(21) - reserved
2651	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2652	\| X86_CPUID_AMD_FEATURE_EDX_MMX
2653	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
2654	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
2655	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2656	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2657	//\| RT_BIT_32(28) - reserved
2658	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2659	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2660	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
2661	;
2662	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2663	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2664	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
2665	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2666	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
2667	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2668	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2669	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2670	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2671	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2672	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2673	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
2674	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
2675	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2676	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
2677	//\| RT_BIT_32(14) - reserved
2678	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2679	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2680	//\| RT_BIT_32(17) - reserved
2681	//\| RT_BIT_32(18) - reserved
2682	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2683	//\| RT_BIT_32(20) - reserved
2684	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2685	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2686	//\| RT_BIT_32(23) - reserved
2687	//\| RT_BIT_32(24) - reserved
2688	//\| RT_BIT_32(25) - reserved
2689	//\| RT_BIT_32(26) - reserved
2690	//\| RT_BIT_32(27) - reserved
2691	//\| RT_BIT_32(28) - reserved
2692	//\| RT_BIT_32(29) - reserved
2693	//\| RT_BIT_32(30) - reserved
2694	//\| RT_BIT_32(31) - reserved
2695	;
2696	#ifdef VBOX_WITH_MULTI_CORE
2697	if ( pVM->cCpus > 1
2698	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2699	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2700	#endif
2701
2702	if (pCpum->u8PortableCpuIdLevel > 0)
2703	{
2704	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2705	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2706	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2707	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2708	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2709	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2710	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2711	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2712	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2713	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2714	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2715	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2716	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2717	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2718	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2719
2720	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2721	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2722	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2723	\| X86_CPUID_AMD_FEATURE_ECX_IBS
2724	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2725	\| X86_CPUID_AMD_FEATURE_ECX_WDT
2726	\| X86_CPUID_AMD_FEATURE_ECX_LWP
2727	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
2728	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2729	\| UINT32_C(0xff964000)
2730	)));
2731	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2732	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2733	\| RT_BIT(18)
2734	\| RT_BIT(19)
2735	\| RT_BIT(21)
2736	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2737	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2738	\| RT_BIT(28)
2739	)));
2740	}
2741
2742	/* Force extended feature bits. */
2743	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2744	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
2745	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2746	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2747	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2748	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2749	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2750	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2751	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2752	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2753	}
2754	pExtFeatureLeaf = NULL; /* Must refetch! */
2755
2756
2757	/* Cpuid 2:
2758	* Intel: (Nondeterministic) Cache and TLB information
2759	* AMD: Reserved
2760	* VIA: Reserved
2761	* Safe to expose. Restrict the number of calls to 1 since we don't
2762	* implement this kind of subleaves (is there hardware that does??).
2763	*/
2764	uint32_t uSubLeaf = 0;
2765	PCPUMCPUIDLEAF pCurLeaf;
2766	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2767	{
2768	if ((pCurLeaf->uEax & 0xff) > 1)
2769	{
2770	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2771	pCurLeaf->uEax &= UINT32_C(0xffffff01);
2772	}
2773	uSubLeaf++;
2774	}
2775
2776	/* Cpuid 3:
2777	* Intel: EAX, EBX - reserved (transmeta uses these)
2778	* ECX, EDX - Processor Serial Number if available, otherwise reserved
2779	* AMD: Reserved
2780	* VIA: Reserved
2781	* Safe to expose
2782	*/
2783	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2784	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
2785	{
2786	uSubLeaf = 0;
2787	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
2788	{
2789	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2790	if (pCpum->u8PortableCpuIdLevel > 0)
2791	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2792	uSubLeaf++;
2793	}
2794	}
2795
2796	/* Cpuid 4 + ECX:
2797	* Intel: Deterministic Cache Parameters Leaf.
2798	* AMD: Reserved
2799	* VIA: Reserved
2800	* Safe to expose, except for EAX:
2801	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
2802	* Bits 31-26: Maximum number of processor cores in this physical package**
2803	* Note: These SMP values are constant regardless of ECX
2804	*/
2805	uSubLeaf = 0;
2806	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
2807	{
2808	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
2809	#ifdef VBOX_WITH_MULTI_CORE
2810	if ( pVM->cCpus > 1
2811	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2812	{
2813	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
2814	/* One logical processor with possibly multiple cores. */
2815	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
2816	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
2817	}
2818	#endif
2819	uSubLeaf++;
2820	}
2821
2822	/* Cpuid 5: Monitor/mwait Leaf
2823	* Intel: ECX, EDX - reserved
2824	* EAX, EBX - Smallest and largest monitor line size
2825	* AMD: EDX - reserved
2826	* EAX, EBX - Smallest and largest monitor line size
2827	* ECX - extensions (ignored for now)
2828	* VIA: Reserved
2829	* Safe to expose
2830	*/
2831	uSubLeaf = 0;
2832	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
2833	{
2834	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2835	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
2836	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2837
2838	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2839	if (pConfig->enmMWaitExtensions)
2840	{
2841	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
2842	/** @todo: for now we just expose host's MWAIT C-states, although conceptually
2843	it shall be part of our power management virtualization model */
2844	#if 0
2845	/* MWAIT sub C-states */
2846	pCurLeaf->uEdx =
2847	(0 << 0) /* 0 in C0 */ \|
2848	(2 << 4) /* 2 in C1 */ \|
2849	(2 << 8) /* 2 in C2 */ \|
2850	(2 << 12) /* 2 in C3 */ \|
2851	(0 << 16) /* 0 in C4 */
2852	;
2853	#endif
2854	}
2855	else
2856	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2857	uSubLeaf++;
2858	}
2859
2860	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
2861	* Intel: Various stuff.
2862	* AMD: EAX, EBX, EDX - reserved.
2863	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
2864	* present. Same as intel.
2865	* VIA: ??
2866	*
2867	* We clear everything here for now.
2868	*/
2869	cpumR3CpuIdZeroLeaf(pCpum, 6);
2870
2871	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
2872	* EAX: Number of sub leaves.
2873	* EBX+ECX+EDX: Feature flags
2874	*
2875	* We only have documentation for one sub-leaf, so clear all other (no need
2876	* to remove them as such, just set them to zero).
2877	*
2878	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2879	* options may require adjusting (i.e. stripping what was enabled).
2880	*/
2881	uSubLeaf = 0;
2882	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
2883	{
2884	switch (uSubLeaf)
2885	{
2886	case 0:
2887	{
2888	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
2889	pCurLeaf->uEbx &= 0
2890	//\| X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
2891	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
2892	//\| RT_BIT(2) - reserved
2893	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
2894	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
2895	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
2896	//\| RT_BIT(6) - reserved
2897	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
2898	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
2899	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
2900	//\| X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
2901	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
2902	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
2903	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
2904	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
2905	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
2906	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
2907	//\| RT_BIT(17) - reserved
2908	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
2909	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
2910	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
2911	//\| RT_BIT(21) - reserved
2912	//\| RT_BIT(22) - reserved
2913	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
2914	//\| RT_BIT(24) - reserved
2915	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
2916	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
2917	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
2918	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
2919	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
2920	//\| RT_BIT(30) - reserved
2921	//\| RT_BIT(31) - reserved
2922	;
2923	pCurLeaf->uEcx &= 0
2924	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
2925	;
2926	pCurLeaf->uEdx &= 0;
2927
2928	if (pCpum->u8PortableCpuIdLevel > 0)
2929	{
2930	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
2931	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
2932	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
2933	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
2934	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
2935	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
2936	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
2937	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
2938	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
2939	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
2940	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
2941	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
2942	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
2943	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
2944	}
2945
2946	/* Force standard feature bits. */
2947	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2948	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
2949	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
2950	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
2951	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2952	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
2953	break;
2954	}
2955
2956	default:
2957	/* Invalid index, all values are zero. */
2958	pCurLeaf->uEax = 0;
2959	pCurLeaf->uEbx = 0;
2960	pCurLeaf->uEcx = 0;
2961	pCurLeaf->uEdx = 0;
2962	break;
2963	}
2964	uSubLeaf++;
2965	}
2966
2967	/* Cpuid 8: Marked as reserved by Intel and AMD.
2968	* We zero this since we don't know what it may have been used for.
2969	*/
2970	cpumR3CpuIdZeroLeaf(pCpum, 8);
2971
2972	/* Cpuid 9: Direct Cache Access (DCA) Parameters
2973	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
2974	* EBX, ECX, EDX - reserved.
2975	* AMD: Reserved
2976	* VIA: ??
2977	*
2978	* We zero this.
2979	*/
2980	cpumR3CpuIdZeroLeaf(pCpum, 9);
2981
2982	/* Cpuid 0xa: Architectural Performance Monitor Features
2983	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
2984	* EBX, ECX, EDX - reserved.
2985	* AMD: Reserved
2986	* VIA: ??
2987	*
2988	* We zero this, for now at least.
2989	*/
2990	cpumR3CpuIdZeroLeaf(pCpum, 10);
2991
2992	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
2993	* Intel: EAX - APCI ID shift right for next level.
2994	* EBX - Factory configured cores/threads at this level.
2995	* ECX - Level number (same as input) and level type (1,2,0).
2996	* EDX - Extended initial APIC ID.
2997	* AMD: Reserved
2998	* VIA: ??
2999	*/
3000	uSubLeaf = 0;
3001	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3002	{
3003	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3004	{
3005	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3006	if (bLevelType == 1)
3007	{
3008	/* Thread level - we don't do threads at the moment. */
3009	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3010	pCurLeaf->uEbx = 1;
3011	}
3012	else if (bLevelType == 2)
3013	{
3014	/* Core level. */
3015	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3016	#ifdef VBOX_WITH_MULTI_CORE
3017	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3018	pCurLeaf->uEax++;
3019	#endif
3020	pCurLeaf->uEbx = pVM->cCpus;
3021	}
3022	else
3023	{
3024	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3025	pCurLeaf->uEax = 0;
3026	pCurLeaf->uEbx = 0;
3027	pCurLeaf->uEcx = 0;
3028	}
3029	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3030	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3031	}
3032	else
3033	{
3034	pCurLeaf->uEax = 0;
3035	pCurLeaf->uEbx = 0;
3036	pCurLeaf->uEcx = 0;
3037	pCurLeaf->uEdx = 0;
3038	}
3039	uSubLeaf++;
3040	}
3041
3042	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3043	* We zero this since we don't know what it may have been used for.
3044	*/
3045	cpumR3CpuIdZeroLeaf(pCpum, 12);
3046
3047	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3048	* ECX=0: EAX - Valid bits in XCR0[31:0].
3049	* EBX - Maximum state size as per current XCR0 value.
3050	* ECX - Maximum state size for all supported features.
3051	* EDX - Valid bits in XCR0[63:32].
3052	* ECX=1: EAX - Various X-features.
3053	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3054	* ECX - Valid bits in IA32_XSS[31:0].
3055	* EDX - Valid bits in IA32_XSS[63:32].
3056	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3057	* if the bit invalid all four registers are set to zero.
3058	* EAX - The state size for this feature.
3059	* EBX - The state byte offset of this feature.
3060	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3061	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3062	*
3063	* Clear them all as we don't currently implement extended CPU state.
3064	*/
3065	/* Figure out the supported XCR0/XSS mask component. */
3066	uint64_t fGuestXcr0Mask = 0;
3067	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3068	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3069	{
3070	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3071	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3072	fGuestXcr0Mask \|= XSAVE_C_YMM;
3073	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3074	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3075	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3076	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3077	}
3078	pStdFeatureLeaf = NULL;
3079	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3080
3081	/* Work the sub-leaves. */
3082	uint32_t cbXSaveMax = sizeof(X86FXSTATE);
3083	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3084	{
3085	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3086	if (pCurLeaf)
3087	{
3088	if (fGuestXcr0Mask)
3089	{
3090	switch (uSubLeaf)
3091	{
3092	case 0:
3093	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3094	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3095	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3096	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3097	VERR_CPUM_IPE_1);
3098	cbXSaveMax = pCurLeaf->uEcx;
3099	AssertLogRelMsgReturn(cbXSaveMax <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMax >= CPUM_MIN_XSAVE_AREA_SIZE,
3100	("%#x max=%#x\n", cbXSaveMax, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3101	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMax,
3102	("ebx=%#x cbXSaveMax=%#x\n", pCurLeaf->uEbx, cbXSaveMax),
3103	VERR_CPUM_IPE_2);
3104	continue;
3105	case 1:
3106	pCurLeaf->uEax &= 0;
3107	pCurLeaf->uEcx &= 0;
3108	pCurLeaf->uEdx &= 0;
3109	/** @todo what about checking ebx? */
3110	continue;
3111	default:
3112	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3113	{
3114	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMax
3115	&& pCurLeaf->uEax > 0
3116	&& pCurLeaf->uEbx < cbXSaveMax
3117	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3118	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMax,
3119	("%#x: eax=%#x ebx=%#x cbMax=%#x\n", pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMax),
3120	VERR_CPUM_IPE_2);
3121	AssertLogRel(!(pCurLeaf->uEcx & 1));
3122	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3123	pCurLeaf->uEdx = 0; /* it's reserved... */
3124	continue;
3125	}
3126	break;
3127	}
3128	}
3129
3130	/* Clear the leaf. */
3131	pCurLeaf->uEax = 0;
3132	pCurLeaf->uEbx = 0;
3133	pCurLeaf->uEcx = 0;
3134	pCurLeaf->uEdx = 0;
3135	}
3136	}
3137
3138	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3139	* We zero this since we don't know what it may have been used for.
3140	*/
3141	cpumR3CpuIdZeroLeaf(pCpum, 14);
3142
3143	/* Cpuid 0xf + ECX: Platform qualifity of service monitoring (PQM).
3144	* We zero this as we don't currently virtualize PQM.
3145	*/
3146	cpumR3CpuIdZeroLeaf(pCpum, 15);
3147
3148	/* Cpuid 0x10 + ECX: Platform qualifity of service enforcement (PQE).
3149	* We zero this as we don't currently virtualize PQE.
3150	*/
3151	cpumR3CpuIdZeroLeaf(pCpum, 16);
3152
3153	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3154	* We zero this since we don't know what it may have been used for.
3155	*/
3156	cpumR3CpuIdZeroLeaf(pCpum, 17);
3157
3158	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3159	* We zero this as we don't currently virtualize this.
3160	*/
3161	cpumR3CpuIdZeroLeaf(pCpum, 18);
3162
3163	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3164	* We zero this since we don't know what it may have been used for.
3165	*/
3166	cpumR3CpuIdZeroLeaf(pCpum, 19);
3167
3168	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3169	* We zero this as we don't currently virtualize this.
3170	*/
3171	cpumR3CpuIdZeroLeaf(pCpum, 20);
3172
3173	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3174	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3175	* EAX - denominator (unsigned).
3176	* EBX - numerator (unsigned).
3177	* ECX, EDX - reserved.
3178	* AMD: Reserved / undefined / not implemented.
3179	* VIA: Reserved / undefined / not implemented.
3180	* We zero this as we don't currently virtualize this.
3181	*/
3182	cpumR3CpuIdZeroLeaf(pCpum, 21);
3183
3184	/* Cpuid 0x16: Processor frequency info
3185	* Intel: EAX - Core base frequency in MHz.
3186	* EBX - Core maximum frequency in MHz.
3187	* ECX - Bus (reference) frequency in MHz.
3188	* EDX - Reserved.
3189	* AMD: Reserved / undefined / not implemented.
3190	* VIA: Reserved / undefined / not implemented.
3191	* We zero this as we don't currently virtualize this.
3192	*/
3193	cpumR3CpuIdZeroLeaf(pCpum, 22);
3194
3195	/* Cpuid 0x17..0x10000000: Unknown.
3196	* We don't know these and what they mean, so remove them. */
3197	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3198	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3199
3200
3201	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3202	* We remove all these as we're a hypervisor and must provide our own.
3203	*/
3204	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3205	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3206
3207
3208	/* Cpuid 0x80000000 is harmless. */
3209
3210	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3211
3212	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3213
3214	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3215	* Safe to pass on to the guest.
3216	*
3217	* AMD: 0x800000005 L1 cache information
3218	* 0x800000006 L2/L3 cache information
3219	* Intel: 0x800000005 reserved
3220	* 0x800000006 L2 cache information
3221	* VIA: 0x800000005 TLB and L1 cache information
3222	* 0x800000006 L2 cache information
3223	*/
3224
3225	/* Cpuid 0x800000007: Advanced Power Management Information.
3226	* AMD: EAX: Processor feedback capabilities.
3227	* EBX: RAS capabilites.
3228	* ECX: Advanced power monitoring interface.
3229	* EDX: Enhanced power management capabilities.
3230	* Intel: EAX, EBX, ECX - reserved.
3231	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3232	* VIA: Reserved
3233	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3234	*/
3235	uSubLeaf = 0;
3236	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3237	{
3238	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3239	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3240	{
3241	pCurLeaf->uEdx &= 0
3242	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3243	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3244	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3245	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3246	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3247	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3248	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3249	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3250	#if 0 /*
3251	* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
3252	* Linux kernels blindly assume that the AMD performance counters work
3253	* if this is set for 64 bits guests. (Can't really find a CPUID feature
3254	* bit for them though.)
3255	*/
3256	/** @todo need to recheck this with new MSR emulation. */
3257	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3258	#endif
3259	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3260	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3261	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3262	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3263	\| 0;
3264	}
3265	else
3266	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3267	if (pConfig->fInvariantTsc)
3268	pCurLeaf->uEdx \|= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3269	uSubLeaf++;
3270	}
3271
3272	/* Cpuid 0x80000008:
3273	* AMD: EBX, EDX - reserved
3274	* EAX: Virtual/Physical/Guest address Size
3275	* ECX: Number of cores + APICIdCoreIdSize
3276	* Intel: EAX: Virtual/Physical address Size
3277	* EBX, ECX, EDX - reserved
3278	* VIA: EAX: Virtual/Physical address Size
3279	* EBX, ECX, EDX - reserved
3280	*
3281	* We only expose the virtual+pysical address size to the guest atm.
3282	* On AMD we set the core count, but not the apic id stuff as we're
3283	* currently not doing the apic id assignments in a complatible manner.
3284	*/
3285	uSubLeaf = 0;
3286	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3287	{
3288	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3289	pCurLeaf->uEbx = 0; /* reserved */
3290	pCurLeaf->uEdx = 0; /* reserved */
3291
3292	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3293	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3294	pCurLeaf->uEcx = 0;
3295	#ifdef VBOX_WITH_MULTI_CORE
3296	if ( pVM->cCpus > 1
3297	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3298	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3299	#endif
3300	uSubLeaf++;
3301	}
3302
3303	/* Cpuid 0x80000009: Reserved
3304	* We zero this since we don't know what it may have been used for.
3305	*/
3306	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3307
3308	/* Cpuid 0x8000000a: SVM Information
3309	* AMD: EAX - SVM revision.
3310	* EBX - Number of ASIDs.
3311	* ECX - Reserved.
3312	* EDX - SVM Feature identification.
3313	* We clear all as we currently does not virtualize SVM.
3314	*/
3315	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3316
3317	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3318	* We clear these as we don't know what purpose they might have. */
3319	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3320	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3321
3322	/* Cpuid 0x80000019: TLB configuration
3323	* Seems to be harmless, pass them thru as is. */
3324
3325	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3326	* Strip anything we don't know what is or addresses feature we don't implement. */
3327	uSubLeaf = 0;
3328	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3329	{
3330	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3331	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3332	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3333	;
3334	pCurLeaf->uEbx = 0; /* reserved */
3335	pCurLeaf->uEcx = 0; /* reserved */
3336	pCurLeaf->uEdx = 0; /* reserved */
3337	uSubLeaf++;
3338	}
3339
3340	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3341	* Clear this as we don't currently virtualize this feature. */
3342	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3343
3344	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3345	* Clear this as we don't currently virtualize this feature. */
3346	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3347
3348	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3349	* We need to sanitize the cores per cache (EAX[25:14]).
3350	*
3351	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3352	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3353	* slightly different meaning.
3354	*/
3355	uSubLeaf = 0;
3356	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3357	{
3358	#ifdef VBOX_WITH_MULTI_CORE
3359	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3360	if (cCores > pVM->cCpus)
3361	cCores = pVM->cCpus;
3362	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3363	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3364	#else
3365	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3366	#endif
3367	uSubLeaf++;
3368	}
3369
3370	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3371	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3372	* setup, we have one compute unit with all the cores in it. Single node.
3373	*/
3374	uSubLeaf = 0;
3375	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3376	{
3377	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3378	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3379	{
3380	#ifdef VBOX_WITH_MULTI_CORE
3381	pCurLeaf->uEbx = pVM->cCpus < 0x100
3382	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3383	#else
3384	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3385	#endif
3386	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3387	}
3388	else
3389	{
3390	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3391	pCurLeaf->uEbx = 0; /* Reserved. */
3392	pCurLeaf->uEcx = 0; /* Reserved. */
3393	}
3394	pCurLeaf->uEdx = 0; /* Reserved. */
3395	uSubLeaf++;
3396	}
3397
3398	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3399	* We don't know these and what they mean, so remove them. */
3400	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3401	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3402
3403	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3404	* Just pass it thru for now. */
3405
3406	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3407	* Just pass it thru for now. */
3408
3409	/* Cpuid 0xc0000000: Centaur stuff.
3410	* Harmless, pass it thru. */
3411
3412	/* Cpuid 0xc0000001: Centaur features.
3413	* VIA: EAX - Family, model, stepping.
3414	* EDX - Centaur extended feature flags. Nothing interesting, except may
3415	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3416	* EBX, ECX - reserved.
3417	* We keep EAX but strips the rest.
3418	*/
3419	uSubLeaf = 0;
3420	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3421	{
3422	pCurLeaf->uEbx = 0;
3423	pCurLeaf->uEcx = 0;
3424	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3425	uSubLeaf++;
3426	}
3427
3428	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3429	* We only have fixed stale values, but should be harmless. */
3430
3431	/* Cpuid 0xc0000003: Reserved.
3432	* We zero this since we don't know what it may have been used for.
3433	*/
3434	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3435
3436	/* Cpuid 0xc0000004: Centaur Performance Info.
3437	* We only have fixed stale values, but should be harmless. */
3438
3439
3440	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3441	* We don't know these and what they mean, so remove them. */
3442	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3443	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3444
3445	return VINF_SUCCESS;
3446	#undef PORTABLE_DISABLE_FEATURE_BIT
3447	#undef PORTABLE_CLEAR_BITS_WHEN
3448	}
3449
3450
3451	/**
3452	* Reads a value in /CPUM/IsaExts/ node.
3453	*
3454	* @returns VBox status code (error message raised).
3455	* @param pVM The VM handle (for errors).
3456	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3457	* @param pszValueName The value / extension name.
3458	* @param penmValue Where to return the choice.
3459	* @param enmDefault The default choice.
3460	*/
3461	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3462	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3463	{
3464	/*
3465	* Try integer encoding first.
3466	*/
3467	uint64_t uValue;
3468	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3469	if (RT_SUCCESS(rc))
3470	switch (uValue)
3471	{
3472	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3473	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3474	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3475	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3476	default:
3477	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3478	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3479	pszValueName, uValue);
3480	}
3481	/*
3482	* If missing, use default.
3483	*/
3484	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3485	*penmValue = enmDefault;
3486	else
3487	{
3488	if (rc == VERR_CFGM_NOT_INTEGER)
3489	{
3490	/*
3491	* Not an integer, try read it as a string.
3492	*/
3493	char szValue[32];
3494	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3495	if (RT_SUCCESS(rc))
3496	{
3497	RTStrToLower(szValue);
3498	size_t cchValue = strlen(szValue);
3499	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3500	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3501	*penmValue = CPUMISAEXTCFG_DISABLED;
3502	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3503	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3504	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3505	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3506	else if (EQ("portable"))
3507	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3508	else if (EQ("default") \|\| EQ("def"))
3509	*penmValue = enmDefault;
3510	else
3511	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3512	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3513	pszValueName, uValue);
3514	#undef EQ
3515	}
3516	}
3517	if (RT_FAILURE(rc))
3518	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3519	}
3520	return VINF_SUCCESS;
3521	}
3522
3523
3524	/**
3525	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3526	*
3527	* @returns VBox status code (error message raised).
3528	* @param pVM The VM handle (for errors).
3529	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3530	* @param pszValueName The value / extension name.
3531	* @param penmValue Where to return the choice.
3532	* @param enmDefault The default choice.
3533	* @param fAllowed Allowed choice. Applied both to the result and to
3534	* the default value.
3535	*/
3536	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3537	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3538	{
3539	int rc;
3540	if (fAllowed)
3541	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3542	else
3543	{
3544	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3545	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3546	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3547	*penmValue = CPUMISAEXTCFG_DISABLED;
3548	}
3549	return rc;
3550	}
3551
3552
3553	/**
3554	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3555	*
3556	* @returns VBox status code (error message raised).
3557	* @param pVM The VM handle (for errors).
3558	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3559	* @param pCpumCfg The /CPUM node (can be NULL).
3560	* @param pszValueName The value / extension name.
3561	* @param penmValue Where to return the choice.
3562	* @param enmDefault The default choice.
3563	*/
3564	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3565	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3566	{
3567	if (CFGMR3Exists(pCpumCfg, pszValueName))
3568	{
3569	if (!CFGMR3Exists(pIsaExts, pszValueName))
3570	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3571	else
3572	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3573	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3574	pszValueName, pszValueName);
3575
3576	bool fLegacy;
3577	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3578	if (RT_SUCCESS(rc))
3579	{
3580	*penmValue = fLegacy;
3581	return VINF_SUCCESS;
3582	}
3583	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3584	}
3585
3586	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3587	}
3588
3589
3590	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3591	{
3592	int rc;
3593
3594	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3595	* When non-zero CPUID features that could cause portability issues will be
3596	* stripped. The higher the value the more features gets stripped. Higher
3597	* values should only be used when older CPUs are involved since it may
3598	* harm performance and maybe also cause problems with specific guests. */
3599	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
3600	AssertLogRelRCReturn(rc, rc);
3601
3602	/** @cfgm{/CPUM/GuestCpuName, string}
3603	* The name of the CPU we're to emulate. The default is the host CPU.
3604	* Note! CPUs other than "host" one is currently unsupported. */
3605	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3606	AssertLogRelRCReturn(rc, rc);
3607
3608	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3609	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3610	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3611	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3612	*/
3613	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3614	AssertLogRelRCReturn(rc, rc);
3615
3616	/** @cfgm{/CPUM/InvariantTsc, boolean, complicated}
3617	* Set the invariant TSC flag in 0x80000007 if true, otherwas take default
3618	* action. By default the flag is passed thru as is from the host CPU, except
3619	* on AMD CPUs where it's suppressed to avoid trouble from linux assuming we
3620	* virtualize performance counters.
3621	*/
3622	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, false);
3623	AssertLogRelRCReturn(rc, rc);
3624
3625	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3626	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
3627	* probably going to be a temporary hack, so don't depend on this.
3628	* The 1st byte of the value is the stepping, the 2nd byte value is the model
3629	* number and the 3rd byte value is the family, and the 4th value must be zero.
3630	*/
3631	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3632	AssertLogRelRCReturn(rc, rc);
3633
3634	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3635	* The last standard leaf to keep. The actual last value that is stored in EAX
3636	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3637	* removed. (This works independently of and differently from NT4LeafLimit.)
3638	* The default is usually set to what we're able to reasonably sanitize.
3639	*/
3640	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3641	AssertLogRelRCReturn(rc, rc);
3642
3643	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3644	* The last extended leaf to keep. The actual last value that is stored in EAX
3645	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3646	* leaf are removed. The default is set to what we're able to sanitize.
3647	*/
3648	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3649	AssertLogRelRCReturn(rc, rc);
3650
3651	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3652	* The last extended leaf to keep. The actual last value that is stored in EAX
3653	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3654	* leaf are removed. The default is set to what we're able to sanitize.
3655	*/
3656	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3657	AssertLogRelRCReturn(rc, rc);
3658
3659
3660	/*
3661	* Instruction Set Architecture (ISA) Extensions.
3662	*/
3663	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3664	if (pIsaExts)
3665	{
3666	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3667	"CMPXCHG16B"
3668	"\|MONITOR"
3669	"\|MWaitExtensions"
3670	"\|SSE4.1"
3671	"\|SSE4.2"
3672	"\|AESNI"
3673	"\|PCLMUL"
3674	"\|POPCNT"
3675	"\|MOVBE"
3676	"\|RDRAND"
3677	"\|RDSEED"
3678	"\|CLFLUSHOPT"
3679	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
3680	if (RT_FAILURE(rc))
3681	return rc;
3682	}
3683
3684	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
3685	* Expose CMPXCHG16B to the guest if supported by the host. For the time
3686	* being the default is to only do this for VMs with nested paging and AMD-V or
3687	* unrestricted guest mode.
3688	*/
3689	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
3690	AssertLogRelRCReturn(rc, rc);
3691
3692	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
3693	* Expose MONITOR/MWAIT instructions to the guest.
3694	*/
3695	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
3696	AssertLogRelRCReturn(rc, rc);
3697
3698	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
3699	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
3700	* break on interrupt feature (bit 1).
3701	*/
3702	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
3703	AssertLogRelRCReturn(rc, rc);
3704
3705	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
3706	* Expose SSE4.1 to the guest if available.
3707	*/
3708	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
3709	AssertLogRelRCReturn(rc, rc);
3710
3711	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
3712	* Expose SSE4.2 to the guest if available.
3713	*/
3714	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
3715	AssertLogRelRCReturn(rc, rc);
3716
3717	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
3718	&& pVM->cpum.s.HostFeatures.fXSaveRstor
3719	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor;
3720
3721	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
3722	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
3723	* default is to only expose this to VMs with nested paging and AMD-V or
3724	* unrestricted guest execution mode. Not possible to force this one without
3725	* host support at the moment.
3726	*/
3727	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
3728	fMayHaveXSave /fAllowed/);
3729	AssertLogRelRCReturn(rc, rc);
3730
3731	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
3732	* Expose the AVX instruction set extensions to the guest if available and
3733	* XSAVE is exposed too. For the time being the default is to only expose this
3734	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3735	*/
3736	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
3737	fMayHaveXSave && pConfig->enmXSave /fAllowed/);
3738	AssertLogRelRCReturn(rc, rc);
3739
3740	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
3741	* Expose the AVX2 instruction set extensions to the guest if available and
3742	* XSAVE is exposed too. For the time being the default is to only expose this
3743	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3744	*/
3745	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec,
3746	fMayHaveXSave && pConfig->enmXSave /fAllowed/);
3747	AssertLogRelRCReturn(rc, rc);
3748
3749	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
3750	* Whether to expose the AES instructions to the guest. For the time being the
3751	* default is to only do this for VMs with nested paging and AMD-V or
3752	* unrestricted guest mode.
3753	*/
3754	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
3755	AssertLogRelRCReturn(rc, rc);
3756
3757	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
3758	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
3759	* being the default is to only do this for VMs with nested paging and AMD-V or
3760	* unrestricted guest mode.
3761	*/
3762	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
3763	AssertLogRelRCReturn(rc, rc);
3764
3765	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
3766	* Whether to expose the POPCNT instructions to the guest. For the time
3767	* being the default is to only do this for VMs with nested paging and AMD-V or
3768	* unrestricted guest mode.
3769	*/
3770	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
3771	AssertLogRelRCReturn(rc, rc);
3772
3773	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
3774	* Whether to expose the MOVBE instructions to the guest. For the time
3775	* being the default is to only do this for VMs with nested paging and AMD-V or
3776	* unrestricted guest mode.
3777	*/
3778	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
3779	AssertLogRelRCReturn(rc, rc);
3780
3781	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
3782	* Whether to expose the RDRAND instructions to the guest. For the time being
3783	* the default is to only do this for VMs with nested paging and AMD-V or
3784	* unrestricted guest mode.
3785	*/
3786	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
3787	AssertLogRelRCReturn(rc, rc);
3788
3789	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
3790	* Whether to expose the RDSEED instructions to the guest. For the time being
3791	* the default is to only do this for VMs with nested paging and AMD-V or
3792	* unrestricted guest mode.
3793	*/
3794	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
3795	AssertLogRelRCReturn(rc, rc);
3796
3797	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
3798	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
3799	* being the default is to only do this for VMs with nested paging and AMD-V or
3800	* unrestricted guest mode.
3801	*/
3802	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
3803	AssertLogRelRCReturn(rc, rc);
3804
3805
3806	/* AMD: */
3807
3808	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
3809	* Whether to expose the AMD ABM instructions to the guest. For the time
3810	* being the default is to only do this for VMs with nested paging and AMD-V or
3811	* unrestricted guest mode.
3812	*/
3813	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
3814	AssertLogRelRCReturn(rc, rc);
3815
3816	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
3817	* Whether to expose the AMD SSE4A instructions to the guest. For the time
3818	* being the default is to only do this for VMs with nested paging and AMD-V or
3819	* unrestricted guest mode.
3820	*/
3821	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
3822	AssertLogRelRCReturn(rc, rc);
3823
3824	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
3825	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
3826	* the time being the default is to only do this for VMs with nested paging and
3827	* AMD-V or unrestricted guest mode.
3828	*/
3829	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
3830	AssertLogRelRCReturn(rc, rc);
3831
3832	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
3833	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
3834	* For the time being the default is to only do this for VMs with nested paging
3835	* and AMD-V or unrestricted guest mode.
3836	*/
3837	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
3838	AssertLogRelRCReturn(rc, rc);
3839
3840	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
3841	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
3842	* the default is to only do this for VMs with nested paging and AMD-V or
3843	* unrestricted guest mode.
3844	*/
3845	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
3846	AssertLogRelRCReturn(rc, rc);
3847
3848	return VINF_SUCCESS;
3849	}
3850
3851
3852	/**
3853	* Initializes the emulated CPU's CPUID & MSR information.
3854	*
3855	* @returns VBox status code.
3856	* @param pVM Pointer to the VM.
3857	*/
3858	int cpumR3InitCpuIdAndMsrs(PVM pVM)
3859	{
3860	PCPUM pCpum = &pVM->cpum.s;
3861	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
3862
3863	/*
3864	* Read the configuration.
3865	*/
3866	CPUMCPUIDCONFIG Config;
3867	RT_ZERO(Config);
3868
3869	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
3870	AssertRCReturn(rc, rc);
3871
3872	/*
3873	* Get the guest CPU data from the database and/or the host.
3874	*
3875	* The CPUID and MSRs are currently living on the regular heap to avoid
3876	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
3877	* API for the hyper heap). This means special cleanup considerations.
3878	*/
3879	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
3880	if (RT_FAILURE(rc))
3881	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
3882	? VMSetError(pVM, rc, RT_SRC_POS,
3883	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
3884	: rc;
3885
3886	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
3887	* Overrides the guest MSRs.
3888	*/
3889	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
3890
3891	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
3892	* Overrides the CPUID leaf values (from the host CPU usually) used for
3893	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
3894	* values when moving a VM to a different machine. Another use is restricting
3895	* (or extending) the feature set exposed to the guest. */
3896	if (RT_SUCCESS(rc))
3897	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
3898
3899	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
3900	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
3901	"Found unsupported configuration node '/CPUM/CPUID/'. "
3902	"Please use IMachine::setCPUIDLeaf() instead.");
3903
3904	/*
3905	* Pre-explode the CPUID info.
3906	*/
3907	if (RT_SUCCESS(rc))
3908	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
3909
3910	/*
3911	* Sanitize the cpuid information passed on to the guest.
3912	*/
3913	if (RT_SUCCESS(rc))
3914	{
3915	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
3916	if (RT_SUCCESS(rc))
3917	{
3918	cpumR3CpuIdLimitLeaves(pCpum, &Config);
3919	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
3920	}
3921	}
3922
3923	/*
3924	* Plant our own hypervisor CPUID leaves.
3925	*/
3926	if (RT_SUCCESS(rc))
3927	rc = cpumR3CpuIdPlantHypervisorLeaves(pCpum, &Config);
3928
3929	/*
3930	* MSR fudging.
3931	*/
3932	if (RT_SUCCESS(rc))
3933	{
3934	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
3935	* Fudges some common MSRs if not present in the selected CPU database entry.
3936	* This is for trying to keep VMs running when moved between different hosts
3937	* and different CPU vendors. */
3938	bool fEnable;
3939	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
3940	if (RT_SUCCESS(rc) && fEnable)
3941	{
3942	rc = cpumR3MsrApplyFudge(pVM);
3943	AssertLogRelRC(rc);
3944	}
3945	}
3946	if (RT_SUCCESS(rc))
3947	{
3948	/*
3949	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
3950	* guest CPU features again.
3951	*/
3952	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
3953	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
3954	pCpum->GuestInfo.cCpuIdLeaves);
3955	RTMemFree(pvFree);
3956
3957	pvFree = pCpum->GuestInfo.paMsrRangesR3;
3958	int rc2 = MMHyperDupMem(pVM, pvFree,
3959	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
3960	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
3961	RTMemFree(pvFree);
3962	AssertLogRelRCReturn(rc1, rc1);
3963	AssertLogRelRCReturn(rc2, rc2);
3964
3965	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
3966	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
3967	cpumR3MsrRegStats(pVM);
3968
3969
3970	/*
3971	* Some more configuration that we're applying at the end of everything
3972	* via the CPUMSetGuestCpuIdFeature API.
3973	*/
3974
3975	/* Check if PAE was explicitely enabled by the user. */
3976	bool fEnable;
3977	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
3978	AssertRCReturn(rc, rc);
3979	if (fEnable)
3980	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3981
3982	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
3983	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
3984	AssertRCReturn(rc, rc);
3985	if (fEnable)
3986	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3987
3988	/* We don't enable the Hypervisor Present bit by default, but it may be needed by some guests. */
3989	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false);
3990	AssertRCReturn(rc, rc);
3991	if (fEnable)
3992	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
3993
3994	return VINF_SUCCESS;
3995	}
3996
3997	/*
3998	* Failed before switching to hyper heap.
3999	*/
4000	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4001	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4002	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4003	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4004	return rc;
4005	}
4006
4007
4008
4009	/*
4010	*
4011	*
4012	* Saved state related code.
4013	* Saved state related code.
4014	* Saved state related code.
4015	*
4016	*
4017	*/
4018
4019	/**
4020	* Called both in pass 0 and the final pass.
4021	*
4022	* @param pVM Pointer to the VM.
4023	* @param pSSM The saved state handle.
4024	*/
4025	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4026	{
4027	/*
4028	* Save all the CPU ID leaves.
4029	*/
4030	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4031	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4032	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4033	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4034
4035	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4036
4037	/*
4038	* Save a good portion of the raw CPU IDs as well as they may come in
4039	* handy when validating features for raw mode.
4040	*/
4041	CPUMCPUID aRawStd[16];
4042	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4043	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4044	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4045	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4046
4047	CPUMCPUID aRawExt[32];
4048	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4049	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4050	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4051	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4052	}
4053
4054
4055	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4056	{
4057	uint32_t cCpuIds;
4058	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4059	if (RT_SUCCESS(rc))
4060	{
4061	if (cCpuIds < 64)
4062	{
4063	for (uint32_t i = 0; i < cCpuIds; i++)
4064	{
4065	CPUMCPUID CpuId;
4066	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4067	if (RT_FAILURE(rc))
4068	break;
4069
4070	CPUMCPUIDLEAF NewLeaf;
4071	NewLeaf.uLeaf = uBase + i;
4072	NewLeaf.uSubLeaf = 0;
4073	NewLeaf.fSubLeafMask = 0;
4074	NewLeaf.uEax = CpuId.uEax;
4075	NewLeaf.uEbx = CpuId.uEbx;
4076	NewLeaf.uEcx = CpuId.uEcx;
4077	NewLeaf.uEdx = CpuId.uEdx;
4078	NewLeaf.fFlags = 0;
4079	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4080	}
4081	}
4082	else
4083	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4084	}
4085	if (RT_FAILURE(rc))
4086	{
4087	RTMemFree(*ppaLeaves);
4088	*ppaLeaves = NULL;
4089	*pcLeaves = 0;
4090	}
4091	return rc;
4092	}
4093
4094
4095	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4096	{
4097	*ppaLeaves = NULL;
4098	*pcLeaves = 0;
4099
4100	int rc;
4101	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4102	{
4103	/*
4104	* The new format. Starts by declaring the leave size and count.
4105	*/
4106	uint32_t cbLeaf;
4107	SSMR3GetU32(pSSM, &cbLeaf);
4108	uint32_t cLeaves;
4109	rc = SSMR3GetU32(pSSM, &cLeaves);
4110	if (RT_SUCCESS(rc))
4111	{
4112	if (cbLeaf == sizeof(**ppaLeaves))
4113	{
4114	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4115	{
4116	/*
4117	* Load the leaves one by one.
4118	*
4119	* The uPrev stuff is a kludge for working around a week worth of bad saved
4120	* states during the CPUID revamp in March 2015. We saved too many leaves
4121	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4122	* garbage entires at the end of the array when restoring. We also had
4123	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
4124	* this kludge doesn't deal correctly with that, but who cares...
4125	*/
4126	uint32_t uPrev = 0;
4127	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4128	{
4129	CPUMCPUIDLEAF Leaf;
4130	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
4131	if (RT_SUCCESS(rc))
4132	{
4133	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
4134	\|\| Leaf.uLeaf >= uPrev)
4135	{
4136	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4137	uPrev = Leaf.uLeaf;
4138	}
4139	else
4140	uPrev = UINT32_MAX;
4141	}
4142	}
4143	}
4144	else
4145	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
4146	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
4147	}
4148	else
4149	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
4150	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
4151	}
4152	}
4153	else
4154	{
4155	/*
4156	* The old format with its three inflexible arrays.
4157	*/
4158	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
4159	if (RT_SUCCESS(rc))
4160	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
4161	if (RT_SUCCESS(rc))
4162	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
4163	if (RT_SUCCESS(rc))
4164	{
4165	/*
4166	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
4167	*/
4168	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
4169	if ( pLeaf
4170	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
4171	{
4172	CPUMCPUIDLEAF Leaf;
4173	Leaf.uLeaf = 4;
4174	Leaf.fSubLeafMask = UINT32_MAX;
4175	Leaf.uSubLeaf = 0;
4176	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
4177	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
4178	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
4179	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
4180	\| UINT32_C(63); /* system coherency line size - 1 */
4181	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
4182	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
4183	\| (UINT32_C(1) << 5) /* cache level */
4184	\| UINT32_C(1); /* cache type (data) */
4185	Leaf.fFlags = 0;
4186	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4187	if (RT_SUCCESS(rc))
4188	{
4189	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
4190	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4191	}
4192	if (RT_SUCCESS(rc))
4193	{
4194	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
4195	Leaf.uEcx = 4095; /* sets - 1 */
4196	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
4197	Leaf.uEbx \|= UINT32_C(23) << 22;
4198	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
4199	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
4200	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
4201	Leaf.uEax \|= UINT32_C(2) << 5;
4202	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4203	}
4204	}
4205	}
4206	}
4207	return rc;
4208	}
4209
4210
4211	/**
4212	* Loads the CPU ID leaves saved by pass 0, inner worker.
4213	*
4214	* @returns VBox status code.
4215	* @param pVM Pointer to the VM.
4216	* @param pSSM The saved state handle.
4217	* @param uVersion The format version.
4218	* @param paLeaves Guest CPUID leaves loaded from the state.
4219	* @param cLeaves The number of leaves in @a paLeaves.
4220	*/
4221	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
4222	{
4223	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4224
4225	/*
4226	* Continue loading the state into stack buffers.
4227	*/
4228	CPUMCPUID GuestDefCpuId;
4229	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
4230	AssertRCReturn(rc, rc);
4231
4232	CPUMCPUID aRawStd[16];
4233	uint32_t cRawStd;
4234	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
4235	if (cRawStd > RT_ELEMENTS(aRawStd))
4236	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4237	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
4238	AssertRCReturn(rc, rc);
4239	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
4240	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4241
4242	CPUMCPUID aRawExt[32];
4243	uint32_t cRawExt;
4244	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
4245	if (cRawExt > RT_ELEMENTS(aRawExt))
4246	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4247	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
4248	AssertRCReturn(rc, rc);
4249	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
4250	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4251
4252	/*
4253	* Get the raw CPU IDs for the current host.
4254	*/
4255	CPUMCPUID aHostRawStd[16];
4256	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
4257	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
4258
4259	CPUMCPUID aHostRawExt[32];
4260	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
4261	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
4262	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4263
4264	/*
4265	* Get the host and guest overrides so we don't reject the state because
4266	* some feature was enabled thru these interfaces.
4267	* Note! We currently only need the feature leaves, so skip rest.
4268	*/
4269	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4270	CPUMCPUID aHostOverrideStd[2];
4271	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4272	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4273
4274	CPUMCPUID aHostOverrideExt[2];
4275	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4276	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4277
4278	/*
4279	* This can be skipped.
4280	*/
4281	bool fStrictCpuIdChecks;
4282	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
4283
4284	/*
4285	* Define a bunch of macros for simplifying the santizing/checking code below.
4286	*/
4287	/* Generic expression + failure message. */
4288	#define CPUID_CHECK_RET(expr, fmt) \
4289	do { \
4290	if (!(expr)) \
4291	{ \
4292	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
4293	if (fStrictCpuIdChecks) \
4294	{ \
4295	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4296	RTStrFree(pszMsg); \
4297	return rcCpuid; \
4298	} \
4299	LogRel(("CPUM: %s\n", pszMsg)); \
4300	RTStrFree(pszMsg); \
4301	} \
4302	} while (0)
4303	#define CPUID_CHECK_WRN(expr, fmt) \
4304	do { \
4305	if (!(expr)) \
4306	LogRel(fmt); \
4307	} while (0)
4308
4309	/* For comparing two values and bitch if they differs. */
4310	#define CPUID_CHECK2_RET(what, host, saved) \
4311	do { \
4312	if ((host) != (saved)) \
4313	{ \
4314	if (fStrictCpuIdChecks) \
4315	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4316	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
4317	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4318	} \
4319	} while (0)
4320	#define CPUID_CHECK2_WRN(what, host, saved) \
4321	do { \
4322	if ((host) != (saved)) \
4323	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4324	} while (0)
4325
4326	/* For checking raw cpu features (raw mode). */
4327	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
4328	do { \
4329	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4330	{ \
4331	if (fStrictCpuIdChecks) \
4332	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4333	N_(#bit " mismatch: host=%d saved=%d"), \
4334	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
4335	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4336	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4337	} \
4338	} while (0)
4339	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
4340	do { \
4341	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4342	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4343	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4344	} while (0)
4345	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
4346
4347	/* For checking guest features. */
4348	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
4349	do { \
4350	if ( (aGuestCpuId##set [1].reg & bit) \
4351	&& !(aHostRaw##set [1].reg & bit) \
4352	&& !(aHostOverride##set [1].reg & bit) \
4353	) \
4354	{ \
4355	if (fStrictCpuIdChecks) \
4356	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4357	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4358	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4359	} \
4360	} while (0)
4361	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
4362	do { \
4363	if ( (aGuestCpuId##set [1].reg & bit) \
4364	&& !(aHostRaw##set [1].reg & bit) \
4365	&& !(aHostOverride##set [1].reg & bit) \
4366	) \
4367	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4368	} while (0)
4369	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
4370	do { \
4371	if ( (aGuestCpuId##set [1].reg & bit) \
4372	&& !(aHostRaw##set [1].reg & bit) \
4373	&& !(aHostOverride##set [1].reg & bit) \
4374	) \
4375	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4376	} while (0)
4377	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
4378
4379	/* For checking guest features if AMD guest CPU. */
4380	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
4381	do { \
4382	if ( (aGuestCpuId##set [1].reg & bit) \
4383	&& fGuestAmd \
4384	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4385	&& !(aHostOverride##set [1].reg & bit) \
4386	) \
4387	{ \
4388	if (fStrictCpuIdChecks) \
4389	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4390	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4391	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4392	} \
4393	} while (0)
4394	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
4395	do { \
4396	if ( (aGuestCpuId##set [1].reg & bit) \
4397	&& fGuestAmd \
4398	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4399	&& !(aHostOverride##set [1].reg & bit) \
4400	) \
4401	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4402	} while (0)
4403	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
4404	do { \
4405	if ( (aGuestCpuId##set [1].reg & bit) \
4406	&& fGuestAmd \
4407	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4408	&& !(aHostOverride##set [1].reg & bit) \
4409	) \
4410	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4411	} while (0)
4412	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
4413
4414	/* For checking AMD features which have a corresponding bit in the standard
4415	range. (Intel defines very few bits in the extended feature sets.) */
4416	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
4417	do { \
4418	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4419	&& !(fHostAmd \
4420	? aHostRawExt[1].reg & (ExtBit) \
4421	: aHostRawStd[1].reg & (StdBit)) \
4422	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4423	) \
4424	{ \
4425	if (fStrictCpuIdChecks) \
4426	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4427	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
4428	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4429	} \
4430	} while (0)
4431	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
4432	do { \
4433	if ( (aGuestCpuId[1].reg & (ExtBit)) \
4434	&& !(fHostAmd \
4435	? aHostRawExt[1].reg & (ExtBit) \
4436	: aHostRawStd[1].reg & (StdBit)) \
4437	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4438	) \
4439	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4440	} while (0)
4441	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
4442	do { \
4443	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4444	&& !(fHostAmd \
4445	? aHostRawExt[1].reg & (ExtBit) \
4446	: aHostRawStd[1].reg & (StdBit)) \
4447	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4448	) \
4449	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4450	} while (0)
4451	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
4452
4453	/*
4454	* For raw-mode we'll require that the CPUs are very similar since we don't
4455	* intercept CPUID instructions for user mode applications.
4456	*/
4457	if (!HMIsEnabled(pVM))
4458	{
4459	/* CPUID(0) */
4460	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
4461	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
4462	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
4463	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
4464	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
4465	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
4466	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
4467	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
4468	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
4469
4470	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
4471
4472	/* CPUID(1).eax */
4473	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
4474	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
4475	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
4476
4477	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
4478	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
4479	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
4480
4481	/* CPUID(1).ecx */
4482	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
4483	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
4484	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
4485	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4486	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
4487	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
4488	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
4489	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
4490	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
4491	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
4492	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
4493	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
4494	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
4495	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
4496	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
4497	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
4498	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
4499	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4500	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
4501	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
4502	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
4503	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4504	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
4505	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
4506	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4507	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
4508	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
4509	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4510	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
4511	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4512	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4513	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
4514
4515	/* CPUID(1).edx */
4516	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4517	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4518	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
4519	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4520	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
4521	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
4522	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4523	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4524	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
4525	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4526	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
4527	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4528	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4529	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4530	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4531	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
4532	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4533	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4534	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4535	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
4536	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
4537	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
4538	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
4539	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
4540	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
4541	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
4542	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
4543	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
4544	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
4545	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
4546	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
4547	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
4548
4549	/* CPUID(2) - config, mostly about caches. ignore. */
4550	/* CPUID(3) - processor serial number. ignore. */
4551	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
4552	/* CPUID(5) - mwait/monitor config. ignore. */
4553	/* CPUID(6) - power management. ignore. */
4554	/* CPUID(7) - ???. ignore. */
4555	/* CPUID(8) - ???. ignore. */
4556	/* CPUID(9) - DCA. ignore for now. */
4557	/* CPUID(a) - PeMo info. ignore for now. */
4558	/* CPUID(b) - topology info - takes ECX as input. ignore. */
4559
4560	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
4561	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
4562	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
4563	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
4564	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
4565	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
4566	{
4567	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
4568	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
4569	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
4570	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
4571	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
4572	}
4573
4574	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
4575	Note! Intel have/is marking many of the fields here as reserved. We
4576	will verify them as if it's an AMD CPU. */
4577	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
4578	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
4579	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
4580	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
4581	{
4582	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
4583	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
4584	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
4585	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
4586	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
4587	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
4588	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
4589
4590	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
4591	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
4592	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
4593	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
4594	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
4595	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
4596
4597	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
4598	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
4599	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
4600	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
4601
4602	/* CPUID(0x80000001).ecx */
4603	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
4604	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
4605	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
4606	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
4607	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
4608	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
4609	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
4610	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
4611	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
4612	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
4613	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
4614	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
4615	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
4616	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
4617	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4618	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4619	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4620	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4621	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4622	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4623	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4624	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4625	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4626	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4627	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4628	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4629	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4630	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4631	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4632	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4633	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4634	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4635
4636	/* CPUID(0x80000001).edx */
4637	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
4638	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
4639	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
4640	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
4641	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
4642	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
4643	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
4644	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
4645	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
4646	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
4647	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4648	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
4649	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
4650	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
4651	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
4652	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
4653	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
4654	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
4655	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4656	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4657	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4658	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
4659	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4660	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
4661	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
4662	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4663	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4664	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4665	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
4666	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4667	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4668	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4669
4670	/** @todo verify the rest as well. */
4671	}
4672	}
4673
4674
4675
4676	/*
4677	* Verify that we can support the features already exposed to the guest on
4678	* this host.
4679	*
4680	* Most of the features we're emulating requires intercepting instruction
4681	* and doing it the slow way, so there is no need to warn when they aren't
4682	* present in the host CPU. Thus we use IGN instead of EMU on these.
4683	*
4684	* Trailing comments:
4685	* "EMU" - Possible to emulate, could be lots of work and very slow.
4686	* "EMU?" - Can this be emulated?
4687	*/
4688	CPUMCPUID aGuestCpuIdStd[2];
4689	RT_ZERO(aGuestCpuIdStd);
4690	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
4691
4692	/* CPUID(1).ecx */
4693	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
4694	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
4695	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
4696	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4697	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
4698	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
4699	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
4700	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
4701	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
4702	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
4703	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
4704	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
4705	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
4706	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
4707	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
4708	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
4709	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
4710	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4711	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
4712	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
4713	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
4714	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4715	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
4716	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
4717	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4718	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
4719	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
4720	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4721	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
4722	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4723	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4724	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
4725
4726	/* CPUID(1).edx */
4727	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4728	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4729	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
4730	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4731	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4732	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4733	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4734	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4735	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4736	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4737	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
4738	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4739	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4740	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4741	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4742	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4743	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4744	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4745	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4746	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
4747	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
4748	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
4749	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
4750	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4751	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4752	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
4753	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
4754	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
4755	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
4756	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
4757	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
4758	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
4759
4760	/* CPUID(0x80000000). */
4761	CPUMCPUID aGuestCpuIdExt[2];
4762	RT_ZERO(aGuestCpuIdExt);
4763	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
4764	{
4765	/** @todo deal with no 0x80000001 on the host. */
4766	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
4767	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
4768
4769	/* CPUID(0x80000001).ecx */
4770	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
4771	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
4772	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
4773	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
4774	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
4775	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
4776	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
4777	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
4778	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
4779	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
4780	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
4781	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
4782	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
4783	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
4784	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4785	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4786	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4787	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4788	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4789	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4790	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4791	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4792	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4793	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4794	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4795	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4796	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4797	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4798	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4799	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4800	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4801	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4802
4803	/* CPUID(0x80000001).edx */
4804	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
4805	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
4806	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
4807	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
4808	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4809	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4810	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
4811	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
4812	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4813	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
4814	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4815	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
4816	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
4817	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
4818	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
4819	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4820	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
4821	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
4822	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4823	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4824	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4825	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
4826	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4827	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4828	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4829	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4830	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4831	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4832	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
4833	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4834	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4835	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4836	}
4837
4838	/** @todo check leaf 7 */
4839
4840	/* CPUID(d) - XCR0 stuff - takes ECX as input.
4841	* ECX=0: EAX - Valid bits in XCR0[31:0].
4842	* EBX - Maximum state size as per current XCR0 value.
4843	* ECX - Maximum state size for all supported features.
4844	* EDX - Valid bits in XCR0[63:32].
4845	* ECX=1: EAX - Various X-features.
4846	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
4847	* ECX - Valid bits in IA32_XSS[31:0].
4848	* EDX - Valid bits in IA32_XSS[63:32].
4849	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
4850	* if the bit invalid all four registers are set to zero.
4851	* EAX - The state size for this feature.
4852	* EBX - The state byte offset of this feature.
4853	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
4854	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
4855	*/
4856	uint64_t fGuestXcr0Mask = 0;
4857	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
4858	if ( pCurLeaf
4859	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
4860	&& ( pCurLeaf->uEax
4861	\|\| pCurLeaf->uEbx
4862	\|\| pCurLeaf->uEcx
4863	\|\| pCurLeaf->uEdx) )
4864	{
4865	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
4866	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
4867	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4868	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
4869	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
4870	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
4871	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4872	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
4873
4874	/* We don't support any additional features yet. */
4875	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
4876	if (pCurLeaf && pCurLeaf->uEax)
4877	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4878	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
4879	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
4880	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4881	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
4882	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
4883
4884
4885	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
4886	{
4887	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4888	if (pCurLeaf)
4889	{
4890	/* If advertised, the state component offset and size must match the one used by host. */
4891	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
4892	{
4893	CPUMCPUID RawHost;
4894	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
4895	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
4896	if ( RawHost.uEbx != pCurLeaf->uEbx
4897	\|\| RawHost.uEax != pCurLeaf->uEax)
4898	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4899	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
4900	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
4901	}
4902	}
4903	}
4904	}
4905	/* Clear leaf 0xd just in case we're loading an old state... */
4906	else if (pCurLeaf)
4907	{
4908	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
4909	{
4910	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4911	if (pCurLeaf)
4912	{
4913	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
4914	\|\| ( pCurLeaf->uEax == 0
4915	&& pCurLeaf->uEbx == 0
4916	&& pCurLeaf->uEcx == 0
4917	&& pCurLeaf->uEdx == 0),
4918	("uVersion=%#x; %#x %#x %#x %#x\n",
4919	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
4920	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
4921	}
4922	}
4923	}
4924
4925	/* Update the fXStateGuestMask value for the VM. */
4926	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
4927	{
4928	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
4929	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
4930	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
4931	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4932	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
4933	}
4934
4935	#undef CPUID_CHECK_RET
4936	#undef CPUID_CHECK_WRN
4937	#undef CPUID_CHECK2_RET
4938	#undef CPUID_CHECK2_WRN
4939	#undef CPUID_RAW_FEATURE_RET
4940	#undef CPUID_RAW_FEATURE_WRN
4941	#undef CPUID_RAW_FEATURE_IGN
4942	#undef CPUID_GST_FEATURE_RET
4943	#undef CPUID_GST_FEATURE_WRN
4944	#undef CPUID_GST_FEATURE_EMU
4945	#undef CPUID_GST_FEATURE_IGN
4946	#undef CPUID_GST_FEATURE2_RET
4947	#undef CPUID_GST_FEATURE2_WRN
4948	#undef CPUID_GST_FEATURE2_EMU
4949	#undef CPUID_GST_FEATURE2_IGN
4950	#undef CPUID_GST_AMD_FEATURE_RET
4951	#undef CPUID_GST_AMD_FEATURE_WRN
4952	#undef CPUID_GST_AMD_FEATURE_EMU
4953	#undef CPUID_GST_AMD_FEATURE_IGN
4954
4955	/*
4956	* We're good, commit the CPU ID leaves.
4957	*/
4958	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
4959	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
4960	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
4961	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
4962	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
4963	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
4964	AssertLogRelRCReturn(rc, rc);
4965
4966	return VINF_SUCCESS;
4967	}
4968
4969
4970	/**
4971	* Loads the CPU ID leaves saved by pass 0.
4972	*
4973	* @returns VBox status code.
4974	* @param pVM Pointer to the VM.
4975	* @param pSSM The saved state handle.
4976	* @param uVersion The format version.
4977	*/
4978	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
4979	{
4980	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4981
4982	/*
4983	* Load the CPUID leaves array first and call worker to do the rest, just so
4984	* we can free the memory when we need to without ending up in column 1000.
4985	*/
4986	PCPUMCPUIDLEAF paLeaves;
4987	uint32_t cLeaves;
4988	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
4989	AssertRC(rc);
4990	if (RT_SUCCESS(rc))
4991	{
4992	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
4993	RTMemFree(paLeaves);
4994	}
4995	return rc;
4996	}
4997
4998
4999
5000	/**
5001	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5002	*
5003	* @returns VBox status code.
5004	* @param pVM Pointer to the VM.
5005	* @param pSSM The saved state handle.
5006	* @param uVersion The format version.
5007	*/
5008	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5009	{
5010	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5011
5012	/*
5013	* Restore the CPUID leaves.
5014	*
5015	* Note that we support restoring less than the current amount of standard
5016	* leaves because we've been allowed more is newer version of VBox.
5017	*/
5018	uint32_t cElements;
5019	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5020	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5021	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5022	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5023
5024	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5025	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5026	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5027	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5028
5029	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5030	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5031	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5032	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5033
5034	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5035
5036	/*
5037	* Check that the basic cpuid id information is unchanged.
5038	*/
5039	/** @todo we should check the 64 bits capabilities too! */
5040	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5041	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5042	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5043	uint32_t au32CpuIdSaved[8];
5044	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5045	if (RT_SUCCESS(rc))
5046	{
5047	/* Ignore CPU stepping. */
5048	au32CpuId[4] &= 0xfffffff0;
5049	au32CpuIdSaved[4] &= 0xfffffff0;
5050
5051	/* Ignore APIC ID (AMD specs). */
5052	au32CpuId[5] &= ~0xff000000;
5053	au32CpuIdSaved[5] &= ~0xff000000;
5054
5055	/* Ignore the number of Logical CPUs (AMD specs). */
5056	au32CpuId[5] &= ~0x00ff0000;
5057	au32CpuIdSaved[5] &= ~0x00ff0000;
5058
5059	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5060	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5061	\| X86_CPUID_FEATURE_ECX_VMX
5062	\| X86_CPUID_FEATURE_ECX_SMX
5063	\| X86_CPUID_FEATURE_ECX_EST
5064	\| X86_CPUID_FEATURE_ECX_TM2
5065	\| X86_CPUID_FEATURE_ECX_CNTXID
5066	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5067	\| X86_CPUID_FEATURE_ECX_PDCM
5068	\| X86_CPUID_FEATURE_ECX_DCA
5069	\| X86_CPUID_FEATURE_ECX_X2APIC
5070	);
5071	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5072	\| X86_CPUID_FEATURE_ECX_VMX
5073	\| X86_CPUID_FEATURE_ECX_SMX
5074	\| X86_CPUID_FEATURE_ECX_EST
5075	\| X86_CPUID_FEATURE_ECX_TM2
5076	\| X86_CPUID_FEATURE_ECX_CNTXID
5077	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5078	\| X86_CPUID_FEATURE_ECX_PDCM
5079	\| X86_CPUID_FEATURE_ECX_DCA
5080	\| X86_CPUID_FEATURE_ECX_X2APIC
5081	);
5082
5083	/* Make sure we don't forget to update the masks when enabling
5084	* features in the future.
5085	*/
5086	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5087	( X86_CPUID_FEATURE_ECX_DTES64
5088	\| X86_CPUID_FEATURE_ECX_VMX
5089	\| X86_CPUID_FEATURE_ECX_SMX
5090	\| X86_CPUID_FEATURE_ECX_EST
5091	\| X86_CPUID_FEATURE_ECX_TM2
5092	\| X86_CPUID_FEATURE_ECX_CNTXID
5093	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5094	\| X86_CPUID_FEATURE_ECX_PDCM
5095	\| X86_CPUID_FEATURE_ECX_DCA
5096	\| X86_CPUID_FEATURE_ECX_X2APIC
5097	)));
5098	/* do the compare */
5099	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5100	{
5101	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5102	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5103	"Saved=%.*Rhxs\n"
5104	"Real =%.*Rhxs\n",
5105	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5106	sizeof(au32CpuId), au32CpuId));
5107	else
5108	{
5109	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5110	"Saved=%.*Rhxs\n"
5111	"Real =%.*Rhxs\n",
5112	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5113	sizeof(au32CpuId), au32CpuId));
5114	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5115	}
5116	}
5117	}
5118
5119	return rc;
5120	}
5121
5122
5123
5124	/*
5125	*
5126	*
5127	* CPUID Info Handler.
5128	* CPUID Info Handler.
5129	* CPUID Info Handler.
5130	*
5131	*
5132	*/
5133
5134
5135
5136	/**
5137	* Get L1 cache / TLS associativity.
5138	*/
5139	static const char getCacheAss(unsigned u, char pszBuf)
5140	{
5141	if (u == 0)
5142	return "res0 ";
5143	if (u == 1)
5144	return "direct";
5145	if (u == 255)
5146	return "fully";
5147	if (u >= 256)
5148	return "???";
5149
5150	RTStrPrintf(pszBuf, 16, "%d way", u);
5151	return pszBuf;
5152	}
5153
5154
5155	/**
5156	* Get L2 cache associativity.
5157	*/
5158	const char *getL2CacheAss(unsigned u)
5159	{
5160	switch (u)
5161	{
5162	case 0: return "off ";
5163	case 1: return "direct";
5164	case 2: return "2 way ";
5165	case 3: return "res3 ";
5166	case 4: return "4 way ";
5167	case 5: return "res5 ";
5168	case 6: return "8 way ";
5169	case 7: return "res7 ";
5170	case 8: return "16 way";
5171	case 9: return "res9 ";
5172	case 10: return "res10 ";
5173	case 11: return "res11 ";
5174	case 12: return "res12 ";
5175	case 13: return "res13 ";
5176	case 14: return "res14 ";
5177	case 15: return "fully ";
5178	default: return "????";
5179	}
5180	}
5181
5182
5183	/** CPUID(1).EDX field descriptions. */
5184	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
5185	{
5186	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5187	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5188	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5189	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5190	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5191	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
5192	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5193	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5194	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5195	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5196	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
5197	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5198	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5199	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5200	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5201	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5202	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5203	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
5204	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
5205	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
5206	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
5207	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5208	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
5209	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
5210	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
5211	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
5212	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
5213	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
5214	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
5215	DBGFREGSUBFIELD_TERMINATOR()
5216	};
5217
5218	/** CPUID(1).ECX field descriptions. */
5219	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
5220	{
5221	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
5222	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
5223	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
5224	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
5225	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
5226	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
5227	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
5228	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
5229	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
5230	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
5231	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
5232	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
5233	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
5234	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
5235	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
5236	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
5237	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
5238	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
5239	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
5240	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
5241	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
5242	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
5243	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
5244	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
5245	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
5246	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
5247	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
5248	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
5249	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
5250	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
5251	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
5252	DBGFREGSUBFIELD_TERMINATOR()
5253	};
5254
5255	/** CPUID(7,0).EBX field descriptions. */
5256	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
5257	{
5258	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
5259	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
5260	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
5261	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
5262	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
5263	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
5264	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
5265	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
5266	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
5267	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
5268	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
5269	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
5270	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
5271	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
5272	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
5273	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
5274	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
5275	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
5276	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
5277	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
5278	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
5279	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
5280	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
5281	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
5282	DBGFREGSUBFIELD_TERMINATOR()
5283	};
5284
5285	/** CPUID(7,0).ECX field descriptions. */
5286	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
5287	{
5288	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
5289	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
5290	DBGFREGSUBFIELD_RO("OSPKU\0" "CR4.PKU mirror", 4, 1, 0),
5291	DBGFREGSUBFIELD_TERMINATOR()
5292	};
5293
5294
5295	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
5296	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
5297	{
5298	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
5299	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
5300	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
5301	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
5302	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
5303	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
5304	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
5305	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
5306	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
5307	DBGFREGSUBFIELD_TERMINATOR()
5308	};
5309
5310	/** CPUID(13,1).EAX field descriptions. */
5311	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
5312	{
5313	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
5314	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
5315	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
5316	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
5317	DBGFREGSUBFIELD_TERMINATOR()
5318	};
5319
5320
5321	/** CPUID(0x80000001,0).EDX field descriptions. */
5322	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
5323	{
5324	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5325	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5326	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5327	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5328	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5329	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
5330	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5331	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5332	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5333	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5334	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
5335	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5336	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5337	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5338	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5339	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5340	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5341	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
5342	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
5343	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5344	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
5345	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
5346	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
5347	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
5348	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
5349	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
5350	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
5351	DBGFREGSUBFIELD_TERMINATOR()
5352	};
5353
5354	/** CPUID(0x80000001,0).ECX field descriptions. */
5355	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
5356	{
5357	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
5358	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
5359	DBGFREGSUBFIELD_RO("SVM\0" "AMD VM extensions", 2, 1, 0),
5360	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
5361	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
5362	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
5363	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
5364	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
5365	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
5366	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
5367	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
5368	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
5369	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
5370	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
5371	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
5372	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
5373	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
5374	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
5375	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
5376	DBGFREGSUBFIELD_TERMINATOR()
5377	};
5378
5379
5380	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
5381	const char *pszLeadIn, uint32_t cchWidth)
5382	{
5383	if (pszLeadIn)
5384	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5385
5386	for (uint32_t iBit = 0; iBit < 32; iBit++)
5387	if (RT_BIT_32(iBit) & uVal)
5388	{
5389	while ( pDesc->pszName != NULL
5390	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5391	pDesc++;
5392	if ( pDesc->pszName != NULL
5393	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5394	{
5395	if (pDesc->cBits == 1)
5396	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5397	else
5398	{
5399	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
5400	if (pDesc->cBits < 32)
5401	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5402	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
5403	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5404	}
5405	}
5406	else
5407	pHlp->pfnPrintf(pHlp, " %u", iBit);
5408	}
5409	if (pszLeadIn)
5410	pHlp->pfnPrintf(pHlp, "\n");
5411	}
5412
5413
5414	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5415	const char *pszLeadIn, uint32_t cchWidth)
5416	{
5417	if (pszLeadIn)
5418	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5419
5420	for (uint32_t iBit = 0; iBit < 64; iBit++)
5421	if (RT_BIT_64(iBit) & uVal)
5422	{
5423	while ( pDesc->pszName != NULL
5424	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5425	pDesc++;
5426	if ( pDesc->pszName != NULL
5427	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5428	{
5429	if (pDesc->cBits == 1)
5430	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5431	else
5432	{
5433	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
5434	if (pDesc->cBits < 64)
5435	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
5436	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
5437	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5438	}
5439	}
5440	else
5441	pHlp->pfnPrintf(pHlp, " %u", iBit);
5442	}
5443	if (pszLeadIn)
5444	pHlp->pfnPrintf(pHlp, "\n");
5445	}
5446
5447
5448	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5449	const char *pszLeadIn, uint32_t cchWidth)
5450	{
5451	if (!uVal)
5452	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5453	else
5454	{
5455	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5456	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
5457	pHlp->pfnPrintf(pHlp, " )\n");
5458	}
5459	}
5460
5461
5462	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
5463	uint32_t cchWidth)
5464	{
5465	uint32_t uCombined = uVal1 \| uVal2;
5466	for (uint32_t iBit = 0; iBit < 32; iBit++)
5467	if ( (RT_BIT_32(iBit) & uCombined)
5468	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
5469	{
5470	while ( pDesc->pszName != NULL
5471	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5472	pDesc++;
5473
5474	if ( pDesc->pszName != NULL
5475	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5476	{
5477	size_t cchMnemonic = strlen(pDesc->pszName);
5478	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
5479	size_t cchDesc = strlen(pszDesc);
5480	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
5481	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
5482	if (pDesc->cBits < 32)
5483	{
5484	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5485	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5486	}
5487
5488	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
5489	pDesc->pszName, pszDesc,
5490	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
5491	uFieldValue1, uFieldValue2);
5492
5493	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
5494	pDesc++;
5495	}
5496	else
5497	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
5498	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
5499	}
5500	}
5501
5502
5503	/**
5504	* Produces a detailed summary of standard leaf 0x00000001.
5505	*
5506	* @param pHlp The info helper functions.
5507	* @param paLeaves The CPUID leaves array.
5508	* @param cLeaves The number of leaves in the array.
5509	* @param pCurLeaf The 0x00000001 leaf.
5510	* @param fVerbose Whether to be very verbose or not.
5511	* @param fIntel Set if intel CPU.
5512	*/
5513	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5514	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
5515	{
5516	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
5517	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
5518	uint32_t uEAX = pCurLeaf->uEax;
5519	uint32_t uEBX = pCurLeaf->uEbx;
5520
5521	pHlp->pfnPrintf(pHlp,
5522	"%36s %2d \tExtended: %d \tEffective: %d\n"
5523	"%36s %2d \tExtended: %d \tEffective: %d\n"
5524	"%36s %d\n"
5525	"%36s %d (%s)\n"
5526	"%36s %#04x\n"
5527	"%36s %d\n"
5528	"%36s %d\n"
5529	"%36s %#04x\n"
5530	,
5531	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
5532	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
5533	"Stepping:", ASMGetCpuStepping(uEAX),
5534	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
5535	"APIC ID:", (uEBX >> 24) & 0xff,
5536	"Logical CPUs:",(uEBX >> 16) & 0xff,
5537	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
5538	"Brand ID:", (uEBX >> 0) & 0xff);
5539	if (fVerbose)
5540	{
5541	CPUMCPUID Host;
5542	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5543	pHlp->pfnPrintf(pHlp, "Features\n");
5544	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5545	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
5546	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
5547	}
5548	else
5549	{
5550	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
5551	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
5552	}
5553	}
5554
5555
5556	/**
5557	* Produces a detailed summary of standard leaf 0x00000007.
5558	*
5559	* @param pHlp The info helper functions.
5560	* @param paLeaves The CPUID leaves array.
5561	* @param cLeaves The number of leaves in the array.
5562	* @param pCurLeaf The first 0x00000007 leaf.
5563	* @param fVerbose Whether to be very verbose or not.
5564	*/
5565	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5566	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5567	{
5568	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
5569	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
5570	for (;;)
5571	{
5572	CPUMCPUID Host;
5573	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5574
5575	switch (pCurLeaf->uSubLeaf)
5576	{
5577	case 0:
5578	if (fVerbose)
5579	{
5580	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5581	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
5582	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
5583	if (pCurLeaf->uEdx \|\| Host.uEdx)
5584	pHlp->pfnPrintf(pHlp, "%36 %#x (%#x)\n", "Ext Features EDX:", pCurLeaf->uEdx, Host.uEdx);
5585	}
5586	else
5587	{
5588	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
5589	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
5590	if (pCurLeaf->uEdx)
5591	pHlp->pfnPrintf(pHlp, "%36 %#x\n", "Ext Features EDX:", pCurLeaf->uEdx);
5592	}
5593	break;
5594
5595	default:
5596	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
5597	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
5598	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
5599	break;
5600
5601	}
5602
5603	/* advance. */
5604	pCurLeaf++;
5605	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5606	\|\| pCurLeaf->uLeaf != 0x7)
5607	break;
5608	}
5609	}
5610
5611
5612	/**
5613	* Produces a detailed summary of standard leaf 0x0000000d.
5614	*
5615	* @param pHlp The info helper functions.
5616	* @param paLeaves The CPUID leaves array.
5617	* @param cLeaves The number of leaves in the array.
5618	* @param pCurLeaf The first 0x00000007 leaf.
5619	* @param fVerbose Whether to be very verbose or not.
5620	*/
5621	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5622	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5623	{
5624	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
5625	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
5626	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5627	{
5628	CPUMCPUID Host;
5629	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5630
5631	switch (uSubLeaf)
5632	{
5633	case 0:
5634	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5635	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
5636	pCurLeaf->uEbx, pCurLeaf->uEcx);
5637	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
5638
5639	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5640	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
5641	"Valid XCR0 bits, guest:", 42);
5642	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
5643	"Valid XCR0 bits, host:", 42);
5644	break;
5645
5646	case 1:
5647	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5648	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
5649	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
5650
5651	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5652	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
5653	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
5654
5655	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5656	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
5657	" Valid IA32_XSS bits, guest:", 42);
5658	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
5659	" Valid IA32_XSS bits, host:", 42);
5660	break;
5661
5662	default:
5663	if ( pCurLeaf
5664	&& pCurLeaf->uSubLeaf == uSubLeaf
5665	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
5666	{
5667	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
5668	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5669	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
5670	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
5671	if (pCurLeaf->uEdx)
5672	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
5673	pHlp->pfnPrintf(pHlp, " --");
5674	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5675	pHlp->pfnPrintf(pHlp, "\n");
5676	}
5677	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
5678	{
5679	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
5680	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5681	if (Host.uEcx & ~RT_BIT_32(0))
5682	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
5683	if (Host.uEdx)
5684	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
5685	pHlp->pfnPrintf(pHlp, " --");
5686	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5687	pHlp->pfnPrintf(pHlp, "\n");
5688	}
5689	break;
5690
5691	}
5692
5693	/* advance. */
5694	if (pCurLeaf)
5695	{
5696	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5697	&& pCurLeaf->uSubLeaf <= uSubLeaf
5698	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
5699	pCurLeaf++;
5700	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5701	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
5702	pCurLeaf = NULL;
5703	}
5704	}
5705	}
5706
5707
5708	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5709	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
5710	{
5711	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5712	&& pCurLeaf->uLeaf <= uUpToLeaf)
5713	{
5714	pHlp->pfnPrintf(pHlp,
5715	" %s\n"
5716	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
5717	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5718	&& pCurLeaf->uLeaf <= uUpToLeaf)
5719	{
5720	CPUMCPUID Host;
5721	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5722	pHlp->pfnPrintf(pHlp,
5723	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5724	"Hst: %08x %08x %08x %08x\n",
5725	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5726	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5727	pCurLeaf++;
5728	}
5729	}
5730
5731	return pCurLeaf;
5732	}
5733
5734
5735	/**
5736	* Display the guest CpuId leaves.
5737	*
5738	* @param pVM Pointer to the VM.
5739	* @param pHlp The info helper functions.
5740	* @param pszArgs "terse", "default" or "verbose".
5741	*/
5742	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
5743	{
5744	/*
5745	* Parse the argument.
5746	*/
5747	unsigned iVerbosity = 1;
5748	if (pszArgs)
5749	{
5750	pszArgs = RTStrStripL(pszArgs);
5751	if (!strcmp(pszArgs, "terse"))
5752	iVerbosity--;
5753	else if (!strcmp(pszArgs, "verbose"))
5754	iVerbosity++;
5755	}
5756
5757	uint32_t uLeaf;
5758	CPUMCPUID Host;
5759	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
5760	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
5761	PCCPUMCPUIDLEAF pCurLeaf;
5762	PCCPUMCPUIDLEAF pNextLeaf;
5763	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
5764	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
5765	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
5766
5767	/*
5768	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
5769	*/
5770	uint32_t cHstMax = ASMCpuId_EAX(0);
5771	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
5772	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
5773	pHlp->pfnPrintf(pHlp,
5774	" Raw Standard CPUID Leaves\n"
5775	" Leaf/sub-leaf eax ebx ecx edx\n");
5776	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
5777	{
5778	uint32_t cMaxSubLeaves = 1;
5779	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
5780	cMaxSubLeaves = 16;
5781	else if (uLeaf == 0xd)
5782	cMaxSubLeaves = 128;
5783
5784	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5785	{
5786	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5787	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5788	&& pCurLeaf->uLeaf == uLeaf
5789	&& pCurLeaf->uSubLeaf == uSubLeaf)
5790	{
5791	pHlp->pfnPrintf(pHlp,
5792	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5793	"Hst: %08x %08x %08x %08x\n",
5794	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5795	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5796	pCurLeaf++;
5797	}
5798	else if ( uLeaf != 0xd
5799	\|\| uSubLeaf <= 1
5800	\|\| Host.uEbx != 0 )
5801	pHlp->pfnPrintf(pHlp,
5802	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5803	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5804
5805	/* Done? */
5806	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5807	\|\| pCurLeaf->uLeaf != uLeaf)
5808	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
5809	\|\| (uLeaf == 0x7 && Host.uEax == 0)
5810	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
5811	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
5812	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
5813	)
5814	)
5815	break;
5816	}
5817	}
5818	pNextLeaf = pCurLeaf;
5819
5820	/*
5821	* If verbose, decode it.
5822	*/
5823	if (iVerbosity && paLeaves[0].uLeaf == 0)
5824	pHlp->pfnPrintf(pHlp,
5825	"%36s %.04s%.04s%.04s\n"
5826	"%36s 0x00000000-%#010x\n"
5827	,
5828	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
5829	"Supports:", paLeaves[0].uEax);
5830
5831	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
5832	cpumR3CpuIdInfoStdLeaf1Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1, fIntel);
5833
5834	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
5835	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5836
5837	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
5838	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5839
5840	pCurLeaf = pNextLeaf;
5841
5842	/*
5843	* Hypervisor leaves.
5844	*
5845	* Unlike most of the other leaves reported, the guest hypervisor leaves
5846	* aren't a subset of the host CPUID bits.
5847	*/
5848	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
5849
5850	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5851	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
5852	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
5853	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
5854	cMax = RT_MAX(cHstMax, cGstMax);
5855	if (cMax >= UINT32_C(0x40000000))
5856	{
5857	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
5858
5859	/** @todo dump these in more detail. */
5860
5861	pCurLeaf = pNextLeaf;
5862	}
5863
5864
5865	/*
5866	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
5867	* Implemented after AMD specs.
5868	*/
5869	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
5870
5871	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5872	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
5873	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
5874	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
5875	cMax = RT_MAX(cHstMax, cGstMax);
5876	if (cMax >= UINT32_C(0x80000000))
5877	{
5878
5879	pHlp->pfnPrintf(pHlp,
5880	" Raw Extended CPUID Leaves\n"
5881	" Leaf/sub-leaf eax ebx ecx edx\n");
5882	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
5883	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
5884	{
5885	uint32_t cMaxSubLeaves = 1;
5886	if (uLeaf == UINT32_C(0x8000001d))
5887	cMaxSubLeaves = 16;
5888
5889	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5890	{
5891	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5892	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5893	&& pCurLeaf->uLeaf == uLeaf
5894	&& pCurLeaf->uSubLeaf == uSubLeaf)
5895	{
5896	pHlp->pfnPrintf(pHlp,
5897	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5898	"Hst: %08x %08x %08x %08x\n",
5899	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5900	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5901	pCurLeaf++;
5902	}
5903	else if ( uLeaf != 0xd
5904	\|\| uSubLeaf <= 1
5905	\|\| Host.uEbx != 0 )
5906	pHlp->pfnPrintf(pHlp,
5907	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5908	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5909
5910	/* Done? */
5911	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5912	\|\| pCurLeaf->uLeaf != uLeaf)
5913	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
5914	break;
5915	}
5916	}
5917	pNextLeaf = pCurLeaf;
5918
5919	/*
5920	* Understandable output
5921	*/
5922	if (iVerbosity)
5923	pHlp->pfnPrintf(pHlp,
5924	"Ext Name: %.4s%.4s%.4s\n"
5925	"Ext Supports: 0x80000000-%#010x\n",
5926	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
5927
5928	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
5929	if (iVerbosity && pCurLeaf)
5930	{
5931	uint32_t uEAX = pCurLeaf->uEax;
5932	pHlp->pfnPrintf(pHlp,
5933	"Family: %d \tExtended: %d \tEffective: %d\n"
5934	"Model: %d \tExtended: %d \tEffective: %d\n"
5935	"Stepping: %d\n"
5936	"Brand ID: %#05x\n",
5937	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
5938	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
5939	ASMGetCpuStepping(uEAX),
5940	pCurLeaf->uEbx & 0xfff);
5941
5942	if (iVerbosity == 1)
5943	{
5944	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
5945	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
5946	}
5947	else
5948	{
5949	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5950	pHlp->pfnPrintf(pHlp, "Ext Features\n");
5951	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5952	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
5953	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
5954	}
5955	}
5956
5957	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
5958	{
5959	char szString[443+1] = {0};
5960	uint32_t pu32 = (uint32_t )szString;
5961	*pu32++ = pCurLeaf->uEax;
5962	*pu32++ = pCurLeaf->uEbx;
5963	*pu32++ = pCurLeaf->uEcx;
5964	*pu32++ = pCurLeaf->uEdx;
5965	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
5966	if (pCurLeaf)
5967	{
5968	*pu32++ = pCurLeaf->uEax;
5969	*pu32++ = pCurLeaf->uEbx;
5970	*pu32++ = pCurLeaf->uEcx;
5971	*pu32++ = pCurLeaf->uEdx;
5972	}
5973	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
5974	if (pCurLeaf)
5975	{
5976	*pu32++ = pCurLeaf->uEax;
5977	*pu32++ = pCurLeaf->uEbx;
5978	*pu32++ = pCurLeaf->uEcx;
5979	*pu32++ = pCurLeaf->uEdx;
5980	}
5981	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
5982	}
5983
5984	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
5985	{
5986	uint32_t uEAX = pCurLeaf->uEax;
5987	uint32_t uEBX = pCurLeaf->uEbx;
5988	uint32_t uECX = pCurLeaf->uEcx;
5989	uint32_t uEDX = pCurLeaf->uEdx;
5990	char sz1[32];
5991	char sz2[32];
5992
5993	pHlp->pfnPrintf(pHlp,
5994	"TLB 2/4M Instr/Uni: %s %3d entries\n"
5995	"TLB 2/4M Data: %s %3d entries\n",
5996	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
5997	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
5998	pHlp->pfnPrintf(pHlp,
5999	"TLB 4K Instr/Uni: %s %3d entries\n"
6000	"TLB 4K Data: %s %3d entries\n",
6001	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6002	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6003	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6004	"L1 Instr Cache Lines Per Tag: %d\n"
6005	"L1 Instr Cache Associativity: %s\n"
6006	"L1 Instr Cache Size: %d KB\n",
6007	(uEDX >> 0) & 0xff,
6008	(uEDX >> 8) & 0xff,
6009	getCacheAss((uEDX >> 16) & 0xff, sz1),
6010	(uEDX >> 24) & 0xff);
6011	pHlp->pfnPrintf(pHlp,
6012	"L1 Data Cache Line Size: %d bytes\n"
6013	"L1 Data Cache Lines Per Tag: %d\n"
6014	"L1 Data Cache Associativity: %s\n"
6015	"L1 Data Cache Size: %d KB\n",
6016	(uECX >> 0) & 0xff,
6017	(uECX >> 8) & 0xff,
6018	getCacheAss((uECX >> 16) & 0xff, sz1),
6019	(uECX >> 24) & 0xff);
6020	}
6021
6022	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6023	{
6024	uint32_t uEAX = pCurLeaf->uEax;
6025	uint32_t uEBX = pCurLeaf->uEbx;
6026	uint32_t uEDX = pCurLeaf->uEdx;
6027
6028	pHlp->pfnPrintf(pHlp,
6029	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6030	"L2 TLB 2/4M Data: %s %4d entries\n",
6031	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6032	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6033	pHlp->pfnPrintf(pHlp,
6034	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6035	"L2 TLB 4K Data: %s %4d entries\n",
6036	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6037	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6038	pHlp->pfnPrintf(pHlp,
6039	"L2 Cache Line Size: %d bytes\n"
6040	"L2 Cache Lines Per Tag: %d\n"
6041	"L2 Cache Associativity: %s\n"
6042	"L2 Cache Size: %d KB\n",
6043	(uEDX >> 0) & 0xff,
6044	(uEDX >> 8) & 0xf,
6045	getL2CacheAss((uEDX >> 12) & 0xf),
6046	(uEDX >> 16) & 0xffff);
6047	}
6048
6049	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
6050	{
6051	uint32_t uEDX = pCurLeaf->uEdx;
6052
6053	pHlp->pfnPrintf(pHlp, "APM Features: ");
6054	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
6055	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
6056	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
6057	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
6058	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
6059	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
6060	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " MC");
6061	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " HWPSTATE");
6062	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TscInvariant");
6063	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " CPB");
6064	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " EffFreqRO");
6065	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PFI");
6066	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PA");
6067	for (unsigned iBit = 13; iBit < 32; iBit++)
6068	if (uEDX & RT_BIT(iBit))
6069	pHlp->pfnPrintf(pHlp, " %d", iBit);
6070	pHlp->pfnPrintf(pHlp, "\n");
6071
6072	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6073	pHlp->pfnPrintf(pHlp, "Host Invariant-TSC support: %RTbool\n",
6074	cHstMax >= UINT32_C(0x80000007) && (Host.uEdx & RT_BIT(8)));
6075
6076	}
6077
6078	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0)) != NULL)
6079	{
6080	uint32_t uEAX = pCurLeaf->uEax;
6081	uint32_t uECX = pCurLeaf->uEcx;
6082
6083	pHlp->pfnPrintf(pHlp,
6084	"Physical Address Width: %d bits\n"
6085	"Virtual Address Width: %d bits\n"
6086	"Guest Physical Address Width: %d bits\n",
6087	(uEAX >> 0) & 0xff,
6088	(uEAX >> 8) & 0xff,
6089	(uEAX >> 16) & 0xff);
6090	pHlp->pfnPrintf(pHlp,
6091	"Physical Core Count: %d\n",
6092	(uECX >> 0) & 0xff);
6093	}
6094
6095	pCurLeaf = pNextLeaf;
6096	}
6097
6098
6099
6100	/*
6101	* Centaur.
6102	*/
6103	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
6104
6105	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6106	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
6107	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
6108	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
6109	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
6110	cMax = RT_MAX(cHstMax, cGstMax);
6111	if (cMax >= UINT32_C(0xc0000000))
6112	{
6113	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
6114
6115	/*
6116	* Understandable output
6117	*/
6118	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
6119	pHlp->pfnPrintf(pHlp,
6120	"Centaur Supports: 0xc0000000-%#010x\n",
6121	pCurLeaf->uEax);
6122
6123	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
6124	{
6125	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6126	uint32_t uEdxGst = pCurLeaf->uEdx;
6127	uint32_t uEdxHst = Host.uEdx;
6128
6129	if (iVerbosity == 1)
6130	{
6131	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
6132	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
6133	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
6134	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
6135	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
6136	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
6137	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
6138	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
6139	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
6140	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6141	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
6142	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
6143	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
6144	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
6145	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
6146	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
6147	for (unsigned iBit = 14; iBit < 32; iBit++)
6148	if (uEdxGst & RT_BIT(iBit))
6149	pHlp->pfnPrintf(pHlp, " %d", iBit);
6150	pHlp->pfnPrintf(pHlp, "\n");
6151	}
6152	else
6153	{
6154	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
6155	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
6156	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
6157	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
6158	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
6159	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
6160	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
6161	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
6162	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
6163	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6164	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
6165	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
6166	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
6167	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
6168	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
6169	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
6170	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
6171	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
6172	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
6173	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
6174	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
6175	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
6176	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
6177	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
6178	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
6179	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
6180	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
6181	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
6182	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
6183	for (unsigned iBit = 27; iBit < 32; iBit++)
6184	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
6185	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
6186	pHlp->pfnPrintf(pHlp, "\n");
6187	}
6188	}
6189
6190	pCurLeaf = pNextLeaf;
6191	}
6192
6193	/*
6194	* The remainder.
6195	*/
6196	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
6197	}
6198
6199
6200
6201
6202
6203	/*
6204	*
6205	*
6206	* PATM interfaces.
6207	* PATM interfaces.
6208	* PATM interfaces.
6209	*
6210	*
6211	*/
6212
6213
6214	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
6215	/** @name Patchmanager CPUID legacy table APIs
6216	* @{
6217	*/
6218
6219	/**
6220	* Gets a pointer to the default CPUID leaf.
6221	*
6222	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
6223	* @param pVM Pointer to the VM.
6224	* @remark Intended for PATM only.
6225	*/
6226	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
6227	{
6228	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
6229	}
6230
6231
6232	/**
6233	* Gets a number of standard CPUID leaves (PATM only).
6234	*
6235	* @returns Number of leaves.
6236	* @param pVM Pointer to the VM.
6237	* @remark Intended for PATM - legacy, don't use in new code.
6238	*/
6239	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
6240	{
6241	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
6242	}
6243
6244
6245	/**
6246	* Gets a number of extended CPUID leaves (PATM only).
6247	*
6248	* @returns Number of leaves.
6249	* @param pVM Pointer to the VM.
6250	* @remark Intended for PATM - legacy, don't use in new code.
6251	*/
6252	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
6253	{
6254	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
6255	}
6256
6257
6258	/**
6259	* Gets a number of centaur CPUID leaves.
6260	*
6261	* @returns Number of leaves.
6262	* @param pVM Pointer to the VM.
6263	* @remark Intended for PATM - legacy, don't use in new code.
6264	*/
6265	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
6266	{
6267	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
6268	}
6269
6270
6271	/**
6272	* Gets a pointer to the array of standard CPUID leaves.
6273	*
6274	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
6275	*
6276	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
6277	* @param pVM Pointer to the VM.
6278	* @remark Intended for PATM - legacy, don't use in new code.
6279	*/
6280	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
6281	{
6282	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
6283	}
6284
6285
6286	/**
6287	* Gets a pointer to the array of extended CPUID leaves.
6288	*
6289	* CPUMGetGuestCpuIdExtMax() give the size of the array.
6290	*
6291	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
6292	* @param pVM Pointer to the VM.
6293	* @remark Intended for PATM - legacy, don't use in new code.
6294	*/
6295	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
6296	{
6297	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
6298	}
6299
6300
6301	/**
6302	* Gets a pointer to the array of centaur CPUID leaves.
6303	*
6304	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
6305	*
6306	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
6307	* @param pVM Pointer to the VM.
6308	* @remark Intended for PATM - legacy, don't use in new code.
6309	*/
6310	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
6311	{
6312	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
6313	}
6314
6315	/** @} */
6316	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
6317
6318	#endif /* VBOX_IN_VMM */
6319

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 56716

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