CPUMR3CpuId.cpp@ 57066

Last change on this file since 57066 was 57056, checked in by vboxsync, 10 years ago
cpumR3CpuIdSanitize: Log and clean up sub-leaves in the feature areas instead of freaking out with VERR_CPUM_IPE_2.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 292.3 KB

Line
1	/* $Id: CPUMR3CpuId.cpp 57056 2015-07-22 14:12:42Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_CPUM
22	#include <VBox/vmm/cpum.h>
23	#include <VBox/vmm/dbgf.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/vmm/ssm.h>
26	#include "CPUMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/vmm/mm.h>
29
30	#include <VBox/err.h>
31	#include <iprt/asm-amd64-x86.h>
32	#include <iprt/ctype.h>
33	#include <iprt/mem.h>
34	#include <iprt/string.h>
35
36
37	/*******************************************************************************
38	* Defined Constants And Macros *
39	*******************************************************************************/
40	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
41	#define CPUM_CPUID_MAX_LEAVES 2048
42	/* Max size we accept for the XSAVE area. */
43	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
44	/* Min size we accept for the XSAVE area. */
45	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
46
47
48	/*******************************************************************************
49	* Global Variables *
50	*******************************************************************************/
51	/**
52	* The intel pentium family.
53	*/
54	static const CPUMMICROARCH g_aenmIntelFamily06[] =
55	{
56	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
57	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
58	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
59	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
60	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
61	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
62	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
63	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
64	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
65	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
66	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
67	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
68	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
69	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
70	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
71	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
72	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
73	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
74	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
78	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
79	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
80	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
81	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
82	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
83	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
85	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
86	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
87	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
88	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
89	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
90	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
91	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
94	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
95	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
96	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
97	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
98	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
99	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
101	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
102	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
103	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
104	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
105	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
106	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
107	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
110	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
111	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
112	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
113	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
114	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
115	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
117	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
118	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
119	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
121	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
122	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
123	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
126	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
127	/* [71(0x47)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
129	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
130	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
131	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [79(0x4f)] = */ kCpumMicroarch_Intel_Unknown,
136	};
137
138
139
140	/**
141	* Figures out the (sub-)micro architecture given a bit of CPUID info.
142	*
143	* @returns Micro architecture.
144	* @param enmVendor The CPU vendor .
145	* @param bFamily The CPU family.
146	* @param bModel The CPU model.
147	* @param bStepping The CPU stepping.
148	*/
149	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
150	uint8_t bModel, uint8_t bStepping)
151	{
152	if (enmVendor == CPUMCPUVENDOR_AMD)
153	{
154	switch (bFamily)
155	{
156	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
157	case 0x03: return kCpumMicroarch_AMD_Am386;
158	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
159	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
160	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
161	case 0x06:
162	switch (bModel)
163	{
164	case 0: return kCpumMicroarch_AMD_K7_Palomino;
165	case 1: return kCpumMicroarch_AMD_K7_Palomino;
166	case 2: return kCpumMicroarch_AMD_K7_Palomino;
167	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
168	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
169	case 6: return kCpumMicroarch_AMD_K7_Palomino;
170	case 7: return kCpumMicroarch_AMD_K7_Morgan;
171	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
172	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
173	}
174	return kCpumMicroarch_AMD_K7_Unknown;
175	case 0x0f:
176	/*
177	* This family is a friggin mess. Trying my best to make some
178	* sense out of it. Too much happened in the 0x0f family to
179	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
180	*
181	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
182	* cpu-world.com, and other places:
183	* - 130nm:
184	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
185	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
186	* - Newcastle: FC0/DH-CG (errum #180: FE0/DH-CG), FF0/DH-CG
187	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
188	* - Odessa: FC0/DH-CG (errum #180: FE0/DH-CG)
189	* - Paris: FF0/DH-CG, FC0/DH-CG (errum #180: FE0/DH-CG),
190	* - 90nm:
191	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
192	* - Oakville: 10FC0/DH-D0.
193	* - Georgetown: 10FC0/DH-D0.
194	* - Sonora: 10FC0/DH-D0.
195	* - Venus: 20F71/SH-E4
196	* - Troy: 20F51/SH-E4
197	* - Athens: 20F51/SH-E4
198	* - San Diego: 20F71/SH-E4.
199	* - Lancaster: 20F42/SH-E5
200	* - Newark: 20F42/SH-E5.
201	* - Albany: 20FC2/DH-E6.
202	* - Roma: 20FC2/DH-E6.
203	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
204	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
205	* - 90nm introducing Dual core:
206	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
207	* - Italy: 20F10/JH-E1, 20F12/JH-E6
208	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
209	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
210	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
211	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
212	* - Santa Ana: 40F32/JH-F2, /-F3
213	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
214	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
215	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
216	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
217	* - Keene: 40FC2/DH-F2.
218	* - Richmond: 40FC2/DH-F2
219	* - Taylor: 40F82/BH-F2
220	* - Trinidad: 40F82/BH-F2
221	*
222	* - 65nm:
223	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
224	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
225	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
226	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
227	* - Sherman: /-G1, 70FC2/DH-G2.
228	* - Huron: 70FF2/DH-G2.
229	*/
230	if (bModel < 0x10)
231	return kCpumMicroarch_AMD_K8_130nm;
232	if (bModel >= 0x60 && bModel < 0x80)
233	return kCpumMicroarch_AMD_K8_65nm;
234	if (bModel >= 0x40)
235	return kCpumMicroarch_AMD_K8_90nm_AMDV;
236	switch (bModel)
237	{
238	case 0x21:
239	case 0x23:
240	case 0x2b:
241	case 0x2f:
242	case 0x37:
243	case 0x3f:
244	return kCpumMicroarch_AMD_K8_90nm_DualCore;
245	}
246	return kCpumMicroarch_AMD_K8_90nm;
247	case 0x10:
248	return kCpumMicroarch_AMD_K10;
249	case 0x11:
250	return kCpumMicroarch_AMD_K10_Lion;
251	case 0x12:
252	return kCpumMicroarch_AMD_K10_Llano;
253	case 0x14:
254	return kCpumMicroarch_AMD_Bobcat;
255	case 0x15:
256	switch (bModel)
257	{
258	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
259	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
260	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
261	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
262	case 0x11: /* ?? */
263	case 0x12: /* ?? */
264	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
265	}
266	return kCpumMicroarch_AMD_15h_Unknown;
267	case 0x16:
268	return kCpumMicroarch_AMD_Jaguar;
269
270	}
271	return kCpumMicroarch_AMD_Unknown;
272	}
273
274	if (enmVendor == CPUMCPUVENDOR_INTEL)
275	{
276	switch (bFamily)
277	{
278	case 3:
279	return kCpumMicroarch_Intel_80386;
280	case 4:
281	return kCpumMicroarch_Intel_80486;
282	case 5:
283	return kCpumMicroarch_Intel_P5;
284	case 6:
285	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
286	return g_aenmIntelFamily06[bModel];
287	return kCpumMicroarch_Intel_Atom_Unknown;
288	case 15:
289	switch (bModel)
290	{
291	case 0: return kCpumMicroarch_Intel_NB_Willamette;
292	case 1: return kCpumMicroarch_Intel_NB_Willamette;
293	case 2: return kCpumMicroarch_Intel_NB_Northwood;
294	case 3: return kCpumMicroarch_Intel_NB_Prescott;
295	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
296	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
297	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
298	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
299	default: return kCpumMicroarch_Intel_NB_Unknown;
300	}
301	break;
302	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
303	case 1:
304	return kCpumMicroarch_Intel_8086;
305	case 2:
306	return kCpumMicroarch_Intel_80286;
307	}
308	return kCpumMicroarch_Intel_Unknown;
309	}
310
311	if (enmVendor == CPUMCPUVENDOR_VIA)
312	{
313	switch (bFamily)
314	{
315	case 5:
316	switch (bModel)
317	{
318	case 1: return kCpumMicroarch_Centaur_C6;
319	case 4: return kCpumMicroarch_Centaur_C6;
320	case 8: return kCpumMicroarch_Centaur_C2;
321	case 9: return kCpumMicroarch_Centaur_C3;
322	}
323	break;
324
325	case 6:
326	switch (bModel)
327	{
328	case 5: return kCpumMicroarch_VIA_C3_M2;
329	case 6: return kCpumMicroarch_VIA_C3_C5A;
330	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
331	case 8: return kCpumMicroarch_VIA_C3_C5N;
332	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
333	case 10: return kCpumMicroarch_VIA_C7_C5J;
334	case 15: return kCpumMicroarch_VIA_Isaiah;
335	}
336	break;
337	}
338	return kCpumMicroarch_VIA_Unknown;
339	}
340
341	if (enmVendor == CPUMCPUVENDOR_CYRIX)
342	{
343	switch (bFamily)
344	{
345	case 4:
346	switch (bModel)
347	{
348	case 9: return kCpumMicroarch_Cyrix_5x86;
349	}
350	break;
351
352	case 5:
353	switch (bModel)
354	{
355	case 2: return kCpumMicroarch_Cyrix_M1;
356	case 4: return kCpumMicroarch_Cyrix_MediaGX;
357	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
358	}
359	break;
360
361	case 6:
362	switch (bModel)
363	{
364	case 0: return kCpumMicroarch_Cyrix_M2;
365	}
366	break;
367
368	}
369	return kCpumMicroarch_Cyrix_Unknown;
370	}
371
372	return kCpumMicroarch_Unknown;
373	}
374
375
376	/**
377	* Translates a microarchitecture enum value to the corresponding string
378	* constant.
379	*
380	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
381	* NULL if the value is invalid.
382	*
383	* @param enmMicroarch The enum value to convert.
384	*/
385	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
386	{
387	switch (enmMicroarch)
388	{
389	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
390	CASE_RET_STR(kCpumMicroarch_Intel_8086);
391	CASE_RET_STR(kCpumMicroarch_Intel_80186);
392	CASE_RET_STR(kCpumMicroarch_Intel_80286);
393	CASE_RET_STR(kCpumMicroarch_Intel_80386);
394	CASE_RET_STR(kCpumMicroarch_Intel_80486);
395	CASE_RET_STR(kCpumMicroarch_Intel_P5);
396
397	CASE_RET_STR(kCpumMicroarch_Intel_P6);
398	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
399	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
400
401	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
402	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
403	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
404
405	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
406	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
407
408	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
409	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
410	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
411	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
412	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
413	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
414	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
415	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Cannonlake);
416
417	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
418	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
419	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
420	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
421	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
422	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
423	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
424
425	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
426	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
427	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
428	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
429	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
430	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
431	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
432
433	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
434
435	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
436	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
437	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
438	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
439	CASE_RET_STR(kCpumMicroarch_AMD_K5);
440	CASE_RET_STR(kCpumMicroarch_AMD_K6);
441
442	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
443	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
444	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
445	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
446	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
447	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
448	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
449
450	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
451	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
452	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
453	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
454	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
455
456	CASE_RET_STR(kCpumMicroarch_AMD_K10);
457	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
458	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
459	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
460	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
461
462	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
463	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
464	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
465	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
466	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
467
468	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
469
470	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
471
472	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
473	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
474	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
475	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
476	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
477	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
478	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
479	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
480	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
481	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
482	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
483	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
484	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
485
486	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
487	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
488	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
489	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
490	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
491	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
492
493	CASE_RET_STR(kCpumMicroarch_Unknown);
494
495	#undef CASE_RET_STR
496	case kCpumMicroarch_Invalid:
497	case kCpumMicroarch_Intel_End:
498	case kCpumMicroarch_Intel_Core7_End:
499	case kCpumMicroarch_Intel_Atom_End:
500	case kCpumMicroarch_Intel_P6_Core_Atom_End:
501	case kCpumMicroarch_Intel_NB_End:
502	case kCpumMicroarch_AMD_K7_End:
503	case kCpumMicroarch_AMD_K8_End:
504	case kCpumMicroarch_AMD_15h_End:
505	case kCpumMicroarch_AMD_16h_End:
506	case kCpumMicroarch_AMD_End:
507	case kCpumMicroarch_VIA_End:
508	case kCpumMicroarch_Cyrix_End:
509	case kCpumMicroarch_32BitHack:
510	break;
511	/* no default! */
512	}
513
514	return NULL;
515	}
516
517
518
519	/**
520	* Gets a matching leaf in the CPUID leaf array.
521	*
522	* @returns Pointer to the matching leaf, or NULL if not found.
523	* @param paLeaves The CPUID leaves to search. This is sorted.
524	* @param cLeaves The number of leaves in the array.
525	* @param uLeaf The leaf to locate.
526	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
527	*/
528	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
529	{
530	/* Lazy bird does linear lookup here since this is only used for the
531	occational CPUID overrides. */
532	for (uint32_t i = 0; i < cLeaves; i++)
533	if ( paLeaves[i].uLeaf == uLeaf
534	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
535	return &paLeaves[i];
536	return NULL;
537	}
538
539
540	/**
541	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
542	*
543	* @returns true if found, false it not.
544	* @param paLeaves The CPUID leaves to search. This is sorted.
545	* @param cLeaves The number of leaves in the array.
546	* @param uLeaf The leaf to locate.
547	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
548	* @param pLegacy The legacy output leaf.
549	*/
550	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
551	PCPUMCPUID pLegacy)
552	{
553	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
554	if (pLeaf)
555	{
556	pLegacy->uEax = pLeaf->uEax;
557	pLegacy->uEbx = pLeaf->uEbx;
558	pLegacy->uEcx = pLeaf->uEcx;
559	pLegacy->uEdx = pLeaf->uEdx;
560	return true;
561	}
562	return false;
563	}
564
565
566	/**
567	* Ensures that the CPUID leaf array can hold one more leaf.
568	*
569	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
570	* failure.
571	* @param pVM Pointer to the VM, used as the heap selector. Passing
572	* NULL uses the host-context heap, otherwise the VM's
573	* hyper heap is used.
574	* @param ppaLeaves Pointer to the variable holding the array pointer
575	* (input/output).
576	* @param cLeaves The current array size.
577	*
578	* @remarks This function will automatically update the R0 and RC pointers when
579	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
580	* be the corresponding VM's CPUID arrays (which is asserted).
581	*/
582	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
583	{
584	/*
585	* If pVM is not specified, we're on the regular heap and can waste a
586	* little space to speed things up.
587	*/
588	uint32_t cAllocated;
589	if (!pVM)
590	{
591	cAllocated = RT_ALIGN(cLeaves, 16);
592	if (cLeaves + 1 > cAllocated)
593	{
594	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
595	if (pvNew)
596	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
597	else
598	{
599	RTMemFree(*ppaLeaves);
600	*ppaLeaves = NULL;
601	}
602	}
603	}
604	/*
605	* Otherwise, we're on the hyper heap and are probably just inserting
606	* one or two leaves and should conserve space.
607	*/
608	else
609	{
610	#ifdef IN_VBOX_CPU_REPORT
611	AssertReleaseFailed();
612	#else
613	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
614	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
615
616	size_t cb = cLeaves * sizeof(**ppaLeaves);
617	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
618	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
619	if (RT_SUCCESS(rc))
620	{
621	/* Update the R0 and RC pointers. */
622	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
623	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
624	}
625	else
626	{
627	*ppaLeaves = NULL;
628	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
629	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
630	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
631	}
632	#endif
633	}
634	return *ppaLeaves;
635	}
636
637
638	/**
639	* Append a CPUID leaf or sub-leaf.
640	*
641	* ASSUMES linear insertion order, so we'll won't need to do any searching or
642	* replace anything. Use cpumR3CpuIdInsert() for those cases.
643	*
644	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
645	* the caller need do no more work.
646	* @param ppaLeaves Pointer to the the pointer to the array of sorted
647	* CPUID leaves and sub-leaves.
648	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
649	* @param uLeaf The leaf we're adding.
650	* @param uSubLeaf The sub-leaf number.
651	* @param fSubLeafMask The sub-leaf mask.
652	* @param uEax The EAX value.
653	* @param uEbx The EBX value.
654	* @param uEcx The ECX value.
655	* @param uEdx The EDX value.
656	* @param fFlags The flags.
657	*/
658	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
659	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
660	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
661	{
662	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
663	return VERR_NO_MEMORY;
664
665	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
666	Assert( *pcLeaves == 0
667	\|\| pNew[-1].uLeaf < uLeaf
668	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
669
670	pNew->uLeaf = uLeaf;
671	pNew->uSubLeaf = uSubLeaf;
672	pNew->fSubLeafMask = fSubLeafMask;
673	pNew->uEax = uEax;
674	pNew->uEbx = uEbx;
675	pNew->uEcx = uEcx;
676	pNew->uEdx = uEdx;
677	pNew->fFlags = fFlags;
678
679	*pcLeaves += 1;
680	return VINF_SUCCESS;
681	}
682
683
684	/**
685	* Checks that we've updated the CPUID leaves array correctly.
686	*
687	* This is a no-op in non-strict builds.
688	*
689	* @param paLeaves The leaves array.
690	* @param cLeaves The number of leaves.
691	*/
692	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
693	{
694	#ifdef VBOX_STRICT
695	for (uint32_t i = 1; i < cLeaves; i++)
696	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
697	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
698	else
699	{
700	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
701	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
702	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
703	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
704	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
705	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
706	}
707	#else
708	NOREF(paLeaves);
709	NOREF(cLeaves);
710	#endif
711	}
712
713
714	/**
715	* Inserts a CPU ID leaf, replacing any existing ones.
716	*
717	* When inserting a simple leaf where we already got a series of sub-leaves with
718	* the same leaf number (eax), the simple leaf will replace the whole series.
719	*
720	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
721	* host-context heap and has only been allocated/reallocated by the
722	* cpumR3CpuIdEnsureSpace function.
723	*
724	* @returns VBox status code.
725	* @param pVM Pointer to the VM, used as the heap selector.
726	* Passing NULL uses the host-context heap, otherwise
727	* the VM's hyper heap is used.
728	* @param ppaLeaves Pointer to the the pointer to the array of sorted
729	* CPUID leaves and sub-leaves. Must be NULL if using
730	* the hyper heap.
731	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must be
732	* NULL if using the hyper heap.
733	* @param pNewLeaf Pointer to the data of the new leaf we're about to
734	* insert.
735	*/
736	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
737	{
738	/*
739	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
740	*/
741	if (pVM)
742	{
743	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
744	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
745
746	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
747	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
748	}
749
750	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
751	uint32_t cLeaves = *pcLeaves;
752
753	/*
754	* Validate the new leaf a little.
755	*/
756	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
757	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
758	VERR_INVALID_FLAGS);
759	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
760	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
761	VERR_INVALID_PARAMETER);
762	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
763	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
764	VERR_INVALID_PARAMETER);
765	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
766	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
767	VERR_INVALID_PARAMETER);
768
769	/*
770	* Find insertion point. The lazy bird uses the same excuse as in
771	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
772	*/
773	uint32_t i;
774	if ( cLeaves > 0
775	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
776	{
777	/* Add at end. */
778	i = cLeaves;
779	}
780	else if ( cLeaves > 0
781	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
782	{
783	/* Either replacing the last leaf or dealing with sub-leaves. Spool
784	back to the first sub-leaf to pretend we did the linear search. */
785	i = cLeaves - 1;
786	while ( i > 0
787	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
788	i--;
789	}
790	else
791	{
792	/* Linear search from the start. */
793	i = 0;
794	while ( i < cLeaves
795	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
796	i++;
797	}
798	if ( i < cLeaves
799	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
800	{
801	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
802	{
803	/*
804	* The sub-leaf mask differs, replace all existing leaves with the
805	* same leaf number.
806	*/
807	uint32_t c = 1;
808	while ( i + c < cLeaves
809	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
810	c++;
811	if (c > 1 && i + c < cLeaves)
812	{
813	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
814	*pcLeaves = cLeaves -= c - 1;
815	}
816
817	paLeaves[i] = *pNewLeaf;
818	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
819	return VINF_SUCCESS;
820	}
821
822	/* Find sub-leaf insertion point. */
823	while ( i < cLeaves
824	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
825	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
826	i++;
827
828	/*
829	* If we've got an exactly matching leaf, replace it.
830	*/
831	if ( i < cLeaves
832	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
833	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
834	{
835	paLeaves[i] = *pNewLeaf;
836	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
837	return VINF_SUCCESS;
838	}
839	}
840
841	/*
842	* Adding a new leaf at 'i'.
843	*/
844	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
845	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
846	if (!paLeaves)
847	return VERR_NO_MEMORY;
848
849	if (i < cLeaves)
850	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
851	*pcLeaves += 1;
852	paLeaves[i] = *pNewLeaf;
853
854	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
855	return VINF_SUCCESS;
856	}
857
858
859	/**
860	* Removes a range of CPUID leaves.
861	*
862	* This will not reallocate the array.
863	*
864	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
865	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
866	* @param uFirst The first leaf.
867	* @param uLast The last leaf.
868	*/
869	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
870	{
871	uint32_t cLeaves = *pcLeaves;
872
873	Assert(uFirst <= uLast);
874
875	/*
876	* Find the first one.
877	*/
878	uint32_t iFirst = 0;
879	while ( iFirst < cLeaves
880	&& paLeaves[iFirst].uLeaf < uFirst)
881	iFirst++;
882
883	/*
884	* Find the end (last + 1).
885	*/
886	uint32_t iEnd = iFirst;
887	while ( iEnd < cLeaves
888	&& paLeaves[iEnd].uLeaf <= uLast)
889	iEnd++;
890
891	/*
892	* Adjust the array if anything needs removing.
893	*/
894	if (iFirst < iEnd)
895	{
896	if (iEnd < cLeaves)
897	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
898	*pcLeaves = cLeaves -= (iEnd - iFirst);
899	}
900
901	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
902	}
903
904
905
906	/**
907	* Checks if ECX make a difference when reading a given CPUID leaf.
908	*
909	* @returns @c true if it does, @c false if it doesn't.
910	* @param uLeaf The leaf we're reading.
911	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
912	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
913	* final sub-leaf (for leaf 0xb only).
914	*/
915	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
916	{
917	*pfFinalEcxUnchanged = false;
918
919	uint32_t auCur[4];
920	uint32_t auPrev[4];
921	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
922
923	/* Look for sub-leaves. */
924	uint32_t uSubLeaf = 1;
925	for (;;)
926	{
927	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
928	if (memcmp(auCur, auPrev, sizeof(auCur)))
929	break;
930
931	/* Advance / give up. */
932	uSubLeaf++;
933	if (uSubLeaf >= 64)
934	{
935	*pcSubLeaves = 1;
936	return false;
937	}
938	}
939
940	/* Count sub-leaves. */
941	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
942	uint32_t cRepeats = 0;
943	uSubLeaf = 0;
944	for (;;)
945	{
946	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
947
948	/* Figuring out when to stop isn't entirely straight forward as we need
949	to cover undocumented behavior up to a point and implementation shortcuts. */
950
951	/* 1. Look for more than 4 repeating value sets. */
952	if ( auCur[0] == auPrev[0]
953	&& auCur[1] == auPrev[1]
954	&& ( auCur[2] == auPrev[2]
955	\|\| ( auCur[2] == uSubLeaf
956	&& auPrev[2] == uSubLeaf - 1) )
957	&& auCur[3] == auPrev[3])
958	{
959	if ( uLeaf != 0xd
960	\|\| uSubLeaf >= 64
961	\|\| ( auCur[0] == 0
962	&& auCur[1] == 0
963	&& auCur[2] == 0
964	&& auCur[3] == 0
965	&& auPrev[2] == 0) )
966	cRepeats++;
967	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
968	break;
969	}
970	else
971	cRepeats = 0;
972
973	/* 2. Look for zero values. */
974	if ( auCur[0] == 0
975	&& auCur[1] == 0
976	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
977	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
978	&& uSubLeaf >= cMinLeaves)
979	{
980	cRepeats = 0;
981	break;
982	}
983
984	/* 3. Leaf 0xb level type 0 check. */
985	if ( uLeaf == 0xb
986	&& (auCur[2] & 0xff00) == 0
987	&& (auPrev[2] & 0xff00) == 0)
988	{
989	cRepeats = 0;
990	break;
991	}
992
993	/* 99. Give up. */
994	if (uSubLeaf >= 128)
995	{
996	#ifndef IN_VBOX_CPU_REPORT
997	/* Ok, limit it according to the documentation if possible just to
998	avoid annoying users with these detection issues. */
999	uint32_t cDocLimit = UINT32_MAX;
1000	if (uLeaf == 0x4)
1001	cDocLimit = 4;
1002	else if (uLeaf == 0x7)
1003	cDocLimit = 1;
1004	else if (uLeaf == 0xd)
1005	cDocLimit = 63;
1006	else if (uLeaf == 0xf)
1007	cDocLimit = 2;
1008	if (cDocLimit != UINT32_MAX)
1009	{
1010	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1011	*pcSubLeaves = cDocLimit + 3;
1012	return true;
1013	}
1014	#endif
1015	*pcSubLeaves = UINT32_MAX;
1016	return true;
1017	}
1018
1019	/* Advance. */
1020	uSubLeaf++;
1021	memcpy(auPrev, auCur, sizeof(auCur));
1022	}
1023
1024	/* Standard exit. */
1025	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1026	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1027	if (*pcSubLeaves == 0)
1028	*pcSubLeaves = 1;
1029	return true;
1030	}
1031
1032
1033	/**
1034	* Gets a CPU ID leaf.
1035	*
1036	* @returns VBox status code.
1037	* @param pVM Pointer to the VM.
1038	* @param pLeaf Where to store the found leaf.
1039	* @param uLeaf The leaf to locate.
1040	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1041	*/
1042	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1043	{
1044	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1045	uLeaf, uSubLeaf);
1046	if (pcLeaf)
1047	{
1048	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1049	return VINF_SUCCESS;
1050	}
1051
1052	return VERR_NOT_FOUND;
1053	}
1054
1055
1056	/**
1057	* Inserts a CPU ID leaf, replacing any existing ones.
1058	*
1059	* @returns VBox status code.
1060	* @param pVM Pointer to the VM.
1061	* @param pNewLeaf Pointer to the leaf being inserted.
1062	*/
1063	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1064	{
1065	/*
1066	* Validate parameters.
1067	*/
1068	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1069	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1070
1071	/*
1072	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1073	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1074	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1075	*/
1076	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1077	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1078	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1079	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1080	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1081	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1082	{
1083	return VERR_NOT_SUPPORTED;
1084	}
1085
1086	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1087	}
1088
1089	/**
1090	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1091	*
1092	* @returns VBox status code.
1093	* @param ppaLeaves Where to return the array pointer on success.
1094	* Use RTMemFree to release.
1095	* @param pcLeaves Where to return the size of the array on
1096	* success.
1097	*/
1098	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1099	{
1100	*ppaLeaves = NULL;
1101	*pcLeaves = 0;
1102
1103	/*
1104	* Try out various candidates. This must be sorted!
1105	*/
1106	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1107	{
1108	{ UINT32_C(0x00000000), false },
1109	{ UINT32_C(0x10000000), false },
1110	{ UINT32_C(0x20000000), false },
1111	{ UINT32_C(0x30000000), false },
1112	{ UINT32_C(0x40000000), false },
1113	{ UINT32_C(0x50000000), false },
1114	{ UINT32_C(0x60000000), false },
1115	{ UINT32_C(0x70000000), false },
1116	{ UINT32_C(0x80000000), false },
1117	{ UINT32_C(0x80860000), false },
1118	{ UINT32_C(0x8ffffffe), true },
1119	{ UINT32_C(0x8fffffff), true },
1120	{ UINT32_C(0x90000000), false },
1121	{ UINT32_C(0xa0000000), false },
1122	{ UINT32_C(0xb0000000), false },
1123	{ UINT32_C(0xc0000000), false },
1124	{ UINT32_C(0xd0000000), false },
1125	{ UINT32_C(0xe0000000), false },
1126	{ UINT32_C(0xf0000000), false },
1127	};
1128
1129	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1130	{
1131	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1132	uint32_t uEax, uEbx, uEcx, uEdx;
1133	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1134
1135	/*
1136	* Does EAX look like a typical leaf count value?
1137	*/
1138	if ( uEax > uLeaf
1139	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1140	{
1141	/* Yes, dump them. */
1142	uint32_t cLeaves = uEax - uLeaf + 1;
1143	while (cLeaves-- > 0)
1144	{
1145	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1146
1147	uint32_t fFlags = 0;
1148
1149	/* There are currently three known leaves containing an APIC ID
1150	that needs EMT specific attention */
1151	if (uLeaf == 1)
1152	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1153	else if (uLeaf == 0xb && uEcx != 0)
1154	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1155	else if ( uLeaf == UINT32_C(0x8000001e)
1156	&& ( uEax
1157	\|\| uEbx
1158	\|\| uEdx
1159	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1160	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1161
1162
1163	/* Check three times here to reduce the chance of CPU migration
1164	resulting in false positives with things like the APIC ID. */
1165	uint32_t cSubLeaves;
1166	bool fFinalEcxUnchanged;
1167	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1168	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1169	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1170	{
1171	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1172	{
1173	/* This shouldn't happen. But in case it does, file all
1174	relevant details in the release log. */
1175	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1176	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1177	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1178	{
1179	uint32_t auTmp[4];
1180	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1181	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1182	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1183	}
1184	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1185	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1186	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1187	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1188	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1189	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1190	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1191	}
1192
1193	if (fFinalEcxUnchanged)
1194	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1195
1196	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1197	{
1198	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1199	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1200	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1201	if (RT_FAILURE(rc))
1202	return rc;
1203	}
1204	}
1205	else
1206	{
1207	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1208	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1209	if (RT_FAILURE(rc))
1210	return rc;
1211	}
1212
1213	/* next */
1214	uLeaf++;
1215	}
1216	}
1217	/*
1218	* Special CPUIDs needs special handling as they don't follow the
1219	* leaf count principle used above.
1220	*/
1221	else if (s_aCandidates[iOuter].fSpecial)
1222	{
1223	bool fKeep = false;
1224	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1225	fKeep = true;
1226	else if ( uLeaf == 0x8fffffff
1227	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1228	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1229	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1230	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1231	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1232	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1233	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1234	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1235	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1236	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1237	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1238	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1239	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1240	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1241	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1242	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1243	fKeep = true;
1244	if (fKeep)
1245	{
1246	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1247	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1248	if (RT_FAILURE(rc))
1249	return rc;
1250	}
1251	}
1252	}
1253
1254	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1255	return VINF_SUCCESS;
1256	}
1257
1258
1259	/**
1260	* Determines the method the CPU uses to handle unknown CPUID leaves.
1261	*
1262	* @returns VBox status code.
1263	* @param penmUnknownMethod Where to return the method.
1264	* @param pDefUnknown Where to return default unknown values. This
1265	* will be set, even if the resulting method
1266	* doesn't actually needs it.
1267	*/
1268	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1269	{
1270	uint32_t uLastStd = ASMCpuId_EAX(0);
1271	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1272	if (!ASMIsValidExtRange(uLastExt))
1273	uLastExt = 0x80000000;
1274
1275	uint32_t auChecks[] =
1276	{
1277	uLastStd + 1,
1278	uLastStd + 5,
1279	uLastStd + 8,
1280	uLastStd + 32,
1281	uLastStd + 251,
1282	uLastExt + 1,
1283	uLastExt + 8,
1284	uLastExt + 15,
1285	uLastExt + 63,
1286	uLastExt + 255,
1287	0x7fbbffcc,
1288	0x833f7872,
1289	0xefff2353,
1290	0x35779456,
1291	0x1ef6d33e,
1292	};
1293
1294	static const uint32_t s_auValues[] =
1295	{
1296	0xa95d2156,
1297	0x00000001,
1298	0x00000002,
1299	0x00000008,
1300	0x00000000,
1301	0x55773399,
1302	0x93401769,
1303	0x12039587,
1304	};
1305
1306	/*
1307	* Simple method, all zeros.
1308	*/
1309	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1310	pDefUnknown->uEax = 0;
1311	pDefUnknown->uEbx = 0;
1312	pDefUnknown->uEcx = 0;
1313	pDefUnknown->uEdx = 0;
1314
1315	/*
1316	* Intel has been observed returning the last standard leaf.
1317	*/
1318	uint32_t auLast[4];
1319	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1320
1321	uint32_t cChecks = RT_ELEMENTS(auChecks);
1322	while (cChecks > 0)
1323	{
1324	uint32_t auCur[4];
1325	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1326	if (memcmp(auCur, auLast, sizeof(auCur)))
1327	break;
1328	cChecks--;
1329	}
1330	if (cChecks == 0)
1331	{
1332	/* Now, what happens when the input changes? Esp. ECX. */
1333	uint32_t cTotal = 0;
1334	uint32_t cSame = 0;
1335	uint32_t cLastWithEcx = 0;
1336	uint32_t cNeither = 0;
1337	uint32_t cValues = RT_ELEMENTS(s_auValues);
1338	while (cValues > 0)
1339	{
1340	uint32_t uValue = s_auValues[cValues - 1];
1341	uint32_t auLastWithEcx[4];
1342	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1343	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1344
1345	cChecks = RT_ELEMENTS(auChecks);
1346	while (cChecks > 0)
1347	{
1348	uint32_t auCur[4];
1349	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1350	if (!memcmp(auCur, auLast, sizeof(auCur)))
1351	{
1352	cSame++;
1353	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1354	cLastWithEcx++;
1355	}
1356	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1357	cLastWithEcx++;
1358	else
1359	cNeither++;
1360	cTotal++;
1361	cChecks--;
1362	}
1363	cValues--;
1364	}
1365
1366	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1367	if (cSame == cTotal)
1368	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1369	else if (cLastWithEcx == cTotal)
1370	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1371	else
1372	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1373	pDefUnknown->uEax = auLast[0];
1374	pDefUnknown->uEbx = auLast[1];
1375	pDefUnknown->uEcx = auLast[2];
1376	pDefUnknown->uEdx = auLast[3];
1377	return VINF_SUCCESS;
1378	}
1379
1380	/*
1381	* Unchanged register values?
1382	*/
1383	cChecks = RT_ELEMENTS(auChecks);
1384	while (cChecks > 0)
1385	{
1386	uint32_t const uLeaf = auChecks[cChecks - 1];
1387	uint32_t cValues = RT_ELEMENTS(s_auValues);
1388	while (cValues > 0)
1389	{
1390	uint32_t uValue = s_auValues[cValues - 1];
1391	uint32_t auCur[4];
1392	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1393	if ( auCur[0] != uLeaf
1394	\|\| auCur[1] != uValue
1395	\|\| auCur[2] != uValue
1396	\|\| auCur[3] != uValue)
1397	break;
1398	cValues--;
1399	}
1400	if (cValues != 0)
1401	break;
1402	cChecks--;
1403	}
1404	if (cChecks == 0)
1405	{
1406	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1407	return VINF_SUCCESS;
1408	}
1409
1410	/*
1411	* Just go with the simple method.
1412	*/
1413	return VINF_SUCCESS;
1414	}
1415
1416
1417	/**
1418	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1419	*
1420	* @returns Read only name string.
1421	* @param enmUnknownMethod The method to translate.
1422	*/
1423	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1424	{
1425	switch (enmUnknownMethod)
1426	{
1427	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1428	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1429	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1430	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1431
1432	case CPUMUNKNOWNCPUID_INVALID:
1433	case CPUMUNKNOWNCPUID_END:
1434	case CPUMUNKNOWNCPUID_32BIT_HACK:
1435	break;
1436	}
1437	return "Invalid-unknown-CPUID-method";
1438	}
1439
1440
1441	/**
1442	* Detect the CPU vendor give n the
1443	*
1444	* @returns The vendor.
1445	* @param uEAX EAX from CPUID(0).
1446	* @param uEBX EBX from CPUID(0).
1447	* @param uECX ECX from CPUID(0).
1448	* @param uEDX EDX from CPUID(0).
1449	*/
1450	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1451	{
1452	if (ASMIsValidStdRange(uEAX))
1453	{
1454	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1455	return CPUMCPUVENDOR_AMD;
1456
1457	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1458	return CPUMCPUVENDOR_INTEL;
1459
1460	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1461	return CPUMCPUVENDOR_VIA;
1462
1463	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1464	&& uECX == UINT32_C(0x64616574)
1465	&& uEDX == UINT32_C(0x736E4978))
1466	return CPUMCPUVENDOR_CYRIX;
1467
1468	/* "Geode by NSC", example: family 5, model 9. */
1469
1470	/** @todo detect the other buggers... */
1471	}
1472
1473	return CPUMCPUVENDOR_UNKNOWN;
1474	}
1475
1476
1477	/**
1478	* Translates a CPU vendor enum value into the corresponding string constant.
1479	*
1480	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1481	* value name. This can be useful when generating code.
1482	*
1483	* @returns Read only name string.
1484	* @param enmVendor The CPU vendor value.
1485	*/
1486	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1487	{
1488	switch (enmVendor)
1489	{
1490	case CPUMCPUVENDOR_INTEL: return "INTEL";
1491	case CPUMCPUVENDOR_AMD: return "AMD";
1492	case CPUMCPUVENDOR_VIA: return "VIA";
1493	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1494	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1495
1496	case CPUMCPUVENDOR_INVALID:
1497	case CPUMCPUVENDOR_32BIT_HACK:
1498	break;
1499	}
1500	return "Invalid-cpu-vendor";
1501	}
1502
1503
1504	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1505	{
1506	/* Could do binary search, doing linear now because I'm lazy. */
1507	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1508	while (cLeaves-- > 0)
1509	{
1510	if (pLeaf->uLeaf == uLeaf)
1511	return pLeaf;
1512	pLeaf++;
1513	}
1514	return NULL;
1515	}
1516
1517
1518	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1519	{
1520	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1521	if ( !pLeaf
1522	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1523	return pLeaf;
1524
1525	/* Linear sub-leaf search. Lazy as usual. */
1526	cLeaves -= pLeaf - paLeaves;
1527	while ( cLeaves-- > 0
1528	&& pLeaf->uLeaf == uLeaf)
1529	{
1530	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1531	return pLeaf;
1532	pLeaf++;
1533	}
1534
1535	return NULL;
1536	}
1537
1538
1539	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1540	{
1541	RT_ZERO(*pFeatures);
1542	if (cLeaves >= 2)
1543	{
1544	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1545	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1546	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1547	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1548	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1549	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1550
1551	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1552	pStd0Leaf->uEbx,
1553	pStd0Leaf->uEcx,
1554	pStd0Leaf->uEdx);
1555	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1556	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1557	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1558	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1559	pFeatures->uFamily,
1560	pFeatures->uModel,
1561	pFeatures->uStepping);
1562
1563	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1564	if (pLeaf)
1565	pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff;
1566	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1567	pFeatures->cMaxPhysAddrWidth = 36;
1568	else
1569	pFeatures->cMaxPhysAddrWidth = 32;
1570
1571	/* Standard features. */
1572	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1573	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1574	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1575	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1576	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1577	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1578	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1579	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1580	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1581	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1582	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1583	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1584	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1585	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1586	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1587	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1588	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1589	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1590	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1591	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1592	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1593	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1594
1595	/* Structured extended features. */
1596	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1597	if (pSxfLeaf0)
1598	{
1599	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEcx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1600	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEcx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1601	}
1602
1603	/* MWAIT/MONITOR leaf. */
1604	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1605	if (pMWaitLeaf)
1606	{
1607	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1608	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1609	}
1610
1611	/* Extended features. */
1612	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1613	if (pExtLeaf)
1614	{
1615	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1616	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1617	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1618	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1619	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1620	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1621	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1622	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1623	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1624	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1625	}
1626
1627	if ( pExtLeaf
1628	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1629	{
1630	/* AMD features. */
1631	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1632	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1633	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1634	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1635	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1636	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1637	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1638	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1639	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1640	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1641	}
1642
1643	/*
1644	* Quirks.
1645	*/
1646	pFeatures->fLeakyFxSR = pExtLeaf
1647	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1648	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1649	&& pFeatures->uFamily >= 6 /* K7 and up */;
1650
1651	/*
1652	* Max extended (/FPU) state.
1653	*/
1654	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1655	if (pFeatures->fXSaveRstor)
1656	{
1657	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1658	if (pXStateLeaf0)
1659	{
1660	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1661	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1662	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1663	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1664	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1665	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1666	{
1667	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1668
1669	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1670	if ( pXStateLeaf1
1671	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1672	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1673	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1674	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEbx;
1675	}
1676	else
1677	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1678	pFeatures->fXSaveRstor = 0);
1679	}
1680	else
1681	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1682	pFeatures->fXSaveRstor = 0);
1683	}
1684	}
1685	else
1686	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1687	return VINF_SUCCESS;
1688	}
1689
1690
1691	/*
1692	*
1693	* Init related code.
1694	* Init related code.
1695	* Init related code.
1696	*
1697	*
1698	*/
1699	#ifdef VBOX_IN_VMM
1700
1701
1702	/**
1703	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1704	*
1705	* This ignores the fSubLeafMask.
1706	*
1707	* @returns Pointer to the matching leaf, or NULL if not found.
1708	* @param paLeaves The CPUID leaves to search. This is sorted.
1709	* @param cLeaves The number of leaves in the array.
1710	* @param uLeaf The leaf to locate.
1711	* @param uSubLeaf The subleaf to locate.
1712	*/
1713	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1714	{
1715	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1716	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1717	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1718	if (iEnd)
1719	{
1720	uint32_t iBegin = 0;
1721	for (;;)
1722	{
1723	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1724	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1725	if (uNeedle < uCur)
1726	{
1727	if (i > iBegin)
1728	iEnd = i;
1729	else
1730	break;
1731	}
1732	else if (uNeedle > uCur)
1733	{
1734	if (i + 1 < iEnd)
1735	iBegin = i + 1;
1736	else
1737	break;
1738	}
1739	else
1740	return &paLeaves[i];
1741	}
1742	}
1743	return NULL;
1744	}
1745
1746
1747	/**
1748	* Loads MSR range overrides.
1749	*
1750	* This must be called before the MSR ranges are moved from the normal heap to
1751	* the hyper heap!
1752	*
1753	* @returns VBox status code (VMSetError called).
1754	* @param pVM Pointer to the cross context VM structure
1755	* @param pMsrNode The CFGM node with the MSR overrides.
1756	*/
1757	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1758	{
1759	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1760	{
1761	/*
1762	* Assemble a valid MSR range.
1763	*/
1764	CPUMMSRRANGE MsrRange;
1765	MsrRange.offCpumCpu = 0;
1766	MsrRange.fReserved = 0;
1767
1768	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1769	if (RT_FAILURE(rc))
1770	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1771
1772	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1773	if (RT_FAILURE(rc))
1774	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1775	MsrRange.szName, rc);
1776
1777	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1778	if (RT_FAILURE(rc))
1779	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1780	MsrRange.szName, rc);
1781
1782	char szType[32];
1783	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1784	if (RT_FAILURE(rc))
1785	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1786	MsrRange.szName, rc);
1787	if (!RTStrICmp(szType, "FixedValue"))
1788	{
1789	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1790	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1791
1792	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1793	if (RT_FAILURE(rc))
1794	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1795	MsrRange.szName, rc);
1796
1797	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1798	if (RT_FAILURE(rc))
1799	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1800	MsrRange.szName, rc);
1801
1802	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1803	if (RT_FAILURE(rc))
1804	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1805	MsrRange.szName, rc);
1806	}
1807	else
1808	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1809	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1810
1811	/*
1812	* Insert the range into the table (replaces/splits/shrinks existing
1813	* MSR ranges).
1814	*/
1815	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1816	&MsrRange);
1817	if (RT_FAILURE(rc))
1818	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
1819	}
1820
1821	return VINF_SUCCESS;
1822	}
1823
1824
1825	/**
1826	* Loads CPUID leaf overrides.
1827	*
1828	* This must be called before the CPUID leaves are moved from the normal
1829	* heap to the hyper heap!
1830	*
1831	* @returns VBox status code (VMSetError called).
1832	* @param pVM Pointer to the cross context VM structure
1833	* @param pParentNode The CFGM node with the CPUID leaves.
1834	* @param pszLabel How to label the overrides we're loading.
1835	*/
1836	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
1837	{
1838	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1839	{
1840	/*
1841	* Get the leaf and subleaf numbers.
1842	*/
1843	char szName[128];
1844	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
1845	if (RT_FAILURE(rc))
1846	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
1847
1848	/* The leaf number is either specified directly or thru the node name. */
1849	uint32_t uLeaf;
1850	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
1851	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1852	{
1853	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
1854	if (rc != VINF_SUCCESS)
1855	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
1856	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
1857	}
1858	else if (RT_FAILURE(rc))
1859	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
1860	pszLabel, szName, rc);
1861
1862	uint32_t uSubLeaf;
1863	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
1864	if (RT_FAILURE(rc))
1865	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
1866	pszLabel, szName, rc);
1867
1868	uint32_t fSubLeafMask;
1869	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
1870	if (RT_FAILURE(rc))
1871	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
1872	pszLabel, szName, rc);
1873
1874	/*
1875	* Look up the specified leaf, since the output register values
1876	* defaults to any existing values. This allows overriding a single
1877	* register, without needing to know the other values.
1878	*/
1879	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
1880	CPUMCPUIDLEAF Leaf;
1881	if (pLeaf)
1882	Leaf = *pLeaf;
1883	else
1884	RT_ZERO(Leaf);
1885	Leaf.uLeaf = uLeaf;
1886	Leaf.uSubLeaf = uSubLeaf;
1887	Leaf.fSubLeafMask = fSubLeafMask;
1888
1889	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
1890	if (RT_FAILURE(rc))
1891	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
1892	pszLabel, szName, rc);
1893	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
1894	if (RT_FAILURE(rc))
1895	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
1896	pszLabel, szName, rc);
1897	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
1898	if (RT_FAILURE(rc))
1899	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
1900	pszLabel, szName, rc);
1901	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
1902	if (RT_FAILURE(rc))
1903	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
1904	pszLabel, szName, rc);
1905
1906	/*
1907	* Insert the leaf into the table (replaces existing ones).
1908	*/
1909	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1910	&Leaf);
1911	if (RT_FAILURE(rc))
1912	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
1913	}
1914
1915	return VINF_SUCCESS;
1916	}
1917
1918
1919
1920	/**
1921	* Fetches overrides for a CPUID leaf.
1922	*
1923	* @returns VBox status code.
1924	* @param pLeaf The leaf to load the overrides into.
1925	* @param pCfgNode The CFGM node containing the overrides
1926	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
1927	* @param iLeaf The CPUID leaf number.
1928	*/
1929	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
1930	{
1931	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
1932	if (pLeafNode)
1933	{
1934	uint32_t u32;
1935	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
1936	if (RT_SUCCESS(rc))
1937	pLeaf->uEax = u32;
1938	else
1939	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1940
1941	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
1942	if (RT_SUCCESS(rc))
1943	pLeaf->uEbx = u32;
1944	else
1945	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1946
1947	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
1948	if (RT_SUCCESS(rc))
1949	pLeaf->uEcx = u32;
1950	else
1951	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1952
1953	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
1954	if (RT_SUCCESS(rc))
1955	pLeaf->uEdx = u32;
1956	else
1957	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1958
1959	}
1960	return VINF_SUCCESS;
1961	}
1962
1963
1964	/**
1965	* Load the overrides for a set of CPUID leaves.
1966	*
1967	* @returns VBox status code.
1968	* @param paLeaves The leaf array.
1969	* @param cLeaves The number of leaves.
1970	* @param uStart The start leaf number.
1971	* @param pCfgNode The CFGM node containing the overrides
1972	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
1973	*/
1974	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
1975	{
1976	for (uint32_t i = 0; i < cLeaves; i++)
1977	{
1978	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
1979	if (RT_FAILURE(rc))
1980	return rc;
1981	}
1982
1983	return VINF_SUCCESS;
1984	}
1985
1986	/**
1987	* Init a set of host CPUID leaves.
1988	*
1989	* @returns VBox status code.
1990	* @param paLeaves The leaf array.
1991	* @param cLeaves The number of leaves.
1992	* @param uStart The start leaf number.
1993	* @param pCfgNode The /CPUM/HostCPUID/ node.
1994	*/
1995	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
1996	{
1997	/* Using the ECX variant for all of them can't hurt... */
1998	for (uint32_t i = 0; i < cLeaves; i++)
1999	ASMCpuIdExSlow(uStart + i, 0, 0, 0, &paLeaves[i].uEax, &paLeaves[i].uEbx, &paLeaves[i].uEcx, &paLeaves[i].uEdx);
2000
2001	/* Load CPUID leaf override; we currently don't care if the user
2002	specifies features the host CPU doesn't support. */
2003	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
2004	}
2005
2006
2007	/**
2008	* Installs the CPUID leaves and explods the data into structures like
2009	* GuestFeatures and CPUMCTX::aoffXState.
2010	*
2011	* @returns VBox status code.
2012	* @param pVM The cross context VM handle.
2013	* @param pCpum The CPUM part of @a VM.
2014	* @param paLeaves The leaves. These will be copied (but not freed).
2015	* @param cLeaves The number of leaves.
2016	*/
2017	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
2018	{
2019	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2020
2021	/*
2022	* Install the CPUID information.
2023	*/
2024	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2025	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2026
2027	AssertLogRelRCReturn(rc, rc);
2028	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2029	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2030	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2031	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2032	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2033
2034	/*
2035	* Update the default CPUID leaf if necessary.
2036	*/
2037	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2038	{
2039	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2040	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2041	{
2042	/* We don't use CPUID(0).eax here because of the NT hack that only
2043	changes that value without actually removing any leaves. */
2044	uint32_t i = 0;
2045	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2046	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2047	{
2048	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2049	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2050	i++;
2051	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2052	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2053	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2054	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2055	}
2056	break;
2057	}
2058	default:
2059	break;
2060	}
2061
2062	/*
2063	* Explode the guest CPU features.
2064	*/
2065	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
2066	AssertLogRelRCReturn(rc, rc);
2067
2068	/*
2069	* Adjust the scalable bus frequency according to the CPUID information
2070	* we're now using.
2071	*/
2072	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2073	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2074	? UINT64_C(100000000) /* 100MHz */
2075	: UINT64_C(133333333); /* 133MHz */
2076
2077	/*
2078	* Populate the legacy arrays. Currently used for everything, later only
2079	* for patch manager.
2080	*/
2081	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2082	{
2083	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2084	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2085	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2086	};
2087	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2088	{
2089	uint32_t cLeft = aOldRanges[i].cCpuIds;
2090	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2091	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2092	while (cLeft-- > 0)
2093	{
2094	uLeaf--;
2095	pLegacyLeaf--;
2096
2097	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2098	if (pLeaf)
2099	{
2100	pLegacyLeaf->uEax = pLeaf->uEax;
2101	pLegacyLeaf->uEbx = pLeaf->uEbx;
2102	pLegacyLeaf->uEcx = pLeaf->uEcx;
2103	pLegacyLeaf->uEdx = pLeaf->uEdx;
2104	}
2105	else
2106	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2107	}
2108	}
2109
2110	/*
2111	* Configure XSAVE offsets according to the CPUID info.
2112	*/
2113	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2114	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2115	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2116	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2117	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2118	{
2119	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2120	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2121	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2122	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2123	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2124	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2125	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2126	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2127	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2128	pCpum->GuestFeatures.cbMaxExtendedState),
2129	VERR_CPUM_IPE_1);
2130	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2131	}
2132	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2133
2134	/* Copy the CPU #0 data to the other CPUs. */
2135	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2136	{
2137	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2138	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2139	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2140	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2141	}
2142
2143	return VINF_SUCCESS;
2144	}
2145
2146
2147	/** @name Instruction Set Extension Options
2148	* @{ */
2149	/** Configuration option type (extended boolean, really). */
2150	typedef uint8_t CPUMISAEXTCFG;
2151	/** Always disable the extension. */
2152	#define CPUMISAEXTCFG_DISABLED false
2153	/** Enable the extension if it's supported by the host CPU. */
2154	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2155	/** Enable the extension if it's supported by the host CPU, but don't let
2156	* the portable CPUID feature disable it. */
2157	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2158	/** Always enable the extension. */
2159	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2160	/** @} */
2161
2162	/**
2163	* CPUID Configuration (from CFGM).
2164	*
2165	* @remarks The members aren't document since we would only be duplicating the
2166	* \@cfgm entries in cpumR3CpuIdReadConfig.
2167	*/
2168	typedef struct CPUMCPUIDCONFIG
2169	{
2170	bool fNt4LeafLimit;
2171	bool fInvariantTsc;
2172
2173	CPUMISAEXTCFG enmCmpXchg16b;
2174	CPUMISAEXTCFG enmMonitor;
2175	CPUMISAEXTCFG enmMWaitExtensions;
2176	CPUMISAEXTCFG enmSse41;
2177	CPUMISAEXTCFG enmSse42;
2178	CPUMISAEXTCFG enmAvx;
2179	CPUMISAEXTCFG enmAvx2;
2180	CPUMISAEXTCFG enmXSave;
2181	CPUMISAEXTCFG enmAesNi;
2182	CPUMISAEXTCFG enmPClMul;
2183	CPUMISAEXTCFG enmPopCnt;
2184	CPUMISAEXTCFG enmMovBe;
2185	CPUMISAEXTCFG enmRdRand;
2186	CPUMISAEXTCFG enmRdSeed;
2187	CPUMISAEXTCFG enmCLFlushOpt;
2188
2189	CPUMISAEXTCFG enmAbm;
2190	CPUMISAEXTCFG enmSse4A;
2191	CPUMISAEXTCFG enmMisAlnSse;
2192	CPUMISAEXTCFG enm3dNowPrf;
2193	CPUMISAEXTCFG enmAmdExtMmx;
2194
2195	uint32_t uMaxStdLeaf;
2196	uint32_t uMaxExtLeaf;
2197	uint32_t uMaxCentaurLeaf;
2198	uint32_t uMaxIntelFamilyModelStep;
2199	char szCpuName[128];
2200	} CPUMCPUIDCONFIG;
2201	/** Pointer to CPUID config (from CFGM). */
2202	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2203
2204
2205	/**
2206	* Insert hypervisor identification leaves.
2207	*
2208	* We only return minimal information, primarily ensuring that the
2209	* 0x40000000 function returns 0x40000001 and identifying ourselves.
2210	* Hypervisor-specific interface is supported through GIM which will
2211	* modify these leaves if required depending on the GIM provider.
2212	*
2213	* @returns VBox status code.
2214	* @param pCpum The CPUM instance data.
2215	* @param pConfig The CPUID configuration we've read from CFGM.
2216	*/
2217	static int cpumR3CpuIdPlantHypervisorLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2218	{
2219	CPUMCPUIDLEAF NewLeaf;
2220	NewLeaf.uLeaf = UINT32_C(0x40000000);
2221	NewLeaf.uSubLeaf = 0;
2222	NewLeaf.fSubLeafMask = 0;
2223	NewLeaf.uEax = UINT32_C(0x40000001);
2224	NewLeaf.uEbx = 0x786f4256 /* 'VBox' */;
2225	NewLeaf.uEcx = 0x786f4256 /* 'VBox' */;
2226	NewLeaf.uEdx = 0x786f4256 /* 'VBox' */;
2227	NewLeaf.fFlags = 0;
2228	int rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
2229	AssertLogRelRCReturn(rc, rc);
2230
2231	NewLeaf.uLeaf = UINT32_C(0x40000001);
2232	NewLeaf.uEax = 0x656e6f6e; /* 'none' */
2233	NewLeaf.uEbx = 0;
2234	NewLeaf.uEcx = 0;
2235	NewLeaf.uEdx = 0;
2236	NewLeaf.fFlags = 0;
2237	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
2238	AssertLogRelRCReturn(rc, rc);
2239
2240	return VINF_SUCCESS;
2241	}
2242
2243
2244	/**
2245	* Mini CPU selection support for making Mac OS X happy.
2246	*
2247	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2248	*
2249	* @param pCpum The CPUM instance data.
2250	* @param pConfig The CPUID configuration we've read from CFGM.
2251	*/
2252	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2253	{
2254	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2255	{
2256	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2257	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2258	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2259	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2260	0);
2261	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2262	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2263	{
2264	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2265	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2266	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2267	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2268	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2269	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2270	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2271	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2272	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2273	pStdFeatureLeaf->uEax = uNew;
2274	}
2275	}
2276	}
2277
2278
2279
2280	/**
2281	* Limit it the number of entries, zapping the remainder.
2282	*
2283	* The limits are masking off stuff about power saving and similar, this
2284	* is perhaps a bit crudely done as there is probably some relatively harmless
2285	* info too in these leaves (like words about having a constant TSC).
2286	*
2287	* @param pCpum The CPUM instance data.
2288	* @param pConfig The CPUID configuration we've read from CFGM.
2289	*/
2290	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2291	{
2292	/*
2293	* Standard leaves.
2294	*/
2295	uint32_t uSubLeaf = 0;
2296	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2297	if (pCurLeaf)
2298	{
2299	uint32_t uLimit = pCurLeaf->uEax;
2300	if (uLimit <= UINT32_C(0x000fffff))
2301	{
2302	if (uLimit > pConfig->uMaxStdLeaf)
2303	{
2304	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2305	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2306	uLimit + 1, UINT32_C(0x000fffff));
2307	}
2308
2309	/* NT4 hack, no zapping of extra leaves here. */
2310	if (pConfig->fNt4LeafLimit && uLimit > 3)
2311	pCurLeaf->uEax = uLimit = 3;
2312
2313	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2314	pCurLeaf->uEax = uLimit;
2315	}
2316	else
2317	{
2318	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2319	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2320	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2321	}
2322	}
2323
2324	/*
2325	* Extended leaves.
2326	*/
2327	uSubLeaf = 0;
2328	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2329	if (pCurLeaf)
2330	{
2331	uint32_t uLimit = pCurLeaf->uEax;
2332	if ( uLimit >= UINT32_C(0x80000000)
2333	&& uLimit <= UINT32_C(0x800fffff))
2334	{
2335	if (uLimit > pConfig->uMaxExtLeaf)
2336	{
2337	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2338	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2339	uLimit + 1, UINT32_C(0x800fffff));
2340	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2341	pCurLeaf->uEax = uLimit;
2342	}
2343	}
2344	else
2345	{
2346	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2347	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2348	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2349	}
2350	}
2351
2352	/*
2353	* Centaur leaves (VIA).
2354	*/
2355	uSubLeaf = 0;
2356	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2357	if (pCurLeaf)
2358	{
2359	uint32_t uLimit = pCurLeaf->uEax;
2360	if ( uLimit >= UINT32_C(0xc0000000)
2361	&& uLimit <= UINT32_C(0xc00fffff))
2362	{
2363	if (uLimit > pConfig->uMaxCentaurLeaf)
2364	{
2365	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2366	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2367	uLimit + 1, UINT32_C(0xcfffffff));
2368	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2369	pCurLeaf->uEax = uLimit;
2370	}
2371	}
2372	else
2373	{
2374	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2375	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2376	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2377	}
2378	}
2379	}
2380
2381
2382	/**
2383	* Clears a CPUID leaf and all sub-leaves (to zero).
2384	*
2385	* @param pCpum The CPUM instance data.
2386	* @param uLeaf The leaf to clear.
2387	*/
2388	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2389	{
2390	uint32_t uSubLeaf = 0;
2391	PCPUMCPUIDLEAF pCurLeaf;
2392	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2393	{
2394	pCurLeaf->uEax = 0;
2395	pCurLeaf->uEbx = 0;
2396	pCurLeaf->uEcx = 0;
2397	pCurLeaf->uEdx = 0;
2398	uSubLeaf++;
2399	}
2400	}
2401
2402
2403	/**
2404	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2405	* the given leaf.
2406	*
2407	* @returns pLeaf.
2408	* @param pCpum The CPUM instance data.
2409	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2410	*/
2411	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2412	{
2413	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2414	if (pLeaf->fSubLeafMask != 0)
2415	{
2416	/*
2417	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2418	* Log everything while we're at it.
2419	*/
2420	LogRel(("CPUM:\n"
2421	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2422	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2423	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2424	for (;;)
2425	{
2426	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2427	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2428	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2429	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2430	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2431	break;
2432	pSubLeaf++;
2433	}
2434	LogRel(("CPUM:\n"));
2435
2436	/*
2437	* Remove the offending sub-leaves.
2438	*/
2439	if (pSubLeaf != pLeaf)
2440	{
2441	if (pSubLeaf != pLast)
2442	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2443	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2444	}
2445
2446	/*
2447	* Convert the first sub-leaf into a single leaf.
2448	*/
2449	pLeaf->uSubLeaf = 0;
2450	pLeaf->fSubLeafMask = 0;
2451	}
2452	return pLeaf;
2453	}
2454
2455
2456	/**
2457	* Sanitizes and adjust the CPUID leaves.
2458	*
2459	* Drop features that aren't virtualized (or virtualizable). Adjust information
2460	* and capabilities to fit the virtualized hardware. Remove information the
2461	* guest shouldn't have (because it's wrong in the virtual world or because it
2462	* gives away host details) or that we don't have documentation for and no idea
2463	* what means.
2464	*
2465	* @returns VBox status code.
2466	* @param pVM Pointer to the cross context VM structure (for cCpus).
2467	* @param pCpum The CPUM instance data.
2468	* @param pConfig The CPUID configuration we've read from CFGM.
2469	*/
2470	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2471	{
2472	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2473	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2474	{ \
2475	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2476	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2477	}
2478	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2479	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2480	{ \
2481	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2482	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2483	}
2484	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2485	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2486	&& ((a_pLeafReg) & (fBitMask)) \
2487	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2488	{ \
2489	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2490	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2491	}
2492	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2493
2494	/* Cpuid 1:
2495	* EAX: CPU model, family and stepping.
2496	*
2497	* ECX + EDX: Supported features. Only report features we can support.
2498	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2499	* options may require adjusting (i.e. stripping what was enabled).
2500	*
2501	* EBX: Branding, CLFLUSH line size, logical processors per package and
2502	* initial APIC ID.
2503	*/
2504	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2505	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2506	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2507
2508	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2509	\| X86_CPUID_FEATURE_EDX_VME
2510	\| X86_CPUID_FEATURE_EDX_DE
2511	\| X86_CPUID_FEATURE_EDX_PSE
2512	\| X86_CPUID_FEATURE_EDX_TSC
2513	\| X86_CPUID_FEATURE_EDX_MSR
2514	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2515	\| X86_CPUID_FEATURE_EDX_MCE
2516	\| X86_CPUID_FEATURE_EDX_CX8
2517	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2518	//\| RT_BIT_32(10) - not defined
2519	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2520	//\| X86_CPUID_FEATURE_EDX_SEP
2521	\| X86_CPUID_FEATURE_EDX_MTRR
2522	\| X86_CPUID_FEATURE_EDX_PGE
2523	\| X86_CPUID_FEATURE_EDX_MCA
2524	\| X86_CPUID_FEATURE_EDX_CMOV
2525	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2526	\| X86_CPUID_FEATURE_EDX_PSE36
2527	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2528	\| X86_CPUID_FEATURE_EDX_CLFSH
2529	//\| RT_BIT_32(20) - not defined
2530	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2531	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2532	\| X86_CPUID_FEATURE_EDX_MMX
2533	\| X86_CPUID_FEATURE_EDX_FXSR
2534	\| X86_CPUID_FEATURE_EDX_SSE
2535	\| X86_CPUID_FEATURE_EDX_SSE2
2536	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2537	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading/cores - see below.
2538	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2539	//\| RT_BIT_32(30) - not defined
2540	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2541	;
2542	pStdFeatureLeaf->uEcx &= 0
2543	\| X86_CPUID_FEATURE_ECX_SSE3
2544	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2545	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2546	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2547	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2548	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2549	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized yet.
2550	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2551	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2552	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2553	\| X86_CPUID_FEATURE_ECX_SSSE3
2554	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2555	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2556	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2557	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2558	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2559	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2560	//\| X86_CPUID_FEATURE_ECX_PCID - not implemented yet.
2561	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2562	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2563	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2564	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2565	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2566	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2567	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2568	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2569	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2570	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2571	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2572	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2573	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2574	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2575	;
2576
2577	if (pCpum->u8PortableCpuIdLevel > 0)
2578	{
2579	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2580	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2581	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2582	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2583	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2584	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2585	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2586	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2587	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2588	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2589	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2590	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2591	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2592	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2593	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2594	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2595	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2596	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2597
2598	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2599	\| X86_CPUID_FEATURE_EDX_PSN
2600	\| X86_CPUID_FEATURE_EDX_DS
2601	\| X86_CPUID_FEATURE_EDX_ACPI
2602	\| X86_CPUID_FEATURE_EDX_SS
2603	\| X86_CPUID_FEATURE_EDX_TM
2604	\| X86_CPUID_FEATURE_EDX_PBE
2605	)));
2606	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2607	\| X86_CPUID_FEATURE_ECX_CPLDS
2608	\| X86_CPUID_FEATURE_ECX_VMX
2609	\| X86_CPUID_FEATURE_ECX_SMX
2610	\| X86_CPUID_FEATURE_ECX_EST
2611	\| X86_CPUID_FEATURE_ECX_TM2
2612	\| X86_CPUID_FEATURE_ECX_CNTXID
2613	\| X86_CPUID_FEATURE_ECX_FMA
2614	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2615	\| X86_CPUID_FEATURE_ECX_PDCM
2616	\| X86_CPUID_FEATURE_ECX_DCA
2617	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2618	)));
2619	}
2620
2621	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2622	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2623	#ifdef VBOX_WITH_MULTI_CORE
2624	if (pVM->cCpus > 1)
2625	{
2626	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2627	core times the number of CPU cores per processor */
2628	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2629	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
2630	}
2631	#endif
2632
2633	/* Force standard feature bits. */
2634	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2635	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2636	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2637	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2638	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2639	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2640	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2641	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2642	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2643	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2644	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2645	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2646	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2647	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2648	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2649	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2650	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2651	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2652	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2653	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2654	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2655	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2656
2657	pStdFeatureLeaf = NULL; /* Must refetch! */
2658
2659	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2660	* AMD:
2661	* EAX: CPU model, family and stepping.
2662	*
2663	* ECX + EDX: Supported features. Only report features we can support.
2664	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2665	* options may require adjusting (i.e. stripping what was enabled).
2666	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2667	*
2668	* EBX: Branding ID and package type (or reserved).
2669	*
2670	* Intel and probably most others:
2671	* EAX: 0
2672	* EBX: 0
2673	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2674	*/
2675	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2676	if (pExtFeatureLeaf)
2677	{
2678	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2679
2680	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2681	\| X86_CPUID_AMD_FEATURE_EDX_VME
2682	\| X86_CPUID_AMD_FEATURE_EDX_DE
2683	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2684	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2685	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2686	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2687	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2688	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2689	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2690	//\| RT_BIT_32(10) - reserved
2691	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2692	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2693	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2694	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2695	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2696	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2697	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2698	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2699	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2700	//\| RT_BIT_32(18) - reserved
2701	//\| RT_BIT_32(19) - reserved
2702	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2703	//\| RT_BIT_32(21) - reserved
2704	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2705	\| X86_CPUID_AMD_FEATURE_EDX_MMX
2706	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
2707	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
2708	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2709	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2710	//\| RT_BIT_32(28) - reserved
2711	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2712	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2713	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
2714	;
2715	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2716	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2717	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
2718	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2719	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
2720	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2721	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2722	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2723	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2724	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2725	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2726	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
2727	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
2728	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2729	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
2730	//\| RT_BIT_32(14) - reserved
2731	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2732	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2733	//\| RT_BIT_32(17) - reserved
2734	//\| RT_BIT_32(18) - reserved
2735	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2736	//\| RT_BIT_32(20) - reserved
2737	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2738	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2739	//\| RT_BIT_32(23) - reserved
2740	//\| RT_BIT_32(24) - reserved
2741	//\| RT_BIT_32(25) - reserved
2742	//\| RT_BIT_32(26) - reserved
2743	//\| RT_BIT_32(27) - reserved
2744	//\| RT_BIT_32(28) - reserved
2745	//\| RT_BIT_32(29) - reserved
2746	//\| RT_BIT_32(30) - reserved
2747	//\| RT_BIT_32(31) - reserved
2748	;
2749	#ifdef VBOX_WITH_MULTI_CORE
2750	if ( pVM->cCpus > 1
2751	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2752	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2753	#endif
2754
2755	if (pCpum->u8PortableCpuIdLevel > 0)
2756	{
2757	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2758	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2759	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2760	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2761	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2762	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2763	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2764	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2765	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2766	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2767	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2768	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2769	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2770	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2771	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2772
2773	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2774	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2775	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2776	\| X86_CPUID_AMD_FEATURE_ECX_IBS
2777	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2778	\| X86_CPUID_AMD_FEATURE_ECX_WDT
2779	\| X86_CPUID_AMD_FEATURE_ECX_LWP
2780	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
2781	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2782	\| UINT32_C(0xff964000)
2783	)));
2784	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2785	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2786	\| RT_BIT(18)
2787	\| RT_BIT(19)
2788	\| RT_BIT(21)
2789	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2790	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2791	\| RT_BIT(28)
2792	)));
2793	}
2794
2795	/* Force extended feature bits. */
2796	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2797	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
2798	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2799	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2800	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2801	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2802	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2803	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2804	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2805	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2806	}
2807	pExtFeatureLeaf = NULL; /* Must refetch! */
2808
2809
2810	/* Cpuid 2:
2811	* Intel: (Nondeterministic) Cache and TLB information
2812	* AMD: Reserved
2813	* VIA: Reserved
2814	* Safe to expose.
2815	*/
2816	uint32_t uSubLeaf = 0;
2817	PCPUMCPUIDLEAF pCurLeaf;
2818	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2819	{
2820	if ((pCurLeaf->uEax & 0xff) > 1)
2821	{
2822	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2823	pCurLeaf->uEax &= UINT32_C(0xffffff01);
2824	}
2825	uSubLeaf++;
2826	}
2827
2828	/* Cpuid 3:
2829	* Intel: EAX, EBX - reserved (transmeta uses these)
2830	* ECX, EDX - Processor Serial Number if available, otherwise reserved
2831	* AMD: Reserved
2832	* VIA: Reserved
2833	* Safe to expose
2834	*/
2835	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2836	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
2837	{
2838	uSubLeaf = 0;
2839	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
2840	{
2841	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2842	if (pCpum->u8PortableCpuIdLevel > 0)
2843	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2844	uSubLeaf++;
2845	}
2846	}
2847
2848	/* Cpuid 4 + ECX:
2849	* Intel: Deterministic Cache Parameters Leaf.
2850	* AMD: Reserved
2851	* VIA: Reserved
2852	* Safe to expose, except for EAX:
2853	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
2854	* Bits 31-26: Maximum number of processor cores in this physical package**
2855	* Note: These SMP values are constant regardless of ECX
2856	*/
2857	uSubLeaf = 0;
2858	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
2859	{
2860	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
2861	#ifdef VBOX_WITH_MULTI_CORE
2862	if ( pVM->cCpus > 1
2863	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2864	{
2865	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
2866	/* One logical processor with possibly multiple cores. */
2867	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
2868	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
2869	}
2870	#endif
2871	uSubLeaf++;
2872	}
2873
2874	/* Cpuid 5: Monitor/mwait Leaf
2875	* Intel: ECX, EDX - reserved
2876	* EAX, EBX - Smallest and largest monitor line size
2877	* AMD: EDX - reserved
2878	* EAX, EBX - Smallest and largest monitor line size
2879	* ECX - extensions (ignored for now)
2880	* VIA: Reserved
2881	* Safe to expose
2882	*/
2883	uSubLeaf = 0;
2884	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
2885	{
2886	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2887	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
2888	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2889
2890	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2891	if (pConfig->enmMWaitExtensions)
2892	{
2893	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
2894	/** @todo: for now we just expose host's MWAIT C-states, although conceptually
2895	it shall be part of our power management virtualization model */
2896	#if 0
2897	/* MWAIT sub C-states */
2898	pCurLeaf->uEdx =
2899	(0 << 0) /* 0 in C0 */ \|
2900	(2 << 4) /* 2 in C1 */ \|
2901	(2 << 8) /* 2 in C2 */ \|
2902	(2 << 12) /* 2 in C3 */ \|
2903	(0 << 16) /* 0 in C4 */
2904	;
2905	#endif
2906	}
2907	else
2908	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2909	uSubLeaf++;
2910	}
2911
2912	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
2913	* Intel: Various stuff.
2914	* AMD: EAX, EBX, EDX - reserved.
2915	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
2916	* present. Same as intel.
2917	* VIA: ??
2918	*
2919	* We clear everything here for now.
2920	*/
2921	cpumR3CpuIdZeroLeaf(pCpum, 6);
2922
2923	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
2924	* EAX: Number of sub leaves.
2925	* EBX+ECX+EDX: Feature flags
2926	*
2927	* We only have documentation for one sub-leaf, so clear all other (no need
2928	* to remove them as such, just set them to zero).
2929	*
2930	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2931	* options may require adjusting (i.e. stripping what was enabled).
2932	*/
2933	uSubLeaf = 0;
2934	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
2935	{
2936	switch (uSubLeaf)
2937	{
2938	case 0:
2939	{
2940	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
2941	pCurLeaf->uEbx &= 0
2942	//\| X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
2943	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
2944	//\| RT_BIT(2) - reserved
2945	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
2946	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
2947	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
2948	//\| RT_BIT(6) - reserved
2949	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
2950	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
2951	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
2952	//\| X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
2953	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
2954	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
2955	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
2956	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
2957	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
2958	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
2959	//\| RT_BIT(17) - reserved
2960	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
2961	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
2962	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
2963	//\| RT_BIT(21) - reserved
2964	//\| RT_BIT(22) - reserved
2965	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
2966	//\| RT_BIT(24) - reserved
2967	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
2968	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
2969	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
2970	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
2971	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
2972	//\| RT_BIT(30) - reserved
2973	//\| RT_BIT(31) - reserved
2974	;
2975	pCurLeaf->uEcx &= 0
2976	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
2977	;
2978	pCurLeaf->uEdx &= 0;
2979
2980	if (pCpum->u8PortableCpuIdLevel > 0)
2981	{
2982	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
2983	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
2984	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
2985	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
2986	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
2987	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
2988	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
2989	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
2990	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
2991	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
2992	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
2993	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
2994	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
2995	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
2996	}
2997
2998	/* Force standard feature bits. */
2999	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3000	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3001	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3002	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3003	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3004	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3005	break;
3006	}
3007
3008	default:
3009	/* Invalid index, all values are zero. */
3010	pCurLeaf->uEax = 0;
3011	pCurLeaf->uEbx = 0;
3012	pCurLeaf->uEcx = 0;
3013	pCurLeaf->uEdx = 0;
3014	break;
3015	}
3016	uSubLeaf++;
3017	}
3018
3019	/* Cpuid 8: Marked as reserved by Intel and AMD.
3020	* We zero this since we don't know what it may have been used for.
3021	*/
3022	cpumR3CpuIdZeroLeaf(pCpum, 8);
3023
3024	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3025	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3026	* EBX, ECX, EDX - reserved.
3027	* AMD: Reserved
3028	* VIA: ??
3029	*
3030	* We zero this.
3031	*/
3032	cpumR3CpuIdZeroLeaf(pCpum, 9);
3033
3034	/* Cpuid 0xa: Architectural Performance Monitor Features
3035	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3036	* EBX, ECX, EDX - reserved.
3037	* AMD: Reserved
3038	* VIA: ??
3039	*
3040	* We zero this, for now at least.
3041	*/
3042	cpumR3CpuIdZeroLeaf(pCpum, 10);
3043
3044	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3045	* Intel: EAX - APCI ID shift right for next level.
3046	* EBX - Factory configured cores/threads at this level.
3047	* ECX - Level number (same as input) and level type (1,2,0).
3048	* EDX - Extended initial APIC ID.
3049	* AMD: Reserved
3050	* VIA: ??
3051	*/
3052	uSubLeaf = 0;
3053	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3054	{
3055	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3056	{
3057	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3058	if (bLevelType == 1)
3059	{
3060	/* Thread level - we don't do threads at the moment. */
3061	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3062	pCurLeaf->uEbx = 1;
3063	}
3064	else if (bLevelType == 2)
3065	{
3066	/* Core level. */
3067	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3068	#ifdef VBOX_WITH_MULTI_CORE
3069	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3070	pCurLeaf->uEax++;
3071	#endif
3072	pCurLeaf->uEbx = pVM->cCpus;
3073	}
3074	else
3075	{
3076	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3077	pCurLeaf->uEax = 0;
3078	pCurLeaf->uEbx = 0;
3079	pCurLeaf->uEcx = 0;
3080	}
3081	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3082	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3083	}
3084	else
3085	{
3086	pCurLeaf->uEax = 0;
3087	pCurLeaf->uEbx = 0;
3088	pCurLeaf->uEcx = 0;
3089	pCurLeaf->uEdx = 0;
3090	}
3091	uSubLeaf++;
3092	}
3093
3094	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3095	* We zero this since we don't know what it may have been used for.
3096	*/
3097	cpumR3CpuIdZeroLeaf(pCpum, 12);
3098
3099	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3100	* ECX=0: EAX - Valid bits in XCR0[31:0].
3101	* EBX - Maximum state size as per current XCR0 value.
3102	* ECX - Maximum state size for all supported features.
3103	* EDX - Valid bits in XCR0[63:32].
3104	* ECX=1: EAX - Various X-features.
3105	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3106	* ECX - Valid bits in IA32_XSS[31:0].
3107	* EDX - Valid bits in IA32_XSS[63:32].
3108	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3109	* if the bit invalid all four registers are set to zero.
3110	* EAX - The state size for this feature.
3111	* EBX - The state byte offset of this feature.
3112	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3113	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3114	*
3115	* Clear them all as we don't currently implement extended CPU state.
3116	*/
3117	/* Figure out the supported XCR0/XSS mask component. */
3118	uint64_t fGuestXcr0Mask = 0;
3119	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3120	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3121	{
3122	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3123	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3124	fGuestXcr0Mask \|= XSAVE_C_YMM;
3125	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3126	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3127	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3128	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3129	}
3130	pStdFeatureLeaf = NULL;
3131	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3132
3133	/* Work the sub-leaves. */
3134	uint32_t cbXSaveMax = sizeof(X86FXSTATE);
3135	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3136	{
3137	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3138	if (pCurLeaf)
3139	{
3140	if (fGuestXcr0Mask)
3141	{
3142	switch (uSubLeaf)
3143	{
3144	case 0:
3145	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3146	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3147	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3148	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3149	VERR_CPUM_IPE_1);
3150	cbXSaveMax = pCurLeaf->uEcx;
3151	AssertLogRelMsgReturn(cbXSaveMax <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMax >= CPUM_MIN_XSAVE_AREA_SIZE,
3152	("%#x max=%#x\n", cbXSaveMax, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3153	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMax,
3154	("ebx=%#x cbXSaveMax=%#x\n", pCurLeaf->uEbx, cbXSaveMax),
3155	VERR_CPUM_IPE_2);
3156	continue;
3157	case 1:
3158	pCurLeaf->uEax &= 0;
3159	pCurLeaf->uEcx &= 0;
3160	pCurLeaf->uEdx &= 0;
3161	/** @todo what about checking ebx? */
3162	continue;
3163	default:
3164	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3165	{
3166	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMax
3167	&& pCurLeaf->uEax > 0
3168	&& pCurLeaf->uEbx < cbXSaveMax
3169	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3170	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMax,
3171	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3172	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMax),
3173	VERR_CPUM_IPE_2);
3174	AssertLogRel(!(pCurLeaf->uEcx & 1));
3175	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3176	pCurLeaf->uEdx = 0; /* it's reserved... */
3177	continue;
3178	}
3179	break;
3180	}
3181	}
3182
3183	/* Clear the leaf. */
3184	pCurLeaf->uEax = 0;
3185	pCurLeaf->uEbx = 0;
3186	pCurLeaf->uEcx = 0;
3187	pCurLeaf->uEdx = 0;
3188	}
3189	}
3190
3191	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3192	* We zero this since we don't know what it may have been used for.
3193	*/
3194	cpumR3CpuIdZeroLeaf(pCpum, 14);
3195
3196	/* Cpuid 0xf + ECX: Platform qualifity of service monitoring (PQM).
3197	* We zero this as we don't currently virtualize PQM.
3198	*/
3199	cpumR3CpuIdZeroLeaf(pCpum, 15);
3200
3201	/* Cpuid 0x10 + ECX: Platform qualifity of service enforcement (PQE).
3202	* We zero this as we don't currently virtualize PQE.
3203	*/
3204	cpumR3CpuIdZeroLeaf(pCpum, 16);
3205
3206	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3207	* We zero this since we don't know what it may have been used for.
3208	*/
3209	cpumR3CpuIdZeroLeaf(pCpum, 17);
3210
3211	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3212	* We zero this as we don't currently virtualize this.
3213	*/
3214	cpumR3CpuIdZeroLeaf(pCpum, 18);
3215
3216	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3217	* We zero this since we don't know what it may have been used for.
3218	*/
3219	cpumR3CpuIdZeroLeaf(pCpum, 19);
3220
3221	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3222	* We zero this as we don't currently virtualize this.
3223	*/
3224	cpumR3CpuIdZeroLeaf(pCpum, 20);
3225
3226	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3227	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3228	* EAX - denominator (unsigned).
3229	* EBX - numerator (unsigned).
3230	* ECX, EDX - reserved.
3231	* AMD: Reserved / undefined / not implemented.
3232	* VIA: Reserved / undefined / not implemented.
3233	* We zero this as we don't currently virtualize this.
3234	*/
3235	cpumR3CpuIdZeroLeaf(pCpum, 21);
3236
3237	/* Cpuid 0x16: Processor frequency info
3238	* Intel: EAX - Core base frequency in MHz.
3239	* EBX - Core maximum frequency in MHz.
3240	* ECX - Bus (reference) frequency in MHz.
3241	* EDX - Reserved.
3242	* AMD: Reserved / undefined / not implemented.
3243	* VIA: Reserved / undefined / not implemented.
3244	* We zero this as we don't currently virtualize this.
3245	*/
3246	cpumR3CpuIdZeroLeaf(pCpum, 22);
3247
3248	/* Cpuid 0x17..0x10000000: Unknown.
3249	* We don't know these and what they mean, so remove them. */
3250	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3251	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3252
3253
3254	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3255	* We remove all these as we're a hypervisor and must provide our own.
3256	*/
3257	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3258	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3259
3260
3261	/* Cpuid 0x80000000 is harmless. */
3262
3263	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3264
3265	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3266
3267	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3268	* Safe to pass on to the guest.
3269	*
3270	* AMD: 0x800000005 L1 cache information
3271	* 0x800000006 L2/L3 cache information
3272	* Intel: 0x800000005 reserved
3273	* 0x800000006 L2 cache information
3274	* VIA: 0x800000005 TLB and L1 cache information
3275	* 0x800000006 L2 cache information
3276	*/
3277
3278	/* Cpuid 0x800000007: Advanced Power Management Information.
3279	* AMD: EAX: Processor feedback capabilities.
3280	* EBX: RAS capabilites.
3281	* ECX: Advanced power monitoring interface.
3282	* EDX: Enhanced power management capabilities.
3283	* Intel: EAX, EBX, ECX - reserved.
3284	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3285	* VIA: Reserved
3286	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3287	*/
3288	uSubLeaf = 0;
3289	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3290	{
3291	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3292	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3293	{
3294	pCurLeaf->uEdx &= 0
3295	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3296	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3297	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3298	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3299	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3300	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3301	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3302	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3303	#if 0 /*
3304	* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
3305	* Linux kernels blindly assume that the AMD performance counters work
3306	* if this is set for 64 bits guests. (Can't really find a CPUID feature
3307	* bit for them though.)
3308	*/
3309	/** @todo need to recheck this with new MSR emulation. */
3310	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3311	#endif
3312	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3313	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3314	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3315	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3316	\| 0;
3317	}
3318	else
3319	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3320	if (pConfig->fInvariantTsc)
3321	pCurLeaf->uEdx \|= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3322	uSubLeaf++;
3323	}
3324
3325	/* Cpuid 0x80000008:
3326	* AMD: EBX, EDX - reserved
3327	* EAX: Virtual/Physical/Guest address Size
3328	* ECX: Number of cores + APICIdCoreIdSize
3329	* Intel: EAX: Virtual/Physical address Size
3330	* EBX, ECX, EDX - reserved
3331	* VIA: EAX: Virtual/Physical address Size
3332	* EBX, ECX, EDX - reserved
3333	*
3334	* We only expose the virtual+pysical address size to the guest atm.
3335	* On AMD we set the core count, but not the apic id stuff as we're
3336	* currently not doing the apic id assignments in a complatible manner.
3337	*/
3338	uSubLeaf = 0;
3339	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3340	{
3341	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3342	pCurLeaf->uEbx = 0; /* reserved */
3343	pCurLeaf->uEdx = 0; /* reserved */
3344
3345	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3346	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3347	pCurLeaf->uEcx = 0;
3348	#ifdef VBOX_WITH_MULTI_CORE
3349	if ( pVM->cCpus > 1
3350	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3351	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3352	#endif
3353	uSubLeaf++;
3354	}
3355
3356	/* Cpuid 0x80000009: Reserved
3357	* We zero this since we don't know what it may have been used for.
3358	*/
3359	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3360
3361	/* Cpuid 0x8000000a: SVM Information
3362	* AMD: EAX - SVM revision.
3363	* EBX - Number of ASIDs.
3364	* ECX - Reserved.
3365	* EDX - SVM Feature identification.
3366	* We clear all as we currently does not virtualize SVM.
3367	*/
3368	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3369
3370	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3371	* We clear these as we don't know what purpose they might have. */
3372	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3373	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3374
3375	/* Cpuid 0x80000019: TLB configuration
3376	* Seems to be harmless, pass them thru as is. */
3377
3378	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3379	* Strip anything we don't know what is or addresses feature we don't implement. */
3380	uSubLeaf = 0;
3381	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3382	{
3383	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3384	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3385	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3386	;
3387	pCurLeaf->uEbx = 0; /* reserved */
3388	pCurLeaf->uEcx = 0; /* reserved */
3389	pCurLeaf->uEdx = 0; /* reserved */
3390	uSubLeaf++;
3391	}
3392
3393	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3394	* Clear this as we don't currently virtualize this feature. */
3395	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3396
3397	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3398	* Clear this as we don't currently virtualize this feature. */
3399	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3400
3401	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3402	* We need to sanitize the cores per cache (EAX[25:14]).
3403	*
3404	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3405	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3406	* slightly different meaning.
3407	*/
3408	uSubLeaf = 0;
3409	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3410	{
3411	#ifdef VBOX_WITH_MULTI_CORE
3412	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3413	if (cCores > pVM->cCpus)
3414	cCores = pVM->cCpus;
3415	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3416	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3417	#else
3418	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3419	#endif
3420	uSubLeaf++;
3421	}
3422
3423	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3424	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3425	* setup, we have one compute unit with all the cores in it. Single node.
3426	*/
3427	uSubLeaf = 0;
3428	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3429	{
3430	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3431	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3432	{
3433	#ifdef VBOX_WITH_MULTI_CORE
3434	pCurLeaf->uEbx = pVM->cCpus < 0x100
3435	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3436	#else
3437	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3438	#endif
3439	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3440	}
3441	else
3442	{
3443	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3444	pCurLeaf->uEbx = 0; /* Reserved. */
3445	pCurLeaf->uEcx = 0; /* Reserved. */
3446	}
3447	pCurLeaf->uEdx = 0; /* Reserved. */
3448	uSubLeaf++;
3449	}
3450
3451	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3452	* We don't know these and what they mean, so remove them. */
3453	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3454	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3455
3456	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3457	* Just pass it thru for now. */
3458
3459	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3460	* Just pass it thru for now. */
3461
3462	/* Cpuid 0xc0000000: Centaur stuff.
3463	* Harmless, pass it thru. */
3464
3465	/* Cpuid 0xc0000001: Centaur features.
3466	* VIA: EAX - Family, model, stepping.
3467	* EDX - Centaur extended feature flags. Nothing interesting, except may
3468	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3469	* EBX, ECX - reserved.
3470	* We keep EAX but strips the rest.
3471	*/
3472	uSubLeaf = 0;
3473	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3474	{
3475	pCurLeaf->uEbx = 0;
3476	pCurLeaf->uEcx = 0;
3477	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3478	uSubLeaf++;
3479	}
3480
3481	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3482	* We only have fixed stale values, but should be harmless. */
3483
3484	/* Cpuid 0xc0000003: Reserved.
3485	* We zero this since we don't know what it may have been used for.
3486	*/
3487	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3488
3489	/* Cpuid 0xc0000004: Centaur Performance Info.
3490	* We only have fixed stale values, but should be harmless. */
3491
3492
3493	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3494	* We don't know these and what they mean, so remove them. */
3495	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3496	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3497
3498	return VINF_SUCCESS;
3499	#undef PORTABLE_DISABLE_FEATURE_BIT
3500	#undef PORTABLE_CLEAR_BITS_WHEN
3501	}
3502
3503
3504	/**
3505	* Reads a value in /CPUM/IsaExts/ node.
3506	*
3507	* @returns VBox status code (error message raised).
3508	* @param pVM The VM handle (for errors).
3509	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3510	* @param pszValueName The value / extension name.
3511	* @param penmValue Where to return the choice.
3512	* @param enmDefault The default choice.
3513	*/
3514	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3515	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3516	{
3517	/*
3518	* Try integer encoding first.
3519	*/
3520	uint64_t uValue;
3521	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3522	if (RT_SUCCESS(rc))
3523	switch (uValue)
3524	{
3525	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3526	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3527	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3528	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3529	default:
3530	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3531	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3532	pszValueName, uValue);
3533	}
3534	/*
3535	* If missing, use default.
3536	*/
3537	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3538	*penmValue = enmDefault;
3539	else
3540	{
3541	if (rc == VERR_CFGM_NOT_INTEGER)
3542	{
3543	/*
3544	* Not an integer, try read it as a string.
3545	*/
3546	char szValue[32];
3547	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3548	if (RT_SUCCESS(rc))
3549	{
3550	RTStrToLower(szValue);
3551	size_t cchValue = strlen(szValue);
3552	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3553	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3554	*penmValue = CPUMISAEXTCFG_DISABLED;
3555	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3556	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3557	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3558	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3559	else if (EQ("portable"))
3560	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3561	else if (EQ("default") \|\| EQ("def"))
3562	*penmValue = enmDefault;
3563	else
3564	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3565	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3566	pszValueName, uValue);
3567	#undef EQ
3568	}
3569	}
3570	if (RT_FAILURE(rc))
3571	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3572	}
3573	return VINF_SUCCESS;
3574	}
3575
3576
3577	/**
3578	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3579	*
3580	* @returns VBox status code (error message raised).
3581	* @param pVM The VM handle (for errors).
3582	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3583	* @param pszValueName The value / extension name.
3584	* @param penmValue Where to return the choice.
3585	* @param enmDefault The default choice.
3586	* @param fAllowed Allowed choice. Applied both to the result and to
3587	* the default value.
3588	*/
3589	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3590	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3591	{
3592	int rc;
3593	if (fAllowed)
3594	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3595	else
3596	{
3597	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3598	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3599	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3600	*penmValue = CPUMISAEXTCFG_DISABLED;
3601	}
3602	return rc;
3603	}
3604
3605
3606	/**
3607	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3608	*
3609	* @returns VBox status code (error message raised).
3610	* @param pVM The VM handle (for errors).
3611	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3612	* @param pCpumCfg The /CPUM node (can be NULL).
3613	* @param pszValueName The value / extension name.
3614	* @param penmValue Where to return the choice.
3615	* @param enmDefault The default choice.
3616	*/
3617	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3618	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3619	{
3620	if (CFGMR3Exists(pCpumCfg, pszValueName))
3621	{
3622	if (!CFGMR3Exists(pIsaExts, pszValueName))
3623	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3624	else
3625	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3626	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3627	pszValueName, pszValueName);
3628
3629	bool fLegacy;
3630	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3631	if (RT_SUCCESS(rc))
3632	{
3633	*penmValue = fLegacy;
3634	return VINF_SUCCESS;
3635	}
3636	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3637	}
3638
3639	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3640	}
3641
3642
3643	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3644	{
3645	int rc;
3646
3647	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3648	* When non-zero CPUID features that could cause portability issues will be
3649	* stripped. The higher the value the more features gets stripped. Higher
3650	* values should only be used when older CPUs are involved since it may
3651	* harm performance and maybe also cause problems with specific guests. */
3652	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
3653	AssertLogRelRCReturn(rc, rc);
3654
3655	/** @cfgm{/CPUM/GuestCpuName, string}
3656	* The name of the CPU we're to emulate. The default is the host CPU.
3657	* Note! CPUs other than "host" one is currently unsupported. */
3658	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3659	AssertLogRelRCReturn(rc, rc);
3660
3661	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3662	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3663	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3664	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3665	*/
3666	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3667	AssertLogRelRCReturn(rc, rc);
3668
3669	/** @cfgm{/CPUM/InvariantTsc, boolean, complicated}
3670	* Set the invariant TSC flag in 0x80000007 if true, otherwas take default
3671	* action. By default the flag is passed thru as is from the host CPU, except
3672	* on AMD CPUs where it's suppressed to avoid trouble from linux assuming we
3673	* virtualize performance counters.
3674	*/
3675	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, false);
3676	AssertLogRelRCReturn(rc, rc);
3677
3678	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3679	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
3680	* probably going to be a temporary hack, so don't depend on this.
3681	* The 1st byte of the value is the stepping, the 2nd byte value is the model
3682	* number and the 3rd byte value is the family, and the 4th value must be zero.
3683	*/
3684	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3685	AssertLogRelRCReturn(rc, rc);
3686
3687	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3688	* The last standard leaf to keep. The actual last value that is stored in EAX
3689	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3690	* removed. (This works independently of and differently from NT4LeafLimit.)
3691	* The default is usually set to what we're able to reasonably sanitize.
3692	*/
3693	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3694	AssertLogRelRCReturn(rc, rc);
3695
3696	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3697	* The last extended leaf to keep. The actual last value that is stored in EAX
3698	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3699	* leaf are removed. The default is set to what we're able to sanitize.
3700	*/
3701	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3702	AssertLogRelRCReturn(rc, rc);
3703
3704	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3705	* The last extended leaf to keep. The actual last value that is stored in EAX
3706	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3707	* leaf are removed. The default is set to what we're able to sanitize.
3708	*/
3709	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3710	AssertLogRelRCReturn(rc, rc);
3711
3712
3713	/*
3714	* Instruction Set Architecture (ISA) Extensions.
3715	*/
3716	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3717	if (pIsaExts)
3718	{
3719	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3720	"CMPXCHG16B"
3721	"\|MONITOR"
3722	"\|MWaitExtensions"
3723	"\|SSE4.1"
3724	"\|SSE4.2"
3725	"\|AESNI"
3726	"\|PCLMUL"
3727	"\|POPCNT"
3728	"\|MOVBE"
3729	"\|RDRAND"
3730	"\|RDSEED"
3731	"\|CLFLUSHOPT"
3732	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
3733	if (RT_FAILURE(rc))
3734	return rc;
3735	}
3736
3737	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
3738	* Expose CMPXCHG16B to the guest if supported by the host. For the time
3739	* being the default is to only do this for VMs with nested paging and AMD-V or
3740	* unrestricted guest mode.
3741	*/
3742	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
3743	AssertLogRelRCReturn(rc, rc);
3744
3745	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
3746	* Expose MONITOR/MWAIT instructions to the guest.
3747	*/
3748	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
3749	AssertLogRelRCReturn(rc, rc);
3750
3751	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
3752	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
3753	* break on interrupt feature (bit 1).
3754	*/
3755	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
3756	AssertLogRelRCReturn(rc, rc);
3757
3758	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
3759	* Expose SSE4.1 to the guest if available.
3760	*/
3761	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
3762	AssertLogRelRCReturn(rc, rc);
3763
3764	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
3765	* Expose SSE4.2 to the guest if available.
3766	*/
3767	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
3768	AssertLogRelRCReturn(rc, rc);
3769
3770	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
3771	&& pVM->cpum.s.HostFeatures.fXSaveRstor
3772	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor;
3773	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
3774
3775	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
3776	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
3777	* default is to only expose this to VMs with nested paging and AMD-V or
3778	* unrestricted guest execution mode. Not possible to force this one without
3779	* host support at the moment.
3780	*/
3781	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
3782	fMayHaveXSave /fAllowed/);
3783	AssertLogRelRCReturn(rc, rc);
3784
3785	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
3786	* Expose the AVX instruction set extensions to the guest if available and
3787	* XSAVE is exposed too. For the time being the default is to only expose this
3788	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3789	*/
3790	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
3791	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3792	AssertLogRelRCReturn(rc, rc);
3793
3794	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
3795	* Expose the AVX2 instruction set extensions to the guest if available and
3796	* XSAVE is exposed too. For the time being the default is to only expose this
3797	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3798	*/
3799	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec,
3800	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3801	AssertLogRelRCReturn(rc, rc);
3802
3803	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
3804	* Whether to expose the AES instructions to the guest. For the time being the
3805	* default is to only do this for VMs with nested paging and AMD-V or
3806	* unrestricted guest mode.
3807	*/
3808	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
3809	AssertLogRelRCReturn(rc, rc);
3810
3811	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
3812	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
3813	* being the default is to only do this for VMs with nested paging and AMD-V or
3814	* unrestricted guest mode.
3815	*/
3816	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
3817	AssertLogRelRCReturn(rc, rc);
3818
3819	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
3820	* Whether to expose the POPCNT instructions to the guest. For the time
3821	* being the default is to only do this for VMs with nested paging and AMD-V or
3822	* unrestricted guest mode.
3823	*/
3824	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
3825	AssertLogRelRCReturn(rc, rc);
3826
3827	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
3828	* Whether to expose the MOVBE instructions to the guest. For the time
3829	* being the default is to only do this for VMs with nested paging and AMD-V or
3830	* unrestricted guest mode.
3831	*/
3832	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
3833	AssertLogRelRCReturn(rc, rc);
3834
3835	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
3836	* Whether to expose the RDRAND instructions to the guest. For the time being
3837	* the default is to only do this for VMs with nested paging and AMD-V or
3838	* unrestricted guest mode.
3839	*/
3840	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
3841	AssertLogRelRCReturn(rc, rc);
3842
3843	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
3844	* Whether to expose the RDSEED instructions to the guest. For the time being
3845	* the default is to only do this for VMs with nested paging and AMD-V or
3846	* unrestricted guest mode.
3847	*/
3848	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
3849	AssertLogRelRCReturn(rc, rc);
3850
3851	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
3852	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
3853	* being the default is to only do this for VMs with nested paging and AMD-V or
3854	* unrestricted guest mode.
3855	*/
3856	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
3857	AssertLogRelRCReturn(rc, rc);
3858
3859
3860	/* AMD: */
3861
3862	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
3863	* Whether to expose the AMD ABM instructions to the guest. For the time
3864	* being the default is to only do this for VMs with nested paging and AMD-V or
3865	* unrestricted guest mode.
3866	*/
3867	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
3868	AssertLogRelRCReturn(rc, rc);
3869
3870	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
3871	* Whether to expose the AMD SSE4A instructions to the guest. For the time
3872	* being the default is to only do this for VMs with nested paging and AMD-V or
3873	* unrestricted guest mode.
3874	*/
3875	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
3876	AssertLogRelRCReturn(rc, rc);
3877
3878	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
3879	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
3880	* the time being the default is to only do this for VMs with nested paging and
3881	* AMD-V or unrestricted guest mode.
3882	*/
3883	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
3884	AssertLogRelRCReturn(rc, rc);
3885
3886	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
3887	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
3888	* For the time being the default is to only do this for VMs with nested paging
3889	* and AMD-V or unrestricted guest mode.
3890	*/
3891	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
3892	AssertLogRelRCReturn(rc, rc);
3893
3894	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
3895	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
3896	* the default is to only do this for VMs with nested paging and AMD-V or
3897	* unrestricted guest mode.
3898	*/
3899	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
3900	AssertLogRelRCReturn(rc, rc);
3901
3902	return VINF_SUCCESS;
3903	}
3904
3905
3906	/**
3907	* Initializes the emulated CPU's CPUID & MSR information.
3908	*
3909	* @returns VBox status code.
3910	* @param pVM Pointer to the VM.
3911	*/
3912	int cpumR3InitCpuIdAndMsrs(PVM pVM)
3913	{
3914	PCPUM pCpum = &pVM->cpum.s;
3915	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
3916
3917	/*
3918	* Read the configuration.
3919	*/
3920	CPUMCPUIDCONFIG Config;
3921	RT_ZERO(Config);
3922
3923	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
3924	AssertRCReturn(rc, rc);
3925
3926	/*
3927	* Get the guest CPU data from the database and/or the host.
3928	*
3929	* The CPUID and MSRs are currently living on the regular heap to avoid
3930	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
3931	* API for the hyper heap). This means special cleanup considerations.
3932	*/
3933	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
3934	if (RT_FAILURE(rc))
3935	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
3936	? VMSetError(pVM, rc, RT_SRC_POS,
3937	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
3938	: rc;
3939
3940	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
3941	* Overrides the guest MSRs.
3942	*/
3943	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
3944
3945	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
3946	* Overrides the CPUID leaf values (from the host CPU usually) used for
3947	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
3948	* values when moving a VM to a different machine. Another use is restricting
3949	* (or extending) the feature set exposed to the guest. */
3950	if (RT_SUCCESS(rc))
3951	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
3952
3953	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
3954	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
3955	"Found unsupported configuration node '/CPUM/CPUID/'. "
3956	"Please use IMachine::setCPUIDLeaf() instead.");
3957
3958	/*
3959	* Pre-explode the CPUID info.
3960	*/
3961	if (RT_SUCCESS(rc))
3962	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
3963
3964	/*
3965	* Sanitize the cpuid information passed on to the guest.
3966	*/
3967	if (RT_SUCCESS(rc))
3968	{
3969	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
3970	if (RT_SUCCESS(rc))
3971	{
3972	cpumR3CpuIdLimitLeaves(pCpum, &Config);
3973	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
3974	}
3975	}
3976
3977	/*
3978	* Plant our own hypervisor CPUID leaves.
3979	*/
3980	if (RT_SUCCESS(rc))
3981	rc = cpumR3CpuIdPlantHypervisorLeaves(pCpum, &Config);
3982
3983	/*
3984	* MSR fudging.
3985	*/
3986	if (RT_SUCCESS(rc))
3987	{
3988	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
3989	* Fudges some common MSRs if not present in the selected CPU database entry.
3990	* This is for trying to keep VMs running when moved between different hosts
3991	* and different CPU vendors. */
3992	bool fEnable;
3993	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
3994	if (RT_SUCCESS(rc) && fEnable)
3995	{
3996	rc = cpumR3MsrApplyFudge(pVM);
3997	AssertLogRelRC(rc);
3998	}
3999	}
4000	if (RT_SUCCESS(rc))
4001	{
4002	/*
4003	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4004	* guest CPU features again.
4005	*/
4006	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4007	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4008	pCpum->GuestInfo.cCpuIdLeaves);
4009	RTMemFree(pvFree);
4010
4011	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4012	int rc2 = MMHyperDupMem(pVM, pvFree,
4013	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4014	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4015	RTMemFree(pvFree);
4016	AssertLogRelRCReturn(rc1, rc1);
4017	AssertLogRelRCReturn(rc2, rc2);
4018
4019	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4020	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4021
4022
4023	/*
4024	* Some more configuration that we're applying at the end of everything
4025	* via the CPUMSetGuestCpuIdFeature API.
4026	*/
4027
4028	/* Check if PAE was explicitely enabled by the user. */
4029	bool fEnable;
4030	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4031	AssertRCReturn(rc, rc);
4032	if (fEnable)
4033	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4034
4035	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4036	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4037	AssertRCReturn(rc, rc);
4038	if (fEnable)
4039	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4040
4041	/* We don't enable the Hypervisor Present bit by default, but it may be needed by some guests. */
4042	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false);
4043	AssertRCReturn(rc, rc);
4044	if (fEnable)
4045	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
4046
4047	return VINF_SUCCESS;
4048	}
4049
4050	/*
4051	* Failed before switching to hyper heap.
4052	*/
4053	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4054	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4055	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4056	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4057	return rc;
4058	}
4059
4060
4061
4062	/*
4063	*
4064	*
4065	* Saved state related code.
4066	* Saved state related code.
4067	* Saved state related code.
4068	*
4069	*
4070	*/
4071
4072	/**
4073	* Called both in pass 0 and the final pass.
4074	*
4075	* @param pVM Pointer to the VM.
4076	* @param pSSM The saved state handle.
4077	*/
4078	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4079	{
4080	/*
4081	* Save all the CPU ID leaves.
4082	*/
4083	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4084	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4085	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4086	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4087
4088	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4089
4090	/*
4091	* Save a good portion of the raw CPU IDs as well as they may come in
4092	* handy when validating features for raw mode.
4093	*/
4094	CPUMCPUID aRawStd[16];
4095	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4096	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4097	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4098	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4099
4100	CPUMCPUID aRawExt[32];
4101	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4102	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4103	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4104	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4105	}
4106
4107
4108	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4109	{
4110	uint32_t cCpuIds;
4111	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4112	if (RT_SUCCESS(rc))
4113	{
4114	if (cCpuIds < 64)
4115	{
4116	for (uint32_t i = 0; i < cCpuIds; i++)
4117	{
4118	CPUMCPUID CpuId;
4119	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4120	if (RT_FAILURE(rc))
4121	break;
4122
4123	CPUMCPUIDLEAF NewLeaf;
4124	NewLeaf.uLeaf = uBase + i;
4125	NewLeaf.uSubLeaf = 0;
4126	NewLeaf.fSubLeafMask = 0;
4127	NewLeaf.uEax = CpuId.uEax;
4128	NewLeaf.uEbx = CpuId.uEbx;
4129	NewLeaf.uEcx = CpuId.uEcx;
4130	NewLeaf.uEdx = CpuId.uEdx;
4131	NewLeaf.fFlags = 0;
4132	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4133	}
4134	}
4135	else
4136	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4137	}
4138	if (RT_FAILURE(rc))
4139	{
4140	RTMemFree(*ppaLeaves);
4141	*ppaLeaves = NULL;
4142	*pcLeaves = 0;
4143	}
4144	return rc;
4145	}
4146
4147
4148	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4149	{
4150	*ppaLeaves = NULL;
4151	*pcLeaves = 0;
4152
4153	int rc;
4154	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4155	{
4156	/*
4157	* The new format. Starts by declaring the leave size and count.
4158	*/
4159	uint32_t cbLeaf;
4160	SSMR3GetU32(pSSM, &cbLeaf);
4161	uint32_t cLeaves;
4162	rc = SSMR3GetU32(pSSM, &cLeaves);
4163	if (RT_SUCCESS(rc))
4164	{
4165	if (cbLeaf == sizeof(**ppaLeaves))
4166	{
4167	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4168	{
4169	/*
4170	* Load the leaves one by one.
4171	*
4172	* The uPrev stuff is a kludge for working around a week worth of bad saved
4173	* states during the CPUID revamp in March 2015. We saved too many leaves
4174	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4175	* garbage entires at the end of the array when restoring. We also had
4176	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
4177	* this kludge doesn't deal correctly with that, but who cares...
4178	*/
4179	uint32_t uPrev = 0;
4180	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4181	{
4182	CPUMCPUIDLEAF Leaf;
4183	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
4184	if (RT_SUCCESS(rc))
4185	{
4186	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
4187	\|\| Leaf.uLeaf >= uPrev)
4188	{
4189	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4190	uPrev = Leaf.uLeaf;
4191	}
4192	else
4193	uPrev = UINT32_MAX;
4194	}
4195	}
4196	}
4197	else
4198	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
4199	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
4200	}
4201	else
4202	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
4203	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
4204	}
4205	}
4206	else
4207	{
4208	/*
4209	* The old format with its three inflexible arrays.
4210	*/
4211	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
4212	if (RT_SUCCESS(rc))
4213	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
4214	if (RT_SUCCESS(rc))
4215	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
4216	if (RT_SUCCESS(rc))
4217	{
4218	/*
4219	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
4220	*/
4221	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
4222	if ( pLeaf
4223	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
4224	{
4225	CPUMCPUIDLEAF Leaf;
4226	Leaf.uLeaf = 4;
4227	Leaf.fSubLeafMask = UINT32_MAX;
4228	Leaf.uSubLeaf = 0;
4229	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
4230	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
4231	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
4232	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
4233	\| UINT32_C(63); /* system coherency line size - 1 */
4234	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
4235	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
4236	\| (UINT32_C(1) << 5) /* cache level */
4237	\| UINT32_C(1); /* cache type (data) */
4238	Leaf.fFlags = 0;
4239	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4240	if (RT_SUCCESS(rc))
4241	{
4242	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
4243	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4244	}
4245	if (RT_SUCCESS(rc))
4246	{
4247	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
4248	Leaf.uEcx = 4095; /* sets - 1 */
4249	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
4250	Leaf.uEbx \|= UINT32_C(23) << 22;
4251	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
4252	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
4253	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
4254	Leaf.uEax \|= UINT32_C(2) << 5;
4255	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4256	}
4257	}
4258	}
4259	}
4260	return rc;
4261	}
4262
4263
4264	/**
4265	* Loads the CPU ID leaves saved by pass 0, inner worker.
4266	*
4267	* @returns VBox status code.
4268	* @param pVM Pointer to the VM.
4269	* @param pSSM The saved state handle.
4270	* @param uVersion The format version.
4271	* @param paLeaves Guest CPUID leaves loaded from the state.
4272	* @param cLeaves The number of leaves in @a paLeaves.
4273	*/
4274	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
4275	{
4276	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4277
4278	/*
4279	* Continue loading the state into stack buffers.
4280	*/
4281	CPUMCPUID GuestDefCpuId;
4282	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
4283	AssertRCReturn(rc, rc);
4284
4285	CPUMCPUID aRawStd[16];
4286	uint32_t cRawStd;
4287	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
4288	if (cRawStd > RT_ELEMENTS(aRawStd))
4289	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4290	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
4291	AssertRCReturn(rc, rc);
4292	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
4293	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4294
4295	CPUMCPUID aRawExt[32];
4296	uint32_t cRawExt;
4297	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
4298	if (cRawExt > RT_ELEMENTS(aRawExt))
4299	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4300	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
4301	AssertRCReturn(rc, rc);
4302	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
4303	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4304
4305	/*
4306	* Get the raw CPU IDs for the current host.
4307	*/
4308	CPUMCPUID aHostRawStd[16];
4309	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
4310	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
4311
4312	CPUMCPUID aHostRawExt[32];
4313	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
4314	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
4315	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4316
4317	/*
4318	* Get the host and guest overrides so we don't reject the state because
4319	* some feature was enabled thru these interfaces.
4320	* Note! We currently only need the feature leaves, so skip rest.
4321	*/
4322	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4323	CPUMCPUID aHostOverrideStd[2];
4324	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4325	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4326
4327	CPUMCPUID aHostOverrideExt[2];
4328	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4329	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4330
4331	/*
4332	* This can be skipped.
4333	*/
4334	bool fStrictCpuIdChecks;
4335	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
4336
4337	/*
4338	* Define a bunch of macros for simplifying the santizing/checking code below.
4339	*/
4340	/* Generic expression + failure message. */
4341	#define CPUID_CHECK_RET(expr, fmt) \
4342	do { \
4343	if (!(expr)) \
4344	{ \
4345	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
4346	if (fStrictCpuIdChecks) \
4347	{ \
4348	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4349	RTStrFree(pszMsg); \
4350	return rcCpuid; \
4351	} \
4352	LogRel(("CPUM: %s\n", pszMsg)); \
4353	RTStrFree(pszMsg); \
4354	} \
4355	} while (0)
4356	#define CPUID_CHECK_WRN(expr, fmt) \
4357	do { \
4358	if (!(expr)) \
4359	LogRel(fmt); \
4360	} while (0)
4361
4362	/* For comparing two values and bitch if they differs. */
4363	#define CPUID_CHECK2_RET(what, host, saved) \
4364	do { \
4365	if ((host) != (saved)) \
4366	{ \
4367	if (fStrictCpuIdChecks) \
4368	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4369	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
4370	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4371	} \
4372	} while (0)
4373	#define CPUID_CHECK2_WRN(what, host, saved) \
4374	do { \
4375	if ((host) != (saved)) \
4376	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4377	} while (0)
4378
4379	/* For checking raw cpu features (raw mode). */
4380	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
4381	do { \
4382	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4383	{ \
4384	if (fStrictCpuIdChecks) \
4385	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4386	N_(#bit " mismatch: host=%d saved=%d"), \
4387	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
4388	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4389	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4390	} \
4391	} while (0)
4392	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
4393	do { \
4394	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4395	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4396	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4397	} while (0)
4398	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
4399
4400	/* For checking guest features. */
4401	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
4402	do { \
4403	if ( (aGuestCpuId##set [1].reg & bit) \
4404	&& !(aHostRaw##set [1].reg & bit) \
4405	&& !(aHostOverride##set [1].reg & bit) \
4406	) \
4407	{ \
4408	if (fStrictCpuIdChecks) \
4409	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4410	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4411	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4412	} \
4413	} while (0)
4414	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
4415	do { \
4416	if ( (aGuestCpuId##set [1].reg & bit) \
4417	&& !(aHostRaw##set [1].reg & bit) \
4418	&& !(aHostOverride##set [1].reg & bit) \
4419	) \
4420	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4421	} while (0)
4422	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
4423	do { \
4424	if ( (aGuestCpuId##set [1].reg & bit) \
4425	&& !(aHostRaw##set [1].reg & bit) \
4426	&& !(aHostOverride##set [1].reg & bit) \
4427	) \
4428	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4429	} while (0)
4430	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
4431
4432	/* For checking guest features if AMD guest CPU. */
4433	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
4434	do { \
4435	if ( (aGuestCpuId##set [1].reg & bit) \
4436	&& fGuestAmd \
4437	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4438	&& !(aHostOverride##set [1].reg & bit) \
4439	) \
4440	{ \
4441	if (fStrictCpuIdChecks) \
4442	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4443	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4444	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4445	} \
4446	} while (0)
4447	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
4448	do { \
4449	if ( (aGuestCpuId##set [1].reg & bit) \
4450	&& fGuestAmd \
4451	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4452	&& !(aHostOverride##set [1].reg & bit) \
4453	) \
4454	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4455	} while (0)
4456	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
4457	do { \
4458	if ( (aGuestCpuId##set [1].reg & bit) \
4459	&& fGuestAmd \
4460	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4461	&& !(aHostOverride##set [1].reg & bit) \
4462	) \
4463	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4464	} while (0)
4465	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
4466
4467	/* For checking AMD features which have a corresponding bit in the standard
4468	range. (Intel defines very few bits in the extended feature sets.) */
4469	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
4470	do { \
4471	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4472	&& !(fHostAmd \
4473	? aHostRawExt[1].reg & (ExtBit) \
4474	: aHostRawStd[1].reg & (StdBit)) \
4475	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4476	) \
4477	{ \
4478	if (fStrictCpuIdChecks) \
4479	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4480	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
4481	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4482	} \
4483	} while (0)
4484	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
4485	do { \
4486	if ( (aGuestCpuId[1].reg & (ExtBit)) \
4487	&& !(fHostAmd \
4488	? aHostRawExt[1].reg & (ExtBit) \
4489	: aHostRawStd[1].reg & (StdBit)) \
4490	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4491	) \
4492	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4493	} while (0)
4494	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
4495	do { \
4496	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4497	&& !(fHostAmd \
4498	? aHostRawExt[1].reg & (ExtBit) \
4499	: aHostRawStd[1].reg & (StdBit)) \
4500	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4501	) \
4502	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4503	} while (0)
4504	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
4505
4506	/*
4507	* For raw-mode we'll require that the CPUs are very similar since we don't
4508	* intercept CPUID instructions for user mode applications.
4509	*/
4510	if (!HMIsEnabled(pVM))
4511	{
4512	/* CPUID(0) */
4513	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
4514	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
4515	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
4516	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
4517	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
4518	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
4519	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
4520	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
4521	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
4522
4523	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
4524
4525	/* CPUID(1).eax */
4526	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
4527	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
4528	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
4529
4530	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
4531	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
4532	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
4533
4534	/* CPUID(1).ecx */
4535	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
4536	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
4537	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
4538	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4539	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
4540	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
4541	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
4542	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
4543	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
4544	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
4545	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
4546	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
4547	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
4548	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
4549	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
4550	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
4551	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
4552	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4553	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
4554	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
4555	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
4556	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4557	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
4558	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
4559	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4560	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
4561	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
4562	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4563	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
4564	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4565	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4566	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
4567
4568	/* CPUID(1).edx */
4569	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4570	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4571	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
4572	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4573	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
4574	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
4575	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4576	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4577	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
4578	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4579	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
4580	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4581	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4582	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4583	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4584	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
4585	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4586	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4587	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4588	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
4589	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
4590	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
4591	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
4592	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
4593	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
4594	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
4595	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
4596	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
4597	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
4598	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
4599	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
4600	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
4601
4602	/* CPUID(2) - config, mostly about caches. ignore. */
4603	/* CPUID(3) - processor serial number. ignore. */
4604	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
4605	/* CPUID(5) - mwait/monitor config. ignore. */
4606	/* CPUID(6) - power management. ignore. */
4607	/* CPUID(7) - ???. ignore. */
4608	/* CPUID(8) - ???. ignore. */
4609	/* CPUID(9) - DCA. ignore for now. */
4610	/* CPUID(a) - PeMo info. ignore for now. */
4611	/* CPUID(b) - topology info - takes ECX as input. ignore. */
4612
4613	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
4614	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
4615	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
4616	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
4617	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
4618	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
4619	{
4620	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
4621	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
4622	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
4623	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
4624	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
4625	}
4626
4627	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
4628	Note! Intel have/is marking many of the fields here as reserved. We
4629	will verify them as if it's an AMD CPU. */
4630	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
4631	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
4632	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
4633	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
4634	{
4635	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
4636	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
4637	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
4638	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
4639	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
4640	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
4641	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
4642
4643	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
4644	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
4645	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
4646	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
4647	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
4648	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
4649
4650	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
4651	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
4652	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
4653	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
4654
4655	/* CPUID(0x80000001).ecx */
4656	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
4657	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
4658	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
4659	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
4660	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
4661	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
4662	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
4663	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
4664	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
4665	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
4666	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
4667	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
4668	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
4669	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
4670	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4671	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4672	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4673	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4674	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4675	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4676	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4677	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4678	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4679	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4680	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4681	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4682	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4683	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4684	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4685	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4686	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4687	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4688
4689	/* CPUID(0x80000001).edx */
4690	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
4691	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
4692	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
4693	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
4694	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
4695	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
4696	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
4697	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
4698	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
4699	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
4700	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4701	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
4702	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
4703	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
4704	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
4705	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
4706	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
4707	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
4708	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4709	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4710	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4711	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
4712	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4713	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
4714	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
4715	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4716	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4717	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4718	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
4719	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4720	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4721	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4722
4723	/** @todo verify the rest as well. */
4724	}
4725	}
4726
4727
4728
4729	/*
4730	* Verify that we can support the features already exposed to the guest on
4731	* this host.
4732	*
4733	* Most of the features we're emulating requires intercepting instruction
4734	* and doing it the slow way, so there is no need to warn when they aren't
4735	* present in the host CPU. Thus we use IGN instead of EMU on these.
4736	*
4737	* Trailing comments:
4738	* "EMU" - Possible to emulate, could be lots of work and very slow.
4739	* "EMU?" - Can this be emulated?
4740	*/
4741	CPUMCPUID aGuestCpuIdStd[2];
4742	RT_ZERO(aGuestCpuIdStd);
4743	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
4744
4745	/* CPUID(1).ecx */
4746	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
4747	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
4748	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
4749	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4750	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
4751	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
4752	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
4753	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
4754	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
4755	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
4756	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
4757	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
4758	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
4759	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
4760	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
4761	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
4762	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
4763	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4764	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
4765	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
4766	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
4767	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4768	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
4769	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
4770	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4771	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
4772	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
4773	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4774	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
4775	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4776	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4777	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
4778
4779	/* CPUID(1).edx */
4780	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4781	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4782	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
4783	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4784	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4785	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4786	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4787	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4788	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4789	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4790	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
4791	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4792	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4793	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4794	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4795	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4796	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4797	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4798	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4799	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
4800	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
4801	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
4802	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
4803	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4804	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4805	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
4806	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
4807	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
4808	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
4809	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
4810	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
4811	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
4812
4813	/* CPUID(0x80000000). */
4814	CPUMCPUID aGuestCpuIdExt[2];
4815	RT_ZERO(aGuestCpuIdExt);
4816	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
4817	{
4818	/** @todo deal with no 0x80000001 on the host. */
4819	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
4820	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
4821
4822	/* CPUID(0x80000001).ecx */
4823	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
4824	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
4825	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
4826	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
4827	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
4828	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
4829	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
4830	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
4831	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
4832	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
4833	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
4834	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
4835	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
4836	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
4837	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4838	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4839	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4840	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4841	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4842	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4843	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4844	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4845	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4846	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4847	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4848	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4849	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4850	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4851	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4852	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4853	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4854	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4855
4856	/* CPUID(0x80000001).edx */
4857	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
4858	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
4859	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
4860	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
4861	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4862	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4863	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
4864	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
4865	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4866	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
4867	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4868	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
4869	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
4870	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
4871	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
4872	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4873	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
4874	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
4875	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4876	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4877	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4878	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
4879	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4880	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4881	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4882	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4883	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4884	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4885	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
4886	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4887	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4888	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4889	}
4890
4891	/** @todo check leaf 7 */
4892
4893	/* CPUID(d) - XCR0 stuff - takes ECX as input.
4894	* ECX=0: EAX - Valid bits in XCR0[31:0].
4895	* EBX - Maximum state size as per current XCR0 value.
4896	* ECX - Maximum state size for all supported features.
4897	* EDX - Valid bits in XCR0[63:32].
4898	* ECX=1: EAX - Various X-features.
4899	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
4900	* ECX - Valid bits in IA32_XSS[31:0].
4901	* EDX - Valid bits in IA32_XSS[63:32].
4902	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
4903	* if the bit invalid all four registers are set to zero.
4904	* EAX - The state size for this feature.
4905	* EBX - The state byte offset of this feature.
4906	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
4907	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
4908	*/
4909	uint64_t fGuestXcr0Mask = 0;
4910	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
4911	if ( pCurLeaf
4912	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
4913	&& ( pCurLeaf->uEax
4914	\|\| pCurLeaf->uEbx
4915	\|\| pCurLeaf->uEcx
4916	\|\| pCurLeaf->uEdx) )
4917	{
4918	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
4919	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
4920	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4921	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
4922	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
4923	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
4924	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4925	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
4926
4927	/* We don't support any additional features yet. */
4928	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
4929	if (pCurLeaf && pCurLeaf->uEax)
4930	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4931	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
4932	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
4933	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4934	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
4935	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
4936
4937
4938	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
4939	{
4940	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4941	if (pCurLeaf)
4942	{
4943	/* If advertised, the state component offset and size must match the one used by host. */
4944	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
4945	{
4946	CPUMCPUID RawHost;
4947	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
4948	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
4949	if ( RawHost.uEbx != pCurLeaf->uEbx
4950	\|\| RawHost.uEax != pCurLeaf->uEax)
4951	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4952	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
4953	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
4954	}
4955	}
4956	}
4957	}
4958	/* Clear leaf 0xd just in case we're loading an old state... */
4959	else if (pCurLeaf)
4960	{
4961	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
4962	{
4963	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4964	if (pCurLeaf)
4965	{
4966	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
4967	\|\| ( pCurLeaf->uEax == 0
4968	&& pCurLeaf->uEbx == 0
4969	&& pCurLeaf->uEcx == 0
4970	&& pCurLeaf->uEdx == 0),
4971	("uVersion=%#x; %#x %#x %#x %#x\n",
4972	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
4973	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
4974	}
4975	}
4976	}
4977
4978	/* Update the fXStateGuestMask value for the VM. */
4979	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
4980	{
4981	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
4982	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
4983	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
4984	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4985	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
4986	}
4987
4988	#undef CPUID_CHECK_RET
4989	#undef CPUID_CHECK_WRN
4990	#undef CPUID_CHECK2_RET
4991	#undef CPUID_CHECK2_WRN
4992	#undef CPUID_RAW_FEATURE_RET
4993	#undef CPUID_RAW_FEATURE_WRN
4994	#undef CPUID_RAW_FEATURE_IGN
4995	#undef CPUID_GST_FEATURE_RET
4996	#undef CPUID_GST_FEATURE_WRN
4997	#undef CPUID_GST_FEATURE_EMU
4998	#undef CPUID_GST_FEATURE_IGN
4999	#undef CPUID_GST_FEATURE2_RET
5000	#undef CPUID_GST_FEATURE2_WRN
5001	#undef CPUID_GST_FEATURE2_EMU
5002	#undef CPUID_GST_FEATURE2_IGN
5003	#undef CPUID_GST_AMD_FEATURE_RET
5004	#undef CPUID_GST_AMD_FEATURE_WRN
5005	#undef CPUID_GST_AMD_FEATURE_EMU
5006	#undef CPUID_GST_AMD_FEATURE_IGN
5007
5008	/*
5009	* We're good, commit the CPU ID leaves.
5010	*/
5011	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5012	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5013	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5014	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
5015	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5016	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
5017	AssertLogRelRCReturn(rc, rc);
5018
5019	return VINF_SUCCESS;
5020	}
5021
5022
5023	/**
5024	* Loads the CPU ID leaves saved by pass 0.
5025	*
5026	* @returns VBox status code.
5027	* @param pVM Pointer to the VM.
5028	* @param pSSM The saved state handle.
5029	* @param uVersion The format version.
5030	*/
5031	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5032	{
5033	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5034
5035	/*
5036	* Load the CPUID leaves array first and call worker to do the rest, just so
5037	* we can free the memory when we need to without ending up in column 1000.
5038	*/
5039	PCPUMCPUIDLEAF paLeaves;
5040	uint32_t cLeaves;
5041	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5042	AssertRC(rc);
5043	if (RT_SUCCESS(rc))
5044	{
5045	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
5046	RTMemFree(paLeaves);
5047	}
5048	return rc;
5049	}
5050
5051
5052
5053	/**
5054	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5055	*
5056	* @returns VBox status code.
5057	* @param pVM Pointer to the VM.
5058	* @param pSSM The saved state handle.
5059	* @param uVersion The format version.
5060	*/
5061	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5062	{
5063	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5064
5065	/*
5066	* Restore the CPUID leaves.
5067	*
5068	* Note that we support restoring less than the current amount of standard
5069	* leaves because we've been allowed more is newer version of VBox.
5070	*/
5071	uint32_t cElements;
5072	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5073	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5074	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5075	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5076
5077	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5078	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5079	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5080	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5081
5082	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5083	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5084	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5085	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5086
5087	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5088
5089	/*
5090	* Check that the basic cpuid id information is unchanged.
5091	*/
5092	/** @todo we should check the 64 bits capabilities too! */
5093	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5094	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5095	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5096	uint32_t au32CpuIdSaved[8];
5097	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5098	if (RT_SUCCESS(rc))
5099	{
5100	/* Ignore CPU stepping. */
5101	au32CpuId[4] &= 0xfffffff0;
5102	au32CpuIdSaved[4] &= 0xfffffff0;
5103
5104	/* Ignore APIC ID (AMD specs). */
5105	au32CpuId[5] &= ~0xff000000;
5106	au32CpuIdSaved[5] &= ~0xff000000;
5107
5108	/* Ignore the number of Logical CPUs (AMD specs). */
5109	au32CpuId[5] &= ~0x00ff0000;
5110	au32CpuIdSaved[5] &= ~0x00ff0000;
5111
5112	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5113	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5114	\| X86_CPUID_FEATURE_ECX_VMX
5115	\| X86_CPUID_FEATURE_ECX_SMX
5116	\| X86_CPUID_FEATURE_ECX_EST
5117	\| X86_CPUID_FEATURE_ECX_TM2
5118	\| X86_CPUID_FEATURE_ECX_CNTXID
5119	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5120	\| X86_CPUID_FEATURE_ECX_PDCM
5121	\| X86_CPUID_FEATURE_ECX_DCA
5122	\| X86_CPUID_FEATURE_ECX_X2APIC
5123	);
5124	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5125	\| X86_CPUID_FEATURE_ECX_VMX
5126	\| X86_CPUID_FEATURE_ECX_SMX
5127	\| X86_CPUID_FEATURE_ECX_EST
5128	\| X86_CPUID_FEATURE_ECX_TM2
5129	\| X86_CPUID_FEATURE_ECX_CNTXID
5130	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5131	\| X86_CPUID_FEATURE_ECX_PDCM
5132	\| X86_CPUID_FEATURE_ECX_DCA
5133	\| X86_CPUID_FEATURE_ECX_X2APIC
5134	);
5135
5136	/* Make sure we don't forget to update the masks when enabling
5137	* features in the future.
5138	*/
5139	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5140	( X86_CPUID_FEATURE_ECX_DTES64
5141	\| X86_CPUID_FEATURE_ECX_VMX
5142	\| X86_CPUID_FEATURE_ECX_SMX
5143	\| X86_CPUID_FEATURE_ECX_EST
5144	\| X86_CPUID_FEATURE_ECX_TM2
5145	\| X86_CPUID_FEATURE_ECX_CNTXID
5146	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5147	\| X86_CPUID_FEATURE_ECX_PDCM
5148	\| X86_CPUID_FEATURE_ECX_DCA
5149	\| X86_CPUID_FEATURE_ECX_X2APIC
5150	)));
5151	/* do the compare */
5152	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5153	{
5154	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5155	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5156	"Saved=%.*Rhxs\n"
5157	"Real =%.*Rhxs\n",
5158	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5159	sizeof(au32CpuId), au32CpuId));
5160	else
5161	{
5162	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5163	"Saved=%.*Rhxs\n"
5164	"Real =%.*Rhxs\n",
5165	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5166	sizeof(au32CpuId), au32CpuId));
5167	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5168	}
5169	}
5170	}
5171
5172	return rc;
5173	}
5174
5175
5176
5177	/*
5178	*
5179	*
5180	* CPUID Info Handler.
5181	* CPUID Info Handler.
5182	* CPUID Info Handler.
5183	*
5184	*
5185	*/
5186
5187
5188
5189	/**
5190	* Get L1 cache / TLS associativity.
5191	*/
5192	static const char getCacheAss(unsigned u, char pszBuf)
5193	{
5194	if (u == 0)
5195	return "res0 ";
5196	if (u == 1)
5197	return "direct";
5198	if (u == 255)
5199	return "fully";
5200	if (u >= 256)
5201	return "???";
5202
5203	RTStrPrintf(pszBuf, 16, "%d way", u);
5204	return pszBuf;
5205	}
5206
5207
5208	/**
5209	* Get L2 cache associativity.
5210	*/
5211	const char *getL2CacheAss(unsigned u)
5212	{
5213	switch (u)
5214	{
5215	case 0: return "off ";
5216	case 1: return "direct";
5217	case 2: return "2 way ";
5218	case 3: return "res3 ";
5219	case 4: return "4 way ";
5220	case 5: return "res5 ";
5221	case 6: return "8 way ";
5222	case 7: return "res7 ";
5223	case 8: return "16 way";
5224	case 9: return "res9 ";
5225	case 10: return "res10 ";
5226	case 11: return "res11 ";
5227	case 12: return "res12 ";
5228	case 13: return "res13 ";
5229	case 14: return "res14 ";
5230	case 15: return "fully ";
5231	default: return "????";
5232	}
5233	}
5234
5235
5236	/** CPUID(1).EDX field descriptions. */
5237	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
5238	{
5239	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5240	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5241	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5242	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5243	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5244	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
5245	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5246	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5247	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5248	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5249	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
5250	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5251	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5252	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5253	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5254	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5255	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5256	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
5257	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
5258	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
5259	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
5260	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5261	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
5262	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
5263	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
5264	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
5265	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
5266	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
5267	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
5268	DBGFREGSUBFIELD_TERMINATOR()
5269	};
5270
5271	/** CPUID(1).ECX field descriptions. */
5272	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
5273	{
5274	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
5275	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
5276	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
5277	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
5278	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
5279	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
5280	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
5281	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
5282	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
5283	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
5284	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
5285	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
5286	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
5287	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
5288	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
5289	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
5290	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
5291	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
5292	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
5293	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
5294	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
5295	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
5296	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
5297	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
5298	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
5299	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
5300	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
5301	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
5302	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
5303	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
5304	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
5305	DBGFREGSUBFIELD_TERMINATOR()
5306	};
5307
5308	/** CPUID(7,0).EBX field descriptions. */
5309	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
5310	{
5311	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
5312	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
5313	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
5314	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
5315	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
5316	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
5317	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
5318	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
5319	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
5320	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
5321	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
5322	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
5323	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
5324	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
5325	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
5326	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
5327	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
5328	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
5329	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
5330	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
5331	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
5332	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
5333	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
5334	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
5335	DBGFREGSUBFIELD_TERMINATOR()
5336	};
5337
5338	/** CPUID(7,0).ECX field descriptions. */
5339	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
5340	{
5341	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
5342	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
5343	DBGFREGSUBFIELD_RO("OSPKU\0" "CR4.PKU mirror", 4, 1, 0),
5344	DBGFREGSUBFIELD_TERMINATOR()
5345	};
5346
5347
5348	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
5349	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
5350	{
5351	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
5352	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
5353	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
5354	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
5355	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
5356	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
5357	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
5358	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
5359	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
5360	DBGFREGSUBFIELD_TERMINATOR()
5361	};
5362
5363	/** CPUID(13,1).EAX field descriptions. */
5364	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
5365	{
5366	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
5367	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
5368	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
5369	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
5370	DBGFREGSUBFIELD_TERMINATOR()
5371	};
5372
5373
5374	/** CPUID(0x80000001,0).EDX field descriptions. */
5375	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
5376	{
5377	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5378	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5379	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5380	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5381	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5382	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
5383	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5384	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5385	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5386	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5387	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
5388	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5389	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5390	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5391	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5392	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5393	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5394	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
5395	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
5396	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5397	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
5398	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
5399	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
5400	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
5401	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
5402	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
5403	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
5404	DBGFREGSUBFIELD_TERMINATOR()
5405	};
5406
5407	/** CPUID(0x80000001,0).ECX field descriptions. */
5408	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
5409	{
5410	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
5411	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
5412	DBGFREGSUBFIELD_RO("SVM\0" "AMD VM extensions", 2, 1, 0),
5413	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
5414	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
5415	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
5416	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
5417	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
5418	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
5419	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
5420	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
5421	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
5422	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
5423	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
5424	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
5425	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
5426	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
5427	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
5428	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
5429	DBGFREGSUBFIELD_TERMINATOR()
5430	};
5431
5432
5433	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
5434	const char *pszLeadIn, uint32_t cchWidth)
5435	{
5436	if (pszLeadIn)
5437	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5438
5439	for (uint32_t iBit = 0; iBit < 32; iBit++)
5440	if (RT_BIT_32(iBit) & uVal)
5441	{
5442	while ( pDesc->pszName != NULL
5443	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5444	pDesc++;
5445	if ( pDesc->pszName != NULL
5446	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5447	{
5448	if (pDesc->cBits == 1)
5449	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5450	else
5451	{
5452	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
5453	if (pDesc->cBits < 32)
5454	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5455	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
5456	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5457	}
5458	}
5459	else
5460	pHlp->pfnPrintf(pHlp, " %u", iBit);
5461	}
5462	if (pszLeadIn)
5463	pHlp->pfnPrintf(pHlp, "\n");
5464	}
5465
5466
5467	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5468	const char *pszLeadIn, uint32_t cchWidth)
5469	{
5470	if (pszLeadIn)
5471	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5472
5473	for (uint32_t iBit = 0; iBit < 64; iBit++)
5474	if (RT_BIT_64(iBit) & uVal)
5475	{
5476	while ( pDesc->pszName != NULL
5477	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5478	pDesc++;
5479	if ( pDesc->pszName != NULL
5480	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5481	{
5482	if (pDesc->cBits == 1)
5483	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5484	else
5485	{
5486	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
5487	if (pDesc->cBits < 64)
5488	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
5489	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
5490	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5491	}
5492	}
5493	else
5494	pHlp->pfnPrintf(pHlp, " %u", iBit);
5495	}
5496	if (pszLeadIn)
5497	pHlp->pfnPrintf(pHlp, "\n");
5498	}
5499
5500
5501	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5502	const char *pszLeadIn, uint32_t cchWidth)
5503	{
5504	if (!uVal)
5505	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5506	else
5507	{
5508	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5509	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
5510	pHlp->pfnPrintf(pHlp, " )\n");
5511	}
5512	}
5513
5514
5515	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
5516	uint32_t cchWidth)
5517	{
5518	uint32_t uCombined = uVal1 \| uVal2;
5519	for (uint32_t iBit = 0; iBit < 32; iBit++)
5520	if ( (RT_BIT_32(iBit) & uCombined)
5521	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
5522	{
5523	while ( pDesc->pszName != NULL
5524	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5525	pDesc++;
5526
5527	if ( pDesc->pszName != NULL
5528	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5529	{
5530	size_t cchMnemonic = strlen(pDesc->pszName);
5531	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
5532	size_t cchDesc = strlen(pszDesc);
5533	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
5534	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
5535	if (pDesc->cBits < 32)
5536	{
5537	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5538	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5539	}
5540
5541	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
5542	pDesc->pszName, pszDesc,
5543	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
5544	uFieldValue1, uFieldValue2);
5545
5546	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
5547	pDesc++;
5548	}
5549	else
5550	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
5551	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
5552	}
5553	}
5554
5555
5556	/**
5557	* Produces a detailed summary of standard leaf 0x00000001.
5558	*
5559	* @param pHlp The info helper functions.
5560	* @param paLeaves The CPUID leaves array.
5561	* @param cLeaves The number of leaves in the array.
5562	* @param pCurLeaf The 0x00000001 leaf.
5563	* @param fVerbose Whether to be very verbose or not.
5564	* @param fIntel Set if intel CPU.
5565	*/
5566	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5567	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
5568	{
5569	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
5570	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
5571	uint32_t uEAX = pCurLeaf->uEax;
5572	uint32_t uEBX = pCurLeaf->uEbx;
5573
5574	pHlp->pfnPrintf(pHlp,
5575	"%36s %2d \tExtended: %d \tEffective: %d\n"
5576	"%36s %2d \tExtended: %d \tEffective: %d\n"
5577	"%36s %d\n"
5578	"%36s %d (%s)\n"
5579	"%36s %#04x\n"
5580	"%36s %d\n"
5581	"%36s %d\n"
5582	"%36s %#04x\n"
5583	,
5584	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
5585	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
5586	"Stepping:", ASMGetCpuStepping(uEAX),
5587	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
5588	"APIC ID:", (uEBX >> 24) & 0xff,
5589	"Logical CPUs:",(uEBX >> 16) & 0xff,
5590	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
5591	"Brand ID:", (uEBX >> 0) & 0xff);
5592	if (fVerbose)
5593	{
5594	CPUMCPUID Host;
5595	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5596	pHlp->pfnPrintf(pHlp, "Features\n");
5597	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5598	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
5599	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
5600	}
5601	else
5602	{
5603	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
5604	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
5605	}
5606	}
5607
5608
5609	/**
5610	* Produces a detailed summary of standard leaf 0x00000007.
5611	*
5612	* @param pHlp The info helper functions.
5613	* @param paLeaves The CPUID leaves array.
5614	* @param cLeaves The number of leaves in the array.
5615	* @param pCurLeaf The first 0x00000007 leaf.
5616	* @param fVerbose Whether to be very verbose or not.
5617	*/
5618	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5619	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5620	{
5621	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
5622	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
5623	for (;;)
5624	{
5625	CPUMCPUID Host;
5626	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5627
5628	switch (pCurLeaf->uSubLeaf)
5629	{
5630	case 0:
5631	if (fVerbose)
5632	{
5633	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5634	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
5635	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
5636	if (pCurLeaf->uEdx \|\| Host.uEdx)
5637	pHlp->pfnPrintf(pHlp, "%36 %#x (%#x)\n", "Ext Features EDX:", pCurLeaf->uEdx, Host.uEdx);
5638	}
5639	else
5640	{
5641	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
5642	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
5643	if (pCurLeaf->uEdx)
5644	pHlp->pfnPrintf(pHlp, "%36 %#x\n", "Ext Features EDX:", pCurLeaf->uEdx);
5645	}
5646	break;
5647
5648	default:
5649	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
5650	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
5651	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
5652	break;
5653
5654	}
5655
5656	/* advance. */
5657	pCurLeaf++;
5658	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5659	\|\| pCurLeaf->uLeaf != 0x7)
5660	break;
5661	}
5662	}
5663
5664
5665	/**
5666	* Produces a detailed summary of standard leaf 0x0000000d.
5667	*
5668	* @param pHlp The info helper functions.
5669	* @param paLeaves The CPUID leaves array.
5670	* @param cLeaves The number of leaves in the array.
5671	* @param pCurLeaf The first 0x00000007 leaf.
5672	* @param fVerbose Whether to be very verbose or not.
5673	*/
5674	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5675	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5676	{
5677	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
5678	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
5679	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5680	{
5681	CPUMCPUID Host;
5682	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5683
5684	switch (uSubLeaf)
5685	{
5686	case 0:
5687	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5688	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
5689	pCurLeaf->uEbx, pCurLeaf->uEcx);
5690	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
5691
5692	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5693	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
5694	"Valid XCR0 bits, guest:", 42);
5695	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
5696	"Valid XCR0 bits, host:", 42);
5697	break;
5698
5699	case 1:
5700	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5701	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
5702	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
5703
5704	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5705	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
5706	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
5707
5708	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5709	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
5710	" Valid IA32_XSS bits, guest:", 42);
5711	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
5712	" Valid IA32_XSS bits, host:", 42);
5713	break;
5714
5715	default:
5716	if ( pCurLeaf
5717	&& pCurLeaf->uSubLeaf == uSubLeaf
5718	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
5719	{
5720	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
5721	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5722	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
5723	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
5724	if (pCurLeaf->uEdx)
5725	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
5726	pHlp->pfnPrintf(pHlp, " --");
5727	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5728	pHlp->pfnPrintf(pHlp, "\n");
5729	}
5730	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
5731	{
5732	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
5733	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5734	if (Host.uEcx & ~RT_BIT_32(0))
5735	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
5736	if (Host.uEdx)
5737	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
5738	pHlp->pfnPrintf(pHlp, " --");
5739	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5740	pHlp->pfnPrintf(pHlp, "\n");
5741	}
5742	break;
5743
5744	}
5745
5746	/* advance. */
5747	if (pCurLeaf)
5748	{
5749	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5750	&& pCurLeaf->uSubLeaf <= uSubLeaf
5751	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
5752	pCurLeaf++;
5753	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5754	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
5755	pCurLeaf = NULL;
5756	}
5757	}
5758	}
5759
5760
5761	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5762	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
5763	{
5764	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5765	&& pCurLeaf->uLeaf <= uUpToLeaf)
5766	{
5767	pHlp->pfnPrintf(pHlp,
5768	" %s\n"
5769	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
5770	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5771	&& pCurLeaf->uLeaf <= uUpToLeaf)
5772	{
5773	CPUMCPUID Host;
5774	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5775	pHlp->pfnPrintf(pHlp,
5776	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5777	"Hst: %08x %08x %08x %08x\n",
5778	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5779	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5780	pCurLeaf++;
5781	}
5782	}
5783
5784	return pCurLeaf;
5785	}
5786
5787
5788	/**
5789	* Display the guest CpuId leaves.
5790	*
5791	* @param pVM Pointer to the VM.
5792	* @param pHlp The info helper functions.
5793	* @param pszArgs "terse", "default" or "verbose".
5794	*/
5795	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
5796	{
5797	/*
5798	* Parse the argument.
5799	*/
5800	unsigned iVerbosity = 1;
5801	if (pszArgs)
5802	{
5803	pszArgs = RTStrStripL(pszArgs);
5804	if (!strcmp(pszArgs, "terse"))
5805	iVerbosity--;
5806	else if (!strcmp(pszArgs, "verbose"))
5807	iVerbosity++;
5808	}
5809
5810	uint32_t uLeaf;
5811	CPUMCPUID Host;
5812	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
5813	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
5814	PCCPUMCPUIDLEAF pCurLeaf;
5815	PCCPUMCPUIDLEAF pNextLeaf;
5816	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
5817	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
5818	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
5819
5820	/*
5821	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
5822	*/
5823	uint32_t cHstMax = ASMCpuId_EAX(0);
5824	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
5825	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
5826	pHlp->pfnPrintf(pHlp,
5827	" Raw Standard CPUID Leaves\n"
5828	" Leaf/sub-leaf eax ebx ecx edx\n");
5829	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
5830	{
5831	uint32_t cMaxSubLeaves = 1;
5832	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
5833	cMaxSubLeaves = 16;
5834	else if (uLeaf == 0xd)
5835	cMaxSubLeaves = 128;
5836
5837	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5838	{
5839	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5840	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5841	&& pCurLeaf->uLeaf == uLeaf
5842	&& pCurLeaf->uSubLeaf == uSubLeaf)
5843	{
5844	pHlp->pfnPrintf(pHlp,
5845	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5846	"Hst: %08x %08x %08x %08x\n",
5847	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5848	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5849	pCurLeaf++;
5850	}
5851	else if ( uLeaf != 0xd
5852	\|\| uSubLeaf <= 1
5853	\|\| Host.uEbx != 0 )
5854	pHlp->pfnPrintf(pHlp,
5855	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5856	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5857
5858	/* Done? */
5859	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5860	\|\| pCurLeaf->uLeaf != uLeaf)
5861	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
5862	\|\| (uLeaf == 0x7 && Host.uEax == 0)
5863	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
5864	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
5865	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
5866	)
5867	)
5868	break;
5869	}
5870	}
5871	pNextLeaf = pCurLeaf;
5872
5873	/*
5874	* If verbose, decode it.
5875	*/
5876	if (iVerbosity && paLeaves[0].uLeaf == 0)
5877	pHlp->pfnPrintf(pHlp,
5878	"%36s %.04s%.04s%.04s\n"
5879	"%36s 0x00000000-%#010x\n"
5880	,
5881	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
5882	"Supports:", paLeaves[0].uEax);
5883
5884	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
5885	cpumR3CpuIdInfoStdLeaf1Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1, fIntel);
5886
5887	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
5888	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5889
5890	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
5891	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5892
5893	pCurLeaf = pNextLeaf;
5894
5895	/*
5896	* Hypervisor leaves.
5897	*
5898	* Unlike most of the other leaves reported, the guest hypervisor leaves
5899	* aren't a subset of the host CPUID bits.
5900	*/
5901	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
5902
5903	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5904	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
5905	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
5906	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
5907	cMax = RT_MAX(cHstMax, cGstMax);
5908	if (cMax >= UINT32_C(0x40000000))
5909	{
5910	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
5911
5912	/** @todo dump these in more detail. */
5913
5914	pCurLeaf = pNextLeaf;
5915	}
5916
5917
5918	/*
5919	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
5920	* Implemented after AMD specs.
5921	*/
5922	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
5923
5924	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5925	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
5926	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
5927	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
5928	cMax = RT_MAX(cHstMax, cGstMax);
5929	if (cMax >= UINT32_C(0x80000000))
5930	{
5931
5932	pHlp->pfnPrintf(pHlp,
5933	" Raw Extended CPUID Leaves\n"
5934	" Leaf/sub-leaf eax ebx ecx edx\n");
5935	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
5936	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
5937	{
5938	uint32_t cMaxSubLeaves = 1;
5939	if (uLeaf == UINT32_C(0x8000001d))
5940	cMaxSubLeaves = 16;
5941
5942	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5943	{
5944	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5945	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5946	&& pCurLeaf->uLeaf == uLeaf
5947	&& pCurLeaf->uSubLeaf == uSubLeaf)
5948	{
5949	pHlp->pfnPrintf(pHlp,
5950	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5951	"Hst: %08x %08x %08x %08x\n",
5952	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5953	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5954	pCurLeaf++;
5955	}
5956	else if ( uLeaf != 0xd
5957	\|\| uSubLeaf <= 1
5958	\|\| Host.uEbx != 0 )
5959	pHlp->pfnPrintf(pHlp,
5960	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5961	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5962
5963	/* Done? */
5964	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5965	\|\| pCurLeaf->uLeaf != uLeaf)
5966	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
5967	break;
5968	}
5969	}
5970	pNextLeaf = pCurLeaf;
5971
5972	/*
5973	* Understandable output
5974	*/
5975	if (iVerbosity)
5976	pHlp->pfnPrintf(pHlp,
5977	"Ext Name: %.4s%.4s%.4s\n"
5978	"Ext Supports: 0x80000000-%#010x\n",
5979	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
5980
5981	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
5982	if (iVerbosity && pCurLeaf)
5983	{
5984	uint32_t uEAX = pCurLeaf->uEax;
5985	pHlp->pfnPrintf(pHlp,
5986	"Family: %d \tExtended: %d \tEffective: %d\n"
5987	"Model: %d \tExtended: %d \tEffective: %d\n"
5988	"Stepping: %d\n"
5989	"Brand ID: %#05x\n",
5990	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
5991	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
5992	ASMGetCpuStepping(uEAX),
5993	pCurLeaf->uEbx & 0xfff);
5994
5995	if (iVerbosity == 1)
5996	{
5997	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
5998	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
5999	}
6000	else
6001	{
6002	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6003	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6004	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6005	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6006	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6007	}
6008	}
6009
6010	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6011	{
6012	char szString[443+1] = {0};
6013	uint32_t pu32 = (uint32_t )szString;
6014	*pu32++ = pCurLeaf->uEax;
6015	*pu32++ = pCurLeaf->uEbx;
6016	*pu32++ = pCurLeaf->uEcx;
6017	*pu32++ = pCurLeaf->uEdx;
6018	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6019	if (pCurLeaf)
6020	{
6021	*pu32++ = pCurLeaf->uEax;
6022	*pu32++ = pCurLeaf->uEbx;
6023	*pu32++ = pCurLeaf->uEcx;
6024	*pu32++ = pCurLeaf->uEdx;
6025	}
6026	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6027	if (pCurLeaf)
6028	{
6029	*pu32++ = pCurLeaf->uEax;
6030	*pu32++ = pCurLeaf->uEbx;
6031	*pu32++ = pCurLeaf->uEcx;
6032	*pu32++ = pCurLeaf->uEdx;
6033	}
6034	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6035	}
6036
6037	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6038	{
6039	uint32_t uEAX = pCurLeaf->uEax;
6040	uint32_t uEBX = pCurLeaf->uEbx;
6041	uint32_t uECX = pCurLeaf->uEcx;
6042	uint32_t uEDX = pCurLeaf->uEdx;
6043	char sz1[32];
6044	char sz2[32];
6045
6046	pHlp->pfnPrintf(pHlp,
6047	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6048	"TLB 2/4M Data: %s %3d entries\n",
6049	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6050	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6051	pHlp->pfnPrintf(pHlp,
6052	"TLB 4K Instr/Uni: %s %3d entries\n"
6053	"TLB 4K Data: %s %3d entries\n",
6054	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6055	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6056	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6057	"L1 Instr Cache Lines Per Tag: %d\n"
6058	"L1 Instr Cache Associativity: %s\n"
6059	"L1 Instr Cache Size: %d KB\n",
6060	(uEDX >> 0) & 0xff,
6061	(uEDX >> 8) & 0xff,
6062	getCacheAss((uEDX >> 16) & 0xff, sz1),
6063	(uEDX >> 24) & 0xff);
6064	pHlp->pfnPrintf(pHlp,
6065	"L1 Data Cache Line Size: %d bytes\n"
6066	"L1 Data Cache Lines Per Tag: %d\n"
6067	"L1 Data Cache Associativity: %s\n"
6068	"L1 Data Cache Size: %d KB\n",
6069	(uECX >> 0) & 0xff,
6070	(uECX >> 8) & 0xff,
6071	getCacheAss((uECX >> 16) & 0xff, sz1),
6072	(uECX >> 24) & 0xff);
6073	}
6074
6075	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6076	{
6077	uint32_t uEAX = pCurLeaf->uEax;
6078	uint32_t uEBX = pCurLeaf->uEbx;
6079	uint32_t uEDX = pCurLeaf->uEdx;
6080
6081	pHlp->pfnPrintf(pHlp,
6082	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6083	"L2 TLB 2/4M Data: %s %4d entries\n",
6084	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6085	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6086	pHlp->pfnPrintf(pHlp,
6087	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6088	"L2 TLB 4K Data: %s %4d entries\n",
6089	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6090	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6091	pHlp->pfnPrintf(pHlp,
6092	"L2 Cache Line Size: %d bytes\n"
6093	"L2 Cache Lines Per Tag: %d\n"
6094	"L2 Cache Associativity: %s\n"
6095	"L2 Cache Size: %d KB\n",
6096	(uEDX >> 0) & 0xff,
6097	(uEDX >> 8) & 0xf,
6098	getL2CacheAss((uEDX >> 12) & 0xf),
6099	(uEDX >> 16) & 0xffff);
6100	}
6101
6102	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
6103	{
6104	uint32_t uEDX = pCurLeaf->uEdx;
6105
6106	pHlp->pfnPrintf(pHlp, "APM Features: ");
6107	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
6108	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
6109	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
6110	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
6111	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
6112	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
6113	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " MC");
6114	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " HWPSTATE");
6115	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TscInvariant");
6116	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " CPB");
6117	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " EffFreqRO");
6118	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PFI");
6119	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PA");
6120	for (unsigned iBit = 13; iBit < 32; iBit++)
6121	if (uEDX & RT_BIT(iBit))
6122	pHlp->pfnPrintf(pHlp, " %d", iBit);
6123	pHlp->pfnPrintf(pHlp, "\n");
6124
6125	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6126	pHlp->pfnPrintf(pHlp, "Host Invariant-TSC support: %RTbool\n",
6127	cHstMax >= UINT32_C(0x80000007) && (Host.uEdx & RT_BIT(8)));
6128
6129	}
6130
6131	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0)) != NULL)
6132	{
6133	uint32_t uEAX = pCurLeaf->uEax;
6134	uint32_t uECX = pCurLeaf->uEcx;
6135
6136	pHlp->pfnPrintf(pHlp,
6137	"Physical Address Width: %d bits\n"
6138	"Virtual Address Width: %d bits\n"
6139	"Guest Physical Address Width: %d bits\n",
6140	(uEAX >> 0) & 0xff,
6141	(uEAX >> 8) & 0xff,
6142	(uEAX >> 16) & 0xff);
6143	pHlp->pfnPrintf(pHlp,
6144	"Physical Core Count: %d\n",
6145	(uECX >> 0) & 0xff);
6146	}
6147
6148	pCurLeaf = pNextLeaf;
6149	}
6150
6151
6152
6153	/*
6154	* Centaur.
6155	*/
6156	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
6157
6158	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6159	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
6160	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
6161	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
6162	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
6163	cMax = RT_MAX(cHstMax, cGstMax);
6164	if (cMax >= UINT32_C(0xc0000000))
6165	{
6166	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
6167
6168	/*
6169	* Understandable output
6170	*/
6171	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
6172	pHlp->pfnPrintf(pHlp,
6173	"Centaur Supports: 0xc0000000-%#010x\n",
6174	pCurLeaf->uEax);
6175
6176	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
6177	{
6178	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6179	uint32_t uEdxGst = pCurLeaf->uEdx;
6180	uint32_t uEdxHst = Host.uEdx;
6181
6182	if (iVerbosity == 1)
6183	{
6184	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
6185	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
6186	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
6187	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
6188	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
6189	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
6190	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
6191	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
6192	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
6193	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6194	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
6195	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
6196	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
6197	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
6198	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
6199	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
6200	for (unsigned iBit = 14; iBit < 32; iBit++)
6201	if (uEdxGst & RT_BIT(iBit))
6202	pHlp->pfnPrintf(pHlp, " %d", iBit);
6203	pHlp->pfnPrintf(pHlp, "\n");
6204	}
6205	else
6206	{
6207	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
6208	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
6209	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
6210	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
6211	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
6212	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
6213	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
6214	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
6215	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
6216	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6217	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
6218	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
6219	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
6220	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
6221	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
6222	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
6223	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
6224	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
6225	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
6226	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
6227	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
6228	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
6229	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
6230	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
6231	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
6232	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
6233	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
6234	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
6235	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
6236	for (unsigned iBit = 27; iBit < 32; iBit++)
6237	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
6238	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
6239	pHlp->pfnPrintf(pHlp, "\n");
6240	}
6241	}
6242
6243	pCurLeaf = pNextLeaf;
6244	}
6245
6246	/*
6247	* The remainder.
6248	*/
6249	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
6250	}
6251
6252
6253
6254
6255
6256	/*
6257	*
6258	*
6259	* PATM interfaces.
6260	* PATM interfaces.
6261	* PATM interfaces.
6262	*
6263	*
6264	*/
6265
6266
6267	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
6268	/** @name Patchmanager CPUID legacy table APIs
6269	* @{
6270	*/
6271
6272	/**
6273	* Gets a pointer to the default CPUID leaf.
6274	*
6275	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
6276	* @param pVM Pointer to the VM.
6277	* @remark Intended for PATM only.
6278	*/
6279	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
6280	{
6281	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
6282	}
6283
6284
6285	/**
6286	* Gets a number of standard CPUID leaves (PATM only).
6287	*
6288	* @returns Number of leaves.
6289	* @param pVM Pointer to the VM.
6290	* @remark Intended for PATM - legacy, don't use in new code.
6291	*/
6292	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
6293	{
6294	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
6295	}
6296
6297
6298	/**
6299	* Gets a number of extended CPUID leaves (PATM only).
6300	*
6301	* @returns Number of leaves.
6302	* @param pVM Pointer to the VM.
6303	* @remark Intended for PATM - legacy, don't use in new code.
6304	*/
6305	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
6306	{
6307	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
6308	}
6309
6310
6311	/**
6312	* Gets a number of centaur CPUID leaves.
6313	*
6314	* @returns Number of leaves.
6315	* @param pVM Pointer to the VM.
6316	* @remark Intended for PATM - legacy, don't use in new code.
6317	*/
6318	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
6319	{
6320	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
6321	}
6322
6323
6324	/**
6325	* Gets a pointer to the array of standard CPUID leaves.
6326	*
6327	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
6328	*
6329	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
6330	* @param pVM Pointer to the VM.
6331	* @remark Intended for PATM - legacy, don't use in new code.
6332	*/
6333	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
6334	{
6335	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
6336	}
6337
6338
6339	/**
6340	* Gets a pointer to the array of extended CPUID leaves.
6341	*
6342	* CPUMGetGuestCpuIdExtMax() give the size of the array.
6343	*
6344	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
6345	* @param pVM Pointer to the VM.
6346	* @remark Intended for PATM - legacy, don't use in new code.
6347	*/
6348	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
6349	{
6350	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
6351	}
6352
6353
6354	/**
6355	* Gets a pointer to the array of centaur CPUID leaves.
6356	*
6357	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
6358	*
6359	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
6360	* @param pVM Pointer to the VM.
6361	* @remark Intended for PATM - legacy, don't use in new code.
6362	*/
6363	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
6364	{
6365	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
6366	}
6367
6368	/** @} */
6369	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
6370
6371	#endif /* VBOX_IN_VMM */
6372

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 57066

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