CPUMR3CpuId.cpp@ 57334

Last change on this file since 57334 was 57331, checked in by vboxsync, 9 years ago
temporarily disables AVX-2 by default.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 293.9 KB

Line
1	/* $Id: CPUMR3CpuId.cpp 57331 2015-08-13 15:02:45Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_CPUM
22	#include <VBox/vmm/cpum.h>
23	#include <VBox/vmm/dbgf.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/vmm/ssm.h>
26	#include "CPUMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/vmm/mm.h>
29
30	#include <VBox/err.h>
31	#include <iprt/asm-amd64-x86.h>
32	#include <iprt/ctype.h>
33	#include <iprt/mem.h>
34	#include <iprt/string.h>
35
36
37	/*******************************************************************************
38	* Defined Constants And Macros *
39	*******************************************************************************/
40	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
41	#define CPUM_CPUID_MAX_LEAVES 2048
42	/* Max size we accept for the XSAVE area. */
43	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
44	/* Min size we accept for the XSAVE area. */
45	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
46
47
48	/*******************************************************************************
49	* Global Variables *
50	*******************************************************************************/
51	/**
52	* The intel pentium family.
53	*/
54	static const CPUMMICROARCH g_aenmIntelFamily06[] =
55	{
56	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
57	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
58	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
59	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
60	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
61	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
62	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
63	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
64	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
65	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
66	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
67	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
68	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
69	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
70	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
71	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
72	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
73	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
74	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
78	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
79	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
80	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
81	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
82	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
83	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
85	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
86	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
87	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
88	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
89	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
90	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
91	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
94	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
95	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
96	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
97	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
98	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
99	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
101	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
102	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
103	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
104	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
105	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
106	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
107	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
110	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
111	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
112	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
113	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
114	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
115	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
117	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
118	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
119	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
121	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
122	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
123	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
126	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
127	/* [71(0x47)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
129	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
130	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
131	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [79(0x4f)] = */ kCpumMicroarch_Intel_Unknown,
136	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
137	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
138	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
139	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [85(0x55)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [86(0x56)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [87(0x57)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
145	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
146	/* [90(0x5a)] = */ kCpumMicroarch_Intel_Unknown,
147	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [92(0x5c)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [93(0x5d)] = */ kCpumMicroarch_Intel_Unknown,
150	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / 6700K */
151	/* [95(0x5f)] = */ kCpumMicroarch_Intel_Unknown,
152	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
153	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
154	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
155	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
156	};
157
158
159
160	/**
161	* Figures out the (sub-)micro architecture given a bit of CPUID info.
162	*
163	* @returns Micro architecture.
164	* @param enmVendor The CPU vendor .
165	* @param bFamily The CPU family.
166	* @param bModel The CPU model.
167	* @param bStepping The CPU stepping.
168	*/
169	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
170	uint8_t bModel, uint8_t bStepping)
171	{
172	if (enmVendor == CPUMCPUVENDOR_AMD)
173	{
174	switch (bFamily)
175	{
176	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
177	case 0x03: return kCpumMicroarch_AMD_Am386;
178	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
179	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
180	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
181	case 0x06:
182	switch (bModel)
183	{
184	case 0: return kCpumMicroarch_AMD_K7_Palomino;
185	case 1: return kCpumMicroarch_AMD_K7_Palomino;
186	case 2: return kCpumMicroarch_AMD_K7_Palomino;
187	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
188	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
189	case 6: return kCpumMicroarch_AMD_K7_Palomino;
190	case 7: return kCpumMicroarch_AMD_K7_Morgan;
191	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
192	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
193	}
194	return kCpumMicroarch_AMD_K7_Unknown;
195	case 0x0f:
196	/*
197	* This family is a friggin mess. Trying my best to make some
198	* sense out of it. Too much happened in the 0x0f family to
199	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
200	*
201	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
202	* cpu-world.com, and other places:
203	* - 130nm:
204	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
205	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
206	* - Newcastle: FC0/DH-CG (errum #180: FE0/DH-CG), FF0/DH-CG
207	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
208	* - Odessa: FC0/DH-CG (errum #180: FE0/DH-CG)
209	* - Paris: FF0/DH-CG, FC0/DH-CG (errum #180: FE0/DH-CG),
210	* - 90nm:
211	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
212	* - Oakville: 10FC0/DH-D0.
213	* - Georgetown: 10FC0/DH-D0.
214	* - Sonora: 10FC0/DH-D0.
215	* - Venus: 20F71/SH-E4
216	* - Troy: 20F51/SH-E4
217	* - Athens: 20F51/SH-E4
218	* - San Diego: 20F71/SH-E4.
219	* - Lancaster: 20F42/SH-E5
220	* - Newark: 20F42/SH-E5.
221	* - Albany: 20FC2/DH-E6.
222	* - Roma: 20FC2/DH-E6.
223	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
224	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
225	* - 90nm introducing Dual core:
226	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
227	* - Italy: 20F10/JH-E1, 20F12/JH-E6
228	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
229	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
230	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
231	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
232	* - Santa Ana: 40F32/JH-F2, /-F3
233	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
234	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
235	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
236	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
237	* - Keene: 40FC2/DH-F2.
238	* - Richmond: 40FC2/DH-F2
239	* - Taylor: 40F82/BH-F2
240	* - Trinidad: 40F82/BH-F2
241	*
242	* - 65nm:
243	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
244	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
245	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
246	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
247	* - Sherman: /-G1, 70FC2/DH-G2.
248	* - Huron: 70FF2/DH-G2.
249	*/
250	if (bModel < 0x10)
251	return kCpumMicroarch_AMD_K8_130nm;
252	if (bModel >= 0x60 && bModel < 0x80)
253	return kCpumMicroarch_AMD_K8_65nm;
254	if (bModel >= 0x40)
255	return kCpumMicroarch_AMD_K8_90nm_AMDV;
256	switch (bModel)
257	{
258	case 0x21:
259	case 0x23:
260	case 0x2b:
261	case 0x2f:
262	case 0x37:
263	case 0x3f:
264	return kCpumMicroarch_AMD_K8_90nm_DualCore;
265	}
266	return kCpumMicroarch_AMD_K8_90nm;
267	case 0x10:
268	return kCpumMicroarch_AMD_K10;
269	case 0x11:
270	return kCpumMicroarch_AMD_K10_Lion;
271	case 0x12:
272	return kCpumMicroarch_AMD_K10_Llano;
273	case 0x14:
274	return kCpumMicroarch_AMD_Bobcat;
275	case 0x15:
276	switch (bModel)
277	{
278	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
279	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
280	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
281	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
282	case 0x11: /* ?? */
283	case 0x12: /* ?? */
284	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
285	}
286	return kCpumMicroarch_AMD_15h_Unknown;
287	case 0x16:
288	return kCpumMicroarch_AMD_Jaguar;
289
290	}
291	return kCpumMicroarch_AMD_Unknown;
292	}
293
294	if (enmVendor == CPUMCPUVENDOR_INTEL)
295	{
296	switch (bFamily)
297	{
298	case 3:
299	return kCpumMicroarch_Intel_80386;
300	case 4:
301	return kCpumMicroarch_Intel_80486;
302	case 5:
303	return kCpumMicroarch_Intel_P5;
304	case 6:
305	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
306	return g_aenmIntelFamily06[bModel];
307	return kCpumMicroarch_Intel_Atom_Unknown;
308	case 15:
309	switch (bModel)
310	{
311	case 0: return kCpumMicroarch_Intel_NB_Willamette;
312	case 1: return kCpumMicroarch_Intel_NB_Willamette;
313	case 2: return kCpumMicroarch_Intel_NB_Northwood;
314	case 3: return kCpumMicroarch_Intel_NB_Prescott;
315	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
316	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
317	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
318	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
319	default: return kCpumMicroarch_Intel_NB_Unknown;
320	}
321	break;
322	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
323	case 1:
324	return kCpumMicroarch_Intel_8086;
325	case 2:
326	return kCpumMicroarch_Intel_80286;
327	}
328	return kCpumMicroarch_Intel_Unknown;
329	}
330
331	if (enmVendor == CPUMCPUVENDOR_VIA)
332	{
333	switch (bFamily)
334	{
335	case 5:
336	switch (bModel)
337	{
338	case 1: return kCpumMicroarch_Centaur_C6;
339	case 4: return kCpumMicroarch_Centaur_C6;
340	case 8: return kCpumMicroarch_Centaur_C2;
341	case 9: return kCpumMicroarch_Centaur_C3;
342	}
343	break;
344
345	case 6:
346	switch (bModel)
347	{
348	case 5: return kCpumMicroarch_VIA_C3_M2;
349	case 6: return kCpumMicroarch_VIA_C3_C5A;
350	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
351	case 8: return kCpumMicroarch_VIA_C3_C5N;
352	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
353	case 10: return kCpumMicroarch_VIA_C7_C5J;
354	case 15: return kCpumMicroarch_VIA_Isaiah;
355	}
356	break;
357	}
358	return kCpumMicroarch_VIA_Unknown;
359	}
360
361	if (enmVendor == CPUMCPUVENDOR_CYRIX)
362	{
363	switch (bFamily)
364	{
365	case 4:
366	switch (bModel)
367	{
368	case 9: return kCpumMicroarch_Cyrix_5x86;
369	}
370	break;
371
372	case 5:
373	switch (bModel)
374	{
375	case 2: return kCpumMicroarch_Cyrix_M1;
376	case 4: return kCpumMicroarch_Cyrix_MediaGX;
377	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
378	}
379	break;
380
381	case 6:
382	switch (bModel)
383	{
384	case 0: return kCpumMicroarch_Cyrix_M2;
385	}
386	break;
387
388	}
389	return kCpumMicroarch_Cyrix_Unknown;
390	}
391
392	return kCpumMicroarch_Unknown;
393	}
394
395
396	/**
397	* Translates a microarchitecture enum value to the corresponding string
398	* constant.
399	*
400	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
401	* NULL if the value is invalid.
402	*
403	* @param enmMicroarch The enum value to convert.
404	*/
405	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
406	{
407	switch (enmMicroarch)
408	{
409	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
410	CASE_RET_STR(kCpumMicroarch_Intel_8086);
411	CASE_RET_STR(kCpumMicroarch_Intel_80186);
412	CASE_RET_STR(kCpumMicroarch_Intel_80286);
413	CASE_RET_STR(kCpumMicroarch_Intel_80386);
414	CASE_RET_STR(kCpumMicroarch_Intel_80486);
415	CASE_RET_STR(kCpumMicroarch_Intel_P5);
416
417	CASE_RET_STR(kCpumMicroarch_Intel_P6);
418	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
419	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
420
421	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
422	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
423	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
424
425	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
426	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
427
428	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
429	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
430	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
431	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
432	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
433	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
434	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
435	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Cannonlake);
436
437	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
438	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
439	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
440	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
441	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
442	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
443	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
444
445	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
446	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
447	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
448	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
449	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
450	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
451	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
452
453	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
454
455	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
456	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
457	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
458	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
459	CASE_RET_STR(kCpumMicroarch_AMD_K5);
460	CASE_RET_STR(kCpumMicroarch_AMD_K6);
461
462	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
463	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
464	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
465	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
466	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
467	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
468	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
469
470	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
471	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
472	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
473	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
474	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
475
476	CASE_RET_STR(kCpumMicroarch_AMD_K10);
477	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
478	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
479	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
480	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
481
482	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
483	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
484	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
485	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
486	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
487
488	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
489
490	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
491
492	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
493	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
494	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
495	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
496	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
497	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
498	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
499	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
500	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
501	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
502	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
503	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
504	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
505
506	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
507	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
508	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
509	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
510	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
511	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
512
513	CASE_RET_STR(kCpumMicroarch_Unknown);
514
515	#undef CASE_RET_STR
516	case kCpumMicroarch_Invalid:
517	case kCpumMicroarch_Intel_End:
518	case kCpumMicroarch_Intel_Core7_End:
519	case kCpumMicroarch_Intel_Atom_End:
520	case kCpumMicroarch_Intel_P6_Core_Atom_End:
521	case kCpumMicroarch_Intel_NB_End:
522	case kCpumMicroarch_AMD_K7_End:
523	case kCpumMicroarch_AMD_K8_End:
524	case kCpumMicroarch_AMD_15h_End:
525	case kCpumMicroarch_AMD_16h_End:
526	case kCpumMicroarch_AMD_End:
527	case kCpumMicroarch_VIA_End:
528	case kCpumMicroarch_Cyrix_End:
529	case kCpumMicroarch_32BitHack:
530	break;
531	/* no default! */
532	}
533
534	return NULL;
535	}
536
537
538
539	/**
540	* Gets a matching leaf in the CPUID leaf array.
541	*
542	* @returns Pointer to the matching leaf, or NULL if not found.
543	* @param paLeaves The CPUID leaves to search. This is sorted.
544	* @param cLeaves The number of leaves in the array.
545	* @param uLeaf The leaf to locate.
546	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
547	*/
548	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
549	{
550	/* Lazy bird does linear lookup here since this is only used for the
551	occational CPUID overrides. */
552	for (uint32_t i = 0; i < cLeaves; i++)
553	if ( paLeaves[i].uLeaf == uLeaf
554	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
555	return &paLeaves[i];
556	return NULL;
557	}
558
559
560	/**
561	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
562	*
563	* @returns true if found, false it not.
564	* @param paLeaves The CPUID leaves to search. This is sorted.
565	* @param cLeaves The number of leaves in the array.
566	* @param uLeaf The leaf to locate.
567	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
568	* @param pLegacy The legacy output leaf.
569	*/
570	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
571	PCPUMCPUID pLegacy)
572	{
573	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
574	if (pLeaf)
575	{
576	pLegacy->uEax = pLeaf->uEax;
577	pLegacy->uEbx = pLeaf->uEbx;
578	pLegacy->uEcx = pLeaf->uEcx;
579	pLegacy->uEdx = pLeaf->uEdx;
580	return true;
581	}
582	return false;
583	}
584
585
586	/**
587	* Ensures that the CPUID leaf array can hold one more leaf.
588	*
589	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
590	* failure.
591	* @param pVM Pointer to the VM, used as the heap selector. Passing
592	* NULL uses the host-context heap, otherwise the VM's
593	* hyper heap is used.
594	* @param ppaLeaves Pointer to the variable holding the array pointer
595	* (input/output).
596	* @param cLeaves The current array size.
597	*
598	* @remarks This function will automatically update the R0 and RC pointers when
599	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
600	* be the corresponding VM's CPUID arrays (which is asserted).
601	*/
602	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
603	{
604	/*
605	* If pVM is not specified, we're on the regular heap and can waste a
606	* little space to speed things up.
607	*/
608	uint32_t cAllocated;
609	if (!pVM)
610	{
611	cAllocated = RT_ALIGN(cLeaves, 16);
612	if (cLeaves + 1 > cAllocated)
613	{
614	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
615	if (pvNew)
616	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
617	else
618	{
619	RTMemFree(*ppaLeaves);
620	*ppaLeaves = NULL;
621	}
622	}
623	}
624	/*
625	* Otherwise, we're on the hyper heap and are probably just inserting
626	* one or two leaves and should conserve space.
627	*/
628	else
629	{
630	#ifdef IN_VBOX_CPU_REPORT
631	AssertReleaseFailed();
632	#else
633	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
634	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
635
636	size_t cb = cLeaves * sizeof(**ppaLeaves);
637	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
638	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
639	if (RT_SUCCESS(rc))
640	{
641	/* Update the R0 and RC pointers. */
642	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
643	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
644	}
645	else
646	{
647	*ppaLeaves = NULL;
648	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
649	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
650	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
651	}
652	#endif
653	}
654	return *ppaLeaves;
655	}
656
657
658	/**
659	* Append a CPUID leaf or sub-leaf.
660	*
661	* ASSUMES linear insertion order, so we'll won't need to do any searching or
662	* replace anything. Use cpumR3CpuIdInsert() for those cases.
663	*
664	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
665	* the caller need do no more work.
666	* @param ppaLeaves Pointer to the the pointer to the array of sorted
667	* CPUID leaves and sub-leaves.
668	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
669	* @param uLeaf The leaf we're adding.
670	* @param uSubLeaf The sub-leaf number.
671	* @param fSubLeafMask The sub-leaf mask.
672	* @param uEax The EAX value.
673	* @param uEbx The EBX value.
674	* @param uEcx The ECX value.
675	* @param uEdx The EDX value.
676	* @param fFlags The flags.
677	*/
678	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
679	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
680	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
681	{
682	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
683	return VERR_NO_MEMORY;
684
685	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
686	Assert( *pcLeaves == 0
687	\|\| pNew[-1].uLeaf < uLeaf
688	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
689
690	pNew->uLeaf = uLeaf;
691	pNew->uSubLeaf = uSubLeaf;
692	pNew->fSubLeafMask = fSubLeafMask;
693	pNew->uEax = uEax;
694	pNew->uEbx = uEbx;
695	pNew->uEcx = uEcx;
696	pNew->uEdx = uEdx;
697	pNew->fFlags = fFlags;
698
699	*pcLeaves += 1;
700	return VINF_SUCCESS;
701	}
702
703
704	/**
705	* Checks that we've updated the CPUID leaves array correctly.
706	*
707	* This is a no-op in non-strict builds.
708	*
709	* @param paLeaves The leaves array.
710	* @param cLeaves The number of leaves.
711	*/
712	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
713	{
714	#ifdef VBOX_STRICT
715	for (uint32_t i = 1; i < cLeaves; i++)
716	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
717	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
718	else
719	{
720	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
721	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
722	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
723	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
724	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
725	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
726	}
727	#else
728	NOREF(paLeaves);
729	NOREF(cLeaves);
730	#endif
731	}
732
733
734	/**
735	* Inserts a CPU ID leaf, replacing any existing ones.
736	*
737	* When inserting a simple leaf where we already got a series of sub-leaves with
738	* the same leaf number (eax), the simple leaf will replace the whole series.
739	*
740	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
741	* host-context heap and has only been allocated/reallocated by the
742	* cpumR3CpuIdEnsureSpace function.
743	*
744	* @returns VBox status code.
745	* @param pVM Pointer to the VM, used as the heap selector.
746	* Passing NULL uses the host-context heap, otherwise
747	* the VM's hyper heap is used.
748	* @param ppaLeaves Pointer to the the pointer to the array of sorted
749	* CPUID leaves and sub-leaves. Must be NULL if using
750	* the hyper heap.
751	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must be
752	* NULL if using the hyper heap.
753	* @param pNewLeaf Pointer to the data of the new leaf we're about to
754	* insert.
755	*/
756	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
757	{
758	/*
759	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
760	*/
761	if (pVM)
762	{
763	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
764	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
765
766	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
767	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
768	}
769
770	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
771	uint32_t cLeaves = *pcLeaves;
772
773	/*
774	* Validate the new leaf a little.
775	*/
776	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
777	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
778	VERR_INVALID_FLAGS);
779	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
780	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
781	VERR_INVALID_PARAMETER);
782	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
783	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
784	VERR_INVALID_PARAMETER);
785	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
786	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
787	VERR_INVALID_PARAMETER);
788
789	/*
790	* Find insertion point. The lazy bird uses the same excuse as in
791	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
792	*/
793	uint32_t i;
794	if ( cLeaves > 0
795	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
796	{
797	/* Add at end. */
798	i = cLeaves;
799	}
800	else if ( cLeaves > 0
801	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
802	{
803	/* Either replacing the last leaf or dealing with sub-leaves. Spool
804	back to the first sub-leaf to pretend we did the linear search. */
805	i = cLeaves - 1;
806	while ( i > 0
807	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
808	i--;
809	}
810	else
811	{
812	/* Linear search from the start. */
813	i = 0;
814	while ( i < cLeaves
815	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
816	i++;
817	}
818	if ( i < cLeaves
819	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
820	{
821	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
822	{
823	/*
824	* The sub-leaf mask differs, replace all existing leaves with the
825	* same leaf number.
826	*/
827	uint32_t c = 1;
828	while ( i + c < cLeaves
829	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
830	c++;
831	if (c > 1 && i + c < cLeaves)
832	{
833	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
834	*pcLeaves = cLeaves -= c - 1;
835	}
836
837	paLeaves[i] = *pNewLeaf;
838	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
839	return VINF_SUCCESS;
840	}
841
842	/* Find sub-leaf insertion point. */
843	while ( i < cLeaves
844	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
845	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
846	i++;
847
848	/*
849	* If we've got an exactly matching leaf, replace it.
850	*/
851	if ( i < cLeaves
852	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
853	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
854	{
855	paLeaves[i] = *pNewLeaf;
856	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
857	return VINF_SUCCESS;
858	}
859	}
860
861	/*
862	* Adding a new leaf at 'i'.
863	*/
864	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
865	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
866	if (!paLeaves)
867	return VERR_NO_MEMORY;
868
869	if (i < cLeaves)
870	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
871	*pcLeaves += 1;
872	paLeaves[i] = *pNewLeaf;
873
874	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
875	return VINF_SUCCESS;
876	}
877
878
879	/**
880	* Removes a range of CPUID leaves.
881	*
882	* This will not reallocate the array.
883	*
884	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
885	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
886	* @param uFirst The first leaf.
887	* @param uLast The last leaf.
888	*/
889	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
890	{
891	uint32_t cLeaves = *pcLeaves;
892
893	Assert(uFirst <= uLast);
894
895	/*
896	* Find the first one.
897	*/
898	uint32_t iFirst = 0;
899	while ( iFirst < cLeaves
900	&& paLeaves[iFirst].uLeaf < uFirst)
901	iFirst++;
902
903	/*
904	* Find the end (last + 1).
905	*/
906	uint32_t iEnd = iFirst;
907	while ( iEnd < cLeaves
908	&& paLeaves[iEnd].uLeaf <= uLast)
909	iEnd++;
910
911	/*
912	* Adjust the array if anything needs removing.
913	*/
914	if (iFirst < iEnd)
915	{
916	if (iEnd < cLeaves)
917	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
918	*pcLeaves = cLeaves -= (iEnd - iFirst);
919	}
920
921	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
922	}
923
924
925
926	/**
927	* Checks if ECX make a difference when reading a given CPUID leaf.
928	*
929	* @returns @c true if it does, @c false if it doesn't.
930	* @param uLeaf The leaf we're reading.
931	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
932	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
933	* final sub-leaf (for leaf 0xb only).
934	*/
935	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
936	{
937	*pfFinalEcxUnchanged = false;
938
939	uint32_t auCur[4];
940	uint32_t auPrev[4];
941	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
942
943	/* Look for sub-leaves. */
944	uint32_t uSubLeaf = 1;
945	for (;;)
946	{
947	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
948	if (memcmp(auCur, auPrev, sizeof(auCur)))
949	break;
950
951	/* Advance / give up. */
952	uSubLeaf++;
953	if (uSubLeaf >= 64)
954	{
955	*pcSubLeaves = 1;
956	return false;
957	}
958	}
959
960	/* Count sub-leaves. */
961	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
962	uint32_t cRepeats = 0;
963	uSubLeaf = 0;
964	for (;;)
965	{
966	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
967
968	/* Figuring out when to stop isn't entirely straight forward as we need
969	to cover undocumented behavior up to a point and implementation shortcuts. */
970
971	/* 1. Look for more than 4 repeating value sets. */
972	if ( auCur[0] == auPrev[0]
973	&& auCur[1] == auPrev[1]
974	&& ( auCur[2] == auPrev[2]
975	\|\| ( auCur[2] == uSubLeaf
976	&& auPrev[2] == uSubLeaf - 1) )
977	&& auCur[3] == auPrev[3])
978	{
979	if ( uLeaf != 0xd
980	\|\| uSubLeaf >= 64
981	\|\| ( auCur[0] == 0
982	&& auCur[1] == 0
983	&& auCur[2] == 0
984	&& auCur[3] == 0
985	&& auPrev[2] == 0) )
986	cRepeats++;
987	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
988	break;
989	}
990	else
991	cRepeats = 0;
992
993	/* 2. Look for zero values. */
994	if ( auCur[0] == 0
995	&& auCur[1] == 0
996	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
997	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
998	&& uSubLeaf >= cMinLeaves)
999	{
1000	cRepeats = 0;
1001	break;
1002	}
1003
1004	/* 3. Leaf 0xb level type 0 check. */
1005	if ( uLeaf == 0xb
1006	&& (auCur[2] & 0xff00) == 0
1007	&& (auPrev[2] & 0xff00) == 0)
1008	{
1009	cRepeats = 0;
1010	break;
1011	}
1012
1013	/* 99. Give up. */
1014	if (uSubLeaf >= 128)
1015	{
1016	#ifndef IN_VBOX_CPU_REPORT
1017	/* Ok, limit it according to the documentation if possible just to
1018	avoid annoying users with these detection issues. */
1019	uint32_t cDocLimit = UINT32_MAX;
1020	if (uLeaf == 0x4)
1021	cDocLimit = 4;
1022	else if (uLeaf == 0x7)
1023	cDocLimit = 1;
1024	else if (uLeaf == 0xd)
1025	cDocLimit = 63;
1026	else if (uLeaf == 0xf)
1027	cDocLimit = 2;
1028	if (cDocLimit != UINT32_MAX)
1029	{
1030	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1031	*pcSubLeaves = cDocLimit + 3;
1032	return true;
1033	}
1034	#endif
1035	*pcSubLeaves = UINT32_MAX;
1036	return true;
1037	}
1038
1039	/* Advance. */
1040	uSubLeaf++;
1041	memcpy(auPrev, auCur, sizeof(auCur));
1042	}
1043
1044	/* Standard exit. */
1045	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1046	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1047	if (*pcSubLeaves == 0)
1048	*pcSubLeaves = 1;
1049	return true;
1050	}
1051
1052
1053	/**
1054	* Gets a CPU ID leaf.
1055	*
1056	* @returns VBox status code.
1057	* @param pVM Pointer to the VM.
1058	* @param pLeaf Where to store the found leaf.
1059	* @param uLeaf The leaf to locate.
1060	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1061	*/
1062	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1063	{
1064	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1065	uLeaf, uSubLeaf);
1066	if (pcLeaf)
1067	{
1068	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1069	return VINF_SUCCESS;
1070	}
1071
1072	return VERR_NOT_FOUND;
1073	}
1074
1075
1076	/**
1077	* Inserts a CPU ID leaf, replacing any existing ones.
1078	*
1079	* @returns VBox status code.
1080	* @param pVM Pointer to the VM.
1081	* @param pNewLeaf Pointer to the leaf being inserted.
1082	*/
1083	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1084	{
1085	/*
1086	* Validate parameters.
1087	*/
1088	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1089	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1090
1091	/*
1092	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1093	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1094	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1095	*/
1096	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1097	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1098	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1099	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1100	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1101	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1102	{
1103	return VERR_NOT_SUPPORTED;
1104	}
1105
1106	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1107	}
1108
1109	/**
1110	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1111	*
1112	* @returns VBox status code.
1113	* @param ppaLeaves Where to return the array pointer on success.
1114	* Use RTMemFree to release.
1115	* @param pcLeaves Where to return the size of the array on
1116	* success.
1117	*/
1118	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1119	{
1120	*ppaLeaves = NULL;
1121	*pcLeaves = 0;
1122
1123	/*
1124	* Try out various candidates. This must be sorted!
1125	*/
1126	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1127	{
1128	{ UINT32_C(0x00000000), false },
1129	{ UINT32_C(0x10000000), false },
1130	{ UINT32_C(0x20000000), false },
1131	{ UINT32_C(0x30000000), false },
1132	{ UINT32_C(0x40000000), false },
1133	{ UINT32_C(0x50000000), false },
1134	{ UINT32_C(0x60000000), false },
1135	{ UINT32_C(0x70000000), false },
1136	{ UINT32_C(0x80000000), false },
1137	{ UINT32_C(0x80860000), false },
1138	{ UINT32_C(0x8ffffffe), true },
1139	{ UINT32_C(0x8fffffff), true },
1140	{ UINT32_C(0x90000000), false },
1141	{ UINT32_C(0xa0000000), false },
1142	{ UINT32_C(0xb0000000), false },
1143	{ UINT32_C(0xc0000000), false },
1144	{ UINT32_C(0xd0000000), false },
1145	{ UINT32_C(0xe0000000), false },
1146	{ UINT32_C(0xf0000000), false },
1147	};
1148
1149	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1150	{
1151	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1152	uint32_t uEax, uEbx, uEcx, uEdx;
1153	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1154
1155	/*
1156	* Does EAX look like a typical leaf count value?
1157	*/
1158	if ( uEax > uLeaf
1159	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1160	{
1161	/* Yes, dump them. */
1162	uint32_t cLeaves = uEax - uLeaf + 1;
1163	while (cLeaves-- > 0)
1164	{
1165	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1166
1167	uint32_t fFlags = 0;
1168
1169	/* There are currently three known leaves containing an APIC ID
1170	that needs EMT specific attention */
1171	if (uLeaf == 1)
1172	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1173	else if (uLeaf == 0xb && uEcx != 0)
1174	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1175	else if ( uLeaf == UINT32_C(0x8000001e)
1176	&& ( uEax
1177	\|\| uEbx
1178	\|\| uEdx
1179	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1180	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1181
1182
1183	/* Check three times here to reduce the chance of CPU migration
1184	resulting in false positives with things like the APIC ID. */
1185	uint32_t cSubLeaves;
1186	bool fFinalEcxUnchanged;
1187	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1188	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1189	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1190	{
1191	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1192	{
1193	/* This shouldn't happen. But in case it does, file all
1194	relevant details in the release log. */
1195	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1196	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1197	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1198	{
1199	uint32_t auTmp[4];
1200	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1201	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1202	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1203	}
1204	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1205	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1206	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1207	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1208	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1209	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1210	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1211	}
1212
1213	if (fFinalEcxUnchanged)
1214	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1215
1216	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1217	{
1218	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1219	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1220	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1221	if (RT_FAILURE(rc))
1222	return rc;
1223	}
1224	}
1225	else
1226	{
1227	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1228	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1229	if (RT_FAILURE(rc))
1230	return rc;
1231	}
1232
1233	/* next */
1234	uLeaf++;
1235	}
1236	}
1237	/*
1238	* Special CPUIDs needs special handling as they don't follow the
1239	* leaf count principle used above.
1240	*/
1241	else if (s_aCandidates[iOuter].fSpecial)
1242	{
1243	bool fKeep = false;
1244	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1245	fKeep = true;
1246	else if ( uLeaf == 0x8fffffff
1247	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1248	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1249	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1250	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1251	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1252	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1253	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1254	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1255	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1256	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1257	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1258	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1259	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1260	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1261	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1262	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1263	fKeep = true;
1264	if (fKeep)
1265	{
1266	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1267	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1268	if (RT_FAILURE(rc))
1269	return rc;
1270	}
1271	}
1272	}
1273
1274	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1275	return VINF_SUCCESS;
1276	}
1277
1278
1279	/**
1280	* Determines the method the CPU uses to handle unknown CPUID leaves.
1281	*
1282	* @returns VBox status code.
1283	* @param penmUnknownMethod Where to return the method.
1284	* @param pDefUnknown Where to return default unknown values. This
1285	* will be set, even if the resulting method
1286	* doesn't actually needs it.
1287	*/
1288	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1289	{
1290	uint32_t uLastStd = ASMCpuId_EAX(0);
1291	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1292	if (!ASMIsValidExtRange(uLastExt))
1293	uLastExt = 0x80000000;
1294
1295	uint32_t auChecks[] =
1296	{
1297	uLastStd + 1,
1298	uLastStd + 5,
1299	uLastStd + 8,
1300	uLastStd + 32,
1301	uLastStd + 251,
1302	uLastExt + 1,
1303	uLastExt + 8,
1304	uLastExt + 15,
1305	uLastExt + 63,
1306	uLastExt + 255,
1307	0x7fbbffcc,
1308	0x833f7872,
1309	0xefff2353,
1310	0x35779456,
1311	0x1ef6d33e,
1312	};
1313
1314	static const uint32_t s_auValues[] =
1315	{
1316	0xa95d2156,
1317	0x00000001,
1318	0x00000002,
1319	0x00000008,
1320	0x00000000,
1321	0x55773399,
1322	0x93401769,
1323	0x12039587,
1324	};
1325
1326	/*
1327	* Simple method, all zeros.
1328	*/
1329	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1330	pDefUnknown->uEax = 0;
1331	pDefUnknown->uEbx = 0;
1332	pDefUnknown->uEcx = 0;
1333	pDefUnknown->uEdx = 0;
1334
1335	/*
1336	* Intel has been observed returning the last standard leaf.
1337	*/
1338	uint32_t auLast[4];
1339	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1340
1341	uint32_t cChecks = RT_ELEMENTS(auChecks);
1342	while (cChecks > 0)
1343	{
1344	uint32_t auCur[4];
1345	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1346	if (memcmp(auCur, auLast, sizeof(auCur)))
1347	break;
1348	cChecks--;
1349	}
1350	if (cChecks == 0)
1351	{
1352	/* Now, what happens when the input changes? Esp. ECX. */
1353	uint32_t cTotal = 0;
1354	uint32_t cSame = 0;
1355	uint32_t cLastWithEcx = 0;
1356	uint32_t cNeither = 0;
1357	uint32_t cValues = RT_ELEMENTS(s_auValues);
1358	while (cValues > 0)
1359	{
1360	uint32_t uValue = s_auValues[cValues - 1];
1361	uint32_t auLastWithEcx[4];
1362	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1363	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1364
1365	cChecks = RT_ELEMENTS(auChecks);
1366	while (cChecks > 0)
1367	{
1368	uint32_t auCur[4];
1369	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1370	if (!memcmp(auCur, auLast, sizeof(auCur)))
1371	{
1372	cSame++;
1373	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1374	cLastWithEcx++;
1375	}
1376	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1377	cLastWithEcx++;
1378	else
1379	cNeither++;
1380	cTotal++;
1381	cChecks--;
1382	}
1383	cValues--;
1384	}
1385
1386	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1387	if (cSame == cTotal)
1388	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1389	else if (cLastWithEcx == cTotal)
1390	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1391	else
1392	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1393	pDefUnknown->uEax = auLast[0];
1394	pDefUnknown->uEbx = auLast[1];
1395	pDefUnknown->uEcx = auLast[2];
1396	pDefUnknown->uEdx = auLast[3];
1397	return VINF_SUCCESS;
1398	}
1399
1400	/*
1401	* Unchanged register values?
1402	*/
1403	cChecks = RT_ELEMENTS(auChecks);
1404	while (cChecks > 0)
1405	{
1406	uint32_t const uLeaf = auChecks[cChecks - 1];
1407	uint32_t cValues = RT_ELEMENTS(s_auValues);
1408	while (cValues > 0)
1409	{
1410	uint32_t uValue = s_auValues[cValues - 1];
1411	uint32_t auCur[4];
1412	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1413	if ( auCur[0] != uLeaf
1414	\|\| auCur[1] != uValue
1415	\|\| auCur[2] != uValue
1416	\|\| auCur[3] != uValue)
1417	break;
1418	cValues--;
1419	}
1420	if (cValues != 0)
1421	break;
1422	cChecks--;
1423	}
1424	if (cChecks == 0)
1425	{
1426	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1427	return VINF_SUCCESS;
1428	}
1429
1430	/*
1431	* Just go with the simple method.
1432	*/
1433	return VINF_SUCCESS;
1434	}
1435
1436
1437	/**
1438	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1439	*
1440	* @returns Read only name string.
1441	* @param enmUnknownMethod The method to translate.
1442	*/
1443	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1444	{
1445	switch (enmUnknownMethod)
1446	{
1447	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1448	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1449	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1450	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1451
1452	case CPUMUNKNOWNCPUID_INVALID:
1453	case CPUMUNKNOWNCPUID_END:
1454	case CPUMUNKNOWNCPUID_32BIT_HACK:
1455	break;
1456	}
1457	return "Invalid-unknown-CPUID-method";
1458	}
1459
1460
1461	/**
1462	* Detect the CPU vendor give n the
1463	*
1464	* @returns The vendor.
1465	* @param uEAX EAX from CPUID(0).
1466	* @param uEBX EBX from CPUID(0).
1467	* @param uECX ECX from CPUID(0).
1468	* @param uEDX EDX from CPUID(0).
1469	*/
1470	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1471	{
1472	if (ASMIsValidStdRange(uEAX))
1473	{
1474	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1475	return CPUMCPUVENDOR_AMD;
1476
1477	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1478	return CPUMCPUVENDOR_INTEL;
1479
1480	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1481	return CPUMCPUVENDOR_VIA;
1482
1483	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1484	&& uECX == UINT32_C(0x64616574)
1485	&& uEDX == UINT32_C(0x736E4978))
1486	return CPUMCPUVENDOR_CYRIX;
1487
1488	/* "Geode by NSC", example: family 5, model 9. */
1489
1490	/** @todo detect the other buggers... */
1491	}
1492
1493	return CPUMCPUVENDOR_UNKNOWN;
1494	}
1495
1496
1497	/**
1498	* Translates a CPU vendor enum value into the corresponding string constant.
1499	*
1500	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1501	* value name. This can be useful when generating code.
1502	*
1503	* @returns Read only name string.
1504	* @param enmVendor The CPU vendor value.
1505	*/
1506	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1507	{
1508	switch (enmVendor)
1509	{
1510	case CPUMCPUVENDOR_INTEL: return "INTEL";
1511	case CPUMCPUVENDOR_AMD: return "AMD";
1512	case CPUMCPUVENDOR_VIA: return "VIA";
1513	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1514	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1515
1516	case CPUMCPUVENDOR_INVALID:
1517	case CPUMCPUVENDOR_32BIT_HACK:
1518	break;
1519	}
1520	return "Invalid-cpu-vendor";
1521	}
1522
1523
1524	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1525	{
1526	/* Could do binary search, doing linear now because I'm lazy. */
1527	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1528	while (cLeaves-- > 0)
1529	{
1530	if (pLeaf->uLeaf == uLeaf)
1531	return pLeaf;
1532	pLeaf++;
1533	}
1534	return NULL;
1535	}
1536
1537
1538	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1539	{
1540	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1541	if ( !pLeaf
1542	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1543	return pLeaf;
1544
1545	/* Linear sub-leaf search. Lazy as usual. */
1546	cLeaves -= pLeaf - paLeaves;
1547	while ( cLeaves-- > 0
1548	&& pLeaf->uLeaf == uLeaf)
1549	{
1550	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1551	return pLeaf;
1552	pLeaf++;
1553	}
1554
1555	return NULL;
1556	}
1557
1558
1559	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1560	{
1561	RT_ZERO(*pFeatures);
1562	if (cLeaves >= 2)
1563	{
1564	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1565	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1566	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1567	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1568	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1569	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1570
1571	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1572	pStd0Leaf->uEbx,
1573	pStd0Leaf->uEcx,
1574	pStd0Leaf->uEdx);
1575	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1576	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1577	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1578	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1579	pFeatures->uFamily,
1580	pFeatures->uModel,
1581	pFeatures->uStepping);
1582
1583	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1584	if (pLeaf)
1585	pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff;
1586	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1587	pFeatures->cMaxPhysAddrWidth = 36;
1588	else
1589	pFeatures->cMaxPhysAddrWidth = 32;
1590
1591	/* Standard features. */
1592	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1593	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1594	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1595	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1596	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1597	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1598	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1599	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1600	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1601	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1602	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1603	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1604	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1605	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1606	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1607	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1608	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1609	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1610	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1611	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1612	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1613	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1614
1615	/* Structured extended features. */
1616	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1617	if (pSxfLeaf0)
1618	{
1619	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEcx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1620	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEcx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1621	}
1622
1623	/* MWAIT/MONITOR leaf. */
1624	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1625	if (pMWaitLeaf)
1626	{
1627	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1628	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1629	}
1630
1631	/* Extended features. */
1632	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1633	if (pExtLeaf)
1634	{
1635	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1636	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1637	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1638	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1639	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1640	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1641	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1642	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1643	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1644	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1645	}
1646
1647	if ( pExtLeaf
1648	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1649	{
1650	/* AMD features. */
1651	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1652	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1653	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1654	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1655	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1656	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1657	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1658	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1659	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1660	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1661	}
1662
1663	/*
1664	* Quirks.
1665	*/
1666	pFeatures->fLeakyFxSR = pExtLeaf
1667	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1668	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1669	&& pFeatures->uFamily >= 6 /* K7 and up */;
1670
1671	/*
1672	* Max extended (/FPU) state.
1673	*/
1674	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1675	if (pFeatures->fXSaveRstor)
1676	{
1677	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1678	if (pXStateLeaf0)
1679	{
1680	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1681	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1682	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1683	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1684	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1685	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1686	{
1687	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1688
1689	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1690	if ( pXStateLeaf1
1691	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1692	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1693	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1694	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEbx;
1695	}
1696	else
1697	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1698	pFeatures->fXSaveRstor = 0);
1699	}
1700	else
1701	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1702	pFeatures->fXSaveRstor = 0);
1703	}
1704	}
1705	else
1706	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1707	return VINF_SUCCESS;
1708	}
1709
1710
1711	/*
1712	*
1713	* Init related code.
1714	* Init related code.
1715	* Init related code.
1716	*
1717	*
1718	*/
1719	#ifdef VBOX_IN_VMM
1720
1721
1722	/**
1723	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1724	*
1725	* This ignores the fSubLeafMask.
1726	*
1727	* @returns Pointer to the matching leaf, or NULL if not found.
1728	* @param paLeaves The CPUID leaves to search. This is sorted.
1729	* @param cLeaves The number of leaves in the array.
1730	* @param uLeaf The leaf to locate.
1731	* @param uSubLeaf The subleaf to locate.
1732	*/
1733	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1734	{
1735	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1736	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1737	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1738	if (iEnd)
1739	{
1740	uint32_t iBegin = 0;
1741	for (;;)
1742	{
1743	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1744	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1745	if (uNeedle < uCur)
1746	{
1747	if (i > iBegin)
1748	iEnd = i;
1749	else
1750	break;
1751	}
1752	else if (uNeedle > uCur)
1753	{
1754	if (i + 1 < iEnd)
1755	iBegin = i + 1;
1756	else
1757	break;
1758	}
1759	else
1760	return &paLeaves[i];
1761	}
1762	}
1763	return NULL;
1764	}
1765
1766
1767	/**
1768	* Loads MSR range overrides.
1769	*
1770	* This must be called before the MSR ranges are moved from the normal heap to
1771	* the hyper heap!
1772	*
1773	* @returns VBox status code (VMSetError called).
1774	* @param pVM Pointer to the cross context VM structure
1775	* @param pMsrNode The CFGM node with the MSR overrides.
1776	*/
1777	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1778	{
1779	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1780	{
1781	/*
1782	* Assemble a valid MSR range.
1783	*/
1784	CPUMMSRRANGE MsrRange;
1785	MsrRange.offCpumCpu = 0;
1786	MsrRange.fReserved = 0;
1787
1788	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1789	if (RT_FAILURE(rc))
1790	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1791
1792	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1793	if (RT_FAILURE(rc))
1794	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1795	MsrRange.szName, rc);
1796
1797	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1798	if (RT_FAILURE(rc))
1799	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1800	MsrRange.szName, rc);
1801
1802	char szType[32];
1803	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1804	if (RT_FAILURE(rc))
1805	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1806	MsrRange.szName, rc);
1807	if (!RTStrICmp(szType, "FixedValue"))
1808	{
1809	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1810	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1811
1812	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1813	if (RT_FAILURE(rc))
1814	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1815	MsrRange.szName, rc);
1816
1817	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1818	if (RT_FAILURE(rc))
1819	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1820	MsrRange.szName, rc);
1821
1822	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1823	if (RT_FAILURE(rc))
1824	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1825	MsrRange.szName, rc);
1826	}
1827	else
1828	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1829	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1830
1831	/*
1832	* Insert the range into the table (replaces/splits/shrinks existing
1833	* MSR ranges).
1834	*/
1835	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1836	&MsrRange);
1837	if (RT_FAILURE(rc))
1838	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
1839	}
1840
1841	return VINF_SUCCESS;
1842	}
1843
1844
1845	/**
1846	* Loads CPUID leaf overrides.
1847	*
1848	* This must be called before the CPUID leaves are moved from the normal
1849	* heap to the hyper heap!
1850	*
1851	* @returns VBox status code (VMSetError called).
1852	* @param pVM Pointer to the cross context VM structure
1853	* @param pParentNode The CFGM node with the CPUID leaves.
1854	* @param pszLabel How to label the overrides we're loading.
1855	*/
1856	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
1857	{
1858	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1859	{
1860	/*
1861	* Get the leaf and subleaf numbers.
1862	*/
1863	char szName[128];
1864	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
1865	if (RT_FAILURE(rc))
1866	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
1867
1868	/* The leaf number is either specified directly or thru the node name. */
1869	uint32_t uLeaf;
1870	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
1871	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1872	{
1873	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
1874	if (rc != VINF_SUCCESS)
1875	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
1876	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
1877	}
1878	else if (RT_FAILURE(rc))
1879	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
1880	pszLabel, szName, rc);
1881
1882	uint32_t uSubLeaf;
1883	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
1884	if (RT_FAILURE(rc))
1885	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
1886	pszLabel, szName, rc);
1887
1888	uint32_t fSubLeafMask;
1889	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
1890	if (RT_FAILURE(rc))
1891	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
1892	pszLabel, szName, rc);
1893
1894	/*
1895	* Look up the specified leaf, since the output register values
1896	* defaults to any existing values. This allows overriding a single
1897	* register, without needing to know the other values.
1898	*/
1899	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
1900	CPUMCPUIDLEAF Leaf;
1901	if (pLeaf)
1902	Leaf = *pLeaf;
1903	else
1904	RT_ZERO(Leaf);
1905	Leaf.uLeaf = uLeaf;
1906	Leaf.uSubLeaf = uSubLeaf;
1907	Leaf.fSubLeafMask = fSubLeafMask;
1908
1909	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
1910	if (RT_FAILURE(rc))
1911	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
1912	pszLabel, szName, rc);
1913	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
1914	if (RT_FAILURE(rc))
1915	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
1916	pszLabel, szName, rc);
1917	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
1918	if (RT_FAILURE(rc))
1919	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
1920	pszLabel, szName, rc);
1921	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
1922	if (RT_FAILURE(rc))
1923	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
1924	pszLabel, szName, rc);
1925
1926	/*
1927	* Insert the leaf into the table (replaces existing ones).
1928	*/
1929	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1930	&Leaf);
1931	if (RT_FAILURE(rc))
1932	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
1933	}
1934
1935	return VINF_SUCCESS;
1936	}
1937
1938
1939
1940	/**
1941	* Fetches overrides for a CPUID leaf.
1942	*
1943	* @returns VBox status code.
1944	* @param pLeaf The leaf to load the overrides into.
1945	* @param pCfgNode The CFGM node containing the overrides
1946	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
1947	* @param iLeaf The CPUID leaf number.
1948	*/
1949	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
1950	{
1951	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
1952	if (pLeafNode)
1953	{
1954	uint32_t u32;
1955	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
1956	if (RT_SUCCESS(rc))
1957	pLeaf->uEax = u32;
1958	else
1959	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1960
1961	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
1962	if (RT_SUCCESS(rc))
1963	pLeaf->uEbx = u32;
1964	else
1965	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1966
1967	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
1968	if (RT_SUCCESS(rc))
1969	pLeaf->uEcx = u32;
1970	else
1971	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1972
1973	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
1974	if (RT_SUCCESS(rc))
1975	pLeaf->uEdx = u32;
1976	else
1977	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1978
1979	}
1980	return VINF_SUCCESS;
1981	}
1982
1983
1984	/**
1985	* Load the overrides for a set of CPUID leaves.
1986	*
1987	* @returns VBox status code.
1988	* @param paLeaves The leaf array.
1989	* @param cLeaves The number of leaves.
1990	* @param uStart The start leaf number.
1991	* @param pCfgNode The CFGM node containing the overrides
1992	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
1993	*/
1994	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
1995	{
1996	for (uint32_t i = 0; i < cLeaves; i++)
1997	{
1998	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
1999	if (RT_FAILURE(rc))
2000	return rc;
2001	}
2002
2003	return VINF_SUCCESS;
2004	}
2005
2006	/**
2007	* Init a set of host CPUID leaves.
2008	*
2009	* @returns VBox status code.
2010	* @param paLeaves The leaf array.
2011	* @param cLeaves The number of leaves.
2012	* @param uStart The start leaf number.
2013	* @param pCfgNode The /CPUM/HostCPUID/ node.
2014	*/
2015	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2016	{
2017	/* Using the ECX variant for all of them can't hurt... */
2018	for (uint32_t i = 0; i < cLeaves; i++)
2019	ASMCpuIdExSlow(uStart + i, 0, 0, 0, &paLeaves[i].uEax, &paLeaves[i].uEbx, &paLeaves[i].uEcx, &paLeaves[i].uEdx);
2020
2021	/* Load CPUID leaf override; we currently don't care if the user
2022	specifies features the host CPU doesn't support. */
2023	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
2024	}
2025
2026
2027	/**
2028	* Installs the CPUID leaves and explods the data into structures like
2029	* GuestFeatures and CPUMCTX::aoffXState.
2030	*
2031	* @returns VBox status code.
2032	* @param pVM The cross context VM handle.
2033	* @param pCpum The CPUM part of @a VM.
2034	* @param paLeaves The leaves. These will be copied (but not freed).
2035	* @param cLeaves The number of leaves.
2036	*/
2037	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
2038	{
2039	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2040
2041	/*
2042	* Install the CPUID information.
2043	*/
2044	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2045	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2046
2047	AssertLogRelRCReturn(rc, rc);
2048	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2049	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2050	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2051	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2052	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2053
2054	/*
2055	* Update the default CPUID leaf if necessary.
2056	*/
2057	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2058	{
2059	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2060	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2061	{
2062	/* We don't use CPUID(0).eax here because of the NT hack that only
2063	changes that value without actually removing any leaves. */
2064	uint32_t i = 0;
2065	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2066	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2067	{
2068	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2069	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2070	i++;
2071	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2072	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2073	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2074	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2075	}
2076	break;
2077	}
2078	default:
2079	break;
2080	}
2081
2082	/*
2083	* Explode the guest CPU features.
2084	*/
2085	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
2086	AssertLogRelRCReturn(rc, rc);
2087
2088	/*
2089	* Adjust the scalable bus frequency according to the CPUID information
2090	* we're now using.
2091	*/
2092	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2093	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2094	? UINT64_C(100000000) /* 100MHz */
2095	: UINT64_C(133333333); /* 133MHz */
2096
2097	/*
2098	* Populate the legacy arrays. Currently used for everything, later only
2099	* for patch manager.
2100	*/
2101	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2102	{
2103	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2104	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2105	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2106	};
2107	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2108	{
2109	uint32_t cLeft = aOldRanges[i].cCpuIds;
2110	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2111	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2112	while (cLeft-- > 0)
2113	{
2114	uLeaf--;
2115	pLegacyLeaf--;
2116
2117	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2118	if (pLeaf)
2119	{
2120	pLegacyLeaf->uEax = pLeaf->uEax;
2121	pLegacyLeaf->uEbx = pLeaf->uEbx;
2122	pLegacyLeaf->uEcx = pLeaf->uEcx;
2123	pLegacyLeaf->uEdx = pLeaf->uEdx;
2124	}
2125	else
2126	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2127	}
2128	}
2129
2130	/*
2131	* Configure XSAVE offsets according to the CPUID info.
2132	*/
2133	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2134	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2135	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2136	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2137	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2138	{
2139	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2140	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2141	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2142	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2143	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2144	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2145	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2146	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2147	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2148	pCpum->GuestFeatures.cbMaxExtendedState),
2149	VERR_CPUM_IPE_1);
2150	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2151	}
2152	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2153
2154	/* Copy the CPU #0 data to the other CPUs. */
2155	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2156	{
2157	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2158	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2159	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2160	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2161	}
2162
2163	return VINF_SUCCESS;
2164	}
2165
2166
2167	/** @name Instruction Set Extension Options
2168	* @{ */
2169	/** Configuration option type (extended boolean, really). */
2170	typedef uint8_t CPUMISAEXTCFG;
2171	/** Always disable the extension. */
2172	#define CPUMISAEXTCFG_DISABLED false
2173	/** Enable the extension if it's supported by the host CPU. */
2174	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2175	/** Enable the extension if it's supported by the host CPU, but don't let
2176	* the portable CPUID feature disable it. */
2177	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2178	/** Always enable the extension. */
2179	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2180	/** @} */
2181
2182	/**
2183	* CPUID Configuration (from CFGM).
2184	*
2185	* @remarks The members aren't document since we would only be duplicating the
2186	* \@cfgm entries in cpumR3CpuIdReadConfig.
2187	*/
2188	typedef struct CPUMCPUIDCONFIG
2189	{
2190	bool fNt4LeafLimit;
2191	bool fInvariantTsc;
2192
2193	CPUMISAEXTCFG enmCmpXchg16b;
2194	CPUMISAEXTCFG enmMonitor;
2195	CPUMISAEXTCFG enmMWaitExtensions;
2196	CPUMISAEXTCFG enmSse41;
2197	CPUMISAEXTCFG enmSse42;
2198	CPUMISAEXTCFG enmAvx;
2199	CPUMISAEXTCFG enmAvx2;
2200	CPUMISAEXTCFG enmXSave;
2201	CPUMISAEXTCFG enmAesNi;
2202	CPUMISAEXTCFG enmPClMul;
2203	CPUMISAEXTCFG enmPopCnt;
2204	CPUMISAEXTCFG enmMovBe;
2205	CPUMISAEXTCFG enmRdRand;
2206	CPUMISAEXTCFG enmRdSeed;
2207	CPUMISAEXTCFG enmCLFlushOpt;
2208
2209	CPUMISAEXTCFG enmAbm;
2210	CPUMISAEXTCFG enmSse4A;
2211	CPUMISAEXTCFG enmMisAlnSse;
2212	CPUMISAEXTCFG enm3dNowPrf;
2213	CPUMISAEXTCFG enmAmdExtMmx;
2214
2215	uint32_t uMaxStdLeaf;
2216	uint32_t uMaxExtLeaf;
2217	uint32_t uMaxCentaurLeaf;
2218	uint32_t uMaxIntelFamilyModelStep;
2219	char szCpuName[128];
2220	} CPUMCPUIDCONFIG;
2221	/** Pointer to CPUID config (from CFGM). */
2222	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2223
2224
2225	/**
2226	* Insert hypervisor identification leaves.
2227	*
2228	* We only return minimal information, primarily ensuring that the
2229	* 0x40000000 function returns 0x40000001 and identifying ourselves.
2230	* Hypervisor-specific interface is supported through GIM which will
2231	* modify these leaves if required depending on the GIM provider.
2232	*
2233	* @returns VBox status code.
2234	* @param pCpum The CPUM instance data.
2235	* @param pConfig The CPUID configuration we've read from CFGM.
2236	*/
2237	static int cpumR3CpuIdPlantHypervisorLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2238	{
2239	CPUMCPUIDLEAF NewLeaf;
2240	NewLeaf.uLeaf = UINT32_C(0x40000000);
2241	NewLeaf.uSubLeaf = 0;
2242	NewLeaf.fSubLeafMask = 0;
2243	NewLeaf.uEax = UINT32_C(0x40000001);
2244	NewLeaf.uEbx = 0x786f4256 /* 'VBox' */;
2245	NewLeaf.uEcx = 0x786f4256 /* 'VBox' */;
2246	NewLeaf.uEdx = 0x786f4256 /* 'VBox' */;
2247	NewLeaf.fFlags = 0;
2248	int rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
2249	AssertLogRelRCReturn(rc, rc);
2250
2251	NewLeaf.uLeaf = UINT32_C(0x40000001);
2252	NewLeaf.uEax = 0x656e6f6e; /* 'none' */
2253	NewLeaf.uEbx = 0;
2254	NewLeaf.uEcx = 0;
2255	NewLeaf.uEdx = 0;
2256	NewLeaf.fFlags = 0;
2257	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
2258	AssertLogRelRCReturn(rc, rc);
2259
2260	return VINF_SUCCESS;
2261	}
2262
2263
2264	/**
2265	* Mini CPU selection support for making Mac OS X happy.
2266	*
2267	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2268	*
2269	* @param pCpum The CPUM instance data.
2270	* @param pConfig The CPUID configuration we've read from CFGM.
2271	*/
2272	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2273	{
2274	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2275	{
2276	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2277	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2278	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2279	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2280	0);
2281	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2282	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2283	{
2284	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2285	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2286	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2287	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2288	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2289	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2290	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2291	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2292	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2293	pStdFeatureLeaf->uEax = uNew;
2294	}
2295	}
2296	}
2297
2298
2299
2300	/**
2301	* Limit it the number of entries, zapping the remainder.
2302	*
2303	* The limits are masking off stuff about power saving and similar, this
2304	* is perhaps a bit crudely done as there is probably some relatively harmless
2305	* info too in these leaves (like words about having a constant TSC).
2306	*
2307	* @param pCpum The CPUM instance data.
2308	* @param pConfig The CPUID configuration we've read from CFGM.
2309	*/
2310	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2311	{
2312	/*
2313	* Standard leaves.
2314	*/
2315	uint32_t uSubLeaf = 0;
2316	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2317	if (pCurLeaf)
2318	{
2319	uint32_t uLimit = pCurLeaf->uEax;
2320	if (uLimit <= UINT32_C(0x000fffff))
2321	{
2322	if (uLimit > pConfig->uMaxStdLeaf)
2323	{
2324	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2325	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2326	uLimit + 1, UINT32_C(0x000fffff));
2327	}
2328
2329	/* NT4 hack, no zapping of extra leaves here. */
2330	if (pConfig->fNt4LeafLimit && uLimit > 3)
2331	pCurLeaf->uEax = uLimit = 3;
2332
2333	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2334	pCurLeaf->uEax = uLimit;
2335	}
2336	else
2337	{
2338	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2339	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2340	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2341	}
2342	}
2343
2344	/*
2345	* Extended leaves.
2346	*/
2347	uSubLeaf = 0;
2348	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2349	if (pCurLeaf)
2350	{
2351	uint32_t uLimit = pCurLeaf->uEax;
2352	if ( uLimit >= UINT32_C(0x80000000)
2353	&& uLimit <= UINT32_C(0x800fffff))
2354	{
2355	if (uLimit > pConfig->uMaxExtLeaf)
2356	{
2357	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2358	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2359	uLimit + 1, UINT32_C(0x800fffff));
2360	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2361	pCurLeaf->uEax = uLimit;
2362	}
2363	}
2364	else
2365	{
2366	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2367	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2368	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2369	}
2370	}
2371
2372	/*
2373	* Centaur leaves (VIA).
2374	*/
2375	uSubLeaf = 0;
2376	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2377	if (pCurLeaf)
2378	{
2379	uint32_t uLimit = pCurLeaf->uEax;
2380	if ( uLimit >= UINT32_C(0xc0000000)
2381	&& uLimit <= UINT32_C(0xc00fffff))
2382	{
2383	if (uLimit > pConfig->uMaxCentaurLeaf)
2384	{
2385	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2386	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2387	uLimit + 1, UINT32_C(0xcfffffff));
2388	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2389	pCurLeaf->uEax = uLimit;
2390	}
2391	}
2392	else
2393	{
2394	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2395	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2396	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2397	}
2398	}
2399	}
2400
2401
2402	/**
2403	* Clears a CPUID leaf and all sub-leaves (to zero).
2404	*
2405	* @param pCpum The CPUM instance data.
2406	* @param uLeaf The leaf to clear.
2407	*/
2408	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2409	{
2410	uint32_t uSubLeaf = 0;
2411	PCPUMCPUIDLEAF pCurLeaf;
2412	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2413	{
2414	pCurLeaf->uEax = 0;
2415	pCurLeaf->uEbx = 0;
2416	pCurLeaf->uEcx = 0;
2417	pCurLeaf->uEdx = 0;
2418	uSubLeaf++;
2419	}
2420	}
2421
2422
2423	/**
2424	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2425	* the given leaf.
2426	*
2427	* @returns pLeaf.
2428	* @param pCpum The CPUM instance data.
2429	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2430	*/
2431	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2432	{
2433	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2434	if (pLeaf->fSubLeafMask != 0)
2435	{
2436	/*
2437	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2438	* Log everything while we're at it.
2439	*/
2440	LogRel(("CPUM:\n"
2441	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2442	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2443	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2444	for (;;)
2445	{
2446	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2447	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2448	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2449	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2450	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2451	break;
2452	pSubLeaf++;
2453	}
2454	LogRel(("CPUM:\n"));
2455
2456	/*
2457	* Remove the offending sub-leaves.
2458	*/
2459	if (pSubLeaf != pLeaf)
2460	{
2461	if (pSubLeaf != pLast)
2462	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2463	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2464	}
2465
2466	/*
2467	* Convert the first sub-leaf into a single leaf.
2468	*/
2469	pLeaf->uSubLeaf = 0;
2470	pLeaf->fSubLeafMask = 0;
2471	}
2472	return pLeaf;
2473	}
2474
2475
2476	/**
2477	* Sanitizes and adjust the CPUID leaves.
2478	*
2479	* Drop features that aren't virtualized (or virtualizable). Adjust information
2480	* and capabilities to fit the virtualized hardware. Remove information the
2481	* guest shouldn't have (because it's wrong in the virtual world or because it
2482	* gives away host details) or that we don't have documentation for and no idea
2483	* what means.
2484	*
2485	* @returns VBox status code.
2486	* @param pVM Pointer to the cross context VM structure (for cCpus).
2487	* @param pCpum The CPUM instance data.
2488	* @param pConfig The CPUID configuration we've read from CFGM.
2489	*/
2490	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2491	{
2492	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2493	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2494	{ \
2495	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2496	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2497	}
2498	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2499	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2500	{ \
2501	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2502	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2503	}
2504	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2505	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2506	&& ((a_pLeafReg) & (fBitMask)) \
2507	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2508	{ \
2509	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2510	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2511	}
2512	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2513
2514	/* Cpuid 1:
2515	* EAX: CPU model, family and stepping.
2516	*
2517	* ECX + EDX: Supported features. Only report features we can support.
2518	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2519	* options may require adjusting (i.e. stripping what was enabled).
2520	*
2521	* EBX: Branding, CLFLUSH line size, logical processors per package and
2522	* initial APIC ID.
2523	*/
2524	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2525	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2526	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2527
2528	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2529	\| X86_CPUID_FEATURE_EDX_VME
2530	\| X86_CPUID_FEATURE_EDX_DE
2531	\| X86_CPUID_FEATURE_EDX_PSE
2532	\| X86_CPUID_FEATURE_EDX_TSC
2533	\| X86_CPUID_FEATURE_EDX_MSR
2534	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2535	\| X86_CPUID_FEATURE_EDX_MCE
2536	\| X86_CPUID_FEATURE_EDX_CX8
2537	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2538	//\| RT_BIT_32(10) - not defined
2539	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2540	//\| X86_CPUID_FEATURE_EDX_SEP
2541	\| X86_CPUID_FEATURE_EDX_MTRR
2542	\| X86_CPUID_FEATURE_EDX_PGE
2543	\| X86_CPUID_FEATURE_EDX_MCA
2544	\| X86_CPUID_FEATURE_EDX_CMOV
2545	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2546	\| X86_CPUID_FEATURE_EDX_PSE36
2547	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2548	\| X86_CPUID_FEATURE_EDX_CLFSH
2549	//\| RT_BIT_32(20) - not defined
2550	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2551	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2552	\| X86_CPUID_FEATURE_EDX_MMX
2553	\| X86_CPUID_FEATURE_EDX_FXSR
2554	\| X86_CPUID_FEATURE_EDX_SSE
2555	\| X86_CPUID_FEATURE_EDX_SSE2
2556	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2557	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading/cores - see below.
2558	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2559	//\| RT_BIT_32(30) - not defined
2560	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2561	;
2562	pStdFeatureLeaf->uEcx &= 0
2563	\| X86_CPUID_FEATURE_ECX_SSE3
2564	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2565	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2566	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2567	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2568	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2569	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized yet.
2570	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2571	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2572	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2573	\| X86_CPUID_FEATURE_ECX_SSSE3
2574	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2575	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2576	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2577	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2578	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2579	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2580	//\| X86_CPUID_FEATURE_ECX_PCID - not implemented yet.
2581	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2582	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2583	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2584	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2585	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2586	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2587	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2588	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2589	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2590	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2591	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2592	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2593	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2594	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2595	;
2596
2597	if (pCpum->u8PortableCpuIdLevel > 0)
2598	{
2599	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2600	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2601	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2602	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2603	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2604	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2605	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2606	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2607	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2608	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2609	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2610	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2611	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2612	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2613	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2614	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2615	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2616	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2617
2618	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2619	\| X86_CPUID_FEATURE_EDX_PSN
2620	\| X86_CPUID_FEATURE_EDX_DS
2621	\| X86_CPUID_FEATURE_EDX_ACPI
2622	\| X86_CPUID_FEATURE_EDX_SS
2623	\| X86_CPUID_FEATURE_EDX_TM
2624	\| X86_CPUID_FEATURE_EDX_PBE
2625	)));
2626	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2627	\| X86_CPUID_FEATURE_ECX_CPLDS
2628	\| X86_CPUID_FEATURE_ECX_VMX
2629	\| X86_CPUID_FEATURE_ECX_SMX
2630	\| X86_CPUID_FEATURE_ECX_EST
2631	\| X86_CPUID_FEATURE_ECX_TM2
2632	\| X86_CPUID_FEATURE_ECX_CNTXID
2633	\| X86_CPUID_FEATURE_ECX_FMA
2634	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2635	\| X86_CPUID_FEATURE_ECX_PDCM
2636	\| X86_CPUID_FEATURE_ECX_DCA
2637	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2638	)));
2639	}
2640
2641	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2642	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2643	#ifdef VBOX_WITH_MULTI_CORE
2644	if (pVM->cCpus > 1)
2645	{
2646	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2647	core times the number of CPU cores per processor */
2648	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2649	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
2650	}
2651	#endif
2652
2653	/* Force standard feature bits. */
2654	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2655	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2656	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2657	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2658	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2659	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2660	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2661	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2662	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2663	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2664	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2665	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2666	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2667	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2668	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2669	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2670	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2671	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2672	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2673	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2674	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2675	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2676
2677	pStdFeatureLeaf = NULL; /* Must refetch! */
2678
2679	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2680	* AMD:
2681	* EAX: CPU model, family and stepping.
2682	*
2683	* ECX + EDX: Supported features. Only report features we can support.
2684	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2685	* options may require adjusting (i.e. stripping what was enabled).
2686	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2687	*
2688	* EBX: Branding ID and package type (or reserved).
2689	*
2690	* Intel and probably most others:
2691	* EAX: 0
2692	* EBX: 0
2693	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2694	*/
2695	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2696	if (pExtFeatureLeaf)
2697	{
2698	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2699
2700	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2701	\| X86_CPUID_AMD_FEATURE_EDX_VME
2702	\| X86_CPUID_AMD_FEATURE_EDX_DE
2703	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2704	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2705	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2706	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2707	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2708	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2709	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2710	//\| RT_BIT_32(10) - reserved
2711	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2712	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2713	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2714	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2715	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2716	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2717	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2718	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2719	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2720	//\| RT_BIT_32(18) - reserved
2721	//\| RT_BIT_32(19) - reserved
2722	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2723	//\| RT_BIT_32(21) - reserved
2724	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2725	\| X86_CPUID_AMD_FEATURE_EDX_MMX
2726	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
2727	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
2728	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2729	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2730	//\| RT_BIT_32(28) - reserved
2731	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2732	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2733	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
2734	;
2735	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2736	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2737	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
2738	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2739	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
2740	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2741	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2742	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2743	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2744	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2745	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2746	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
2747	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
2748	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2749	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
2750	//\| RT_BIT_32(14) - reserved
2751	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2752	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2753	//\| RT_BIT_32(17) - reserved
2754	//\| RT_BIT_32(18) - reserved
2755	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2756	//\| RT_BIT_32(20) - reserved
2757	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2758	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2759	//\| RT_BIT_32(23) - reserved
2760	//\| RT_BIT_32(24) - reserved
2761	//\| RT_BIT_32(25) - reserved
2762	//\| RT_BIT_32(26) - reserved
2763	//\| RT_BIT_32(27) - reserved
2764	//\| RT_BIT_32(28) - reserved
2765	//\| RT_BIT_32(29) - reserved
2766	//\| RT_BIT_32(30) - reserved
2767	//\| RT_BIT_32(31) - reserved
2768	;
2769	#ifdef VBOX_WITH_MULTI_CORE
2770	if ( pVM->cCpus > 1
2771	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2772	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2773	#endif
2774
2775	if (pCpum->u8PortableCpuIdLevel > 0)
2776	{
2777	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2778	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2779	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2780	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2781	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2782	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2783	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2784	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2785	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2786	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2787	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2788	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2789	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2790	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2791	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2792
2793	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2794	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2795	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2796	\| X86_CPUID_AMD_FEATURE_ECX_IBS
2797	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2798	\| X86_CPUID_AMD_FEATURE_ECX_WDT
2799	\| X86_CPUID_AMD_FEATURE_ECX_LWP
2800	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
2801	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2802	\| UINT32_C(0xff964000)
2803	)));
2804	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2805	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2806	\| RT_BIT(18)
2807	\| RT_BIT(19)
2808	\| RT_BIT(21)
2809	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2810	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2811	\| RT_BIT(28)
2812	)));
2813	}
2814
2815	/* Force extended feature bits. */
2816	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2817	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
2818	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2819	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2820	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2821	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2822	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2823	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2824	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2825	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2826	}
2827	pExtFeatureLeaf = NULL; /* Must refetch! */
2828
2829
2830	/* Cpuid 2:
2831	* Intel: (Nondeterministic) Cache and TLB information
2832	* AMD: Reserved
2833	* VIA: Reserved
2834	* Safe to expose.
2835	*/
2836	uint32_t uSubLeaf = 0;
2837	PCPUMCPUIDLEAF pCurLeaf;
2838	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2839	{
2840	if ((pCurLeaf->uEax & 0xff) > 1)
2841	{
2842	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2843	pCurLeaf->uEax &= UINT32_C(0xffffff01);
2844	}
2845	uSubLeaf++;
2846	}
2847
2848	/* Cpuid 3:
2849	* Intel: EAX, EBX - reserved (transmeta uses these)
2850	* ECX, EDX - Processor Serial Number if available, otherwise reserved
2851	* AMD: Reserved
2852	* VIA: Reserved
2853	* Safe to expose
2854	*/
2855	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2856	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
2857	{
2858	uSubLeaf = 0;
2859	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
2860	{
2861	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2862	if (pCpum->u8PortableCpuIdLevel > 0)
2863	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2864	uSubLeaf++;
2865	}
2866	}
2867
2868	/* Cpuid 4 + ECX:
2869	* Intel: Deterministic Cache Parameters Leaf.
2870	* AMD: Reserved
2871	* VIA: Reserved
2872	* Safe to expose, except for EAX:
2873	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
2874	* Bits 31-26: Maximum number of processor cores in this physical package**
2875	* Note: These SMP values are constant regardless of ECX
2876	*/
2877	uSubLeaf = 0;
2878	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
2879	{
2880	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
2881	#ifdef VBOX_WITH_MULTI_CORE
2882	if ( pVM->cCpus > 1
2883	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2884	{
2885	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
2886	/* One logical processor with possibly multiple cores. */
2887	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
2888	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
2889	}
2890	#endif
2891	uSubLeaf++;
2892	}
2893
2894	/* Cpuid 5: Monitor/mwait Leaf
2895	* Intel: ECX, EDX - reserved
2896	* EAX, EBX - Smallest and largest monitor line size
2897	* AMD: EDX - reserved
2898	* EAX, EBX - Smallest and largest monitor line size
2899	* ECX - extensions (ignored for now)
2900	* VIA: Reserved
2901	* Safe to expose
2902	*/
2903	uSubLeaf = 0;
2904	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
2905	{
2906	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2907	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
2908	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2909
2910	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2911	if (pConfig->enmMWaitExtensions)
2912	{
2913	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
2914	/** @todo: for now we just expose host's MWAIT C-states, although conceptually
2915	it shall be part of our power management virtualization model */
2916	#if 0
2917	/* MWAIT sub C-states */
2918	pCurLeaf->uEdx =
2919	(0 << 0) /* 0 in C0 */ \|
2920	(2 << 4) /* 2 in C1 */ \|
2921	(2 << 8) /* 2 in C2 */ \|
2922	(2 << 12) /* 2 in C3 */ \|
2923	(0 << 16) /* 0 in C4 */
2924	;
2925	#endif
2926	}
2927	else
2928	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2929	uSubLeaf++;
2930	}
2931
2932	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
2933	* Intel: Various stuff.
2934	* AMD: EAX, EBX, EDX - reserved.
2935	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
2936	* present. Same as intel.
2937	* VIA: ??
2938	*
2939	* We clear everything here for now.
2940	*/
2941	cpumR3CpuIdZeroLeaf(pCpum, 6);
2942
2943	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
2944	* EAX: Number of sub leaves.
2945	* EBX+ECX+EDX: Feature flags
2946	*
2947	* We only have documentation for one sub-leaf, so clear all other (no need
2948	* to remove them as such, just set them to zero).
2949	*
2950	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2951	* options may require adjusting (i.e. stripping what was enabled).
2952	*/
2953	uSubLeaf = 0;
2954	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
2955	{
2956	switch (uSubLeaf)
2957	{
2958	case 0:
2959	{
2960	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
2961	pCurLeaf->uEbx &= 0
2962	//\| X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
2963	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
2964	//\| RT_BIT(2) - reserved
2965	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
2966	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
2967	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
2968	//\| RT_BIT(6) - reserved
2969	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
2970	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
2971	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
2972	//\| X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
2973	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
2974	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
2975	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
2976	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
2977	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
2978	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
2979	//\| RT_BIT(17) - reserved
2980	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
2981	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
2982	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
2983	//\| RT_BIT(21) - reserved
2984	//\| RT_BIT(22) - reserved
2985	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
2986	//\| RT_BIT(24) - reserved
2987	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
2988	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
2989	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
2990	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
2991	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
2992	//\| RT_BIT(30) - reserved
2993	//\| RT_BIT(31) - reserved
2994	;
2995	pCurLeaf->uEcx &= 0
2996	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
2997	;
2998	pCurLeaf->uEdx &= 0;
2999
3000	if (pCpum->u8PortableCpuIdLevel > 0)
3001	{
3002	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
3003	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3004	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3005	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3006	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
3007	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3008	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3009	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3010	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3011	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3012	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3013	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3014	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3015	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3016	}
3017
3018	/* Force standard feature bits. */
3019	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3020	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3021	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3022	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3023	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3024	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3025	break;
3026	}
3027
3028	default:
3029	/* Invalid index, all values are zero. */
3030	pCurLeaf->uEax = 0;
3031	pCurLeaf->uEbx = 0;
3032	pCurLeaf->uEcx = 0;
3033	pCurLeaf->uEdx = 0;
3034	break;
3035	}
3036	uSubLeaf++;
3037	}
3038
3039	/* Cpuid 8: Marked as reserved by Intel and AMD.
3040	* We zero this since we don't know what it may have been used for.
3041	*/
3042	cpumR3CpuIdZeroLeaf(pCpum, 8);
3043
3044	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3045	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3046	* EBX, ECX, EDX - reserved.
3047	* AMD: Reserved
3048	* VIA: ??
3049	*
3050	* We zero this.
3051	*/
3052	cpumR3CpuIdZeroLeaf(pCpum, 9);
3053
3054	/* Cpuid 0xa: Architectural Performance Monitor Features
3055	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3056	* EBX, ECX, EDX - reserved.
3057	* AMD: Reserved
3058	* VIA: ??
3059	*
3060	* We zero this, for now at least.
3061	*/
3062	cpumR3CpuIdZeroLeaf(pCpum, 10);
3063
3064	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3065	* Intel: EAX - APCI ID shift right for next level.
3066	* EBX - Factory configured cores/threads at this level.
3067	* ECX - Level number (same as input) and level type (1,2,0).
3068	* EDX - Extended initial APIC ID.
3069	* AMD: Reserved
3070	* VIA: ??
3071	*/
3072	uSubLeaf = 0;
3073	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3074	{
3075	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3076	{
3077	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3078	if (bLevelType == 1)
3079	{
3080	/* Thread level - we don't do threads at the moment. */
3081	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3082	pCurLeaf->uEbx = 1;
3083	}
3084	else if (bLevelType == 2)
3085	{
3086	/* Core level. */
3087	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3088	#ifdef VBOX_WITH_MULTI_CORE
3089	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3090	pCurLeaf->uEax++;
3091	#endif
3092	pCurLeaf->uEbx = pVM->cCpus;
3093	}
3094	else
3095	{
3096	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3097	pCurLeaf->uEax = 0;
3098	pCurLeaf->uEbx = 0;
3099	pCurLeaf->uEcx = 0;
3100	}
3101	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3102	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3103	}
3104	else
3105	{
3106	pCurLeaf->uEax = 0;
3107	pCurLeaf->uEbx = 0;
3108	pCurLeaf->uEcx = 0;
3109	pCurLeaf->uEdx = 0;
3110	}
3111	uSubLeaf++;
3112	}
3113
3114	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3115	* We zero this since we don't know what it may have been used for.
3116	*/
3117	cpumR3CpuIdZeroLeaf(pCpum, 12);
3118
3119	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3120	* ECX=0: EAX - Valid bits in XCR0[31:0].
3121	* EBX - Maximum state size as per current XCR0 value.
3122	* ECX - Maximum state size for all supported features.
3123	* EDX - Valid bits in XCR0[63:32].
3124	* ECX=1: EAX - Various X-features.
3125	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3126	* ECX - Valid bits in IA32_XSS[31:0].
3127	* EDX - Valid bits in IA32_XSS[63:32].
3128	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3129	* if the bit invalid all four registers are set to zero.
3130	* EAX - The state size for this feature.
3131	* EBX - The state byte offset of this feature.
3132	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3133	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3134	*
3135	* Clear them all as we don't currently implement extended CPU state.
3136	*/
3137	/* Figure out the supported XCR0/XSS mask component. */
3138	uint64_t fGuestXcr0Mask = 0;
3139	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3140	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3141	{
3142	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3143	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3144	fGuestXcr0Mask \|= XSAVE_C_YMM;
3145	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3146	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3147	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3148	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3149	}
3150	pStdFeatureLeaf = NULL;
3151	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3152
3153	/* Work the sub-leaves. */
3154	uint32_t cbXSaveMax = sizeof(X86FXSTATE);
3155	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3156	{
3157	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3158	if (pCurLeaf)
3159	{
3160	if (fGuestXcr0Mask)
3161	{
3162	switch (uSubLeaf)
3163	{
3164	case 0:
3165	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3166	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3167	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3168	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3169	VERR_CPUM_IPE_1);
3170	cbXSaveMax = pCurLeaf->uEcx;
3171	AssertLogRelMsgReturn(cbXSaveMax <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMax >= CPUM_MIN_XSAVE_AREA_SIZE,
3172	("%#x max=%#x\n", cbXSaveMax, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3173	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMax,
3174	("ebx=%#x cbXSaveMax=%#x\n", pCurLeaf->uEbx, cbXSaveMax),
3175	VERR_CPUM_IPE_2);
3176	continue;
3177	case 1:
3178	pCurLeaf->uEax &= 0;
3179	pCurLeaf->uEcx &= 0;
3180	pCurLeaf->uEdx &= 0;
3181	/** @todo what about checking ebx? */
3182	continue;
3183	default:
3184	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3185	{
3186	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMax
3187	&& pCurLeaf->uEax > 0
3188	&& pCurLeaf->uEbx < cbXSaveMax
3189	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3190	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMax,
3191	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3192	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMax),
3193	VERR_CPUM_IPE_2);
3194	AssertLogRel(!(pCurLeaf->uEcx & 1));
3195	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3196	pCurLeaf->uEdx = 0; /* it's reserved... */
3197	continue;
3198	}
3199	break;
3200	}
3201	}
3202
3203	/* Clear the leaf. */
3204	pCurLeaf->uEax = 0;
3205	pCurLeaf->uEbx = 0;
3206	pCurLeaf->uEcx = 0;
3207	pCurLeaf->uEdx = 0;
3208	}
3209	}
3210
3211	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3212	* We zero this since we don't know what it may have been used for.
3213	*/
3214	cpumR3CpuIdZeroLeaf(pCpum, 14);
3215
3216	/* Cpuid 0xf + ECX: Platform qualifity of service monitoring (PQM).
3217	* We zero this as we don't currently virtualize PQM.
3218	*/
3219	cpumR3CpuIdZeroLeaf(pCpum, 15);
3220
3221	/* Cpuid 0x10 + ECX: Platform qualifity of service enforcement (PQE).
3222	* We zero this as we don't currently virtualize PQE.
3223	*/
3224	cpumR3CpuIdZeroLeaf(pCpum, 16);
3225
3226	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3227	* We zero this since we don't know what it may have been used for.
3228	*/
3229	cpumR3CpuIdZeroLeaf(pCpum, 17);
3230
3231	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3232	* We zero this as we don't currently virtualize this.
3233	*/
3234	cpumR3CpuIdZeroLeaf(pCpum, 18);
3235
3236	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3237	* We zero this since we don't know what it may have been used for.
3238	*/
3239	cpumR3CpuIdZeroLeaf(pCpum, 19);
3240
3241	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3242	* We zero this as we don't currently virtualize this.
3243	*/
3244	cpumR3CpuIdZeroLeaf(pCpum, 20);
3245
3246	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3247	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3248	* EAX - denominator (unsigned).
3249	* EBX - numerator (unsigned).
3250	* ECX, EDX - reserved.
3251	* AMD: Reserved / undefined / not implemented.
3252	* VIA: Reserved / undefined / not implemented.
3253	* We zero this as we don't currently virtualize this.
3254	*/
3255	cpumR3CpuIdZeroLeaf(pCpum, 21);
3256
3257	/* Cpuid 0x16: Processor frequency info
3258	* Intel: EAX - Core base frequency in MHz.
3259	* EBX - Core maximum frequency in MHz.
3260	* ECX - Bus (reference) frequency in MHz.
3261	* EDX - Reserved.
3262	* AMD: Reserved / undefined / not implemented.
3263	* VIA: Reserved / undefined / not implemented.
3264	* We zero this as we don't currently virtualize this.
3265	*/
3266	cpumR3CpuIdZeroLeaf(pCpum, 22);
3267
3268	/* Cpuid 0x17..0x10000000: Unknown.
3269	* We don't know these and what they mean, so remove them. */
3270	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3271	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3272
3273
3274	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3275	* We remove all these as we're a hypervisor and must provide our own.
3276	*/
3277	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3278	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3279
3280
3281	/* Cpuid 0x80000000 is harmless. */
3282
3283	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3284
3285	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3286
3287	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3288	* Safe to pass on to the guest.
3289	*
3290	* AMD: 0x800000005 L1 cache information
3291	* 0x800000006 L2/L3 cache information
3292	* Intel: 0x800000005 reserved
3293	* 0x800000006 L2 cache information
3294	* VIA: 0x800000005 TLB and L1 cache information
3295	* 0x800000006 L2 cache information
3296	*/
3297
3298	/* Cpuid 0x800000007: Advanced Power Management Information.
3299	* AMD: EAX: Processor feedback capabilities.
3300	* EBX: RAS capabilites.
3301	* ECX: Advanced power monitoring interface.
3302	* EDX: Enhanced power management capabilities.
3303	* Intel: EAX, EBX, ECX - reserved.
3304	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3305	* VIA: Reserved
3306	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3307	*/
3308	uSubLeaf = 0;
3309	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3310	{
3311	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3312	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3313	{
3314	pCurLeaf->uEdx &= 0
3315	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3316	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3317	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3318	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3319	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3320	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3321	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3322	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3323	#if 0 /*
3324	* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
3325	* Linux kernels blindly assume that the AMD performance counters work
3326	* if this is set for 64 bits guests. (Can't really find a CPUID feature
3327	* bit for them though.)
3328	*/
3329	/** @todo need to recheck this with new MSR emulation. */
3330	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3331	#endif
3332	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3333	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3334	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3335	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3336	\| 0;
3337	}
3338	else
3339	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3340	if (pConfig->fInvariantTsc)
3341	pCurLeaf->uEdx \|= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3342	uSubLeaf++;
3343	}
3344
3345	/* Cpuid 0x80000008:
3346	* AMD: EBX, EDX - reserved
3347	* EAX: Virtual/Physical/Guest address Size
3348	* ECX: Number of cores + APICIdCoreIdSize
3349	* Intel: EAX: Virtual/Physical address Size
3350	* EBX, ECX, EDX - reserved
3351	* VIA: EAX: Virtual/Physical address Size
3352	* EBX, ECX, EDX - reserved
3353	*
3354	* We only expose the virtual+pysical address size to the guest atm.
3355	* On AMD we set the core count, but not the apic id stuff as we're
3356	* currently not doing the apic id assignments in a complatible manner.
3357	*/
3358	uSubLeaf = 0;
3359	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3360	{
3361	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3362	pCurLeaf->uEbx = 0; /* reserved */
3363	pCurLeaf->uEdx = 0; /* reserved */
3364
3365	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3366	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3367	pCurLeaf->uEcx = 0;
3368	#ifdef VBOX_WITH_MULTI_CORE
3369	if ( pVM->cCpus > 1
3370	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3371	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3372	#endif
3373	uSubLeaf++;
3374	}
3375
3376	/* Cpuid 0x80000009: Reserved
3377	* We zero this since we don't know what it may have been used for.
3378	*/
3379	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3380
3381	/* Cpuid 0x8000000a: SVM Information
3382	* AMD: EAX - SVM revision.
3383	* EBX - Number of ASIDs.
3384	* ECX - Reserved.
3385	* EDX - SVM Feature identification.
3386	* We clear all as we currently does not virtualize SVM.
3387	*/
3388	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3389
3390	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3391	* We clear these as we don't know what purpose they might have. */
3392	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3393	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3394
3395	/* Cpuid 0x80000019: TLB configuration
3396	* Seems to be harmless, pass them thru as is. */
3397
3398	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3399	* Strip anything we don't know what is or addresses feature we don't implement. */
3400	uSubLeaf = 0;
3401	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3402	{
3403	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3404	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3405	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3406	;
3407	pCurLeaf->uEbx = 0; /* reserved */
3408	pCurLeaf->uEcx = 0; /* reserved */
3409	pCurLeaf->uEdx = 0; /* reserved */
3410	uSubLeaf++;
3411	}
3412
3413	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3414	* Clear this as we don't currently virtualize this feature. */
3415	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3416
3417	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3418	* Clear this as we don't currently virtualize this feature. */
3419	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3420
3421	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3422	* We need to sanitize the cores per cache (EAX[25:14]).
3423	*
3424	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3425	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3426	* slightly different meaning.
3427	*/
3428	uSubLeaf = 0;
3429	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3430	{
3431	#ifdef VBOX_WITH_MULTI_CORE
3432	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3433	if (cCores > pVM->cCpus)
3434	cCores = pVM->cCpus;
3435	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3436	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3437	#else
3438	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3439	#endif
3440	uSubLeaf++;
3441	}
3442
3443	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3444	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3445	* setup, we have one compute unit with all the cores in it. Single node.
3446	*/
3447	uSubLeaf = 0;
3448	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3449	{
3450	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3451	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3452	{
3453	#ifdef VBOX_WITH_MULTI_CORE
3454	pCurLeaf->uEbx = pVM->cCpus < 0x100
3455	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3456	#else
3457	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3458	#endif
3459	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3460	}
3461	else
3462	{
3463	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3464	pCurLeaf->uEbx = 0; /* Reserved. */
3465	pCurLeaf->uEcx = 0; /* Reserved. */
3466	}
3467	pCurLeaf->uEdx = 0; /* Reserved. */
3468	uSubLeaf++;
3469	}
3470
3471	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3472	* We don't know these and what they mean, so remove them. */
3473	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3474	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3475
3476	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3477	* Just pass it thru for now. */
3478
3479	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3480	* Just pass it thru for now. */
3481
3482	/* Cpuid 0xc0000000: Centaur stuff.
3483	* Harmless, pass it thru. */
3484
3485	/* Cpuid 0xc0000001: Centaur features.
3486	* VIA: EAX - Family, model, stepping.
3487	* EDX - Centaur extended feature flags. Nothing interesting, except may
3488	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3489	* EBX, ECX - reserved.
3490	* We keep EAX but strips the rest.
3491	*/
3492	uSubLeaf = 0;
3493	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3494	{
3495	pCurLeaf->uEbx = 0;
3496	pCurLeaf->uEcx = 0;
3497	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3498	uSubLeaf++;
3499	}
3500
3501	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3502	* We only have fixed stale values, but should be harmless. */
3503
3504	/* Cpuid 0xc0000003: Reserved.
3505	* We zero this since we don't know what it may have been used for.
3506	*/
3507	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3508
3509	/* Cpuid 0xc0000004: Centaur Performance Info.
3510	* We only have fixed stale values, but should be harmless. */
3511
3512
3513	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3514	* We don't know these and what they mean, so remove them. */
3515	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3516	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3517
3518	return VINF_SUCCESS;
3519	#undef PORTABLE_DISABLE_FEATURE_BIT
3520	#undef PORTABLE_CLEAR_BITS_WHEN
3521	}
3522
3523
3524	/**
3525	* Reads a value in /CPUM/IsaExts/ node.
3526	*
3527	* @returns VBox status code (error message raised).
3528	* @param pVM The VM handle (for errors).
3529	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3530	* @param pszValueName The value / extension name.
3531	* @param penmValue Where to return the choice.
3532	* @param enmDefault The default choice.
3533	*/
3534	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3535	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3536	{
3537	/*
3538	* Try integer encoding first.
3539	*/
3540	uint64_t uValue;
3541	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3542	if (RT_SUCCESS(rc))
3543	switch (uValue)
3544	{
3545	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3546	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3547	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3548	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3549	default:
3550	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3551	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3552	pszValueName, uValue);
3553	}
3554	/*
3555	* If missing, use default.
3556	*/
3557	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3558	*penmValue = enmDefault;
3559	else
3560	{
3561	if (rc == VERR_CFGM_NOT_INTEGER)
3562	{
3563	/*
3564	* Not an integer, try read it as a string.
3565	*/
3566	char szValue[32];
3567	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3568	if (RT_SUCCESS(rc))
3569	{
3570	RTStrToLower(szValue);
3571	size_t cchValue = strlen(szValue);
3572	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3573	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3574	*penmValue = CPUMISAEXTCFG_DISABLED;
3575	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3576	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3577	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3578	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3579	else if (EQ("portable"))
3580	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3581	else if (EQ("default") \|\| EQ("def"))
3582	*penmValue = enmDefault;
3583	else
3584	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3585	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3586	pszValueName, uValue);
3587	#undef EQ
3588	}
3589	}
3590	if (RT_FAILURE(rc))
3591	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3592	}
3593	return VINF_SUCCESS;
3594	}
3595
3596
3597	/**
3598	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3599	*
3600	* @returns VBox status code (error message raised).
3601	* @param pVM The VM handle (for errors).
3602	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3603	* @param pszValueName The value / extension name.
3604	* @param penmValue Where to return the choice.
3605	* @param enmDefault The default choice.
3606	* @param fAllowed Allowed choice. Applied both to the result and to
3607	* the default value.
3608	*/
3609	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3610	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3611	{
3612	int rc;
3613	if (fAllowed)
3614	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3615	else
3616	{
3617	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3618	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3619	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3620	*penmValue = CPUMISAEXTCFG_DISABLED;
3621	}
3622	return rc;
3623	}
3624
3625
3626	/**
3627	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3628	*
3629	* @returns VBox status code (error message raised).
3630	* @param pVM The VM handle (for errors).
3631	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3632	* @param pCpumCfg The /CPUM node (can be NULL).
3633	* @param pszValueName The value / extension name.
3634	* @param penmValue Where to return the choice.
3635	* @param enmDefault The default choice.
3636	*/
3637	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3638	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3639	{
3640	if (CFGMR3Exists(pCpumCfg, pszValueName))
3641	{
3642	if (!CFGMR3Exists(pIsaExts, pszValueName))
3643	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3644	else
3645	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3646	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3647	pszValueName, pszValueName);
3648
3649	bool fLegacy;
3650	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3651	if (RT_SUCCESS(rc))
3652	{
3653	*penmValue = fLegacy;
3654	return VINF_SUCCESS;
3655	}
3656	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3657	}
3658
3659	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3660	}
3661
3662
3663	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3664	{
3665	int rc;
3666
3667	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3668	* When non-zero CPUID features that could cause portability issues will be
3669	* stripped. The higher the value the more features gets stripped. Higher
3670	* values should only be used when older CPUs are involved since it may
3671	* harm performance and maybe also cause problems with specific guests. */
3672	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
3673	AssertLogRelRCReturn(rc, rc);
3674
3675	/** @cfgm{/CPUM/GuestCpuName, string}
3676	* The name of the CPU we're to emulate. The default is the host CPU.
3677	* Note! CPUs other than "host" one is currently unsupported. */
3678	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3679	AssertLogRelRCReturn(rc, rc);
3680
3681	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3682	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3683	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3684	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3685	*/
3686	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3687	AssertLogRelRCReturn(rc, rc);
3688
3689	/** @cfgm{/CPUM/InvariantTsc, boolean, complicated}
3690	* Set the invariant TSC flag in 0x80000007 if true, otherwas take default
3691	* action. By default the flag is passed thru as is from the host CPU, except
3692	* on AMD CPUs where it's suppressed to avoid trouble from linux assuming we
3693	* virtualize performance counters.
3694	*/
3695	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, false);
3696	AssertLogRelRCReturn(rc, rc);
3697
3698	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3699	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
3700	* probably going to be a temporary hack, so don't depend on this.
3701	* The 1st byte of the value is the stepping, the 2nd byte value is the model
3702	* number and the 3rd byte value is the family, and the 4th value must be zero.
3703	*/
3704	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3705	AssertLogRelRCReturn(rc, rc);
3706
3707	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3708	* The last standard leaf to keep. The actual last value that is stored in EAX
3709	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3710	* removed. (This works independently of and differently from NT4LeafLimit.)
3711	* The default is usually set to what we're able to reasonably sanitize.
3712	*/
3713	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3714	AssertLogRelRCReturn(rc, rc);
3715
3716	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3717	* The last extended leaf to keep. The actual last value that is stored in EAX
3718	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3719	* leaf are removed. The default is set to what we're able to sanitize.
3720	*/
3721	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3722	AssertLogRelRCReturn(rc, rc);
3723
3724	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3725	* The last extended leaf to keep. The actual last value that is stored in EAX
3726	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3727	* leaf are removed. The default is set to what we're able to sanitize.
3728	*/
3729	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3730	AssertLogRelRCReturn(rc, rc);
3731
3732
3733	/*
3734	* Instruction Set Architecture (ISA) Extensions.
3735	*/
3736	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3737	if (pIsaExts)
3738	{
3739	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3740	"CMPXCHG16B"
3741	"\|MONITOR"
3742	"\|MWaitExtensions"
3743	"\|SSE4.1"
3744	"\|SSE4.2"
3745	"\|XSAVE"
3746	"\|AVX"
3747	"\|AVX2"
3748	"\|AESNI"
3749	"\|PCLMUL"
3750	"\|POPCNT"
3751	"\|MOVBE"
3752	"\|RDRAND"
3753	"\|RDSEED"
3754	"\|CLFLUSHOPT"
3755	"\|ABM"
3756	"\|SSE4A"
3757	"\|MISALNSSE"
3758	"\|3DNOWPRF"
3759	"\|AXMMX"
3760	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
3761	if (RT_FAILURE(rc))
3762	return rc;
3763	}
3764
3765	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
3766	* Expose CMPXCHG16B to the guest if supported by the host. For the time
3767	* being the default is to only do this for VMs with nested paging and AMD-V or
3768	* unrestricted guest mode.
3769	*/
3770	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
3771	AssertLogRelRCReturn(rc, rc);
3772
3773	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
3774	* Expose MONITOR/MWAIT instructions to the guest.
3775	*/
3776	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
3777	AssertLogRelRCReturn(rc, rc);
3778
3779	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
3780	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
3781	* break on interrupt feature (bit 1).
3782	*/
3783	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
3784	AssertLogRelRCReturn(rc, rc);
3785
3786	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
3787	* Expose SSE4.1 to the guest if available.
3788	*/
3789	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
3790	AssertLogRelRCReturn(rc, rc);
3791
3792	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
3793	* Expose SSE4.2 to the guest if available.
3794	*/
3795	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
3796	AssertLogRelRCReturn(rc, rc);
3797
3798	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
3799	&& pVM->cpum.s.HostFeatures.fXSaveRstor
3800	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
3801	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
3802	&& !HMIsLongModeAllowed(pVM)
3803	#endif
3804	;
3805	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
3806
3807	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
3808	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
3809	* default is to only expose this to VMs with nested paging and AMD-V or
3810	* unrestricted guest execution mode. Not possible to force this one without
3811	* host support at the moment.
3812	*/
3813	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
3814	fMayHaveXSave /fAllowed/);
3815	AssertLogRelRCReturn(rc, rc);
3816
3817	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
3818	* Expose the AVX instruction set extensions to the guest if available and
3819	* XSAVE is exposed too. For the time being the default is to only expose this
3820	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3821	*/
3822	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
3823	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3824	AssertLogRelRCReturn(rc, rc);
3825
3826	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
3827	* Expose the AVX2 instruction set extensions to the guest if available and
3828	* XSAVE is exposed too. For the time being the default is to only expose this
3829	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3830	*/
3831	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec && false /* temporarily */,
3832	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3833	AssertLogRelRCReturn(rc, rc);
3834
3835	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
3836	* Whether to expose the AES instructions to the guest. For the time being the
3837	* default is to only do this for VMs with nested paging and AMD-V or
3838	* unrestricted guest mode.
3839	*/
3840	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
3841	AssertLogRelRCReturn(rc, rc);
3842
3843	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
3844	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
3845	* being the default is to only do this for VMs with nested paging and AMD-V or
3846	* unrestricted guest mode.
3847	*/
3848	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
3849	AssertLogRelRCReturn(rc, rc);
3850
3851	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
3852	* Whether to expose the POPCNT instructions to the guest. For the time
3853	* being the default is to only do this for VMs with nested paging and AMD-V or
3854	* unrestricted guest mode.
3855	*/
3856	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
3857	AssertLogRelRCReturn(rc, rc);
3858
3859	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
3860	* Whether to expose the MOVBE instructions to the guest. For the time
3861	* being the default is to only do this for VMs with nested paging and AMD-V or
3862	* unrestricted guest mode.
3863	*/
3864	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
3865	AssertLogRelRCReturn(rc, rc);
3866
3867	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
3868	* Whether to expose the RDRAND instructions to the guest. For the time being
3869	* the default is to only do this for VMs with nested paging and AMD-V or
3870	* unrestricted guest mode.
3871	*/
3872	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
3873	AssertLogRelRCReturn(rc, rc);
3874
3875	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
3876	* Whether to expose the RDSEED instructions to the guest. For the time being
3877	* the default is to only do this for VMs with nested paging and AMD-V or
3878	* unrestricted guest mode.
3879	*/
3880	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
3881	AssertLogRelRCReturn(rc, rc);
3882
3883	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
3884	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
3885	* being the default is to only do this for VMs with nested paging and AMD-V or
3886	* unrestricted guest mode.
3887	*/
3888	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
3889	AssertLogRelRCReturn(rc, rc);
3890
3891
3892	/* AMD: */
3893
3894	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
3895	* Whether to expose the AMD ABM instructions to the guest. For the time
3896	* being the default is to only do this for VMs with nested paging and AMD-V or
3897	* unrestricted guest mode.
3898	*/
3899	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
3900	AssertLogRelRCReturn(rc, rc);
3901
3902	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
3903	* Whether to expose the AMD SSE4A instructions to the guest. For the time
3904	* being the default is to only do this for VMs with nested paging and AMD-V or
3905	* unrestricted guest mode.
3906	*/
3907	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
3908	AssertLogRelRCReturn(rc, rc);
3909
3910	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
3911	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
3912	* the time being the default is to only do this for VMs with nested paging and
3913	* AMD-V or unrestricted guest mode.
3914	*/
3915	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
3916	AssertLogRelRCReturn(rc, rc);
3917
3918	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
3919	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
3920	* For the time being the default is to only do this for VMs with nested paging
3921	* and AMD-V or unrestricted guest mode.
3922	*/
3923	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
3924	AssertLogRelRCReturn(rc, rc);
3925
3926	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
3927	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
3928	* the default is to only do this for VMs with nested paging and AMD-V or
3929	* unrestricted guest mode.
3930	*/
3931	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
3932	AssertLogRelRCReturn(rc, rc);
3933
3934	return VINF_SUCCESS;
3935	}
3936
3937
3938	/**
3939	* Initializes the emulated CPU's CPUID & MSR information.
3940	*
3941	* @returns VBox status code.
3942	* @param pVM Pointer to the VM.
3943	*/
3944	int cpumR3InitCpuIdAndMsrs(PVM pVM)
3945	{
3946	PCPUM pCpum = &pVM->cpum.s;
3947	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
3948
3949	/*
3950	* Read the configuration.
3951	*/
3952	CPUMCPUIDCONFIG Config;
3953	RT_ZERO(Config);
3954
3955	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
3956	AssertRCReturn(rc, rc);
3957
3958	/*
3959	* Get the guest CPU data from the database and/or the host.
3960	*
3961	* The CPUID and MSRs are currently living on the regular heap to avoid
3962	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
3963	* API for the hyper heap). This means special cleanup considerations.
3964	*/
3965	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
3966	if (RT_FAILURE(rc))
3967	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
3968	? VMSetError(pVM, rc, RT_SRC_POS,
3969	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
3970	: rc;
3971
3972	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
3973	* Overrides the guest MSRs.
3974	*/
3975	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
3976
3977	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
3978	* Overrides the CPUID leaf values (from the host CPU usually) used for
3979	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
3980	* values when moving a VM to a different machine. Another use is restricting
3981	* (or extending) the feature set exposed to the guest. */
3982	if (RT_SUCCESS(rc))
3983	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
3984
3985	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
3986	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
3987	"Found unsupported configuration node '/CPUM/CPUID/'. "
3988	"Please use IMachine::setCPUIDLeaf() instead.");
3989
3990	/*
3991	* Pre-explode the CPUID info.
3992	*/
3993	if (RT_SUCCESS(rc))
3994	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
3995
3996	/*
3997	* Sanitize the cpuid information passed on to the guest.
3998	*/
3999	if (RT_SUCCESS(rc))
4000	{
4001	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4002	if (RT_SUCCESS(rc))
4003	{
4004	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4005	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4006	}
4007	}
4008
4009	/*
4010	* Plant our own hypervisor CPUID leaves.
4011	*/
4012	if (RT_SUCCESS(rc))
4013	rc = cpumR3CpuIdPlantHypervisorLeaves(pCpum, &Config);
4014
4015	/*
4016	* MSR fudging.
4017	*/
4018	if (RT_SUCCESS(rc))
4019	{
4020	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4021	* Fudges some common MSRs if not present in the selected CPU database entry.
4022	* This is for trying to keep VMs running when moved between different hosts
4023	* and different CPU vendors. */
4024	bool fEnable;
4025	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4026	if (RT_SUCCESS(rc) && fEnable)
4027	{
4028	rc = cpumR3MsrApplyFudge(pVM);
4029	AssertLogRelRC(rc);
4030	}
4031	}
4032	if (RT_SUCCESS(rc))
4033	{
4034	/*
4035	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4036	* guest CPU features again.
4037	*/
4038	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4039	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4040	pCpum->GuestInfo.cCpuIdLeaves);
4041	RTMemFree(pvFree);
4042
4043	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4044	int rc2 = MMHyperDupMem(pVM, pvFree,
4045	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4046	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4047	RTMemFree(pvFree);
4048	AssertLogRelRCReturn(rc1, rc1);
4049	AssertLogRelRCReturn(rc2, rc2);
4050
4051	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4052	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4053
4054
4055	/*
4056	* Some more configuration that we're applying at the end of everything
4057	* via the CPUMSetGuestCpuIdFeature API.
4058	*/
4059
4060	/* Check if PAE was explicitely enabled by the user. */
4061	bool fEnable;
4062	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4063	AssertRCReturn(rc, rc);
4064	if (fEnable)
4065	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4066
4067	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4068	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4069	AssertRCReturn(rc, rc);
4070	if (fEnable)
4071	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4072
4073	/* We don't enable the Hypervisor Present bit by default, but it may be needed by some guests. */
4074	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false);
4075	AssertRCReturn(rc, rc);
4076	if (fEnable)
4077	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
4078
4079	return VINF_SUCCESS;
4080	}
4081
4082	/*
4083	* Failed before switching to hyper heap.
4084	*/
4085	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4086	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4087	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4088	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4089	return rc;
4090	}
4091
4092
4093
4094	/*
4095	*
4096	*
4097	* Saved state related code.
4098	* Saved state related code.
4099	* Saved state related code.
4100	*
4101	*
4102	*/
4103
4104	/**
4105	* Called both in pass 0 and the final pass.
4106	*
4107	* @param pVM Pointer to the VM.
4108	* @param pSSM The saved state handle.
4109	*/
4110	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4111	{
4112	/*
4113	* Save all the CPU ID leaves.
4114	*/
4115	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4116	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4117	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4118	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4119
4120	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4121
4122	/*
4123	* Save a good portion of the raw CPU IDs as well as they may come in
4124	* handy when validating features for raw mode.
4125	*/
4126	CPUMCPUID aRawStd[16];
4127	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4128	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4129	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4130	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4131
4132	CPUMCPUID aRawExt[32];
4133	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4134	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4135	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4136	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4137	}
4138
4139
4140	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4141	{
4142	uint32_t cCpuIds;
4143	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4144	if (RT_SUCCESS(rc))
4145	{
4146	if (cCpuIds < 64)
4147	{
4148	for (uint32_t i = 0; i < cCpuIds; i++)
4149	{
4150	CPUMCPUID CpuId;
4151	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4152	if (RT_FAILURE(rc))
4153	break;
4154
4155	CPUMCPUIDLEAF NewLeaf;
4156	NewLeaf.uLeaf = uBase + i;
4157	NewLeaf.uSubLeaf = 0;
4158	NewLeaf.fSubLeafMask = 0;
4159	NewLeaf.uEax = CpuId.uEax;
4160	NewLeaf.uEbx = CpuId.uEbx;
4161	NewLeaf.uEcx = CpuId.uEcx;
4162	NewLeaf.uEdx = CpuId.uEdx;
4163	NewLeaf.fFlags = 0;
4164	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4165	}
4166	}
4167	else
4168	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4169	}
4170	if (RT_FAILURE(rc))
4171	{
4172	RTMemFree(*ppaLeaves);
4173	*ppaLeaves = NULL;
4174	*pcLeaves = 0;
4175	}
4176	return rc;
4177	}
4178
4179
4180	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4181	{
4182	*ppaLeaves = NULL;
4183	*pcLeaves = 0;
4184
4185	int rc;
4186	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4187	{
4188	/*
4189	* The new format. Starts by declaring the leave size and count.
4190	*/
4191	uint32_t cbLeaf;
4192	SSMR3GetU32(pSSM, &cbLeaf);
4193	uint32_t cLeaves;
4194	rc = SSMR3GetU32(pSSM, &cLeaves);
4195	if (RT_SUCCESS(rc))
4196	{
4197	if (cbLeaf == sizeof(**ppaLeaves))
4198	{
4199	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4200	{
4201	/*
4202	* Load the leaves one by one.
4203	*
4204	* The uPrev stuff is a kludge for working around a week worth of bad saved
4205	* states during the CPUID revamp in March 2015. We saved too many leaves
4206	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4207	* garbage entires at the end of the array when restoring. We also had
4208	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
4209	* this kludge doesn't deal correctly with that, but who cares...
4210	*/
4211	uint32_t uPrev = 0;
4212	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4213	{
4214	CPUMCPUIDLEAF Leaf;
4215	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
4216	if (RT_SUCCESS(rc))
4217	{
4218	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
4219	\|\| Leaf.uLeaf >= uPrev)
4220	{
4221	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4222	uPrev = Leaf.uLeaf;
4223	}
4224	else
4225	uPrev = UINT32_MAX;
4226	}
4227	}
4228	}
4229	else
4230	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
4231	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
4232	}
4233	else
4234	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
4235	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
4236	}
4237	}
4238	else
4239	{
4240	/*
4241	* The old format with its three inflexible arrays.
4242	*/
4243	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
4244	if (RT_SUCCESS(rc))
4245	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
4246	if (RT_SUCCESS(rc))
4247	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
4248	if (RT_SUCCESS(rc))
4249	{
4250	/*
4251	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
4252	*/
4253	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
4254	if ( pLeaf
4255	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
4256	{
4257	CPUMCPUIDLEAF Leaf;
4258	Leaf.uLeaf = 4;
4259	Leaf.fSubLeafMask = UINT32_MAX;
4260	Leaf.uSubLeaf = 0;
4261	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
4262	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
4263	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
4264	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
4265	\| UINT32_C(63); /* system coherency line size - 1 */
4266	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
4267	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
4268	\| (UINT32_C(1) << 5) /* cache level */
4269	\| UINT32_C(1); /* cache type (data) */
4270	Leaf.fFlags = 0;
4271	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4272	if (RT_SUCCESS(rc))
4273	{
4274	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
4275	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4276	}
4277	if (RT_SUCCESS(rc))
4278	{
4279	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
4280	Leaf.uEcx = 4095; /* sets - 1 */
4281	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
4282	Leaf.uEbx \|= UINT32_C(23) << 22;
4283	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
4284	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
4285	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
4286	Leaf.uEax \|= UINT32_C(2) << 5;
4287	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4288	}
4289	}
4290	}
4291	}
4292	return rc;
4293	}
4294
4295
4296	/**
4297	* Loads the CPU ID leaves saved by pass 0, inner worker.
4298	*
4299	* @returns VBox status code.
4300	* @param pVM Pointer to the VM.
4301	* @param pSSM The saved state handle.
4302	* @param uVersion The format version.
4303	* @param paLeaves Guest CPUID leaves loaded from the state.
4304	* @param cLeaves The number of leaves in @a paLeaves.
4305	*/
4306	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
4307	{
4308	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4309
4310	/*
4311	* Continue loading the state into stack buffers.
4312	*/
4313	CPUMCPUID GuestDefCpuId;
4314	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
4315	AssertRCReturn(rc, rc);
4316
4317	CPUMCPUID aRawStd[16];
4318	uint32_t cRawStd;
4319	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
4320	if (cRawStd > RT_ELEMENTS(aRawStd))
4321	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4322	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
4323	AssertRCReturn(rc, rc);
4324	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
4325	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4326
4327	CPUMCPUID aRawExt[32];
4328	uint32_t cRawExt;
4329	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
4330	if (cRawExt > RT_ELEMENTS(aRawExt))
4331	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4332	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
4333	AssertRCReturn(rc, rc);
4334	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
4335	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4336
4337	/*
4338	* Get the raw CPU IDs for the current host.
4339	*/
4340	CPUMCPUID aHostRawStd[16];
4341	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
4342	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
4343
4344	CPUMCPUID aHostRawExt[32];
4345	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
4346	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
4347	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4348
4349	/*
4350	* Get the host and guest overrides so we don't reject the state because
4351	* some feature was enabled thru these interfaces.
4352	* Note! We currently only need the feature leaves, so skip rest.
4353	*/
4354	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4355	CPUMCPUID aHostOverrideStd[2];
4356	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4357	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4358
4359	CPUMCPUID aHostOverrideExt[2];
4360	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4361	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4362
4363	/*
4364	* This can be skipped.
4365	*/
4366	bool fStrictCpuIdChecks;
4367	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
4368
4369	/*
4370	* Define a bunch of macros for simplifying the santizing/checking code below.
4371	*/
4372	/* Generic expression + failure message. */
4373	#define CPUID_CHECK_RET(expr, fmt) \
4374	do { \
4375	if (!(expr)) \
4376	{ \
4377	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
4378	if (fStrictCpuIdChecks) \
4379	{ \
4380	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4381	RTStrFree(pszMsg); \
4382	return rcCpuid; \
4383	} \
4384	LogRel(("CPUM: %s\n", pszMsg)); \
4385	RTStrFree(pszMsg); \
4386	} \
4387	} while (0)
4388	#define CPUID_CHECK_WRN(expr, fmt) \
4389	do { \
4390	if (!(expr)) \
4391	LogRel(fmt); \
4392	} while (0)
4393
4394	/* For comparing two values and bitch if they differs. */
4395	#define CPUID_CHECK2_RET(what, host, saved) \
4396	do { \
4397	if ((host) != (saved)) \
4398	{ \
4399	if (fStrictCpuIdChecks) \
4400	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4401	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
4402	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4403	} \
4404	} while (0)
4405	#define CPUID_CHECK2_WRN(what, host, saved) \
4406	do { \
4407	if ((host) != (saved)) \
4408	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4409	} while (0)
4410
4411	/* For checking raw cpu features (raw mode). */
4412	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
4413	do { \
4414	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4415	{ \
4416	if (fStrictCpuIdChecks) \
4417	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4418	N_(#bit " mismatch: host=%d saved=%d"), \
4419	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
4420	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4421	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4422	} \
4423	} while (0)
4424	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
4425	do { \
4426	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4427	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4428	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4429	} while (0)
4430	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
4431
4432	/* For checking guest features. */
4433	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
4434	do { \
4435	if ( (aGuestCpuId##set [1].reg & bit) \
4436	&& !(aHostRaw##set [1].reg & bit) \
4437	&& !(aHostOverride##set [1].reg & bit) \
4438	) \
4439	{ \
4440	if (fStrictCpuIdChecks) \
4441	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4442	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4443	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4444	} \
4445	} while (0)
4446	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
4447	do { \
4448	if ( (aGuestCpuId##set [1].reg & bit) \
4449	&& !(aHostRaw##set [1].reg & bit) \
4450	&& !(aHostOverride##set [1].reg & bit) \
4451	) \
4452	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4453	} while (0)
4454	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
4455	do { \
4456	if ( (aGuestCpuId##set [1].reg & bit) \
4457	&& !(aHostRaw##set [1].reg & bit) \
4458	&& !(aHostOverride##set [1].reg & bit) \
4459	) \
4460	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4461	} while (0)
4462	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
4463
4464	/* For checking guest features if AMD guest CPU. */
4465	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
4466	do { \
4467	if ( (aGuestCpuId##set [1].reg & bit) \
4468	&& fGuestAmd \
4469	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4470	&& !(aHostOverride##set [1].reg & bit) \
4471	) \
4472	{ \
4473	if (fStrictCpuIdChecks) \
4474	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4475	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4476	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4477	} \
4478	} while (0)
4479	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
4480	do { \
4481	if ( (aGuestCpuId##set [1].reg & bit) \
4482	&& fGuestAmd \
4483	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4484	&& !(aHostOverride##set [1].reg & bit) \
4485	) \
4486	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4487	} while (0)
4488	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
4489	do { \
4490	if ( (aGuestCpuId##set [1].reg & bit) \
4491	&& fGuestAmd \
4492	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4493	&& !(aHostOverride##set [1].reg & bit) \
4494	) \
4495	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4496	} while (0)
4497	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
4498
4499	/* For checking AMD features which have a corresponding bit in the standard
4500	range. (Intel defines very few bits in the extended feature sets.) */
4501	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
4502	do { \
4503	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4504	&& !(fHostAmd \
4505	? aHostRawExt[1].reg & (ExtBit) \
4506	: aHostRawStd[1].reg & (StdBit)) \
4507	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4508	) \
4509	{ \
4510	if (fStrictCpuIdChecks) \
4511	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4512	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
4513	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4514	} \
4515	} while (0)
4516	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
4517	do { \
4518	if ( (aGuestCpuId[1].reg & (ExtBit)) \
4519	&& !(fHostAmd \
4520	? aHostRawExt[1].reg & (ExtBit) \
4521	: aHostRawStd[1].reg & (StdBit)) \
4522	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4523	) \
4524	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4525	} while (0)
4526	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
4527	do { \
4528	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4529	&& !(fHostAmd \
4530	? aHostRawExt[1].reg & (ExtBit) \
4531	: aHostRawStd[1].reg & (StdBit)) \
4532	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4533	) \
4534	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4535	} while (0)
4536	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
4537
4538	/*
4539	* For raw-mode we'll require that the CPUs are very similar since we don't
4540	* intercept CPUID instructions for user mode applications.
4541	*/
4542	if (!HMIsEnabled(pVM))
4543	{
4544	/* CPUID(0) */
4545	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
4546	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
4547	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
4548	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
4549	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
4550	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
4551	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
4552	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
4553	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
4554
4555	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
4556
4557	/* CPUID(1).eax */
4558	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
4559	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
4560	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
4561
4562	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
4563	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
4564	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
4565
4566	/* CPUID(1).ecx */
4567	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
4568	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
4569	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
4570	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4571	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
4572	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
4573	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
4574	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
4575	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
4576	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
4577	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
4578	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
4579	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
4580	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
4581	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
4582	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
4583	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
4584	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4585	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
4586	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
4587	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
4588	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4589	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
4590	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
4591	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4592	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
4593	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
4594	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4595	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
4596	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4597	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4598	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
4599
4600	/* CPUID(1).edx */
4601	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4602	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4603	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
4604	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4605	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
4606	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
4607	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4608	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4609	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
4610	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4611	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
4612	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4613	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4614	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4615	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4616	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
4617	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4618	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4619	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4620	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
4621	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
4622	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
4623	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
4624	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
4625	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
4626	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
4627	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
4628	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
4629	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
4630	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
4631	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
4632	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
4633
4634	/* CPUID(2) - config, mostly about caches. ignore. */
4635	/* CPUID(3) - processor serial number. ignore. */
4636	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
4637	/* CPUID(5) - mwait/monitor config. ignore. */
4638	/* CPUID(6) - power management. ignore. */
4639	/* CPUID(7) - ???. ignore. */
4640	/* CPUID(8) - ???. ignore. */
4641	/* CPUID(9) - DCA. ignore for now. */
4642	/* CPUID(a) - PeMo info. ignore for now. */
4643	/* CPUID(b) - topology info - takes ECX as input. ignore. */
4644
4645	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
4646	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
4647	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
4648	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
4649	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
4650	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
4651	{
4652	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
4653	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
4654	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
4655	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
4656	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
4657	}
4658
4659	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
4660	Note! Intel have/is marking many of the fields here as reserved. We
4661	will verify them as if it's an AMD CPU. */
4662	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
4663	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
4664	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
4665	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
4666	{
4667	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
4668	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
4669	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
4670	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
4671	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
4672	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
4673	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
4674
4675	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
4676	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
4677	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
4678	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
4679	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
4680	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
4681
4682	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
4683	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
4684	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
4685	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
4686
4687	/* CPUID(0x80000001).ecx */
4688	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
4689	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
4690	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
4691	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
4692	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
4693	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
4694	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
4695	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
4696	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
4697	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
4698	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
4699	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
4700	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
4701	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
4702	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4703	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4704	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4705	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4706	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4707	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4708	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4709	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4710	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4711	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4712	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4713	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4714	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4715	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4716	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4717	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4718	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4719	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4720
4721	/* CPUID(0x80000001).edx */
4722	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
4723	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
4724	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
4725	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
4726	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
4727	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
4728	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
4729	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
4730	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
4731	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
4732	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4733	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
4734	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
4735	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
4736	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
4737	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
4738	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
4739	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
4740	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4741	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4742	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4743	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
4744	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4745	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
4746	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
4747	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4748	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4749	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4750	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
4751	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4752	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4753	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4754
4755	/** @todo verify the rest as well. */
4756	}
4757	}
4758
4759
4760
4761	/*
4762	* Verify that we can support the features already exposed to the guest on
4763	* this host.
4764	*
4765	* Most of the features we're emulating requires intercepting instruction
4766	* and doing it the slow way, so there is no need to warn when they aren't
4767	* present in the host CPU. Thus we use IGN instead of EMU on these.
4768	*
4769	* Trailing comments:
4770	* "EMU" - Possible to emulate, could be lots of work and very slow.
4771	* "EMU?" - Can this be emulated?
4772	*/
4773	CPUMCPUID aGuestCpuIdStd[2];
4774	RT_ZERO(aGuestCpuIdStd);
4775	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
4776
4777	/* CPUID(1).ecx */
4778	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
4779	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
4780	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
4781	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4782	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
4783	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
4784	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
4785	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
4786	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
4787	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
4788	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
4789	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
4790	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
4791	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
4792	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
4793	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
4794	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
4795	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4796	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
4797	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
4798	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
4799	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4800	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
4801	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
4802	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4803	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
4804	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
4805	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4806	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
4807	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4808	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4809	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
4810
4811	/* CPUID(1).edx */
4812	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4813	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4814	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
4815	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4816	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4817	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4818	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4819	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4820	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4821	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4822	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
4823	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4824	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4825	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4826	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4827	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4828	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4829	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4830	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4831	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
4832	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
4833	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
4834	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
4835	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4836	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4837	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
4838	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
4839	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
4840	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
4841	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
4842	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
4843	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
4844
4845	/* CPUID(0x80000000). */
4846	CPUMCPUID aGuestCpuIdExt[2];
4847	RT_ZERO(aGuestCpuIdExt);
4848	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
4849	{
4850	/** @todo deal with no 0x80000001 on the host. */
4851	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
4852	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
4853
4854	/* CPUID(0x80000001).ecx */
4855	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
4856	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
4857	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
4858	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
4859	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
4860	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
4861	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
4862	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
4863	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
4864	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
4865	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
4866	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
4867	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
4868	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
4869	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4870	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4871	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4872	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4873	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4874	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4875	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4876	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4877	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4878	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4879	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4880	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4881	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4882	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4883	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4884	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4885	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4886	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4887
4888	/* CPUID(0x80000001).edx */
4889	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
4890	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
4891	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
4892	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
4893	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4894	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4895	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
4896	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
4897	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4898	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
4899	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4900	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
4901	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
4902	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
4903	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
4904	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4905	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
4906	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
4907	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4908	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4909	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4910	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
4911	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4912	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4913	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4914	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4915	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4916	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4917	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
4918	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4919	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4920	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4921	}
4922
4923	/** @todo check leaf 7 */
4924
4925	/* CPUID(d) - XCR0 stuff - takes ECX as input.
4926	* ECX=0: EAX - Valid bits in XCR0[31:0].
4927	* EBX - Maximum state size as per current XCR0 value.
4928	* ECX - Maximum state size for all supported features.
4929	* EDX - Valid bits in XCR0[63:32].
4930	* ECX=1: EAX - Various X-features.
4931	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
4932	* ECX - Valid bits in IA32_XSS[31:0].
4933	* EDX - Valid bits in IA32_XSS[63:32].
4934	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
4935	* if the bit invalid all four registers are set to zero.
4936	* EAX - The state size for this feature.
4937	* EBX - The state byte offset of this feature.
4938	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
4939	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
4940	*/
4941	uint64_t fGuestXcr0Mask = 0;
4942	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
4943	if ( pCurLeaf
4944	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
4945	&& ( pCurLeaf->uEax
4946	\|\| pCurLeaf->uEbx
4947	\|\| pCurLeaf->uEcx
4948	\|\| pCurLeaf->uEdx) )
4949	{
4950	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
4951	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
4952	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4953	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
4954	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
4955	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
4956	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4957	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
4958
4959	/* We don't support any additional features yet. */
4960	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
4961	if (pCurLeaf && pCurLeaf->uEax)
4962	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4963	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
4964	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
4965	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4966	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
4967	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
4968
4969
4970	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
4971	{
4972	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4973	if (pCurLeaf)
4974	{
4975	/* If advertised, the state component offset and size must match the one used by host. */
4976	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
4977	{
4978	CPUMCPUID RawHost;
4979	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
4980	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
4981	if ( RawHost.uEbx != pCurLeaf->uEbx
4982	\|\| RawHost.uEax != pCurLeaf->uEax)
4983	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4984	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
4985	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
4986	}
4987	}
4988	}
4989	}
4990	/* Clear leaf 0xd just in case we're loading an old state... */
4991	else if (pCurLeaf)
4992	{
4993	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
4994	{
4995	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4996	if (pCurLeaf)
4997	{
4998	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
4999	\|\| ( pCurLeaf->uEax == 0
5000	&& pCurLeaf->uEbx == 0
5001	&& pCurLeaf->uEcx == 0
5002	&& pCurLeaf->uEdx == 0),
5003	("uVersion=%#x; %#x %#x %#x %#x\n",
5004	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5005	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5006	}
5007	}
5008	}
5009
5010	/* Update the fXStateGuestMask value for the VM. */
5011	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5012	{
5013	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5014	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5015	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5016	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5017	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5018	}
5019
5020	#undef CPUID_CHECK_RET
5021	#undef CPUID_CHECK_WRN
5022	#undef CPUID_CHECK2_RET
5023	#undef CPUID_CHECK2_WRN
5024	#undef CPUID_RAW_FEATURE_RET
5025	#undef CPUID_RAW_FEATURE_WRN
5026	#undef CPUID_RAW_FEATURE_IGN
5027	#undef CPUID_GST_FEATURE_RET
5028	#undef CPUID_GST_FEATURE_WRN
5029	#undef CPUID_GST_FEATURE_EMU
5030	#undef CPUID_GST_FEATURE_IGN
5031	#undef CPUID_GST_FEATURE2_RET
5032	#undef CPUID_GST_FEATURE2_WRN
5033	#undef CPUID_GST_FEATURE2_EMU
5034	#undef CPUID_GST_FEATURE2_IGN
5035	#undef CPUID_GST_AMD_FEATURE_RET
5036	#undef CPUID_GST_AMD_FEATURE_WRN
5037	#undef CPUID_GST_AMD_FEATURE_EMU
5038	#undef CPUID_GST_AMD_FEATURE_IGN
5039
5040	/*
5041	* We're good, commit the CPU ID leaves.
5042	*/
5043	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5044	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5045	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5046	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
5047	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5048	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
5049	AssertLogRelRCReturn(rc, rc);
5050
5051	return VINF_SUCCESS;
5052	}
5053
5054
5055	/**
5056	* Loads the CPU ID leaves saved by pass 0.
5057	*
5058	* @returns VBox status code.
5059	* @param pVM Pointer to the VM.
5060	* @param pSSM The saved state handle.
5061	* @param uVersion The format version.
5062	*/
5063	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5064	{
5065	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5066
5067	/*
5068	* Load the CPUID leaves array first and call worker to do the rest, just so
5069	* we can free the memory when we need to without ending up in column 1000.
5070	*/
5071	PCPUMCPUIDLEAF paLeaves;
5072	uint32_t cLeaves;
5073	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5074	AssertRC(rc);
5075	if (RT_SUCCESS(rc))
5076	{
5077	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
5078	RTMemFree(paLeaves);
5079	}
5080	return rc;
5081	}
5082
5083
5084
5085	/**
5086	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5087	*
5088	* @returns VBox status code.
5089	* @param pVM Pointer to the VM.
5090	* @param pSSM The saved state handle.
5091	* @param uVersion The format version.
5092	*/
5093	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5094	{
5095	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5096
5097	/*
5098	* Restore the CPUID leaves.
5099	*
5100	* Note that we support restoring less than the current amount of standard
5101	* leaves because we've been allowed more is newer version of VBox.
5102	*/
5103	uint32_t cElements;
5104	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5105	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5106	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5107	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5108
5109	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5110	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5111	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5112	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5113
5114	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5115	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5116	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5117	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5118
5119	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5120
5121	/*
5122	* Check that the basic cpuid id information is unchanged.
5123	*/
5124	/** @todo we should check the 64 bits capabilities too! */
5125	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5126	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5127	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5128	uint32_t au32CpuIdSaved[8];
5129	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5130	if (RT_SUCCESS(rc))
5131	{
5132	/* Ignore CPU stepping. */
5133	au32CpuId[4] &= 0xfffffff0;
5134	au32CpuIdSaved[4] &= 0xfffffff0;
5135
5136	/* Ignore APIC ID (AMD specs). */
5137	au32CpuId[5] &= ~0xff000000;
5138	au32CpuIdSaved[5] &= ~0xff000000;
5139
5140	/* Ignore the number of Logical CPUs (AMD specs). */
5141	au32CpuId[5] &= ~0x00ff0000;
5142	au32CpuIdSaved[5] &= ~0x00ff0000;
5143
5144	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5145	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5146	\| X86_CPUID_FEATURE_ECX_VMX
5147	\| X86_CPUID_FEATURE_ECX_SMX
5148	\| X86_CPUID_FEATURE_ECX_EST
5149	\| X86_CPUID_FEATURE_ECX_TM2
5150	\| X86_CPUID_FEATURE_ECX_CNTXID
5151	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5152	\| X86_CPUID_FEATURE_ECX_PDCM
5153	\| X86_CPUID_FEATURE_ECX_DCA
5154	\| X86_CPUID_FEATURE_ECX_X2APIC
5155	);
5156	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5157	\| X86_CPUID_FEATURE_ECX_VMX
5158	\| X86_CPUID_FEATURE_ECX_SMX
5159	\| X86_CPUID_FEATURE_ECX_EST
5160	\| X86_CPUID_FEATURE_ECX_TM2
5161	\| X86_CPUID_FEATURE_ECX_CNTXID
5162	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5163	\| X86_CPUID_FEATURE_ECX_PDCM
5164	\| X86_CPUID_FEATURE_ECX_DCA
5165	\| X86_CPUID_FEATURE_ECX_X2APIC
5166	);
5167
5168	/* Make sure we don't forget to update the masks when enabling
5169	* features in the future.
5170	*/
5171	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5172	( X86_CPUID_FEATURE_ECX_DTES64
5173	\| X86_CPUID_FEATURE_ECX_VMX
5174	\| X86_CPUID_FEATURE_ECX_SMX
5175	\| X86_CPUID_FEATURE_ECX_EST
5176	\| X86_CPUID_FEATURE_ECX_TM2
5177	\| X86_CPUID_FEATURE_ECX_CNTXID
5178	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5179	\| X86_CPUID_FEATURE_ECX_PDCM
5180	\| X86_CPUID_FEATURE_ECX_DCA
5181	\| X86_CPUID_FEATURE_ECX_X2APIC
5182	)));
5183	/* do the compare */
5184	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5185	{
5186	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5187	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5188	"Saved=%.*Rhxs\n"
5189	"Real =%.*Rhxs\n",
5190	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5191	sizeof(au32CpuId), au32CpuId));
5192	else
5193	{
5194	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5195	"Saved=%.*Rhxs\n"
5196	"Real =%.*Rhxs\n",
5197	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5198	sizeof(au32CpuId), au32CpuId));
5199	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5200	}
5201	}
5202	}
5203
5204	return rc;
5205	}
5206
5207
5208
5209	/*
5210	*
5211	*
5212	* CPUID Info Handler.
5213	* CPUID Info Handler.
5214	* CPUID Info Handler.
5215	*
5216	*
5217	*/
5218
5219
5220
5221	/**
5222	* Get L1 cache / TLS associativity.
5223	*/
5224	static const char getCacheAss(unsigned u, char pszBuf)
5225	{
5226	if (u == 0)
5227	return "res0 ";
5228	if (u == 1)
5229	return "direct";
5230	if (u == 255)
5231	return "fully";
5232	if (u >= 256)
5233	return "???";
5234
5235	RTStrPrintf(pszBuf, 16, "%d way", u);
5236	return pszBuf;
5237	}
5238
5239
5240	/**
5241	* Get L2 cache associativity.
5242	*/
5243	const char *getL2CacheAss(unsigned u)
5244	{
5245	switch (u)
5246	{
5247	case 0: return "off ";
5248	case 1: return "direct";
5249	case 2: return "2 way ";
5250	case 3: return "res3 ";
5251	case 4: return "4 way ";
5252	case 5: return "res5 ";
5253	case 6: return "8 way ";
5254	case 7: return "res7 ";
5255	case 8: return "16 way";
5256	case 9: return "res9 ";
5257	case 10: return "res10 ";
5258	case 11: return "res11 ";
5259	case 12: return "res12 ";
5260	case 13: return "res13 ";
5261	case 14: return "res14 ";
5262	case 15: return "fully ";
5263	default: return "????";
5264	}
5265	}
5266
5267
5268	/** CPUID(1).EDX field descriptions. */
5269	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
5270	{
5271	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5272	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5273	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5274	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5275	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5276	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
5277	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5278	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5279	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5280	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5281	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
5282	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5283	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5284	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5285	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5286	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5287	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5288	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
5289	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
5290	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
5291	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
5292	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5293	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
5294	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
5295	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
5296	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
5297	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
5298	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
5299	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
5300	DBGFREGSUBFIELD_TERMINATOR()
5301	};
5302
5303	/** CPUID(1).ECX field descriptions. */
5304	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
5305	{
5306	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
5307	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
5308	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
5309	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
5310	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
5311	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
5312	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
5313	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
5314	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
5315	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
5316	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
5317	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
5318	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
5319	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
5320	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
5321	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
5322	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
5323	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
5324	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
5325	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
5326	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
5327	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
5328	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
5329	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
5330	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
5331	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
5332	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
5333	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
5334	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
5335	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
5336	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
5337	DBGFREGSUBFIELD_TERMINATOR()
5338	};
5339
5340	/** CPUID(7,0).EBX field descriptions. */
5341	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
5342	{
5343	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
5344	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
5345	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
5346	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
5347	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
5348	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
5349	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
5350	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
5351	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
5352	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
5353	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
5354	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
5355	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
5356	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
5357	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
5358	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
5359	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
5360	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
5361	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
5362	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
5363	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
5364	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
5365	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
5366	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
5367	DBGFREGSUBFIELD_TERMINATOR()
5368	};
5369
5370	/** CPUID(7,0).ECX field descriptions. */
5371	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
5372	{
5373	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
5374	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
5375	DBGFREGSUBFIELD_RO("OSPKU\0" "CR4.PKU mirror", 4, 1, 0),
5376	DBGFREGSUBFIELD_TERMINATOR()
5377	};
5378
5379
5380	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
5381	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
5382	{
5383	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
5384	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
5385	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
5386	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
5387	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
5388	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
5389	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
5390	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
5391	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
5392	DBGFREGSUBFIELD_TERMINATOR()
5393	};
5394
5395	/** CPUID(13,1).EAX field descriptions. */
5396	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
5397	{
5398	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
5399	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
5400	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
5401	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
5402	DBGFREGSUBFIELD_TERMINATOR()
5403	};
5404
5405
5406	/** CPUID(0x80000001,0).EDX field descriptions. */
5407	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
5408	{
5409	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5410	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5411	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5412	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5413	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5414	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
5415	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5416	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5417	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5418	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5419	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
5420	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5421	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5422	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5423	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5424	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5425	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5426	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
5427	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
5428	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5429	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
5430	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
5431	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
5432	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
5433	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
5434	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
5435	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
5436	DBGFREGSUBFIELD_TERMINATOR()
5437	};
5438
5439	/** CPUID(0x80000001,0).ECX field descriptions. */
5440	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
5441	{
5442	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
5443	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
5444	DBGFREGSUBFIELD_RO("SVM\0" "AMD VM extensions", 2, 1, 0),
5445	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
5446	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
5447	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
5448	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
5449	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
5450	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
5451	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
5452	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
5453	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
5454	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
5455	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
5456	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
5457	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
5458	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
5459	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
5460	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
5461	DBGFREGSUBFIELD_TERMINATOR()
5462	};
5463
5464
5465	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
5466	const char *pszLeadIn, uint32_t cchWidth)
5467	{
5468	if (pszLeadIn)
5469	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5470
5471	for (uint32_t iBit = 0; iBit < 32; iBit++)
5472	if (RT_BIT_32(iBit) & uVal)
5473	{
5474	while ( pDesc->pszName != NULL
5475	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5476	pDesc++;
5477	if ( pDesc->pszName != NULL
5478	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5479	{
5480	if (pDesc->cBits == 1)
5481	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5482	else
5483	{
5484	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
5485	if (pDesc->cBits < 32)
5486	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5487	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
5488	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5489	}
5490	}
5491	else
5492	pHlp->pfnPrintf(pHlp, " %u", iBit);
5493	}
5494	if (pszLeadIn)
5495	pHlp->pfnPrintf(pHlp, "\n");
5496	}
5497
5498
5499	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5500	const char *pszLeadIn, uint32_t cchWidth)
5501	{
5502	if (pszLeadIn)
5503	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5504
5505	for (uint32_t iBit = 0; iBit < 64; iBit++)
5506	if (RT_BIT_64(iBit) & uVal)
5507	{
5508	while ( pDesc->pszName != NULL
5509	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5510	pDesc++;
5511	if ( pDesc->pszName != NULL
5512	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5513	{
5514	if (pDesc->cBits == 1)
5515	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5516	else
5517	{
5518	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
5519	if (pDesc->cBits < 64)
5520	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
5521	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
5522	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5523	}
5524	}
5525	else
5526	pHlp->pfnPrintf(pHlp, " %u", iBit);
5527	}
5528	if (pszLeadIn)
5529	pHlp->pfnPrintf(pHlp, "\n");
5530	}
5531
5532
5533	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5534	const char *pszLeadIn, uint32_t cchWidth)
5535	{
5536	if (!uVal)
5537	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5538	else
5539	{
5540	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5541	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
5542	pHlp->pfnPrintf(pHlp, " )\n");
5543	}
5544	}
5545
5546
5547	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
5548	uint32_t cchWidth)
5549	{
5550	uint32_t uCombined = uVal1 \| uVal2;
5551	for (uint32_t iBit = 0; iBit < 32; iBit++)
5552	if ( (RT_BIT_32(iBit) & uCombined)
5553	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
5554	{
5555	while ( pDesc->pszName != NULL
5556	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5557	pDesc++;
5558
5559	if ( pDesc->pszName != NULL
5560	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5561	{
5562	size_t cchMnemonic = strlen(pDesc->pszName);
5563	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
5564	size_t cchDesc = strlen(pszDesc);
5565	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
5566	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
5567	if (pDesc->cBits < 32)
5568	{
5569	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5570	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5571	}
5572
5573	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
5574	pDesc->pszName, pszDesc,
5575	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
5576	uFieldValue1, uFieldValue2);
5577
5578	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
5579	pDesc++;
5580	}
5581	else
5582	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
5583	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
5584	}
5585	}
5586
5587
5588	/**
5589	* Produces a detailed summary of standard leaf 0x00000001.
5590	*
5591	* @param pHlp The info helper functions.
5592	* @param paLeaves The CPUID leaves array.
5593	* @param cLeaves The number of leaves in the array.
5594	* @param pCurLeaf The 0x00000001 leaf.
5595	* @param fVerbose Whether to be very verbose or not.
5596	* @param fIntel Set if intel CPU.
5597	*/
5598	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5599	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
5600	{
5601	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
5602	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
5603	uint32_t uEAX = pCurLeaf->uEax;
5604	uint32_t uEBX = pCurLeaf->uEbx;
5605
5606	pHlp->pfnPrintf(pHlp,
5607	"%36s %2d \tExtended: %d \tEffective: %d\n"
5608	"%36s %2d \tExtended: %d \tEffective: %d\n"
5609	"%36s %d\n"
5610	"%36s %d (%s)\n"
5611	"%36s %#04x\n"
5612	"%36s %d\n"
5613	"%36s %d\n"
5614	"%36s %#04x\n"
5615	,
5616	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
5617	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
5618	"Stepping:", ASMGetCpuStepping(uEAX),
5619	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
5620	"APIC ID:", (uEBX >> 24) & 0xff,
5621	"Logical CPUs:",(uEBX >> 16) & 0xff,
5622	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
5623	"Brand ID:", (uEBX >> 0) & 0xff);
5624	if (fVerbose)
5625	{
5626	CPUMCPUID Host;
5627	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5628	pHlp->pfnPrintf(pHlp, "Features\n");
5629	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5630	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
5631	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
5632	}
5633	else
5634	{
5635	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
5636	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
5637	}
5638	}
5639
5640
5641	/**
5642	* Produces a detailed summary of standard leaf 0x00000007.
5643	*
5644	* @param pHlp The info helper functions.
5645	* @param paLeaves The CPUID leaves array.
5646	* @param cLeaves The number of leaves in the array.
5647	* @param pCurLeaf The first 0x00000007 leaf.
5648	* @param fVerbose Whether to be very verbose or not.
5649	*/
5650	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5651	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5652	{
5653	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
5654	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
5655	for (;;)
5656	{
5657	CPUMCPUID Host;
5658	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5659
5660	switch (pCurLeaf->uSubLeaf)
5661	{
5662	case 0:
5663	if (fVerbose)
5664	{
5665	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5666	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
5667	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
5668	if (pCurLeaf->uEdx \|\| Host.uEdx)
5669	pHlp->pfnPrintf(pHlp, "%36 %#x (%#x)\n", "Ext Features EDX:", pCurLeaf->uEdx, Host.uEdx);
5670	}
5671	else
5672	{
5673	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
5674	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
5675	if (pCurLeaf->uEdx)
5676	pHlp->pfnPrintf(pHlp, "%36 %#x\n", "Ext Features EDX:", pCurLeaf->uEdx);
5677	}
5678	break;
5679
5680	default:
5681	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
5682	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
5683	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
5684	break;
5685
5686	}
5687
5688	/* advance. */
5689	pCurLeaf++;
5690	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5691	\|\| pCurLeaf->uLeaf != 0x7)
5692	break;
5693	}
5694	}
5695
5696
5697	/**
5698	* Produces a detailed summary of standard leaf 0x0000000d.
5699	*
5700	* @param pHlp The info helper functions.
5701	* @param paLeaves The CPUID leaves array.
5702	* @param cLeaves The number of leaves in the array.
5703	* @param pCurLeaf The first 0x00000007 leaf.
5704	* @param fVerbose Whether to be very verbose or not.
5705	*/
5706	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5707	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5708	{
5709	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
5710	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
5711	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5712	{
5713	CPUMCPUID Host;
5714	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5715
5716	switch (uSubLeaf)
5717	{
5718	case 0:
5719	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5720	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
5721	pCurLeaf->uEbx, pCurLeaf->uEcx);
5722	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
5723
5724	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5725	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
5726	"Valid XCR0 bits, guest:", 42);
5727	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
5728	"Valid XCR0 bits, host:", 42);
5729	break;
5730
5731	case 1:
5732	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5733	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
5734	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
5735
5736	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5737	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
5738	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
5739
5740	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5741	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
5742	" Valid IA32_XSS bits, guest:", 42);
5743	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
5744	" Valid IA32_XSS bits, host:", 42);
5745	break;
5746
5747	default:
5748	if ( pCurLeaf
5749	&& pCurLeaf->uSubLeaf == uSubLeaf
5750	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
5751	{
5752	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
5753	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5754	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
5755	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
5756	if (pCurLeaf->uEdx)
5757	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
5758	pHlp->pfnPrintf(pHlp, " --");
5759	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5760	pHlp->pfnPrintf(pHlp, "\n");
5761	}
5762	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
5763	{
5764	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
5765	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5766	if (Host.uEcx & ~RT_BIT_32(0))
5767	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
5768	if (Host.uEdx)
5769	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
5770	pHlp->pfnPrintf(pHlp, " --");
5771	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5772	pHlp->pfnPrintf(pHlp, "\n");
5773	}
5774	break;
5775
5776	}
5777
5778	/* advance. */
5779	if (pCurLeaf)
5780	{
5781	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5782	&& pCurLeaf->uSubLeaf <= uSubLeaf
5783	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
5784	pCurLeaf++;
5785	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5786	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
5787	pCurLeaf = NULL;
5788	}
5789	}
5790	}
5791
5792
5793	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5794	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
5795	{
5796	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5797	&& pCurLeaf->uLeaf <= uUpToLeaf)
5798	{
5799	pHlp->pfnPrintf(pHlp,
5800	" %s\n"
5801	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
5802	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5803	&& pCurLeaf->uLeaf <= uUpToLeaf)
5804	{
5805	CPUMCPUID Host;
5806	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5807	pHlp->pfnPrintf(pHlp,
5808	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5809	"Hst: %08x %08x %08x %08x\n",
5810	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5811	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5812	pCurLeaf++;
5813	}
5814	}
5815
5816	return pCurLeaf;
5817	}
5818
5819
5820	/**
5821	* Display the guest CpuId leaves.
5822	*
5823	* @param pVM Pointer to the VM.
5824	* @param pHlp The info helper functions.
5825	* @param pszArgs "terse", "default" or "verbose".
5826	*/
5827	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
5828	{
5829	/*
5830	* Parse the argument.
5831	*/
5832	unsigned iVerbosity = 1;
5833	if (pszArgs)
5834	{
5835	pszArgs = RTStrStripL(pszArgs);
5836	if (!strcmp(pszArgs, "terse"))
5837	iVerbosity--;
5838	else if (!strcmp(pszArgs, "verbose"))
5839	iVerbosity++;
5840	}
5841
5842	uint32_t uLeaf;
5843	CPUMCPUID Host;
5844	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
5845	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
5846	PCCPUMCPUIDLEAF pCurLeaf;
5847	PCCPUMCPUIDLEAF pNextLeaf;
5848	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
5849	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
5850	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
5851
5852	/*
5853	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
5854	*/
5855	uint32_t cHstMax = ASMCpuId_EAX(0);
5856	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
5857	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
5858	pHlp->pfnPrintf(pHlp,
5859	" Raw Standard CPUID Leaves\n"
5860	" Leaf/sub-leaf eax ebx ecx edx\n");
5861	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
5862	{
5863	uint32_t cMaxSubLeaves = 1;
5864	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
5865	cMaxSubLeaves = 16;
5866	else if (uLeaf == 0xd)
5867	cMaxSubLeaves = 128;
5868
5869	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5870	{
5871	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5872	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5873	&& pCurLeaf->uLeaf == uLeaf
5874	&& pCurLeaf->uSubLeaf == uSubLeaf)
5875	{
5876	pHlp->pfnPrintf(pHlp,
5877	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5878	"Hst: %08x %08x %08x %08x\n",
5879	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5880	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5881	pCurLeaf++;
5882	}
5883	else if ( uLeaf != 0xd
5884	\|\| uSubLeaf <= 1
5885	\|\| Host.uEbx != 0 )
5886	pHlp->pfnPrintf(pHlp,
5887	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5888	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5889
5890	/* Done? */
5891	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5892	\|\| pCurLeaf->uLeaf != uLeaf)
5893	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
5894	\|\| (uLeaf == 0x7 && Host.uEax == 0)
5895	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
5896	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
5897	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
5898	)
5899	)
5900	break;
5901	}
5902	}
5903	pNextLeaf = pCurLeaf;
5904
5905	/*
5906	* If verbose, decode it.
5907	*/
5908	if (iVerbosity && paLeaves[0].uLeaf == 0)
5909	pHlp->pfnPrintf(pHlp,
5910	"%36s %.04s%.04s%.04s\n"
5911	"%36s 0x00000000-%#010x\n"
5912	,
5913	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
5914	"Supports:", paLeaves[0].uEax);
5915
5916	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
5917	cpumR3CpuIdInfoStdLeaf1Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1, fIntel);
5918
5919	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
5920	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5921
5922	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
5923	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5924
5925	pCurLeaf = pNextLeaf;
5926
5927	/*
5928	* Hypervisor leaves.
5929	*
5930	* Unlike most of the other leaves reported, the guest hypervisor leaves
5931	* aren't a subset of the host CPUID bits.
5932	*/
5933	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
5934
5935	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5936	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
5937	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
5938	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
5939	cMax = RT_MAX(cHstMax, cGstMax);
5940	if (cMax >= UINT32_C(0x40000000))
5941	{
5942	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
5943
5944	/** @todo dump these in more detail. */
5945
5946	pCurLeaf = pNextLeaf;
5947	}
5948
5949
5950	/*
5951	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
5952	* Implemented after AMD specs.
5953	*/
5954	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
5955
5956	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5957	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
5958	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
5959	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
5960	cMax = RT_MAX(cHstMax, cGstMax);
5961	if (cMax >= UINT32_C(0x80000000))
5962	{
5963
5964	pHlp->pfnPrintf(pHlp,
5965	" Raw Extended CPUID Leaves\n"
5966	" Leaf/sub-leaf eax ebx ecx edx\n");
5967	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
5968	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
5969	{
5970	uint32_t cMaxSubLeaves = 1;
5971	if (uLeaf == UINT32_C(0x8000001d))
5972	cMaxSubLeaves = 16;
5973
5974	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5975	{
5976	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5977	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5978	&& pCurLeaf->uLeaf == uLeaf
5979	&& pCurLeaf->uSubLeaf == uSubLeaf)
5980	{
5981	pHlp->pfnPrintf(pHlp,
5982	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5983	"Hst: %08x %08x %08x %08x\n",
5984	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5985	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5986	pCurLeaf++;
5987	}
5988	else if ( uLeaf != 0xd
5989	\|\| uSubLeaf <= 1
5990	\|\| Host.uEbx != 0 )
5991	pHlp->pfnPrintf(pHlp,
5992	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5993	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5994
5995	/* Done? */
5996	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5997	\|\| pCurLeaf->uLeaf != uLeaf)
5998	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
5999	break;
6000	}
6001	}
6002	pNextLeaf = pCurLeaf;
6003
6004	/*
6005	* Understandable output
6006	*/
6007	if (iVerbosity)
6008	pHlp->pfnPrintf(pHlp,
6009	"Ext Name: %.4s%.4s%.4s\n"
6010	"Ext Supports: 0x80000000-%#010x\n",
6011	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6012
6013	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6014	if (iVerbosity && pCurLeaf)
6015	{
6016	uint32_t uEAX = pCurLeaf->uEax;
6017	pHlp->pfnPrintf(pHlp,
6018	"Family: %d \tExtended: %d \tEffective: %d\n"
6019	"Model: %d \tExtended: %d \tEffective: %d\n"
6020	"Stepping: %d\n"
6021	"Brand ID: %#05x\n",
6022	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6023	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6024	ASMGetCpuStepping(uEAX),
6025	pCurLeaf->uEbx & 0xfff);
6026
6027	if (iVerbosity == 1)
6028	{
6029	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6030	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6031	}
6032	else
6033	{
6034	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6035	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6036	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6037	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6038	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6039	}
6040	}
6041
6042	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6043	{
6044	char szString[443+1] = {0};
6045	uint32_t pu32 = (uint32_t )szString;
6046	*pu32++ = pCurLeaf->uEax;
6047	*pu32++ = pCurLeaf->uEbx;
6048	*pu32++ = pCurLeaf->uEcx;
6049	*pu32++ = pCurLeaf->uEdx;
6050	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6051	if (pCurLeaf)
6052	{
6053	*pu32++ = pCurLeaf->uEax;
6054	*pu32++ = pCurLeaf->uEbx;
6055	*pu32++ = pCurLeaf->uEcx;
6056	*pu32++ = pCurLeaf->uEdx;
6057	}
6058	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6059	if (pCurLeaf)
6060	{
6061	*pu32++ = pCurLeaf->uEax;
6062	*pu32++ = pCurLeaf->uEbx;
6063	*pu32++ = pCurLeaf->uEcx;
6064	*pu32++ = pCurLeaf->uEdx;
6065	}
6066	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6067	}
6068
6069	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6070	{
6071	uint32_t uEAX = pCurLeaf->uEax;
6072	uint32_t uEBX = pCurLeaf->uEbx;
6073	uint32_t uECX = pCurLeaf->uEcx;
6074	uint32_t uEDX = pCurLeaf->uEdx;
6075	char sz1[32];
6076	char sz2[32];
6077
6078	pHlp->pfnPrintf(pHlp,
6079	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6080	"TLB 2/4M Data: %s %3d entries\n",
6081	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6082	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6083	pHlp->pfnPrintf(pHlp,
6084	"TLB 4K Instr/Uni: %s %3d entries\n"
6085	"TLB 4K Data: %s %3d entries\n",
6086	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6087	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6088	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6089	"L1 Instr Cache Lines Per Tag: %d\n"
6090	"L1 Instr Cache Associativity: %s\n"
6091	"L1 Instr Cache Size: %d KB\n",
6092	(uEDX >> 0) & 0xff,
6093	(uEDX >> 8) & 0xff,
6094	getCacheAss((uEDX >> 16) & 0xff, sz1),
6095	(uEDX >> 24) & 0xff);
6096	pHlp->pfnPrintf(pHlp,
6097	"L1 Data Cache Line Size: %d bytes\n"
6098	"L1 Data Cache Lines Per Tag: %d\n"
6099	"L1 Data Cache Associativity: %s\n"
6100	"L1 Data Cache Size: %d KB\n",
6101	(uECX >> 0) & 0xff,
6102	(uECX >> 8) & 0xff,
6103	getCacheAss((uECX >> 16) & 0xff, sz1),
6104	(uECX >> 24) & 0xff);
6105	}
6106
6107	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6108	{
6109	uint32_t uEAX = pCurLeaf->uEax;
6110	uint32_t uEBX = pCurLeaf->uEbx;
6111	uint32_t uEDX = pCurLeaf->uEdx;
6112
6113	pHlp->pfnPrintf(pHlp,
6114	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6115	"L2 TLB 2/4M Data: %s %4d entries\n",
6116	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6117	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6118	pHlp->pfnPrintf(pHlp,
6119	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6120	"L2 TLB 4K Data: %s %4d entries\n",
6121	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6122	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6123	pHlp->pfnPrintf(pHlp,
6124	"L2 Cache Line Size: %d bytes\n"
6125	"L2 Cache Lines Per Tag: %d\n"
6126	"L2 Cache Associativity: %s\n"
6127	"L2 Cache Size: %d KB\n",
6128	(uEDX >> 0) & 0xff,
6129	(uEDX >> 8) & 0xf,
6130	getL2CacheAss((uEDX >> 12) & 0xf),
6131	(uEDX >> 16) & 0xffff);
6132	}
6133
6134	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
6135	{
6136	uint32_t uEDX = pCurLeaf->uEdx;
6137
6138	pHlp->pfnPrintf(pHlp, "APM Features: ");
6139	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
6140	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
6141	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
6142	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
6143	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
6144	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
6145	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " MC");
6146	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " HWPSTATE");
6147	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TscInvariant");
6148	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " CPB");
6149	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " EffFreqRO");
6150	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PFI");
6151	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PA");
6152	for (unsigned iBit = 13; iBit < 32; iBit++)
6153	if (uEDX & RT_BIT(iBit))
6154	pHlp->pfnPrintf(pHlp, " %d", iBit);
6155	pHlp->pfnPrintf(pHlp, "\n");
6156
6157	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6158	pHlp->pfnPrintf(pHlp, "Host Invariant-TSC support: %RTbool\n",
6159	cHstMax >= UINT32_C(0x80000007) && (Host.uEdx & RT_BIT(8)));
6160
6161	}
6162
6163	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0)) != NULL)
6164	{
6165	uint32_t uEAX = pCurLeaf->uEax;
6166	uint32_t uECX = pCurLeaf->uEcx;
6167
6168	pHlp->pfnPrintf(pHlp,
6169	"Physical Address Width: %d bits\n"
6170	"Virtual Address Width: %d bits\n"
6171	"Guest Physical Address Width: %d bits\n",
6172	(uEAX >> 0) & 0xff,
6173	(uEAX >> 8) & 0xff,
6174	(uEAX >> 16) & 0xff);
6175	pHlp->pfnPrintf(pHlp,
6176	"Physical Core Count: %d\n",
6177	(uECX >> 0) & 0xff);
6178	}
6179
6180	pCurLeaf = pNextLeaf;
6181	}
6182
6183
6184
6185	/*
6186	* Centaur.
6187	*/
6188	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
6189
6190	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6191	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
6192	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
6193	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
6194	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
6195	cMax = RT_MAX(cHstMax, cGstMax);
6196	if (cMax >= UINT32_C(0xc0000000))
6197	{
6198	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
6199
6200	/*
6201	* Understandable output
6202	*/
6203	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
6204	pHlp->pfnPrintf(pHlp,
6205	"Centaur Supports: 0xc0000000-%#010x\n",
6206	pCurLeaf->uEax);
6207
6208	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
6209	{
6210	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6211	uint32_t uEdxGst = pCurLeaf->uEdx;
6212	uint32_t uEdxHst = Host.uEdx;
6213
6214	if (iVerbosity == 1)
6215	{
6216	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
6217	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
6218	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
6219	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
6220	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
6221	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
6222	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
6223	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
6224	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
6225	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6226	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
6227	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
6228	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
6229	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
6230	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
6231	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
6232	for (unsigned iBit = 14; iBit < 32; iBit++)
6233	if (uEdxGst & RT_BIT(iBit))
6234	pHlp->pfnPrintf(pHlp, " %d", iBit);
6235	pHlp->pfnPrintf(pHlp, "\n");
6236	}
6237	else
6238	{
6239	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
6240	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
6241	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
6242	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
6243	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
6244	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
6245	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
6246	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
6247	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
6248	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6249	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
6250	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
6251	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
6252	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
6253	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
6254	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
6255	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
6256	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
6257	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
6258	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
6259	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
6260	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
6261	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
6262	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
6263	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
6264	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
6265	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
6266	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
6267	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
6268	for (unsigned iBit = 27; iBit < 32; iBit++)
6269	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
6270	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
6271	pHlp->pfnPrintf(pHlp, "\n");
6272	}
6273	}
6274
6275	pCurLeaf = pNextLeaf;
6276	}
6277
6278	/*
6279	* The remainder.
6280	*/
6281	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
6282	}
6283
6284
6285
6286
6287
6288	/*
6289	*
6290	*
6291	* PATM interfaces.
6292	* PATM interfaces.
6293	* PATM interfaces.
6294	*
6295	*
6296	*/
6297
6298
6299	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
6300	/** @name Patchmanager CPUID legacy table APIs
6301	* @{
6302	*/
6303
6304	/**
6305	* Gets a pointer to the default CPUID leaf.
6306	*
6307	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
6308	* @param pVM Pointer to the VM.
6309	* @remark Intended for PATM only.
6310	*/
6311	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
6312	{
6313	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
6314	}
6315
6316
6317	/**
6318	* Gets a number of standard CPUID leaves (PATM only).
6319	*
6320	* @returns Number of leaves.
6321	* @param pVM Pointer to the VM.
6322	* @remark Intended for PATM - legacy, don't use in new code.
6323	*/
6324	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
6325	{
6326	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
6327	}
6328
6329
6330	/**
6331	* Gets a number of extended CPUID leaves (PATM only).
6332	*
6333	* @returns Number of leaves.
6334	* @param pVM Pointer to the VM.
6335	* @remark Intended for PATM - legacy, don't use in new code.
6336	*/
6337	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
6338	{
6339	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
6340	}
6341
6342
6343	/**
6344	* Gets a number of centaur CPUID leaves.
6345	*
6346	* @returns Number of leaves.
6347	* @param pVM Pointer to the VM.
6348	* @remark Intended for PATM - legacy, don't use in new code.
6349	*/
6350	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
6351	{
6352	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
6353	}
6354
6355
6356	/**
6357	* Gets a pointer to the array of standard CPUID leaves.
6358	*
6359	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
6360	*
6361	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
6362	* @param pVM Pointer to the VM.
6363	* @remark Intended for PATM - legacy, don't use in new code.
6364	*/
6365	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
6366	{
6367	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
6368	}
6369
6370
6371	/**
6372	* Gets a pointer to the array of extended CPUID leaves.
6373	*
6374	* CPUMGetGuestCpuIdExtMax() give the size of the array.
6375	*
6376	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
6377	* @param pVM Pointer to the VM.
6378	* @remark Intended for PATM - legacy, don't use in new code.
6379	*/
6380	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
6381	{
6382	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
6383	}
6384
6385
6386	/**
6387	* Gets a pointer to the array of centaur CPUID leaves.
6388	*
6389	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
6390	*
6391	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
6392	* @param pVM Pointer to the VM.
6393	* @remark Intended for PATM - legacy, don't use in new code.
6394	*/
6395	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
6396	{
6397	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
6398	}
6399
6400	/** @} */
6401	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
6402
6403	#endif /* VBOX_IN_VMM */
6404

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 57334

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