CPUMR3CpuId.cpp@ 58120

Last change on this file since 58120 was 57373, checked in by vboxsync, 10 years ago
CPUMR3CpuId.cpp: Intel CPU march classification updates.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 294.8 KB

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1	/* $Id: CPUMR3CpuId.cpp 57373 2015-08-14 22:33:00Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/ssm.h>
27	#include "CPUMInternal.h"
28	#include <VBox/vmm/vm.h>
29	#include <VBox/vmm/mm.h>
30
31	#include <VBox/err.h>
32	#include <iprt/asm-amd64-x86.h>
33	#include <iprt/ctype.h>
34	#include <iprt/mem.h>
35	#include <iprt/string.h>
36
37
38	/*********************************************************************************************************************************
39	* Defined Constants And Macros *
40	*********************************************************************************************************************************/
41	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
42	#define CPUM_CPUID_MAX_LEAVES 2048
43	/* Max size we accept for the XSAVE area. */
44	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
45	/* Min size we accept for the XSAVE area. */
46	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
47
48
49	/*********************************************************************************************************************************
50	* Global Variables *
51	*********************************************************************************************************************************/
52	/**
53	* The intel pentium family.
54	*/
55	static const CPUMMICROARCH g_aenmIntelFamily06[] =
56	{
57	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
58	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
59	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
60	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
61	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
63	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
64	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
65	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
66	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
67	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
68	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
69	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
70	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
71	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
72	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
73	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
74	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
79	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
80	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
81	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
82	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
83	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
84	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
86	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
87	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
88	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
89	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
90	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
91	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
95	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
96	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
97	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
98	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
99	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
100	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
102	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
103	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
104	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
105	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
106	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
107	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
111	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
112	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
113	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
114	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
115	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
116	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
118	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
119	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
120	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
121	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
122	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
123	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
127	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
128	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
129	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
130	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
131	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
132	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
134	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
135	/* [78(0x4e)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed */
136	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / unconfirmed, Broadwell-E */
137	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
138	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
139	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed server cpu */
143	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
144	/* [87(0x57)] = */ kCpumMicroarch_Intel_Unknown,
145	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
146	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
147	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
148	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / unconfirmed */
150	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
151	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
152	/* [95(0x5f)] = */ kCpumMicroarch_Intel_Unknown,
153	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
154	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
155	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [99(0x64)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x65)] = */ kCpumMicroarch_Intel_Unknown,
159	/* [99(0x66)] = / kCpumMicroarch_Intel_Core7_Cannonlake, / unconfirmed */
160	};
161
162
163
164	/**
165	* Figures out the (sub-)micro architecture given a bit of CPUID info.
166	*
167	* @returns Micro architecture.
168	* @param enmVendor The CPU vendor .
169	* @param bFamily The CPU family.
170	* @param bModel The CPU model.
171	* @param bStepping The CPU stepping.
172	*/
173	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
174	uint8_t bModel, uint8_t bStepping)
175	{
176	if (enmVendor == CPUMCPUVENDOR_AMD)
177	{
178	switch (bFamily)
179	{
180	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
181	case 0x03: return kCpumMicroarch_AMD_Am386;
182	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
183	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
184	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
185	case 0x06:
186	switch (bModel)
187	{
188	case 0: return kCpumMicroarch_AMD_K7_Palomino;
189	case 1: return kCpumMicroarch_AMD_K7_Palomino;
190	case 2: return kCpumMicroarch_AMD_K7_Palomino;
191	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
192	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
193	case 6: return kCpumMicroarch_AMD_K7_Palomino;
194	case 7: return kCpumMicroarch_AMD_K7_Morgan;
195	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
196	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
197	}
198	return kCpumMicroarch_AMD_K7_Unknown;
199	case 0x0f:
200	/*
201	* This family is a friggin mess. Trying my best to make some
202	* sense out of it. Too much happened in the 0x0f family to
203	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
204	*
205	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
206	* cpu-world.com, and other places:
207	* - 130nm:
208	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
209	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
210	* - Newcastle: FC0/DH-CG (errum #180: FE0/DH-CG), FF0/DH-CG
211	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
212	* - Odessa: FC0/DH-CG (errum #180: FE0/DH-CG)
213	* - Paris: FF0/DH-CG, FC0/DH-CG (errum #180: FE0/DH-CG),
214	* - 90nm:
215	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
216	* - Oakville: 10FC0/DH-D0.
217	* - Georgetown: 10FC0/DH-D0.
218	* - Sonora: 10FC0/DH-D0.
219	* - Venus: 20F71/SH-E4
220	* - Troy: 20F51/SH-E4
221	* - Athens: 20F51/SH-E4
222	* - San Diego: 20F71/SH-E4.
223	* - Lancaster: 20F42/SH-E5
224	* - Newark: 20F42/SH-E5.
225	* - Albany: 20FC2/DH-E6.
226	* - Roma: 20FC2/DH-E6.
227	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
228	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
229	* - 90nm introducing Dual core:
230	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
231	* - Italy: 20F10/JH-E1, 20F12/JH-E6
232	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
233	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
234	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
235	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
236	* - Santa Ana: 40F32/JH-F2, /-F3
237	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
238	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
239	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
240	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
241	* - Keene: 40FC2/DH-F2.
242	* - Richmond: 40FC2/DH-F2
243	* - Taylor: 40F82/BH-F2
244	* - Trinidad: 40F82/BH-F2
245	*
246	* - 65nm:
247	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
248	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
249	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
250	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
251	* - Sherman: /-G1, 70FC2/DH-G2.
252	* - Huron: 70FF2/DH-G2.
253	*/
254	if (bModel < 0x10)
255	return kCpumMicroarch_AMD_K8_130nm;
256	if (bModel >= 0x60 && bModel < 0x80)
257	return kCpumMicroarch_AMD_K8_65nm;
258	if (bModel >= 0x40)
259	return kCpumMicroarch_AMD_K8_90nm_AMDV;
260	switch (bModel)
261	{
262	case 0x21:
263	case 0x23:
264	case 0x2b:
265	case 0x2f:
266	case 0x37:
267	case 0x3f:
268	return kCpumMicroarch_AMD_K8_90nm_DualCore;
269	}
270	return kCpumMicroarch_AMD_K8_90nm;
271	case 0x10:
272	return kCpumMicroarch_AMD_K10;
273	case 0x11:
274	return kCpumMicroarch_AMD_K10_Lion;
275	case 0x12:
276	return kCpumMicroarch_AMD_K10_Llano;
277	case 0x14:
278	return kCpumMicroarch_AMD_Bobcat;
279	case 0x15:
280	switch (bModel)
281	{
282	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
283	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
284	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
285	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
286	case 0x11: /* ?? */
287	case 0x12: /* ?? */
288	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
289	}
290	return kCpumMicroarch_AMD_15h_Unknown;
291	case 0x16:
292	return kCpumMicroarch_AMD_Jaguar;
293
294	}
295	return kCpumMicroarch_AMD_Unknown;
296	}
297
298	if (enmVendor == CPUMCPUVENDOR_INTEL)
299	{
300	switch (bFamily)
301	{
302	case 3:
303	return kCpumMicroarch_Intel_80386;
304	case 4:
305	return kCpumMicroarch_Intel_80486;
306	case 5:
307	return kCpumMicroarch_Intel_P5;
308	case 6:
309	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
310	return g_aenmIntelFamily06[bModel];
311	return kCpumMicroarch_Intel_Atom_Unknown;
312	case 15:
313	switch (bModel)
314	{
315	case 0: return kCpumMicroarch_Intel_NB_Willamette;
316	case 1: return kCpumMicroarch_Intel_NB_Willamette;
317	case 2: return kCpumMicroarch_Intel_NB_Northwood;
318	case 3: return kCpumMicroarch_Intel_NB_Prescott;
319	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
320	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
321	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
322	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
323	default: return kCpumMicroarch_Intel_NB_Unknown;
324	}
325	break;
326	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
327	case 1:
328	return kCpumMicroarch_Intel_8086;
329	case 2:
330	return kCpumMicroarch_Intel_80286;
331	}
332	return kCpumMicroarch_Intel_Unknown;
333	}
334
335	if (enmVendor == CPUMCPUVENDOR_VIA)
336	{
337	switch (bFamily)
338	{
339	case 5:
340	switch (bModel)
341	{
342	case 1: return kCpumMicroarch_Centaur_C6;
343	case 4: return kCpumMicroarch_Centaur_C6;
344	case 8: return kCpumMicroarch_Centaur_C2;
345	case 9: return kCpumMicroarch_Centaur_C3;
346	}
347	break;
348
349	case 6:
350	switch (bModel)
351	{
352	case 5: return kCpumMicroarch_VIA_C3_M2;
353	case 6: return kCpumMicroarch_VIA_C3_C5A;
354	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
355	case 8: return kCpumMicroarch_VIA_C3_C5N;
356	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
357	case 10: return kCpumMicroarch_VIA_C7_C5J;
358	case 15: return kCpumMicroarch_VIA_Isaiah;
359	}
360	break;
361	}
362	return kCpumMicroarch_VIA_Unknown;
363	}
364
365	if (enmVendor == CPUMCPUVENDOR_CYRIX)
366	{
367	switch (bFamily)
368	{
369	case 4:
370	switch (bModel)
371	{
372	case 9: return kCpumMicroarch_Cyrix_5x86;
373	}
374	break;
375
376	case 5:
377	switch (bModel)
378	{
379	case 2: return kCpumMicroarch_Cyrix_M1;
380	case 4: return kCpumMicroarch_Cyrix_MediaGX;
381	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
382	}
383	break;
384
385	case 6:
386	switch (bModel)
387	{
388	case 0: return kCpumMicroarch_Cyrix_M2;
389	}
390	break;
391
392	}
393	return kCpumMicroarch_Cyrix_Unknown;
394	}
395
396	return kCpumMicroarch_Unknown;
397	}
398
399
400	/**
401	* Translates a microarchitecture enum value to the corresponding string
402	* constant.
403	*
404	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
405	* NULL if the value is invalid.
406	*
407	* @param enmMicroarch The enum value to convert.
408	*/
409	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
410	{
411	switch (enmMicroarch)
412	{
413	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
414	CASE_RET_STR(kCpumMicroarch_Intel_8086);
415	CASE_RET_STR(kCpumMicroarch_Intel_80186);
416	CASE_RET_STR(kCpumMicroarch_Intel_80286);
417	CASE_RET_STR(kCpumMicroarch_Intel_80386);
418	CASE_RET_STR(kCpumMicroarch_Intel_80486);
419	CASE_RET_STR(kCpumMicroarch_Intel_P5);
420
421	CASE_RET_STR(kCpumMicroarch_Intel_P6);
422	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
423	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
424
425	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
426	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
427	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
428
429	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
430	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
431
432	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
433	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
434	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
435	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
436	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
437	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
438	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
439	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Cannonlake);
440
441	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
442	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
443	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
444	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
445	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
446	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
447	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
448
449	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
450	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
451	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
452	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
453	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
454	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
455	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
456
457	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
458
459	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
460	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
461	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
462	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
463	CASE_RET_STR(kCpumMicroarch_AMD_K5);
464	CASE_RET_STR(kCpumMicroarch_AMD_K6);
465
466	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
467	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
468	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
469	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
470	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
471	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
472	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
473
474	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
475	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
476	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
477	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
478	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
479
480	CASE_RET_STR(kCpumMicroarch_AMD_K10);
481	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
482	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
483	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
484	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
485
486	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
487	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
488	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
489	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
490	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
491
492	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
493
494	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
495
496	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
497	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
498	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
499	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
500	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
501	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
502	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
503	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
504	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
505	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
506	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
507	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
508	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
509
510	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
511	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
512	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
513	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
514	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
515	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
516
517	CASE_RET_STR(kCpumMicroarch_Unknown);
518
519	#undef CASE_RET_STR
520	case kCpumMicroarch_Invalid:
521	case kCpumMicroarch_Intel_End:
522	case kCpumMicroarch_Intel_Core7_End:
523	case kCpumMicroarch_Intel_Atom_End:
524	case kCpumMicroarch_Intel_P6_Core_Atom_End:
525	case kCpumMicroarch_Intel_NB_End:
526	case kCpumMicroarch_AMD_K7_End:
527	case kCpumMicroarch_AMD_K8_End:
528	case kCpumMicroarch_AMD_15h_End:
529	case kCpumMicroarch_AMD_16h_End:
530	case kCpumMicroarch_AMD_End:
531	case kCpumMicroarch_VIA_End:
532	case kCpumMicroarch_Cyrix_End:
533	case kCpumMicroarch_32BitHack:
534	break;
535	/* no default! */
536	}
537
538	return NULL;
539	}
540
541
542
543	/**
544	* Gets a matching leaf in the CPUID leaf array.
545	*
546	* @returns Pointer to the matching leaf, or NULL if not found.
547	* @param paLeaves The CPUID leaves to search. This is sorted.
548	* @param cLeaves The number of leaves in the array.
549	* @param uLeaf The leaf to locate.
550	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
551	*/
552	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
553	{
554	/* Lazy bird does linear lookup here since this is only used for the
555	occational CPUID overrides. */
556	for (uint32_t i = 0; i < cLeaves; i++)
557	if ( paLeaves[i].uLeaf == uLeaf
558	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
559	return &paLeaves[i];
560	return NULL;
561	}
562
563
564	/**
565	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
566	*
567	* @returns true if found, false it not.
568	* @param paLeaves The CPUID leaves to search. This is sorted.
569	* @param cLeaves The number of leaves in the array.
570	* @param uLeaf The leaf to locate.
571	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
572	* @param pLegacy The legacy output leaf.
573	*/
574	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
575	PCPUMCPUID pLegacy)
576	{
577	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
578	if (pLeaf)
579	{
580	pLegacy->uEax = pLeaf->uEax;
581	pLegacy->uEbx = pLeaf->uEbx;
582	pLegacy->uEcx = pLeaf->uEcx;
583	pLegacy->uEdx = pLeaf->uEdx;
584	return true;
585	}
586	return false;
587	}
588
589
590	/**
591	* Ensures that the CPUID leaf array can hold one more leaf.
592	*
593	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
594	* failure.
595	* @param pVM Pointer to the VM, used as the heap selector. Passing
596	* NULL uses the host-context heap, otherwise the VM's
597	* hyper heap is used.
598	* @param ppaLeaves Pointer to the variable holding the array pointer
599	* (input/output).
600	* @param cLeaves The current array size.
601	*
602	* @remarks This function will automatically update the R0 and RC pointers when
603	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
604	* be the corresponding VM's CPUID arrays (which is asserted).
605	*/
606	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
607	{
608	/*
609	* If pVM is not specified, we're on the regular heap and can waste a
610	* little space to speed things up.
611	*/
612	uint32_t cAllocated;
613	if (!pVM)
614	{
615	cAllocated = RT_ALIGN(cLeaves, 16);
616	if (cLeaves + 1 > cAllocated)
617	{
618	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
619	if (pvNew)
620	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
621	else
622	{
623	RTMemFree(*ppaLeaves);
624	*ppaLeaves = NULL;
625	}
626	}
627	}
628	/*
629	* Otherwise, we're on the hyper heap and are probably just inserting
630	* one or two leaves and should conserve space.
631	*/
632	else
633	{
634	#ifdef IN_VBOX_CPU_REPORT
635	AssertReleaseFailed();
636	#else
637	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
638	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
639
640	size_t cb = cLeaves * sizeof(**ppaLeaves);
641	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
642	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
643	if (RT_SUCCESS(rc))
644	{
645	/* Update the R0 and RC pointers. */
646	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
647	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
648	}
649	else
650	{
651	*ppaLeaves = NULL;
652	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
653	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
654	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
655	}
656	#endif
657	}
658	return *ppaLeaves;
659	}
660
661
662	/**
663	* Append a CPUID leaf or sub-leaf.
664	*
665	* ASSUMES linear insertion order, so we'll won't need to do any searching or
666	* replace anything. Use cpumR3CpuIdInsert() for those cases.
667	*
668	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
669	* the caller need do no more work.
670	* @param ppaLeaves Pointer to the the pointer to the array of sorted
671	* CPUID leaves and sub-leaves.
672	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
673	* @param uLeaf The leaf we're adding.
674	* @param uSubLeaf The sub-leaf number.
675	* @param fSubLeafMask The sub-leaf mask.
676	* @param uEax The EAX value.
677	* @param uEbx The EBX value.
678	* @param uEcx The ECX value.
679	* @param uEdx The EDX value.
680	* @param fFlags The flags.
681	*/
682	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
683	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
684	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
685	{
686	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
687	return VERR_NO_MEMORY;
688
689	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
690	Assert( *pcLeaves == 0
691	\|\| pNew[-1].uLeaf < uLeaf
692	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
693
694	pNew->uLeaf = uLeaf;
695	pNew->uSubLeaf = uSubLeaf;
696	pNew->fSubLeafMask = fSubLeafMask;
697	pNew->uEax = uEax;
698	pNew->uEbx = uEbx;
699	pNew->uEcx = uEcx;
700	pNew->uEdx = uEdx;
701	pNew->fFlags = fFlags;
702
703	*pcLeaves += 1;
704	return VINF_SUCCESS;
705	}
706
707
708	/**
709	* Checks that we've updated the CPUID leaves array correctly.
710	*
711	* This is a no-op in non-strict builds.
712	*
713	* @param paLeaves The leaves array.
714	* @param cLeaves The number of leaves.
715	*/
716	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
717	{
718	#ifdef VBOX_STRICT
719	for (uint32_t i = 1; i < cLeaves; i++)
720	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
721	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
722	else
723	{
724	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
725	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
726	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
727	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
728	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
729	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
730	}
731	#else
732	NOREF(paLeaves);
733	NOREF(cLeaves);
734	#endif
735	}
736
737
738	/**
739	* Inserts a CPU ID leaf, replacing any existing ones.
740	*
741	* When inserting a simple leaf where we already got a series of sub-leaves with
742	* the same leaf number (eax), the simple leaf will replace the whole series.
743	*
744	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
745	* host-context heap and has only been allocated/reallocated by the
746	* cpumR3CpuIdEnsureSpace function.
747	*
748	* @returns VBox status code.
749	* @param pVM Pointer to the VM, used as the heap selector.
750	* Passing NULL uses the host-context heap, otherwise
751	* the VM's hyper heap is used.
752	* @param ppaLeaves Pointer to the the pointer to the array of sorted
753	* CPUID leaves and sub-leaves. Must be NULL if using
754	* the hyper heap.
755	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must be
756	* NULL if using the hyper heap.
757	* @param pNewLeaf Pointer to the data of the new leaf we're about to
758	* insert.
759	*/
760	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
761	{
762	/*
763	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
764	*/
765	if (pVM)
766	{
767	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
768	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
769
770	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
771	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
772	}
773
774	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
775	uint32_t cLeaves = *pcLeaves;
776
777	/*
778	* Validate the new leaf a little.
779	*/
780	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
781	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
782	VERR_INVALID_FLAGS);
783	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
784	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
785	VERR_INVALID_PARAMETER);
786	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
787	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
788	VERR_INVALID_PARAMETER);
789	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
790	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
791	VERR_INVALID_PARAMETER);
792
793	/*
794	* Find insertion point. The lazy bird uses the same excuse as in
795	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
796	*/
797	uint32_t i;
798	if ( cLeaves > 0
799	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
800	{
801	/* Add at end. */
802	i = cLeaves;
803	}
804	else if ( cLeaves > 0
805	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
806	{
807	/* Either replacing the last leaf or dealing with sub-leaves. Spool
808	back to the first sub-leaf to pretend we did the linear search. */
809	i = cLeaves - 1;
810	while ( i > 0
811	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
812	i--;
813	}
814	else
815	{
816	/* Linear search from the start. */
817	i = 0;
818	while ( i < cLeaves
819	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
820	i++;
821	}
822	if ( i < cLeaves
823	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
824	{
825	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
826	{
827	/*
828	* The sub-leaf mask differs, replace all existing leaves with the
829	* same leaf number.
830	*/
831	uint32_t c = 1;
832	while ( i + c < cLeaves
833	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
834	c++;
835	if (c > 1 && i + c < cLeaves)
836	{
837	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
838	*pcLeaves = cLeaves -= c - 1;
839	}
840
841	paLeaves[i] = *pNewLeaf;
842	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
843	return VINF_SUCCESS;
844	}
845
846	/* Find sub-leaf insertion point. */
847	while ( i < cLeaves
848	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
849	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
850	i++;
851
852	/*
853	* If we've got an exactly matching leaf, replace it.
854	*/
855	if ( i < cLeaves
856	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
857	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
858	{
859	paLeaves[i] = *pNewLeaf;
860	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
861	return VINF_SUCCESS;
862	}
863	}
864
865	/*
866	* Adding a new leaf at 'i'.
867	*/
868	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
869	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
870	if (!paLeaves)
871	return VERR_NO_MEMORY;
872
873	if (i < cLeaves)
874	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
875	*pcLeaves += 1;
876	paLeaves[i] = *pNewLeaf;
877
878	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
879	return VINF_SUCCESS;
880	}
881
882
883	/**
884	* Removes a range of CPUID leaves.
885	*
886	* This will not reallocate the array.
887	*
888	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
889	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
890	* @param uFirst The first leaf.
891	* @param uLast The last leaf.
892	*/
893	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
894	{
895	uint32_t cLeaves = *pcLeaves;
896
897	Assert(uFirst <= uLast);
898
899	/*
900	* Find the first one.
901	*/
902	uint32_t iFirst = 0;
903	while ( iFirst < cLeaves
904	&& paLeaves[iFirst].uLeaf < uFirst)
905	iFirst++;
906
907	/*
908	* Find the end (last + 1).
909	*/
910	uint32_t iEnd = iFirst;
911	while ( iEnd < cLeaves
912	&& paLeaves[iEnd].uLeaf <= uLast)
913	iEnd++;
914
915	/*
916	* Adjust the array if anything needs removing.
917	*/
918	if (iFirst < iEnd)
919	{
920	if (iEnd < cLeaves)
921	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
922	*pcLeaves = cLeaves -= (iEnd - iFirst);
923	}
924
925	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
926	}
927
928
929
930	/**
931	* Checks if ECX make a difference when reading a given CPUID leaf.
932	*
933	* @returns @c true if it does, @c false if it doesn't.
934	* @param uLeaf The leaf we're reading.
935	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
936	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
937	* final sub-leaf (for leaf 0xb only).
938	*/
939	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
940	{
941	*pfFinalEcxUnchanged = false;
942
943	uint32_t auCur[4];
944	uint32_t auPrev[4];
945	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
946
947	/* Look for sub-leaves. */
948	uint32_t uSubLeaf = 1;
949	for (;;)
950	{
951	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
952	if (memcmp(auCur, auPrev, sizeof(auCur)))
953	break;
954
955	/* Advance / give up. */
956	uSubLeaf++;
957	if (uSubLeaf >= 64)
958	{
959	*pcSubLeaves = 1;
960	return false;
961	}
962	}
963
964	/* Count sub-leaves. */
965	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
966	uint32_t cRepeats = 0;
967	uSubLeaf = 0;
968	for (;;)
969	{
970	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
971
972	/* Figuring out when to stop isn't entirely straight forward as we need
973	to cover undocumented behavior up to a point and implementation shortcuts. */
974
975	/* 1. Look for more than 4 repeating value sets. */
976	if ( auCur[0] == auPrev[0]
977	&& auCur[1] == auPrev[1]
978	&& ( auCur[2] == auPrev[2]
979	\|\| ( auCur[2] == uSubLeaf
980	&& auPrev[2] == uSubLeaf - 1) )
981	&& auCur[3] == auPrev[3])
982	{
983	if ( uLeaf != 0xd
984	\|\| uSubLeaf >= 64
985	\|\| ( auCur[0] == 0
986	&& auCur[1] == 0
987	&& auCur[2] == 0
988	&& auCur[3] == 0
989	&& auPrev[2] == 0) )
990	cRepeats++;
991	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
992	break;
993	}
994	else
995	cRepeats = 0;
996
997	/* 2. Look for zero values. */
998	if ( auCur[0] == 0
999	&& auCur[1] == 0
1000	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1001	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1002	&& uSubLeaf >= cMinLeaves)
1003	{
1004	cRepeats = 0;
1005	break;
1006	}
1007
1008	/* 3. Leaf 0xb level type 0 check. */
1009	if ( uLeaf == 0xb
1010	&& (auCur[2] & 0xff00) == 0
1011	&& (auPrev[2] & 0xff00) == 0)
1012	{
1013	cRepeats = 0;
1014	break;
1015	}
1016
1017	/* 99. Give up. */
1018	if (uSubLeaf >= 128)
1019	{
1020	#ifndef IN_VBOX_CPU_REPORT
1021	/* Ok, limit it according to the documentation if possible just to
1022	avoid annoying users with these detection issues. */
1023	uint32_t cDocLimit = UINT32_MAX;
1024	if (uLeaf == 0x4)
1025	cDocLimit = 4;
1026	else if (uLeaf == 0x7)
1027	cDocLimit = 1;
1028	else if (uLeaf == 0xd)
1029	cDocLimit = 63;
1030	else if (uLeaf == 0xf)
1031	cDocLimit = 2;
1032	if (cDocLimit != UINT32_MAX)
1033	{
1034	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1035	*pcSubLeaves = cDocLimit + 3;
1036	return true;
1037	}
1038	#endif
1039	*pcSubLeaves = UINT32_MAX;
1040	return true;
1041	}
1042
1043	/* Advance. */
1044	uSubLeaf++;
1045	memcpy(auPrev, auCur, sizeof(auCur));
1046	}
1047
1048	/* Standard exit. */
1049	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1050	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1051	if (*pcSubLeaves == 0)
1052	*pcSubLeaves = 1;
1053	return true;
1054	}
1055
1056
1057	/**
1058	* Gets a CPU ID leaf.
1059	*
1060	* @returns VBox status code.
1061	* @param pVM Pointer to the VM.
1062	* @param pLeaf Where to store the found leaf.
1063	* @param uLeaf The leaf to locate.
1064	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1065	*/
1066	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1067	{
1068	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1069	uLeaf, uSubLeaf);
1070	if (pcLeaf)
1071	{
1072	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1073	return VINF_SUCCESS;
1074	}
1075
1076	return VERR_NOT_FOUND;
1077	}
1078
1079
1080	/**
1081	* Inserts a CPU ID leaf, replacing any existing ones.
1082	*
1083	* @returns VBox status code.
1084	* @param pVM Pointer to the VM.
1085	* @param pNewLeaf Pointer to the leaf being inserted.
1086	*/
1087	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1088	{
1089	/*
1090	* Validate parameters.
1091	*/
1092	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1093	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1094
1095	/*
1096	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1097	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1098	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1099	*/
1100	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1101	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1102	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1103	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1104	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1105	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1106	{
1107	return VERR_NOT_SUPPORTED;
1108	}
1109
1110	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1111	}
1112
1113	/**
1114	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1115	*
1116	* @returns VBox status code.
1117	* @param ppaLeaves Where to return the array pointer on success.
1118	* Use RTMemFree to release.
1119	* @param pcLeaves Where to return the size of the array on
1120	* success.
1121	*/
1122	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1123	{
1124	*ppaLeaves = NULL;
1125	*pcLeaves = 0;
1126
1127	/*
1128	* Try out various candidates. This must be sorted!
1129	*/
1130	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1131	{
1132	{ UINT32_C(0x00000000), false },
1133	{ UINT32_C(0x10000000), false },
1134	{ UINT32_C(0x20000000), false },
1135	{ UINT32_C(0x30000000), false },
1136	{ UINT32_C(0x40000000), false },
1137	{ UINT32_C(0x50000000), false },
1138	{ UINT32_C(0x60000000), false },
1139	{ UINT32_C(0x70000000), false },
1140	{ UINT32_C(0x80000000), false },
1141	{ UINT32_C(0x80860000), false },
1142	{ UINT32_C(0x8ffffffe), true },
1143	{ UINT32_C(0x8fffffff), true },
1144	{ UINT32_C(0x90000000), false },
1145	{ UINT32_C(0xa0000000), false },
1146	{ UINT32_C(0xb0000000), false },
1147	{ UINT32_C(0xc0000000), false },
1148	{ UINT32_C(0xd0000000), false },
1149	{ UINT32_C(0xe0000000), false },
1150	{ UINT32_C(0xf0000000), false },
1151	};
1152
1153	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1154	{
1155	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1156	uint32_t uEax, uEbx, uEcx, uEdx;
1157	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1158
1159	/*
1160	* Does EAX look like a typical leaf count value?
1161	*/
1162	if ( uEax > uLeaf
1163	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1164	{
1165	/* Yes, dump them. */
1166	uint32_t cLeaves = uEax - uLeaf + 1;
1167	while (cLeaves-- > 0)
1168	{
1169	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1170
1171	uint32_t fFlags = 0;
1172
1173	/* There are currently three known leaves containing an APIC ID
1174	that needs EMT specific attention */
1175	if (uLeaf == 1)
1176	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1177	else if (uLeaf == 0xb && uEcx != 0)
1178	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1179	else if ( uLeaf == UINT32_C(0x8000001e)
1180	&& ( uEax
1181	\|\| uEbx
1182	\|\| uEdx
1183	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1184	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1185
1186
1187	/* Check three times here to reduce the chance of CPU migration
1188	resulting in false positives with things like the APIC ID. */
1189	uint32_t cSubLeaves;
1190	bool fFinalEcxUnchanged;
1191	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1192	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1193	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1194	{
1195	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1196	{
1197	/* This shouldn't happen. But in case it does, file all
1198	relevant details in the release log. */
1199	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1200	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1201	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1202	{
1203	uint32_t auTmp[4];
1204	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1205	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1206	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1207	}
1208	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1209	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1210	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1211	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1212	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1213	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1214	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1215	}
1216
1217	if (fFinalEcxUnchanged)
1218	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1219
1220	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1221	{
1222	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1223	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1224	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1225	if (RT_FAILURE(rc))
1226	return rc;
1227	}
1228	}
1229	else
1230	{
1231	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1232	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1233	if (RT_FAILURE(rc))
1234	return rc;
1235	}
1236
1237	/* next */
1238	uLeaf++;
1239	}
1240	}
1241	/*
1242	* Special CPUIDs needs special handling as they don't follow the
1243	* leaf count principle used above.
1244	*/
1245	else if (s_aCandidates[iOuter].fSpecial)
1246	{
1247	bool fKeep = false;
1248	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1249	fKeep = true;
1250	else if ( uLeaf == 0x8fffffff
1251	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1252	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1253	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1254	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1255	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1256	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1257	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1258	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1259	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1260	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1261	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1262	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1263	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1264	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1265	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1266	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1267	fKeep = true;
1268	if (fKeep)
1269	{
1270	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1271	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1272	if (RT_FAILURE(rc))
1273	return rc;
1274	}
1275	}
1276	}
1277
1278	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1279	return VINF_SUCCESS;
1280	}
1281
1282
1283	/**
1284	* Determines the method the CPU uses to handle unknown CPUID leaves.
1285	*
1286	* @returns VBox status code.
1287	* @param penmUnknownMethod Where to return the method.
1288	* @param pDefUnknown Where to return default unknown values. This
1289	* will be set, even if the resulting method
1290	* doesn't actually needs it.
1291	*/
1292	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1293	{
1294	uint32_t uLastStd = ASMCpuId_EAX(0);
1295	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1296	if (!ASMIsValidExtRange(uLastExt))
1297	uLastExt = 0x80000000;
1298
1299	uint32_t auChecks[] =
1300	{
1301	uLastStd + 1,
1302	uLastStd + 5,
1303	uLastStd + 8,
1304	uLastStd + 32,
1305	uLastStd + 251,
1306	uLastExt + 1,
1307	uLastExt + 8,
1308	uLastExt + 15,
1309	uLastExt + 63,
1310	uLastExt + 255,
1311	0x7fbbffcc,
1312	0x833f7872,
1313	0xefff2353,
1314	0x35779456,
1315	0x1ef6d33e,
1316	};
1317
1318	static const uint32_t s_auValues[] =
1319	{
1320	0xa95d2156,
1321	0x00000001,
1322	0x00000002,
1323	0x00000008,
1324	0x00000000,
1325	0x55773399,
1326	0x93401769,
1327	0x12039587,
1328	};
1329
1330	/*
1331	* Simple method, all zeros.
1332	*/
1333	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1334	pDefUnknown->uEax = 0;
1335	pDefUnknown->uEbx = 0;
1336	pDefUnknown->uEcx = 0;
1337	pDefUnknown->uEdx = 0;
1338
1339	/*
1340	* Intel has been observed returning the last standard leaf.
1341	*/
1342	uint32_t auLast[4];
1343	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1344
1345	uint32_t cChecks = RT_ELEMENTS(auChecks);
1346	while (cChecks > 0)
1347	{
1348	uint32_t auCur[4];
1349	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1350	if (memcmp(auCur, auLast, sizeof(auCur)))
1351	break;
1352	cChecks--;
1353	}
1354	if (cChecks == 0)
1355	{
1356	/* Now, what happens when the input changes? Esp. ECX. */
1357	uint32_t cTotal = 0;
1358	uint32_t cSame = 0;
1359	uint32_t cLastWithEcx = 0;
1360	uint32_t cNeither = 0;
1361	uint32_t cValues = RT_ELEMENTS(s_auValues);
1362	while (cValues > 0)
1363	{
1364	uint32_t uValue = s_auValues[cValues - 1];
1365	uint32_t auLastWithEcx[4];
1366	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1367	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1368
1369	cChecks = RT_ELEMENTS(auChecks);
1370	while (cChecks > 0)
1371	{
1372	uint32_t auCur[4];
1373	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1374	if (!memcmp(auCur, auLast, sizeof(auCur)))
1375	{
1376	cSame++;
1377	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1378	cLastWithEcx++;
1379	}
1380	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1381	cLastWithEcx++;
1382	else
1383	cNeither++;
1384	cTotal++;
1385	cChecks--;
1386	}
1387	cValues--;
1388	}
1389
1390	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1391	if (cSame == cTotal)
1392	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1393	else if (cLastWithEcx == cTotal)
1394	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1395	else
1396	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1397	pDefUnknown->uEax = auLast[0];
1398	pDefUnknown->uEbx = auLast[1];
1399	pDefUnknown->uEcx = auLast[2];
1400	pDefUnknown->uEdx = auLast[3];
1401	return VINF_SUCCESS;
1402	}
1403
1404	/*
1405	* Unchanged register values?
1406	*/
1407	cChecks = RT_ELEMENTS(auChecks);
1408	while (cChecks > 0)
1409	{
1410	uint32_t const uLeaf = auChecks[cChecks - 1];
1411	uint32_t cValues = RT_ELEMENTS(s_auValues);
1412	while (cValues > 0)
1413	{
1414	uint32_t uValue = s_auValues[cValues - 1];
1415	uint32_t auCur[4];
1416	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1417	if ( auCur[0] != uLeaf
1418	\|\| auCur[1] != uValue
1419	\|\| auCur[2] != uValue
1420	\|\| auCur[3] != uValue)
1421	break;
1422	cValues--;
1423	}
1424	if (cValues != 0)
1425	break;
1426	cChecks--;
1427	}
1428	if (cChecks == 0)
1429	{
1430	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1431	return VINF_SUCCESS;
1432	}
1433
1434	/*
1435	* Just go with the simple method.
1436	*/
1437	return VINF_SUCCESS;
1438	}
1439
1440
1441	/**
1442	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1443	*
1444	* @returns Read only name string.
1445	* @param enmUnknownMethod The method to translate.
1446	*/
1447	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1448	{
1449	switch (enmUnknownMethod)
1450	{
1451	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1452	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1453	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1454	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1455
1456	case CPUMUNKNOWNCPUID_INVALID:
1457	case CPUMUNKNOWNCPUID_END:
1458	case CPUMUNKNOWNCPUID_32BIT_HACK:
1459	break;
1460	}
1461	return "Invalid-unknown-CPUID-method";
1462	}
1463
1464
1465	/**
1466	* Detect the CPU vendor give n the
1467	*
1468	* @returns The vendor.
1469	* @param uEAX EAX from CPUID(0).
1470	* @param uEBX EBX from CPUID(0).
1471	* @param uECX ECX from CPUID(0).
1472	* @param uEDX EDX from CPUID(0).
1473	*/
1474	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1475	{
1476	if (ASMIsValidStdRange(uEAX))
1477	{
1478	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1479	return CPUMCPUVENDOR_AMD;
1480
1481	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1482	return CPUMCPUVENDOR_INTEL;
1483
1484	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1485	return CPUMCPUVENDOR_VIA;
1486
1487	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1488	&& uECX == UINT32_C(0x64616574)
1489	&& uEDX == UINT32_C(0x736E4978))
1490	return CPUMCPUVENDOR_CYRIX;
1491
1492	/* "Geode by NSC", example: family 5, model 9. */
1493
1494	/** @todo detect the other buggers... */
1495	}
1496
1497	return CPUMCPUVENDOR_UNKNOWN;
1498	}
1499
1500
1501	/**
1502	* Translates a CPU vendor enum value into the corresponding string constant.
1503	*
1504	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1505	* value name. This can be useful when generating code.
1506	*
1507	* @returns Read only name string.
1508	* @param enmVendor The CPU vendor value.
1509	*/
1510	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1511	{
1512	switch (enmVendor)
1513	{
1514	case CPUMCPUVENDOR_INTEL: return "INTEL";
1515	case CPUMCPUVENDOR_AMD: return "AMD";
1516	case CPUMCPUVENDOR_VIA: return "VIA";
1517	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1518	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1519
1520	case CPUMCPUVENDOR_INVALID:
1521	case CPUMCPUVENDOR_32BIT_HACK:
1522	break;
1523	}
1524	return "Invalid-cpu-vendor";
1525	}
1526
1527
1528	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1529	{
1530	/* Could do binary search, doing linear now because I'm lazy. */
1531	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1532	while (cLeaves-- > 0)
1533	{
1534	if (pLeaf->uLeaf == uLeaf)
1535	return pLeaf;
1536	pLeaf++;
1537	}
1538	return NULL;
1539	}
1540
1541
1542	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1543	{
1544	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1545	if ( !pLeaf
1546	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1547	return pLeaf;
1548
1549	/* Linear sub-leaf search. Lazy as usual. */
1550	cLeaves -= pLeaf - paLeaves;
1551	while ( cLeaves-- > 0
1552	&& pLeaf->uLeaf == uLeaf)
1553	{
1554	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1555	return pLeaf;
1556	pLeaf++;
1557	}
1558
1559	return NULL;
1560	}
1561
1562
1563	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1564	{
1565	RT_ZERO(*pFeatures);
1566	if (cLeaves >= 2)
1567	{
1568	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1569	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1570	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1571	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1572	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1573	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1574
1575	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1576	pStd0Leaf->uEbx,
1577	pStd0Leaf->uEcx,
1578	pStd0Leaf->uEdx);
1579	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1580	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1581	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1582	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1583	pFeatures->uFamily,
1584	pFeatures->uModel,
1585	pFeatures->uStepping);
1586
1587	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1588	if (pLeaf)
1589	pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff;
1590	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1591	pFeatures->cMaxPhysAddrWidth = 36;
1592	else
1593	pFeatures->cMaxPhysAddrWidth = 32;
1594
1595	/* Standard features. */
1596	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1597	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1598	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1599	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1600	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1601	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1602	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1603	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1604	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1605	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1606	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1607	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1608	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1609	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1610	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1611	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1612	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1613	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1614	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1615	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1616	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1617	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1618
1619	/* Structured extended features. */
1620	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1621	if (pSxfLeaf0)
1622	{
1623	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEcx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1624	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEcx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1625	}
1626
1627	/* MWAIT/MONITOR leaf. */
1628	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1629	if (pMWaitLeaf)
1630	{
1631	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1632	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1633	}
1634
1635	/* Extended features. */
1636	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1637	if (pExtLeaf)
1638	{
1639	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1640	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1641	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1642	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1643	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1644	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1645	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1646	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1647	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1648	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1649	}
1650
1651	if ( pExtLeaf
1652	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1653	{
1654	/* AMD features. */
1655	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1656	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1657	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1658	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1659	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1660	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1661	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1662	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1663	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1664	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1665	}
1666
1667	/*
1668	* Quirks.
1669	*/
1670	pFeatures->fLeakyFxSR = pExtLeaf
1671	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1672	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1673	&& pFeatures->uFamily >= 6 /* K7 and up */;
1674
1675	/*
1676	* Max extended (/FPU) state.
1677	*/
1678	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1679	if (pFeatures->fXSaveRstor)
1680	{
1681	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1682	if (pXStateLeaf0)
1683	{
1684	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1685	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1686	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1687	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1688	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1689	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1690	{
1691	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1692
1693	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1694	if ( pXStateLeaf1
1695	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1696	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1697	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1698	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEbx;
1699	}
1700	else
1701	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1702	pFeatures->fXSaveRstor = 0);
1703	}
1704	else
1705	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1706	pFeatures->fXSaveRstor = 0);
1707	}
1708	}
1709	else
1710	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1711	return VINF_SUCCESS;
1712	}
1713
1714
1715	/*
1716	*
1717	* Init related code.
1718	* Init related code.
1719	* Init related code.
1720	*
1721	*
1722	*/
1723	#ifdef VBOX_IN_VMM
1724
1725
1726	/**
1727	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1728	*
1729	* This ignores the fSubLeafMask.
1730	*
1731	* @returns Pointer to the matching leaf, or NULL if not found.
1732	* @param paLeaves The CPUID leaves to search. This is sorted.
1733	* @param cLeaves The number of leaves in the array.
1734	* @param uLeaf The leaf to locate.
1735	* @param uSubLeaf The subleaf to locate.
1736	*/
1737	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1738	{
1739	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1740	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1741	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1742	if (iEnd)
1743	{
1744	uint32_t iBegin = 0;
1745	for (;;)
1746	{
1747	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1748	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1749	if (uNeedle < uCur)
1750	{
1751	if (i > iBegin)
1752	iEnd = i;
1753	else
1754	break;
1755	}
1756	else if (uNeedle > uCur)
1757	{
1758	if (i + 1 < iEnd)
1759	iBegin = i + 1;
1760	else
1761	break;
1762	}
1763	else
1764	return &paLeaves[i];
1765	}
1766	}
1767	return NULL;
1768	}
1769
1770
1771	/**
1772	* Loads MSR range overrides.
1773	*
1774	* This must be called before the MSR ranges are moved from the normal heap to
1775	* the hyper heap!
1776	*
1777	* @returns VBox status code (VMSetError called).
1778	* @param pVM Pointer to the cross context VM structure
1779	* @param pMsrNode The CFGM node with the MSR overrides.
1780	*/
1781	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1782	{
1783	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1784	{
1785	/*
1786	* Assemble a valid MSR range.
1787	*/
1788	CPUMMSRRANGE MsrRange;
1789	MsrRange.offCpumCpu = 0;
1790	MsrRange.fReserved = 0;
1791
1792	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1793	if (RT_FAILURE(rc))
1794	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1795
1796	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1797	if (RT_FAILURE(rc))
1798	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1799	MsrRange.szName, rc);
1800
1801	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1802	if (RT_FAILURE(rc))
1803	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1804	MsrRange.szName, rc);
1805
1806	char szType[32];
1807	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1808	if (RT_FAILURE(rc))
1809	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1810	MsrRange.szName, rc);
1811	if (!RTStrICmp(szType, "FixedValue"))
1812	{
1813	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1814	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1815
1816	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1817	if (RT_FAILURE(rc))
1818	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1819	MsrRange.szName, rc);
1820
1821	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1822	if (RT_FAILURE(rc))
1823	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1824	MsrRange.szName, rc);
1825
1826	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1827	if (RT_FAILURE(rc))
1828	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1829	MsrRange.szName, rc);
1830	}
1831	else
1832	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1833	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1834
1835	/*
1836	* Insert the range into the table (replaces/splits/shrinks existing
1837	* MSR ranges).
1838	*/
1839	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1840	&MsrRange);
1841	if (RT_FAILURE(rc))
1842	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
1843	}
1844
1845	return VINF_SUCCESS;
1846	}
1847
1848
1849	/**
1850	* Loads CPUID leaf overrides.
1851	*
1852	* This must be called before the CPUID leaves are moved from the normal
1853	* heap to the hyper heap!
1854	*
1855	* @returns VBox status code (VMSetError called).
1856	* @param pVM Pointer to the cross context VM structure
1857	* @param pParentNode The CFGM node with the CPUID leaves.
1858	* @param pszLabel How to label the overrides we're loading.
1859	*/
1860	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
1861	{
1862	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1863	{
1864	/*
1865	* Get the leaf and subleaf numbers.
1866	*/
1867	char szName[128];
1868	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
1869	if (RT_FAILURE(rc))
1870	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
1871
1872	/* The leaf number is either specified directly or thru the node name. */
1873	uint32_t uLeaf;
1874	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
1875	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1876	{
1877	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
1878	if (rc != VINF_SUCCESS)
1879	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
1880	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
1881	}
1882	else if (RT_FAILURE(rc))
1883	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
1884	pszLabel, szName, rc);
1885
1886	uint32_t uSubLeaf;
1887	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
1888	if (RT_FAILURE(rc))
1889	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
1890	pszLabel, szName, rc);
1891
1892	uint32_t fSubLeafMask;
1893	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
1894	if (RT_FAILURE(rc))
1895	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
1896	pszLabel, szName, rc);
1897
1898	/*
1899	* Look up the specified leaf, since the output register values
1900	* defaults to any existing values. This allows overriding a single
1901	* register, without needing to know the other values.
1902	*/
1903	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
1904	CPUMCPUIDLEAF Leaf;
1905	if (pLeaf)
1906	Leaf = *pLeaf;
1907	else
1908	RT_ZERO(Leaf);
1909	Leaf.uLeaf = uLeaf;
1910	Leaf.uSubLeaf = uSubLeaf;
1911	Leaf.fSubLeafMask = fSubLeafMask;
1912
1913	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
1914	if (RT_FAILURE(rc))
1915	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
1916	pszLabel, szName, rc);
1917	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
1918	if (RT_FAILURE(rc))
1919	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
1920	pszLabel, szName, rc);
1921	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
1922	if (RT_FAILURE(rc))
1923	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
1924	pszLabel, szName, rc);
1925	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
1926	if (RT_FAILURE(rc))
1927	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
1928	pszLabel, szName, rc);
1929
1930	/*
1931	* Insert the leaf into the table (replaces existing ones).
1932	*/
1933	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1934	&Leaf);
1935	if (RT_FAILURE(rc))
1936	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
1937	}
1938
1939	return VINF_SUCCESS;
1940	}
1941
1942
1943
1944	/**
1945	* Fetches overrides for a CPUID leaf.
1946	*
1947	* @returns VBox status code.
1948	* @param pLeaf The leaf to load the overrides into.
1949	* @param pCfgNode The CFGM node containing the overrides
1950	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
1951	* @param iLeaf The CPUID leaf number.
1952	*/
1953	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
1954	{
1955	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
1956	if (pLeafNode)
1957	{
1958	uint32_t u32;
1959	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
1960	if (RT_SUCCESS(rc))
1961	pLeaf->uEax = u32;
1962	else
1963	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1964
1965	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
1966	if (RT_SUCCESS(rc))
1967	pLeaf->uEbx = u32;
1968	else
1969	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1970
1971	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
1972	if (RT_SUCCESS(rc))
1973	pLeaf->uEcx = u32;
1974	else
1975	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1976
1977	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
1978	if (RT_SUCCESS(rc))
1979	pLeaf->uEdx = u32;
1980	else
1981	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1982
1983	}
1984	return VINF_SUCCESS;
1985	}
1986
1987
1988	/**
1989	* Load the overrides for a set of CPUID leaves.
1990	*
1991	* @returns VBox status code.
1992	* @param paLeaves The leaf array.
1993	* @param cLeaves The number of leaves.
1994	* @param uStart The start leaf number.
1995	* @param pCfgNode The CFGM node containing the overrides
1996	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
1997	*/
1998	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
1999	{
2000	for (uint32_t i = 0; i < cLeaves; i++)
2001	{
2002	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2003	if (RT_FAILURE(rc))
2004	return rc;
2005	}
2006
2007	return VINF_SUCCESS;
2008	}
2009
2010	/**
2011	* Init a set of host CPUID leaves.
2012	*
2013	* @returns VBox status code.
2014	* @param paLeaves The leaf array.
2015	* @param cLeaves The number of leaves.
2016	* @param uStart The start leaf number.
2017	* @param pCfgNode The /CPUM/HostCPUID/ node.
2018	*/
2019	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2020	{
2021	/* Using the ECX variant for all of them can't hurt... */
2022	for (uint32_t i = 0; i < cLeaves; i++)
2023	ASMCpuIdExSlow(uStart + i, 0, 0, 0, &paLeaves[i].uEax, &paLeaves[i].uEbx, &paLeaves[i].uEcx, &paLeaves[i].uEdx);
2024
2025	/* Load CPUID leaf override; we currently don't care if the user
2026	specifies features the host CPU doesn't support. */
2027	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
2028	}
2029
2030
2031	/**
2032	* Installs the CPUID leaves and explods the data into structures like
2033	* GuestFeatures and CPUMCTX::aoffXState.
2034	*
2035	* @returns VBox status code.
2036	* @param pVM The cross context VM handle.
2037	* @param pCpum The CPUM part of @a VM.
2038	* @param paLeaves The leaves. These will be copied (but not freed).
2039	* @param cLeaves The number of leaves.
2040	*/
2041	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
2042	{
2043	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2044
2045	/*
2046	* Install the CPUID information.
2047	*/
2048	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2049	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2050
2051	AssertLogRelRCReturn(rc, rc);
2052	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2053	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2054	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2055	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2056	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2057
2058	/*
2059	* Update the default CPUID leaf if necessary.
2060	*/
2061	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2062	{
2063	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2064	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2065	{
2066	/* We don't use CPUID(0).eax here because of the NT hack that only
2067	changes that value without actually removing any leaves. */
2068	uint32_t i = 0;
2069	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2070	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2071	{
2072	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2073	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2074	i++;
2075	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2076	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2077	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2078	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2079	}
2080	break;
2081	}
2082	default:
2083	break;
2084	}
2085
2086	/*
2087	* Explode the guest CPU features.
2088	*/
2089	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
2090	AssertLogRelRCReturn(rc, rc);
2091
2092	/*
2093	* Adjust the scalable bus frequency according to the CPUID information
2094	* we're now using.
2095	*/
2096	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2097	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2098	? UINT64_C(100000000) /* 100MHz */
2099	: UINT64_C(133333333); /* 133MHz */
2100
2101	/*
2102	* Populate the legacy arrays. Currently used for everything, later only
2103	* for patch manager.
2104	*/
2105	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2106	{
2107	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2108	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2109	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2110	};
2111	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2112	{
2113	uint32_t cLeft = aOldRanges[i].cCpuIds;
2114	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2115	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2116	while (cLeft-- > 0)
2117	{
2118	uLeaf--;
2119	pLegacyLeaf--;
2120
2121	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2122	if (pLeaf)
2123	{
2124	pLegacyLeaf->uEax = pLeaf->uEax;
2125	pLegacyLeaf->uEbx = pLeaf->uEbx;
2126	pLegacyLeaf->uEcx = pLeaf->uEcx;
2127	pLegacyLeaf->uEdx = pLeaf->uEdx;
2128	}
2129	else
2130	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2131	}
2132	}
2133
2134	/*
2135	* Configure XSAVE offsets according to the CPUID info.
2136	*/
2137	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2138	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2139	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2140	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2141	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2142	{
2143	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2144	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2145	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2146	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2147	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2148	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2149	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2150	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2151	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2152	pCpum->GuestFeatures.cbMaxExtendedState),
2153	VERR_CPUM_IPE_1);
2154	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2155	}
2156	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2157
2158	/* Copy the CPU #0 data to the other CPUs. */
2159	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2160	{
2161	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2162	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2163	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2164	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2165	}
2166
2167	return VINF_SUCCESS;
2168	}
2169
2170
2171	/** @name Instruction Set Extension Options
2172	* @{ */
2173	/** Configuration option type (extended boolean, really). */
2174	typedef uint8_t CPUMISAEXTCFG;
2175	/** Always disable the extension. */
2176	#define CPUMISAEXTCFG_DISABLED false
2177	/** Enable the extension if it's supported by the host CPU. */
2178	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2179	/** Enable the extension if it's supported by the host CPU, but don't let
2180	* the portable CPUID feature disable it. */
2181	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2182	/** Always enable the extension. */
2183	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2184	/** @} */
2185
2186	/**
2187	* CPUID Configuration (from CFGM).
2188	*
2189	* @remarks The members aren't document since we would only be duplicating the
2190	* \@cfgm entries in cpumR3CpuIdReadConfig.
2191	*/
2192	typedef struct CPUMCPUIDCONFIG
2193	{
2194	bool fNt4LeafLimit;
2195	bool fInvariantTsc;
2196
2197	CPUMISAEXTCFG enmCmpXchg16b;
2198	CPUMISAEXTCFG enmMonitor;
2199	CPUMISAEXTCFG enmMWaitExtensions;
2200	CPUMISAEXTCFG enmSse41;
2201	CPUMISAEXTCFG enmSse42;
2202	CPUMISAEXTCFG enmAvx;
2203	CPUMISAEXTCFG enmAvx2;
2204	CPUMISAEXTCFG enmXSave;
2205	CPUMISAEXTCFG enmAesNi;
2206	CPUMISAEXTCFG enmPClMul;
2207	CPUMISAEXTCFG enmPopCnt;
2208	CPUMISAEXTCFG enmMovBe;
2209	CPUMISAEXTCFG enmRdRand;
2210	CPUMISAEXTCFG enmRdSeed;
2211	CPUMISAEXTCFG enmCLFlushOpt;
2212
2213	CPUMISAEXTCFG enmAbm;
2214	CPUMISAEXTCFG enmSse4A;
2215	CPUMISAEXTCFG enmMisAlnSse;
2216	CPUMISAEXTCFG enm3dNowPrf;
2217	CPUMISAEXTCFG enmAmdExtMmx;
2218
2219	uint32_t uMaxStdLeaf;
2220	uint32_t uMaxExtLeaf;
2221	uint32_t uMaxCentaurLeaf;
2222	uint32_t uMaxIntelFamilyModelStep;
2223	char szCpuName[128];
2224	} CPUMCPUIDCONFIG;
2225	/** Pointer to CPUID config (from CFGM). */
2226	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2227
2228
2229	/**
2230	* Insert hypervisor identification leaves.
2231	*
2232	* We only return minimal information, primarily ensuring that the
2233	* 0x40000000 function returns 0x40000001 and identifying ourselves.
2234	* Hypervisor-specific interface is supported through GIM which will
2235	* modify these leaves if required depending on the GIM provider.
2236	*
2237	* @returns VBox status code.
2238	* @param pCpum The CPUM instance data.
2239	* @param pConfig The CPUID configuration we've read from CFGM.
2240	*/
2241	static int cpumR3CpuIdPlantHypervisorLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2242	{
2243	CPUMCPUIDLEAF NewLeaf;
2244	NewLeaf.uLeaf = UINT32_C(0x40000000);
2245	NewLeaf.uSubLeaf = 0;
2246	NewLeaf.fSubLeafMask = 0;
2247	NewLeaf.uEax = UINT32_C(0x40000001);
2248	NewLeaf.uEbx = 0x786f4256 /* 'VBox' */;
2249	NewLeaf.uEcx = 0x786f4256 /* 'VBox' */;
2250	NewLeaf.uEdx = 0x786f4256 /* 'VBox' */;
2251	NewLeaf.fFlags = 0;
2252	int rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
2253	AssertLogRelRCReturn(rc, rc);
2254
2255	NewLeaf.uLeaf = UINT32_C(0x40000001);
2256	NewLeaf.uEax = 0x656e6f6e; /* 'none' */
2257	NewLeaf.uEbx = 0;
2258	NewLeaf.uEcx = 0;
2259	NewLeaf.uEdx = 0;
2260	NewLeaf.fFlags = 0;
2261	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
2262	AssertLogRelRCReturn(rc, rc);
2263
2264	return VINF_SUCCESS;
2265	}
2266
2267
2268	/**
2269	* Mini CPU selection support for making Mac OS X happy.
2270	*
2271	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2272	*
2273	* @param pCpum The CPUM instance data.
2274	* @param pConfig The CPUID configuration we've read from CFGM.
2275	*/
2276	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2277	{
2278	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2279	{
2280	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2281	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2282	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2283	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2284	0);
2285	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2286	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2287	{
2288	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2289	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2290	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2291	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2292	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2293	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2294	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2295	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2296	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2297	pStdFeatureLeaf->uEax = uNew;
2298	}
2299	}
2300	}
2301
2302
2303
2304	/**
2305	* Limit it the number of entries, zapping the remainder.
2306	*
2307	* The limits are masking off stuff about power saving and similar, this
2308	* is perhaps a bit crudely done as there is probably some relatively harmless
2309	* info too in these leaves (like words about having a constant TSC).
2310	*
2311	* @param pCpum The CPUM instance data.
2312	* @param pConfig The CPUID configuration we've read from CFGM.
2313	*/
2314	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2315	{
2316	/*
2317	* Standard leaves.
2318	*/
2319	uint32_t uSubLeaf = 0;
2320	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2321	if (pCurLeaf)
2322	{
2323	uint32_t uLimit = pCurLeaf->uEax;
2324	if (uLimit <= UINT32_C(0x000fffff))
2325	{
2326	if (uLimit > pConfig->uMaxStdLeaf)
2327	{
2328	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2329	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2330	uLimit + 1, UINT32_C(0x000fffff));
2331	}
2332
2333	/* NT4 hack, no zapping of extra leaves here. */
2334	if (pConfig->fNt4LeafLimit && uLimit > 3)
2335	pCurLeaf->uEax = uLimit = 3;
2336
2337	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2338	pCurLeaf->uEax = uLimit;
2339	}
2340	else
2341	{
2342	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2343	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2344	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2345	}
2346	}
2347
2348	/*
2349	* Extended leaves.
2350	*/
2351	uSubLeaf = 0;
2352	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2353	if (pCurLeaf)
2354	{
2355	uint32_t uLimit = pCurLeaf->uEax;
2356	if ( uLimit >= UINT32_C(0x80000000)
2357	&& uLimit <= UINT32_C(0x800fffff))
2358	{
2359	if (uLimit > pConfig->uMaxExtLeaf)
2360	{
2361	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2362	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2363	uLimit + 1, UINT32_C(0x800fffff));
2364	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2365	pCurLeaf->uEax = uLimit;
2366	}
2367	}
2368	else
2369	{
2370	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2371	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2372	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2373	}
2374	}
2375
2376	/*
2377	* Centaur leaves (VIA).
2378	*/
2379	uSubLeaf = 0;
2380	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2381	if (pCurLeaf)
2382	{
2383	uint32_t uLimit = pCurLeaf->uEax;
2384	if ( uLimit >= UINT32_C(0xc0000000)
2385	&& uLimit <= UINT32_C(0xc00fffff))
2386	{
2387	if (uLimit > pConfig->uMaxCentaurLeaf)
2388	{
2389	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2390	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2391	uLimit + 1, UINT32_C(0xcfffffff));
2392	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2393	pCurLeaf->uEax = uLimit;
2394	}
2395	}
2396	else
2397	{
2398	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2399	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2400	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2401	}
2402	}
2403	}
2404
2405
2406	/**
2407	* Clears a CPUID leaf and all sub-leaves (to zero).
2408	*
2409	* @param pCpum The CPUM instance data.
2410	* @param uLeaf The leaf to clear.
2411	*/
2412	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2413	{
2414	uint32_t uSubLeaf = 0;
2415	PCPUMCPUIDLEAF pCurLeaf;
2416	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2417	{
2418	pCurLeaf->uEax = 0;
2419	pCurLeaf->uEbx = 0;
2420	pCurLeaf->uEcx = 0;
2421	pCurLeaf->uEdx = 0;
2422	uSubLeaf++;
2423	}
2424	}
2425
2426
2427	/**
2428	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2429	* the given leaf.
2430	*
2431	* @returns pLeaf.
2432	* @param pCpum The CPUM instance data.
2433	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2434	*/
2435	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2436	{
2437	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2438	if (pLeaf->fSubLeafMask != 0)
2439	{
2440	/*
2441	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2442	* Log everything while we're at it.
2443	*/
2444	LogRel(("CPUM:\n"
2445	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2446	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2447	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2448	for (;;)
2449	{
2450	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2451	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2452	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2453	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2454	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2455	break;
2456	pSubLeaf++;
2457	}
2458	LogRel(("CPUM:\n"));
2459
2460	/*
2461	* Remove the offending sub-leaves.
2462	*/
2463	if (pSubLeaf != pLeaf)
2464	{
2465	if (pSubLeaf != pLast)
2466	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2467	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2468	}
2469
2470	/*
2471	* Convert the first sub-leaf into a single leaf.
2472	*/
2473	pLeaf->uSubLeaf = 0;
2474	pLeaf->fSubLeafMask = 0;
2475	}
2476	return pLeaf;
2477	}
2478
2479
2480	/**
2481	* Sanitizes and adjust the CPUID leaves.
2482	*
2483	* Drop features that aren't virtualized (or virtualizable). Adjust information
2484	* and capabilities to fit the virtualized hardware. Remove information the
2485	* guest shouldn't have (because it's wrong in the virtual world or because it
2486	* gives away host details) or that we don't have documentation for and no idea
2487	* what means.
2488	*
2489	* @returns VBox status code.
2490	* @param pVM Pointer to the cross context VM structure (for cCpus).
2491	* @param pCpum The CPUM instance data.
2492	* @param pConfig The CPUID configuration we've read from CFGM.
2493	*/
2494	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2495	{
2496	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2497	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2498	{ \
2499	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2500	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2501	}
2502	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2503	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2504	{ \
2505	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2506	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2507	}
2508	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2509	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2510	&& ((a_pLeafReg) & (fBitMask)) \
2511	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2512	{ \
2513	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2514	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2515	}
2516	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2517
2518	/* Cpuid 1:
2519	* EAX: CPU model, family and stepping.
2520	*
2521	* ECX + EDX: Supported features. Only report features we can support.
2522	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2523	* options may require adjusting (i.e. stripping what was enabled).
2524	*
2525	* EBX: Branding, CLFLUSH line size, logical processors per package and
2526	* initial APIC ID.
2527	*/
2528	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2529	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2530	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2531
2532	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2533	\| X86_CPUID_FEATURE_EDX_VME
2534	\| X86_CPUID_FEATURE_EDX_DE
2535	\| X86_CPUID_FEATURE_EDX_PSE
2536	\| X86_CPUID_FEATURE_EDX_TSC
2537	\| X86_CPUID_FEATURE_EDX_MSR
2538	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2539	\| X86_CPUID_FEATURE_EDX_MCE
2540	\| X86_CPUID_FEATURE_EDX_CX8
2541	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2542	//\| RT_BIT_32(10) - not defined
2543	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2544	//\| X86_CPUID_FEATURE_EDX_SEP
2545	\| X86_CPUID_FEATURE_EDX_MTRR
2546	\| X86_CPUID_FEATURE_EDX_PGE
2547	\| X86_CPUID_FEATURE_EDX_MCA
2548	\| X86_CPUID_FEATURE_EDX_CMOV
2549	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2550	\| X86_CPUID_FEATURE_EDX_PSE36
2551	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2552	\| X86_CPUID_FEATURE_EDX_CLFSH
2553	//\| RT_BIT_32(20) - not defined
2554	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2555	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2556	\| X86_CPUID_FEATURE_EDX_MMX
2557	\| X86_CPUID_FEATURE_EDX_FXSR
2558	\| X86_CPUID_FEATURE_EDX_SSE
2559	\| X86_CPUID_FEATURE_EDX_SSE2
2560	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2561	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading/cores - see below.
2562	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2563	//\| RT_BIT_32(30) - not defined
2564	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2565	;
2566	pStdFeatureLeaf->uEcx &= 0
2567	\| X86_CPUID_FEATURE_ECX_SSE3
2568	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2569	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2570	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2571	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2572	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2573	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized yet.
2574	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2575	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2576	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2577	\| X86_CPUID_FEATURE_ECX_SSSE3
2578	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2579	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2580	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2581	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2582	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2583	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2584	//\| X86_CPUID_FEATURE_ECX_PCID - not implemented yet.
2585	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2586	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2587	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2588	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2589	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2590	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2591	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2592	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2593	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2594	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2595	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2596	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2597	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2598	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2599	;
2600
2601	if (pCpum->u8PortableCpuIdLevel > 0)
2602	{
2603	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2604	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2605	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2606	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2607	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2608	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2609	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2610	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2611	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2612	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2613	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2614	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2615	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2616	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2617	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2618	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2619	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2620	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2621
2622	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2623	\| X86_CPUID_FEATURE_EDX_PSN
2624	\| X86_CPUID_FEATURE_EDX_DS
2625	\| X86_CPUID_FEATURE_EDX_ACPI
2626	\| X86_CPUID_FEATURE_EDX_SS
2627	\| X86_CPUID_FEATURE_EDX_TM
2628	\| X86_CPUID_FEATURE_EDX_PBE
2629	)));
2630	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2631	\| X86_CPUID_FEATURE_ECX_CPLDS
2632	\| X86_CPUID_FEATURE_ECX_VMX
2633	\| X86_CPUID_FEATURE_ECX_SMX
2634	\| X86_CPUID_FEATURE_ECX_EST
2635	\| X86_CPUID_FEATURE_ECX_TM2
2636	\| X86_CPUID_FEATURE_ECX_CNTXID
2637	\| X86_CPUID_FEATURE_ECX_FMA
2638	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2639	\| X86_CPUID_FEATURE_ECX_PDCM
2640	\| X86_CPUID_FEATURE_ECX_DCA
2641	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2642	)));
2643	}
2644
2645	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2646	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2647	#ifdef VBOX_WITH_MULTI_CORE
2648	if (pVM->cCpus > 1)
2649	{
2650	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2651	core times the number of CPU cores per processor */
2652	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2653	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
2654	}
2655	#endif
2656
2657	/* Force standard feature bits. */
2658	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2659	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2660	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2661	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2662	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2663	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2664	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2665	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2666	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2667	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2668	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2669	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2670	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2671	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2672	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2673	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2674	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2675	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2676	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2677	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2678	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2679	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2680
2681	pStdFeatureLeaf = NULL; /* Must refetch! */
2682
2683	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2684	* AMD:
2685	* EAX: CPU model, family and stepping.
2686	*
2687	* ECX + EDX: Supported features. Only report features we can support.
2688	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2689	* options may require adjusting (i.e. stripping what was enabled).
2690	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2691	*
2692	* EBX: Branding ID and package type (or reserved).
2693	*
2694	* Intel and probably most others:
2695	* EAX: 0
2696	* EBX: 0
2697	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2698	*/
2699	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2700	if (pExtFeatureLeaf)
2701	{
2702	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2703
2704	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2705	\| X86_CPUID_AMD_FEATURE_EDX_VME
2706	\| X86_CPUID_AMD_FEATURE_EDX_DE
2707	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2708	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2709	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2710	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2711	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2712	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2713	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2714	//\| RT_BIT_32(10) - reserved
2715	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2716	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2717	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2718	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2719	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2720	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2721	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2722	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2723	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2724	//\| RT_BIT_32(18) - reserved
2725	//\| RT_BIT_32(19) - reserved
2726	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2727	//\| RT_BIT_32(21) - reserved
2728	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2729	\| X86_CPUID_AMD_FEATURE_EDX_MMX
2730	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
2731	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
2732	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2733	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2734	//\| RT_BIT_32(28) - reserved
2735	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2736	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2737	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
2738	;
2739	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2740	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2741	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
2742	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2743	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
2744	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2745	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2746	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2747	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2748	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2749	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2750	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
2751	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
2752	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2753	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
2754	//\| RT_BIT_32(14) - reserved
2755	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2756	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2757	//\| RT_BIT_32(17) - reserved
2758	//\| RT_BIT_32(18) - reserved
2759	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2760	//\| RT_BIT_32(20) - reserved
2761	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2762	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2763	//\| RT_BIT_32(23) - reserved
2764	//\| RT_BIT_32(24) - reserved
2765	//\| RT_BIT_32(25) - reserved
2766	//\| RT_BIT_32(26) - reserved
2767	//\| RT_BIT_32(27) - reserved
2768	//\| RT_BIT_32(28) - reserved
2769	//\| RT_BIT_32(29) - reserved
2770	//\| RT_BIT_32(30) - reserved
2771	//\| RT_BIT_32(31) - reserved
2772	;
2773	#ifdef VBOX_WITH_MULTI_CORE
2774	if ( pVM->cCpus > 1
2775	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2776	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2777	#endif
2778
2779	if (pCpum->u8PortableCpuIdLevel > 0)
2780	{
2781	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2782	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2783	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2784	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2785	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2786	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2787	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2788	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2789	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2790	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2791	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2792	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2793	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2794	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2795	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2796
2797	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2798	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2799	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2800	\| X86_CPUID_AMD_FEATURE_ECX_IBS
2801	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2802	\| X86_CPUID_AMD_FEATURE_ECX_WDT
2803	\| X86_CPUID_AMD_FEATURE_ECX_LWP
2804	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
2805	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2806	\| UINT32_C(0xff964000)
2807	)));
2808	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2809	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2810	\| RT_BIT(18)
2811	\| RT_BIT(19)
2812	\| RT_BIT(21)
2813	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2814	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2815	\| RT_BIT(28)
2816	)));
2817	}
2818
2819	/* Force extended feature bits. */
2820	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2821	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
2822	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2823	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2824	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2825	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2826	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2827	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2828	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2829	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2830	}
2831	pExtFeatureLeaf = NULL; /* Must refetch! */
2832
2833
2834	/* Cpuid 2:
2835	* Intel: (Nondeterministic) Cache and TLB information
2836	* AMD: Reserved
2837	* VIA: Reserved
2838	* Safe to expose.
2839	*/
2840	uint32_t uSubLeaf = 0;
2841	PCPUMCPUIDLEAF pCurLeaf;
2842	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2843	{
2844	if ((pCurLeaf->uEax & 0xff) > 1)
2845	{
2846	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2847	pCurLeaf->uEax &= UINT32_C(0xffffff01);
2848	}
2849	uSubLeaf++;
2850	}
2851
2852	/* Cpuid 3:
2853	* Intel: EAX, EBX - reserved (transmeta uses these)
2854	* ECX, EDX - Processor Serial Number if available, otherwise reserved
2855	* AMD: Reserved
2856	* VIA: Reserved
2857	* Safe to expose
2858	*/
2859	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2860	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
2861	{
2862	uSubLeaf = 0;
2863	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
2864	{
2865	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2866	if (pCpum->u8PortableCpuIdLevel > 0)
2867	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2868	uSubLeaf++;
2869	}
2870	}
2871
2872	/* Cpuid 4 + ECX:
2873	* Intel: Deterministic Cache Parameters Leaf.
2874	* AMD: Reserved
2875	* VIA: Reserved
2876	* Safe to expose, except for EAX:
2877	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
2878	* Bits 31-26: Maximum number of processor cores in this physical package**
2879	* Note: These SMP values are constant regardless of ECX
2880	*/
2881	uSubLeaf = 0;
2882	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
2883	{
2884	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
2885	#ifdef VBOX_WITH_MULTI_CORE
2886	if ( pVM->cCpus > 1
2887	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2888	{
2889	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
2890	/* One logical processor with possibly multiple cores. */
2891	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
2892	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
2893	}
2894	#endif
2895	uSubLeaf++;
2896	}
2897
2898	/* Cpuid 5: Monitor/mwait Leaf
2899	* Intel: ECX, EDX - reserved
2900	* EAX, EBX - Smallest and largest monitor line size
2901	* AMD: EDX - reserved
2902	* EAX, EBX - Smallest and largest monitor line size
2903	* ECX - extensions (ignored for now)
2904	* VIA: Reserved
2905	* Safe to expose
2906	*/
2907	uSubLeaf = 0;
2908	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
2909	{
2910	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2911	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
2912	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2913
2914	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2915	if (pConfig->enmMWaitExtensions)
2916	{
2917	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
2918	/** @todo: for now we just expose host's MWAIT C-states, although conceptually
2919	it shall be part of our power management virtualization model */
2920	#if 0
2921	/* MWAIT sub C-states */
2922	pCurLeaf->uEdx =
2923	(0 << 0) /* 0 in C0 */ \|
2924	(2 << 4) /* 2 in C1 */ \|
2925	(2 << 8) /* 2 in C2 */ \|
2926	(2 << 12) /* 2 in C3 */ \|
2927	(0 << 16) /* 0 in C4 */
2928	;
2929	#endif
2930	}
2931	else
2932	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2933	uSubLeaf++;
2934	}
2935
2936	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
2937	* Intel: Various stuff.
2938	* AMD: EAX, EBX, EDX - reserved.
2939	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
2940	* present. Same as intel.
2941	* VIA: ??
2942	*
2943	* We clear everything here for now.
2944	*/
2945	cpumR3CpuIdZeroLeaf(pCpum, 6);
2946
2947	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
2948	* EAX: Number of sub leaves.
2949	* EBX+ECX+EDX: Feature flags
2950	*
2951	* We only have documentation for one sub-leaf, so clear all other (no need
2952	* to remove them as such, just set them to zero).
2953	*
2954	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2955	* options may require adjusting (i.e. stripping what was enabled).
2956	*/
2957	uSubLeaf = 0;
2958	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
2959	{
2960	switch (uSubLeaf)
2961	{
2962	case 0:
2963	{
2964	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
2965	pCurLeaf->uEbx &= 0
2966	//\| X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
2967	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
2968	//\| RT_BIT(2) - reserved
2969	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
2970	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
2971	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
2972	//\| RT_BIT(6) - reserved
2973	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
2974	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
2975	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
2976	//\| X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
2977	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
2978	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
2979	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
2980	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
2981	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
2982	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
2983	//\| RT_BIT(17) - reserved
2984	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
2985	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
2986	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
2987	//\| RT_BIT(21) - reserved
2988	//\| RT_BIT(22) - reserved
2989	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
2990	//\| RT_BIT(24) - reserved
2991	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
2992	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
2993	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
2994	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
2995	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
2996	//\| RT_BIT(30) - reserved
2997	//\| RT_BIT(31) - reserved
2998	;
2999	pCurLeaf->uEcx &= 0
3000	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3001	;
3002	pCurLeaf->uEdx &= 0;
3003
3004	if (pCpum->u8PortableCpuIdLevel > 0)
3005	{
3006	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
3007	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3008	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3009	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3010	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
3011	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3012	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3013	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3014	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3015	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3016	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3017	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3018	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3019	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3020	}
3021
3022	/* Force standard feature bits. */
3023	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3024	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3025	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3026	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3027	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3028	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3029	break;
3030	}
3031
3032	default:
3033	/* Invalid index, all values are zero. */
3034	pCurLeaf->uEax = 0;
3035	pCurLeaf->uEbx = 0;
3036	pCurLeaf->uEcx = 0;
3037	pCurLeaf->uEdx = 0;
3038	break;
3039	}
3040	uSubLeaf++;
3041	}
3042
3043	/* Cpuid 8: Marked as reserved by Intel and AMD.
3044	* We zero this since we don't know what it may have been used for.
3045	*/
3046	cpumR3CpuIdZeroLeaf(pCpum, 8);
3047
3048	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3049	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3050	* EBX, ECX, EDX - reserved.
3051	* AMD: Reserved
3052	* VIA: ??
3053	*
3054	* We zero this.
3055	*/
3056	cpumR3CpuIdZeroLeaf(pCpum, 9);
3057
3058	/* Cpuid 0xa: Architectural Performance Monitor Features
3059	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3060	* EBX, ECX, EDX - reserved.
3061	* AMD: Reserved
3062	* VIA: ??
3063	*
3064	* We zero this, for now at least.
3065	*/
3066	cpumR3CpuIdZeroLeaf(pCpum, 10);
3067
3068	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3069	* Intel: EAX - APCI ID shift right for next level.
3070	* EBX - Factory configured cores/threads at this level.
3071	* ECX - Level number (same as input) and level type (1,2,0).
3072	* EDX - Extended initial APIC ID.
3073	* AMD: Reserved
3074	* VIA: ??
3075	*/
3076	uSubLeaf = 0;
3077	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3078	{
3079	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3080	{
3081	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3082	if (bLevelType == 1)
3083	{
3084	/* Thread level - we don't do threads at the moment. */
3085	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3086	pCurLeaf->uEbx = 1;
3087	}
3088	else if (bLevelType == 2)
3089	{
3090	/* Core level. */
3091	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3092	#ifdef VBOX_WITH_MULTI_CORE
3093	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3094	pCurLeaf->uEax++;
3095	#endif
3096	pCurLeaf->uEbx = pVM->cCpus;
3097	}
3098	else
3099	{
3100	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3101	pCurLeaf->uEax = 0;
3102	pCurLeaf->uEbx = 0;
3103	pCurLeaf->uEcx = 0;
3104	}
3105	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3106	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3107	}
3108	else
3109	{
3110	pCurLeaf->uEax = 0;
3111	pCurLeaf->uEbx = 0;
3112	pCurLeaf->uEcx = 0;
3113	pCurLeaf->uEdx = 0;
3114	}
3115	uSubLeaf++;
3116	}
3117
3118	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3119	* We zero this since we don't know what it may have been used for.
3120	*/
3121	cpumR3CpuIdZeroLeaf(pCpum, 12);
3122
3123	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3124	* ECX=0: EAX - Valid bits in XCR0[31:0].
3125	* EBX - Maximum state size as per current XCR0 value.
3126	* ECX - Maximum state size for all supported features.
3127	* EDX - Valid bits in XCR0[63:32].
3128	* ECX=1: EAX - Various X-features.
3129	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3130	* ECX - Valid bits in IA32_XSS[31:0].
3131	* EDX - Valid bits in IA32_XSS[63:32].
3132	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3133	* if the bit invalid all four registers are set to zero.
3134	* EAX - The state size for this feature.
3135	* EBX - The state byte offset of this feature.
3136	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3137	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3138	*
3139	* Clear them all as we don't currently implement extended CPU state.
3140	*/
3141	/* Figure out the supported XCR0/XSS mask component. */
3142	uint64_t fGuestXcr0Mask = 0;
3143	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3144	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3145	{
3146	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3147	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3148	fGuestXcr0Mask \|= XSAVE_C_YMM;
3149	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3150	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3151	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3152	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3153	}
3154	pStdFeatureLeaf = NULL;
3155	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3156
3157	/* Work the sub-leaves. */
3158	uint32_t cbXSaveMax = sizeof(X86FXSTATE);
3159	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3160	{
3161	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3162	if (pCurLeaf)
3163	{
3164	if (fGuestXcr0Mask)
3165	{
3166	switch (uSubLeaf)
3167	{
3168	case 0:
3169	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3170	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3171	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3172	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3173	VERR_CPUM_IPE_1);
3174	cbXSaveMax = pCurLeaf->uEcx;
3175	AssertLogRelMsgReturn(cbXSaveMax <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMax >= CPUM_MIN_XSAVE_AREA_SIZE,
3176	("%#x max=%#x\n", cbXSaveMax, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3177	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMax,
3178	("ebx=%#x cbXSaveMax=%#x\n", pCurLeaf->uEbx, cbXSaveMax),
3179	VERR_CPUM_IPE_2);
3180	continue;
3181	case 1:
3182	pCurLeaf->uEax &= 0;
3183	pCurLeaf->uEcx &= 0;
3184	pCurLeaf->uEdx &= 0;
3185	/** @todo what about checking ebx? */
3186	continue;
3187	default:
3188	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3189	{
3190	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMax
3191	&& pCurLeaf->uEax > 0
3192	&& pCurLeaf->uEbx < cbXSaveMax
3193	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3194	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMax,
3195	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3196	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMax),
3197	VERR_CPUM_IPE_2);
3198	AssertLogRel(!(pCurLeaf->uEcx & 1));
3199	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3200	pCurLeaf->uEdx = 0; /* it's reserved... */
3201	continue;
3202	}
3203	break;
3204	}
3205	}
3206
3207	/* Clear the leaf. */
3208	pCurLeaf->uEax = 0;
3209	pCurLeaf->uEbx = 0;
3210	pCurLeaf->uEcx = 0;
3211	pCurLeaf->uEdx = 0;
3212	}
3213	}
3214
3215	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3216	* We zero this since we don't know what it may have been used for.
3217	*/
3218	cpumR3CpuIdZeroLeaf(pCpum, 14);
3219
3220	/* Cpuid 0xf + ECX: Platform qualifity of service monitoring (PQM).
3221	* We zero this as we don't currently virtualize PQM.
3222	*/
3223	cpumR3CpuIdZeroLeaf(pCpum, 15);
3224
3225	/* Cpuid 0x10 + ECX: Platform qualifity of service enforcement (PQE).
3226	* We zero this as we don't currently virtualize PQE.
3227	*/
3228	cpumR3CpuIdZeroLeaf(pCpum, 16);
3229
3230	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3231	* We zero this since we don't know what it may have been used for.
3232	*/
3233	cpumR3CpuIdZeroLeaf(pCpum, 17);
3234
3235	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3236	* We zero this as we don't currently virtualize this.
3237	*/
3238	cpumR3CpuIdZeroLeaf(pCpum, 18);
3239
3240	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3241	* We zero this since we don't know what it may have been used for.
3242	*/
3243	cpumR3CpuIdZeroLeaf(pCpum, 19);
3244
3245	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3246	* We zero this as we don't currently virtualize this.
3247	*/
3248	cpumR3CpuIdZeroLeaf(pCpum, 20);
3249
3250	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3251	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3252	* EAX - denominator (unsigned).
3253	* EBX - numerator (unsigned).
3254	* ECX, EDX - reserved.
3255	* AMD: Reserved / undefined / not implemented.
3256	* VIA: Reserved / undefined / not implemented.
3257	* We zero this as we don't currently virtualize this.
3258	*/
3259	cpumR3CpuIdZeroLeaf(pCpum, 21);
3260
3261	/* Cpuid 0x16: Processor frequency info
3262	* Intel: EAX - Core base frequency in MHz.
3263	* EBX - Core maximum frequency in MHz.
3264	* ECX - Bus (reference) frequency in MHz.
3265	* EDX - Reserved.
3266	* AMD: Reserved / undefined / not implemented.
3267	* VIA: Reserved / undefined / not implemented.
3268	* We zero this as we don't currently virtualize this.
3269	*/
3270	cpumR3CpuIdZeroLeaf(pCpum, 22);
3271
3272	/* Cpuid 0x17..0x10000000: Unknown.
3273	* We don't know these and what they mean, so remove them. */
3274	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3275	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3276
3277
3278	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3279	* We remove all these as we're a hypervisor and must provide our own.
3280	*/
3281	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3282	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3283
3284
3285	/* Cpuid 0x80000000 is harmless. */
3286
3287	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3288
3289	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3290
3291	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3292	* Safe to pass on to the guest.
3293	*
3294	* AMD: 0x800000005 L1 cache information
3295	* 0x800000006 L2/L3 cache information
3296	* Intel: 0x800000005 reserved
3297	* 0x800000006 L2 cache information
3298	* VIA: 0x800000005 TLB and L1 cache information
3299	* 0x800000006 L2 cache information
3300	*/
3301
3302	/* Cpuid 0x800000007: Advanced Power Management Information.
3303	* AMD: EAX: Processor feedback capabilities.
3304	* EBX: RAS capabilites.
3305	* ECX: Advanced power monitoring interface.
3306	* EDX: Enhanced power management capabilities.
3307	* Intel: EAX, EBX, ECX - reserved.
3308	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3309	* VIA: Reserved
3310	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3311	*/
3312	uSubLeaf = 0;
3313	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3314	{
3315	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3316	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3317	{
3318	pCurLeaf->uEdx &= 0
3319	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3320	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3321	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3322	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3323	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3324	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3325	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3326	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3327	#if 0 /*
3328	* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
3329	* Linux kernels blindly assume that the AMD performance counters work
3330	* if this is set for 64 bits guests. (Can't really find a CPUID feature
3331	* bit for them though.)
3332	*/
3333	/** @todo need to recheck this with new MSR emulation. */
3334	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3335	#endif
3336	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3337	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3338	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3339	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3340	\| 0;
3341	}
3342	else
3343	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3344	if (pConfig->fInvariantTsc)
3345	pCurLeaf->uEdx \|= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3346	uSubLeaf++;
3347	}
3348
3349	/* Cpuid 0x80000008:
3350	* AMD: EBX, EDX - reserved
3351	* EAX: Virtual/Physical/Guest address Size
3352	* ECX: Number of cores + APICIdCoreIdSize
3353	* Intel: EAX: Virtual/Physical address Size
3354	* EBX, ECX, EDX - reserved
3355	* VIA: EAX: Virtual/Physical address Size
3356	* EBX, ECX, EDX - reserved
3357	*
3358	* We only expose the virtual+pysical address size to the guest atm.
3359	* On AMD we set the core count, but not the apic id stuff as we're
3360	* currently not doing the apic id assignments in a complatible manner.
3361	*/
3362	uSubLeaf = 0;
3363	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3364	{
3365	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3366	pCurLeaf->uEbx = 0; /* reserved */
3367	pCurLeaf->uEdx = 0; /* reserved */
3368
3369	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3370	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3371	pCurLeaf->uEcx = 0;
3372	#ifdef VBOX_WITH_MULTI_CORE
3373	if ( pVM->cCpus > 1
3374	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3375	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3376	#endif
3377	uSubLeaf++;
3378	}
3379
3380	/* Cpuid 0x80000009: Reserved
3381	* We zero this since we don't know what it may have been used for.
3382	*/
3383	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3384
3385	/* Cpuid 0x8000000a: SVM Information
3386	* AMD: EAX - SVM revision.
3387	* EBX - Number of ASIDs.
3388	* ECX - Reserved.
3389	* EDX - SVM Feature identification.
3390	* We clear all as we currently does not virtualize SVM.
3391	*/
3392	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3393
3394	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3395	* We clear these as we don't know what purpose they might have. */
3396	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3397	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3398
3399	/* Cpuid 0x80000019: TLB configuration
3400	* Seems to be harmless, pass them thru as is. */
3401
3402	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3403	* Strip anything we don't know what is or addresses feature we don't implement. */
3404	uSubLeaf = 0;
3405	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3406	{
3407	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3408	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3409	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3410	;
3411	pCurLeaf->uEbx = 0; /* reserved */
3412	pCurLeaf->uEcx = 0; /* reserved */
3413	pCurLeaf->uEdx = 0; /* reserved */
3414	uSubLeaf++;
3415	}
3416
3417	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3418	* Clear this as we don't currently virtualize this feature. */
3419	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3420
3421	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3422	* Clear this as we don't currently virtualize this feature. */
3423	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3424
3425	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3426	* We need to sanitize the cores per cache (EAX[25:14]).
3427	*
3428	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3429	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3430	* slightly different meaning.
3431	*/
3432	uSubLeaf = 0;
3433	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3434	{
3435	#ifdef VBOX_WITH_MULTI_CORE
3436	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3437	if (cCores > pVM->cCpus)
3438	cCores = pVM->cCpus;
3439	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3440	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3441	#else
3442	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3443	#endif
3444	uSubLeaf++;
3445	}
3446
3447	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3448	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3449	* setup, we have one compute unit with all the cores in it. Single node.
3450	*/
3451	uSubLeaf = 0;
3452	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3453	{
3454	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3455	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3456	{
3457	#ifdef VBOX_WITH_MULTI_CORE
3458	pCurLeaf->uEbx = pVM->cCpus < 0x100
3459	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3460	#else
3461	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3462	#endif
3463	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3464	}
3465	else
3466	{
3467	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3468	pCurLeaf->uEbx = 0; /* Reserved. */
3469	pCurLeaf->uEcx = 0; /* Reserved. */
3470	}
3471	pCurLeaf->uEdx = 0; /* Reserved. */
3472	uSubLeaf++;
3473	}
3474
3475	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3476	* We don't know these and what they mean, so remove them. */
3477	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3478	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3479
3480	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3481	* Just pass it thru for now. */
3482
3483	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3484	* Just pass it thru for now. */
3485
3486	/* Cpuid 0xc0000000: Centaur stuff.
3487	* Harmless, pass it thru. */
3488
3489	/* Cpuid 0xc0000001: Centaur features.
3490	* VIA: EAX - Family, model, stepping.
3491	* EDX - Centaur extended feature flags. Nothing interesting, except may
3492	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3493	* EBX, ECX - reserved.
3494	* We keep EAX but strips the rest.
3495	*/
3496	uSubLeaf = 0;
3497	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3498	{
3499	pCurLeaf->uEbx = 0;
3500	pCurLeaf->uEcx = 0;
3501	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3502	uSubLeaf++;
3503	}
3504
3505	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3506	* We only have fixed stale values, but should be harmless. */
3507
3508	/* Cpuid 0xc0000003: Reserved.
3509	* We zero this since we don't know what it may have been used for.
3510	*/
3511	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3512
3513	/* Cpuid 0xc0000004: Centaur Performance Info.
3514	* We only have fixed stale values, but should be harmless. */
3515
3516
3517	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3518	* We don't know these and what they mean, so remove them. */
3519	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3520	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3521
3522	return VINF_SUCCESS;
3523	#undef PORTABLE_DISABLE_FEATURE_BIT
3524	#undef PORTABLE_CLEAR_BITS_WHEN
3525	}
3526
3527
3528	/**
3529	* Reads a value in /CPUM/IsaExts/ node.
3530	*
3531	* @returns VBox status code (error message raised).
3532	* @param pVM The VM handle (for errors).
3533	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3534	* @param pszValueName The value / extension name.
3535	* @param penmValue Where to return the choice.
3536	* @param enmDefault The default choice.
3537	*/
3538	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3539	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3540	{
3541	/*
3542	* Try integer encoding first.
3543	*/
3544	uint64_t uValue;
3545	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3546	if (RT_SUCCESS(rc))
3547	switch (uValue)
3548	{
3549	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3550	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3551	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3552	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3553	default:
3554	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3555	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3556	pszValueName, uValue);
3557	}
3558	/*
3559	* If missing, use default.
3560	*/
3561	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3562	*penmValue = enmDefault;
3563	else
3564	{
3565	if (rc == VERR_CFGM_NOT_INTEGER)
3566	{
3567	/*
3568	* Not an integer, try read it as a string.
3569	*/
3570	char szValue[32];
3571	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3572	if (RT_SUCCESS(rc))
3573	{
3574	RTStrToLower(szValue);
3575	size_t cchValue = strlen(szValue);
3576	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3577	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3578	*penmValue = CPUMISAEXTCFG_DISABLED;
3579	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3580	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3581	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3582	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3583	else if (EQ("portable"))
3584	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3585	else if (EQ("default") \|\| EQ("def"))
3586	*penmValue = enmDefault;
3587	else
3588	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3589	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3590	pszValueName, uValue);
3591	#undef EQ
3592	}
3593	}
3594	if (RT_FAILURE(rc))
3595	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3596	}
3597	return VINF_SUCCESS;
3598	}
3599
3600
3601	/**
3602	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3603	*
3604	* @returns VBox status code (error message raised).
3605	* @param pVM The VM handle (for errors).
3606	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3607	* @param pszValueName The value / extension name.
3608	* @param penmValue Where to return the choice.
3609	* @param enmDefault The default choice.
3610	* @param fAllowed Allowed choice. Applied both to the result and to
3611	* the default value.
3612	*/
3613	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3614	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3615	{
3616	int rc;
3617	if (fAllowed)
3618	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3619	else
3620	{
3621	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3622	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3623	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3624	*penmValue = CPUMISAEXTCFG_DISABLED;
3625	}
3626	return rc;
3627	}
3628
3629
3630	/**
3631	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3632	*
3633	* @returns VBox status code (error message raised).
3634	* @param pVM The VM handle (for errors).
3635	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3636	* @param pCpumCfg The /CPUM node (can be NULL).
3637	* @param pszValueName The value / extension name.
3638	* @param penmValue Where to return the choice.
3639	* @param enmDefault The default choice.
3640	*/
3641	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3642	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3643	{
3644	if (CFGMR3Exists(pCpumCfg, pszValueName))
3645	{
3646	if (!CFGMR3Exists(pIsaExts, pszValueName))
3647	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3648	else
3649	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3650	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3651	pszValueName, pszValueName);
3652
3653	bool fLegacy;
3654	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3655	if (RT_SUCCESS(rc))
3656	{
3657	*penmValue = fLegacy;
3658	return VINF_SUCCESS;
3659	}
3660	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3661	}
3662
3663	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3664	}
3665
3666
3667	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3668	{
3669	int rc;
3670
3671	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3672	* When non-zero CPUID features that could cause portability issues will be
3673	* stripped. The higher the value the more features gets stripped. Higher
3674	* values should only be used when older CPUs are involved since it may
3675	* harm performance and maybe also cause problems with specific guests. */
3676	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
3677	AssertLogRelRCReturn(rc, rc);
3678
3679	/** @cfgm{/CPUM/GuestCpuName, string}
3680	* The name of the CPU we're to emulate. The default is the host CPU.
3681	* Note! CPUs other than "host" one is currently unsupported. */
3682	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3683	AssertLogRelRCReturn(rc, rc);
3684
3685	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3686	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3687	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3688	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3689	*/
3690	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3691	AssertLogRelRCReturn(rc, rc);
3692
3693	/** @cfgm{/CPUM/InvariantTsc, boolean, complicated}
3694	* Set the invariant TSC flag in 0x80000007 if true, otherwas take default
3695	* action. By default the flag is passed thru as is from the host CPU, except
3696	* on AMD CPUs where it's suppressed to avoid trouble from linux assuming we
3697	* virtualize performance counters.
3698	*/
3699	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, false);
3700	AssertLogRelRCReturn(rc, rc);
3701
3702	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3703	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
3704	* probably going to be a temporary hack, so don't depend on this.
3705	* The 1st byte of the value is the stepping, the 2nd byte value is the model
3706	* number and the 3rd byte value is the family, and the 4th value must be zero.
3707	*/
3708	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3709	AssertLogRelRCReturn(rc, rc);
3710
3711	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3712	* The last standard leaf to keep. The actual last value that is stored in EAX
3713	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3714	* removed. (This works independently of and differently from NT4LeafLimit.)
3715	* The default is usually set to what we're able to reasonably sanitize.
3716	*/
3717	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3718	AssertLogRelRCReturn(rc, rc);
3719
3720	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3721	* The last extended leaf to keep. The actual last value that is stored in EAX
3722	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3723	* leaf are removed. The default is set to what we're able to sanitize.
3724	*/
3725	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3726	AssertLogRelRCReturn(rc, rc);
3727
3728	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3729	* The last extended leaf to keep. The actual last value that is stored in EAX
3730	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3731	* leaf are removed. The default is set to what we're able to sanitize.
3732	*/
3733	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3734	AssertLogRelRCReturn(rc, rc);
3735
3736
3737	/*
3738	* Instruction Set Architecture (ISA) Extensions.
3739	*/
3740	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3741	if (pIsaExts)
3742	{
3743	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3744	"CMPXCHG16B"
3745	"\|MONITOR"
3746	"\|MWaitExtensions"
3747	"\|SSE4.1"
3748	"\|SSE4.2"
3749	"\|XSAVE"
3750	"\|AVX"
3751	"\|AVX2"
3752	"\|AESNI"
3753	"\|PCLMUL"
3754	"\|POPCNT"
3755	"\|MOVBE"
3756	"\|RDRAND"
3757	"\|RDSEED"
3758	"\|CLFLUSHOPT"
3759	"\|ABM"
3760	"\|SSE4A"
3761	"\|MISALNSSE"
3762	"\|3DNOWPRF"
3763	"\|AXMMX"
3764	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
3765	if (RT_FAILURE(rc))
3766	return rc;
3767	}
3768
3769	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
3770	* Expose CMPXCHG16B to the guest if supported by the host. For the time
3771	* being the default is to only do this for VMs with nested paging and AMD-V or
3772	* unrestricted guest mode.
3773	*/
3774	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
3775	AssertLogRelRCReturn(rc, rc);
3776
3777	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
3778	* Expose MONITOR/MWAIT instructions to the guest.
3779	*/
3780	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
3781	AssertLogRelRCReturn(rc, rc);
3782
3783	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
3784	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
3785	* break on interrupt feature (bit 1).
3786	*/
3787	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
3788	AssertLogRelRCReturn(rc, rc);
3789
3790	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
3791	* Expose SSE4.1 to the guest if available.
3792	*/
3793	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
3794	AssertLogRelRCReturn(rc, rc);
3795
3796	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
3797	* Expose SSE4.2 to the guest if available.
3798	*/
3799	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
3800	AssertLogRelRCReturn(rc, rc);
3801
3802	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
3803	&& pVM->cpum.s.HostFeatures.fXSaveRstor
3804	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
3805	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
3806	&& !HMIsLongModeAllowed(pVM)
3807	#endif
3808	;
3809	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
3810
3811	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
3812	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
3813	* default is to only expose this to VMs with nested paging and AMD-V or
3814	* unrestricted guest execution mode. Not possible to force this one without
3815	* host support at the moment.
3816	*/
3817	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
3818	fMayHaveXSave /fAllowed/);
3819	AssertLogRelRCReturn(rc, rc);
3820
3821	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
3822	* Expose the AVX instruction set extensions to the guest if available and
3823	* XSAVE is exposed too. For the time being the default is to only expose this
3824	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3825	*/
3826	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
3827	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3828	AssertLogRelRCReturn(rc, rc);
3829
3830	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
3831	* Expose the AVX2 instruction set extensions to the guest if available and
3832	* XSAVE is exposed too. For the time being the default is to only expose this
3833	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3834	*/
3835	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec && false /* temporarily */,
3836	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3837	AssertLogRelRCReturn(rc, rc);
3838
3839	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
3840	* Whether to expose the AES instructions to the guest. For the time being the
3841	* default is to only do this for VMs with nested paging and AMD-V or
3842	* unrestricted guest mode.
3843	*/
3844	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
3845	AssertLogRelRCReturn(rc, rc);
3846
3847	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
3848	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
3849	* being the default is to only do this for VMs with nested paging and AMD-V or
3850	* unrestricted guest mode.
3851	*/
3852	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
3853	AssertLogRelRCReturn(rc, rc);
3854
3855	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
3856	* Whether to expose the POPCNT instructions to the guest. For the time
3857	* being the default is to only do this for VMs with nested paging and AMD-V or
3858	* unrestricted guest mode.
3859	*/
3860	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
3861	AssertLogRelRCReturn(rc, rc);
3862
3863	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
3864	* Whether to expose the MOVBE instructions to the guest. For the time
3865	* being the default is to only do this for VMs with nested paging and AMD-V or
3866	* unrestricted guest mode.
3867	*/
3868	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
3869	AssertLogRelRCReturn(rc, rc);
3870
3871	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
3872	* Whether to expose the RDRAND instructions to the guest. For the time being
3873	* the default is to only do this for VMs with nested paging and AMD-V or
3874	* unrestricted guest mode.
3875	*/
3876	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
3877	AssertLogRelRCReturn(rc, rc);
3878
3879	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
3880	* Whether to expose the RDSEED instructions to the guest. For the time being
3881	* the default is to only do this for VMs with nested paging and AMD-V or
3882	* unrestricted guest mode.
3883	*/
3884	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
3885	AssertLogRelRCReturn(rc, rc);
3886
3887	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
3888	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
3889	* being the default is to only do this for VMs with nested paging and AMD-V or
3890	* unrestricted guest mode.
3891	*/
3892	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
3893	AssertLogRelRCReturn(rc, rc);
3894
3895
3896	/* AMD: */
3897
3898	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
3899	* Whether to expose the AMD ABM instructions to the guest. For the time
3900	* being the default is to only do this for VMs with nested paging and AMD-V or
3901	* unrestricted guest mode.
3902	*/
3903	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
3904	AssertLogRelRCReturn(rc, rc);
3905
3906	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
3907	* Whether to expose the AMD SSE4A instructions to the guest. For the time
3908	* being the default is to only do this for VMs with nested paging and AMD-V or
3909	* unrestricted guest mode.
3910	*/
3911	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
3912	AssertLogRelRCReturn(rc, rc);
3913
3914	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
3915	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
3916	* the time being the default is to only do this for VMs with nested paging and
3917	* AMD-V or unrestricted guest mode.
3918	*/
3919	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
3920	AssertLogRelRCReturn(rc, rc);
3921
3922	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
3923	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
3924	* For the time being the default is to only do this for VMs with nested paging
3925	* and AMD-V or unrestricted guest mode.
3926	*/
3927	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
3928	AssertLogRelRCReturn(rc, rc);
3929
3930	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
3931	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
3932	* the default is to only do this for VMs with nested paging and AMD-V or
3933	* unrestricted guest mode.
3934	*/
3935	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
3936	AssertLogRelRCReturn(rc, rc);
3937
3938	return VINF_SUCCESS;
3939	}
3940
3941
3942	/**
3943	* Initializes the emulated CPU's CPUID & MSR information.
3944	*
3945	* @returns VBox status code.
3946	* @param pVM Pointer to the VM.
3947	*/
3948	int cpumR3InitCpuIdAndMsrs(PVM pVM)
3949	{
3950	PCPUM pCpum = &pVM->cpum.s;
3951	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
3952
3953	/*
3954	* Read the configuration.
3955	*/
3956	CPUMCPUIDCONFIG Config;
3957	RT_ZERO(Config);
3958
3959	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
3960	AssertRCReturn(rc, rc);
3961
3962	/*
3963	* Get the guest CPU data from the database and/or the host.
3964	*
3965	* The CPUID and MSRs are currently living on the regular heap to avoid
3966	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
3967	* API for the hyper heap). This means special cleanup considerations.
3968	*/
3969	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
3970	if (RT_FAILURE(rc))
3971	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
3972	? VMSetError(pVM, rc, RT_SRC_POS,
3973	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
3974	: rc;
3975
3976	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
3977	* Overrides the guest MSRs.
3978	*/
3979	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
3980
3981	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
3982	* Overrides the CPUID leaf values (from the host CPU usually) used for
3983	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
3984	* values when moving a VM to a different machine. Another use is restricting
3985	* (or extending) the feature set exposed to the guest. */
3986	if (RT_SUCCESS(rc))
3987	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
3988
3989	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
3990	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
3991	"Found unsupported configuration node '/CPUM/CPUID/'. "
3992	"Please use IMachine::setCPUIDLeaf() instead.");
3993
3994	/*
3995	* Pre-explode the CPUID info.
3996	*/
3997	if (RT_SUCCESS(rc))
3998	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
3999
4000	/*
4001	* Sanitize the cpuid information passed on to the guest.
4002	*/
4003	if (RT_SUCCESS(rc))
4004	{
4005	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4006	if (RT_SUCCESS(rc))
4007	{
4008	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4009	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4010	}
4011	}
4012
4013	/*
4014	* Plant our own hypervisor CPUID leaves.
4015	*/
4016	if (RT_SUCCESS(rc))
4017	rc = cpumR3CpuIdPlantHypervisorLeaves(pCpum, &Config);
4018
4019	/*
4020	* MSR fudging.
4021	*/
4022	if (RT_SUCCESS(rc))
4023	{
4024	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4025	* Fudges some common MSRs if not present in the selected CPU database entry.
4026	* This is for trying to keep VMs running when moved between different hosts
4027	* and different CPU vendors. */
4028	bool fEnable;
4029	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4030	if (RT_SUCCESS(rc) && fEnable)
4031	{
4032	rc = cpumR3MsrApplyFudge(pVM);
4033	AssertLogRelRC(rc);
4034	}
4035	}
4036	if (RT_SUCCESS(rc))
4037	{
4038	/*
4039	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4040	* guest CPU features again.
4041	*/
4042	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4043	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4044	pCpum->GuestInfo.cCpuIdLeaves);
4045	RTMemFree(pvFree);
4046
4047	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4048	int rc2 = MMHyperDupMem(pVM, pvFree,
4049	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4050	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4051	RTMemFree(pvFree);
4052	AssertLogRelRCReturn(rc1, rc1);
4053	AssertLogRelRCReturn(rc2, rc2);
4054
4055	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4056	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4057
4058
4059	/*
4060	* Some more configuration that we're applying at the end of everything
4061	* via the CPUMSetGuestCpuIdFeature API.
4062	*/
4063
4064	/* Check if PAE was explicitely enabled by the user. */
4065	bool fEnable;
4066	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4067	AssertRCReturn(rc, rc);
4068	if (fEnable)
4069	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4070
4071	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4072	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4073	AssertRCReturn(rc, rc);
4074	if (fEnable)
4075	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4076
4077	/* We don't enable the Hypervisor Present bit by default, but it may be needed by some guests. */
4078	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false);
4079	AssertRCReturn(rc, rc);
4080	if (fEnable)
4081	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
4082
4083	return VINF_SUCCESS;
4084	}
4085
4086	/*
4087	* Failed before switching to hyper heap.
4088	*/
4089	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4090	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4091	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4092	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4093	return rc;
4094	}
4095
4096
4097
4098	/*
4099	*
4100	*
4101	* Saved state related code.
4102	* Saved state related code.
4103	* Saved state related code.
4104	*
4105	*
4106	*/
4107
4108	/**
4109	* Called both in pass 0 and the final pass.
4110	*
4111	* @param pVM Pointer to the VM.
4112	* @param pSSM The saved state handle.
4113	*/
4114	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4115	{
4116	/*
4117	* Save all the CPU ID leaves.
4118	*/
4119	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4120	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4121	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4122	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4123
4124	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4125
4126	/*
4127	* Save a good portion of the raw CPU IDs as well as they may come in
4128	* handy when validating features for raw mode.
4129	*/
4130	CPUMCPUID aRawStd[16];
4131	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4132	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4133	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4134	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4135
4136	CPUMCPUID aRawExt[32];
4137	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4138	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4139	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4140	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4141	}
4142
4143
4144	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4145	{
4146	uint32_t cCpuIds;
4147	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4148	if (RT_SUCCESS(rc))
4149	{
4150	if (cCpuIds < 64)
4151	{
4152	for (uint32_t i = 0; i < cCpuIds; i++)
4153	{
4154	CPUMCPUID CpuId;
4155	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4156	if (RT_FAILURE(rc))
4157	break;
4158
4159	CPUMCPUIDLEAF NewLeaf;
4160	NewLeaf.uLeaf = uBase + i;
4161	NewLeaf.uSubLeaf = 0;
4162	NewLeaf.fSubLeafMask = 0;
4163	NewLeaf.uEax = CpuId.uEax;
4164	NewLeaf.uEbx = CpuId.uEbx;
4165	NewLeaf.uEcx = CpuId.uEcx;
4166	NewLeaf.uEdx = CpuId.uEdx;
4167	NewLeaf.fFlags = 0;
4168	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4169	}
4170	}
4171	else
4172	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4173	}
4174	if (RT_FAILURE(rc))
4175	{
4176	RTMemFree(*ppaLeaves);
4177	*ppaLeaves = NULL;
4178	*pcLeaves = 0;
4179	}
4180	return rc;
4181	}
4182
4183
4184	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4185	{
4186	*ppaLeaves = NULL;
4187	*pcLeaves = 0;
4188
4189	int rc;
4190	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4191	{
4192	/*
4193	* The new format. Starts by declaring the leave size and count.
4194	*/
4195	uint32_t cbLeaf;
4196	SSMR3GetU32(pSSM, &cbLeaf);
4197	uint32_t cLeaves;
4198	rc = SSMR3GetU32(pSSM, &cLeaves);
4199	if (RT_SUCCESS(rc))
4200	{
4201	if (cbLeaf == sizeof(**ppaLeaves))
4202	{
4203	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4204	{
4205	/*
4206	* Load the leaves one by one.
4207	*
4208	* The uPrev stuff is a kludge for working around a week worth of bad saved
4209	* states during the CPUID revamp in March 2015. We saved too many leaves
4210	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4211	* garbage entires at the end of the array when restoring. We also had
4212	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
4213	* this kludge doesn't deal correctly with that, but who cares...
4214	*/
4215	uint32_t uPrev = 0;
4216	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4217	{
4218	CPUMCPUIDLEAF Leaf;
4219	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
4220	if (RT_SUCCESS(rc))
4221	{
4222	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
4223	\|\| Leaf.uLeaf >= uPrev)
4224	{
4225	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4226	uPrev = Leaf.uLeaf;
4227	}
4228	else
4229	uPrev = UINT32_MAX;
4230	}
4231	}
4232	}
4233	else
4234	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
4235	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
4236	}
4237	else
4238	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
4239	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
4240	}
4241	}
4242	else
4243	{
4244	/*
4245	* The old format with its three inflexible arrays.
4246	*/
4247	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
4248	if (RT_SUCCESS(rc))
4249	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
4250	if (RT_SUCCESS(rc))
4251	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
4252	if (RT_SUCCESS(rc))
4253	{
4254	/*
4255	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
4256	*/
4257	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
4258	if ( pLeaf
4259	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
4260	{
4261	CPUMCPUIDLEAF Leaf;
4262	Leaf.uLeaf = 4;
4263	Leaf.fSubLeafMask = UINT32_MAX;
4264	Leaf.uSubLeaf = 0;
4265	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
4266	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
4267	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
4268	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
4269	\| UINT32_C(63); /* system coherency line size - 1 */
4270	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
4271	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
4272	\| (UINT32_C(1) << 5) /* cache level */
4273	\| UINT32_C(1); /* cache type (data) */
4274	Leaf.fFlags = 0;
4275	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4276	if (RT_SUCCESS(rc))
4277	{
4278	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
4279	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4280	}
4281	if (RT_SUCCESS(rc))
4282	{
4283	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
4284	Leaf.uEcx = 4095; /* sets - 1 */
4285	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
4286	Leaf.uEbx \|= UINT32_C(23) << 22;
4287	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
4288	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
4289	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
4290	Leaf.uEax \|= UINT32_C(2) << 5;
4291	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4292	}
4293	}
4294	}
4295	}
4296	return rc;
4297	}
4298
4299
4300	/**
4301	* Loads the CPU ID leaves saved by pass 0, inner worker.
4302	*
4303	* @returns VBox status code.
4304	* @param pVM Pointer to the VM.
4305	* @param pSSM The saved state handle.
4306	* @param uVersion The format version.
4307	* @param paLeaves Guest CPUID leaves loaded from the state.
4308	* @param cLeaves The number of leaves in @a paLeaves.
4309	*/
4310	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
4311	{
4312	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4313
4314	/*
4315	* Continue loading the state into stack buffers.
4316	*/
4317	CPUMCPUID GuestDefCpuId;
4318	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
4319	AssertRCReturn(rc, rc);
4320
4321	CPUMCPUID aRawStd[16];
4322	uint32_t cRawStd;
4323	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
4324	if (cRawStd > RT_ELEMENTS(aRawStd))
4325	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4326	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
4327	AssertRCReturn(rc, rc);
4328	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
4329	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4330
4331	CPUMCPUID aRawExt[32];
4332	uint32_t cRawExt;
4333	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
4334	if (cRawExt > RT_ELEMENTS(aRawExt))
4335	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4336	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
4337	AssertRCReturn(rc, rc);
4338	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
4339	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4340
4341	/*
4342	* Get the raw CPU IDs for the current host.
4343	*/
4344	CPUMCPUID aHostRawStd[16];
4345	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
4346	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
4347
4348	CPUMCPUID aHostRawExt[32];
4349	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
4350	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
4351	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4352
4353	/*
4354	* Get the host and guest overrides so we don't reject the state because
4355	* some feature was enabled thru these interfaces.
4356	* Note! We currently only need the feature leaves, so skip rest.
4357	*/
4358	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4359	CPUMCPUID aHostOverrideStd[2];
4360	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4361	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4362
4363	CPUMCPUID aHostOverrideExt[2];
4364	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4365	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4366
4367	/*
4368	* This can be skipped.
4369	*/
4370	bool fStrictCpuIdChecks;
4371	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
4372
4373	/*
4374	* Define a bunch of macros for simplifying the santizing/checking code below.
4375	*/
4376	/* Generic expression + failure message. */
4377	#define CPUID_CHECK_RET(expr, fmt) \
4378	do { \
4379	if (!(expr)) \
4380	{ \
4381	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
4382	if (fStrictCpuIdChecks) \
4383	{ \
4384	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4385	RTStrFree(pszMsg); \
4386	return rcCpuid; \
4387	} \
4388	LogRel(("CPUM: %s\n", pszMsg)); \
4389	RTStrFree(pszMsg); \
4390	} \
4391	} while (0)
4392	#define CPUID_CHECK_WRN(expr, fmt) \
4393	do { \
4394	if (!(expr)) \
4395	LogRel(fmt); \
4396	} while (0)
4397
4398	/* For comparing two values and bitch if they differs. */
4399	#define CPUID_CHECK2_RET(what, host, saved) \
4400	do { \
4401	if ((host) != (saved)) \
4402	{ \
4403	if (fStrictCpuIdChecks) \
4404	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4405	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
4406	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4407	} \
4408	} while (0)
4409	#define CPUID_CHECK2_WRN(what, host, saved) \
4410	do { \
4411	if ((host) != (saved)) \
4412	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4413	} while (0)
4414
4415	/* For checking raw cpu features (raw mode). */
4416	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
4417	do { \
4418	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4419	{ \
4420	if (fStrictCpuIdChecks) \
4421	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4422	N_(#bit " mismatch: host=%d saved=%d"), \
4423	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
4424	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4425	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4426	} \
4427	} while (0)
4428	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
4429	do { \
4430	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4431	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4432	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4433	} while (0)
4434	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
4435
4436	/* For checking guest features. */
4437	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
4438	do { \
4439	if ( (aGuestCpuId##set [1].reg & bit) \
4440	&& !(aHostRaw##set [1].reg & bit) \
4441	&& !(aHostOverride##set [1].reg & bit) \
4442	) \
4443	{ \
4444	if (fStrictCpuIdChecks) \
4445	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4446	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4447	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4448	} \
4449	} while (0)
4450	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
4451	do { \
4452	if ( (aGuestCpuId##set [1].reg & bit) \
4453	&& !(aHostRaw##set [1].reg & bit) \
4454	&& !(aHostOverride##set [1].reg & bit) \
4455	) \
4456	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4457	} while (0)
4458	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
4459	do { \
4460	if ( (aGuestCpuId##set [1].reg & bit) \
4461	&& !(aHostRaw##set [1].reg & bit) \
4462	&& !(aHostOverride##set [1].reg & bit) \
4463	) \
4464	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4465	} while (0)
4466	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
4467
4468	/* For checking guest features if AMD guest CPU. */
4469	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
4470	do { \
4471	if ( (aGuestCpuId##set [1].reg & bit) \
4472	&& fGuestAmd \
4473	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4474	&& !(aHostOverride##set [1].reg & bit) \
4475	) \
4476	{ \
4477	if (fStrictCpuIdChecks) \
4478	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4479	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4480	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4481	} \
4482	} while (0)
4483	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
4484	do { \
4485	if ( (aGuestCpuId##set [1].reg & bit) \
4486	&& fGuestAmd \
4487	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4488	&& !(aHostOverride##set [1].reg & bit) \
4489	) \
4490	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4491	} while (0)
4492	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
4493	do { \
4494	if ( (aGuestCpuId##set [1].reg & bit) \
4495	&& fGuestAmd \
4496	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4497	&& !(aHostOverride##set [1].reg & bit) \
4498	) \
4499	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4500	} while (0)
4501	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
4502
4503	/* For checking AMD features which have a corresponding bit in the standard
4504	range. (Intel defines very few bits in the extended feature sets.) */
4505	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
4506	do { \
4507	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4508	&& !(fHostAmd \
4509	? aHostRawExt[1].reg & (ExtBit) \
4510	: aHostRawStd[1].reg & (StdBit)) \
4511	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4512	) \
4513	{ \
4514	if (fStrictCpuIdChecks) \
4515	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4516	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
4517	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4518	} \
4519	} while (0)
4520	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
4521	do { \
4522	if ( (aGuestCpuId[1].reg & (ExtBit)) \
4523	&& !(fHostAmd \
4524	? aHostRawExt[1].reg & (ExtBit) \
4525	: aHostRawStd[1].reg & (StdBit)) \
4526	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4527	) \
4528	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4529	} while (0)
4530	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
4531	do { \
4532	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4533	&& !(fHostAmd \
4534	? aHostRawExt[1].reg & (ExtBit) \
4535	: aHostRawStd[1].reg & (StdBit)) \
4536	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4537	) \
4538	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4539	} while (0)
4540	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
4541
4542	/*
4543	* For raw-mode we'll require that the CPUs are very similar since we don't
4544	* intercept CPUID instructions for user mode applications.
4545	*/
4546	if (!HMIsEnabled(pVM))
4547	{
4548	/* CPUID(0) */
4549	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
4550	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
4551	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
4552	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
4553	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
4554	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
4555	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
4556	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
4557	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
4558
4559	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
4560
4561	/* CPUID(1).eax */
4562	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
4563	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
4564	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
4565
4566	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
4567	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
4568	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
4569
4570	/* CPUID(1).ecx */
4571	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
4572	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
4573	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
4574	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4575	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
4576	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
4577	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
4578	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
4579	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
4580	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
4581	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
4582	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
4583	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
4584	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
4585	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
4586	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
4587	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
4588	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4589	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
4590	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
4591	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
4592	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4593	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
4594	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
4595	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4596	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
4597	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
4598	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4599	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
4600	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4601	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4602	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
4603
4604	/* CPUID(1).edx */
4605	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4606	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4607	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
4608	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4609	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
4610	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
4611	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4612	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4613	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
4614	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4615	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
4616	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4617	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4618	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4619	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4620	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
4621	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4622	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4623	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4624	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
4625	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
4626	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
4627	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
4628	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
4629	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
4630	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
4631	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
4632	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
4633	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
4634	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
4635	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
4636	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
4637
4638	/* CPUID(2) - config, mostly about caches. ignore. */
4639	/* CPUID(3) - processor serial number. ignore. */
4640	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
4641	/* CPUID(5) - mwait/monitor config. ignore. */
4642	/* CPUID(6) - power management. ignore. */
4643	/* CPUID(7) - ???. ignore. */
4644	/* CPUID(8) - ???. ignore. */
4645	/* CPUID(9) - DCA. ignore for now. */
4646	/* CPUID(a) - PeMo info. ignore for now. */
4647	/* CPUID(b) - topology info - takes ECX as input. ignore. */
4648
4649	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
4650	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
4651	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
4652	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
4653	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
4654	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
4655	{
4656	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
4657	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
4658	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
4659	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
4660	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
4661	}
4662
4663	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
4664	Note! Intel have/is marking many of the fields here as reserved. We
4665	will verify them as if it's an AMD CPU. */
4666	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
4667	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
4668	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
4669	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
4670	{
4671	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
4672	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
4673	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
4674	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
4675	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
4676	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
4677	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
4678
4679	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
4680	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
4681	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
4682	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
4683	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
4684	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
4685
4686	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
4687	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
4688	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
4689	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
4690
4691	/* CPUID(0x80000001).ecx */
4692	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
4693	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
4694	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
4695	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
4696	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
4697	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
4698	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
4699	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
4700	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
4701	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
4702	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
4703	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
4704	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
4705	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
4706	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4707	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4708	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4709	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4710	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4711	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4712	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4713	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4714	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4715	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4716	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4717	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4718	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4719	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4720	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4721	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4722	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4723	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4724
4725	/* CPUID(0x80000001).edx */
4726	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
4727	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
4728	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
4729	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
4730	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
4731	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
4732	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
4733	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
4734	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
4735	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
4736	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4737	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
4738	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
4739	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
4740	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
4741	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
4742	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
4743	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
4744	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4745	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4746	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4747	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
4748	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4749	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
4750	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
4751	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4752	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4753	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4754	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
4755	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4756	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4757	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4758
4759	/** @todo verify the rest as well. */
4760	}
4761	}
4762
4763
4764
4765	/*
4766	* Verify that we can support the features already exposed to the guest on
4767	* this host.
4768	*
4769	* Most of the features we're emulating requires intercepting instruction
4770	* and doing it the slow way, so there is no need to warn when they aren't
4771	* present in the host CPU. Thus we use IGN instead of EMU on these.
4772	*
4773	* Trailing comments:
4774	* "EMU" - Possible to emulate, could be lots of work and very slow.
4775	* "EMU?" - Can this be emulated?
4776	*/
4777	CPUMCPUID aGuestCpuIdStd[2];
4778	RT_ZERO(aGuestCpuIdStd);
4779	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
4780
4781	/* CPUID(1).ecx */
4782	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
4783	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
4784	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
4785	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4786	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
4787	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
4788	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
4789	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
4790	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
4791	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
4792	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
4793	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
4794	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
4795	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
4796	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
4797	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
4798	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
4799	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4800	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
4801	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
4802	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
4803	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4804	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
4805	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
4806	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4807	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
4808	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
4809	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4810	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
4811	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4812	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4813	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
4814
4815	/* CPUID(1).edx */
4816	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4817	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4818	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
4819	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4820	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4821	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4822	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4823	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4824	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4825	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4826	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
4827	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4828	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4829	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4830	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4831	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4832	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4833	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4834	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4835	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
4836	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
4837	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
4838	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
4839	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4840	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4841	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
4842	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
4843	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
4844	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
4845	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
4846	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
4847	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
4848
4849	/* CPUID(0x80000000). */
4850	CPUMCPUID aGuestCpuIdExt[2];
4851	RT_ZERO(aGuestCpuIdExt);
4852	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
4853	{
4854	/** @todo deal with no 0x80000001 on the host. */
4855	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
4856	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
4857
4858	/* CPUID(0x80000001).ecx */
4859	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
4860	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
4861	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
4862	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
4863	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
4864	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
4865	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
4866	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
4867	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
4868	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
4869	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
4870	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
4871	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
4872	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
4873	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4874	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4875	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4876	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4877	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4878	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4879	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4880	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4881	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4882	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4883	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4884	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4885	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4886	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4887	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4888	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4889	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4890	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4891
4892	/* CPUID(0x80000001).edx */
4893	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
4894	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
4895	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
4896	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
4897	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4898	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4899	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
4900	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
4901	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4902	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
4903	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4904	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
4905	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
4906	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
4907	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
4908	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4909	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
4910	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
4911	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4912	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4913	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4914	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
4915	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4916	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4917	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4918	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4919	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4920	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4921	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
4922	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4923	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4924	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4925	}
4926
4927	/** @todo check leaf 7 */
4928
4929	/* CPUID(d) - XCR0 stuff - takes ECX as input.
4930	* ECX=0: EAX - Valid bits in XCR0[31:0].
4931	* EBX - Maximum state size as per current XCR0 value.
4932	* ECX - Maximum state size for all supported features.
4933	* EDX - Valid bits in XCR0[63:32].
4934	* ECX=1: EAX - Various X-features.
4935	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
4936	* ECX - Valid bits in IA32_XSS[31:0].
4937	* EDX - Valid bits in IA32_XSS[63:32].
4938	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
4939	* if the bit invalid all four registers are set to zero.
4940	* EAX - The state size for this feature.
4941	* EBX - The state byte offset of this feature.
4942	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
4943	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
4944	*/
4945	uint64_t fGuestXcr0Mask = 0;
4946	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
4947	if ( pCurLeaf
4948	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
4949	&& ( pCurLeaf->uEax
4950	\|\| pCurLeaf->uEbx
4951	\|\| pCurLeaf->uEcx
4952	\|\| pCurLeaf->uEdx) )
4953	{
4954	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
4955	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
4956	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4957	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
4958	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
4959	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
4960	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4961	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
4962
4963	/* We don't support any additional features yet. */
4964	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
4965	if (pCurLeaf && pCurLeaf->uEax)
4966	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4967	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
4968	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
4969	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4970	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
4971	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
4972
4973
4974	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
4975	{
4976	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4977	if (pCurLeaf)
4978	{
4979	/* If advertised, the state component offset and size must match the one used by host. */
4980	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
4981	{
4982	CPUMCPUID RawHost;
4983	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
4984	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
4985	if ( RawHost.uEbx != pCurLeaf->uEbx
4986	\|\| RawHost.uEax != pCurLeaf->uEax)
4987	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4988	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
4989	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
4990	}
4991	}
4992	}
4993	}
4994	/* Clear leaf 0xd just in case we're loading an old state... */
4995	else if (pCurLeaf)
4996	{
4997	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
4998	{
4999	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5000	if (pCurLeaf)
5001	{
5002	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5003	\|\| ( pCurLeaf->uEax == 0
5004	&& pCurLeaf->uEbx == 0
5005	&& pCurLeaf->uEcx == 0
5006	&& pCurLeaf->uEdx == 0),
5007	("uVersion=%#x; %#x %#x %#x %#x\n",
5008	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5009	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5010	}
5011	}
5012	}
5013
5014	/* Update the fXStateGuestMask value for the VM. */
5015	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5016	{
5017	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5018	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5019	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5020	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5021	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5022	}
5023
5024	#undef CPUID_CHECK_RET
5025	#undef CPUID_CHECK_WRN
5026	#undef CPUID_CHECK2_RET
5027	#undef CPUID_CHECK2_WRN
5028	#undef CPUID_RAW_FEATURE_RET
5029	#undef CPUID_RAW_FEATURE_WRN
5030	#undef CPUID_RAW_FEATURE_IGN
5031	#undef CPUID_GST_FEATURE_RET
5032	#undef CPUID_GST_FEATURE_WRN
5033	#undef CPUID_GST_FEATURE_EMU
5034	#undef CPUID_GST_FEATURE_IGN
5035	#undef CPUID_GST_FEATURE2_RET
5036	#undef CPUID_GST_FEATURE2_WRN
5037	#undef CPUID_GST_FEATURE2_EMU
5038	#undef CPUID_GST_FEATURE2_IGN
5039	#undef CPUID_GST_AMD_FEATURE_RET
5040	#undef CPUID_GST_AMD_FEATURE_WRN
5041	#undef CPUID_GST_AMD_FEATURE_EMU
5042	#undef CPUID_GST_AMD_FEATURE_IGN
5043
5044	/*
5045	* We're good, commit the CPU ID leaves.
5046	*/
5047	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5048	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5049	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5050	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
5051	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5052	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
5053	AssertLogRelRCReturn(rc, rc);
5054
5055	return VINF_SUCCESS;
5056	}
5057
5058
5059	/**
5060	* Loads the CPU ID leaves saved by pass 0.
5061	*
5062	* @returns VBox status code.
5063	* @param pVM Pointer to the VM.
5064	* @param pSSM The saved state handle.
5065	* @param uVersion The format version.
5066	*/
5067	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5068	{
5069	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5070
5071	/*
5072	* Load the CPUID leaves array first and call worker to do the rest, just so
5073	* we can free the memory when we need to without ending up in column 1000.
5074	*/
5075	PCPUMCPUIDLEAF paLeaves;
5076	uint32_t cLeaves;
5077	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5078	AssertRC(rc);
5079	if (RT_SUCCESS(rc))
5080	{
5081	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
5082	RTMemFree(paLeaves);
5083	}
5084	return rc;
5085	}
5086
5087
5088
5089	/**
5090	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5091	*
5092	* @returns VBox status code.
5093	* @param pVM Pointer to the VM.
5094	* @param pSSM The saved state handle.
5095	* @param uVersion The format version.
5096	*/
5097	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5098	{
5099	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5100
5101	/*
5102	* Restore the CPUID leaves.
5103	*
5104	* Note that we support restoring less than the current amount of standard
5105	* leaves because we've been allowed more is newer version of VBox.
5106	*/
5107	uint32_t cElements;
5108	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5109	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5110	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5111	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5112
5113	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5114	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5115	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5116	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5117
5118	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5119	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5120	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5121	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5122
5123	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5124
5125	/*
5126	* Check that the basic cpuid id information is unchanged.
5127	*/
5128	/** @todo we should check the 64 bits capabilities too! */
5129	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5130	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5131	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5132	uint32_t au32CpuIdSaved[8];
5133	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5134	if (RT_SUCCESS(rc))
5135	{
5136	/* Ignore CPU stepping. */
5137	au32CpuId[4] &= 0xfffffff0;
5138	au32CpuIdSaved[4] &= 0xfffffff0;
5139
5140	/* Ignore APIC ID (AMD specs). */
5141	au32CpuId[5] &= ~0xff000000;
5142	au32CpuIdSaved[5] &= ~0xff000000;
5143
5144	/* Ignore the number of Logical CPUs (AMD specs). */
5145	au32CpuId[5] &= ~0x00ff0000;
5146	au32CpuIdSaved[5] &= ~0x00ff0000;
5147
5148	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5149	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5150	\| X86_CPUID_FEATURE_ECX_VMX
5151	\| X86_CPUID_FEATURE_ECX_SMX
5152	\| X86_CPUID_FEATURE_ECX_EST
5153	\| X86_CPUID_FEATURE_ECX_TM2
5154	\| X86_CPUID_FEATURE_ECX_CNTXID
5155	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5156	\| X86_CPUID_FEATURE_ECX_PDCM
5157	\| X86_CPUID_FEATURE_ECX_DCA
5158	\| X86_CPUID_FEATURE_ECX_X2APIC
5159	);
5160	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5161	\| X86_CPUID_FEATURE_ECX_VMX
5162	\| X86_CPUID_FEATURE_ECX_SMX
5163	\| X86_CPUID_FEATURE_ECX_EST
5164	\| X86_CPUID_FEATURE_ECX_TM2
5165	\| X86_CPUID_FEATURE_ECX_CNTXID
5166	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5167	\| X86_CPUID_FEATURE_ECX_PDCM
5168	\| X86_CPUID_FEATURE_ECX_DCA
5169	\| X86_CPUID_FEATURE_ECX_X2APIC
5170	);
5171
5172	/* Make sure we don't forget to update the masks when enabling
5173	* features in the future.
5174	*/
5175	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5176	( X86_CPUID_FEATURE_ECX_DTES64
5177	\| X86_CPUID_FEATURE_ECX_VMX
5178	\| X86_CPUID_FEATURE_ECX_SMX
5179	\| X86_CPUID_FEATURE_ECX_EST
5180	\| X86_CPUID_FEATURE_ECX_TM2
5181	\| X86_CPUID_FEATURE_ECX_CNTXID
5182	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5183	\| X86_CPUID_FEATURE_ECX_PDCM
5184	\| X86_CPUID_FEATURE_ECX_DCA
5185	\| X86_CPUID_FEATURE_ECX_X2APIC
5186	)));
5187	/* do the compare */
5188	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5189	{
5190	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5191	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5192	"Saved=%.*Rhxs\n"
5193	"Real =%.*Rhxs\n",
5194	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5195	sizeof(au32CpuId), au32CpuId));
5196	else
5197	{
5198	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5199	"Saved=%.*Rhxs\n"
5200	"Real =%.*Rhxs\n",
5201	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5202	sizeof(au32CpuId), au32CpuId));
5203	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5204	}
5205	}
5206	}
5207
5208	return rc;
5209	}
5210
5211
5212
5213	/*
5214	*
5215	*
5216	* CPUID Info Handler.
5217	* CPUID Info Handler.
5218	* CPUID Info Handler.
5219	*
5220	*
5221	*/
5222
5223
5224
5225	/**
5226	* Get L1 cache / TLS associativity.
5227	*/
5228	static const char getCacheAss(unsigned u, char pszBuf)
5229	{
5230	if (u == 0)
5231	return "res0 ";
5232	if (u == 1)
5233	return "direct";
5234	if (u == 255)
5235	return "fully";
5236	if (u >= 256)
5237	return "???";
5238
5239	RTStrPrintf(pszBuf, 16, "%d way", u);
5240	return pszBuf;
5241	}
5242
5243
5244	/**
5245	* Get L2 cache associativity.
5246	*/
5247	const char *getL2CacheAss(unsigned u)
5248	{
5249	switch (u)
5250	{
5251	case 0: return "off ";
5252	case 1: return "direct";
5253	case 2: return "2 way ";
5254	case 3: return "res3 ";
5255	case 4: return "4 way ";
5256	case 5: return "res5 ";
5257	case 6: return "8 way ";
5258	case 7: return "res7 ";
5259	case 8: return "16 way";
5260	case 9: return "res9 ";
5261	case 10: return "res10 ";
5262	case 11: return "res11 ";
5263	case 12: return "res12 ";
5264	case 13: return "res13 ";
5265	case 14: return "res14 ";
5266	case 15: return "fully ";
5267	default: return "????";
5268	}
5269	}
5270
5271
5272	/** CPUID(1).EDX field descriptions. */
5273	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
5274	{
5275	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5276	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5277	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5278	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5279	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5280	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
5281	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5282	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5283	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5284	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5285	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
5286	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5287	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5288	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5289	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5290	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5291	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5292	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
5293	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
5294	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
5295	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
5296	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5297	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
5298	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
5299	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
5300	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
5301	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
5302	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
5303	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
5304	DBGFREGSUBFIELD_TERMINATOR()
5305	};
5306
5307	/** CPUID(1).ECX field descriptions. */
5308	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
5309	{
5310	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
5311	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
5312	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
5313	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
5314	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
5315	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
5316	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
5317	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
5318	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
5319	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
5320	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
5321	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
5322	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
5323	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
5324	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
5325	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
5326	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
5327	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
5328	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
5329	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
5330	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
5331	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
5332	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
5333	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
5334	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
5335	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
5336	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
5337	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
5338	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
5339	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
5340	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
5341	DBGFREGSUBFIELD_TERMINATOR()
5342	};
5343
5344	/** CPUID(7,0).EBX field descriptions. */
5345	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
5346	{
5347	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
5348	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
5349	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
5350	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
5351	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
5352	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
5353	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
5354	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
5355	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
5356	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
5357	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
5358	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
5359	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
5360	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
5361	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
5362	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
5363	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
5364	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
5365	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
5366	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
5367	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
5368	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
5369	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
5370	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
5371	DBGFREGSUBFIELD_TERMINATOR()
5372	};
5373
5374	/** CPUID(7,0).ECX field descriptions. */
5375	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
5376	{
5377	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
5378	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
5379	DBGFREGSUBFIELD_RO("OSPKU\0" "CR4.PKU mirror", 4, 1, 0),
5380	DBGFREGSUBFIELD_TERMINATOR()
5381	};
5382
5383
5384	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
5385	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
5386	{
5387	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
5388	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
5389	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
5390	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
5391	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
5392	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
5393	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
5394	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
5395	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
5396	DBGFREGSUBFIELD_TERMINATOR()
5397	};
5398
5399	/** CPUID(13,1).EAX field descriptions. */
5400	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
5401	{
5402	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
5403	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
5404	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
5405	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
5406	DBGFREGSUBFIELD_TERMINATOR()
5407	};
5408
5409
5410	/** CPUID(0x80000001,0).EDX field descriptions. */
5411	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
5412	{
5413	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5414	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5415	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5416	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5417	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5418	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
5419	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5420	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5421	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5422	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5423	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
5424	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5425	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5426	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5427	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5428	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5429	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5430	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
5431	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
5432	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5433	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
5434	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
5435	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
5436	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
5437	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
5438	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
5439	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
5440	DBGFREGSUBFIELD_TERMINATOR()
5441	};
5442
5443	/** CPUID(0x80000001,0).ECX field descriptions. */
5444	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
5445	{
5446	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
5447	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
5448	DBGFREGSUBFIELD_RO("SVM\0" "AMD VM extensions", 2, 1, 0),
5449	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
5450	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
5451	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
5452	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
5453	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
5454	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
5455	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
5456	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
5457	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
5458	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
5459	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
5460	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
5461	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
5462	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
5463	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
5464	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
5465	DBGFREGSUBFIELD_TERMINATOR()
5466	};
5467
5468
5469	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
5470	const char *pszLeadIn, uint32_t cchWidth)
5471	{
5472	if (pszLeadIn)
5473	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5474
5475	for (uint32_t iBit = 0; iBit < 32; iBit++)
5476	if (RT_BIT_32(iBit) & uVal)
5477	{
5478	while ( pDesc->pszName != NULL
5479	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5480	pDesc++;
5481	if ( pDesc->pszName != NULL
5482	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5483	{
5484	if (pDesc->cBits == 1)
5485	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5486	else
5487	{
5488	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
5489	if (pDesc->cBits < 32)
5490	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5491	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
5492	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5493	}
5494	}
5495	else
5496	pHlp->pfnPrintf(pHlp, " %u", iBit);
5497	}
5498	if (pszLeadIn)
5499	pHlp->pfnPrintf(pHlp, "\n");
5500	}
5501
5502
5503	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5504	const char *pszLeadIn, uint32_t cchWidth)
5505	{
5506	if (pszLeadIn)
5507	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5508
5509	for (uint32_t iBit = 0; iBit < 64; iBit++)
5510	if (RT_BIT_64(iBit) & uVal)
5511	{
5512	while ( pDesc->pszName != NULL
5513	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5514	pDesc++;
5515	if ( pDesc->pszName != NULL
5516	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5517	{
5518	if (pDesc->cBits == 1)
5519	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5520	else
5521	{
5522	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
5523	if (pDesc->cBits < 64)
5524	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
5525	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
5526	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5527	}
5528	}
5529	else
5530	pHlp->pfnPrintf(pHlp, " %u", iBit);
5531	}
5532	if (pszLeadIn)
5533	pHlp->pfnPrintf(pHlp, "\n");
5534	}
5535
5536
5537	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5538	const char *pszLeadIn, uint32_t cchWidth)
5539	{
5540	if (!uVal)
5541	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5542	else
5543	{
5544	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5545	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
5546	pHlp->pfnPrintf(pHlp, " )\n");
5547	}
5548	}
5549
5550
5551	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
5552	uint32_t cchWidth)
5553	{
5554	uint32_t uCombined = uVal1 \| uVal2;
5555	for (uint32_t iBit = 0; iBit < 32; iBit++)
5556	if ( (RT_BIT_32(iBit) & uCombined)
5557	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
5558	{
5559	while ( pDesc->pszName != NULL
5560	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5561	pDesc++;
5562
5563	if ( pDesc->pszName != NULL
5564	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5565	{
5566	size_t cchMnemonic = strlen(pDesc->pszName);
5567	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
5568	size_t cchDesc = strlen(pszDesc);
5569	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
5570	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
5571	if (pDesc->cBits < 32)
5572	{
5573	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5574	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5575	}
5576
5577	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
5578	pDesc->pszName, pszDesc,
5579	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
5580	uFieldValue1, uFieldValue2);
5581
5582	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
5583	pDesc++;
5584	}
5585	else
5586	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
5587	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
5588	}
5589	}
5590
5591
5592	/**
5593	* Produces a detailed summary of standard leaf 0x00000001.
5594	*
5595	* @param pHlp The info helper functions.
5596	* @param paLeaves The CPUID leaves array.
5597	* @param cLeaves The number of leaves in the array.
5598	* @param pCurLeaf The 0x00000001 leaf.
5599	* @param fVerbose Whether to be very verbose or not.
5600	* @param fIntel Set if intel CPU.
5601	*/
5602	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5603	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
5604	{
5605	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
5606	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
5607	uint32_t uEAX = pCurLeaf->uEax;
5608	uint32_t uEBX = pCurLeaf->uEbx;
5609
5610	pHlp->pfnPrintf(pHlp,
5611	"%36s %2d \tExtended: %d \tEffective: %d\n"
5612	"%36s %2d \tExtended: %d \tEffective: %d\n"
5613	"%36s %d\n"
5614	"%36s %d (%s)\n"
5615	"%36s %#04x\n"
5616	"%36s %d\n"
5617	"%36s %d\n"
5618	"%36s %#04x\n"
5619	,
5620	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
5621	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
5622	"Stepping:", ASMGetCpuStepping(uEAX),
5623	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
5624	"APIC ID:", (uEBX >> 24) & 0xff,
5625	"Logical CPUs:",(uEBX >> 16) & 0xff,
5626	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
5627	"Brand ID:", (uEBX >> 0) & 0xff);
5628	if (fVerbose)
5629	{
5630	CPUMCPUID Host;
5631	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5632	pHlp->pfnPrintf(pHlp, "Features\n");
5633	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5634	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
5635	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
5636	}
5637	else
5638	{
5639	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
5640	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
5641	}
5642	}
5643
5644
5645	/**
5646	* Produces a detailed summary of standard leaf 0x00000007.
5647	*
5648	* @param pHlp The info helper functions.
5649	* @param paLeaves The CPUID leaves array.
5650	* @param cLeaves The number of leaves in the array.
5651	* @param pCurLeaf The first 0x00000007 leaf.
5652	* @param fVerbose Whether to be very verbose or not.
5653	*/
5654	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5655	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5656	{
5657	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
5658	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
5659	for (;;)
5660	{
5661	CPUMCPUID Host;
5662	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5663
5664	switch (pCurLeaf->uSubLeaf)
5665	{
5666	case 0:
5667	if (fVerbose)
5668	{
5669	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5670	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
5671	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
5672	if (pCurLeaf->uEdx \|\| Host.uEdx)
5673	pHlp->pfnPrintf(pHlp, "%36 %#x (%#x)\n", "Ext Features EDX:", pCurLeaf->uEdx, Host.uEdx);
5674	}
5675	else
5676	{
5677	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
5678	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
5679	if (pCurLeaf->uEdx)
5680	pHlp->pfnPrintf(pHlp, "%36 %#x\n", "Ext Features EDX:", pCurLeaf->uEdx);
5681	}
5682	break;
5683
5684	default:
5685	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
5686	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
5687	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
5688	break;
5689
5690	}
5691
5692	/* advance. */
5693	pCurLeaf++;
5694	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5695	\|\| pCurLeaf->uLeaf != 0x7)
5696	break;
5697	}
5698	}
5699
5700
5701	/**
5702	* Produces a detailed summary of standard leaf 0x0000000d.
5703	*
5704	* @param pHlp The info helper functions.
5705	* @param paLeaves The CPUID leaves array.
5706	* @param cLeaves The number of leaves in the array.
5707	* @param pCurLeaf The first 0x00000007 leaf.
5708	* @param fVerbose Whether to be very verbose or not.
5709	*/
5710	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5711	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5712	{
5713	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
5714	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
5715	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5716	{
5717	CPUMCPUID Host;
5718	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5719
5720	switch (uSubLeaf)
5721	{
5722	case 0:
5723	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5724	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
5725	pCurLeaf->uEbx, pCurLeaf->uEcx);
5726	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
5727
5728	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5729	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
5730	"Valid XCR0 bits, guest:", 42);
5731	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
5732	"Valid XCR0 bits, host:", 42);
5733	break;
5734
5735	case 1:
5736	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5737	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
5738	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
5739
5740	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5741	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
5742	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
5743
5744	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5745	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
5746	" Valid IA32_XSS bits, guest:", 42);
5747	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
5748	" Valid IA32_XSS bits, host:", 42);
5749	break;
5750
5751	default:
5752	if ( pCurLeaf
5753	&& pCurLeaf->uSubLeaf == uSubLeaf
5754	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
5755	{
5756	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
5757	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5758	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
5759	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
5760	if (pCurLeaf->uEdx)
5761	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
5762	pHlp->pfnPrintf(pHlp, " --");
5763	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5764	pHlp->pfnPrintf(pHlp, "\n");
5765	}
5766	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
5767	{
5768	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
5769	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5770	if (Host.uEcx & ~RT_BIT_32(0))
5771	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
5772	if (Host.uEdx)
5773	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
5774	pHlp->pfnPrintf(pHlp, " --");
5775	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5776	pHlp->pfnPrintf(pHlp, "\n");
5777	}
5778	break;
5779
5780	}
5781
5782	/* advance. */
5783	if (pCurLeaf)
5784	{
5785	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5786	&& pCurLeaf->uSubLeaf <= uSubLeaf
5787	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
5788	pCurLeaf++;
5789	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5790	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
5791	pCurLeaf = NULL;
5792	}
5793	}
5794	}
5795
5796
5797	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5798	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
5799	{
5800	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5801	&& pCurLeaf->uLeaf <= uUpToLeaf)
5802	{
5803	pHlp->pfnPrintf(pHlp,
5804	" %s\n"
5805	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
5806	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5807	&& pCurLeaf->uLeaf <= uUpToLeaf)
5808	{
5809	CPUMCPUID Host;
5810	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5811	pHlp->pfnPrintf(pHlp,
5812	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5813	"Hst: %08x %08x %08x %08x\n",
5814	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5815	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5816	pCurLeaf++;
5817	}
5818	}
5819
5820	return pCurLeaf;
5821	}
5822
5823
5824	/**
5825	* Display the guest CpuId leaves.
5826	*
5827	* @param pVM Pointer to the VM.
5828	* @param pHlp The info helper functions.
5829	* @param pszArgs "terse", "default" or "verbose".
5830	*/
5831	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
5832	{
5833	/*
5834	* Parse the argument.
5835	*/
5836	unsigned iVerbosity = 1;
5837	if (pszArgs)
5838	{
5839	pszArgs = RTStrStripL(pszArgs);
5840	if (!strcmp(pszArgs, "terse"))
5841	iVerbosity--;
5842	else if (!strcmp(pszArgs, "verbose"))
5843	iVerbosity++;
5844	}
5845
5846	uint32_t uLeaf;
5847	CPUMCPUID Host;
5848	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
5849	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
5850	PCCPUMCPUIDLEAF pCurLeaf;
5851	PCCPUMCPUIDLEAF pNextLeaf;
5852	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
5853	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
5854	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
5855
5856	/*
5857	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
5858	*/
5859	uint32_t cHstMax = ASMCpuId_EAX(0);
5860	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
5861	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
5862	pHlp->pfnPrintf(pHlp,
5863	" Raw Standard CPUID Leaves\n"
5864	" Leaf/sub-leaf eax ebx ecx edx\n");
5865	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
5866	{
5867	uint32_t cMaxSubLeaves = 1;
5868	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
5869	cMaxSubLeaves = 16;
5870	else if (uLeaf == 0xd)
5871	cMaxSubLeaves = 128;
5872
5873	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5874	{
5875	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5876	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5877	&& pCurLeaf->uLeaf == uLeaf
5878	&& pCurLeaf->uSubLeaf == uSubLeaf)
5879	{
5880	pHlp->pfnPrintf(pHlp,
5881	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5882	"Hst: %08x %08x %08x %08x\n",
5883	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5884	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5885	pCurLeaf++;
5886	}
5887	else if ( uLeaf != 0xd
5888	\|\| uSubLeaf <= 1
5889	\|\| Host.uEbx != 0 )
5890	pHlp->pfnPrintf(pHlp,
5891	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5892	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5893
5894	/* Done? */
5895	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5896	\|\| pCurLeaf->uLeaf != uLeaf)
5897	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
5898	\|\| (uLeaf == 0x7 && Host.uEax == 0)
5899	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
5900	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
5901	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
5902	)
5903	)
5904	break;
5905	}
5906	}
5907	pNextLeaf = pCurLeaf;
5908
5909	/*
5910	* If verbose, decode it.
5911	*/
5912	if (iVerbosity && paLeaves[0].uLeaf == 0)
5913	pHlp->pfnPrintf(pHlp,
5914	"%36s %.04s%.04s%.04s\n"
5915	"%36s 0x00000000-%#010x\n"
5916	,
5917	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
5918	"Supports:", paLeaves[0].uEax);
5919
5920	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
5921	cpumR3CpuIdInfoStdLeaf1Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1, fIntel);
5922
5923	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
5924	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5925
5926	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
5927	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5928
5929	pCurLeaf = pNextLeaf;
5930
5931	/*
5932	* Hypervisor leaves.
5933	*
5934	* Unlike most of the other leaves reported, the guest hypervisor leaves
5935	* aren't a subset of the host CPUID bits.
5936	*/
5937	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
5938
5939	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5940	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
5941	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
5942	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
5943	cMax = RT_MAX(cHstMax, cGstMax);
5944	if (cMax >= UINT32_C(0x40000000))
5945	{
5946	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
5947
5948	/** @todo dump these in more detail. */
5949
5950	pCurLeaf = pNextLeaf;
5951	}
5952
5953
5954	/*
5955	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
5956	* Implemented after AMD specs.
5957	*/
5958	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
5959
5960	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5961	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
5962	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
5963	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
5964	cMax = RT_MAX(cHstMax, cGstMax);
5965	if (cMax >= UINT32_C(0x80000000))
5966	{
5967
5968	pHlp->pfnPrintf(pHlp,
5969	" Raw Extended CPUID Leaves\n"
5970	" Leaf/sub-leaf eax ebx ecx edx\n");
5971	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
5972	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
5973	{
5974	uint32_t cMaxSubLeaves = 1;
5975	if (uLeaf == UINT32_C(0x8000001d))
5976	cMaxSubLeaves = 16;
5977
5978	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5979	{
5980	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5981	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5982	&& pCurLeaf->uLeaf == uLeaf
5983	&& pCurLeaf->uSubLeaf == uSubLeaf)
5984	{
5985	pHlp->pfnPrintf(pHlp,
5986	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5987	"Hst: %08x %08x %08x %08x\n",
5988	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5989	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5990	pCurLeaf++;
5991	}
5992	else if ( uLeaf != 0xd
5993	\|\| uSubLeaf <= 1
5994	\|\| Host.uEbx != 0 )
5995	pHlp->pfnPrintf(pHlp,
5996	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5997	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5998
5999	/* Done? */
6000	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6001	\|\| pCurLeaf->uLeaf != uLeaf)
6002	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6003	break;
6004	}
6005	}
6006	pNextLeaf = pCurLeaf;
6007
6008	/*
6009	* Understandable output
6010	*/
6011	if (iVerbosity)
6012	pHlp->pfnPrintf(pHlp,
6013	"Ext Name: %.4s%.4s%.4s\n"
6014	"Ext Supports: 0x80000000-%#010x\n",
6015	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6016
6017	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6018	if (iVerbosity && pCurLeaf)
6019	{
6020	uint32_t uEAX = pCurLeaf->uEax;
6021	pHlp->pfnPrintf(pHlp,
6022	"Family: %d \tExtended: %d \tEffective: %d\n"
6023	"Model: %d \tExtended: %d \tEffective: %d\n"
6024	"Stepping: %d\n"
6025	"Brand ID: %#05x\n",
6026	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6027	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6028	ASMGetCpuStepping(uEAX),
6029	pCurLeaf->uEbx & 0xfff);
6030
6031	if (iVerbosity == 1)
6032	{
6033	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6034	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6035	}
6036	else
6037	{
6038	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6039	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6040	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6041	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6042	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6043	}
6044	}
6045
6046	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6047	{
6048	char szString[443+1] = {0};
6049	uint32_t pu32 = (uint32_t )szString;
6050	*pu32++ = pCurLeaf->uEax;
6051	*pu32++ = pCurLeaf->uEbx;
6052	*pu32++ = pCurLeaf->uEcx;
6053	*pu32++ = pCurLeaf->uEdx;
6054	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6055	if (pCurLeaf)
6056	{
6057	*pu32++ = pCurLeaf->uEax;
6058	*pu32++ = pCurLeaf->uEbx;
6059	*pu32++ = pCurLeaf->uEcx;
6060	*pu32++ = pCurLeaf->uEdx;
6061	}
6062	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6063	if (pCurLeaf)
6064	{
6065	*pu32++ = pCurLeaf->uEax;
6066	*pu32++ = pCurLeaf->uEbx;
6067	*pu32++ = pCurLeaf->uEcx;
6068	*pu32++ = pCurLeaf->uEdx;
6069	}
6070	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6071	}
6072
6073	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6074	{
6075	uint32_t uEAX = pCurLeaf->uEax;
6076	uint32_t uEBX = pCurLeaf->uEbx;
6077	uint32_t uECX = pCurLeaf->uEcx;
6078	uint32_t uEDX = pCurLeaf->uEdx;
6079	char sz1[32];
6080	char sz2[32];
6081
6082	pHlp->pfnPrintf(pHlp,
6083	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6084	"TLB 2/4M Data: %s %3d entries\n",
6085	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6086	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6087	pHlp->pfnPrintf(pHlp,
6088	"TLB 4K Instr/Uni: %s %3d entries\n"
6089	"TLB 4K Data: %s %3d entries\n",
6090	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6091	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6092	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6093	"L1 Instr Cache Lines Per Tag: %d\n"
6094	"L1 Instr Cache Associativity: %s\n"
6095	"L1 Instr Cache Size: %d KB\n",
6096	(uEDX >> 0) & 0xff,
6097	(uEDX >> 8) & 0xff,
6098	getCacheAss((uEDX >> 16) & 0xff, sz1),
6099	(uEDX >> 24) & 0xff);
6100	pHlp->pfnPrintf(pHlp,
6101	"L1 Data Cache Line Size: %d bytes\n"
6102	"L1 Data Cache Lines Per Tag: %d\n"
6103	"L1 Data Cache Associativity: %s\n"
6104	"L1 Data Cache Size: %d KB\n",
6105	(uECX >> 0) & 0xff,
6106	(uECX >> 8) & 0xff,
6107	getCacheAss((uECX >> 16) & 0xff, sz1),
6108	(uECX >> 24) & 0xff);
6109	}
6110
6111	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6112	{
6113	uint32_t uEAX = pCurLeaf->uEax;
6114	uint32_t uEBX = pCurLeaf->uEbx;
6115	uint32_t uEDX = pCurLeaf->uEdx;
6116
6117	pHlp->pfnPrintf(pHlp,
6118	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6119	"L2 TLB 2/4M Data: %s %4d entries\n",
6120	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6121	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6122	pHlp->pfnPrintf(pHlp,
6123	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6124	"L2 TLB 4K Data: %s %4d entries\n",
6125	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6126	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6127	pHlp->pfnPrintf(pHlp,
6128	"L2 Cache Line Size: %d bytes\n"
6129	"L2 Cache Lines Per Tag: %d\n"
6130	"L2 Cache Associativity: %s\n"
6131	"L2 Cache Size: %d KB\n",
6132	(uEDX >> 0) & 0xff,
6133	(uEDX >> 8) & 0xf,
6134	getL2CacheAss((uEDX >> 12) & 0xf),
6135	(uEDX >> 16) & 0xffff);
6136	}
6137
6138	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
6139	{
6140	uint32_t uEDX = pCurLeaf->uEdx;
6141
6142	pHlp->pfnPrintf(pHlp, "APM Features: ");
6143	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
6144	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
6145	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
6146	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
6147	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
6148	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
6149	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " MC");
6150	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " HWPSTATE");
6151	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TscInvariant");
6152	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " CPB");
6153	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " EffFreqRO");
6154	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PFI");
6155	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PA");
6156	for (unsigned iBit = 13; iBit < 32; iBit++)
6157	if (uEDX & RT_BIT(iBit))
6158	pHlp->pfnPrintf(pHlp, " %d", iBit);
6159	pHlp->pfnPrintf(pHlp, "\n");
6160
6161	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6162	pHlp->pfnPrintf(pHlp, "Host Invariant-TSC support: %RTbool\n",
6163	cHstMax >= UINT32_C(0x80000007) && (Host.uEdx & RT_BIT(8)));
6164
6165	}
6166
6167	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0)) != NULL)
6168	{
6169	uint32_t uEAX = pCurLeaf->uEax;
6170	uint32_t uECX = pCurLeaf->uEcx;
6171
6172	pHlp->pfnPrintf(pHlp,
6173	"Physical Address Width: %d bits\n"
6174	"Virtual Address Width: %d bits\n"
6175	"Guest Physical Address Width: %d bits\n",
6176	(uEAX >> 0) & 0xff,
6177	(uEAX >> 8) & 0xff,
6178	(uEAX >> 16) & 0xff);
6179	pHlp->pfnPrintf(pHlp,
6180	"Physical Core Count: %d\n",
6181	(uECX >> 0) & 0xff);
6182	}
6183
6184	pCurLeaf = pNextLeaf;
6185	}
6186
6187
6188
6189	/*
6190	* Centaur.
6191	*/
6192	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
6193
6194	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6195	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
6196	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
6197	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
6198	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
6199	cMax = RT_MAX(cHstMax, cGstMax);
6200	if (cMax >= UINT32_C(0xc0000000))
6201	{
6202	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
6203
6204	/*
6205	* Understandable output
6206	*/
6207	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
6208	pHlp->pfnPrintf(pHlp,
6209	"Centaur Supports: 0xc0000000-%#010x\n",
6210	pCurLeaf->uEax);
6211
6212	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
6213	{
6214	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6215	uint32_t uEdxGst = pCurLeaf->uEdx;
6216	uint32_t uEdxHst = Host.uEdx;
6217
6218	if (iVerbosity == 1)
6219	{
6220	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
6221	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
6222	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
6223	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
6224	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
6225	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
6226	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
6227	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
6228	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
6229	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6230	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
6231	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
6232	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
6233	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
6234	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
6235	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
6236	for (unsigned iBit = 14; iBit < 32; iBit++)
6237	if (uEdxGst & RT_BIT(iBit))
6238	pHlp->pfnPrintf(pHlp, " %d", iBit);
6239	pHlp->pfnPrintf(pHlp, "\n");
6240	}
6241	else
6242	{
6243	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
6244	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
6245	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
6246	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
6247	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
6248	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
6249	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
6250	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
6251	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
6252	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6253	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
6254	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
6255	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
6256	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
6257	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
6258	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
6259	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
6260	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
6261	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
6262	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
6263	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
6264	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
6265	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
6266	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
6267	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
6268	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
6269	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
6270	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
6271	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
6272	for (unsigned iBit = 27; iBit < 32; iBit++)
6273	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
6274	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
6275	pHlp->pfnPrintf(pHlp, "\n");
6276	}
6277	}
6278
6279	pCurLeaf = pNextLeaf;
6280	}
6281
6282	/*
6283	* The remainder.
6284	*/
6285	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
6286	}
6287
6288
6289
6290
6291
6292	/*
6293	*
6294	*
6295	* PATM interfaces.
6296	* PATM interfaces.
6297	* PATM interfaces.
6298	*
6299	*
6300	*/
6301
6302
6303	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
6304	/** @name Patchmanager CPUID legacy table APIs
6305	* @{
6306	*/
6307
6308	/**
6309	* Gets a pointer to the default CPUID leaf.
6310	*
6311	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
6312	* @param pVM Pointer to the VM.
6313	* @remark Intended for PATM only.
6314	*/
6315	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
6316	{
6317	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
6318	}
6319
6320
6321	/**
6322	* Gets a number of standard CPUID leaves (PATM only).
6323	*
6324	* @returns Number of leaves.
6325	* @param pVM Pointer to the VM.
6326	* @remark Intended for PATM - legacy, don't use in new code.
6327	*/
6328	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
6329	{
6330	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
6331	}
6332
6333
6334	/**
6335	* Gets a number of extended CPUID leaves (PATM only).
6336	*
6337	* @returns Number of leaves.
6338	* @param pVM Pointer to the VM.
6339	* @remark Intended for PATM - legacy, don't use in new code.
6340	*/
6341	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
6342	{
6343	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
6344	}
6345
6346
6347	/**
6348	* Gets a number of centaur CPUID leaves.
6349	*
6350	* @returns Number of leaves.
6351	* @param pVM Pointer to the VM.
6352	* @remark Intended for PATM - legacy, don't use in new code.
6353	*/
6354	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
6355	{
6356	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
6357	}
6358
6359
6360	/**
6361	* Gets a pointer to the array of standard CPUID leaves.
6362	*
6363	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
6364	*
6365	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
6366	* @param pVM Pointer to the VM.
6367	* @remark Intended for PATM - legacy, don't use in new code.
6368	*/
6369	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
6370	{
6371	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
6372	}
6373
6374
6375	/**
6376	* Gets a pointer to the array of extended CPUID leaves.
6377	*
6378	* CPUMGetGuestCpuIdExtMax() give the size of the array.
6379	*
6380	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
6381	* @param pVM Pointer to the VM.
6382	* @remark Intended for PATM - legacy, don't use in new code.
6383	*/
6384	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
6385	{
6386	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
6387	}
6388
6389
6390	/**
6391	* Gets a pointer to the array of centaur CPUID leaves.
6392	*
6393	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
6394	*
6395	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
6396	* @param pVM Pointer to the VM.
6397	* @remark Intended for PATM - legacy, don't use in new code.
6398	*/
6399	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
6400	{
6401	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
6402	}
6403
6404	/** @} */
6405	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
6406
6407	#endif /* VBOX_IN_VMM */
6408

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 58120

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