CPUMR3CpuId.cpp@ 60850

Last change on this file since 60850 was 60438, checked in by vboxsync, 9 years ago
CPUR3CpuId: Fixed fake 8086/80186 classification.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 295.1 KB

Line
1	/* $Id: CPUMR3CpuId.cpp 60438 2016-04-11 17:47:37Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/ssm.h>
27	#include "CPUMInternal.h"
28	#include <VBox/vmm/vm.h>
29	#include <VBox/vmm/mm.h>
30
31	#include <VBox/err.h>
32	#include <iprt/asm-amd64-x86.h>
33	#include <iprt/ctype.h>
34	#include <iprt/mem.h>
35	#include <iprt/string.h>
36
37
38	/*********************************************************************************************************************************
39	* Defined Constants And Macros *
40	*********************************************************************************************************************************/
41	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
42	#define CPUM_CPUID_MAX_LEAVES 2048
43	/* Max size we accept for the XSAVE area. */
44	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
45	/* Min size we accept for the XSAVE area. */
46	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
47
48
49	/*********************************************************************************************************************************
50	* Global Variables *
51	*********************************************************************************************************************************/
52	/**
53	* The intel pentium family.
54	*/
55	static const CPUMMICROARCH g_aenmIntelFamily06[] =
56	{
57	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
58	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
59	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
60	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
61	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
63	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
64	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
65	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
66	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
67	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
68	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
69	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
70	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
71	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
72	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
73	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
74	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
79	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
80	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
81	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
82	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
83	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
84	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
86	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
87	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
88	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
89	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
90	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
91	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
95	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
96	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
97	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
98	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
99	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
100	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
102	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
103	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
104	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
105	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
106	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
107	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
111	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
112	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
113	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
114	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
115	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
116	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
118	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
119	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
120	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
121	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
122	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
123	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
127	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
128	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
129	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
130	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
131	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
132	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
134	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
135	/* [78(0x4e)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed */
136	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / unconfirmed, Broadwell-E */
137	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
138	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
139	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed server cpu */
143	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
144	/* [87(0x57)] = */ kCpumMicroarch_Intel_Unknown,
145	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
146	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
147	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
148	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / unconfirmed */
150	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
151	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
152	/* [95(0x5f)] = */ kCpumMicroarch_Intel_Unknown,
153	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
154	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
155	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [99(0x64)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x65)] = */ kCpumMicroarch_Intel_Unknown,
159	/* [99(0x66)] = / kCpumMicroarch_Intel_Core7_Cannonlake, / unconfirmed */
160	};
161
162
163
164	/**
165	* Figures out the (sub-)micro architecture given a bit of CPUID info.
166	*
167	* @returns Micro architecture.
168	* @param enmVendor The CPU vendor .
169	* @param bFamily The CPU family.
170	* @param bModel The CPU model.
171	* @param bStepping The CPU stepping.
172	*/
173	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
174	uint8_t bModel, uint8_t bStepping)
175	{
176	if (enmVendor == CPUMCPUVENDOR_AMD)
177	{
178	switch (bFamily)
179	{
180	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
181	case 0x03: return kCpumMicroarch_AMD_Am386;
182	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
183	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
184	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
185	case 0x06:
186	switch (bModel)
187	{
188	case 0: return kCpumMicroarch_AMD_K7_Palomino;
189	case 1: return kCpumMicroarch_AMD_K7_Palomino;
190	case 2: return kCpumMicroarch_AMD_K7_Palomino;
191	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
192	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
193	case 6: return kCpumMicroarch_AMD_K7_Palomino;
194	case 7: return kCpumMicroarch_AMD_K7_Morgan;
195	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
196	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
197	}
198	return kCpumMicroarch_AMD_K7_Unknown;
199	case 0x0f:
200	/*
201	* This family is a friggin mess. Trying my best to make some
202	* sense out of it. Too much happened in the 0x0f family to
203	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
204	*
205	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
206	* cpu-world.com, and other places:
207	* - 130nm:
208	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
209	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
210	* - Newcastle: FC0/DH-CG (errum #180: FE0/DH-CG), FF0/DH-CG
211	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
212	* - Odessa: FC0/DH-CG (errum #180: FE0/DH-CG)
213	* - Paris: FF0/DH-CG, FC0/DH-CG (errum #180: FE0/DH-CG),
214	* - 90nm:
215	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
216	* - Oakville: 10FC0/DH-D0.
217	* - Georgetown: 10FC0/DH-D0.
218	* - Sonora: 10FC0/DH-D0.
219	* - Venus: 20F71/SH-E4
220	* - Troy: 20F51/SH-E4
221	* - Athens: 20F51/SH-E4
222	* - San Diego: 20F71/SH-E4.
223	* - Lancaster: 20F42/SH-E5
224	* - Newark: 20F42/SH-E5.
225	* - Albany: 20FC2/DH-E6.
226	* - Roma: 20FC2/DH-E6.
227	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
228	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
229	* - 90nm introducing Dual core:
230	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
231	* - Italy: 20F10/JH-E1, 20F12/JH-E6
232	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
233	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
234	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
235	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
236	* - Santa Ana: 40F32/JH-F2, /-F3
237	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
238	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
239	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
240	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
241	* - Keene: 40FC2/DH-F2.
242	* - Richmond: 40FC2/DH-F2
243	* - Taylor: 40F82/BH-F2
244	* - Trinidad: 40F82/BH-F2
245	*
246	* - 65nm:
247	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
248	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
249	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
250	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
251	* - Sherman: /-G1, 70FC2/DH-G2.
252	* - Huron: 70FF2/DH-G2.
253	*/
254	if (bModel < 0x10)
255	return kCpumMicroarch_AMD_K8_130nm;
256	if (bModel >= 0x60 && bModel < 0x80)
257	return kCpumMicroarch_AMD_K8_65nm;
258	if (bModel >= 0x40)
259	return kCpumMicroarch_AMD_K8_90nm_AMDV;
260	switch (bModel)
261	{
262	case 0x21:
263	case 0x23:
264	case 0x2b:
265	case 0x2f:
266	case 0x37:
267	case 0x3f:
268	return kCpumMicroarch_AMD_K8_90nm_DualCore;
269	}
270	return kCpumMicroarch_AMD_K8_90nm;
271	case 0x10:
272	return kCpumMicroarch_AMD_K10;
273	case 0x11:
274	return kCpumMicroarch_AMD_K10_Lion;
275	case 0x12:
276	return kCpumMicroarch_AMD_K10_Llano;
277	case 0x14:
278	return kCpumMicroarch_AMD_Bobcat;
279	case 0x15:
280	switch (bModel)
281	{
282	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
283	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
284	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
285	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
286	case 0x11: /* ?? */
287	case 0x12: /* ?? */
288	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
289	}
290	return kCpumMicroarch_AMD_15h_Unknown;
291	case 0x16:
292	return kCpumMicroarch_AMD_Jaguar;
293
294	}
295	return kCpumMicroarch_AMD_Unknown;
296	}
297
298	if (enmVendor == CPUMCPUVENDOR_INTEL)
299	{
300	switch (bFamily)
301	{
302	case 3:
303	return kCpumMicroarch_Intel_80386;
304	case 4:
305	return kCpumMicroarch_Intel_80486;
306	case 5:
307	return kCpumMicroarch_Intel_P5;
308	case 6:
309	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
310	return g_aenmIntelFamily06[bModel];
311	return kCpumMicroarch_Intel_Atom_Unknown;
312	case 15:
313	switch (bModel)
314	{
315	case 0: return kCpumMicroarch_Intel_NB_Willamette;
316	case 1: return kCpumMicroarch_Intel_NB_Willamette;
317	case 2: return kCpumMicroarch_Intel_NB_Northwood;
318	case 3: return kCpumMicroarch_Intel_NB_Prescott;
319	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
320	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
321	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
322	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
323	default: return kCpumMicroarch_Intel_NB_Unknown;
324	}
325	break;
326	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
327	case 0:
328	return kCpumMicroarch_Intel_8086;
329	case 1:
330	return kCpumMicroarch_Intel_80186;
331	case 2:
332	return kCpumMicroarch_Intel_80286;
333	}
334	return kCpumMicroarch_Intel_Unknown;
335	}
336
337	if (enmVendor == CPUMCPUVENDOR_VIA)
338	{
339	switch (bFamily)
340	{
341	case 5:
342	switch (bModel)
343	{
344	case 1: return kCpumMicroarch_Centaur_C6;
345	case 4: return kCpumMicroarch_Centaur_C6;
346	case 8: return kCpumMicroarch_Centaur_C2;
347	case 9: return kCpumMicroarch_Centaur_C3;
348	}
349	break;
350
351	case 6:
352	switch (bModel)
353	{
354	case 5: return kCpumMicroarch_VIA_C3_M2;
355	case 6: return kCpumMicroarch_VIA_C3_C5A;
356	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
357	case 8: return kCpumMicroarch_VIA_C3_C5N;
358	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
359	case 10: return kCpumMicroarch_VIA_C7_C5J;
360	case 15: return kCpumMicroarch_VIA_Isaiah;
361	}
362	break;
363	}
364	return kCpumMicroarch_VIA_Unknown;
365	}
366
367	if (enmVendor == CPUMCPUVENDOR_CYRIX)
368	{
369	switch (bFamily)
370	{
371	case 4:
372	switch (bModel)
373	{
374	case 9: return kCpumMicroarch_Cyrix_5x86;
375	}
376	break;
377
378	case 5:
379	switch (bModel)
380	{
381	case 2: return kCpumMicroarch_Cyrix_M1;
382	case 4: return kCpumMicroarch_Cyrix_MediaGX;
383	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
384	}
385	break;
386
387	case 6:
388	switch (bModel)
389	{
390	case 0: return kCpumMicroarch_Cyrix_M2;
391	}
392	break;
393
394	}
395	return kCpumMicroarch_Cyrix_Unknown;
396	}
397
398	return kCpumMicroarch_Unknown;
399	}
400
401
402	/**
403	* Translates a microarchitecture enum value to the corresponding string
404	* constant.
405	*
406	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
407	* NULL if the value is invalid.
408	*
409	* @param enmMicroarch The enum value to convert.
410	*/
411	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
412	{
413	switch (enmMicroarch)
414	{
415	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
416	CASE_RET_STR(kCpumMicroarch_Intel_8086);
417	CASE_RET_STR(kCpumMicroarch_Intel_80186);
418	CASE_RET_STR(kCpumMicroarch_Intel_80286);
419	CASE_RET_STR(kCpumMicroarch_Intel_80386);
420	CASE_RET_STR(kCpumMicroarch_Intel_80486);
421	CASE_RET_STR(kCpumMicroarch_Intel_P5);
422
423	CASE_RET_STR(kCpumMicroarch_Intel_P6);
424	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
425	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
426
427	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
428	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
429	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
430
431	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
432	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
433
434	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
435	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
436	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
437	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
438	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
439	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
440	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
441	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Cannonlake);
442
443	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
444	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
445	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
446	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
447	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
448	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
449	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
450
451	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
452	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
453	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
454	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
455	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
456	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
457	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
458
459	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
460
461	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
462	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
463	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
464	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
465	CASE_RET_STR(kCpumMicroarch_AMD_K5);
466	CASE_RET_STR(kCpumMicroarch_AMD_K6);
467
468	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
469	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
470	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
471	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
472	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
473	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
474	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
475
476	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
477	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
478	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
479	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
480	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
481
482	CASE_RET_STR(kCpumMicroarch_AMD_K10);
483	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
484	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
485	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
486	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
487
488	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
489	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
490	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
491	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
492	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
493
494	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
495
496	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
497
498	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
499	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
500	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
501	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
502	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
503	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
504	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
505	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
506	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
507	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
508	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
509	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
510	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
511
512	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
513	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
514	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
515	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
516	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
517	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
518
519	CASE_RET_STR(kCpumMicroarch_NEC_V20);
520	CASE_RET_STR(kCpumMicroarch_NEC_V30);
521
522	CASE_RET_STR(kCpumMicroarch_Unknown);
523
524	#undef CASE_RET_STR
525	case kCpumMicroarch_Invalid:
526	case kCpumMicroarch_Intel_End:
527	case kCpumMicroarch_Intel_Core7_End:
528	case kCpumMicroarch_Intel_Atom_End:
529	case kCpumMicroarch_Intel_P6_Core_Atom_End:
530	case kCpumMicroarch_Intel_NB_End:
531	case kCpumMicroarch_AMD_K7_End:
532	case kCpumMicroarch_AMD_K8_End:
533	case kCpumMicroarch_AMD_15h_End:
534	case kCpumMicroarch_AMD_16h_End:
535	case kCpumMicroarch_AMD_End:
536	case kCpumMicroarch_VIA_End:
537	case kCpumMicroarch_Cyrix_End:
538	case kCpumMicroarch_NEC_End:
539	case kCpumMicroarch_32BitHack:
540	break;
541	/* no default! */
542	}
543
544	return NULL;
545	}
546
547
548
549	/**
550	* Gets a matching leaf in the CPUID leaf array.
551	*
552	* @returns Pointer to the matching leaf, or NULL if not found.
553	* @param paLeaves The CPUID leaves to search. This is sorted.
554	* @param cLeaves The number of leaves in the array.
555	* @param uLeaf The leaf to locate.
556	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
557	*/
558	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
559	{
560	/* Lazy bird does linear lookup here since this is only used for the
561	occational CPUID overrides. */
562	for (uint32_t i = 0; i < cLeaves; i++)
563	if ( paLeaves[i].uLeaf == uLeaf
564	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
565	return &paLeaves[i];
566	return NULL;
567	}
568
569
570	/**
571	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
572	*
573	* @returns true if found, false it not.
574	* @param paLeaves The CPUID leaves to search. This is sorted.
575	* @param cLeaves The number of leaves in the array.
576	* @param uLeaf The leaf to locate.
577	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
578	* @param pLegacy The legacy output leaf.
579	*/
580	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
581	PCPUMCPUID pLegacy)
582	{
583	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
584	if (pLeaf)
585	{
586	pLegacy->uEax = pLeaf->uEax;
587	pLegacy->uEbx = pLeaf->uEbx;
588	pLegacy->uEcx = pLeaf->uEcx;
589	pLegacy->uEdx = pLeaf->uEdx;
590	return true;
591	}
592	return false;
593	}
594
595
596	/**
597	* Ensures that the CPUID leaf array can hold one more leaf.
598	*
599	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
600	* failure.
601	* @param pVM The cross context VM structure. If NULL, use
602	* the process heap, otherwise the VM's hyper heap.
603	* @param ppaLeaves Pointer to the variable holding the array pointer
604	* (input/output).
605	* @param cLeaves The current array size.
606	*
607	* @remarks This function will automatically update the R0 and RC pointers when
608	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
609	* be the corresponding VM's CPUID arrays (which is asserted).
610	*/
611	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
612	{
613	/*
614	* If pVM is not specified, we're on the regular heap and can waste a
615	* little space to speed things up.
616	*/
617	uint32_t cAllocated;
618	if (!pVM)
619	{
620	cAllocated = RT_ALIGN(cLeaves, 16);
621	if (cLeaves + 1 > cAllocated)
622	{
623	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
624	if (pvNew)
625	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
626	else
627	{
628	RTMemFree(*ppaLeaves);
629	*ppaLeaves = NULL;
630	}
631	}
632	}
633	/*
634	* Otherwise, we're on the hyper heap and are probably just inserting
635	* one or two leaves and should conserve space.
636	*/
637	else
638	{
639	#ifdef IN_VBOX_CPU_REPORT
640	AssertReleaseFailed();
641	#else
642	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
643	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
644
645	size_t cb = cLeaves * sizeof(**ppaLeaves);
646	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
647	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
648	if (RT_SUCCESS(rc))
649	{
650	/* Update the R0 and RC pointers. */
651	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
652	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
653	}
654	else
655	{
656	*ppaLeaves = NULL;
657	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
658	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
659	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
660	}
661	#endif
662	}
663	return *ppaLeaves;
664	}
665
666
667	/**
668	* Append a CPUID leaf or sub-leaf.
669	*
670	* ASSUMES linear insertion order, so we'll won't need to do any searching or
671	* replace anything. Use cpumR3CpuIdInsert() for those cases.
672	*
673	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
674	* the caller need do no more work.
675	* @param ppaLeaves Pointer to the the pointer to the array of sorted
676	* CPUID leaves and sub-leaves.
677	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
678	* @param uLeaf The leaf we're adding.
679	* @param uSubLeaf The sub-leaf number.
680	* @param fSubLeafMask The sub-leaf mask.
681	* @param uEax The EAX value.
682	* @param uEbx The EBX value.
683	* @param uEcx The ECX value.
684	* @param uEdx The EDX value.
685	* @param fFlags The flags.
686	*/
687	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
688	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
689	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
690	{
691	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
692	return VERR_NO_MEMORY;
693
694	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
695	Assert( *pcLeaves == 0
696	\|\| pNew[-1].uLeaf < uLeaf
697	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
698
699	pNew->uLeaf = uLeaf;
700	pNew->uSubLeaf = uSubLeaf;
701	pNew->fSubLeafMask = fSubLeafMask;
702	pNew->uEax = uEax;
703	pNew->uEbx = uEbx;
704	pNew->uEcx = uEcx;
705	pNew->uEdx = uEdx;
706	pNew->fFlags = fFlags;
707
708	*pcLeaves += 1;
709	return VINF_SUCCESS;
710	}
711
712
713	/**
714	* Checks that we've updated the CPUID leaves array correctly.
715	*
716	* This is a no-op in non-strict builds.
717	*
718	* @param paLeaves The leaves array.
719	* @param cLeaves The number of leaves.
720	*/
721	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
722	{
723	#ifdef VBOX_STRICT
724	for (uint32_t i = 1; i < cLeaves; i++)
725	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
726	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
727	else
728	{
729	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
730	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
731	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
732	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
733	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
734	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
735	}
736	#else
737	NOREF(paLeaves);
738	NOREF(cLeaves);
739	#endif
740	}
741
742
743	/**
744	* Inserts a CPU ID leaf, replacing any existing ones.
745	*
746	* When inserting a simple leaf where we already got a series of sub-leaves with
747	* the same leaf number (eax), the simple leaf will replace the whole series.
748	*
749	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
750	* host-context heap and has only been allocated/reallocated by the
751	* cpumR3CpuIdEnsureSpace function.
752	*
753	* @returns VBox status code.
754	* @param pVM The cross context VM structure. If NULL, use
755	* the process heap, otherwise the VM's hyper heap.
756	* @param ppaLeaves Pointer to the the pointer to the array of sorted
757	* CPUID leaves and sub-leaves. Must be NULL if using
758	* the hyper heap.
759	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
760	* be NULL if using the hyper heap.
761	* @param pNewLeaf Pointer to the data of the new leaf we're about to
762	* insert.
763	*/
764	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
765	{
766	/*
767	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
768	*/
769	if (pVM)
770	{
771	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
772	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
773
774	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
775	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
776	}
777
778	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
779	uint32_t cLeaves = *pcLeaves;
780
781	/*
782	* Validate the new leaf a little.
783	*/
784	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
785	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
786	VERR_INVALID_FLAGS);
787	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
788	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
789	VERR_INVALID_PARAMETER);
790	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
791	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
792	VERR_INVALID_PARAMETER);
793	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
794	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
795	VERR_INVALID_PARAMETER);
796
797	/*
798	* Find insertion point. The lazy bird uses the same excuse as in
799	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
800	*/
801	uint32_t i;
802	if ( cLeaves > 0
803	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
804	{
805	/* Add at end. */
806	i = cLeaves;
807	}
808	else if ( cLeaves > 0
809	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
810	{
811	/* Either replacing the last leaf or dealing with sub-leaves. Spool
812	back to the first sub-leaf to pretend we did the linear search. */
813	i = cLeaves - 1;
814	while ( i > 0
815	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
816	i--;
817	}
818	else
819	{
820	/* Linear search from the start. */
821	i = 0;
822	while ( i < cLeaves
823	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
824	i++;
825	}
826	if ( i < cLeaves
827	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
828	{
829	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
830	{
831	/*
832	* The sub-leaf mask differs, replace all existing leaves with the
833	* same leaf number.
834	*/
835	uint32_t c = 1;
836	while ( i + c < cLeaves
837	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
838	c++;
839	if (c > 1 && i + c < cLeaves)
840	{
841	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
842	*pcLeaves = cLeaves -= c - 1;
843	}
844
845	paLeaves[i] = *pNewLeaf;
846	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
847	return VINF_SUCCESS;
848	}
849
850	/* Find sub-leaf insertion point. */
851	while ( i < cLeaves
852	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
853	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
854	i++;
855
856	/*
857	* If we've got an exactly matching leaf, replace it.
858	*/
859	if ( i < cLeaves
860	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
861	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
862	{
863	paLeaves[i] = *pNewLeaf;
864	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
865	return VINF_SUCCESS;
866	}
867	}
868
869	/*
870	* Adding a new leaf at 'i'.
871	*/
872	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
873	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
874	if (!paLeaves)
875	return VERR_NO_MEMORY;
876
877	if (i < cLeaves)
878	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
879	*pcLeaves += 1;
880	paLeaves[i] = *pNewLeaf;
881
882	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
883	return VINF_SUCCESS;
884	}
885
886
887	/**
888	* Removes a range of CPUID leaves.
889	*
890	* This will not reallocate the array.
891	*
892	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
893	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
894	* @param uFirst The first leaf.
895	* @param uLast The last leaf.
896	*/
897	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
898	{
899	uint32_t cLeaves = *pcLeaves;
900
901	Assert(uFirst <= uLast);
902
903	/*
904	* Find the first one.
905	*/
906	uint32_t iFirst = 0;
907	while ( iFirst < cLeaves
908	&& paLeaves[iFirst].uLeaf < uFirst)
909	iFirst++;
910
911	/*
912	* Find the end (last + 1).
913	*/
914	uint32_t iEnd = iFirst;
915	while ( iEnd < cLeaves
916	&& paLeaves[iEnd].uLeaf <= uLast)
917	iEnd++;
918
919	/*
920	* Adjust the array if anything needs removing.
921	*/
922	if (iFirst < iEnd)
923	{
924	if (iEnd < cLeaves)
925	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
926	*pcLeaves = cLeaves -= (iEnd - iFirst);
927	}
928
929	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
930	}
931
932
933
934	/**
935	* Checks if ECX make a difference when reading a given CPUID leaf.
936	*
937	* @returns @c true if it does, @c false if it doesn't.
938	* @param uLeaf The leaf we're reading.
939	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
940	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
941	* final sub-leaf (for leaf 0xb only).
942	*/
943	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
944	{
945	*pfFinalEcxUnchanged = false;
946
947	uint32_t auCur[4];
948	uint32_t auPrev[4];
949	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
950
951	/* Look for sub-leaves. */
952	uint32_t uSubLeaf = 1;
953	for (;;)
954	{
955	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
956	if (memcmp(auCur, auPrev, sizeof(auCur)))
957	break;
958
959	/* Advance / give up. */
960	uSubLeaf++;
961	if (uSubLeaf >= 64)
962	{
963	*pcSubLeaves = 1;
964	return false;
965	}
966	}
967
968	/* Count sub-leaves. */
969	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
970	uint32_t cRepeats = 0;
971	uSubLeaf = 0;
972	for (;;)
973	{
974	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
975
976	/* Figuring out when to stop isn't entirely straight forward as we need
977	to cover undocumented behavior up to a point and implementation shortcuts. */
978
979	/* 1. Look for more than 4 repeating value sets. */
980	if ( auCur[0] == auPrev[0]
981	&& auCur[1] == auPrev[1]
982	&& ( auCur[2] == auPrev[2]
983	\|\| ( auCur[2] == uSubLeaf
984	&& auPrev[2] == uSubLeaf - 1) )
985	&& auCur[3] == auPrev[3])
986	{
987	if ( uLeaf != 0xd
988	\|\| uSubLeaf >= 64
989	\|\| ( auCur[0] == 0
990	&& auCur[1] == 0
991	&& auCur[2] == 0
992	&& auCur[3] == 0
993	&& auPrev[2] == 0) )
994	cRepeats++;
995	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
996	break;
997	}
998	else
999	cRepeats = 0;
1000
1001	/* 2. Look for zero values. */
1002	if ( auCur[0] == 0
1003	&& auCur[1] == 0
1004	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1005	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1006	&& uSubLeaf >= cMinLeaves)
1007	{
1008	cRepeats = 0;
1009	break;
1010	}
1011
1012	/* 3. Leaf 0xb level type 0 check. */
1013	if ( uLeaf == 0xb
1014	&& (auCur[2] & 0xff00) == 0
1015	&& (auPrev[2] & 0xff00) == 0)
1016	{
1017	cRepeats = 0;
1018	break;
1019	}
1020
1021	/* 99. Give up. */
1022	if (uSubLeaf >= 128)
1023	{
1024	#ifndef IN_VBOX_CPU_REPORT
1025	/* Ok, limit it according to the documentation if possible just to
1026	avoid annoying users with these detection issues. */
1027	uint32_t cDocLimit = UINT32_MAX;
1028	if (uLeaf == 0x4)
1029	cDocLimit = 4;
1030	else if (uLeaf == 0x7)
1031	cDocLimit = 1;
1032	else if (uLeaf == 0xd)
1033	cDocLimit = 63;
1034	else if (uLeaf == 0xf)
1035	cDocLimit = 2;
1036	if (cDocLimit != UINT32_MAX)
1037	{
1038	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1039	*pcSubLeaves = cDocLimit + 3;
1040	return true;
1041	}
1042	#endif
1043	*pcSubLeaves = UINT32_MAX;
1044	return true;
1045	}
1046
1047	/* Advance. */
1048	uSubLeaf++;
1049	memcpy(auPrev, auCur, sizeof(auCur));
1050	}
1051
1052	/* Standard exit. */
1053	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1054	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1055	if (*pcSubLeaves == 0)
1056	*pcSubLeaves = 1;
1057	return true;
1058	}
1059
1060
1061	/**
1062	* Gets a CPU ID leaf.
1063	*
1064	* @returns VBox status code.
1065	* @param pVM The cross context VM structure.
1066	* @param pLeaf Where to store the found leaf.
1067	* @param uLeaf The leaf to locate.
1068	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1069	*/
1070	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1071	{
1072	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1073	uLeaf, uSubLeaf);
1074	if (pcLeaf)
1075	{
1076	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1077	return VINF_SUCCESS;
1078	}
1079
1080	return VERR_NOT_FOUND;
1081	}
1082
1083
1084	/**
1085	* Inserts a CPU ID leaf, replacing any existing ones.
1086	*
1087	* @returns VBox status code.
1088	* @param pVM The cross context VM structure.
1089	* @param pNewLeaf Pointer to the leaf being inserted.
1090	*/
1091	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1092	{
1093	/*
1094	* Validate parameters.
1095	*/
1096	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1097	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1098
1099	/*
1100	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1101	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1102	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1103	*/
1104	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1105	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1106	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1107	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1108	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1109	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1110	{
1111	return VERR_NOT_SUPPORTED;
1112	}
1113
1114	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1115	}
1116
1117	/**
1118	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1119	*
1120	* @returns VBox status code.
1121	* @param ppaLeaves Where to return the array pointer on success.
1122	* Use RTMemFree to release.
1123	* @param pcLeaves Where to return the size of the array on
1124	* success.
1125	*/
1126	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1127	{
1128	*ppaLeaves = NULL;
1129	*pcLeaves = 0;
1130
1131	/*
1132	* Try out various candidates. This must be sorted!
1133	*/
1134	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1135	{
1136	{ UINT32_C(0x00000000), false },
1137	{ UINT32_C(0x10000000), false },
1138	{ UINT32_C(0x20000000), false },
1139	{ UINT32_C(0x30000000), false },
1140	{ UINT32_C(0x40000000), false },
1141	{ UINT32_C(0x50000000), false },
1142	{ UINT32_C(0x60000000), false },
1143	{ UINT32_C(0x70000000), false },
1144	{ UINT32_C(0x80000000), false },
1145	{ UINT32_C(0x80860000), false },
1146	{ UINT32_C(0x8ffffffe), true },
1147	{ UINT32_C(0x8fffffff), true },
1148	{ UINT32_C(0x90000000), false },
1149	{ UINT32_C(0xa0000000), false },
1150	{ UINT32_C(0xb0000000), false },
1151	{ UINT32_C(0xc0000000), false },
1152	{ UINT32_C(0xd0000000), false },
1153	{ UINT32_C(0xe0000000), false },
1154	{ UINT32_C(0xf0000000), false },
1155	};
1156
1157	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1158	{
1159	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1160	uint32_t uEax, uEbx, uEcx, uEdx;
1161	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1162
1163	/*
1164	* Does EAX look like a typical leaf count value?
1165	*/
1166	if ( uEax > uLeaf
1167	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1168	{
1169	/* Yes, dump them. */
1170	uint32_t cLeaves = uEax - uLeaf + 1;
1171	while (cLeaves-- > 0)
1172	{
1173	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1174
1175	uint32_t fFlags = 0;
1176
1177	/* There are currently three known leaves containing an APIC ID
1178	that needs EMT specific attention */
1179	if (uLeaf == 1)
1180	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1181	else if (uLeaf == 0xb && uEcx != 0)
1182	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1183	else if ( uLeaf == UINT32_C(0x8000001e)
1184	&& ( uEax
1185	\|\| uEbx
1186	\|\| uEdx
1187	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1188	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1189
1190
1191	/* Check three times here to reduce the chance of CPU migration
1192	resulting in false positives with things like the APIC ID. */
1193	uint32_t cSubLeaves;
1194	bool fFinalEcxUnchanged;
1195	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1196	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1197	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1198	{
1199	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1200	{
1201	/* This shouldn't happen. But in case it does, file all
1202	relevant details in the release log. */
1203	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1204	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1205	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1206	{
1207	uint32_t auTmp[4];
1208	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1209	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1210	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1211	}
1212	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1213	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1214	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1215	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1216	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1217	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1218	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1219	}
1220
1221	if (fFinalEcxUnchanged)
1222	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1223
1224	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1225	{
1226	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1227	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1228	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1229	if (RT_FAILURE(rc))
1230	return rc;
1231	}
1232	}
1233	else
1234	{
1235	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1236	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1237	if (RT_FAILURE(rc))
1238	return rc;
1239	}
1240
1241	/* next */
1242	uLeaf++;
1243	}
1244	}
1245	/*
1246	* Special CPUIDs needs special handling as they don't follow the
1247	* leaf count principle used above.
1248	*/
1249	else if (s_aCandidates[iOuter].fSpecial)
1250	{
1251	bool fKeep = false;
1252	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1253	fKeep = true;
1254	else if ( uLeaf == 0x8fffffff
1255	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1256	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1257	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1258	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1259	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1260	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1261	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1262	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1263	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1264	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1265	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1266	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1267	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1268	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1269	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1270	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1271	fKeep = true;
1272	if (fKeep)
1273	{
1274	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1275	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1276	if (RT_FAILURE(rc))
1277	return rc;
1278	}
1279	}
1280	}
1281
1282	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1283	return VINF_SUCCESS;
1284	}
1285
1286
1287	/**
1288	* Determines the method the CPU uses to handle unknown CPUID leaves.
1289	*
1290	* @returns VBox status code.
1291	* @param penmUnknownMethod Where to return the method.
1292	* @param pDefUnknown Where to return default unknown values. This
1293	* will be set, even if the resulting method
1294	* doesn't actually needs it.
1295	*/
1296	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1297	{
1298	uint32_t uLastStd = ASMCpuId_EAX(0);
1299	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1300	if (!ASMIsValidExtRange(uLastExt))
1301	uLastExt = 0x80000000;
1302
1303	uint32_t auChecks[] =
1304	{
1305	uLastStd + 1,
1306	uLastStd + 5,
1307	uLastStd + 8,
1308	uLastStd + 32,
1309	uLastStd + 251,
1310	uLastExt + 1,
1311	uLastExt + 8,
1312	uLastExt + 15,
1313	uLastExt + 63,
1314	uLastExt + 255,
1315	0x7fbbffcc,
1316	0x833f7872,
1317	0xefff2353,
1318	0x35779456,
1319	0x1ef6d33e,
1320	};
1321
1322	static const uint32_t s_auValues[] =
1323	{
1324	0xa95d2156,
1325	0x00000001,
1326	0x00000002,
1327	0x00000008,
1328	0x00000000,
1329	0x55773399,
1330	0x93401769,
1331	0x12039587,
1332	};
1333
1334	/*
1335	* Simple method, all zeros.
1336	*/
1337	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1338	pDefUnknown->uEax = 0;
1339	pDefUnknown->uEbx = 0;
1340	pDefUnknown->uEcx = 0;
1341	pDefUnknown->uEdx = 0;
1342
1343	/*
1344	* Intel has been observed returning the last standard leaf.
1345	*/
1346	uint32_t auLast[4];
1347	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1348
1349	uint32_t cChecks = RT_ELEMENTS(auChecks);
1350	while (cChecks > 0)
1351	{
1352	uint32_t auCur[4];
1353	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1354	if (memcmp(auCur, auLast, sizeof(auCur)))
1355	break;
1356	cChecks--;
1357	}
1358	if (cChecks == 0)
1359	{
1360	/* Now, what happens when the input changes? Esp. ECX. */
1361	uint32_t cTotal = 0;
1362	uint32_t cSame = 0;
1363	uint32_t cLastWithEcx = 0;
1364	uint32_t cNeither = 0;
1365	uint32_t cValues = RT_ELEMENTS(s_auValues);
1366	while (cValues > 0)
1367	{
1368	uint32_t uValue = s_auValues[cValues - 1];
1369	uint32_t auLastWithEcx[4];
1370	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1371	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1372
1373	cChecks = RT_ELEMENTS(auChecks);
1374	while (cChecks > 0)
1375	{
1376	uint32_t auCur[4];
1377	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1378	if (!memcmp(auCur, auLast, sizeof(auCur)))
1379	{
1380	cSame++;
1381	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1382	cLastWithEcx++;
1383	}
1384	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1385	cLastWithEcx++;
1386	else
1387	cNeither++;
1388	cTotal++;
1389	cChecks--;
1390	}
1391	cValues--;
1392	}
1393
1394	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1395	if (cSame == cTotal)
1396	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1397	else if (cLastWithEcx == cTotal)
1398	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1399	else
1400	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1401	pDefUnknown->uEax = auLast[0];
1402	pDefUnknown->uEbx = auLast[1];
1403	pDefUnknown->uEcx = auLast[2];
1404	pDefUnknown->uEdx = auLast[3];
1405	return VINF_SUCCESS;
1406	}
1407
1408	/*
1409	* Unchanged register values?
1410	*/
1411	cChecks = RT_ELEMENTS(auChecks);
1412	while (cChecks > 0)
1413	{
1414	uint32_t const uLeaf = auChecks[cChecks - 1];
1415	uint32_t cValues = RT_ELEMENTS(s_auValues);
1416	while (cValues > 0)
1417	{
1418	uint32_t uValue = s_auValues[cValues - 1];
1419	uint32_t auCur[4];
1420	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1421	if ( auCur[0] != uLeaf
1422	\|\| auCur[1] != uValue
1423	\|\| auCur[2] != uValue
1424	\|\| auCur[3] != uValue)
1425	break;
1426	cValues--;
1427	}
1428	if (cValues != 0)
1429	break;
1430	cChecks--;
1431	}
1432	if (cChecks == 0)
1433	{
1434	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1435	return VINF_SUCCESS;
1436	}
1437
1438	/*
1439	* Just go with the simple method.
1440	*/
1441	return VINF_SUCCESS;
1442	}
1443
1444
1445	/**
1446	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1447	*
1448	* @returns Read only name string.
1449	* @param enmUnknownMethod The method to translate.
1450	*/
1451	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1452	{
1453	switch (enmUnknownMethod)
1454	{
1455	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1456	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1457	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1458	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1459
1460	case CPUMUNKNOWNCPUID_INVALID:
1461	case CPUMUNKNOWNCPUID_END:
1462	case CPUMUNKNOWNCPUID_32BIT_HACK:
1463	break;
1464	}
1465	return "Invalid-unknown-CPUID-method";
1466	}
1467
1468
1469	/**
1470	* Detect the CPU vendor give n the
1471	*
1472	* @returns The vendor.
1473	* @param uEAX EAX from CPUID(0).
1474	* @param uEBX EBX from CPUID(0).
1475	* @param uECX ECX from CPUID(0).
1476	* @param uEDX EDX from CPUID(0).
1477	*/
1478	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1479	{
1480	if (ASMIsValidStdRange(uEAX))
1481	{
1482	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1483	return CPUMCPUVENDOR_AMD;
1484
1485	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1486	return CPUMCPUVENDOR_INTEL;
1487
1488	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1489	return CPUMCPUVENDOR_VIA;
1490
1491	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1492	&& uECX == UINT32_C(0x64616574)
1493	&& uEDX == UINT32_C(0x736E4978))
1494	return CPUMCPUVENDOR_CYRIX;
1495
1496	/* "Geode by NSC", example: family 5, model 9. */
1497
1498	/** @todo detect the other buggers... */
1499	}
1500
1501	return CPUMCPUVENDOR_UNKNOWN;
1502	}
1503
1504
1505	/**
1506	* Translates a CPU vendor enum value into the corresponding string constant.
1507	*
1508	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1509	* value name. This can be useful when generating code.
1510	*
1511	* @returns Read only name string.
1512	* @param enmVendor The CPU vendor value.
1513	*/
1514	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1515	{
1516	switch (enmVendor)
1517	{
1518	case CPUMCPUVENDOR_INTEL: return "INTEL";
1519	case CPUMCPUVENDOR_AMD: return "AMD";
1520	case CPUMCPUVENDOR_VIA: return "VIA";
1521	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1522	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1523
1524	case CPUMCPUVENDOR_INVALID:
1525	case CPUMCPUVENDOR_32BIT_HACK:
1526	break;
1527	}
1528	return "Invalid-cpu-vendor";
1529	}
1530
1531
1532	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1533	{
1534	/* Could do binary search, doing linear now because I'm lazy. */
1535	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1536	while (cLeaves-- > 0)
1537	{
1538	if (pLeaf->uLeaf == uLeaf)
1539	return pLeaf;
1540	pLeaf++;
1541	}
1542	return NULL;
1543	}
1544
1545
1546	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1547	{
1548	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1549	if ( !pLeaf
1550	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1551	return pLeaf;
1552
1553	/* Linear sub-leaf search. Lazy as usual. */
1554	cLeaves -= pLeaf - paLeaves;
1555	while ( cLeaves-- > 0
1556	&& pLeaf->uLeaf == uLeaf)
1557	{
1558	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1559	return pLeaf;
1560	pLeaf++;
1561	}
1562
1563	return NULL;
1564	}
1565
1566
1567	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1568	{
1569	RT_ZERO(*pFeatures);
1570	if (cLeaves >= 2)
1571	{
1572	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1573	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1574	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1575	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1576	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1577	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1578
1579	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1580	pStd0Leaf->uEbx,
1581	pStd0Leaf->uEcx,
1582	pStd0Leaf->uEdx);
1583	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1584	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1585	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1586	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1587	pFeatures->uFamily,
1588	pFeatures->uModel,
1589	pFeatures->uStepping);
1590
1591	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1592	if (pLeaf)
1593	pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff;
1594	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1595	pFeatures->cMaxPhysAddrWidth = 36;
1596	else
1597	pFeatures->cMaxPhysAddrWidth = 32;
1598
1599	/* Standard features. */
1600	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1601	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1602	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1603	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1604	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1605	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1606	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1607	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1608	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1609	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1610	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1611	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1612	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1613	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1614	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1615	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1616	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1617	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1618	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1619	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1620	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1621	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1622
1623	/* Structured extended features. */
1624	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1625	if (pSxfLeaf0)
1626	{
1627	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEcx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1628	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEcx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1629	}
1630
1631	/* MWAIT/MONITOR leaf. */
1632	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1633	if (pMWaitLeaf)
1634	{
1635	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1636	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1637	}
1638
1639	/* Extended features. */
1640	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1641	if (pExtLeaf)
1642	{
1643	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1644	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1645	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1646	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1647	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1648	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1649	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1650	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1651	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1652	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1653	}
1654
1655	if ( pExtLeaf
1656	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1657	{
1658	/* AMD features. */
1659	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1660	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1661	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1662	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1663	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1664	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1665	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1666	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1667	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1668	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1669	}
1670
1671	/*
1672	* Quirks.
1673	*/
1674	pFeatures->fLeakyFxSR = pExtLeaf
1675	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1676	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1677	&& pFeatures->uFamily >= 6 /* K7 and up */;
1678
1679	/*
1680	* Max extended (/FPU) state.
1681	*/
1682	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1683	if (pFeatures->fXSaveRstor)
1684	{
1685	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1686	if (pXStateLeaf0)
1687	{
1688	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1689	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1690	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1691	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1692	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1693	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1694	{
1695	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1696
1697	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1698	if ( pXStateLeaf1
1699	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1700	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1701	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1702	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEbx;
1703	}
1704	else
1705	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1706	pFeatures->fXSaveRstor = 0);
1707	}
1708	else
1709	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1710	pFeatures->fXSaveRstor = 0);
1711	}
1712	}
1713	else
1714	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1715	return VINF_SUCCESS;
1716	}
1717
1718
1719	/*
1720	*
1721	* Init related code.
1722	* Init related code.
1723	* Init related code.
1724	*
1725	*
1726	*/
1727	#ifdef VBOX_IN_VMM
1728
1729
1730	/**
1731	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1732	*
1733	* This ignores the fSubLeafMask.
1734	*
1735	* @returns Pointer to the matching leaf, or NULL if not found.
1736	* @param paLeaves The CPUID leaves to search. This is sorted.
1737	* @param cLeaves The number of leaves in the array.
1738	* @param uLeaf The leaf to locate.
1739	* @param uSubLeaf The subleaf to locate.
1740	*/
1741	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1742	{
1743	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1744	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1745	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1746	if (iEnd)
1747	{
1748	uint32_t iBegin = 0;
1749	for (;;)
1750	{
1751	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1752	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1753	if (uNeedle < uCur)
1754	{
1755	if (i > iBegin)
1756	iEnd = i;
1757	else
1758	break;
1759	}
1760	else if (uNeedle > uCur)
1761	{
1762	if (i + 1 < iEnd)
1763	iBegin = i + 1;
1764	else
1765	break;
1766	}
1767	else
1768	return &paLeaves[i];
1769	}
1770	}
1771	return NULL;
1772	}
1773
1774
1775	/**
1776	* Loads MSR range overrides.
1777	*
1778	* This must be called before the MSR ranges are moved from the normal heap to
1779	* the hyper heap!
1780	*
1781	* @returns VBox status code (VMSetError called).
1782	* @param pVM The cross context VM structure.
1783	* @param pMsrNode The CFGM node with the MSR overrides.
1784	*/
1785	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1786	{
1787	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1788	{
1789	/*
1790	* Assemble a valid MSR range.
1791	*/
1792	CPUMMSRRANGE MsrRange;
1793	MsrRange.offCpumCpu = 0;
1794	MsrRange.fReserved = 0;
1795
1796	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1797	if (RT_FAILURE(rc))
1798	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1799
1800	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1801	if (RT_FAILURE(rc))
1802	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1803	MsrRange.szName, rc);
1804
1805	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1806	if (RT_FAILURE(rc))
1807	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1808	MsrRange.szName, rc);
1809
1810	char szType[32];
1811	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1812	if (RT_FAILURE(rc))
1813	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1814	MsrRange.szName, rc);
1815	if (!RTStrICmp(szType, "FixedValue"))
1816	{
1817	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1818	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1819
1820	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1821	if (RT_FAILURE(rc))
1822	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1823	MsrRange.szName, rc);
1824
1825	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1826	if (RT_FAILURE(rc))
1827	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1828	MsrRange.szName, rc);
1829
1830	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1831	if (RT_FAILURE(rc))
1832	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1833	MsrRange.szName, rc);
1834	}
1835	else
1836	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1837	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1838
1839	/*
1840	* Insert the range into the table (replaces/splits/shrinks existing
1841	* MSR ranges).
1842	*/
1843	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1844	&MsrRange);
1845	if (RT_FAILURE(rc))
1846	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
1847	}
1848
1849	return VINF_SUCCESS;
1850	}
1851
1852
1853	/**
1854	* Loads CPUID leaf overrides.
1855	*
1856	* This must be called before the CPUID leaves are moved from the normal
1857	* heap to the hyper heap!
1858	*
1859	* @returns VBox status code (VMSetError called).
1860	* @param pVM The cross context VM structure.
1861	* @param pParentNode The CFGM node with the CPUID leaves.
1862	* @param pszLabel How to label the overrides we're loading.
1863	*/
1864	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
1865	{
1866	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1867	{
1868	/*
1869	* Get the leaf and subleaf numbers.
1870	*/
1871	char szName[128];
1872	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
1873	if (RT_FAILURE(rc))
1874	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
1875
1876	/* The leaf number is either specified directly or thru the node name. */
1877	uint32_t uLeaf;
1878	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
1879	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1880	{
1881	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
1882	if (rc != VINF_SUCCESS)
1883	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
1884	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
1885	}
1886	else if (RT_FAILURE(rc))
1887	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
1888	pszLabel, szName, rc);
1889
1890	uint32_t uSubLeaf;
1891	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
1892	if (RT_FAILURE(rc))
1893	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
1894	pszLabel, szName, rc);
1895
1896	uint32_t fSubLeafMask;
1897	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
1898	if (RT_FAILURE(rc))
1899	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
1900	pszLabel, szName, rc);
1901
1902	/*
1903	* Look up the specified leaf, since the output register values
1904	* defaults to any existing values. This allows overriding a single
1905	* register, without needing to know the other values.
1906	*/
1907	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
1908	CPUMCPUIDLEAF Leaf;
1909	if (pLeaf)
1910	Leaf = *pLeaf;
1911	else
1912	RT_ZERO(Leaf);
1913	Leaf.uLeaf = uLeaf;
1914	Leaf.uSubLeaf = uSubLeaf;
1915	Leaf.fSubLeafMask = fSubLeafMask;
1916
1917	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
1918	if (RT_FAILURE(rc))
1919	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
1920	pszLabel, szName, rc);
1921	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
1922	if (RT_FAILURE(rc))
1923	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
1924	pszLabel, szName, rc);
1925	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
1926	if (RT_FAILURE(rc))
1927	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
1928	pszLabel, szName, rc);
1929	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
1930	if (RT_FAILURE(rc))
1931	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
1932	pszLabel, szName, rc);
1933
1934	/*
1935	* Insert the leaf into the table (replaces existing ones).
1936	*/
1937	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1938	&Leaf);
1939	if (RT_FAILURE(rc))
1940	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
1941	}
1942
1943	return VINF_SUCCESS;
1944	}
1945
1946
1947
1948	/**
1949	* Fetches overrides for a CPUID leaf.
1950	*
1951	* @returns VBox status code.
1952	* @param pLeaf The leaf to load the overrides into.
1953	* @param pCfgNode The CFGM node containing the overrides
1954	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
1955	* @param iLeaf The CPUID leaf number.
1956	*/
1957	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
1958	{
1959	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
1960	if (pLeafNode)
1961	{
1962	uint32_t u32;
1963	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
1964	if (RT_SUCCESS(rc))
1965	pLeaf->uEax = u32;
1966	else
1967	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1968
1969	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
1970	if (RT_SUCCESS(rc))
1971	pLeaf->uEbx = u32;
1972	else
1973	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1974
1975	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
1976	if (RT_SUCCESS(rc))
1977	pLeaf->uEcx = u32;
1978	else
1979	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1980
1981	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
1982	if (RT_SUCCESS(rc))
1983	pLeaf->uEdx = u32;
1984	else
1985	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1986
1987	}
1988	return VINF_SUCCESS;
1989	}
1990
1991
1992	/**
1993	* Load the overrides for a set of CPUID leaves.
1994	*
1995	* @returns VBox status code.
1996	* @param paLeaves The leaf array.
1997	* @param cLeaves The number of leaves.
1998	* @param uStart The start leaf number.
1999	* @param pCfgNode The CFGM node containing the overrides
2000	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2001	*/
2002	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2003	{
2004	for (uint32_t i = 0; i < cLeaves; i++)
2005	{
2006	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2007	if (RT_FAILURE(rc))
2008	return rc;
2009	}
2010
2011	return VINF_SUCCESS;
2012	}
2013
2014	/**
2015	* Init a set of host CPUID leaves.
2016	*
2017	* @returns VBox status code.
2018	* @param paLeaves The leaf array.
2019	* @param cLeaves The number of leaves.
2020	* @param uStart The start leaf number.
2021	* @param pCfgNode The /CPUM/HostCPUID/ node.
2022	*/
2023	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2024	{
2025	/* Using the ECX variant for all of them can't hurt... */
2026	for (uint32_t i = 0; i < cLeaves; i++)
2027	ASMCpuIdExSlow(uStart + i, 0, 0, 0, &paLeaves[i].uEax, &paLeaves[i].uEbx, &paLeaves[i].uEcx, &paLeaves[i].uEdx);
2028
2029	/* Load CPUID leaf override; we currently don't care if the user
2030	specifies features the host CPU doesn't support. */
2031	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
2032	}
2033
2034
2035	/**
2036	* Installs the CPUID leaves and explods the data into structures like
2037	* GuestFeatures and CPUMCTX::aoffXState.
2038	*
2039	* @returns VBox status code.
2040	* @param pVM The cross context VM structure.
2041	* @param pCpum The CPUM part of @a VM.
2042	* @param paLeaves The leaves. These will be copied (but not freed).
2043	* @param cLeaves The number of leaves.
2044	*/
2045	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
2046	{
2047	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2048
2049	/*
2050	* Install the CPUID information.
2051	*/
2052	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2053	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2054
2055	AssertLogRelRCReturn(rc, rc);
2056	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2057	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2058	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2059	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2060	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2061
2062	/*
2063	* Update the default CPUID leaf if necessary.
2064	*/
2065	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2066	{
2067	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2068	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2069	{
2070	/* We don't use CPUID(0).eax here because of the NT hack that only
2071	changes that value without actually removing any leaves. */
2072	uint32_t i = 0;
2073	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2074	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2075	{
2076	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2077	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2078	i++;
2079	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2080	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2081	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2082	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2083	}
2084	break;
2085	}
2086	default:
2087	break;
2088	}
2089
2090	/*
2091	* Explode the guest CPU features.
2092	*/
2093	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
2094	AssertLogRelRCReturn(rc, rc);
2095
2096	/*
2097	* Adjust the scalable bus frequency according to the CPUID information
2098	* we're now using.
2099	*/
2100	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2101	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2102	? UINT64_C(100000000) /* 100MHz */
2103	: UINT64_C(133333333); /* 133MHz */
2104
2105	/*
2106	* Populate the legacy arrays. Currently used for everything, later only
2107	* for patch manager.
2108	*/
2109	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2110	{
2111	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2112	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2113	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2114	};
2115	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2116	{
2117	uint32_t cLeft = aOldRanges[i].cCpuIds;
2118	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2119	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2120	while (cLeft-- > 0)
2121	{
2122	uLeaf--;
2123	pLegacyLeaf--;
2124
2125	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2126	if (pLeaf)
2127	{
2128	pLegacyLeaf->uEax = pLeaf->uEax;
2129	pLegacyLeaf->uEbx = pLeaf->uEbx;
2130	pLegacyLeaf->uEcx = pLeaf->uEcx;
2131	pLegacyLeaf->uEdx = pLeaf->uEdx;
2132	}
2133	else
2134	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2135	}
2136	}
2137
2138	/*
2139	* Configure XSAVE offsets according to the CPUID info.
2140	*/
2141	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2142	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2143	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2144	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2145	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2146	{
2147	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2148	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2149	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2150	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2151	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2152	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2153	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2154	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2155	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2156	pCpum->GuestFeatures.cbMaxExtendedState),
2157	VERR_CPUM_IPE_1);
2158	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2159	}
2160	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2161
2162	/* Copy the CPU #0 data to the other CPUs. */
2163	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2164	{
2165	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2166	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2167	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2168	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2169	}
2170
2171	return VINF_SUCCESS;
2172	}
2173
2174
2175	/** @name Instruction Set Extension Options
2176	* @{ */
2177	/** Configuration option type (extended boolean, really). */
2178	typedef uint8_t CPUMISAEXTCFG;
2179	/** Always disable the extension. */
2180	#define CPUMISAEXTCFG_DISABLED false
2181	/** Enable the extension if it's supported by the host CPU. */
2182	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2183	/** Enable the extension if it's supported by the host CPU, but don't let
2184	* the portable CPUID feature disable it. */
2185	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2186	/** Always enable the extension. */
2187	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2188	/** @} */
2189
2190	/**
2191	* CPUID Configuration (from CFGM).
2192	*
2193	* @remarks The members aren't document since we would only be duplicating the
2194	* \@cfgm entries in cpumR3CpuIdReadConfig.
2195	*/
2196	typedef struct CPUMCPUIDCONFIG
2197	{
2198	bool fNt4LeafLimit;
2199	bool fInvariantTsc;
2200
2201	CPUMISAEXTCFG enmCmpXchg16b;
2202	CPUMISAEXTCFG enmMonitor;
2203	CPUMISAEXTCFG enmMWaitExtensions;
2204	CPUMISAEXTCFG enmSse41;
2205	CPUMISAEXTCFG enmSse42;
2206	CPUMISAEXTCFG enmAvx;
2207	CPUMISAEXTCFG enmAvx2;
2208	CPUMISAEXTCFG enmXSave;
2209	CPUMISAEXTCFG enmAesNi;
2210	CPUMISAEXTCFG enmPClMul;
2211	CPUMISAEXTCFG enmPopCnt;
2212	CPUMISAEXTCFG enmMovBe;
2213	CPUMISAEXTCFG enmRdRand;
2214	CPUMISAEXTCFG enmRdSeed;
2215	CPUMISAEXTCFG enmCLFlushOpt;
2216
2217	CPUMISAEXTCFG enmAbm;
2218	CPUMISAEXTCFG enmSse4A;
2219	CPUMISAEXTCFG enmMisAlnSse;
2220	CPUMISAEXTCFG enm3dNowPrf;
2221	CPUMISAEXTCFG enmAmdExtMmx;
2222
2223	uint32_t uMaxStdLeaf;
2224	uint32_t uMaxExtLeaf;
2225	uint32_t uMaxCentaurLeaf;
2226	uint32_t uMaxIntelFamilyModelStep;
2227	char szCpuName[128];
2228	} CPUMCPUIDCONFIG;
2229	/** Pointer to CPUID config (from CFGM). */
2230	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2231
2232
2233	/**
2234	* Insert hypervisor identification leaves.
2235	*
2236	* We only return minimal information, primarily ensuring that the
2237	* 0x40000000 function returns 0x40000001 and identifying ourselves.
2238	* Hypervisor-specific interface is supported through GIM which will
2239	* modify these leaves if required depending on the GIM provider.
2240	*
2241	* @returns VBox status code.
2242	* @param pCpum The CPUM instance data.
2243	* @param pConfig The CPUID configuration we've read from CFGM.
2244	*/
2245	static int cpumR3CpuIdPlantHypervisorLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2246	{
2247	CPUMCPUIDLEAF NewLeaf;
2248	NewLeaf.uLeaf = UINT32_C(0x40000000);
2249	NewLeaf.uSubLeaf = 0;
2250	NewLeaf.fSubLeafMask = 0;
2251	NewLeaf.uEax = UINT32_C(0x40000001);
2252	NewLeaf.uEbx = 0x786f4256 /* 'VBox' */;
2253	NewLeaf.uEcx = 0x786f4256 /* 'VBox' */;
2254	NewLeaf.uEdx = 0x786f4256 /* 'VBox' */;
2255	NewLeaf.fFlags = 0;
2256	int rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
2257	AssertLogRelRCReturn(rc, rc);
2258
2259	NewLeaf.uLeaf = UINT32_C(0x40000001);
2260	NewLeaf.uEax = 0x656e6f6e; /* 'none' */
2261	NewLeaf.uEbx = 0;
2262	NewLeaf.uEcx = 0;
2263	NewLeaf.uEdx = 0;
2264	NewLeaf.fFlags = 0;
2265	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
2266	AssertLogRelRCReturn(rc, rc);
2267
2268	return VINF_SUCCESS;
2269	}
2270
2271
2272	/**
2273	* Mini CPU selection support for making Mac OS X happy.
2274	*
2275	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2276	*
2277	* @param pCpum The CPUM instance data.
2278	* @param pConfig The CPUID configuration we've read from CFGM.
2279	*/
2280	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2281	{
2282	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2283	{
2284	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2285	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2286	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2287	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2288	0);
2289	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2290	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2291	{
2292	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2293	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2294	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2295	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2296	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2297	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2298	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2299	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2300	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2301	pStdFeatureLeaf->uEax = uNew;
2302	}
2303	}
2304	}
2305
2306
2307
2308	/**
2309	* Limit it the number of entries, zapping the remainder.
2310	*
2311	* The limits are masking off stuff about power saving and similar, this
2312	* is perhaps a bit crudely done as there is probably some relatively harmless
2313	* info too in these leaves (like words about having a constant TSC).
2314	*
2315	* @param pCpum The CPUM instance data.
2316	* @param pConfig The CPUID configuration we've read from CFGM.
2317	*/
2318	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2319	{
2320	/*
2321	* Standard leaves.
2322	*/
2323	uint32_t uSubLeaf = 0;
2324	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2325	if (pCurLeaf)
2326	{
2327	uint32_t uLimit = pCurLeaf->uEax;
2328	if (uLimit <= UINT32_C(0x000fffff))
2329	{
2330	if (uLimit > pConfig->uMaxStdLeaf)
2331	{
2332	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2333	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2334	uLimit + 1, UINT32_C(0x000fffff));
2335	}
2336
2337	/* NT4 hack, no zapping of extra leaves here. */
2338	if (pConfig->fNt4LeafLimit && uLimit > 3)
2339	pCurLeaf->uEax = uLimit = 3;
2340
2341	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2342	pCurLeaf->uEax = uLimit;
2343	}
2344	else
2345	{
2346	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2347	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2348	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2349	}
2350	}
2351
2352	/*
2353	* Extended leaves.
2354	*/
2355	uSubLeaf = 0;
2356	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2357	if (pCurLeaf)
2358	{
2359	uint32_t uLimit = pCurLeaf->uEax;
2360	if ( uLimit >= UINT32_C(0x80000000)
2361	&& uLimit <= UINT32_C(0x800fffff))
2362	{
2363	if (uLimit > pConfig->uMaxExtLeaf)
2364	{
2365	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2366	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2367	uLimit + 1, UINT32_C(0x800fffff));
2368	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2369	pCurLeaf->uEax = uLimit;
2370	}
2371	}
2372	else
2373	{
2374	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2375	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2376	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2377	}
2378	}
2379
2380	/*
2381	* Centaur leaves (VIA).
2382	*/
2383	uSubLeaf = 0;
2384	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2385	if (pCurLeaf)
2386	{
2387	uint32_t uLimit = pCurLeaf->uEax;
2388	if ( uLimit >= UINT32_C(0xc0000000)
2389	&& uLimit <= UINT32_C(0xc00fffff))
2390	{
2391	if (uLimit > pConfig->uMaxCentaurLeaf)
2392	{
2393	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2394	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2395	uLimit + 1, UINT32_C(0xcfffffff));
2396	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2397	pCurLeaf->uEax = uLimit;
2398	}
2399	}
2400	else
2401	{
2402	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2403	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2404	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2405	}
2406	}
2407	}
2408
2409
2410	/**
2411	* Clears a CPUID leaf and all sub-leaves (to zero).
2412	*
2413	* @param pCpum The CPUM instance data.
2414	* @param uLeaf The leaf to clear.
2415	*/
2416	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2417	{
2418	uint32_t uSubLeaf = 0;
2419	PCPUMCPUIDLEAF pCurLeaf;
2420	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2421	{
2422	pCurLeaf->uEax = 0;
2423	pCurLeaf->uEbx = 0;
2424	pCurLeaf->uEcx = 0;
2425	pCurLeaf->uEdx = 0;
2426	uSubLeaf++;
2427	}
2428	}
2429
2430
2431	/**
2432	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2433	* the given leaf.
2434	*
2435	* @returns pLeaf.
2436	* @param pCpum The CPUM instance data.
2437	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2438	*/
2439	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2440	{
2441	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2442	if (pLeaf->fSubLeafMask != 0)
2443	{
2444	/*
2445	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2446	* Log everything while we're at it.
2447	*/
2448	LogRel(("CPUM:\n"
2449	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2450	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2451	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2452	for (;;)
2453	{
2454	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2455	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2456	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2457	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2458	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2459	break;
2460	pSubLeaf++;
2461	}
2462	LogRel(("CPUM:\n"));
2463
2464	/*
2465	* Remove the offending sub-leaves.
2466	*/
2467	if (pSubLeaf != pLeaf)
2468	{
2469	if (pSubLeaf != pLast)
2470	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2471	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2472	}
2473
2474	/*
2475	* Convert the first sub-leaf into a single leaf.
2476	*/
2477	pLeaf->uSubLeaf = 0;
2478	pLeaf->fSubLeafMask = 0;
2479	}
2480	return pLeaf;
2481	}
2482
2483
2484	/**
2485	* Sanitizes and adjust the CPUID leaves.
2486	*
2487	* Drop features that aren't virtualized (or virtualizable). Adjust information
2488	* and capabilities to fit the virtualized hardware. Remove information the
2489	* guest shouldn't have (because it's wrong in the virtual world or because it
2490	* gives away host details) or that we don't have documentation for and no idea
2491	* what means.
2492	*
2493	* @returns VBox status code.
2494	* @param pVM The cross context VM structure (for cCpus).
2495	* @param pCpum The CPUM instance data.
2496	* @param pConfig The CPUID configuration we've read from CFGM.
2497	*/
2498	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2499	{
2500	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2501	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2502	{ \
2503	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2504	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2505	}
2506	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2507	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2508	{ \
2509	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2510	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2511	}
2512	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2513	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2514	&& ((a_pLeafReg) & (fBitMask)) \
2515	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2516	{ \
2517	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2518	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2519	}
2520	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2521
2522	/* Cpuid 1:
2523	* EAX: CPU model, family and stepping.
2524	*
2525	* ECX + EDX: Supported features. Only report features we can support.
2526	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2527	* options may require adjusting (i.e. stripping what was enabled).
2528	*
2529	* EBX: Branding, CLFLUSH line size, logical processors per package and
2530	* initial APIC ID.
2531	*/
2532	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2533	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2534	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2535
2536	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2537	\| X86_CPUID_FEATURE_EDX_VME
2538	\| X86_CPUID_FEATURE_EDX_DE
2539	\| X86_CPUID_FEATURE_EDX_PSE
2540	\| X86_CPUID_FEATURE_EDX_TSC
2541	\| X86_CPUID_FEATURE_EDX_MSR
2542	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2543	\| X86_CPUID_FEATURE_EDX_MCE
2544	\| X86_CPUID_FEATURE_EDX_CX8
2545	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2546	//\| RT_BIT_32(10) - not defined
2547	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2548	//\| X86_CPUID_FEATURE_EDX_SEP
2549	\| X86_CPUID_FEATURE_EDX_MTRR
2550	\| X86_CPUID_FEATURE_EDX_PGE
2551	\| X86_CPUID_FEATURE_EDX_MCA
2552	\| X86_CPUID_FEATURE_EDX_CMOV
2553	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2554	\| X86_CPUID_FEATURE_EDX_PSE36
2555	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2556	\| X86_CPUID_FEATURE_EDX_CLFSH
2557	//\| RT_BIT_32(20) - not defined
2558	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2559	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2560	\| X86_CPUID_FEATURE_EDX_MMX
2561	\| X86_CPUID_FEATURE_EDX_FXSR
2562	\| X86_CPUID_FEATURE_EDX_SSE
2563	\| X86_CPUID_FEATURE_EDX_SSE2
2564	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2565	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading/cores - see below.
2566	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2567	//\| RT_BIT_32(30) - not defined
2568	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2569	;
2570	pStdFeatureLeaf->uEcx &= 0
2571	\| X86_CPUID_FEATURE_ECX_SSE3
2572	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2573	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2574	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2575	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2576	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2577	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized yet.
2578	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2579	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2580	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2581	\| X86_CPUID_FEATURE_ECX_SSSE3
2582	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2583	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2584	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2585	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2586	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2587	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2588	//\| X86_CPUID_FEATURE_ECX_PCID - not implemented yet.
2589	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2590	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2591	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2592	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2593	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2594	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2595	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2596	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2597	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2598	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2599	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2600	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2601	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2602	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2603	;
2604
2605	if (pCpum->u8PortableCpuIdLevel > 0)
2606	{
2607	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2608	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2609	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2610	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2611	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2612	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2613	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2614	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2615	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2616	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2617	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2618	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2619	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2620	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2621	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2622	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2623	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2624	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2625
2626	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2627	\| X86_CPUID_FEATURE_EDX_PSN
2628	\| X86_CPUID_FEATURE_EDX_DS
2629	\| X86_CPUID_FEATURE_EDX_ACPI
2630	\| X86_CPUID_FEATURE_EDX_SS
2631	\| X86_CPUID_FEATURE_EDX_TM
2632	\| X86_CPUID_FEATURE_EDX_PBE
2633	)));
2634	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2635	\| X86_CPUID_FEATURE_ECX_CPLDS
2636	\| X86_CPUID_FEATURE_ECX_VMX
2637	\| X86_CPUID_FEATURE_ECX_SMX
2638	\| X86_CPUID_FEATURE_ECX_EST
2639	\| X86_CPUID_FEATURE_ECX_TM2
2640	\| X86_CPUID_FEATURE_ECX_CNTXID
2641	\| X86_CPUID_FEATURE_ECX_FMA
2642	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2643	\| X86_CPUID_FEATURE_ECX_PDCM
2644	\| X86_CPUID_FEATURE_ECX_DCA
2645	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2646	)));
2647	}
2648
2649	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2650	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2651	#ifdef VBOX_WITH_MULTI_CORE
2652	if (pVM->cCpus > 1)
2653	{
2654	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2655	core times the number of CPU cores per processor */
2656	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2657	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
2658	}
2659	#endif
2660
2661	/* Force standard feature bits. */
2662	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2663	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2664	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2665	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2666	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2667	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2668	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2669	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2670	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2671	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2672	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2673	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2674	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2675	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2676	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2677	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2678	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2679	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2680	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2681	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2682	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2683	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2684
2685	pStdFeatureLeaf = NULL; /* Must refetch! */
2686
2687	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2688	* AMD:
2689	* EAX: CPU model, family and stepping.
2690	*
2691	* ECX + EDX: Supported features. Only report features we can support.
2692	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2693	* options may require adjusting (i.e. stripping what was enabled).
2694	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2695	*
2696	* EBX: Branding ID and package type (or reserved).
2697	*
2698	* Intel and probably most others:
2699	* EAX: 0
2700	* EBX: 0
2701	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2702	*/
2703	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2704	if (pExtFeatureLeaf)
2705	{
2706	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2707
2708	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2709	\| X86_CPUID_AMD_FEATURE_EDX_VME
2710	\| X86_CPUID_AMD_FEATURE_EDX_DE
2711	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2712	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2713	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2714	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2715	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2716	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2717	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2718	//\| RT_BIT_32(10) - reserved
2719	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2720	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2721	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2722	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2723	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2724	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2725	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2726	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2727	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2728	//\| RT_BIT_32(18) - reserved
2729	//\| RT_BIT_32(19) - reserved
2730	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2731	//\| RT_BIT_32(21) - reserved
2732	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2733	\| X86_CPUID_AMD_FEATURE_EDX_MMX
2734	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
2735	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
2736	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2737	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2738	//\| RT_BIT_32(28) - reserved
2739	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2740	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2741	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
2742	;
2743	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2744	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2745	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
2746	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2747	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
2748	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2749	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2750	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2751	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2752	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2753	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2754	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
2755	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
2756	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2757	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
2758	//\| RT_BIT_32(14) - reserved
2759	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2760	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2761	//\| RT_BIT_32(17) - reserved
2762	//\| RT_BIT_32(18) - reserved
2763	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2764	//\| RT_BIT_32(20) - reserved
2765	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2766	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2767	//\| RT_BIT_32(23) - reserved
2768	//\| RT_BIT_32(24) - reserved
2769	//\| RT_BIT_32(25) - reserved
2770	//\| RT_BIT_32(26) - reserved
2771	//\| RT_BIT_32(27) - reserved
2772	//\| RT_BIT_32(28) - reserved
2773	//\| RT_BIT_32(29) - reserved
2774	//\| RT_BIT_32(30) - reserved
2775	//\| RT_BIT_32(31) - reserved
2776	;
2777	#ifdef VBOX_WITH_MULTI_CORE
2778	if ( pVM->cCpus > 1
2779	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2780	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2781	#endif
2782
2783	if (pCpum->u8PortableCpuIdLevel > 0)
2784	{
2785	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2786	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2787	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2788	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2789	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2790	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2791	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2792	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2793	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2794	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2795	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2796	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2797	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2798	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2799	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2800
2801	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2802	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2803	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2804	\| X86_CPUID_AMD_FEATURE_ECX_IBS
2805	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2806	\| X86_CPUID_AMD_FEATURE_ECX_WDT
2807	\| X86_CPUID_AMD_FEATURE_ECX_LWP
2808	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
2809	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2810	\| UINT32_C(0xff964000)
2811	)));
2812	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2813	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2814	\| RT_BIT(18)
2815	\| RT_BIT(19)
2816	\| RT_BIT(21)
2817	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2818	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2819	\| RT_BIT(28)
2820	)));
2821	}
2822
2823	/* Force extended feature bits. */
2824	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2825	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
2826	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2827	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2828	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2829	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2830	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2831	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2832	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2833	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2834	}
2835	pExtFeatureLeaf = NULL; /* Must refetch! */
2836
2837
2838	/* Cpuid 2:
2839	* Intel: (Nondeterministic) Cache and TLB information
2840	* AMD: Reserved
2841	* VIA: Reserved
2842	* Safe to expose.
2843	*/
2844	uint32_t uSubLeaf = 0;
2845	PCPUMCPUIDLEAF pCurLeaf;
2846	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2847	{
2848	if ((pCurLeaf->uEax & 0xff) > 1)
2849	{
2850	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2851	pCurLeaf->uEax &= UINT32_C(0xffffff01);
2852	}
2853	uSubLeaf++;
2854	}
2855
2856	/* Cpuid 3:
2857	* Intel: EAX, EBX - reserved (transmeta uses these)
2858	* ECX, EDX - Processor Serial Number if available, otherwise reserved
2859	* AMD: Reserved
2860	* VIA: Reserved
2861	* Safe to expose
2862	*/
2863	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2864	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
2865	{
2866	uSubLeaf = 0;
2867	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
2868	{
2869	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2870	if (pCpum->u8PortableCpuIdLevel > 0)
2871	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2872	uSubLeaf++;
2873	}
2874	}
2875
2876	/* Cpuid 4 + ECX:
2877	* Intel: Deterministic Cache Parameters Leaf.
2878	* AMD: Reserved
2879	* VIA: Reserved
2880	* Safe to expose, except for EAX:
2881	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
2882	* Bits 31-26: Maximum number of processor cores in this physical package**
2883	* Note: These SMP values are constant regardless of ECX
2884	*/
2885	uSubLeaf = 0;
2886	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
2887	{
2888	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
2889	#ifdef VBOX_WITH_MULTI_CORE
2890	if ( pVM->cCpus > 1
2891	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2892	{
2893	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
2894	/* One logical processor with possibly multiple cores. */
2895	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
2896	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
2897	}
2898	#endif
2899	uSubLeaf++;
2900	}
2901
2902	/* Cpuid 5: Monitor/mwait Leaf
2903	* Intel: ECX, EDX - reserved
2904	* EAX, EBX - Smallest and largest monitor line size
2905	* AMD: EDX - reserved
2906	* EAX, EBX - Smallest and largest monitor line size
2907	* ECX - extensions (ignored for now)
2908	* VIA: Reserved
2909	* Safe to expose
2910	*/
2911	uSubLeaf = 0;
2912	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
2913	{
2914	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2915	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
2916	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2917
2918	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2919	if (pConfig->enmMWaitExtensions)
2920	{
2921	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
2922	/** @todo: for now we just expose host's MWAIT C-states, although conceptually
2923	it shall be part of our power management virtualization model */
2924	#if 0
2925	/* MWAIT sub C-states */
2926	pCurLeaf->uEdx =
2927	(0 << 0) /* 0 in C0 */ \|
2928	(2 << 4) /* 2 in C1 */ \|
2929	(2 << 8) /* 2 in C2 */ \|
2930	(2 << 12) /* 2 in C3 */ \|
2931	(0 << 16) /* 0 in C4 */
2932	;
2933	#endif
2934	}
2935	else
2936	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2937	uSubLeaf++;
2938	}
2939
2940	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
2941	* Intel: Various stuff.
2942	* AMD: EAX, EBX, EDX - reserved.
2943	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
2944	* present. Same as intel.
2945	* VIA: ??
2946	*
2947	* We clear everything here for now.
2948	*/
2949	cpumR3CpuIdZeroLeaf(pCpum, 6);
2950
2951	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
2952	* EAX: Number of sub leaves.
2953	* EBX+ECX+EDX: Feature flags
2954	*
2955	* We only have documentation for one sub-leaf, so clear all other (no need
2956	* to remove them as such, just set them to zero).
2957	*
2958	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2959	* options may require adjusting (i.e. stripping what was enabled).
2960	*/
2961	uSubLeaf = 0;
2962	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
2963	{
2964	switch (uSubLeaf)
2965	{
2966	case 0:
2967	{
2968	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
2969	pCurLeaf->uEbx &= 0
2970	//\| X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
2971	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
2972	//\| RT_BIT(2) - reserved
2973	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
2974	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
2975	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
2976	//\| RT_BIT(6) - reserved
2977	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
2978	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
2979	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
2980	//\| X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
2981	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
2982	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
2983	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
2984	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
2985	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
2986	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
2987	//\| RT_BIT(17) - reserved
2988	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
2989	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
2990	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
2991	//\| RT_BIT(21) - reserved
2992	//\| RT_BIT(22) - reserved
2993	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
2994	//\| RT_BIT(24) - reserved
2995	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
2996	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
2997	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
2998	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
2999	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3000	//\| RT_BIT(30) - reserved
3001	//\| RT_BIT(31) - reserved
3002	;
3003	pCurLeaf->uEcx &= 0
3004	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3005	;
3006	pCurLeaf->uEdx &= 0;
3007
3008	if (pCpum->u8PortableCpuIdLevel > 0)
3009	{
3010	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
3011	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3012	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3013	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3014	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
3015	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3016	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3017	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3018	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3019	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3020	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3021	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3022	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3023	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3024	}
3025
3026	/* Force standard feature bits. */
3027	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3028	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3029	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3030	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3031	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3032	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3033	break;
3034	}
3035
3036	default:
3037	/* Invalid index, all values are zero. */
3038	pCurLeaf->uEax = 0;
3039	pCurLeaf->uEbx = 0;
3040	pCurLeaf->uEcx = 0;
3041	pCurLeaf->uEdx = 0;
3042	break;
3043	}
3044	uSubLeaf++;
3045	}
3046
3047	/* Cpuid 8: Marked as reserved by Intel and AMD.
3048	* We zero this since we don't know what it may have been used for.
3049	*/
3050	cpumR3CpuIdZeroLeaf(pCpum, 8);
3051
3052	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3053	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3054	* EBX, ECX, EDX - reserved.
3055	* AMD: Reserved
3056	* VIA: ??
3057	*
3058	* We zero this.
3059	*/
3060	cpumR3CpuIdZeroLeaf(pCpum, 9);
3061
3062	/* Cpuid 0xa: Architectural Performance Monitor Features
3063	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3064	* EBX, ECX, EDX - reserved.
3065	* AMD: Reserved
3066	* VIA: ??
3067	*
3068	* We zero this, for now at least.
3069	*/
3070	cpumR3CpuIdZeroLeaf(pCpum, 10);
3071
3072	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3073	* Intel: EAX - APCI ID shift right for next level.
3074	* EBX - Factory configured cores/threads at this level.
3075	* ECX - Level number (same as input) and level type (1,2,0).
3076	* EDX - Extended initial APIC ID.
3077	* AMD: Reserved
3078	* VIA: ??
3079	*/
3080	uSubLeaf = 0;
3081	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3082	{
3083	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3084	{
3085	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3086	if (bLevelType == 1)
3087	{
3088	/* Thread level - we don't do threads at the moment. */
3089	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3090	pCurLeaf->uEbx = 1;
3091	}
3092	else if (bLevelType == 2)
3093	{
3094	/* Core level. */
3095	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3096	#ifdef VBOX_WITH_MULTI_CORE
3097	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3098	pCurLeaf->uEax++;
3099	#endif
3100	pCurLeaf->uEbx = pVM->cCpus;
3101	}
3102	else
3103	{
3104	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3105	pCurLeaf->uEax = 0;
3106	pCurLeaf->uEbx = 0;
3107	pCurLeaf->uEcx = 0;
3108	}
3109	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3110	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3111	}
3112	else
3113	{
3114	pCurLeaf->uEax = 0;
3115	pCurLeaf->uEbx = 0;
3116	pCurLeaf->uEcx = 0;
3117	pCurLeaf->uEdx = 0;
3118	}
3119	uSubLeaf++;
3120	}
3121
3122	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3123	* We zero this since we don't know what it may have been used for.
3124	*/
3125	cpumR3CpuIdZeroLeaf(pCpum, 12);
3126
3127	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3128	* ECX=0: EAX - Valid bits in XCR0[31:0].
3129	* EBX - Maximum state size as per current XCR0 value.
3130	* ECX - Maximum state size for all supported features.
3131	* EDX - Valid bits in XCR0[63:32].
3132	* ECX=1: EAX - Various X-features.
3133	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3134	* ECX - Valid bits in IA32_XSS[31:0].
3135	* EDX - Valid bits in IA32_XSS[63:32].
3136	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3137	* if the bit invalid all four registers are set to zero.
3138	* EAX - The state size for this feature.
3139	* EBX - The state byte offset of this feature.
3140	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3141	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3142	*
3143	* Clear them all as we don't currently implement extended CPU state.
3144	*/
3145	/* Figure out the supported XCR0/XSS mask component. */
3146	uint64_t fGuestXcr0Mask = 0;
3147	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3148	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3149	{
3150	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3151	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3152	fGuestXcr0Mask \|= XSAVE_C_YMM;
3153	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3154	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3155	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3156	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3157	}
3158	pStdFeatureLeaf = NULL;
3159	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3160
3161	/* Work the sub-leaves. */
3162	uint32_t cbXSaveMax = sizeof(X86FXSTATE);
3163	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3164	{
3165	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3166	if (pCurLeaf)
3167	{
3168	if (fGuestXcr0Mask)
3169	{
3170	switch (uSubLeaf)
3171	{
3172	case 0:
3173	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3174	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3175	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3176	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3177	VERR_CPUM_IPE_1);
3178	cbXSaveMax = pCurLeaf->uEcx;
3179	AssertLogRelMsgReturn(cbXSaveMax <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMax >= CPUM_MIN_XSAVE_AREA_SIZE,
3180	("%#x max=%#x\n", cbXSaveMax, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3181	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMax,
3182	("ebx=%#x cbXSaveMax=%#x\n", pCurLeaf->uEbx, cbXSaveMax),
3183	VERR_CPUM_IPE_2);
3184	continue;
3185	case 1:
3186	pCurLeaf->uEax &= 0;
3187	pCurLeaf->uEcx &= 0;
3188	pCurLeaf->uEdx &= 0;
3189	/** @todo what about checking ebx? */
3190	continue;
3191	default:
3192	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3193	{
3194	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMax
3195	&& pCurLeaf->uEax > 0
3196	&& pCurLeaf->uEbx < cbXSaveMax
3197	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3198	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMax,
3199	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3200	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMax),
3201	VERR_CPUM_IPE_2);
3202	AssertLogRel(!(pCurLeaf->uEcx & 1));
3203	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3204	pCurLeaf->uEdx = 0; /* it's reserved... */
3205	continue;
3206	}
3207	break;
3208	}
3209	}
3210
3211	/* Clear the leaf. */
3212	pCurLeaf->uEax = 0;
3213	pCurLeaf->uEbx = 0;
3214	pCurLeaf->uEcx = 0;
3215	pCurLeaf->uEdx = 0;
3216	}
3217	}
3218
3219	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3220	* We zero this since we don't know what it may have been used for.
3221	*/
3222	cpumR3CpuIdZeroLeaf(pCpum, 14);
3223
3224	/* Cpuid 0xf + ECX: Platform qualifity of service monitoring (PQM).
3225	* We zero this as we don't currently virtualize PQM.
3226	*/
3227	cpumR3CpuIdZeroLeaf(pCpum, 15);
3228
3229	/* Cpuid 0x10 + ECX: Platform qualifity of service enforcement (PQE).
3230	* We zero this as we don't currently virtualize PQE.
3231	*/
3232	cpumR3CpuIdZeroLeaf(pCpum, 16);
3233
3234	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3235	* We zero this since we don't know what it may have been used for.
3236	*/
3237	cpumR3CpuIdZeroLeaf(pCpum, 17);
3238
3239	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3240	* We zero this as we don't currently virtualize this.
3241	*/
3242	cpumR3CpuIdZeroLeaf(pCpum, 18);
3243
3244	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3245	* We zero this since we don't know what it may have been used for.
3246	*/
3247	cpumR3CpuIdZeroLeaf(pCpum, 19);
3248
3249	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3250	* We zero this as we don't currently virtualize this.
3251	*/
3252	cpumR3CpuIdZeroLeaf(pCpum, 20);
3253
3254	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3255	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3256	* EAX - denominator (unsigned).
3257	* EBX - numerator (unsigned).
3258	* ECX, EDX - reserved.
3259	* AMD: Reserved / undefined / not implemented.
3260	* VIA: Reserved / undefined / not implemented.
3261	* We zero this as we don't currently virtualize this.
3262	*/
3263	cpumR3CpuIdZeroLeaf(pCpum, 21);
3264
3265	/* Cpuid 0x16: Processor frequency info
3266	* Intel: EAX - Core base frequency in MHz.
3267	* EBX - Core maximum frequency in MHz.
3268	* ECX - Bus (reference) frequency in MHz.
3269	* EDX - Reserved.
3270	* AMD: Reserved / undefined / not implemented.
3271	* VIA: Reserved / undefined / not implemented.
3272	* We zero this as we don't currently virtualize this.
3273	*/
3274	cpumR3CpuIdZeroLeaf(pCpum, 22);
3275
3276	/* Cpuid 0x17..0x10000000: Unknown.
3277	* We don't know these and what they mean, so remove them. */
3278	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3279	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3280
3281
3282	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3283	* We remove all these as we're a hypervisor and must provide our own.
3284	*/
3285	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3286	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3287
3288
3289	/* Cpuid 0x80000000 is harmless. */
3290
3291	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3292
3293	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3294
3295	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3296	* Safe to pass on to the guest.
3297	*
3298	* AMD: 0x800000005 L1 cache information
3299	* 0x800000006 L2/L3 cache information
3300	* Intel: 0x800000005 reserved
3301	* 0x800000006 L2 cache information
3302	* VIA: 0x800000005 TLB and L1 cache information
3303	* 0x800000006 L2 cache information
3304	*/
3305
3306	/* Cpuid 0x800000007: Advanced Power Management Information.
3307	* AMD: EAX: Processor feedback capabilities.
3308	* EBX: RAS capabilites.
3309	* ECX: Advanced power monitoring interface.
3310	* EDX: Enhanced power management capabilities.
3311	* Intel: EAX, EBX, ECX - reserved.
3312	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3313	* VIA: Reserved
3314	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3315	*/
3316	uSubLeaf = 0;
3317	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3318	{
3319	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3320	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3321	{
3322	pCurLeaf->uEdx &= 0
3323	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3324	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3325	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3326	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3327	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3328	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3329	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3330	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3331	#if 0 /*
3332	* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
3333	* Linux kernels blindly assume that the AMD performance counters work
3334	* if this is set for 64 bits guests. (Can't really find a CPUID feature
3335	* bit for them though.)
3336	*/
3337	/** @todo need to recheck this with new MSR emulation. */
3338	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3339	#endif
3340	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3341	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3342	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3343	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3344	\| 0;
3345	}
3346	else
3347	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3348	if (pConfig->fInvariantTsc)
3349	pCurLeaf->uEdx \|= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3350	uSubLeaf++;
3351	}
3352
3353	/* Cpuid 0x80000008:
3354	* AMD: EBX, EDX - reserved
3355	* EAX: Virtual/Physical/Guest address Size
3356	* ECX: Number of cores + APICIdCoreIdSize
3357	* Intel: EAX: Virtual/Physical address Size
3358	* EBX, ECX, EDX - reserved
3359	* VIA: EAX: Virtual/Physical address Size
3360	* EBX, ECX, EDX - reserved
3361	*
3362	* We only expose the virtual+pysical address size to the guest atm.
3363	* On AMD we set the core count, but not the apic id stuff as we're
3364	* currently not doing the apic id assignments in a complatible manner.
3365	*/
3366	uSubLeaf = 0;
3367	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3368	{
3369	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3370	pCurLeaf->uEbx = 0; /* reserved */
3371	pCurLeaf->uEdx = 0; /* reserved */
3372
3373	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3374	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3375	pCurLeaf->uEcx = 0;
3376	#ifdef VBOX_WITH_MULTI_CORE
3377	if ( pVM->cCpus > 1
3378	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3379	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3380	#endif
3381	uSubLeaf++;
3382	}
3383
3384	/* Cpuid 0x80000009: Reserved
3385	* We zero this since we don't know what it may have been used for.
3386	*/
3387	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3388
3389	/* Cpuid 0x8000000a: SVM Information
3390	* AMD: EAX - SVM revision.
3391	* EBX - Number of ASIDs.
3392	* ECX - Reserved.
3393	* EDX - SVM Feature identification.
3394	* We clear all as we currently does not virtualize SVM.
3395	*/
3396	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3397
3398	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3399	* We clear these as we don't know what purpose they might have. */
3400	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3401	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3402
3403	/* Cpuid 0x80000019: TLB configuration
3404	* Seems to be harmless, pass them thru as is. */
3405
3406	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3407	* Strip anything we don't know what is or addresses feature we don't implement. */
3408	uSubLeaf = 0;
3409	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3410	{
3411	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3412	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3413	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3414	;
3415	pCurLeaf->uEbx = 0; /* reserved */
3416	pCurLeaf->uEcx = 0; /* reserved */
3417	pCurLeaf->uEdx = 0; /* reserved */
3418	uSubLeaf++;
3419	}
3420
3421	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3422	* Clear this as we don't currently virtualize this feature. */
3423	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3424
3425	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3426	* Clear this as we don't currently virtualize this feature. */
3427	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3428
3429	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3430	* We need to sanitize the cores per cache (EAX[25:14]).
3431	*
3432	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3433	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3434	* slightly different meaning.
3435	*/
3436	uSubLeaf = 0;
3437	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3438	{
3439	#ifdef VBOX_WITH_MULTI_CORE
3440	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3441	if (cCores > pVM->cCpus)
3442	cCores = pVM->cCpus;
3443	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3444	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3445	#else
3446	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3447	#endif
3448	uSubLeaf++;
3449	}
3450
3451	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3452	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3453	* setup, we have one compute unit with all the cores in it. Single node.
3454	*/
3455	uSubLeaf = 0;
3456	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3457	{
3458	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3459	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3460	{
3461	#ifdef VBOX_WITH_MULTI_CORE
3462	pCurLeaf->uEbx = pVM->cCpus < 0x100
3463	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3464	#else
3465	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3466	#endif
3467	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3468	}
3469	else
3470	{
3471	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3472	pCurLeaf->uEbx = 0; /* Reserved. */
3473	pCurLeaf->uEcx = 0; /* Reserved. */
3474	}
3475	pCurLeaf->uEdx = 0; /* Reserved. */
3476	uSubLeaf++;
3477	}
3478
3479	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3480	* We don't know these and what they mean, so remove them. */
3481	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3482	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3483
3484	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3485	* Just pass it thru for now. */
3486
3487	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3488	* Just pass it thru for now. */
3489
3490	/* Cpuid 0xc0000000: Centaur stuff.
3491	* Harmless, pass it thru. */
3492
3493	/* Cpuid 0xc0000001: Centaur features.
3494	* VIA: EAX - Family, model, stepping.
3495	* EDX - Centaur extended feature flags. Nothing interesting, except may
3496	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3497	* EBX, ECX - reserved.
3498	* We keep EAX but strips the rest.
3499	*/
3500	uSubLeaf = 0;
3501	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3502	{
3503	pCurLeaf->uEbx = 0;
3504	pCurLeaf->uEcx = 0;
3505	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3506	uSubLeaf++;
3507	}
3508
3509	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3510	* We only have fixed stale values, but should be harmless. */
3511
3512	/* Cpuid 0xc0000003: Reserved.
3513	* We zero this since we don't know what it may have been used for.
3514	*/
3515	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3516
3517	/* Cpuid 0xc0000004: Centaur Performance Info.
3518	* We only have fixed stale values, but should be harmless. */
3519
3520
3521	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3522	* We don't know these and what they mean, so remove them. */
3523	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3524	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3525
3526	return VINF_SUCCESS;
3527	#undef PORTABLE_DISABLE_FEATURE_BIT
3528	#undef PORTABLE_CLEAR_BITS_WHEN
3529	}
3530
3531
3532	/**
3533	* Reads a value in /CPUM/IsaExts/ node.
3534	*
3535	* @returns VBox status code (error message raised).
3536	* @param pVM The cross context VM structure. (For errors.)
3537	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3538	* @param pszValueName The value / extension name.
3539	* @param penmValue Where to return the choice.
3540	* @param enmDefault The default choice.
3541	*/
3542	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3543	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3544	{
3545	/*
3546	* Try integer encoding first.
3547	*/
3548	uint64_t uValue;
3549	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3550	if (RT_SUCCESS(rc))
3551	switch (uValue)
3552	{
3553	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3554	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3555	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3556	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3557	default:
3558	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3559	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3560	pszValueName, uValue);
3561	}
3562	/*
3563	* If missing, use default.
3564	*/
3565	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3566	*penmValue = enmDefault;
3567	else
3568	{
3569	if (rc == VERR_CFGM_NOT_INTEGER)
3570	{
3571	/*
3572	* Not an integer, try read it as a string.
3573	*/
3574	char szValue[32];
3575	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3576	if (RT_SUCCESS(rc))
3577	{
3578	RTStrToLower(szValue);
3579	size_t cchValue = strlen(szValue);
3580	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3581	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3582	*penmValue = CPUMISAEXTCFG_DISABLED;
3583	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3584	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3585	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3586	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3587	else if (EQ("portable"))
3588	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3589	else if (EQ("default") \|\| EQ("def"))
3590	*penmValue = enmDefault;
3591	else
3592	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3593	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3594	pszValueName, uValue);
3595	#undef EQ
3596	}
3597	}
3598	if (RT_FAILURE(rc))
3599	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3600	}
3601	return VINF_SUCCESS;
3602	}
3603
3604
3605	/**
3606	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3607	*
3608	* @returns VBox status code (error message raised).
3609	* @param pVM The cross context VM structure. (For errors.)
3610	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3611	* @param pszValueName The value / extension name.
3612	* @param penmValue Where to return the choice.
3613	* @param enmDefault The default choice.
3614	* @param fAllowed Allowed choice. Applied both to the result and to
3615	* the default value.
3616	*/
3617	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3618	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3619	{
3620	int rc;
3621	if (fAllowed)
3622	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3623	else
3624	{
3625	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3626	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3627	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3628	*penmValue = CPUMISAEXTCFG_DISABLED;
3629	}
3630	return rc;
3631	}
3632
3633
3634	/**
3635	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3636	*
3637	* @returns VBox status code (error message raised).
3638	* @param pVM The cross context VM structure. (For errors.)
3639	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3640	* @param pCpumCfg The /CPUM node (can be NULL).
3641	* @param pszValueName The value / extension name.
3642	* @param penmValue Where to return the choice.
3643	* @param enmDefault The default choice.
3644	*/
3645	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3646	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3647	{
3648	if (CFGMR3Exists(pCpumCfg, pszValueName))
3649	{
3650	if (!CFGMR3Exists(pIsaExts, pszValueName))
3651	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3652	else
3653	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3654	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3655	pszValueName, pszValueName);
3656
3657	bool fLegacy;
3658	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3659	if (RT_SUCCESS(rc))
3660	{
3661	*penmValue = fLegacy;
3662	return VINF_SUCCESS;
3663	}
3664	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3665	}
3666
3667	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3668	}
3669
3670
3671	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3672	{
3673	int rc;
3674
3675	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3676	* When non-zero CPUID features that could cause portability issues will be
3677	* stripped. The higher the value the more features gets stripped. Higher
3678	* values should only be used when older CPUs are involved since it may
3679	* harm performance and maybe also cause problems with specific guests. */
3680	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
3681	AssertLogRelRCReturn(rc, rc);
3682
3683	/** @cfgm{/CPUM/GuestCpuName, string}
3684	* The name of the CPU we're to emulate. The default is the host CPU.
3685	* Note! CPUs other than "host" one is currently unsupported. */
3686	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3687	AssertLogRelRCReturn(rc, rc);
3688
3689	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3690	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3691	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3692	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3693	*/
3694	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3695	AssertLogRelRCReturn(rc, rc);
3696
3697	/** @cfgm{/CPUM/InvariantTsc, boolean, complicated}
3698	* Set the invariant TSC flag in 0x80000007 if true, otherwas take default
3699	* action. By default the flag is passed thru as is from the host CPU, except
3700	* on AMD CPUs where it's suppressed to avoid trouble from linux assuming we
3701	* virtualize performance counters.
3702	*/
3703	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, false);
3704	AssertLogRelRCReturn(rc, rc);
3705
3706	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3707	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
3708	* probably going to be a temporary hack, so don't depend on this.
3709	* The 1st byte of the value is the stepping, the 2nd byte value is the model
3710	* number and the 3rd byte value is the family, and the 4th value must be zero.
3711	*/
3712	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3713	AssertLogRelRCReturn(rc, rc);
3714
3715	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3716	* The last standard leaf to keep. The actual last value that is stored in EAX
3717	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3718	* removed. (This works independently of and differently from NT4LeafLimit.)
3719	* The default is usually set to what we're able to reasonably sanitize.
3720	*/
3721	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3722	AssertLogRelRCReturn(rc, rc);
3723
3724	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3725	* The last extended leaf to keep. The actual last value that is stored in EAX
3726	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3727	* leaf are removed. The default is set to what we're able to sanitize.
3728	*/
3729	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3730	AssertLogRelRCReturn(rc, rc);
3731
3732	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3733	* The last extended leaf to keep. The actual last value that is stored in EAX
3734	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3735	* leaf are removed. The default is set to what we're able to sanitize.
3736	*/
3737	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3738	AssertLogRelRCReturn(rc, rc);
3739
3740
3741	/*
3742	* Instruction Set Architecture (ISA) Extensions.
3743	*/
3744	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3745	if (pIsaExts)
3746	{
3747	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3748	"CMPXCHG16B"
3749	"\|MONITOR"
3750	"\|MWaitExtensions"
3751	"\|SSE4.1"
3752	"\|SSE4.2"
3753	"\|XSAVE"
3754	"\|AVX"
3755	"\|AVX2"
3756	"\|AESNI"
3757	"\|PCLMUL"
3758	"\|POPCNT"
3759	"\|MOVBE"
3760	"\|RDRAND"
3761	"\|RDSEED"
3762	"\|CLFLUSHOPT"
3763	"\|ABM"
3764	"\|SSE4A"
3765	"\|MISALNSSE"
3766	"\|3DNOWPRF"
3767	"\|AXMMX"
3768	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
3769	if (RT_FAILURE(rc))
3770	return rc;
3771	}
3772
3773	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
3774	* Expose CMPXCHG16B to the guest if supported by the host. For the time
3775	* being the default is to only do this for VMs with nested paging and AMD-V or
3776	* unrestricted guest mode.
3777	*/
3778	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
3779	AssertLogRelRCReturn(rc, rc);
3780
3781	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
3782	* Expose MONITOR/MWAIT instructions to the guest.
3783	*/
3784	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
3785	AssertLogRelRCReturn(rc, rc);
3786
3787	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
3788	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
3789	* break on interrupt feature (bit 1).
3790	*/
3791	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
3792	AssertLogRelRCReturn(rc, rc);
3793
3794	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
3795	* Expose SSE4.1 to the guest if available.
3796	*/
3797	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
3798	AssertLogRelRCReturn(rc, rc);
3799
3800	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
3801	* Expose SSE4.2 to the guest if available.
3802	*/
3803	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
3804	AssertLogRelRCReturn(rc, rc);
3805
3806	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
3807	&& pVM->cpum.s.HostFeatures.fXSaveRstor
3808	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
3809	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
3810	&& !HMIsLongModeAllowed(pVM)
3811	#endif
3812	;
3813	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
3814
3815	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
3816	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
3817	* default is to only expose this to VMs with nested paging and AMD-V or
3818	* unrestricted guest execution mode. Not possible to force this one without
3819	* host support at the moment.
3820	*/
3821	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
3822	fMayHaveXSave /fAllowed/);
3823	AssertLogRelRCReturn(rc, rc);
3824
3825	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
3826	* Expose the AVX instruction set extensions to the guest if available and
3827	* XSAVE is exposed too. For the time being the default is to only expose this
3828	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3829	*/
3830	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
3831	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3832	AssertLogRelRCReturn(rc, rc);
3833
3834	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
3835	* Expose the AVX2 instruction set extensions to the guest if available and
3836	* XSAVE is exposed too. For the time being the default is to only expose this
3837	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3838	*/
3839	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec && false /* temporarily */,
3840	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3841	AssertLogRelRCReturn(rc, rc);
3842
3843	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
3844	* Whether to expose the AES instructions to the guest. For the time being the
3845	* default is to only do this for VMs with nested paging and AMD-V or
3846	* unrestricted guest mode.
3847	*/
3848	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
3849	AssertLogRelRCReturn(rc, rc);
3850
3851	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
3852	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
3853	* being the default is to only do this for VMs with nested paging and AMD-V or
3854	* unrestricted guest mode.
3855	*/
3856	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
3857	AssertLogRelRCReturn(rc, rc);
3858
3859	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
3860	* Whether to expose the POPCNT instructions to the guest. For the time
3861	* being the default is to only do this for VMs with nested paging and AMD-V or
3862	* unrestricted guest mode.
3863	*/
3864	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
3865	AssertLogRelRCReturn(rc, rc);
3866
3867	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
3868	* Whether to expose the MOVBE instructions to the guest. For the time
3869	* being the default is to only do this for VMs with nested paging and AMD-V or
3870	* unrestricted guest mode.
3871	*/
3872	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
3873	AssertLogRelRCReturn(rc, rc);
3874
3875	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
3876	* Whether to expose the RDRAND instructions to the guest. For the time being
3877	* the default is to only do this for VMs with nested paging and AMD-V or
3878	* unrestricted guest mode.
3879	*/
3880	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
3881	AssertLogRelRCReturn(rc, rc);
3882
3883	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
3884	* Whether to expose the RDSEED instructions to the guest. For the time being
3885	* the default is to only do this for VMs with nested paging and AMD-V or
3886	* unrestricted guest mode.
3887	*/
3888	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
3889	AssertLogRelRCReturn(rc, rc);
3890
3891	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
3892	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
3893	* being the default is to only do this for VMs with nested paging and AMD-V or
3894	* unrestricted guest mode.
3895	*/
3896	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
3897	AssertLogRelRCReturn(rc, rc);
3898
3899
3900	/* AMD: */
3901
3902	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
3903	* Whether to expose the AMD ABM instructions to the guest. For the time
3904	* being the default is to only do this for VMs with nested paging and AMD-V or
3905	* unrestricted guest mode.
3906	*/
3907	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
3908	AssertLogRelRCReturn(rc, rc);
3909
3910	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
3911	* Whether to expose the AMD SSE4A instructions to the guest. For the time
3912	* being the default is to only do this for VMs with nested paging and AMD-V or
3913	* unrestricted guest mode.
3914	*/
3915	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
3916	AssertLogRelRCReturn(rc, rc);
3917
3918	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
3919	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
3920	* the time being the default is to only do this for VMs with nested paging and
3921	* AMD-V or unrestricted guest mode.
3922	*/
3923	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
3924	AssertLogRelRCReturn(rc, rc);
3925
3926	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
3927	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
3928	* For the time being the default is to only do this for VMs with nested paging
3929	* and AMD-V or unrestricted guest mode.
3930	*/
3931	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
3932	AssertLogRelRCReturn(rc, rc);
3933
3934	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
3935	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
3936	* the default is to only do this for VMs with nested paging and AMD-V or
3937	* unrestricted guest mode.
3938	*/
3939	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
3940	AssertLogRelRCReturn(rc, rc);
3941
3942	return VINF_SUCCESS;
3943	}
3944
3945
3946	/**
3947	* Initializes the emulated CPU's CPUID & MSR information.
3948	*
3949	* @returns VBox status code.
3950	* @param pVM The cross context VM structure.
3951	*/
3952	int cpumR3InitCpuIdAndMsrs(PVM pVM)
3953	{
3954	PCPUM pCpum = &pVM->cpum.s;
3955	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
3956
3957	/*
3958	* Read the configuration.
3959	*/
3960	CPUMCPUIDCONFIG Config;
3961	RT_ZERO(Config);
3962
3963	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
3964	AssertRCReturn(rc, rc);
3965
3966	/*
3967	* Get the guest CPU data from the database and/or the host.
3968	*
3969	* The CPUID and MSRs are currently living on the regular heap to avoid
3970	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
3971	* API for the hyper heap). This means special cleanup considerations.
3972	*/
3973	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
3974	if (RT_FAILURE(rc))
3975	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
3976	? VMSetError(pVM, rc, RT_SRC_POS,
3977	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
3978	: rc;
3979
3980	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
3981	* Overrides the guest MSRs.
3982	*/
3983	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
3984
3985	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
3986	* Overrides the CPUID leaf values (from the host CPU usually) used for
3987	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
3988	* values when moving a VM to a different machine. Another use is restricting
3989	* (or extending) the feature set exposed to the guest. */
3990	if (RT_SUCCESS(rc))
3991	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
3992
3993	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
3994	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
3995	"Found unsupported configuration node '/CPUM/CPUID/'. "
3996	"Please use IMachine::setCPUIDLeaf() instead.");
3997
3998	/*
3999	* Pre-explode the CPUID info.
4000	*/
4001	if (RT_SUCCESS(rc))
4002	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
4003
4004	/*
4005	* Sanitize the cpuid information passed on to the guest.
4006	*/
4007	if (RT_SUCCESS(rc))
4008	{
4009	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4010	if (RT_SUCCESS(rc))
4011	{
4012	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4013	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4014	}
4015	}
4016
4017	/*
4018	* Plant our own hypervisor CPUID leaves.
4019	*/
4020	if (RT_SUCCESS(rc))
4021	rc = cpumR3CpuIdPlantHypervisorLeaves(pCpum, &Config);
4022
4023	/*
4024	* MSR fudging.
4025	*/
4026	if (RT_SUCCESS(rc))
4027	{
4028	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4029	* Fudges some common MSRs if not present in the selected CPU database entry.
4030	* This is for trying to keep VMs running when moved between different hosts
4031	* and different CPU vendors. */
4032	bool fEnable;
4033	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4034	if (RT_SUCCESS(rc) && fEnable)
4035	{
4036	rc = cpumR3MsrApplyFudge(pVM);
4037	AssertLogRelRC(rc);
4038	}
4039	}
4040	if (RT_SUCCESS(rc))
4041	{
4042	/*
4043	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4044	* guest CPU features again.
4045	*/
4046	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4047	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4048	pCpum->GuestInfo.cCpuIdLeaves);
4049	RTMemFree(pvFree);
4050
4051	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4052	int rc2 = MMHyperDupMem(pVM, pvFree,
4053	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4054	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4055	RTMemFree(pvFree);
4056	AssertLogRelRCReturn(rc1, rc1);
4057	AssertLogRelRCReturn(rc2, rc2);
4058
4059	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4060	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4061
4062
4063	/*
4064	* Some more configuration that we're applying at the end of everything
4065	* via the CPUMSetGuestCpuIdFeature API.
4066	*/
4067
4068	/* Check if PAE was explicitely enabled by the user. */
4069	bool fEnable;
4070	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4071	AssertRCReturn(rc, rc);
4072	if (fEnable)
4073	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4074
4075	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4076	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4077	AssertRCReturn(rc, rc);
4078	if (fEnable)
4079	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4080
4081	/* We don't enable the Hypervisor Present bit by default, but it may be needed by some guests. */
4082	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false);
4083	AssertRCReturn(rc, rc);
4084	if (fEnable)
4085	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
4086
4087	return VINF_SUCCESS;
4088	}
4089
4090	/*
4091	* Failed before switching to hyper heap.
4092	*/
4093	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4094	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4095	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4096	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4097	return rc;
4098	}
4099
4100
4101
4102	/*
4103	*
4104	*
4105	* Saved state related code.
4106	* Saved state related code.
4107	* Saved state related code.
4108	*
4109	*
4110	*/
4111
4112	/**
4113	* Called both in pass 0 and the final pass.
4114	*
4115	* @param pVM The cross context VM structure.
4116	* @param pSSM The saved state handle.
4117	*/
4118	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4119	{
4120	/*
4121	* Save all the CPU ID leaves.
4122	*/
4123	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4124	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4125	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4126	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4127
4128	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4129
4130	/*
4131	* Save a good portion of the raw CPU IDs as well as they may come in
4132	* handy when validating features for raw mode.
4133	*/
4134	CPUMCPUID aRawStd[16];
4135	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4136	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4137	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4138	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4139
4140	CPUMCPUID aRawExt[32];
4141	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4142	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4143	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4144	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4145	}
4146
4147
4148	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4149	{
4150	uint32_t cCpuIds;
4151	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4152	if (RT_SUCCESS(rc))
4153	{
4154	if (cCpuIds < 64)
4155	{
4156	for (uint32_t i = 0; i < cCpuIds; i++)
4157	{
4158	CPUMCPUID CpuId;
4159	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4160	if (RT_FAILURE(rc))
4161	break;
4162
4163	CPUMCPUIDLEAF NewLeaf;
4164	NewLeaf.uLeaf = uBase + i;
4165	NewLeaf.uSubLeaf = 0;
4166	NewLeaf.fSubLeafMask = 0;
4167	NewLeaf.uEax = CpuId.uEax;
4168	NewLeaf.uEbx = CpuId.uEbx;
4169	NewLeaf.uEcx = CpuId.uEcx;
4170	NewLeaf.uEdx = CpuId.uEdx;
4171	NewLeaf.fFlags = 0;
4172	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4173	}
4174	}
4175	else
4176	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4177	}
4178	if (RT_FAILURE(rc))
4179	{
4180	RTMemFree(*ppaLeaves);
4181	*ppaLeaves = NULL;
4182	*pcLeaves = 0;
4183	}
4184	return rc;
4185	}
4186
4187
4188	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4189	{
4190	*ppaLeaves = NULL;
4191	*pcLeaves = 0;
4192
4193	int rc;
4194	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4195	{
4196	/*
4197	* The new format. Starts by declaring the leave size and count.
4198	*/
4199	uint32_t cbLeaf;
4200	SSMR3GetU32(pSSM, &cbLeaf);
4201	uint32_t cLeaves;
4202	rc = SSMR3GetU32(pSSM, &cLeaves);
4203	if (RT_SUCCESS(rc))
4204	{
4205	if (cbLeaf == sizeof(**ppaLeaves))
4206	{
4207	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4208	{
4209	/*
4210	* Load the leaves one by one.
4211	*
4212	* The uPrev stuff is a kludge for working around a week worth of bad saved
4213	* states during the CPUID revamp in March 2015. We saved too many leaves
4214	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4215	* garbage entires at the end of the array when restoring. We also had
4216	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
4217	* this kludge doesn't deal correctly with that, but who cares...
4218	*/
4219	uint32_t uPrev = 0;
4220	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4221	{
4222	CPUMCPUIDLEAF Leaf;
4223	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
4224	if (RT_SUCCESS(rc))
4225	{
4226	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
4227	\|\| Leaf.uLeaf >= uPrev)
4228	{
4229	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4230	uPrev = Leaf.uLeaf;
4231	}
4232	else
4233	uPrev = UINT32_MAX;
4234	}
4235	}
4236	}
4237	else
4238	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
4239	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
4240	}
4241	else
4242	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
4243	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
4244	}
4245	}
4246	else
4247	{
4248	/*
4249	* The old format with its three inflexible arrays.
4250	*/
4251	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
4252	if (RT_SUCCESS(rc))
4253	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
4254	if (RT_SUCCESS(rc))
4255	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
4256	if (RT_SUCCESS(rc))
4257	{
4258	/*
4259	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
4260	*/
4261	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
4262	if ( pLeaf
4263	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
4264	{
4265	CPUMCPUIDLEAF Leaf;
4266	Leaf.uLeaf = 4;
4267	Leaf.fSubLeafMask = UINT32_MAX;
4268	Leaf.uSubLeaf = 0;
4269	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
4270	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
4271	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
4272	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
4273	\| UINT32_C(63); /* system coherency line size - 1 */
4274	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
4275	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
4276	\| (UINT32_C(1) << 5) /* cache level */
4277	\| UINT32_C(1); /* cache type (data) */
4278	Leaf.fFlags = 0;
4279	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4280	if (RT_SUCCESS(rc))
4281	{
4282	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
4283	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4284	}
4285	if (RT_SUCCESS(rc))
4286	{
4287	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
4288	Leaf.uEcx = 4095; /* sets - 1 */
4289	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
4290	Leaf.uEbx \|= UINT32_C(23) << 22;
4291	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
4292	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
4293	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
4294	Leaf.uEax \|= UINT32_C(2) << 5;
4295	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4296	}
4297	}
4298	}
4299	}
4300	return rc;
4301	}
4302
4303
4304	/**
4305	* Loads the CPU ID leaves saved by pass 0, inner worker.
4306	*
4307	* @returns VBox status code.
4308	* @param pVM The cross context VM structure.
4309	* @param pSSM The saved state handle.
4310	* @param uVersion The format version.
4311	* @param paLeaves Guest CPUID leaves loaded from the state.
4312	* @param cLeaves The number of leaves in @a paLeaves.
4313	*/
4314	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
4315	{
4316	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4317
4318	/*
4319	* Continue loading the state into stack buffers.
4320	*/
4321	CPUMCPUID GuestDefCpuId;
4322	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
4323	AssertRCReturn(rc, rc);
4324
4325	CPUMCPUID aRawStd[16];
4326	uint32_t cRawStd;
4327	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
4328	if (cRawStd > RT_ELEMENTS(aRawStd))
4329	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4330	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
4331	AssertRCReturn(rc, rc);
4332	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
4333	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4334
4335	CPUMCPUID aRawExt[32];
4336	uint32_t cRawExt;
4337	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
4338	if (cRawExt > RT_ELEMENTS(aRawExt))
4339	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4340	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
4341	AssertRCReturn(rc, rc);
4342	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
4343	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4344
4345	/*
4346	* Get the raw CPU IDs for the current host.
4347	*/
4348	CPUMCPUID aHostRawStd[16];
4349	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
4350	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
4351
4352	CPUMCPUID aHostRawExt[32];
4353	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
4354	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
4355	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4356
4357	/*
4358	* Get the host and guest overrides so we don't reject the state because
4359	* some feature was enabled thru these interfaces.
4360	* Note! We currently only need the feature leaves, so skip rest.
4361	*/
4362	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4363	CPUMCPUID aHostOverrideStd[2];
4364	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4365	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4366
4367	CPUMCPUID aHostOverrideExt[2];
4368	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4369	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4370
4371	/*
4372	* This can be skipped.
4373	*/
4374	bool fStrictCpuIdChecks;
4375	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
4376
4377	/*
4378	* Define a bunch of macros for simplifying the santizing/checking code below.
4379	*/
4380	/* Generic expression + failure message. */
4381	#define CPUID_CHECK_RET(expr, fmt) \
4382	do { \
4383	if (!(expr)) \
4384	{ \
4385	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
4386	if (fStrictCpuIdChecks) \
4387	{ \
4388	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4389	RTStrFree(pszMsg); \
4390	return rcCpuid; \
4391	} \
4392	LogRel(("CPUM: %s\n", pszMsg)); \
4393	RTStrFree(pszMsg); \
4394	} \
4395	} while (0)
4396	#define CPUID_CHECK_WRN(expr, fmt) \
4397	do { \
4398	if (!(expr)) \
4399	LogRel(fmt); \
4400	} while (0)
4401
4402	/* For comparing two values and bitch if they differs. */
4403	#define CPUID_CHECK2_RET(what, host, saved) \
4404	do { \
4405	if ((host) != (saved)) \
4406	{ \
4407	if (fStrictCpuIdChecks) \
4408	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4409	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
4410	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4411	} \
4412	} while (0)
4413	#define CPUID_CHECK2_WRN(what, host, saved) \
4414	do { \
4415	if ((host) != (saved)) \
4416	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4417	} while (0)
4418
4419	/* For checking raw cpu features (raw mode). */
4420	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
4421	do { \
4422	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4423	{ \
4424	if (fStrictCpuIdChecks) \
4425	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4426	N_(#bit " mismatch: host=%d saved=%d"), \
4427	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
4428	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4429	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4430	} \
4431	} while (0)
4432	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
4433	do { \
4434	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4435	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4436	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4437	} while (0)
4438	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
4439
4440	/* For checking guest features. */
4441	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
4442	do { \
4443	if ( (aGuestCpuId##set [1].reg & bit) \
4444	&& !(aHostRaw##set [1].reg & bit) \
4445	&& !(aHostOverride##set [1].reg & bit) \
4446	) \
4447	{ \
4448	if (fStrictCpuIdChecks) \
4449	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4450	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4451	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4452	} \
4453	} while (0)
4454	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
4455	do { \
4456	if ( (aGuestCpuId##set [1].reg & bit) \
4457	&& !(aHostRaw##set [1].reg & bit) \
4458	&& !(aHostOverride##set [1].reg & bit) \
4459	) \
4460	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4461	} while (0)
4462	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
4463	do { \
4464	if ( (aGuestCpuId##set [1].reg & bit) \
4465	&& !(aHostRaw##set [1].reg & bit) \
4466	&& !(aHostOverride##set [1].reg & bit) \
4467	) \
4468	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4469	} while (0)
4470	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
4471
4472	/* For checking guest features if AMD guest CPU. */
4473	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
4474	do { \
4475	if ( (aGuestCpuId##set [1].reg & bit) \
4476	&& fGuestAmd \
4477	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4478	&& !(aHostOverride##set [1].reg & bit) \
4479	) \
4480	{ \
4481	if (fStrictCpuIdChecks) \
4482	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4483	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4484	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4485	} \
4486	} while (0)
4487	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
4488	do { \
4489	if ( (aGuestCpuId##set [1].reg & bit) \
4490	&& fGuestAmd \
4491	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4492	&& !(aHostOverride##set [1].reg & bit) \
4493	) \
4494	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4495	} while (0)
4496	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
4497	do { \
4498	if ( (aGuestCpuId##set [1].reg & bit) \
4499	&& fGuestAmd \
4500	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4501	&& !(aHostOverride##set [1].reg & bit) \
4502	) \
4503	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4504	} while (0)
4505	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
4506
4507	/* For checking AMD features which have a corresponding bit in the standard
4508	range. (Intel defines very few bits in the extended feature sets.) */
4509	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
4510	do { \
4511	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4512	&& !(fHostAmd \
4513	? aHostRawExt[1].reg & (ExtBit) \
4514	: aHostRawStd[1].reg & (StdBit)) \
4515	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4516	) \
4517	{ \
4518	if (fStrictCpuIdChecks) \
4519	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4520	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
4521	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4522	} \
4523	} while (0)
4524	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
4525	do { \
4526	if ( (aGuestCpuId[1].reg & (ExtBit)) \
4527	&& !(fHostAmd \
4528	? aHostRawExt[1].reg & (ExtBit) \
4529	: aHostRawStd[1].reg & (StdBit)) \
4530	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4531	) \
4532	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4533	} while (0)
4534	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
4535	do { \
4536	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4537	&& !(fHostAmd \
4538	? aHostRawExt[1].reg & (ExtBit) \
4539	: aHostRawStd[1].reg & (StdBit)) \
4540	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4541	) \
4542	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4543	} while (0)
4544	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
4545
4546	/*
4547	* For raw-mode we'll require that the CPUs are very similar since we don't
4548	* intercept CPUID instructions for user mode applications.
4549	*/
4550	if (!HMIsEnabled(pVM))
4551	{
4552	/* CPUID(0) */
4553	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
4554	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
4555	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
4556	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
4557	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
4558	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
4559	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
4560	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
4561	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
4562
4563	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
4564
4565	/* CPUID(1).eax */
4566	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
4567	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
4568	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
4569
4570	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
4571	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
4572	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
4573
4574	/* CPUID(1).ecx */
4575	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
4576	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
4577	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
4578	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4579	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
4580	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
4581	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
4582	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
4583	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
4584	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
4585	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
4586	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
4587	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
4588	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
4589	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
4590	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
4591	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
4592	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4593	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
4594	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
4595	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
4596	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4597	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
4598	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
4599	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4600	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
4601	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
4602	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4603	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
4604	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4605	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4606	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
4607
4608	/* CPUID(1).edx */
4609	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4610	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4611	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
4612	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4613	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
4614	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
4615	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4616	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4617	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
4618	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4619	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
4620	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4621	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4622	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4623	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4624	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
4625	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4626	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4627	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4628	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
4629	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
4630	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
4631	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
4632	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
4633	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
4634	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
4635	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
4636	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
4637	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
4638	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
4639	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
4640	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
4641
4642	/* CPUID(2) - config, mostly about caches. ignore. */
4643	/* CPUID(3) - processor serial number. ignore. */
4644	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
4645	/* CPUID(5) - mwait/monitor config. ignore. */
4646	/* CPUID(6) - power management. ignore. */
4647	/* CPUID(7) - ???. ignore. */
4648	/* CPUID(8) - ???. ignore. */
4649	/* CPUID(9) - DCA. ignore for now. */
4650	/* CPUID(a) - PeMo info. ignore for now. */
4651	/* CPUID(b) - topology info - takes ECX as input. ignore. */
4652
4653	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
4654	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
4655	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
4656	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
4657	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
4658	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
4659	{
4660	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
4661	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
4662	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
4663	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
4664	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
4665	}
4666
4667	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
4668	Note! Intel have/is marking many of the fields here as reserved. We
4669	will verify them as if it's an AMD CPU. */
4670	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
4671	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
4672	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
4673	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
4674	{
4675	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
4676	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
4677	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
4678	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
4679	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
4680	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
4681	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
4682
4683	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
4684	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
4685	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
4686	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
4687	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
4688	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
4689
4690	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
4691	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
4692	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
4693	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
4694
4695	/* CPUID(0x80000001).ecx */
4696	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
4697	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
4698	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
4699	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
4700	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
4701	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
4702	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
4703	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
4704	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
4705	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
4706	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
4707	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
4708	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
4709	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
4710	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4711	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4712	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4713	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4714	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4715	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4716	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4717	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4718	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4719	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4720	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4721	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4722	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4723	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4724	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4725	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4726	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4727	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4728
4729	/* CPUID(0x80000001).edx */
4730	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
4731	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
4732	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
4733	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
4734	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
4735	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
4736	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
4737	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
4738	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
4739	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
4740	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4741	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
4742	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
4743	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
4744	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
4745	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
4746	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
4747	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
4748	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4749	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4750	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4751	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
4752	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4753	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
4754	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
4755	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4756	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4757	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4758	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
4759	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4760	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4761	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4762
4763	/** @todo verify the rest as well. */
4764	}
4765	}
4766
4767
4768
4769	/*
4770	* Verify that we can support the features already exposed to the guest on
4771	* this host.
4772	*
4773	* Most of the features we're emulating requires intercepting instruction
4774	* and doing it the slow way, so there is no need to warn when they aren't
4775	* present in the host CPU. Thus we use IGN instead of EMU on these.
4776	*
4777	* Trailing comments:
4778	* "EMU" - Possible to emulate, could be lots of work and very slow.
4779	* "EMU?" - Can this be emulated?
4780	*/
4781	CPUMCPUID aGuestCpuIdStd[2];
4782	RT_ZERO(aGuestCpuIdStd);
4783	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
4784
4785	/* CPUID(1).ecx */
4786	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
4787	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
4788	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
4789	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4790	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
4791	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
4792	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
4793	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
4794	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
4795	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
4796	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
4797	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
4798	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
4799	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
4800	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
4801	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
4802	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
4803	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4804	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
4805	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
4806	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
4807	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4808	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
4809	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
4810	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4811	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
4812	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
4813	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4814	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
4815	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4816	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4817	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
4818
4819	/* CPUID(1).edx */
4820	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4821	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4822	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
4823	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4824	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4825	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4826	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4827	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4828	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4829	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4830	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
4831	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4832	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4833	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4834	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4835	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4836	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4837	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4838	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4839	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
4840	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
4841	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
4842	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
4843	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4844	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4845	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
4846	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
4847	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
4848	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
4849	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
4850	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
4851	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
4852
4853	/* CPUID(0x80000000). */
4854	CPUMCPUID aGuestCpuIdExt[2];
4855	RT_ZERO(aGuestCpuIdExt);
4856	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
4857	{
4858	/** @todo deal with no 0x80000001 on the host. */
4859	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
4860	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
4861
4862	/* CPUID(0x80000001).ecx */
4863	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
4864	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
4865	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
4866	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
4867	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
4868	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
4869	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
4870	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
4871	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
4872	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
4873	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
4874	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
4875	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
4876	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
4877	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4878	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4879	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4880	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4881	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4882	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4883	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4884	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4885	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4886	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4887	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4888	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4889	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4890	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4891	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4892	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4893	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4894	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4895
4896	/* CPUID(0x80000001).edx */
4897	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
4898	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
4899	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
4900	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
4901	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4902	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4903	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
4904	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
4905	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4906	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
4907	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4908	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
4909	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
4910	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
4911	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
4912	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4913	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
4914	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
4915	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4916	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4917	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4918	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
4919	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4920	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4921	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4922	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4923	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4924	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4925	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
4926	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4927	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4928	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4929	}
4930
4931	/** @todo check leaf 7 */
4932
4933	/* CPUID(d) - XCR0 stuff - takes ECX as input.
4934	* ECX=0: EAX - Valid bits in XCR0[31:0].
4935	* EBX - Maximum state size as per current XCR0 value.
4936	* ECX - Maximum state size for all supported features.
4937	* EDX - Valid bits in XCR0[63:32].
4938	* ECX=1: EAX - Various X-features.
4939	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
4940	* ECX - Valid bits in IA32_XSS[31:0].
4941	* EDX - Valid bits in IA32_XSS[63:32].
4942	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
4943	* if the bit invalid all four registers are set to zero.
4944	* EAX - The state size for this feature.
4945	* EBX - The state byte offset of this feature.
4946	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
4947	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
4948	*/
4949	uint64_t fGuestXcr0Mask = 0;
4950	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
4951	if ( pCurLeaf
4952	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
4953	&& ( pCurLeaf->uEax
4954	\|\| pCurLeaf->uEbx
4955	\|\| pCurLeaf->uEcx
4956	\|\| pCurLeaf->uEdx) )
4957	{
4958	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
4959	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
4960	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4961	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
4962	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
4963	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
4964	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4965	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
4966
4967	/* We don't support any additional features yet. */
4968	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
4969	if (pCurLeaf && pCurLeaf->uEax)
4970	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4971	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
4972	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
4973	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4974	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
4975	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
4976
4977
4978	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
4979	{
4980	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4981	if (pCurLeaf)
4982	{
4983	/* If advertised, the state component offset and size must match the one used by host. */
4984	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
4985	{
4986	CPUMCPUID RawHost;
4987	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
4988	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
4989	if ( RawHost.uEbx != pCurLeaf->uEbx
4990	\|\| RawHost.uEax != pCurLeaf->uEax)
4991	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4992	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
4993	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
4994	}
4995	}
4996	}
4997	}
4998	/* Clear leaf 0xd just in case we're loading an old state... */
4999	else if (pCurLeaf)
5000	{
5001	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5002	{
5003	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5004	if (pCurLeaf)
5005	{
5006	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5007	\|\| ( pCurLeaf->uEax == 0
5008	&& pCurLeaf->uEbx == 0
5009	&& pCurLeaf->uEcx == 0
5010	&& pCurLeaf->uEdx == 0),
5011	("uVersion=%#x; %#x %#x %#x %#x\n",
5012	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5013	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5014	}
5015	}
5016	}
5017
5018	/* Update the fXStateGuestMask value for the VM. */
5019	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5020	{
5021	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5022	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5023	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5024	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5025	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5026	}
5027
5028	#undef CPUID_CHECK_RET
5029	#undef CPUID_CHECK_WRN
5030	#undef CPUID_CHECK2_RET
5031	#undef CPUID_CHECK2_WRN
5032	#undef CPUID_RAW_FEATURE_RET
5033	#undef CPUID_RAW_FEATURE_WRN
5034	#undef CPUID_RAW_FEATURE_IGN
5035	#undef CPUID_GST_FEATURE_RET
5036	#undef CPUID_GST_FEATURE_WRN
5037	#undef CPUID_GST_FEATURE_EMU
5038	#undef CPUID_GST_FEATURE_IGN
5039	#undef CPUID_GST_FEATURE2_RET
5040	#undef CPUID_GST_FEATURE2_WRN
5041	#undef CPUID_GST_FEATURE2_EMU
5042	#undef CPUID_GST_FEATURE2_IGN
5043	#undef CPUID_GST_AMD_FEATURE_RET
5044	#undef CPUID_GST_AMD_FEATURE_WRN
5045	#undef CPUID_GST_AMD_FEATURE_EMU
5046	#undef CPUID_GST_AMD_FEATURE_IGN
5047
5048	/*
5049	* We're good, commit the CPU ID leaves.
5050	*/
5051	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5052	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5053	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5054	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
5055	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5056	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
5057	AssertLogRelRCReturn(rc, rc);
5058
5059	return VINF_SUCCESS;
5060	}
5061
5062
5063	/**
5064	* Loads the CPU ID leaves saved by pass 0.
5065	*
5066	* @returns VBox status code.
5067	* @param pVM The cross context VM structure.
5068	* @param pSSM The saved state handle.
5069	* @param uVersion The format version.
5070	*/
5071	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5072	{
5073	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5074
5075	/*
5076	* Load the CPUID leaves array first and call worker to do the rest, just so
5077	* we can free the memory when we need to without ending up in column 1000.
5078	*/
5079	PCPUMCPUIDLEAF paLeaves;
5080	uint32_t cLeaves;
5081	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5082	AssertRC(rc);
5083	if (RT_SUCCESS(rc))
5084	{
5085	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
5086	RTMemFree(paLeaves);
5087	}
5088	return rc;
5089	}
5090
5091
5092
5093	/**
5094	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5095	*
5096	* @returns VBox status code.
5097	* @param pVM The cross context VM structure.
5098	* @param pSSM The saved state handle.
5099	* @param uVersion The format version.
5100	*/
5101	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5102	{
5103	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5104
5105	/*
5106	* Restore the CPUID leaves.
5107	*
5108	* Note that we support restoring less than the current amount of standard
5109	* leaves because we've been allowed more is newer version of VBox.
5110	*/
5111	uint32_t cElements;
5112	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5113	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5114	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5115	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5116
5117	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5118	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5119	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5120	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5121
5122	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5123	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5124	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5125	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5126
5127	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5128
5129	/*
5130	* Check that the basic cpuid id information is unchanged.
5131	*/
5132	/** @todo we should check the 64 bits capabilities too! */
5133	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5134	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5135	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5136	uint32_t au32CpuIdSaved[8];
5137	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5138	if (RT_SUCCESS(rc))
5139	{
5140	/* Ignore CPU stepping. */
5141	au32CpuId[4] &= 0xfffffff0;
5142	au32CpuIdSaved[4] &= 0xfffffff0;
5143
5144	/* Ignore APIC ID (AMD specs). */
5145	au32CpuId[5] &= ~0xff000000;
5146	au32CpuIdSaved[5] &= ~0xff000000;
5147
5148	/* Ignore the number of Logical CPUs (AMD specs). */
5149	au32CpuId[5] &= ~0x00ff0000;
5150	au32CpuIdSaved[5] &= ~0x00ff0000;
5151
5152	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5153	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5154	\| X86_CPUID_FEATURE_ECX_VMX
5155	\| X86_CPUID_FEATURE_ECX_SMX
5156	\| X86_CPUID_FEATURE_ECX_EST
5157	\| X86_CPUID_FEATURE_ECX_TM2
5158	\| X86_CPUID_FEATURE_ECX_CNTXID
5159	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5160	\| X86_CPUID_FEATURE_ECX_PDCM
5161	\| X86_CPUID_FEATURE_ECX_DCA
5162	\| X86_CPUID_FEATURE_ECX_X2APIC
5163	);
5164	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5165	\| X86_CPUID_FEATURE_ECX_VMX
5166	\| X86_CPUID_FEATURE_ECX_SMX
5167	\| X86_CPUID_FEATURE_ECX_EST
5168	\| X86_CPUID_FEATURE_ECX_TM2
5169	\| X86_CPUID_FEATURE_ECX_CNTXID
5170	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5171	\| X86_CPUID_FEATURE_ECX_PDCM
5172	\| X86_CPUID_FEATURE_ECX_DCA
5173	\| X86_CPUID_FEATURE_ECX_X2APIC
5174	);
5175
5176	/* Make sure we don't forget to update the masks when enabling
5177	* features in the future.
5178	*/
5179	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5180	( X86_CPUID_FEATURE_ECX_DTES64
5181	\| X86_CPUID_FEATURE_ECX_VMX
5182	\| X86_CPUID_FEATURE_ECX_SMX
5183	\| X86_CPUID_FEATURE_ECX_EST
5184	\| X86_CPUID_FEATURE_ECX_TM2
5185	\| X86_CPUID_FEATURE_ECX_CNTXID
5186	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5187	\| X86_CPUID_FEATURE_ECX_PDCM
5188	\| X86_CPUID_FEATURE_ECX_DCA
5189	\| X86_CPUID_FEATURE_ECX_X2APIC
5190	)));
5191	/* do the compare */
5192	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5193	{
5194	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5195	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5196	"Saved=%.*Rhxs\n"
5197	"Real =%.*Rhxs\n",
5198	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5199	sizeof(au32CpuId), au32CpuId));
5200	else
5201	{
5202	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5203	"Saved=%.*Rhxs\n"
5204	"Real =%.*Rhxs\n",
5205	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5206	sizeof(au32CpuId), au32CpuId));
5207	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5208	}
5209	}
5210	}
5211
5212	return rc;
5213	}
5214
5215
5216
5217	/*
5218	*
5219	*
5220	* CPUID Info Handler.
5221	* CPUID Info Handler.
5222	* CPUID Info Handler.
5223	*
5224	*
5225	*/
5226
5227
5228
5229	/**
5230	* Get L1 cache / TLS associativity.
5231	*/
5232	static const char getCacheAss(unsigned u, char pszBuf)
5233	{
5234	if (u == 0)
5235	return "res0 ";
5236	if (u == 1)
5237	return "direct";
5238	if (u == 255)
5239	return "fully";
5240	if (u >= 256)
5241	return "???";
5242
5243	RTStrPrintf(pszBuf, 16, "%d way", u);
5244	return pszBuf;
5245	}
5246
5247
5248	/**
5249	* Get L2 cache associativity.
5250	*/
5251	const char *getL2CacheAss(unsigned u)
5252	{
5253	switch (u)
5254	{
5255	case 0: return "off ";
5256	case 1: return "direct";
5257	case 2: return "2 way ";
5258	case 3: return "res3 ";
5259	case 4: return "4 way ";
5260	case 5: return "res5 ";
5261	case 6: return "8 way ";
5262	case 7: return "res7 ";
5263	case 8: return "16 way";
5264	case 9: return "res9 ";
5265	case 10: return "res10 ";
5266	case 11: return "res11 ";
5267	case 12: return "res12 ";
5268	case 13: return "res13 ";
5269	case 14: return "res14 ";
5270	case 15: return "fully ";
5271	default: return "????";
5272	}
5273	}
5274
5275
5276	/** CPUID(1).EDX field descriptions. */
5277	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
5278	{
5279	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5280	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5281	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5282	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5283	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5284	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
5285	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5286	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5287	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5288	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5289	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
5290	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5291	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5292	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5293	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5294	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5295	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5296	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
5297	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
5298	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
5299	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
5300	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5301	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
5302	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
5303	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
5304	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
5305	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
5306	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
5307	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
5308	DBGFREGSUBFIELD_TERMINATOR()
5309	};
5310
5311	/** CPUID(1).ECX field descriptions. */
5312	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
5313	{
5314	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
5315	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
5316	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
5317	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
5318	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
5319	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
5320	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
5321	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
5322	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
5323	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
5324	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
5325	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
5326	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
5327	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
5328	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
5329	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
5330	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
5331	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
5332	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
5333	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
5334	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
5335	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
5336	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
5337	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
5338	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
5339	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
5340	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
5341	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
5342	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
5343	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
5344	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
5345	DBGFREGSUBFIELD_TERMINATOR()
5346	};
5347
5348	/** CPUID(7,0).EBX field descriptions. */
5349	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
5350	{
5351	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
5352	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
5353	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
5354	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
5355	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
5356	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
5357	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
5358	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
5359	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
5360	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
5361	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
5362	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
5363	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
5364	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
5365	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
5366	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
5367	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
5368	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
5369	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
5370	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
5371	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
5372	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
5373	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
5374	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
5375	DBGFREGSUBFIELD_TERMINATOR()
5376	};
5377
5378	/** CPUID(7,0).ECX field descriptions. */
5379	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
5380	{
5381	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
5382	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
5383	DBGFREGSUBFIELD_RO("OSPKU\0" "CR4.PKU mirror", 4, 1, 0),
5384	DBGFREGSUBFIELD_TERMINATOR()
5385	};
5386
5387
5388	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
5389	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
5390	{
5391	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
5392	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
5393	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
5394	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
5395	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
5396	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
5397	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
5398	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
5399	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
5400	DBGFREGSUBFIELD_TERMINATOR()
5401	};
5402
5403	/** CPUID(13,1).EAX field descriptions. */
5404	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
5405	{
5406	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
5407	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
5408	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
5409	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
5410	DBGFREGSUBFIELD_TERMINATOR()
5411	};
5412
5413
5414	/** CPUID(0x80000001,0).EDX field descriptions. */
5415	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
5416	{
5417	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5418	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5419	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5420	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5421	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5422	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
5423	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5424	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5425	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5426	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5427	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
5428	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5429	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5430	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5431	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5432	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5433	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5434	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
5435	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
5436	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5437	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
5438	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
5439	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
5440	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
5441	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
5442	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
5443	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
5444	DBGFREGSUBFIELD_TERMINATOR()
5445	};
5446
5447	/** CPUID(0x80000001,0).ECX field descriptions. */
5448	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
5449	{
5450	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
5451	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
5452	DBGFREGSUBFIELD_RO("SVM\0" "AMD VM extensions", 2, 1, 0),
5453	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
5454	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
5455	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
5456	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
5457	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
5458	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
5459	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
5460	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
5461	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
5462	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
5463	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
5464	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
5465	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
5466	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
5467	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
5468	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
5469	DBGFREGSUBFIELD_TERMINATOR()
5470	};
5471
5472
5473	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
5474	const char *pszLeadIn, uint32_t cchWidth)
5475	{
5476	if (pszLeadIn)
5477	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5478
5479	for (uint32_t iBit = 0; iBit < 32; iBit++)
5480	if (RT_BIT_32(iBit) & uVal)
5481	{
5482	while ( pDesc->pszName != NULL
5483	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5484	pDesc++;
5485	if ( pDesc->pszName != NULL
5486	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5487	{
5488	if (pDesc->cBits == 1)
5489	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5490	else
5491	{
5492	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
5493	if (pDesc->cBits < 32)
5494	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5495	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
5496	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5497	}
5498	}
5499	else
5500	pHlp->pfnPrintf(pHlp, " %u", iBit);
5501	}
5502	if (pszLeadIn)
5503	pHlp->pfnPrintf(pHlp, "\n");
5504	}
5505
5506
5507	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5508	const char *pszLeadIn, uint32_t cchWidth)
5509	{
5510	if (pszLeadIn)
5511	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5512
5513	for (uint32_t iBit = 0; iBit < 64; iBit++)
5514	if (RT_BIT_64(iBit) & uVal)
5515	{
5516	while ( pDesc->pszName != NULL
5517	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5518	pDesc++;
5519	if ( pDesc->pszName != NULL
5520	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5521	{
5522	if (pDesc->cBits == 1)
5523	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5524	else
5525	{
5526	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
5527	if (pDesc->cBits < 64)
5528	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
5529	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
5530	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5531	}
5532	}
5533	else
5534	pHlp->pfnPrintf(pHlp, " %u", iBit);
5535	}
5536	if (pszLeadIn)
5537	pHlp->pfnPrintf(pHlp, "\n");
5538	}
5539
5540
5541	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5542	const char *pszLeadIn, uint32_t cchWidth)
5543	{
5544	if (!uVal)
5545	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5546	else
5547	{
5548	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5549	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
5550	pHlp->pfnPrintf(pHlp, " )\n");
5551	}
5552	}
5553
5554
5555	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
5556	uint32_t cchWidth)
5557	{
5558	uint32_t uCombined = uVal1 \| uVal2;
5559	for (uint32_t iBit = 0; iBit < 32; iBit++)
5560	if ( (RT_BIT_32(iBit) & uCombined)
5561	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
5562	{
5563	while ( pDesc->pszName != NULL
5564	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5565	pDesc++;
5566
5567	if ( pDesc->pszName != NULL
5568	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5569	{
5570	size_t cchMnemonic = strlen(pDesc->pszName);
5571	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
5572	size_t cchDesc = strlen(pszDesc);
5573	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
5574	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
5575	if (pDesc->cBits < 32)
5576	{
5577	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5578	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5579	}
5580
5581	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
5582	pDesc->pszName, pszDesc,
5583	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
5584	uFieldValue1, uFieldValue2);
5585
5586	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
5587	pDesc++;
5588	}
5589	else
5590	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
5591	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
5592	}
5593	}
5594
5595
5596	/**
5597	* Produces a detailed summary of standard leaf 0x00000001.
5598	*
5599	* @param pHlp The info helper functions.
5600	* @param paLeaves The CPUID leaves array.
5601	* @param cLeaves The number of leaves in the array.
5602	* @param pCurLeaf The 0x00000001 leaf.
5603	* @param fVerbose Whether to be very verbose or not.
5604	* @param fIntel Set if intel CPU.
5605	*/
5606	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5607	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
5608	{
5609	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
5610	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
5611	uint32_t uEAX = pCurLeaf->uEax;
5612	uint32_t uEBX = pCurLeaf->uEbx;
5613
5614	pHlp->pfnPrintf(pHlp,
5615	"%36s %2d \tExtended: %d \tEffective: %d\n"
5616	"%36s %2d \tExtended: %d \tEffective: %d\n"
5617	"%36s %d\n"
5618	"%36s %d (%s)\n"
5619	"%36s %#04x\n"
5620	"%36s %d\n"
5621	"%36s %d\n"
5622	"%36s %#04x\n"
5623	,
5624	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
5625	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
5626	"Stepping:", ASMGetCpuStepping(uEAX),
5627	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
5628	"APIC ID:", (uEBX >> 24) & 0xff,
5629	"Logical CPUs:",(uEBX >> 16) & 0xff,
5630	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
5631	"Brand ID:", (uEBX >> 0) & 0xff);
5632	if (fVerbose)
5633	{
5634	CPUMCPUID Host;
5635	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5636	pHlp->pfnPrintf(pHlp, "Features\n");
5637	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5638	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
5639	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
5640	}
5641	else
5642	{
5643	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
5644	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
5645	}
5646	}
5647
5648
5649	/**
5650	* Produces a detailed summary of standard leaf 0x00000007.
5651	*
5652	* @param pHlp The info helper functions.
5653	* @param paLeaves The CPUID leaves array.
5654	* @param cLeaves The number of leaves in the array.
5655	* @param pCurLeaf The first 0x00000007 leaf.
5656	* @param fVerbose Whether to be very verbose or not.
5657	*/
5658	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5659	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5660	{
5661	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
5662	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
5663	for (;;)
5664	{
5665	CPUMCPUID Host;
5666	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5667
5668	switch (pCurLeaf->uSubLeaf)
5669	{
5670	case 0:
5671	if (fVerbose)
5672	{
5673	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5674	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
5675	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
5676	if (pCurLeaf->uEdx \|\| Host.uEdx)
5677	pHlp->pfnPrintf(pHlp, "%36 %#x (%#x)\n", "Ext Features EDX:", pCurLeaf->uEdx, Host.uEdx);
5678	}
5679	else
5680	{
5681	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
5682	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
5683	if (pCurLeaf->uEdx)
5684	pHlp->pfnPrintf(pHlp, "%36 %#x\n", "Ext Features EDX:", pCurLeaf->uEdx);
5685	}
5686	break;
5687
5688	default:
5689	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
5690	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
5691	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
5692	break;
5693
5694	}
5695
5696	/* advance. */
5697	pCurLeaf++;
5698	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5699	\|\| pCurLeaf->uLeaf != 0x7)
5700	break;
5701	}
5702	}
5703
5704
5705	/**
5706	* Produces a detailed summary of standard leaf 0x0000000d.
5707	*
5708	* @param pHlp The info helper functions.
5709	* @param paLeaves The CPUID leaves array.
5710	* @param cLeaves The number of leaves in the array.
5711	* @param pCurLeaf The first 0x00000007 leaf.
5712	* @param fVerbose Whether to be very verbose or not.
5713	*/
5714	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5715	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5716	{
5717	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
5718	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
5719	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5720	{
5721	CPUMCPUID Host;
5722	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5723
5724	switch (uSubLeaf)
5725	{
5726	case 0:
5727	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5728	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
5729	pCurLeaf->uEbx, pCurLeaf->uEcx);
5730	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
5731
5732	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5733	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
5734	"Valid XCR0 bits, guest:", 42);
5735	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
5736	"Valid XCR0 bits, host:", 42);
5737	break;
5738
5739	case 1:
5740	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5741	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
5742	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
5743
5744	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5745	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
5746	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
5747
5748	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5749	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
5750	" Valid IA32_XSS bits, guest:", 42);
5751	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
5752	" Valid IA32_XSS bits, host:", 42);
5753	break;
5754
5755	default:
5756	if ( pCurLeaf
5757	&& pCurLeaf->uSubLeaf == uSubLeaf
5758	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
5759	{
5760	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
5761	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5762	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
5763	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
5764	if (pCurLeaf->uEdx)
5765	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
5766	pHlp->pfnPrintf(pHlp, " --");
5767	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5768	pHlp->pfnPrintf(pHlp, "\n");
5769	}
5770	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
5771	{
5772	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
5773	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5774	if (Host.uEcx & ~RT_BIT_32(0))
5775	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
5776	if (Host.uEdx)
5777	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
5778	pHlp->pfnPrintf(pHlp, " --");
5779	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5780	pHlp->pfnPrintf(pHlp, "\n");
5781	}
5782	break;
5783
5784	}
5785
5786	/* advance. */
5787	if (pCurLeaf)
5788	{
5789	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5790	&& pCurLeaf->uSubLeaf <= uSubLeaf
5791	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
5792	pCurLeaf++;
5793	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5794	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
5795	pCurLeaf = NULL;
5796	}
5797	}
5798	}
5799
5800
5801	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5802	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
5803	{
5804	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5805	&& pCurLeaf->uLeaf <= uUpToLeaf)
5806	{
5807	pHlp->pfnPrintf(pHlp,
5808	" %s\n"
5809	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
5810	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5811	&& pCurLeaf->uLeaf <= uUpToLeaf)
5812	{
5813	CPUMCPUID Host;
5814	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5815	pHlp->pfnPrintf(pHlp,
5816	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5817	"Hst: %08x %08x %08x %08x\n",
5818	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5819	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5820	pCurLeaf++;
5821	}
5822	}
5823
5824	return pCurLeaf;
5825	}
5826
5827
5828	/**
5829	* Display the guest CpuId leaves.
5830	*
5831	* @param pVM The cross context VM structure.
5832	* @param pHlp The info helper functions.
5833	* @param pszArgs "terse", "default" or "verbose".
5834	*/
5835	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
5836	{
5837	/*
5838	* Parse the argument.
5839	*/
5840	unsigned iVerbosity = 1;
5841	if (pszArgs)
5842	{
5843	pszArgs = RTStrStripL(pszArgs);
5844	if (!strcmp(pszArgs, "terse"))
5845	iVerbosity--;
5846	else if (!strcmp(pszArgs, "verbose"))
5847	iVerbosity++;
5848	}
5849
5850	uint32_t uLeaf;
5851	CPUMCPUID Host;
5852	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
5853	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
5854	PCCPUMCPUIDLEAF pCurLeaf;
5855	PCCPUMCPUIDLEAF pNextLeaf;
5856	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
5857	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
5858	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
5859
5860	/*
5861	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
5862	*/
5863	uint32_t cHstMax = ASMCpuId_EAX(0);
5864	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
5865	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
5866	pHlp->pfnPrintf(pHlp,
5867	" Raw Standard CPUID Leaves\n"
5868	" Leaf/sub-leaf eax ebx ecx edx\n");
5869	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
5870	{
5871	uint32_t cMaxSubLeaves = 1;
5872	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
5873	cMaxSubLeaves = 16;
5874	else if (uLeaf == 0xd)
5875	cMaxSubLeaves = 128;
5876
5877	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5878	{
5879	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5880	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5881	&& pCurLeaf->uLeaf == uLeaf
5882	&& pCurLeaf->uSubLeaf == uSubLeaf)
5883	{
5884	pHlp->pfnPrintf(pHlp,
5885	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5886	"Hst: %08x %08x %08x %08x\n",
5887	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5888	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5889	pCurLeaf++;
5890	}
5891	else if ( uLeaf != 0xd
5892	\|\| uSubLeaf <= 1
5893	\|\| Host.uEbx != 0 )
5894	pHlp->pfnPrintf(pHlp,
5895	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5896	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5897
5898	/* Done? */
5899	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5900	\|\| pCurLeaf->uLeaf != uLeaf)
5901	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
5902	\|\| (uLeaf == 0x7 && Host.uEax == 0)
5903	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
5904	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
5905	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
5906	)
5907	)
5908	break;
5909	}
5910	}
5911	pNextLeaf = pCurLeaf;
5912
5913	/*
5914	* If verbose, decode it.
5915	*/
5916	if (iVerbosity && paLeaves[0].uLeaf == 0)
5917	pHlp->pfnPrintf(pHlp,
5918	"%36s %.04s%.04s%.04s\n"
5919	"%36s 0x00000000-%#010x\n"
5920	,
5921	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
5922	"Supports:", paLeaves[0].uEax);
5923
5924	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
5925	cpumR3CpuIdInfoStdLeaf1Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1, fIntel);
5926
5927	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
5928	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5929
5930	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
5931	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5932
5933	pCurLeaf = pNextLeaf;
5934
5935	/*
5936	* Hypervisor leaves.
5937	*
5938	* Unlike most of the other leaves reported, the guest hypervisor leaves
5939	* aren't a subset of the host CPUID bits.
5940	*/
5941	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
5942
5943	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5944	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
5945	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
5946	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
5947	cMax = RT_MAX(cHstMax, cGstMax);
5948	if (cMax >= UINT32_C(0x40000000))
5949	{
5950	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
5951
5952	/** @todo dump these in more detail. */
5953
5954	pCurLeaf = pNextLeaf;
5955	}
5956
5957
5958	/*
5959	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
5960	* Implemented after AMD specs.
5961	*/
5962	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
5963
5964	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5965	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
5966	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
5967	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
5968	cMax = RT_MAX(cHstMax, cGstMax);
5969	if (cMax >= UINT32_C(0x80000000))
5970	{
5971
5972	pHlp->pfnPrintf(pHlp,
5973	" Raw Extended CPUID Leaves\n"
5974	" Leaf/sub-leaf eax ebx ecx edx\n");
5975	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
5976	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
5977	{
5978	uint32_t cMaxSubLeaves = 1;
5979	if (uLeaf == UINT32_C(0x8000001d))
5980	cMaxSubLeaves = 16;
5981
5982	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5983	{
5984	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5985	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5986	&& pCurLeaf->uLeaf == uLeaf
5987	&& pCurLeaf->uSubLeaf == uSubLeaf)
5988	{
5989	pHlp->pfnPrintf(pHlp,
5990	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5991	"Hst: %08x %08x %08x %08x\n",
5992	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5993	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5994	pCurLeaf++;
5995	}
5996	else if ( uLeaf != 0xd
5997	\|\| uSubLeaf <= 1
5998	\|\| Host.uEbx != 0 )
5999	pHlp->pfnPrintf(pHlp,
6000	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6001	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6002
6003	/* Done? */
6004	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6005	\|\| pCurLeaf->uLeaf != uLeaf)
6006	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6007	break;
6008	}
6009	}
6010	pNextLeaf = pCurLeaf;
6011
6012	/*
6013	* Understandable output
6014	*/
6015	if (iVerbosity)
6016	pHlp->pfnPrintf(pHlp,
6017	"Ext Name: %.4s%.4s%.4s\n"
6018	"Ext Supports: 0x80000000-%#010x\n",
6019	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6020
6021	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6022	if (iVerbosity && pCurLeaf)
6023	{
6024	uint32_t uEAX = pCurLeaf->uEax;
6025	pHlp->pfnPrintf(pHlp,
6026	"Family: %d \tExtended: %d \tEffective: %d\n"
6027	"Model: %d \tExtended: %d \tEffective: %d\n"
6028	"Stepping: %d\n"
6029	"Brand ID: %#05x\n",
6030	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6031	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6032	ASMGetCpuStepping(uEAX),
6033	pCurLeaf->uEbx & 0xfff);
6034
6035	if (iVerbosity == 1)
6036	{
6037	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6038	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6039	}
6040	else
6041	{
6042	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6043	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6044	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6045	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6046	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6047	}
6048	}
6049
6050	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6051	{
6052	char szString[443+1] = {0};
6053	uint32_t pu32 = (uint32_t )szString;
6054	*pu32++ = pCurLeaf->uEax;
6055	*pu32++ = pCurLeaf->uEbx;
6056	*pu32++ = pCurLeaf->uEcx;
6057	*pu32++ = pCurLeaf->uEdx;
6058	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6059	if (pCurLeaf)
6060	{
6061	*pu32++ = pCurLeaf->uEax;
6062	*pu32++ = pCurLeaf->uEbx;
6063	*pu32++ = pCurLeaf->uEcx;
6064	*pu32++ = pCurLeaf->uEdx;
6065	}
6066	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6067	if (pCurLeaf)
6068	{
6069	*pu32++ = pCurLeaf->uEax;
6070	*pu32++ = pCurLeaf->uEbx;
6071	*pu32++ = pCurLeaf->uEcx;
6072	*pu32++ = pCurLeaf->uEdx;
6073	}
6074	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6075	}
6076
6077	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6078	{
6079	uint32_t uEAX = pCurLeaf->uEax;
6080	uint32_t uEBX = pCurLeaf->uEbx;
6081	uint32_t uECX = pCurLeaf->uEcx;
6082	uint32_t uEDX = pCurLeaf->uEdx;
6083	char sz1[32];
6084	char sz2[32];
6085
6086	pHlp->pfnPrintf(pHlp,
6087	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6088	"TLB 2/4M Data: %s %3d entries\n",
6089	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6090	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6091	pHlp->pfnPrintf(pHlp,
6092	"TLB 4K Instr/Uni: %s %3d entries\n"
6093	"TLB 4K Data: %s %3d entries\n",
6094	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6095	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6096	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6097	"L1 Instr Cache Lines Per Tag: %d\n"
6098	"L1 Instr Cache Associativity: %s\n"
6099	"L1 Instr Cache Size: %d KB\n",
6100	(uEDX >> 0) & 0xff,
6101	(uEDX >> 8) & 0xff,
6102	getCacheAss((uEDX >> 16) & 0xff, sz1),
6103	(uEDX >> 24) & 0xff);
6104	pHlp->pfnPrintf(pHlp,
6105	"L1 Data Cache Line Size: %d bytes\n"
6106	"L1 Data Cache Lines Per Tag: %d\n"
6107	"L1 Data Cache Associativity: %s\n"
6108	"L1 Data Cache Size: %d KB\n",
6109	(uECX >> 0) & 0xff,
6110	(uECX >> 8) & 0xff,
6111	getCacheAss((uECX >> 16) & 0xff, sz1),
6112	(uECX >> 24) & 0xff);
6113	}
6114
6115	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6116	{
6117	uint32_t uEAX = pCurLeaf->uEax;
6118	uint32_t uEBX = pCurLeaf->uEbx;
6119	uint32_t uEDX = pCurLeaf->uEdx;
6120
6121	pHlp->pfnPrintf(pHlp,
6122	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6123	"L2 TLB 2/4M Data: %s %4d entries\n",
6124	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6125	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6126	pHlp->pfnPrintf(pHlp,
6127	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6128	"L2 TLB 4K Data: %s %4d entries\n",
6129	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6130	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6131	pHlp->pfnPrintf(pHlp,
6132	"L2 Cache Line Size: %d bytes\n"
6133	"L2 Cache Lines Per Tag: %d\n"
6134	"L2 Cache Associativity: %s\n"
6135	"L2 Cache Size: %d KB\n",
6136	(uEDX >> 0) & 0xff,
6137	(uEDX >> 8) & 0xf,
6138	getL2CacheAss((uEDX >> 12) & 0xf),
6139	(uEDX >> 16) & 0xffff);
6140	}
6141
6142	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
6143	{
6144	uint32_t uEDX = pCurLeaf->uEdx;
6145
6146	pHlp->pfnPrintf(pHlp, "APM Features: ");
6147	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
6148	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
6149	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
6150	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
6151	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
6152	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
6153	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " MC");
6154	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " HWPSTATE");
6155	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TscInvariant");
6156	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " CPB");
6157	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " EffFreqRO");
6158	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PFI");
6159	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PA");
6160	for (unsigned iBit = 13; iBit < 32; iBit++)
6161	if (uEDX & RT_BIT(iBit))
6162	pHlp->pfnPrintf(pHlp, " %d", iBit);
6163	pHlp->pfnPrintf(pHlp, "\n");
6164
6165	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6166	pHlp->pfnPrintf(pHlp, "Host Invariant-TSC support: %RTbool\n",
6167	cHstMax >= UINT32_C(0x80000007) && (Host.uEdx & RT_BIT(8)));
6168
6169	}
6170
6171	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0)) != NULL)
6172	{
6173	uint32_t uEAX = pCurLeaf->uEax;
6174	uint32_t uECX = pCurLeaf->uEcx;
6175
6176	pHlp->pfnPrintf(pHlp,
6177	"Physical Address Width: %d bits\n"
6178	"Virtual Address Width: %d bits\n"
6179	"Guest Physical Address Width: %d bits\n",
6180	(uEAX >> 0) & 0xff,
6181	(uEAX >> 8) & 0xff,
6182	(uEAX >> 16) & 0xff);
6183	pHlp->pfnPrintf(pHlp,
6184	"Physical Core Count: %d\n",
6185	((uECX >> 0) & 0xff) + 1);
6186	}
6187
6188	pCurLeaf = pNextLeaf;
6189	}
6190
6191
6192
6193	/*
6194	* Centaur.
6195	*/
6196	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
6197
6198	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6199	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
6200	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
6201	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
6202	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
6203	cMax = RT_MAX(cHstMax, cGstMax);
6204	if (cMax >= UINT32_C(0xc0000000))
6205	{
6206	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
6207
6208	/*
6209	* Understandable output
6210	*/
6211	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
6212	pHlp->pfnPrintf(pHlp,
6213	"Centaur Supports: 0xc0000000-%#010x\n",
6214	pCurLeaf->uEax);
6215
6216	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
6217	{
6218	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6219	uint32_t uEdxGst = pCurLeaf->uEdx;
6220	uint32_t uEdxHst = Host.uEdx;
6221
6222	if (iVerbosity == 1)
6223	{
6224	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
6225	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
6226	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
6227	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
6228	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
6229	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
6230	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
6231	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
6232	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
6233	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6234	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
6235	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
6236	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
6237	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
6238	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
6239	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
6240	for (unsigned iBit = 14; iBit < 32; iBit++)
6241	if (uEdxGst & RT_BIT(iBit))
6242	pHlp->pfnPrintf(pHlp, " %d", iBit);
6243	pHlp->pfnPrintf(pHlp, "\n");
6244	}
6245	else
6246	{
6247	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
6248	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
6249	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
6250	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
6251	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
6252	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
6253	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
6254	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
6255	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
6256	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6257	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
6258	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
6259	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
6260	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
6261	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
6262	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
6263	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
6264	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
6265	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
6266	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
6267	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
6268	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
6269	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
6270	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
6271	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
6272	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
6273	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
6274	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
6275	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
6276	for (unsigned iBit = 27; iBit < 32; iBit++)
6277	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
6278	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
6279	pHlp->pfnPrintf(pHlp, "\n");
6280	}
6281	}
6282
6283	pCurLeaf = pNextLeaf;
6284	}
6285
6286	/*
6287	* The remainder.
6288	*/
6289	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
6290	}
6291
6292
6293
6294
6295
6296	/*
6297	*
6298	*
6299	* PATM interfaces.
6300	* PATM interfaces.
6301	* PATM interfaces.
6302	*
6303	*
6304	*/
6305
6306
6307	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
6308	/** @name Patchmanager CPUID legacy table APIs
6309	* @{
6310	*/
6311
6312	/**
6313	* Gets a pointer to the default CPUID leaf.
6314	*
6315	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
6316	* @param pVM The cross context VM structure.
6317	* @remark Intended for PATM only.
6318	*/
6319	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
6320	{
6321	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
6322	}
6323
6324
6325	/**
6326	* Gets a number of standard CPUID leaves (PATM only).
6327	*
6328	* @returns Number of leaves.
6329	* @param pVM The cross context VM structure.
6330	* @remark Intended for PATM - legacy, don't use in new code.
6331	*/
6332	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
6333	{
6334	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
6335	}
6336
6337
6338	/**
6339	* Gets a number of extended CPUID leaves (PATM only).
6340	*
6341	* @returns Number of leaves.
6342	* @param pVM The cross context VM structure.
6343	* @remark Intended for PATM - legacy, don't use in new code.
6344	*/
6345	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
6346	{
6347	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
6348	}
6349
6350
6351	/**
6352	* Gets a number of centaur CPUID leaves.
6353	*
6354	* @returns Number of leaves.
6355	* @param pVM The cross context VM structure.
6356	* @remark Intended for PATM - legacy, don't use in new code.
6357	*/
6358	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
6359	{
6360	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
6361	}
6362
6363
6364	/**
6365	* Gets a pointer to the array of standard CPUID leaves.
6366	*
6367	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
6368	*
6369	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
6370	* @param pVM The cross context VM structure.
6371	* @remark Intended for PATM - legacy, don't use in new code.
6372	*/
6373	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
6374	{
6375	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
6376	}
6377
6378
6379	/**
6380	* Gets a pointer to the array of extended CPUID leaves.
6381	*
6382	* CPUMGetGuestCpuIdExtMax() give the size of the array.
6383	*
6384	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
6385	* @param pVM The cross context VM structure.
6386	* @remark Intended for PATM - legacy, don't use in new code.
6387	*/
6388	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
6389	{
6390	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
6391	}
6392
6393
6394	/**
6395	* Gets a pointer to the array of centaur CPUID leaves.
6396	*
6397	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
6398	*
6399	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
6400	* @param pVM The cross context VM structure.
6401	* @remark Intended for PATM - legacy, don't use in new code.
6402	*/
6403	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
6404	{
6405	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
6406	}
6407
6408	/** @} */
6409	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
6410
6411	#endif /* VBOX_IN_VMM */
6412

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 60850

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