CPUMR3CpuId.cpp@ 66095

Last change on this file since 66095 was 66095, checked in by vboxsync, 8 years ago
CPUMR3CpuId.cpp: Detect AMD Ryzen.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 313.4 KB

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1	/* $Id: CPUMR3CpuId.cpp 66095 2017-03-14 15:10:09Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/ssm.h>
27	#include "CPUMInternal.h"
28	#include <VBox/vmm/vm.h>
29	#include <VBox/vmm/mm.h>
30
31	#include <VBox/err.h>
32	#include <iprt/asm-amd64-x86.h>
33	#include <iprt/ctype.h>
34	#include <iprt/mem.h>
35	#include <iprt/string.h>
36
37
38	/*********************************************************************************************************************************
39	* Defined Constants And Macros *
40	*********************************************************************************************************************************/
41	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
42	#define CPUM_CPUID_MAX_LEAVES 2048
43	/* Max size we accept for the XSAVE area. */
44	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
45	/* Min size we accept for the XSAVE area. */
46	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
47
48
49	/*********************************************************************************************************************************
50	* Global Variables *
51	*********************************************************************************************************************************/
52	/**
53	* The intel pentium family.
54	*/
55	static const CPUMMICROARCH g_aenmIntelFamily06[] =
56	{
57	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
58	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
59	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
60	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
61	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
63	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
64	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
65	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
66	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
67	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
68	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
69	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
70	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
71	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
72	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
73	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
74	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
79	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
80	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
81	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
82	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
83	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
84	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
86	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
87	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
88	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
89	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
90	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
91	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
95	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
96	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
97	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
98	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
99	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
100	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
102	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
103	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
104	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
105	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
106	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
107	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
111	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
112	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
113	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
114	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
115	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
116	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
118	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
119	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
120	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
121	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
122	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
123	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
127	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
128	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
129	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
130	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
131	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
132	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
134	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
135	/* [78(0x4e)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed */
136	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / unconfirmed, Broadwell-E */
137	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
138	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
139	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed server cpu */
143	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
144	/* [87(0x57)] = */ kCpumMicroarch_Intel_Unknown,
145	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
146	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
147	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
148	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / unconfirmed */
150	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
151	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
152	/* [95(0x5f)] = */ kCpumMicroarch_Intel_Unknown,
153	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
154	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
155	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [99(0x64)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x65)] = */ kCpumMicroarch_Intel_Unknown,
159	/* [99(0x66)] = / kCpumMicroarch_Intel_Core7_Cannonlake, / unconfirmed */
160	};
161
162
163
164	/**
165	* Figures out the (sub-)micro architecture given a bit of CPUID info.
166	*
167	* @returns Micro architecture.
168	* @param enmVendor The CPU vendor .
169	* @param bFamily The CPU family.
170	* @param bModel The CPU model.
171	* @param bStepping The CPU stepping.
172	*/
173	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
174	uint8_t bModel, uint8_t bStepping)
175	{
176	if (enmVendor == CPUMCPUVENDOR_AMD)
177	{
178	switch (bFamily)
179	{
180	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
181	case 0x03: return kCpumMicroarch_AMD_Am386;
182	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
183	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
184	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
185	case 0x06:
186	switch (bModel)
187	{
188	case 0: return kCpumMicroarch_AMD_K7_Palomino;
189	case 1: return kCpumMicroarch_AMD_K7_Palomino;
190	case 2: return kCpumMicroarch_AMD_K7_Palomino;
191	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
192	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
193	case 6: return kCpumMicroarch_AMD_K7_Palomino;
194	case 7: return kCpumMicroarch_AMD_K7_Morgan;
195	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
196	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
197	}
198	return kCpumMicroarch_AMD_K7_Unknown;
199	case 0x0f:
200	/*
201	* This family is a friggin mess. Trying my best to make some
202	* sense out of it. Too much happened in the 0x0f family to
203	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
204	*
205	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
206	* cpu-world.com, and other places:
207	* - 130nm:
208	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
209	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
210	* - Newcastle: FC0/DH-CG (errum #180: FE0/DH-CG), FF0/DH-CG
211	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
212	* - Odessa: FC0/DH-CG (errum #180: FE0/DH-CG)
213	* - Paris: FF0/DH-CG, FC0/DH-CG (errum #180: FE0/DH-CG),
214	* - 90nm:
215	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
216	* - Oakville: 10FC0/DH-D0.
217	* - Georgetown: 10FC0/DH-D0.
218	* - Sonora: 10FC0/DH-D0.
219	* - Venus: 20F71/SH-E4
220	* - Troy: 20F51/SH-E4
221	* - Athens: 20F51/SH-E4
222	* - San Diego: 20F71/SH-E4.
223	* - Lancaster: 20F42/SH-E5
224	* - Newark: 20F42/SH-E5.
225	* - Albany: 20FC2/DH-E6.
226	* - Roma: 20FC2/DH-E6.
227	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
228	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
229	* - 90nm introducing Dual core:
230	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
231	* - Italy: 20F10/JH-E1, 20F12/JH-E6
232	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
233	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
234	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
235	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
236	* - Santa Ana: 40F32/JH-F2, /-F3
237	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
238	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
239	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
240	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
241	* - Keene: 40FC2/DH-F2.
242	* - Richmond: 40FC2/DH-F2
243	* - Taylor: 40F82/BH-F2
244	* - Trinidad: 40F82/BH-F2
245	*
246	* - 65nm:
247	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
248	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
249	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
250	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
251	* - Sherman: /-G1, 70FC2/DH-G2.
252	* - Huron: 70FF2/DH-G2.
253	*/
254	if (bModel < 0x10)
255	return kCpumMicroarch_AMD_K8_130nm;
256	if (bModel >= 0x60 && bModel < 0x80)
257	return kCpumMicroarch_AMD_K8_65nm;
258	if (bModel >= 0x40)
259	return kCpumMicroarch_AMD_K8_90nm_AMDV;
260	switch (bModel)
261	{
262	case 0x21:
263	case 0x23:
264	case 0x2b:
265	case 0x2f:
266	case 0x37:
267	case 0x3f:
268	return kCpumMicroarch_AMD_K8_90nm_DualCore;
269	}
270	return kCpumMicroarch_AMD_K8_90nm;
271	case 0x10:
272	return kCpumMicroarch_AMD_K10;
273	case 0x11:
274	return kCpumMicroarch_AMD_K10_Lion;
275	case 0x12:
276	return kCpumMicroarch_AMD_K10_Llano;
277	case 0x14:
278	return kCpumMicroarch_AMD_Bobcat;
279	case 0x15:
280	switch (bModel)
281	{
282	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
283	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
284	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
285	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
286	case 0x11: /* ?? */
287	case 0x12: /* ?? */
288	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
289	}
290	return kCpumMicroarch_AMD_15h_Unknown;
291	case 0x16:
292	return kCpumMicroarch_AMD_Jaguar;
293	case 0x17:
294	return kCpumMicroarch_AMD_Zen_Ryzen;
295	}
296	return kCpumMicroarch_AMD_Unknown;
297	}
298
299	if (enmVendor == CPUMCPUVENDOR_INTEL)
300	{
301	switch (bFamily)
302	{
303	case 3:
304	return kCpumMicroarch_Intel_80386;
305	case 4:
306	return kCpumMicroarch_Intel_80486;
307	case 5:
308	return kCpumMicroarch_Intel_P5;
309	case 6:
310	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
311	return g_aenmIntelFamily06[bModel];
312	return kCpumMicroarch_Intel_Atom_Unknown;
313	case 15:
314	switch (bModel)
315	{
316	case 0: return kCpumMicroarch_Intel_NB_Willamette;
317	case 1: return kCpumMicroarch_Intel_NB_Willamette;
318	case 2: return kCpumMicroarch_Intel_NB_Northwood;
319	case 3: return kCpumMicroarch_Intel_NB_Prescott;
320	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
321	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
322	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
323	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
324	default: return kCpumMicroarch_Intel_NB_Unknown;
325	}
326	break;
327	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
328	case 0:
329	return kCpumMicroarch_Intel_8086;
330	case 1:
331	return kCpumMicroarch_Intel_80186;
332	case 2:
333	return kCpumMicroarch_Intel_80286;
334	}
335	return kCpumMicroarch_Intel_Unknown;
336	}
337
338	if (enmVendor == CPUMCPUVENDOR_VIA)
339	{
340	switch (bFamily)
341	{
342	case 5:
343	switch (bModel)
344	{
345	case 1: return kCpumMicroarch_Centaur_C6;
346	case 4: return kCpumMicroarch_Centaur_C6;
347	case 8: return kCpumMicroarch_Centaur_C2;
348	case 9: return kCpumMicroarch_Centaur_C3;
349	}
350	break;
351
352	case 6:
353	switch (bModel)
354	{
355	case 5: return kCpumMicroarch_VIA_C3_M2;
356	case 6: return kCpumMicroarch_VIA_C3_C5A;
357	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
358	case 8: return kCpumMicroarch_VIA_C3_C5N;
359	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
360	case 10: return kCpumMicroarch_VIA_C7_C5J;
361	case 15: return kCpumMicroarch_VIA_Isaiah;
362	}
363	break;
364	}
365	return kCpumMicroarch_VIA_Unknown;
366	}
367
368	if (enmVendor == CPUMCPUVENDOR_CYRIX)
369	{
370	switch (bFamily)
371	{
372	case 4:
373	switch (bModel)
374	{
375	case 9: return kCpumMicroarch_Cyrix_5x86;
376	}
377	break;
378
379	case 5:
380	switch (bModel)
381	{
382	case 2: return kCpumMicroarch_Cyrix_M1;
383	case 4: return kCpumMicroarch_Cyrix_MediaGX;
384	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
385	}
386	break;
387
388	case 6:
389	switch (bModel)
390	{
391	case 0: return kCpumMicroarch_Cyrix_M2;
392	}
393	break;
394
395	}
396	return kCpumMicroarch_Cyrix_Unknown;
397	}
398
399	return kCpumMicroarch_Unknown;
400	}
401
402
403	/**
404	* Translates a microarchitecture enum value to the corresponding string
405	* constant.
406	*
407	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
408	* NULL if the value is invalid.
409	*
410	* @param enmMicroarch The enum value to convert.
411	*/
412	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
413	{
414	switch (enmMicroarch)
415	{
416	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
417	CASE_RET_STR(kCpumMicroarch_Intel_8086);
418	CASE_RET_STR(kCpumMicroarch_Intel_80186);
419	CASE_RET_STR(kCpumMicroarch_Intel_80286);
420	CASE_RET_STR(kCpumMicroarch_Intel_80386);
421	CASE_RET_STR(kCpumMicroarch_Intel_80486);
422	CASE_RET_STR(kCpumMicroarch_Intel_P5);
423
424	CASE_RET_STR(kCpumMicroarch_Intel_P6);
425	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
426	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
427
428	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
429	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
430	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
431
432	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
433	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
434
435	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
436	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
437	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
438	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
439	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
440	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
441	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
442	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Cannonlake);
443
444	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
445	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
446	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
447	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
448	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
449	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
450	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
451
452	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
453	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
454	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
455	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
456	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
457	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
458	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
459
460	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
461
462	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
463	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
464	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
465	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
466	CASE_RET_STR(kCpumMicroarch_AMD_K5);
467	CASE_RET_STR(kCpumMicroarch_AMD_K6);
468
469	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
470	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
471	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
472	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
473	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
474	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
475	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
476
477	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
478	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
479	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
480	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
481	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
482
483	CASE_RET_STR(kCpumMicroarch_AMD_K10);
484	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
485	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
486	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
487	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
488
489	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
490	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
491	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
492	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
493	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
494
495	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
496
497	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
498
499	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
500
501	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
502	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
503	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
504	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
505	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
506	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
507	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
508	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
509	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
510	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
511	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
512	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
513	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
514
515	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
516	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
517	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
518	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
519	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
520	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
521
522	CASE_RET_STR(kCpumMicroarch_NEC_V20);
523	CASE_RET_STR(kCpumMicroarch_NEC_V30);
524
525	CASE_RET_STR(kCpumMicroarch_Unknown);
526
527	#undef CASE_RET_STR
528	case kCpumMicroarch_Invalid:
529	case kCpumMicroarch_Intel_End:
530	case kCpumMicroarch_Intel_Core7_End:
531	case kCpumMicroarch_Intel_Atom_End:
532	case kCpumMicroarch_Intel_P6_Core_Atom_End:
533	case kCpumMicroarch_Intel_NB_End:
534	case kCpumMicroarch_AMD_K7_End:
535	case kCpumMicroarch_AMD_K8_End:
536	case kCpumMicroarch_AMD_15h_End:
537	case kCpumMicroarch_AMD_16h_End:
538	case kCpumMicroarch_AMD_Zen_End:
539	case kCpumMicroarch_AMD_End:
540	case kCpumMicroarch_VIA_End:
541	case kCpumMicroarch_Cyrix_End:
542	case kCpumMicroarch_NEC_End:
543	case kCpumMicroarch_32BitHack:
544	break;
545	/* no default! */
546	}
547
548	return NULL;
549	}
550
551
552
553	/**
554	* Gets a matching leaf in the CPUID leaf array.
555	*
556	* @returns Pointer to the matching leaf, or NULL if not found.
557	* @param paLeaves The CPUID leaves to search. This is sorted.
558	* @param cLeaves The number of leaves in the array.
559	* @param uLeaf The leaf to locate.
560	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
561	*/
562	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
563	{
564	/* Lazy bird does linear lookup here since this is only used for the
565	occational CPUID overrides. */
566	for (uint32_t i = 0; i < cLeaves; i++)
567	if ( paLeaves[i].uLeaf == uLeaf
568	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
569	return &paLeaves[i];
570	return NULL;
571	}
572
573
574	#ifndef IN_VBOX_CPU_REPORT
575	/**
576	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
577	*
578	* @returns true if found, false it not.
579	* @param paLeaves The CPUID leaves to search. This is sorted.
580	* @param cLeaves The number of leaves in the array.
581	* @param uLeaf The leaf to locate.
582	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
583	* @param pLegacy The legacy output leaf.
584	*/
585	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
586	PCPUMCPUID pLegacy)
587	{
588	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
589	if (pLeaf)
590	{
591	pLegacy->uEax = pLeaf->uEax;
592	pLegacy->uEbx = pLeaf->uEbx;
593	pLegacy->uEcx = pLeaf->uEcx;
594	pLegacy->uEdx = pLeaf->uEdx;
595	return true;
596	}
597	return false;
598	}
599	#endif /* IN_VBOX_CPU_REPORT */
600
601
602	/**
603	* Ensures that the CPUID leaf array can hold one more leaf.
604	*
605	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
606	* failure.
607	* @param pVM The cross context VM structure. If NULL, use
608	* the process heap, otherwise the VM's hyper heap.
609	* @param ppaLeaves Pointer to the variable holding the array pointer
610	* (input/output).
611	* @param cLeaves The current array size.
612	*
613	* @remarks This function will automatically update the R0 and RC pointers when
614	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
615	* be the corresponding VM's CPUID arrays (which is asserted).
616	*/
617	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
618	{
619	/*
620	* If pVM is not specified, we're on the regular heap and can waste a
621	* little space to speed things up.
622	*/
623	uint32_t cAllocated;
624	if (!pVM)
625	{
626	cAllocated = RT_ALIGN(cLeaves, 16);
627	if (cLeaves + 1 > cAllocated)
628	{
629	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
630	if (pvNew)
631	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
632	else
633	{
634	RTMemFree(*ppaLeaves);
635	*ppaLeaves = NULL;
636	}
637	}
638	}
639	/*
640	* Otherwise, we're on the hyper heap and are probably just inserting
641	* one or two leaves and should conserve space.
642	*/
643	else
644	{
645	#ifdef IN_VBOX_CPU_REPORT
646	AssertReleaseFailed();
647	#else
648	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
649	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
650
651	size_t cb = cLeaves * sizeof(**ppaLeaves);
652	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
653	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
654	if (RT_SUCCESS(rc))
655	{
656	/* Update the R0 and RC pointers. */
657	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
658	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
659	}
660	else
661	{
662	*ppaLeaves = NULL;
663	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
664	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
665	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
666	}
667	#endif
668	}
669	return *ppaLeaves;
670	}
671
672
673	/**
674	* Append a CPUID leaf or sub-leaf.
675	*
676	* ASSUMES linear insertion order, so we'll won't need to do any searching or
677	* replace anything. Use cpumR3CpuIdInsert() for those cases.
678	*
679	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
680	* the caller need do no more work.
681	* @param ppaLeaves Pointer to the pointer to the array of sorted
682	* CPUID leaves and sub-leaves.
683	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
684	* @param uLeaf The leaf we're adding.
685	* @param uSubLeaf The sub-leaf number.
686	* @param fSubLeafMask The sub-leaf mask.
687	* @param uEax The EAX value.
688	* @param uEbx The EBX value.
689	* @param uEcx The ECX value.
690	* @param uEdx The EDX value.
691	* @param fFlags The flags.
692	*/
693	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
694	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
695	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
696	{
697	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
698	return VERR_NO_MEMORY;
699
700	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
701	Assert( *pcLeaves == 0
702	\|\| pNew[-1].uLeaf < uLeaf
703	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
704
705	pNew->uLeaf = uLeaf;
706	pNew->uSubLeaf = uSubLeaf;
707	pNew->fSubLeafMask = fSubLeafMask;
708	pNew->uEax = uEax;
709	pNew->uEbx = uEbx;
710	pNew->uEcx = uEcx;
711	pNew->uEdx = uEdx;
712	pNew->fFlags = fFlags;
713
714	*pcLeaves += 1;
715	return VINF_SUCCESS;
716	}
717
718
719	/**
720	* Checks that we've updated the CPUID leaves array correctly.
721	*
722	* This is a no-op in non-strict builds.
723	*
724	* @param paLeaves The leaves array.
725	* @param cLeaves The number of leaves.
726	*/
727	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
728	{
729	#ifdef VBOX_STRICT
730	for (uint32_t i = 1; i < cLeaves; i++)
731	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
732	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
733	else
734	{
735	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
736	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
737	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
738	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
739	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
740	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
741	}
742	#else
743	NOREF(paLeaves);
744	NOREF(cLeaves);
745	#endif
746	}
747
748
749	/**
750	* Inserts a CPU ID leaf, replacing any existing ones.
751	*
752	* When inserting a simple leaf where we already got a series of sub-leaves with
753	* the same leaf number (eax), the simple leaf will replace the whole series.
754	*
755	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
756	* host-context heap and has only been allocated/reallocated by the
757	* cpumR3CpuIdEnsureSpace function.
758	*
759	* @returns VBox status code.
760	* @param pVM The cross context VM structure. If NULL, use
761	* the process heap, otherwise the VM's hyper heap.
762	* @param ppaLeaves Pointer to the pointer to the array of sorted
763	* CPUID leaves and sub-leaves. Must be NULL if using
764	* the hyper heap.
765	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
766	* be NULL if using the hyper heap.
767	* @param pNewLeaf Pointer to the data of the new leaf we're about to
768	* insert.
769	*/
770	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
771	{
772	/*
773	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
774	*/
775	if (pVM)
776	{
777	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
778	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
779
780	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
781	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
782	}
783
784	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
785	uint32_t cLeaves = *pcLeaves;
786
787	/*
788	* Validate the new leaf a little.
789	*/
790	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
791	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
792	VERR_INVALID_FLAGS);
793	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
794	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
795	VERR_INVALID_PARAMETER);
796	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
797	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
798	VERR_INVALID_PARAMETER);
799	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
800	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
801	VERR_INVALID_PARAMETER);
802
803	/*
804	* Find insertion point. The lazy bird uses the same excuse as in
805	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
806	*/
807	uint32_t i;
808	if ( cLeaves > 0
809	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
810	{
811	/* Add at end. */
812	i = cLeaves;
813	}
814	else if ( cLeaves > 0
815	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
816	{
817	/* Either replacing the last leaf or dealing with sub-leaves. Spool
818	back to the first sub-leaf to pretend we did the linear search. */
819	i = cLeaves - 1;
820	while ( i > 0
821	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
822	i--;
823	}
824	else
825	{
826	/* Linear search from the start. */
827	i = 0;
828	while ( i < cLeaves
829	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
830	i++;
831	}
832	if ( i < cLeaves
833	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
834	{
835	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
836	{
837	/*
838	* The sub-leaf mask differs, replace all existing leaves with the
839	* same leaf number.
840	*/
841	uint32_t c = 1;
842	while ( i + c < cLeaves
843	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
844	c++;
845	if (c > 1 && i + c < cLeaves)
846	{
847	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
848	*pcLeaves = cLeaves -= c - 1;
849	}
850
851	paLeaves[i] = *pNewLeaf;
852	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
853	return VINF_SUCCESS;
854	}
855
856	/* Find sub-leaf insertion point. */
857	while ( i < cLeaves
858	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
859	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
860	i++;
861
862	/*
863	* If we've got an exactly matching leaf, replace it.
864	*/
865	if ( i < cLeaves
866	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
867	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
868	{
869	paLeaves[i] = *pNewLeaf;
870	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
871	return VINF_SUCCESS;
872	}
873	}
874
875	/*
876	* Adding a new leaf at 'i'.
877	*/
878	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
879	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
880	if (!paLeaves)
881	return VERR_NO_MEMORY;
882
883	if (i < cLeaves)
884	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
885	*pcLeaves += 1;
886	paLeaves[i] = *pNewLeaf;
887
888	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
889	return VINF_SUCCESS;
890	}
891
892
893	#ifndef IN_VBOX_CPU_REPORT
894	/**
895	* Removes a range of CPUID leaves.
896	*
897	* This will not reallocate the array.
898	*
899	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
900	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
901	* @param uFirst The first leaf.
902	* @param uLast The last leaf.
903	*/
904	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
905	{
906	uint32_t cLeaves = *pcLeaves;
907
908	Assert(uFirst <= uLast);
909
910	/*
911	* Find the first one.
912	*/
913	uint32_t iFirst = 0;
914	while ( iFirst < cLeaves
915	&& paLeaves[iFirst].uLeaf < uFirst)
916	iFirst++;
917
918	/*
919	* Find the end (last + 1).
920	*/
921	uint32_t iEnd = iFirst;
922	while ( iEnd < cLeaves
923	&& paLeaves[iEnd].uLeaf <= uLast)
924	iEnd++;
925
926	/*
927	* Adjust the array if anything needs removing.
928	*/
929	if (iFirst < iEnd)
930	{
931	if (iEnd < cLeaves)
932	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
933	*pcLeaves = cLeaves -= (iEnd - iFirst);
934	}
935
936	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
937	}
938	#endif /* IN_VBOX_CPU_REPORT */
939
940
941	/**
942	* Checks if ECX make a difference when reading a given CPUID leaf.
943	*
944	* @returns @c true if it does, @c false if it doesn't.
945	* @param uLeaf The leaf we're reading.
946	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
947	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
948	* final sub-leaf (for leaf 0xb only).
949	*/
950	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
951	{
952	*pfFinalEcxUnchanged = false;
953
954	uint32_t auCur[4];
955	uint32_t auPrev[4];
956	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
957
958	/* Look for sub-leaves. */
959	uint32_t uSubLeaf = 1;
960	for (;;)
961	{
962	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
963	if (memcmp(auCur, auPrev, sizeof(auCur)))
964	break;
965
966	/* Advance / give up. */
967	uSubLeaf++;
968	if (uSubLeaf >= 64)
969	{
970	*pcSubLeaves = 1;
971	return false;
972	}
973	}
974
975	/* Count sub-leaves. */
976	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
977	uint32_t cRepeats = 0;
978	uSubLeaf = 0;
979	for (;;)
980	{
981	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
982
983	/* Figuring out when to stop isn't entirely straight forward as we need
984	to cover undocumented behavior up to a point and implementation shortcuts. */
985
986	/* 1. Look for more than 4 repeating value sets. */
987	if ( auCur[0] == auPrev[0]
988	&& auCur[1] == auPrev[1]
989	&& ( auCur[2] == auPrev[2]
990	\|\| ( auCur[2] == uSubLeaf
991	&& auPrev[2] == uSubLeaf - 1) )
992	&& auCur[3] == auPrev[3])
993	{
994	if ( uLeaf != 0xd
995	\|\| uSubLeaf >= 64
996	\|\| ( auCur[0] == 0
997	&& auCur[1] == 0
998	&& auCur[2] == 0
999	&& auCur[3] == 0
1000	&& auPrev[2] == 0) )
1001	cRepeats++;
1002	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1003	break;
1004	}
1005	else
1006	cRepeats = 0;
1007
1008	/* 2. Look for zero values. */
1009	if ( auCur[0] == 0
1010	&& auCur[1] == 0
1011	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1012	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1013	&& uSubLeaf >= cMinLeaves)
1014	{
1015	cRepeats = 0;
1016	break;
1017	}
1018
1019	/* 3. Leaf 0xb level type 0 check. */
1020	if ( uLeaf == 0xb
1021	&& (auCur[2] & 0xff00) == 0
1022	&& (auPrev[2] & 0xff00) == 0)
1023	{
1024	cRepeats = 0;
1025	break;
1026	}
1027
1028	/* 99. Give up. */
1029	if (uSubLeaf >= 128)
1030	{
1031	#ifndef IN_VBOX_CPU_REPORT
1032	/* Ok, limit it according to the documentation if possible just to
1033	avoid annoying users with these detection issues. */
1034	uint32_t cDocLimit = UINT32_MAX;
1035	if (uLeaf == 0x4)
1036	cDocLimit = 4;
1037	else if (uLeaf == 0x7)
1038	cDocLimit = 1;
1039	else if (uLeaf == 0xd)
1040	cDocLimit = 63;
1041	else if (uLeaf == 0xf)
1042	cDocLimit = 2;
1043	if (cDocLimit != UINT32_MAX)
1044	{
1045	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1046	*pcSubLeaves = cDocLimit + 3;
1047	return true;
1048	}
1049	#endif
1050	*pcSubLeaves = UINT32_MAX;
1051	return true;
1052	}
1053
1054	/* Advance. */
1055	uSubLeaf++;
1056	memcpy(auPrev, auCur, sizeof(auCur));
1057	}
1058
1059	/* Standard exit. */
1060	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1061	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1062	if (*pcSubLeaves == 0)
1063	*pcSubLeaves = 1;
1064	return true;
1065	}
1066
1067
1068	/**
1069	* Gets a CPU ID leaf.
1070	*
1071	* @returns VBox status code.
1072	* @param pVM The cross context VM structure.
1073	* @param pLeaf Where to store the found leaf.
1074	* @param uLeaf The leaf to locate.
1075	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1076	*/
1077	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1078	{
1079	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1080	uLeaf, uSubLeaf);
1081	if (pcLeaf)
1082	{
1083	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1084	return VINF_SUCCESS;
1085	}
1086
1087	return VERR_NOT_FOUND;
1088	}
1089
1090
1091	/**
1092	* Inserts a CPU ID leaf, replacing any existing ones.
1093	*
1094	* @returns VBox status code.
1095	* @param pVM The cross context VM structure.
1096	* @param pNewLeaf Pointer to the leaf being inserted.
1097	*/
1098	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1099	{
1100	/*
1101	* Validate parameters.
1102	*/
1103	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1104	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1105
1106	/*
1107	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1108	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1109	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1110	*/
1111	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1112	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1113	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1114	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1115	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1116	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1117	{
1118	return VERR_NOT_SUPPORTED;
1119	}
1120
1121	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1122	}
1123
1124	/**
1125	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1126	*
1127	* @returns VBox status code.
1128	* @param ppaLeaves Where to return the array pointer on success.
1129	* Use RTMemFree to release.
1130	* @param pcLeaves Where to return the size of the array on
1131	* success.
1132	*/
1133	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1134	{
1135	*ppaLeaves = NULL;
1136	*pcLeaves = 0;
1137
1138	/*
1139	* Try out various candidates. This must be sorted!
1140	*/
1141	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1142	{
1143	{ UINT32_C(0x00000000), false },
1144	{ UINT32_C(0x10000000), false },
1145	{ UINT32_C(0x20000000), false },
1146	{ UINT32_C(0x30000000), false },
1147	{ UINT32_C(0x40000000), false },
1148	{ UINT32_C(0x50000000), false },
1149	{ UINT32_C(0x60000000), false },
1150	{ UINT32_C(0x70000000), false },
1151	{ UINT32_C(0x80000000), false },
1152	{ UINT32_C(0x80860000), false },
1153	{ UINT32_C(0x8ffffffe), true },
1154	{ UINT32_C(0x8fffffff), true },
1155	{ UINT32_C(0x90000000), false },
1156	{ UINT32_C(0xa0000000), false },
1157	{ UINT32_C(0xb0000000), false },
1158	{ UINT32_C(0xc0000000), false },
1159	{ UINT32_C(0xd0000000), false },
1160	{ UINT32_C(0xe0000000), false },
1161	{ UINT32_C(0xf0000000), false },
1162	};
1163
1164	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1165	{
1166	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1167	uint32_t uEax, uEbx, uEcx, uEdx;
1168	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1169
1170	/*
1171	* Does EAX look like a typical leaf count value?
1172	*/
1173	if ( uEax > uLeaf
1174	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1175	{
1176	/* Yes, dump them. */
1177	uint32_t cLeaves = uEax - uLeaf + 1;
1178	while (cLeaves-- > 0)
1179	{
1180	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1181
1182	uint32_t fFlags = 0;
1183
1184	/* There are currently three known leaves containing an APIC ID
1185	that needs EMT specific attention */
1186	if (uLeaf == 1)
1187	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1188	else if (uLeaf == 0xb && uEcx != 0)
1189	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1190	else if ( uLeaf == UINT32_C(0x8000001e)
1191	&& ( uEax
1192	\|\| uEbx
1193	\|\| uEdx
1194	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1195	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1196
1197	/* The APIC bit is per-VCpu and needs flagging. */
1198	if (uLeaf == 1)
1199	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1200	else if ( uLeaf == UINT32_C(0x80000001)
1201	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1202	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1203	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1204
1205	/* Check three times here to reduce the chance of CPU migration
1206	resulting in false positives with things like the APIC ID. */
1207	uint32_t cSubLeaves;
1208	bool fFinalEcxUnchanged;
1209	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1210	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1211	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1212	{
1213	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1214	{
1215	/* This shouldn't happen. But in case it does, file all
1216	relevant details in the release log. */
1217	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1218	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1219	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1220	{
1221	uint32_t auTmp[4];
1222	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1223	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1224	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1225	}
1226	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1227	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1228	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1229	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1230	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1231	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1232	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1233	}
1234
1235	if (fFinalEcxUnchanged)
1236	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1237
1238	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1239	{
1240	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1241	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1242	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1243	if (RT_FAILURE(rc))
1244	return rc;
1245	}
1246	}
1247	else
1248	{
1249	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1250	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1251	if (RT_FAILURE(rc))
1252	return rc;
1253	}
1254
1255	/* next */
1256	uLeaf++;
1257	}
1258	}
1259	/*
1260	* Special CPUIDs needs special handling as they don't follow the
1261	* leaf count principle used above.
1262	*/
1263	else if (s_aCandidates[iOuter].fSpecial)
1264	{
1265	bool fKeep = false;
1266	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1267	fKeep = true;
1268	else if ( uLeaf == 0x8fffffff
1269	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1270	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1271	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1272	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1273	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1274	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1275	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1276	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1277	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1278	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1279	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1280	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1281	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1282	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1283	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1284	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1285	fKeep = true;
1286	if (fKeep)
1287	{
1288	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1289	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1290	if (RT_FAILURE(rc))
1291	return rc;
1292	}
1293	}
1294	}
1295
1296	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1297	return VINF_SUCCESS;
1298	}
1299
1300
1301	/**
1302	* Determines the method the CPU uses to handle unknown CPUID leaves.
1303	*
1304	* @returns VBox status code.
1305	* @param penmUnknownMethod Where to return the method.
1306	* @param pDefUnknown Where to return default unknown values. This
1307	* will be set, even if the resulting method
1308	* doesn't actually needs it.
1309	*/
1310	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1311	{
1312	uint32_t uLastStd = ASMCpuId_EAX(0);
1313	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1314	if (!ASMIsValidExtRange(uLastExt))
1315	uLastExt = 0x80000000;
1316
1317	uint32_t auChecks[] =
1318	{
1319	uLastStd + 1,
1320	uLastStd + 5,
1321	uLastStd + 8,
1322	uLastStd + 32,
1323	uLastStd + 251,
1324	uLastExt + 1,
1325	uLastExt + 8,
1326	uLastExt + 15,
1327	uLastExt + 63,
1328	uLastExt + 255,
1329	0x7fbbffcc,
1330	0x833f7872,
1331	0xefff2353,
1332	0x35779456,
1333	0x1ef6d33e,
1334	};
1335
1336	static const uint32_t s_auValues[] =
1337	{
1338	0xa95d2156,
1339	0x00000001,
1340	0x00000002,
1341	0x00000008,
1342	0x00000000,
1343	0x55773399,
1344	0x93401769,
1345	0x12039587,
1346	};
1347
1348	/*
1349	* Simple method, all zeros.
1350	*/
1351	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1352	pDefUnknown->uEax = 0;
1353	pDefUnknown->uEbx = 0;
1354	pDefUnknown->uEcx = 0;
1355	pDefUnknown->uEdx = 0;
1356
1357	/*
1358	* Intel has been observed returning the last standard leaf.
1359	*/
1360	uint32_t auLast[4];
1361	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1362
1363	uint32_t cChecks = RT_ELEMENTS(auChecks);
1364	while (cChecks > 0)
1365	{
1366	uint32_t auCur[4];
1367	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1368	if (memcmp(auCur, auLast, sizeof(auCur)))
1369	break;
1370	cChecks--;
1371	}
1372	if (cChecks == 0)
1373	{
1374	/* Now, what happens when the input changes? Esp. ECX. */
1375	uint32_t cTotal = 0;
1376	uint32_t cSame = 0;
1377	uint32_t cLastWithEcx = 0;
1378	uint32_t cNeither = 0;
1379	uint32_t cValues = RT_ELEMENTS(s_auValues);
1380	while (cValues > 0)
1381	{
1382	uint32_t uValue = s_auValues[cValues - 1];
1383	uint32_t auLastWithEcx[4];
1384	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1385	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1386
1387	cChecks = RT_ELEMENTS(auChecks);
1388	while (cChecks > 0)
1389	{
1390	uint32_t auCur[4];
1391	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1392	if (!memcmp(auCur, auLast, sizeof(auCur)))
1393	{
1394	cSame++;
1395	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1396	cLastWithEcx++;
1397	}
1398	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1399	cLastWithEcx++;
1400	else
1401	cNeither++;
1402	cTotal++;
1403	cChecks--;
1404	}
1405	cValues--;
1406	}
1407
1408	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1409	if (cSame == cTotal)
1410	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1411	else if (cLastWithEcx == cTotal)
1412	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1413	else
1414	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1415	pDefUnknown->uEax = auLast[0];
1416	pDefUnknown->uEbx = auLast[1];
1417	pDefUnknown->uEcx = auLast[2];
1418	pDefUnknown->uEdx = auLast[3];
1419	return VINF_SUCCESS;
1420	}
1421
1422	/*
1423	* Unchanged register values?
1424	*/
1425	cChecks = RT_ELEMENTS(auChecks);
1426	while (cChecks > 0)
1427	{
1428	uint32_t const uLeaf = auChecks[cChecks - 1];
1429	uint32_t cValues = RT_ELEMENTS(s_auValues);
1430	while (cValues > 0)
1431	{
1432	uint32_t uValue = s_auValues[cValues - 1];
1433	uint32_t auCur[4];
1434	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1435	if ( auCur[0] != uLeaf
1436	\|\| auCur[1] != uValue
1437	\|\| auCur[2] != uValue
1438	\|\| auCur[3] != uValue)
1439	break;
1440	cValues--;
1441	}
1442	if (cValues != 0)
1443	break;
1444	cChecks--;
1445	}
1446	if (cChecks == 0)
1447	{
1448	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1449	return VINF_SUCCESS;
1450	}
1451
1452	/*
1453	* Just go with the simple method.
1454	*/
1455	return VINF_SUCCESS;
1456	}
1457
1458
1459	/**
1460	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1461	*
1462	* @returns Read only name string.
1463	* @param enmUnknownMethod The method to translate.
1464	*/
1465	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1466	{
1467	switch (enmUnknownMethod)
1468	{
1469	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1470	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1471	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1472	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1473
1474	case CPUMUNKNOWNCPUID_INVALID:
1475	case CPUMUNKNOWNCPUID_END:
1476	case CPUMUNKNOWNCPUID_32BIT_HACK:
1477	break;
1478	}
1479	return "Invalid-unknown-CPUID-method";
1480	}
1481
1482
1483	/**
1484	* Detect the CPU vendor give n the
1485	*
1486	* @returns The vendor.
1487	* @param uEAX EAX from CPUID(0).
1488	* @param uEBX EBX from CPUID(0).
1489	* @param uECX ECX from CPUID(0).
1490	* @param uEDX EDX from CPUID(0).
1491	*/
1492	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1493	{
1494	if (ASMIsValidStdRange(uEAX))
1495	{
1496	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1497	return CPUMCPUVENDOR_AMD;
1498
1499	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1500	return CPUMCPUVENDOR_INTEL;
1501
1502	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1503	return CPUMCPUVENDOR_VIA;
1504
1505	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1506	&& uECX == UINT32_C(0x64616574)
1507	&& uEDX == UINT32_C(0x736E4978))
1508	return CPUMCPUVENDOR_CYRIX;
1509
1510	/* "Geode by NSC", example: family 5, model 9. */
1511
1512	/** @todo detect the other buggers... */
1513	}
1514
1515	return CPUMCPUVENDOR_UNKNOWN;
1516	}
1517
1518
1519	/**
1520	* Translates a CPU vendor enum value into the corresponding string constant.
1521	*
1522	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1523	* value name. This can be useful when generating code.
1524	*
1525	* @returns Read only name string.
1526	* @param enmVendor The CPU vendor value.
1527	*/
1528	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1529	{
1530	switch (enmVendor)
1531	{
1532	case CPUMCPUVENDOR_INTEL: return "INTEL";
1533	case CPUMCPUVENDOR_AMD: return "AMD";
1534	case CPUMCPUVENDOR_VIA: return "VIA";
1535	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1536	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1537
1538	case CPUMCPUVENDOR_INVALID:
1539	case CPUMCPUVENDOR_32BIT_HACK:
1540	break;
1541	}
1542	return "Invalid-cpu-vendor";
1543	}
1544
1545
1546	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1547	{
1548	/* Could do binary search, doing linear now because I'm lazy. */
1549	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1550	while (cLeaves-- > 0)
1551	{
1552	if (pLeaf->uLeaf == uLeaf)
1553	return pLeaf;
1554	pLeaf++;
1555	}
1556	return NULL;
1557	}
1558
1559
1560	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1561	{
1562	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1563	if ( !pLeaf
1564	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1565	return pLeaf;
1566
1567	/* Linear sub-leaf search. Lazy as usual. */
1568	cLeaves -= pLeaf - paLeaves;
1569	while ( cLeaves-- > 0
1570	&& pLeaf->uLeaf == uLeaf)
1571	{
1572	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1573	return pLeaf;
1574	pLeaf++;
1575	}
1576
1577	return NULL;
1578	}
1579
1580
1581	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1582	{
1583	RT_ZERO(*pFeatures);
1584	if (cLeaves >= 2)
1585	{
1586	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1587	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1588	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1589	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1590	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1591	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1592
1593	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1594	pStd0Leaf->uEbx,
1595	pStd0Leaf->uEcx,
1596	pStd0Leaf->uEdx);
1597	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1598	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1599	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1600	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1601	pFeatures->uFamily,
1602	pFeatures->uModel,
1603	pFeatures->uStepping);
1604
1605	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1606	if (pLeaf)
1607	pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff;
1608	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1609	pFeatures->cMaxPhysAddrWidth = 36;
1610	else
1611	pFeatures->cMaxPhysAddrWidth = 32;
1612
1613	/* Standard features. */
1614	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1615	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1616	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1617	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1618	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1619	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1620	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1621	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1622	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1623	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1624	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1625	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1626	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1627	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1628	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1629	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1630	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1631	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1632	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1633	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1634	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1635	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1636	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1637
1638	/* Structured extended features. */
1639	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1640	if (pSxfLeaf0)
1641	{
1642	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEcx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1643	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEcx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1644	}
1645
1646	/* MWAIT/MONITOR leaf. */
1647	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1648	if (pMWaitLeaf)
1649	{
1650	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1651	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1652	}
1653
1654	/* Extended features. */
1655	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1656	if (pExtLeaf)
1657	{
1658	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1659	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1660	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1661	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1662	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1663	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1664	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1665	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1666	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1667	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1668	}
1669
1670	if ( pExtLeaf
1671	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1672	{
1673	/* AMD features. */
1674	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1675	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1676	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1677	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1678	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1679	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1680	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1681	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1682	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1683	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1684	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1685	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1686	if (pFeatures->fSvm)
1687	{
1688	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1689	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1690	pFeatures->svm.feat.u = pSvmLeaf->uEdx;
1691	pFeatures->svm.uMaxAsid = pSvmLeaf->uEbx;
1692	}
1693	}
1694
1695	/*
1696	* Quirks.
1697	*/
1698	pFeatures->fLeakyFxSR = pExtLeaf
1699	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1700	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1701	&& pFeatures->uFamily >= 6 /* K7 and up */;
1702
1703	/*
1704	* Max extended (/FPU) state.
1705	*/
1706	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1707	if (pFeatures->fXSaveRstor)
1708	{
1709	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1710	if (pXStateLeaf0)
1711	{
1712	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1713	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1714	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1715	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1716	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1717	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1718	{
1719	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1720
1721	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1722	if ( pXStateLeaf1
1723	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1724	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1725	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1726	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEbx;
1727	}
1728	else
1729	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1730	pFeatures->fXSaveRstor = 0);
1731	}
1732	else
1733	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1734	pFeatures->fXSaveRstor = 0);
1735	}
1736	}
1737	else
1738	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1739	return VINF_SUCCESS;
1740	}
1741
1742
1743	/*
1744	*
1745	* Init related code.
1746	* Init related code.
1747	* Init related code.
1748	*
1749	*
1750	*/
1751	#ifdef VBOX_IN_VMM
1752
1753
1754	/**
1755	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1756	*
1757	* This ignores the fSubLeafMask.
1758	*
1759	* @returns Pointer to the matching leaf, or NULL if not found.
1760	* @param paLeaves The CPUID leaves to search. This is sorted.
1761	* @param cLeaves The number of leaves in the array.
1762	* @param uLeaf The leaf to locate.
1763	* @param uSubLeaf The subleaf to locate.
1764	*/
1765	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1766	{
1767	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1768	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1769	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1770	if (iEnd)
1771	{
1772	uint32_t iBegin = 0;
1773	for (;;)
1774	{
1775	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1776	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1777	if (uNeedle < uCur)
1778	{
1779	if (i > iBegin)
1780	iEnd = i;
1781	else
1782	break;
1783	}
1784	else if (uNeedle > uCur)
1785	{
1786	if (i + 1 < iEnd)
1787	iBegin = i + 1;
1788	else
1789	break;
1790	}
1791	else
1792	return &paLeaves[i];
1793	}
1794	}
1795	return NULL;
1796	}
1797
1798
1799	/**
1800	* Loads MSR range overrides.
1801	*
1802	* This must be called before the MSR ranges are moved from the normal heap to
1803	* the hyper heap!
1804	*
1805	* @returns VBox status code (VMSetError called).
1806	* @param pVM The cross context VM structure.
1807	* @param pMsrNode The CFGM node with the MSR overrides.
1808	*/
1809	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1810	{
1811	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1812	{
1813	/*
1814	* Assemble a valid MSR range.
1815	*/
1816	CPUMMSRRANGE MsrRange;
1817	MsrRange.offCpumCpu = 0;
1818	MsrRange.fReserved = 0;
1819
1820	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1821	if (RT_FAILURE(rc))
1822	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1823
1824	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1825	if (RT_FAILURE(rc))
1826	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1827	MsrRange.szName, rc);
1828
1829	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1830	if (RT_FAILURE(rc))
1831	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1832	MsrRange.szName, rc);
1833
1834	char szType[32];
1835	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1836	if (RT_FAILURE(rc))
1837	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1838	MsrRange.szName, rc);
1839	if (!RTStrICmp(szType, "FixedValue"))
1840	{
1841	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1842	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1843
1844	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1845	if (RT_FAILURE(rc))
1846	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1847	MsrRange.szName, rc);
1848
1849	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1850	if (RT_FAILURE(rc))
1851	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1852	MsrRange.szName, rc);
1853
1854	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1855	if (RT_FAILURE(rc))
1856	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1857	MsrRange.szName, rc);
1858	}
1859	else
1860	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1861	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1862
1863	/*
1864	* Insert the range into the table (replaces/splits/shrinks existing
1865	* MSR ranges).
1866	*/
1867	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1868	&MsrRange);
1869	if (RT_FAILURE(rc))
1870	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
1871	}
1872
1873	return VINF_SUCCESS;
1874	}
1875
1876
1877	/**
1878	* Loads CPUID leaf overrides.
1879	*
1880	* This must be called before the CPUID leaves are moved from the normal
1881	* heap to the hyper heap!
1882	*
1883	* @returns VBox status code (VMSetError called).
1884	* @param pVM The cross context VM structure.
1885	* @param pParentNode The CFGM node with the CPUID leaves.
1886	* @param pszLabel How to label the overrides we're loading.
1887	*/
1888	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
1889	{
1890	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1891	{
1892	/*
1893	* Get the leaf and subleaf numbers.
1894	*/
1895	char szName[128];
1896	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
1897	if (RT_FAILURE(rc))
1898	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
1899
1900	/* The leaf number is either specified directly or thru the node name. */
1901	uint32_t uLeaf;
1902	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
1903	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1904	{
1905	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
1906	if (rc != VINF_SUCCESS)
1907	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
1908	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
1909	}
1910	else if (RT_FAILURE(rc))
1911	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
1912	pszLabel, szName, rc);
1913
1914	uint32_t uSubLeaf;
1915	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
1916	if (RT_FAILURE(rc))
1917	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
1918	pszLabel, szName, rc);
1919
1920	uint32_t fSubLeafMask;
1921	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
1922	if (RT_FAILURE(rc))
1923	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
1924	pszLabel, szName, rc);
1925
1926	/*
1927	* Look up the specified leaf, since the output register values
1928	* defaults to any existing values. This allows overriding a single
1929	* register, without needing to know the other values.
1930	*/
1931	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
1932	CPUMCPUIDLEAF Leaf;
1933	if (pLeaf)
1934	Leaf = *pLeaf;
1935	else
1936	RT_ZERO(Leaf);
1937	Leaf.uLeaf = uLeaf;
1938	Leaf.uSubLeaf = uSubLeaf;
1939	Leaf.fSubLeafMask = fSubLeafMask;
1940
1941	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
1942	if (RT_FAILURE(rc))
1943	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
1944	pszLabel, szName, rc);
1945	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
1946	if (RT_FAILURE(rc))
1947	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
1948	pszLabel, szName, rc);
1949	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
1950	if (RT_FAILURE(rc))
1951	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
1952	pszLabel, szName, rc);
1953	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
1954	if (RT_FAILURE(rc))
1955	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
1956	pszLabel, szName, rc);
1957
1958	/*
1959	* Insert the leaf into the table (replaces existing ones).
1960	*/
1961	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1962	&Leaf);
1963	if (RT_FAILURE(rc))
1964	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
1965	}
1966
1967	return VINF_SUCCESS;
1968	}
1969
1970
1971
1972	/**
1973	* Fetches overrides for a CPUID leaf.
1974	*
1975	* @returns VBox status code.
1976	* @param pLeaf The leaf to load the overrides into.
1977	* @param pCfgNode The CFGM node containing the overrides
1978	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
1979	* @param iLeaf The CPUID leaf number.
1980	*/
1981	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
1982	{
1983	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
1984	if (pLeafNode)
1985	{
1986	uint32_t u32;
1987	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
1988	if (RT_SUCCESS(rc))
1989	pLeaf->uEax = u32;
1990	else
1991	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1992
1993	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
1994	if (RT_SUCCESS(rc))
1995	pLeaf->uEbx = u32;
1996	else
1997	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1998
1999	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2000	if (RT_SUCCESS(rc))
2001	pLeaf->uEcx = u32;
2002	else
2003	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2004
2005	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2006	if (RT_SUCCESS(rc))
2007	pLeaf->uEdx = u32;
2008	else
2009	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2010
2011	}
2012	return VINF_SUCCESS;
2013	}
2014
2015
2016	/**
2017	* Load the overrides for a set of CPUID leaves.
2018	*
2019	* @returns VBox status code.
2020	* @param paLeaves The leaf array.
2021	* @param cLeaves The number of leaves.
2022	* @param uStart The start leaf number.
2023	* @param pCfgNode The CFGM node containing the overrides
2024	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2025	*/
2026	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2027	{
2028	for (uint32_t i = 0; i < cLeaves; i++)
2029	{
2030	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2031	if (RT_FAILURE(rc))
2032	return rc;
2033	}
2034
2035	return VINF_SUCCESS;
2036	}
2037
2038
2039	/**
2040	* Installs the CPUID leaves and explods the data into structures like
2041	* GuestFeatures and CPUMCTX::aoffXState.
2042	*
2043	* @returns VBox status code.
2044	* @param pVM The cross context VM structure.
2045	* @param pCpum The CPUM part of @a VM.
2046	* @param paLeaves The leaves. These will be copied (but not freed).
2047	* @param cLeaves The number of leaves.
2048	*/
2049	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
2050	{
2051	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2052
2053	/*
2054	* Install the CPUID information.
2055	*/
2056	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2057	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2058
2059	AssertLogRelRCReturn(rc, rc);
2060	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2061	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2062	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2063	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2064	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2065
2066	/*
2067	* Update the default CPUID leaf if necessary.
2068	*/
2069	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2070	{
2071	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2072	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2073	{
2074	/* We don't use CPUID(0).eax here because of the NT hack that only
2075	changes that value without actually removing any leaves. */
2076	uint32_t i = 0;
2077	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2078	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2079	{
2080	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2081	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2082	i++;
2083	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2084	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2085	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2086	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2087	}
2088	break;
2089	}
2090	default:
2091	break;
2092	}
2093
2094	/*
2095	* Explode the guest CPU features.
2096	*/
2097	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
2098	AssertLogRelRCReturn(rc, rc);
2099
2100	/*
2101	* Adjust the scalable bus frequency according to the CPUID information
2102	* we're now using.
2103	*/
2104	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2105	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2106	? UINT64_C(100000000) /* 100MHz */
2107	: UINT64_C(133333333); /* 133MHz */
2108
2109	/*
2110	* Populate the legacy arrays. Currently used for everything, later only
2111	* for patch manager.
2112	*/
2113	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2114	{
2115	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2116	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2117	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2118	};
2119	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2120	{
2121	uint32_t cLeft = aOldRanges[i].cCpuIds;
2122	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2123	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2124	while (cLeft-- > 0)
2125	{
2126	uLeaf--;
2127	pLegacyLeaf--;
2128
2129	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2130	if (pLeaf)
2131	{
2132	pLegacyLeaf->uEax = pLeaf->uEax;
2133	pLegacyLeaf->uEbx = pLeaf->uEbx;
2134	pLegacyLeaf->uEcx = pLeaf->uEcx;
2135	pLegacyLeaf->uEdx = pLeaf->uEdx;
2136	}
2137	else
2138	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2139	}
2140	}
2141
2142	/*
2143	* Configure XSAVE offsets according to the CPUID info.
2144	*/
2145	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2146	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2147	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2148	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2149	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2150	{
2151	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2152	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2153	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2154	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2155	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2156	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2157	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2158	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2159	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2160	pCpum->GuestFeatures.cbMaxExtendedState),
2161	VERR_CPUM_IPE_1);
2162	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2163	}
2164	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2165
2166	/* Copy the CPU #0 data to the other CPUs. */
2167	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2168	{
2169	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2170	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2171	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2172	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2173	}
2174
2175	return VINF_SUCCESS;
2176	}
2177
2178
2179	/** @name Instruction Set Extension Options
2180	* @{ */
2181	/** Configuration option type (extended boolean, really). */
2182	typedef uint8_t CPUMISAEXTCFG;
2183	/** Always disable the extension. */
2184	#define CPUMISAEXTCFG_DISABLED false
2185	/** Enable the extension if it's supported by the host CPU. */
2186	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2187	/** Enable the extension if it's supported by the host CPU, but don't let
2188	* the portable CPUID feature disable it. */
2189	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2190	/** Always enable the extension. */
2191	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2192	/** @} */
2193
2194	/**
2195	* CPUID Configuration (from CFGM).
2196	*
2197	* @remarks The members aren't document since we would only be duplicating the
2198	* \@cfgm entries in cpumR3CpuIdReadConfig.
2199	*/
2200	typedef struct CPUMCPUIDCONFIG
2201	{
2202	bool fNt4LeafLimit;
2203	bool fInvariantTsc;
2204
2205	CPUMISAEXTCFG enmCmpXchg16b;
2206	CPUMISAEXTCFG enmMonitor;
2207	CPUMISAEXTCFG enmMWaitExtensions;
2208	CPUMISAEXTCFG enmSse41;
2209	CPUMISAEXTCFG enmSse42;
2210	CPUMISAEXTCFG enmAvx;
2211	CPUMISAEXTCFG enmAvx2;
2212	CPUMISAEXTCFG enmXSave;
2213	CPUMISAEXTCFG enmAesNi;
2214	CPUMISAEXTCFG enmPClMul;
2215	CPUMISAEXTCFG enmPopCnt;
2216	CPUMISAEXTCFG enmMovBe;
2217	CPUMISAEXTCFG enmRdRand;
2218	CPUMISAEXTCFG enmRdSeed;
2219	CPUMISAEXTCFG enmCLFlushOpt;
2220
2221	CPUMISAEXTCFG enmAbm;
2222	CPUMISAEXTCFG enmSse4A;
2223	CPUMISAEXTCFG enmMisAlnSse;
2224	CPUMISAEXTCFG enm3dNowPrf;
2225	CPUMISAEXTCFG enmAmdExtMmx;
2226	CPUMISAEXTCFG enmSvm;
2227
2228	uint32_t uMaxStdLeaf;
2229	uint32_t uMaxExtLeaf;
2230	uint32_t uMaxCentaurLeaf;
2231	uint32_t uMaxIntelFamilyModelStep;
2232	char szCpuName[128];
2233	} CPUMCPUIDCONFIG;
2234	/** Pointer to CPUID config (from CFGM). */
2235	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2236
2237
2238	/**
2239	* Mini CPU selection support for making Mac OS X happy.
2240	*
2241	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2242	*
2243	* @param pCpum The CPUM instance data.
2244	* @param pConfig The CPUID configuration we've read from CFGM.
2245	*/
2246	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2247	{
2248	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2249	{
2250	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2251	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2252	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2253	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2254	0);
2255	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2256	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2257	{
2258	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2259	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2260	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2261	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2262	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2263	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2264	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2265	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2266	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2267	pStdFeatureLeaf->uEax = uNew;
2268	}
2269	}
2270	}
2271
2272
2273
2274	/**
2275	* Limit it the number of entries, zapping the remainder.
2276	*
2277	* The limits are masking off stuff about power saving and similar, this
2278	* is perhaps a bit crudely done as there is probably some relatively harmless
2279	* info too in these leaves (like words about having a constant TSC).
2280	*
2281	* @param pCpum The CPUM instance data.
2282	* @param pConfig The CPUID configuration we've read from CFGM.
2283	*/
2284	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2285	{
2286	/*
2287	* Standard leaves.
2288	*/
2289	uint32_t uSubLeaf = 0;
2290	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2291	if (pCurLeaf)
2292	{
2293	uint32_t uLimit = pCurLeaf->uEax;
2294	if (uLimit <= UINT32_C(0x000fffff))
2295	{
2296	if (uLimit > pConfig->uMaxStdLeaf)
2297	{
2298	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2299	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2300	uLimit + 1, UINT32_C(0x000fffff));
2301	}
2302
2303	/* NT4 hack, no zapping of extra leaves here. */
2304	if (pConfig->fNt4LeafLimit && uLimit > 3)
2305	pCurLeaf->uEax = uLimit = 3;
2306
2307	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2308	pCurLeaf->uEax = uLimit;
2309	}
2310	else
2311	{
2312	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2313	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2314	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2315	}
2316	}
2317
2318	/*
2319	* Extended leaves.
2320	*/
2321	uSubLeaf = 0;
2322	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2323	if (pCurLeaf)
2324	{
2325	uint32_t uLimit = pCurLeaf->uEax;
2326	if ( uLimit >= UINT32_C(0x80000000)
2327	&& uLimit <= UINT32_C(0x800fffff))
2328	{
2329	if (uLimit > pConfig->uMaxExtLeaf)
2330	{
2331	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2332	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2333	uLimit + 1, UINT32_C(0x800fffff));
2334	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2335	pCurLeaf->uEax = uLimit;
2336	}
2337	}
2338	else
2339	{
2340	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2341	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2342	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2343	}
2344	}
2345
2346	/*
2347	* Centaur leaves (VIA).
2348	*/
2349	uSubLeaf = 0;
2350	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2351	if (pCurLeaf)
2352	{
2353	uint32_t uLimit = pCurLeaf->uEax;
2354	if ( uLimit >= UINT32_C(0xc0000000)
2355	&& uLimit <= UINT32_C(0xc00fffff))
2356	{
2357	if (uLimit > pConfig->uMaxCentaurLeaf)
2358	{
2359	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2360	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2361	uLimit + 1, UINT32_C(0xcfffffff));
2362	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2363	pCurLeaf->uEax = uLimit;
2364	}
2365	}
2366	else
2367	{
2368	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2369	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2370	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2371	}
2372	}
2373	}
2374
2375
2376	/**
2377	* Clears a CPUID leaf and all sub-leaves (to zero).
2378	*
2379	* @param pCpum The CPUM instance data.
2380	* @param uLeaf The leaf to clear.
2381	*/
2382	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2383	{
2384	uint32_t uSubLeaf = 0;
2385	PCPUMCPUIDLEAF pCurLeaf;
2386	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2387	{
2388	pCurLeaf->uEax = 0;
2389	pCurLeaf->uEbx = 0;
2390	pCurLeaf->uEcx = 0;
2391	pCurLeaf->uEdx = 0;
2392	uSubLeaf++;
2393	}
2394	}
2395
2396
2397	/**
2398	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2399	* the given leaf.
2400	*
2401	* @returns pLeaf.
2402	* @param pCpum The CPUM instance data.
2403	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2404	*/
2405	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2406	{
2407	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2408	if (pLeaf->fSubLeafMask != 0)
2409	{
2410	/*
2411	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2412	* Log everything while we're at it.
2413	*/
2414	LogRel(("CPUM:\n"
2415	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2416	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2417	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2418	for (;;)
2419	{
2420	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2421	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2422	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2423	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2424	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2425	break;
2426	pSubLeaf++;
2427	}
2428	LogRel(("CPUM:\n"));
2429
2430	/*
2431	* Remove the offending sub-leaves.
2432	*/
2433	if (pSubLeaf != pLeaf)
2434	{
2435	if (pSubLeaf != pLast)
2436	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2437	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2438	}
2439
2440	/*
2441	* Convert the first sub-leaf into a single leaf.
2442	*/
2443	pLeaf->uSubLeaf = 0;
2444	pLeaf->fSubLeafMask = 0;
2445	}
2446	return pLeaf;
2447	}
2448
2449
2450	/**
2451	* Sanitizes and adjust the CPUID leaves.
2452	*
2453	* Drop features that aren't virtualized (or virtualizable). Adjust information
2454	* and capabilities to fit the virtualized hardware. Remove information the
2455	* guest shouldn't have (because it's wrong in the virtual world or because it
2456	* gives away host details) or that we don't have documentation for and no idea
2457	* what means.
2458	*
2459	* @returns VBox status code.
2460	* @param pVM The cross context VM structure (for cCpus).
2461	* @param pCpum The CPUM instance data.
2462	* @param pConfig The CPUID configuration we've read from CFGM.
2463	*/
2464	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2465	{
2466	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2467	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2468	{ \
2469	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2470	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2471	}
2472	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2473	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2474	{ \
2475	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2476	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2477	}
2478	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2479	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2480	&& ((a_pLeafReg) & (fBitMask)) \
2481	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2482	{ \
2483	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2484	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2485	}
2486	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2487
2488	/* Cpuid 1:
2489	* EAX: CPU model, family and stepping.
2490	*
2491	* ECX + EDX: Supported features. Only report features we can support.
2492	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2493	* options may require adjusting (i.e. stripping what was enabled).
2494	*
2495	* EBX: Branding, CLFLUSH line size, logical processors per package and
2496	* initial APIC ID.
2497	*/
2498	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2499	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2500	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2501
2502	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2503	\| X86_CPUID_FEATURE_EDX_VME
2504	\| X86_CPUID_FEATURE_EDX_DE
2505	\| X86_CPUID_FEATURE_EDX_PSE
2506	\| X86_CPUID_FEATURE_EDX_TSC
2507	\| X86_CPUID_FEATURE_EDX_MSR
2508	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2509	\| X86_CPUID_FEATURE_EDX_MCE
2510	\| X86_CPUID_FEATURE_EDX_CX8
2511	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2512	//\| RT_BIT_32(10) - not defined
2513	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2514	//\| X86_CPUID_FEATURE_EDX_SEP
2515	\| X86_CPUID_FEATURE_EDX_MTRR
2516	\| X86_CPUID_FEATURE_EDX_PGE
2517	\| X86_CPUID_FEATURE_EDX_MCA
2518	\| X86_CPUID_FEATURE_EDX_CMOV
2519	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2520	\| X86_CPUID_FEATURE_EDX_PSE36
2521	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2522	\| X86_CPUID_FEATURE_EDX_CLFSH
2523	//\| RT_BIT_32(20) - not defined
2524	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2525	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2526	\| X86_CPUID_FEATURE_EDX_MMX
2527	\| X86_CPUID_FEATURE_EDX_FXSR
2528	\| X86_CPUID_FEATURE_EDX_SSE
2529	\| X86_CPUID_FEATURE_EDX_SSE2
2530	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2531	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading/cores - see below.
2532	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2533	//\| RT_BIT_32(30) - not defined
2534	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2535	;
2536	pStdFeatureLeaf->uEcx &= 0
2537	\| X86_CPUID_FEATURE_ECX_SSE3
2538	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2539	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2540	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2541	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2542	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2543	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized yet.
2544	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2545	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2546	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2547	\| X86_CPUID_FEATURE_ECX_SSSE3
2548	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2549	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2550	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2551	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2552	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2553	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2554	//\| X86_CPUID_FEATURE_ECX_PCID - not implemented yet.
2555	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2556	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2557	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2558	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2559	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2560	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2561	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2562	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2563	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2564	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2565	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2566	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2567	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2568	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2569	;
2570
2571	if (pCpum->u8PortableCpuIdLevel > 0)
2572	{
2573	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2574	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2575	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2576	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2577	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2578	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2579	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2580	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2581	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2582	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2583	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2584	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2585	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2586	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2587	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2588	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2589	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2590	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2591
2592	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2593	\| X86_CPUID_FEATURE_EDX_PSN
2594	\| X86_CPUID_FEATURE_EDX_DS
2595	\| X86_CPUID_FEATURE_EDX_ACPI
2596	\| X86_CPUID_FEATURE_EDX_SS
2597	\| X86_CPUID_FEATURE_EDX_TM
2598	\| X86_CPUID_FEATURE_EDX_PBE
2599	)));
2600	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2601	\| X86_CPUID_FEATURE_ECX_CPLDS
2602	\| X86_CPUID_FEATURE_ECX_VMX
2603	\| X86_CPUID_FEATURE_ECX_SMX
2604	\| X86_CPUID_FEATURE_ECX_EST
2605	\| X86_CPUID_FEATURE_ECX_TM2
2606	\| X86_CPUID_FEATURE_ECX_CNTXID
2607	\| X86_CPUID_FEATURE_ECX_FMA
2608	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2609	\| X86_CPUID_FEATURE_ECX_PDCM
2610	\| X86_CPUID_FEATURE_ECX_DCA
2611	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2612	)));
2613	}
2614
2615	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2616	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2617	#ifdef VBOX_WITH_MULTI_CORE
2618	if (pVM->cCpus > 1)
2619	{
2620	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2621	core times the number of CPU cores per processor */
2622	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2623	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
2624	}
2625	#endif
2626
2627	/* Force standard feature bits. */
2628	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2629	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2630	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2631	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2632	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2633	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2634	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2635	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2636	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2637	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2638	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2639	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2640	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2641	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2642	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2643	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2644	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2645	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2646	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2647	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2648	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2649	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2650
2651	pStdFeatureLeaf = NULL; /* Must refetch! */
2652
2653	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2654	* AMD:
2655	* EAX: CPU model, family and stepping.
2656	*
2657	* ECX + EDX: Supported features. Only report features we can support.
2658	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2659	* options may require adjusting (i.e. stripping what was enabled).
2660	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2661	*
2662	* EBX: Branding ID and package type (or reserved).
2663	*
2664	* Intel and probably most others:
2665	* EAX: 0
2666	* EBX: 0
2667	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2668	*/
2669	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2670	if (pExtFeatureLeaf)
2671	{
2672	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2673
2674	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2675	\| X86_CPUID_AMD_FEATURE_EDX_VME
2676	\| X86_CPUID_AMD_FEATURE_EDX_DE
2677	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2678	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2679	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2680	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2681	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2682	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2683	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2684	//\| RT_BIT_32(10) - reserved
2685	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2686	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2687	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2688	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2689	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2690	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2691	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2692	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2693	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2694	//\| RT_BIT_32(18) - reserved
2695	//\| RT_BIT_32(19) - reserved
2696	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2697	//\| RT_BIT_32(21) - reserved
2698	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2699	\| X86_CPUID_AMD_FEATURE_EDX_MMX
2700	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
2701	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
2702	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2703	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2704	//\| RT_BIT_32(28) - reserved
2705	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2706	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2707	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
2708	;
2709	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2710	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2711	\| (pConfig->enmSvm ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
2712	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2713	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
2714	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2715	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2716	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2717	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2718	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2719	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2720	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
2721	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
2722	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2723	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
2724	//\| RT_BIT_32(14) - reserved
2725	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2726	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2727	//\| RT_BIT_32(17) - reserved
2728	//\| RT_BIT_32(18) - reserved
2729	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2730	//\| RT_BIT_32(20) - reserved
2731	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2732	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2733	//\| RT_BIT_32(23) - reserved
2734	//\| RT_BIT_32(24) - reserved
2735	//\| RT_BIT_32(25) - reserved
2736	//\| RT_BIT_32(26) - reserved
2737	//\| RT_BIT_32(27) - reserved
2738	//\| RT_BIT_32(28) - reserved
2739	//\| RT_BIT_32(29) - reserved
2740	//\| RT_BIT_32(30) - reserved
2741	//\| RT_BIT_32(31) - reserved
2742	;
2743	#ifdef VBOX_WITH_MULTI_CORE
2744	if ( pVM->cCpus > 1
2745	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2746	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2747	#endif
2748
2749	if (pCpum->u8PortableCpuIdLevel > 0)
2750	{
2751	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2752	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM, pConfig->enmSvm);
2753	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2754	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2755	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2756	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2757	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2758	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2759	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2760	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2761	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2762	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2763	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2764	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2765	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2766	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2767
2768	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2769	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2770	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2771	\| X86_CPUID_AMD_FEATURE_ECX_IBS
2772	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2773	\| X86_CPUID_AMD_FEATURE_ECX_WDT
2774	\| X86_CPUID_AMD_FEATURE_ECX_LWP
2775	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
2776	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2777	\| UINT32_C(0xff964000)
2778	)));
2779	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2780	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2781	\| RT_BIT(18)
2782	\| RT_BIT(19)
2783	\| RT_BIT(21)
2784	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2785	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2786	\| RT_BIT(28)
2787	)));
2788	}
2789
2790	/* Force extended feature bits. */
2791	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2792	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
2793	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2794	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2795	if (pConfig->enmSvm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2796	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SVM;
2797	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2798	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2799	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2800	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2801	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2802	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2803	if (pConfig->enmSvm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2804	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SVM;
2805	}
2806	pExtFeatureLeaf = NULL; /* Must refetch! */
2807
2808
2809	/* Cpuid 2:
2810	* Intel: (Nondeterministic) Cache and TLB information
2811	* AMD: Reserved
2812	* VIA: Reserved
2813	* Safe to expose.
2814	*/
2815	uint32_t uSubLeaf = 0;
2816	PCPUMCPUIDLEAF pCurLeaf;
2817	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2818	{
2819	if ((pCurLeaf->uEax & 0xff) > 1)
2820	{
2821	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2822	pCurLeaf->uEax &= UINT32_C(0xffffff01);
2823	}
2824	uSubLeaf++;
2825	}
2826
2827	/* Cpuid 3:
2828	* Intel: EAX, EBX - reserved (transmeta uses these)
2829	* ECX, EDX - Processor Serial Number if available, otherwise reserved
2830	* AMD: Reserved
2831	* VIA: Reserved
2832	* Safe to expose
2833	*/
2834	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2835	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
2836	{
2837	uSubLeaf = 0;
2838	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
2839	{
2840	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2841	if (pCpum->u8PortableCpuIdLevel > 0)
2842	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2843	uSubLeaf++;
2844	}
2845	}
2846
2847	/* Cpuid 4 + ECX:
2848	* Intel: Deterministic Cache Parameters Leaf.
2849	* AMD: Reserved
2850	* VIA: Reserved
2851	* Safe to expose, except for EAX:
2852	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
2853	* Bits 31-26: Maximum number of processor cores in this physical package**
2854	* Note: These SMP values are constant regardless of ECX
2855	*/
2856	uSubLeaf = 0;
2857	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
2858	{
2859	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
2860	#ifdef VBOX_WITH_MULTI_CORE
2861	if ( pVM->cCpus > 1
2862	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2863	{
2864	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
2865	/* One logical processor with possibly multiple cores. */
2866	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
2867	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
2868	}
2869	#endif
2870	uSubLeaf++;
2871	}
2872
2873	/* Cpuid 5: Monitor/mwait Leaf
2874	* Intel: ECX, EDX - reserved
2875	* EAX, EBX - Smallest and largest monitor line size
2876	* AMD: EDX - reserved
2877	* EAX, EBX - Smallest and largest monitor line size
2878	* ECX - extensions (ignored for now)
2879	* VIA: Reserved
2880	* Safe to expose
2881	*/
2882	uSubLeaf = 0;
2883	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
2884	{
2885	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2886	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
2887	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2888
2889	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2890	if (pConfig->enmMWaitExtensions)
2891	{
2892	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
2893	/** @todo for now we just expose host's MWAIT C-states, although conceptually
2894	it shall be part of our power management virtualization model */
2895	#if 0
2896	/* MWAIT sub C-states */
2897	pCurLeaf->uEdx =
2898	(0 << 0) /* 0 in C0 */ \|
2899	(2 << 4) /* 2 in C1 */ \|
2900	(2 << 8) /* 2 in C2 */ \|
2901	(2 << 12) /* 2 in C3 */ \|
2902	(0 << 16) /* 0 in C4 */
2903	;
2904	#endif
2905	}
2906	else
2907	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2908	uSubLeaf++;
2909	}
2910
2911	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
2912	* Intel: Various stuff.
2913	* AMD: EAX, EBX, EDX - reserved.
2914	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
2915	* present. Same as intel.
2916	* VIA: ??
2917	*
2918	* We clear everything here for now.
2919	*/
2920	cpumR3CpuIdZeroLeaf(pCpum, 6);
2921
2922	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
2923	* EAX: Number of sub leaves.
2924	* EBX+ECX+EDX: Feature flags
2925	*
2926	* We only have documentation for one sub-leaf, so clear all other (no need
2927	* to remove them as such, just set them to zero).
2928	*
2929	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2930	* options may require adjusting (i.e. stripping what was enabled).
2931	*/
2932	uSubLeaf = 0;
2933	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
2934	{
2935	switch (uSubLeaf)
2936	{
2937	case 0:
2938	{
2939	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
2940	pCurLeaf->uEbx &= 0
2941	//\| X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
2942	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
2943	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
2944	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
2945	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
2946	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
2947	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
2948	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
2949	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
2950	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
2951	//\| X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
2952	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
2953	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
2954	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
2955	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
2956	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
2957	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
2958	//\| RT_BIT(17) - reserved
2959	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
2960	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
2961	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
2962	//\| RT_BIT(21) - reserved
2963	//\| RT_BIT(22) - reserved
2964	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
2965	//\| RT_BIT(24) - reserved
2966	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
2967	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
2968	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
2969	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
2970	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
2971	//\| RT_BIT(30) - reserved
2972	//\| RT_BIT(31) - reserved
2973	;
2974	pCurLeaf->uEcx &= 0
2975	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
2976	;
2977	pCurLeaf->uEdx &= 0;
2978
2979	if (pCpum->u8PortableCpuIdLevel > 0)
2980	{
2981	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
2982	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
2983	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
2984	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
2985	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
2986	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
2987	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
2988	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
2989	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
2990	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
2991	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
2992	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
2993	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
2994	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
2995	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
2996	}
2997
2998	/* Force standard feature bits. */
2999	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3000	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3001	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3002	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3003	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3004	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3005	break;
3006	}
3007
3008	default:
3009	/* Invalid index, all values are zero. */
3010	pCurLeaf->uEax = 0;
3011	pCurLeaf->uEbx = 0;
3012	pCurLeaf->uEcx = 0;
3013	pCurLeaf->uEdx = 0;
3014	break;
3015	}
3016	uSubLeaf++;
3017	}
3018
3019	/* Cpuid 8: Marked as reserved by Intel and AMD.
3020	* We zero this since we don't know what it may have been used for.
3021	*/
3022	cpumR3CpuIdZeroLeaf(pCpum, 8);
3023
3024	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3025	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3026	* EBX, ECX, EDX - reserved.
3027	* AMD: Reserved
3028	* VIA: ??
3029	*
3030	* We zero this.
3031	*/
3032	cpumR3CpuIdZeroLeaf(pCpum, 9);
3033
3034	/* Cpuid 0xa: Architectural Performance Monitor Features
3035	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3036	* EBX, ECX, EDX - reserved.
3037	* AMD: Reserved
3038	* VIA: ??
3039	*
3040	* We zero this, for now at least.
3041	*/
3042	cpumR3CpuIdZeroLeaf(pCpum, 10);
3043
3044	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3045	* Intel: EAX - APCI ID shift right for next level.
3046	* EBX - Factory configured cores/threads at this level.
3047	* ECX - Level number (same as input) and level type (1,2,0).
3048	* EDX - Extended initial APIC ID.
3049	* AMD: Reserved
3050	* VIA: ??
3051	*/
3052	uSubLeaf = 0;
3053	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3054	{
3055	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3056	{
3057	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3058	if (bLevelType == 1)
3059	{
3060	/* Thread level - we don't do threads at the moment. */
3061	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3062	pCurLeaf->uEbx = 1;
3063	}
3064	else if (bLevelType == 2)
3065	{
3066	/* Core level. */
3067	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3068	#ifdef VBOX_WITH_MULTI_CORE
3069	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3070	pCurLeaf->uEax++;
3071	#endif
3072	pCurLeaf->uEbx = pVM->cCpus;
3073	}
3074	else
3075	{
3076	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3077	pCurLeaf->uEax = 0;
3078	pCurLeaf->uEbx = 0;
3079	pCurLeaf->uEcx = 0;
3080	}
3081	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3082	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3083	}
3084	else
3085	{
3086	pCurLeaf->uEax = 0;
3087	pCurLeaf->uEbx = 0;
3088	pCurLeaf->uEcx = 0;
3089	pCurLeaf->uEdx = 0;
3090	}
3091	uSubLeaf++;
3092	}
3093
3094	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3095	* We zero this since we don't know what it may have been used for.
3096	*/
3097	cpumR3CpuIdZeroLeaf(pCpum, 12);
3098
3099	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3100	* ECX=0: EAX - Valid bits in XCR0[31:0].
3101	* EBX - Maximum state size as per current XCR0 value.
3102	* ECX - Maximum state size for all supported features.
3103	* EDX - Valid bits in XCR0[63:32].
3104	* ECX=1: EAX - Various X-features.
3105	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3106	* ECX - Valid bits in IA32_XSS[31:0].
3107	* EDX - Valid bits in IA32_XSS[63:32].
3108	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3109	* if the bit invalid all four registers are set to zero.
3110	* EAX - The state size for this feature.
3111	* EBX - The state byte offset of this feature.
3112	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3113	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3114	*
3115	* Clear them all as we don't currently implement extended CPU state.
3116	*/
3117	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3118	uint64_t fGuestXcr0Mask = 0;
3119	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3120	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3121	{
3122	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3123	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3124	fGuestXcr0Mask \|= XSAVE_C_YMM;
3125	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3126	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3127	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3128	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3129
3130	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3131	}
3132	pStdFeatureLeaf = NULL;
3133	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3134
3135	/* Work the sub-leaves. */
3136	uint32_t cbXSaveMax = sizeof(X86FXSTATE);
3137	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3138	{
3139	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3140	if (pCurLeaf)
3141	{
3142	if (fGuestXcr0Mask)
3143	{
3144	switch (uSubLeaf)
3145	{
3146	case 0:
3147	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3148	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3149	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3150	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3151	VERR_CPUM_IPE_1);
3152	cbXSaveMax = pCurLeaf->uEcx;
3153	AssertLogRelMsgReturn(cbXSaveMax <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMax >= CPUM_MIN_XSAVE_AREA_SIZE,
3154	("%#x max=%#x\n", cbXSaveMax, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3155	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMax,
3156	("ebx=%#x cbXSaveMax=%#x\n", pCurLeaf->uEbx, cbXSaveMax),
3157	VERR_CPUM_IPE_2);
3158	continue;
3159	case 1:
3160	pCurLeaf->uEax &= 0;
3161	pCurLeaf->uEcx &= 0;
3162	pCurLeaf->uEdx &= 0;
3163	/** @todo what about checking ebx? */
3164	continue;
3165	default:
3166	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3167	{
3168	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMax
3169	&& pCurLeaf->uEax > 0
3170	&& pCurLeaf->uEbx < cbXSaveMax
3171	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3172	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMax,
3173	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3174	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMax),
3175	VERR_CPUM_IPE_2);
3176	AssertLogRel(!(pCurLeaf->uEcx & 1));
3177	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3178	pCurLeaf->uEdx = 0; /* it's reserved... */
3179	continue;
3180	}
3181	break;
3182	}
3183	}
3184
3185	/* Clear the leaf. */
3186	pCurLeaf->uEax = 0;
3187	pCurLeaf->uEbx = 0;
3188	pCurLeaf->uEcx = 0;
3189	pCurLeaf->uEdx = 0;
3190	}
3191	}
3192
3193	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3194	* We zero this since we don't know what it may have been used for.
3195	*/
3196	cpumR3CpuIdZeroLeaf(pCpum, 14);
3197
3198	/* Cpuid 0xf + ECX: Platform qualifity of service monitoring (PQM).
3199	* We zero this as we don't currently virtualize PQM.
3200	*/
3201	cpumR3CpuIdZeroLeaf(pCpum, 15);
3202
3203	/* Cpuid 0x10 + ECX: Platform qualifity of service enforcement (PQE).
3204	* We zero this as we don't currently virtualize PQE.
3205	*/
3206	cpumR3CpuIdZeroLeaf(pCpum, 16);
3207
3208	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3209	* We zero this since we don't know what it may have been used for.
3210	*/
3211	cpumR3CpuIdZeroLeaf(pCpum, 17);
3212
3213	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3214	* We zero this as we don't currently virtualize this.
3215	*/
3216	cpumR3CpuIdZeroLeaf(pCpum, 18);
3217
3218	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3219	* We zero this since we don't know what it may have been used for.
3220	*/
3221	cpumR3CpuIdZeroLeaf(pCpum, 19);
3222
3223	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3224	* We zero this as we don't currently virtualize this.
3225	*/
3226	cpumR3CpuIdZeroLeaf(pCpum, 20);
3227
3228	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3229	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3230	* EAX - denominator (unsigned).
3231	* EBX - numerator (unsigned).
3232	* ECX, EDX - reserved.
3233	* AMD: Reserved / undefined / not implemented.
3234	* VIA: Reserved / undefined / not implemented.
3235	* We zero this as we don't currently virtualize this.
3236	*/
3237	cpumR3CpuIdZeroLeaf(pCpum, 21);
3238
3239	/* Cpuid 0x16: Processor frequency info
3240	* Intel: EAX - Core base frequency in MHz.
3241	* EBX - Core maximum frequency in MHz.
3242	* ECX - Bus (reference) frequency in MHz.
3243	* EDX - Reserved.
3244	* AMD: Reserved / undefined / not implemented.
3245	* VIA: Reserved / undefined / not implemented.
3246	* We zero this as we don't currently virtualize this.
3247	*/
3248	cpumR3CpuIdZeroLeaf(pCpum, 22);
3249
3250	/* Cpuid 0x17..0x10000000: Unknown.
3251	* We don't know these and what they mean, so remove them. */
3252	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3253	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3254
3255
3256	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3257	* We remove all these as we're a hypervisor and must provide our own.
3258	*/
3259	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3260	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3261
3262
3263	/* Cpuid 0x80000000 is harmless. */
3264
3265	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3266
3267	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3268
3269	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3270	* Safe to pass on to the guest.
3271	*
3272	* AMD: 0x800000005 L1 cache information
3273	* 0x800000006 L2/L3 cache information
3274	* Intel: 0x800000005 reserved
3275	* 0x800000006 L2 cache information
3276	* VIA: 0x800000005 TLB and L1 cache information
3277	* 0x800000006 L2 cache information
3278	*/
3279
3280	/* Cpuid 0x800000007: Advanced Power Management Information.
3281	* AMD: EAX: Processor feedback capabilities.
3282	* EBX: RAS capabilites.
3283	* ECX: Advanced power monitoring interface.
3284	* EDX: Enhanced power management capabilities.
3285	* Intel: EAX, EBX, ECX - reserved.
3286	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3287	* VIA: Reserved
3288	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3289	*/
3290	uSubLeaf = 0;
3291	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3292	{
3293	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3294	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3295	{
3296	pCurLeaf->uEdx &= 0
3297	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3298	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3299	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3300	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3301	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3302	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3303	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3304	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3305	#if 0 /*
3306	* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
3307	* Linux kernels blindly assume that the AMD performance counters work
3308	* if this is set for 64 bits guests. (Can't really find a CPUID feature
3309	* bit for them though.)
3310	*/
3311	/** @todo need to recheck this with new MSR emulation. */
3312	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3313	#endif
3314	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3315	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3316	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3317	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3318	\| 0;
3319	}
3320	else
3321	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3322	if (pConfig->fInvariantTsc)
3323	pCurLeaf->uEdx \|= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3324	uSubLeaf++;
3325	}
3326
3327	/* Cpuid 0x80000008:
3328	* AMD: EBX, EDX - reserved
3329	* EAX: Virtual/Physical/Guest address Size
3330	* ECX: Number of cores + APICIdCoreIdSize
3331	* Intel: EAX: Virtual/Physical address Size
3332	* EBX, ECX, EDX - reserved
3333	* VIA: EAX: Virtual/Physical address Size
3334	* EBX, ECX, EDX - reserved
3335	*
3336	* We only expose the virtual+pysical address size to the guest atm.
3337	* On AMD we set the core count, but not the apic id stuff as we're
3338	* currently not doing the apic id assignments in a complatible manner.
3339	*/
3340	uSubLeaf = 0;
3341	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3342	{
3343	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3344	pCurLeaf->uEbx = 0; /* reserved */
3345	pCurLeaf->uEdx = 0; /* reserved */
3346
3347	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3348	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3349	pCurLeaf->uEcx = 0;
3350	#ifdef VBOX_WITH_MULTI_CORE
3351	if ( pVM->cCpus > 1
3352	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3353	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3354	#endif
3355	uSubLeaf++;
3356	}
3357
3358	/* Cpuid 0x80000009: Reserved
3359	* We zero this since we don't know what it may have been used for.
3360	*/
3361	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3362
3363	/* Cpuid 0x8000000a: SVM Information
3364	* AMD: EAX - SVM revision.
3365	* EBX - Number of ASIDs.
3366	* ECX - Reserved.
3367	* EDX - SVM Feature identification.
3368	*/
3369	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3370	if (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
3371	{
3372	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3373	pSvmFeatureLeaf->uEax = 0x1;
3374	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3375	pSvmFeatureLeaf->uEcx = 0;
3376	pSvmFeatureLeaf->uEdx = 0; /** @todo Support SVM features */
3377	}
3378	else
3379	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3380
3381	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3382	* We clear these as we don't know what purpose they might have. */
3383	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3384	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3385
3386	/* Cpuid 0x80000019: TLB configuration
3387	* Seems to be harmless, pass them thru as is. */
3388
3389	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3390	* Strip anything we don't know what is or addresses feature we don't implement. */
3391	uSubLeaf = 0;
3392	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3393	{
3394	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3395	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3396	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3397	;
3398	pCurLeaf->uEbx = 0; /* reserved */
3399	pCurLeaf->uEcx = 0; /* reserved */
3400	pCurLeaf->uEdx = 0; /* reserved */
3401	uSubLeaf++;
3402	}
3403
3404	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3405	* Clear this as we don't currently virtualize this feature. */
3406	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3407
3408	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3409	* Clear this as we don't currently virtualize this feature. */
3410	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3411
3412	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3413	* We need to sanitize the cores per cache (EAX[25:14]).
3414	*
3415	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3416	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3417	* slightly different meaning.
3418	*/
3419	uSubLeaf = 0;
3420	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3421	{
3422	#ifdef VBOX_WITH_MULTI_CORE
3423	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3424	if (cCores > pVM->cCpus)
3425	cCores = pVM->cCpus;
3426	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3427	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3428	#else
3429	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3430	#endif
3431	uSubLeaf++;
3432	}
3433
3434	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3435	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3436	* setup, we have one compute unit with all the cores in it. Single node.
3437	*/
3438	uSubLeaf = 0;
3439	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3440	{
3441	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3442	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3443	{
3444	#ifdef VBOX_WITH_MULTI_CORE
3445	pCurLeaf->uEbx = pVM->cCpus < 0x100
3446	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3447	#else
3448	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3449	#endif
3450	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3451	}
3452	else
3453	{
3454	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3455	pCurLeaf->uEbx = 0; /* Reserved. */
3456	pCurLeaf->uEcx = 0; /* Reserved. */
3457	}
3458	pCurLeaf->uEdx = 0; /* Reserved. */
3459	uSubLeaf++;
3460	}
3461
3462	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3463	* We don't know these and what they mean, so remove them. */
3464	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3465	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3466
3467	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3468	* Just pass it thru for now. */
3469
3470	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3471	* Just pass it thru for now. */
3472
3473	/* Cpuid 0xc0000000: Centaur stuff.
3474	* Harmless, pass it thru. */
3475
3476	/* Cpuid 0xc0000001: Centaur features.
3477	* VIA: EAX - Family, model, stepping.
3478	* EDX - Centaur extended feature flags. Nothing interesting, except may
3479	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3480	* EBX, ECX - reserved.
3481	* We keep EAX but strips the rest.
3482	*/
3483	uSubLeaf = 0;
3484	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3485	{
3486	pCurLeaf->uEbx = 0;
3487	pCurLeaf->uEcx = 0;
3488	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3489	uSubLeaf++;
3490	}
3491
3492	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3493	* We only have fixed stale values, but should be harmless. */
3494
3495	/* Cpuid 0xc0000003: Reserved.
3496	* We zero this since we don't know what it may have been used for.
3497	*/
3498	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3499
3500	/* Cpuid 0xc0000004: Centaur Performance Info.
3501	* We only have fixed stale values, but should be harmless. */
3502
3503
3504	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3505	* We don't know these and what they mean, so remove them. */
3506	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3507	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3508
3509	return VINF_SUCCESS;
3510	#undef PORTABLE_DISABLE_FEATURE_BIT
3511	#undef PORTABLE_CLEAR_BITS_WHEN
3512	}
3513
3514
3515	/**
3516	* Reads a value in /CPUM/IsaExts/ node.
3517	*
3518	* @returns VBox status code (error message raised).
3519	* @param pVM The cross context VM structure. (For errors.)
3520	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3521	* @param pszValueName The value / extension name.
3522	* @param penmValue Where to return the choice.
3523	* @param enmDefault The default choice.
3524	*/
3525	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3526	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3527	{
3528	/*
3529	* Try integer encoding first.
3530	*/
3531	uint64_t uValue;
3532	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3533	if (RT_SUCCESS(rc))
3534	switch (uValue)
3535	{
3536	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3537	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3538	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3539	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3540	default:
3541	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3542	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3543	pszValueName, uValue);
3544	}
3545	/*
3546	* If missing, use default.
3547	*/
3548	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3549	*penmValue = enmDefault;
3550	else
3551	{
3552	if (rc == VERR_CFGM_NOT_INTEGER)
3553	{
3554	/*
3555	* Not an integer, try read it as a string.
3556	*/
3557	char szValue[32];
3558	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3559	if (RT_SUCCESS(rc))
3560	{
3561	RTStrToLower(szValue);
3562	size_t cchValue = strlen(szValue);
3563	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3564	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3565	*penmValue = CPUMISAEXTCFG_DISABLED;
3566	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3567	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3568	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3569	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3570	else if (EQ("portable"))
3571	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3572	else if (EQ("default") \|\| EQ("def"))
3573	*penmValue = enmDefault;
3574	else
3575	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3576	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3577	pszValueName, uValue);
3578	#undef EQ
3579	}
3580	}
3581	if (RT_FAILURE(rc))
3582	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3583	}
3584	return VINF_SUCCESS;
3585	}
3586
3587
3588	/**
3589	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3590	*
3591	* @returns VBox status code (error message raised).
3592	* @param pVM The cross context VM structure. (For errors.)
3593	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3594	* @param pszValueName The value / extension name.
3595	* @param penmValue Where to return the choice.
3596	* @param enmDefault The default choice.
3597	* @param fAllowed Allowed choice. Applied both to the result and to
3598	* the default value.
3599	*/
3600	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3601	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3602	{
3603	int rc;
3604	if (fAllowed)
3605	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3606	else
3607	{
3608	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3609	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3610	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3611	*penmValue = CPUMISAEXTCFG_DISABLED;
3612	}
3613	return rc;
3614	}
3615
3616
3617	/**
3618	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3619	*
3620	* @returns VBox status code (error message raised).
3621	* @param pVM The cross context VM structure. (For errors.)
3622	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3623	* @param pCpumCfg The /CPUM node (can be NULL).
3624	* @param pszValueName The value / extension name.
3625	* @param penmValue Where to return the choice.
3626	* @param enmDefault The default choice.
3627	*/
3628	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3629	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3630	{
3631	if (CFGMR3Exists(pCpumCfg, pszValueName))
3632	{
3633	if (!CFGMR3Exists(pIsaExts, pszValueName))
3634	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3635	else
3636	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3637	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3638	pszValueName, pszValueName);
3639
3640	bool fLegacy;
3641	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3642	if (RT_SUCCESS(rc))
3643	{
3644	*penmValue = fLegacy;
3645	return VINF_SUCCESS;
3646	}
3647	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3648	}
3649
3650	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3651	}
3652
3653
3654	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3655	{
3656	int rc;
3657
3658	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3659	* When non-zero CPUID features that could cause portability issues will be
3660	* stripped. The higher the value the more features gets stripped. Higher
3661	* values should only be used when older CPUs are involved since it may
3662	* harm performance and maybe also cause problems with specific guests. */
3663	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
3664	AssertLogRelRCReturn(rc, rc);
3665
3666	/** @cfgm{/CPUM/GuestCpuName, string}
3667	* The name of the CPU we're to emulate. The default is the host CPU.
3668	* Note! CPUs other than "host" one is currently unsupported. */
3669	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3670	AssertLogRelRCReturn(rc, rc);
3671
3672	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3673	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3674	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3675	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3676	*/
3677	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3678	AssertLogRelRCReturn(rc, rc);
3679
3680	/** @cfgm{/CPUM/InvariantTsc, boolean, complicated}
3681	* Set the invariant TSC flag in 0x80000007 if true, otherwas take default
3682	* action. By default the flag is passed thru as is from the host CPU, except
3683	* on AMD CPUs where it's suppressed to avoid trouble from linux assuming we
3684	* virtualize performance counters.
3685	*/
3686	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, false);
3687	AssertLogRelRCReturn(rc, rc);
3688
3689	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3690	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
3691	* probably going to be a temporary hack, so don't depend on this.
3692	* The 1st byte of the value is the stepping, the 2nd byte value is the model
3693	* number and the 3rd byte value is the family, and the 4th value must be zero.
3694	*/
3695	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3696	AssertLogRelRCReturn(rc, rc);
3697
3698	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3699	* The last standard leaf to keep. The actual last value that is stored in EAX
3700	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3701	* removed. (This works independently of and differently from NT4LeafLimit.)
3702	* The default is usually set to what we're able to reasonably sanitize.
3703	*/
3704	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3705	AssertLogRelRCReturn(rc, rc);
3706
3707	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3708	* The last extended leaf to keep. The actual last value that is stored in EAX
3709	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3710	* leaf are removed. The default is set to what we're able to sanitize.
3711	*/
3712	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3713	AssertLogRelRCReturn(rc, rc);
3714
3715	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3716	* The last extended leaf to keep. The actual last value that is stored in EAX
3717	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3718	* leaf are removed. The default is set to what we're able to sanitize.
3719	*/
3720	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3721	AssertLogRelRCReturn(rc, rc);
3722
3723
3724	/*
3725	* Instruction Set Architecture (ISA) Extensions.
3726	*/
3727	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3728	if (pIsaExts)
3729	{
3730	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3731	"CMPXCHG16B"
3732	"\|MONITOR"
3733	"\|MWaitExtensions"
3734	"\|SSE4.1"
3735	"\|SSE4.2"
3736	"\|XSAVE"
3737	"\|AVX"
3738	"\|AVX2"
3739	"\|AESNI"
3740	"\|PCLMUL"
3741	"\|POPCNT"
3742	"\|MOVBE"
3743	"\|RDRAND"
3744	"\|RDSEED"
3745	"\|CLFLUSHOPT"
3746	"\|ABM"
3747	"\|SSE4A"
3748	"\|MISALNSSE"
3749	"\|3DNOWPRF"
3750	"\|AXMMX"
3751	"\|SVM"
3752	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
3753	if (RT_FAILURE(rc))
3754	return rc;
3755	}
3756
3757	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
3758	* Expose CMPXCHG16B to the guest if supported by the host. For the time
3759	* being the default is to only do this for VMs with nested paging and AMD-V or
3760	* unrestricted guest mode.
3761	*/
3762	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
3763	AssertLogRelRCReturn(rc, rc);
3764
3765	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
3766	* Expose MONITOR/MWAIT instructions to the guest.
3767	*/
3768	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
3769	AssertLogRelRCReturn(rc, rc);
3770
3771	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
3772	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
3773	* break on interrupt feature (bit 1).
3774	*/
3775	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
3776	AssertLogRelRCReturn(rc, rc);
3777
3778	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
3779	* Expose SSE4.1 to the guest if available.
3780	*/
3781	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
3782	AssertLogRelRCReturn(rc, rc);
3783
3784	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
3785	* Expose SSE4.2 to the guest if available.
3786	*/
3787	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
3788	AssertLogRelRCReturn(rc, rc);
3789
3790	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
3791	&& pVM->cpum.s.HostFeatures.fXSaveRstor
3792	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
3793	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
3794	&& !HMIsLongModeAllowed(pVM)
3795	#endif
3796	;
3797	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
3798
3799	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
3800	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
3801	* default is to only expose this to VMs with nested paging and AMD-V or
3802	* unrestricted guest execution mode. Not possible to force this one without
3803	* host support at the moment.
3804	*/
3805	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
3806	fMayHaveXSave /fAllowed/);
3807	AssertLogRelRCReturn(rc, rc);
3808
3809	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
3810	* Expose the AVX instruction set extensions to the guest if available and
3811	* XSAVE is exposed too. For the time being the default is to only expose this
3812	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3813	*/
3814	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
3815	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3816	AssertLogRelRCReturn(rc, rc);
3817
3818	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
3819	* Expose the AVX2 instruction set extensions to the guest if available and
3820	* XSAVE is exposed too. For the time being the default is to only expose this
3821	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3822	*/
3823	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec && false /* temporarily */,
3824	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3825	AssertLogRelRCReturn(rc, rc);
3826
3827	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
3828	* Whether to expose the AES instructions to the guest. For the time being the
3829	* default is to only do this for VMs with nested paging and AMD-V or
3830	* unrestricted guest mode.
3831	*/
3832	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
3833	AssertLogRelRCReturn(rc, rc);
3834
3835	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
3836	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
3837	* being the default is to only do this for VMs with nested paging and AMD-V or
3838	* unrestricted guest mode.
3839	*/
3840	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
3841	AssertLogRelRCReturn(rc, rc);
3842
3843	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
3844	* Whether to expose the POPCNT instructions to the guest. For the time
3845	* being the default is to only do this for VMs with nested paging and AMD-V or
3846	* unrestricted guest mode.
3847	*/
3848	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
3849	AssertLogRelRCReturn(rc, rc);
3850
3851	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
3852	* Whether to expose the MOVBE instructions to the guest. For the time
3853	* being the default is to only do this for VMs with nested paging and AMD-V or
3854	* unrestricted guest mode.
3855	*/
3856	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
3857	AssertLogRelRCReturn(rc, rc);
3858
3859	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
3860	* Whether to expose the RDRAND instructions to the guest. For the time being
3861	* the default is to only do this for VMs with nested paging and AMD-V or
3862	* unrestricted guest mode.
3863	*/
3864	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
3865	AssertLogRelRCReturn(rc, rc);
3866
3867	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
3868	* Whether to expose the RDSEED instructions to the guest. For the time being
3869	* the default is to only do this for VMs with nested paging and AMD-V or
3870	* unrestricted guest mode.
3871	*/
3872	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
3873	AssertLogRelRCReturn(rc, rc);
3874
3875	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
3876	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
3877	* being the default is to only do this for VMs with nested paging and AMD-V or
3878	* unrestricted guest mode.
3879	*/
3880	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
3881	AssertLogRelRCReturn(rc, rc);
3882
3883
3884	/* AMD: */
3885
3886	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
3887	* Whether to expose the AMD ABM instructions to the guest. For the time
3888	* being the default is to only do this for VMs with nested paging and AMD-V or
3889	* unrestricted guest mode.
3890	*/
3891	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
3892	AssertLogRelRCReturn(rc, rc);
3893
3894	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
3895	* Whether to expose the AMD SSE4A instructions to the guest. For the time
3896	* being the default is to only do this for VMs with nested paging and AMD-V or
3897	* unrestricted guest mode.
3898	*/
3899	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
3900	AssertLogRelRCReturn(rc, rc);
3901
3902	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
3903	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
3904	* the time being the default is to only do this for VMs with nested paging and
3905	* AMD-V or unrestricted guest mode.
3906	*/
3907	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
3908	AssertLogRelRCReturn(rc, rc);
3909
3910	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
3911	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
3912	* For the time being the default is to only do this for VMs with nested paging
3913	* and AMD-V or unrestricted guest mode.
3914	*/
3915	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
3916	AssertLogRelRCReturn(rc, rc);
3917
3918	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
3919	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
3920	* the default is to only do this for VMs with nested paging and AMD-V or
3921	* unrestricted guest mode.
3922	*/
3923	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
3924	AssertLogRelRCReturn(rc, rc);
3925
3926	#ifdef VBOX_WITH_NESTED_HWVIRT
3927	/** @cfgm{/CPUM/IsaExts/SVM, isaextcfg, depends}
3928	* Whether to expose the AMD's hardware virtualization (SVM) instructions to the
3929	* guest. For the time being, the default is to only do this for VMs with nested
3930	* paging and AMD-V.
3931	*/
3932	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SVM", &pConfig->enmSvm, fNestedPagingAndFullGuestExec);
3933	AssertLogRelRCReturn(rc, rc);
3934	#endif
3935
3936	return VINF_SUCCESS;
3937	}
3938
3939
3940	/**
3941	* Initializes the emulated CPU's CPUID & MSR information.
3942	*
3943	* @returns VBox status code.
3944	* @param pVM The cross context VM structure.
3945	*/
3946	int cpumR3InitCpuIdAndMsrs(PVM pVM)
3947	{
3948	PCPUM pCpum = &pVM->cpum.s;
3949	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
3950
3951	/*
3952	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
3953	* on construction and manage everything from here on.
3954	*/
3955	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
3956	pVM->aCpus[iCpu].cpum.s.fCpuIdApicFeatureVisible = true;
3957
3958	/*
3959	* Read the configuration.
3960	*/
3961	CPUMCPUIDCONFIG Config;
3962	RT_ZERO(Config);
3963
3964	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
3965	AssertRCReturn(rc, rc);
3966
3967	/*
3968	* Get the guest CPU data from the database and/or the host.
3969	*
3970	* The CPUID and MSRs are currently living on the regular heap to avoid
3971	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
3972	* API for the hyper heap). This means special cleanup considerations.
3973	*/
3974	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
3975	if (RT_FAILURE(rc))
3976	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
3977	? VMSetError(pVM, rc, RT_SRC_POS,
3978	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
3979	: rc;
3980
3981	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
3982	* Overrides the guest MSRs.
3983	*/
3984	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
3985
3986	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
3987	* Overrides the CPUID leaf values (from the host CPU usually) used for
3988	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
3989	* values when moving a VM to a different machine. Another use is restricting
3990	* (or extending) the feature set exposed to the guest. */
3991	if (RT_SUCCESS(rc))
3992	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
3993
3994	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
3995	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
3996	"Found unsupported configuration node '/CPUM/CPUID/'. "
3997	"Please use IMachine::setCPUIDLeaf() instead.");
3998
3999	/*
4000	* Pre-explode the CPUID info.
4001	*/
4002	if (RT_SUCCESS(rc))
4003	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
4004
4005	/*
4006	* Sanitize the cpuid information passed on to the guest.
4007	*/
4008	if (RT_SUCCESS(rc))
4009	{
4010	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4011	if (RT_SUCCESS(rc))
4012	{
4013	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4014	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4015	}
4016	}
4017
4018	/*
4019	* MSR fudging.
4020	*/
4021	if (RT_SUCCESS(rc))
4022	{
4023	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4024	* Fudges some common MSRs if not present in the selected CPU database entry.
4025	* This is for trying to keep VMs running when moved between different hosts
4026	* and different CPU vendors. */
4027	bool fEnable;
4028	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4029	if (RT_SUCCESS(rc) && fEnable)
4030	{
4031	rc = cpumR3MsrApplyFudge(pVM);
4032	AssertLogRelRC(rc);
4033	}
4034	}
4035	if (RT_SUCCESS(rc))
4036	{
4037	/*
4038	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4039	* guest CPU features again.
4040	*/
4041	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4042	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4043	pCpum->GuestInfo.cCpuIdLeaves);
4044	RTMemFree(pvFree);
4045
4046	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4047	int rc2 = MMHyperDupMem(pVM, pvFree,
4048	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4049	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4050	RTMemFree(pvFree);
4051	AssertLogRelRCReturn(rc1, rc1);
4052	AssertLogRelRCReturn(rc2, rc2);
4053
4054	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4055	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4056
4057
4058	/*
4059	* Some more configuration that we're applying at the end of everything
4060	* via the CPUMSetGuestCpuIdFeature API.
4061	*/
4062
4063	/* Check if PAE was explicitely enabled by the user. */
4064	bool fEnable;
4065	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4066	AssertRCReturn(rc, rc);
4067	if (fEnable)
4068	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4069
4070	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4071	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4072	AssertRCReturn(rc, rc);
4073	if (fEnable)
4074	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4075
4076	return VINF_SUCCESS;
4077	}
4078
4079	/*
4080	* Failed before switching to hyper heap.
4081	*/
4082	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4083	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4084	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4085	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4086	return rc;
4087	}
4088
4089
4090	/**
4091	* Sets a CPUID feature bit during VM initialization.
4092	*
4093	* Since the CPUID feature bits are generally related to CPU features, other
4094	* CPUM configuration like MSRs can also be modified by calls to this API.
4095	*
4096	* @param pVM The cross context VM structure.
4097	* @param enmFeature The feature to set.
4098	*/
4099	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4100	{
4101	PCPUMCPUIDLEAF pLeaf;
4102	PCPUMMSRRANGE pMsrRange;
4103
4104	switch (enmFeature)
4105	{
4106	/*
4107	* Set the APIC bit in both feature masks.
4108	*/
4109	case CPUMCPUIDFEATURE_APIC:
4110	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4111	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4112	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4113
4114	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4115	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4116	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4117
4118	pVM->cpum.s.GuestFeatures.fApic = 1;
4119
4120	/* Make sure we've got the APICBASE MSR present. */
4121	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4122	if (!pMsrRange)
4123	{
4124	static CPUMMSRRANGE const s_ApicBase =
4125	{
4126	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4127	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4128	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4129	/.szName = / "IA32_APIC_BASE"
4130	};
4131	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4132	AssertLogRelRC(rc);
4133	}
4134
4135	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4136	break;
4137
4138	/*
4139	* Set the x2APIC bit in the standard feature mask.
4140	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4141	*/
4142	case CPUMCPUIDFEATURE_X2APIC:
4143	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4144	if (pLeaf)
4145	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4146	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4147
4148	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4149	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4150	if (pMsrRange)
4151	{
4152	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4153	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4154	}
4155
4156	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4157	break;
4158
4159	/*
4160	* Set the sysenter/sysexit bit in the standard feature mask.
4161	* Assumes the caller knows what it's doing! (host must support these)
4162	*/
4163	case CPUMCPUIDFEATURE_SEP:
4164	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4165	{
4166	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4167	return;
4168	}
4169
4170	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4171	if (pLeaf)
4172	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4173	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4174	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4175	break;
4176
4177	/*
4178	* Set the syscall/sysret bit in the extended feature mask.
4179	* Assumes the caller knows what it's doing! (host must support these)
4180	*/
4181	case CPUMCPUIDFEATURE_SYSCALL:
4182	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4183	if ( !pLeaf
4184	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4185	{
4186	#if HC_ARCH_BITS == 32
4187	/* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit
4188	mode by Intel, even when the cpu is capable of doing so in
4189	64-bit mode. Long mode requires syscall support. */
4190	if (!pVM->cpum.s.HostFeatures.fLongMode)
4191	#endif
4192	{
4193	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4194	return;
4195	}
4196	}
4197
4198	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4199	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4200	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4201	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4202	break;
4203
4204	/*
4205	* Set the PAE bit in both feature masks.
4206	* Assumes the caller knows what it's doing! (host must support these)
4207	*/
4208	case CPUMCPUIDFEATURE_PAE:
4209	if (!pVM->cpum.s.HostFeatures.fPae)
4210	{
4211	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4212	return;
4213	}
4214
4215	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4216	if (pLeaf)
4217	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4218
4219	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4220	if ( pLeaf
4221	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4222	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4223
4224	pVM->cpum.s.GuestFeatures.fPae = 1;
4225	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4226	break;
4227
4228	/*
4229	* Set the LONG MODE bit in the extended feature mask.
4230	* Assumes the caller knows what it's doing! (host must support these)
4231	*/
4232	case CPUMCPUIDFEATURE_LONG_MODE:
4233	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4234	if ( !pLeaf
4235	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4236	{
4237	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4238	return;
4239	}
4240
4241	/* Valid for both Intel and AMD. */
4242	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4243	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4244	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4245	break;
4246
4247	/*
4248	* Set the NX/XD bit in the extended feature mask.
4249	* Assumes the caller knows what it's doing! (host must support these)
4250	*/
4251	case CPUMCPUIDFEATURE_NX:
4252	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4253	if ( !pLeaf
4254	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4255	{
4256	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4257	return;
4258	}
4259
4260	/* Valid for both Intel and AMD. */
4261	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4262	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4263	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4264	break;
4265
4266
4267	/*
4268	* Set the LAHF/SAHF support in 64-bit mode.
4269	* Assumes the caller knows what it's doing! (host must support this)
4270	*/
4271	case CPUMCPUIDFEATURE_LAHF:
4272	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4273	if ( !pLeaf
4274	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4275	{
4276	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4277	return;
4278	}
4279
4280	/* Valid for both Intel and AMD. */
4281	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4282	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4283	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4284	break;
4285
4286	/*
4287	* Set the page attribute table bit. This is alternative page level
4288	* cache control that doesn't much matter when everything is
4289	* virtualized, though it may when passing thru device memory.
4290	*/
4291	case CPUMCPUIDFEATURE_PAT:
4292	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4293	if (pLeaf)
4294	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4295
4296	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4297	if ( pLeaf
4298	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4299	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4300
4301	pVM->cpum.s.GuestFeatures.fPat = 1;
4302	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4303	break;
4304
4305	/*
4306	* Set the RDTSCP support bit.
4307	* Assumes the caller knows what it's doing! (host must support this)
4308	*/
4309	case CPUMCPUIDFEATURE_RDTSCP:
4310	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4311	if ( !pLeaf
4312	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4313	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4314	{
4315	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4316	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4317	return;
4318	}
4319
4320	/* Valid for both Intel and AMD. */
4321	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4322	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4323	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4324	break;
4325
4326	/*
4327	* Set the Hypervisor Present bit in the standard feature mask.
4328	*/
4329	case CPUMCPUIDFEATURE_HVP:
4330	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4331	if (pLeaf)
4332	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4333	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4334	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4335	break;
4336
4337	/*
4338	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4339	* This currently includes the Present bit and MWAITBREAK bit as well.
4340	*/
4341	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4342	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4343	if ( !pLeaf
4344	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4345	{
4346	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4347	return;
4348	}
4349
4350	/* Valid for both Intel and AMD. */
4351	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4352	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4353	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4354	break;
4355
4356	default:
4357	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4358	break;
4359	}
4360
4361	/** @todo can probably kill this as this API is now init time only... */
4362	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4363	{
4364	PVMCPU pVCpu = &pVM->aCpus[i];
4365	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4366	}
4367	}
4368
4369
4370	/**
4371	* Queries a CPUID feature bit.
4372	*
4373	* @returns boolean for feature presence
4374	* @param pVM The cross context VM structure.
4375	* @param enmFeature The feature to query.
4376	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4377	*/
4378	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4379	{
4380	switch (enmFeature)
4381	{
4382	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4383	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4384	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4385	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4386	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4387	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4388	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4389	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4390	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4391	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4392	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4393	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4394
4395	case CPUMCPUIDFEATURE_INVALID:
4396	case CPUMCPUIDFEATURE_32BIT_HACK:
4397	break;
4398	}
4399	AssertFailed();
4400	return false;
4401	}
4402
4403
4404	/**
4405	* Clears a CPUID feature bit.
4406	*
4407	* @param pVM The cross context VM structure.
4408	* @param enmFeature The feature to clear.
4409	*
4410	* @deprecated Probably better to default the feature to disabled and only allow
4411	* setting (enabling) it during construction.
4412	*/
4413	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4414	{
4415	PCPUMCPUIDLEAF pLeaf;
4416	switch (enmFeature)
4417	{
4418	case CPUMCPUIDFEATURE_APIC:
4419	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
4420	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4421	if (pLeaf)
4422	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
4423
4424	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4425	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4426	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4427
4428	pVM->cpum.s.GuestFeatures.fApic = 0;
4429	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4430	break;
4431
4432	case CPUMCPUIDFEATURE_X2APIC:
4433	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4434	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4435	if (pLeaf)
4436	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
4437	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
4438	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
4439	break;
4440
4441	case CPUMCPUIDFEATURE_PAE:
4442	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4443	if (pLeaf)
4444	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
4445
4446	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4447	if ( pLeaf
4448	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4449	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
4450
4451	pVM->cpum.s.GuestFeatures.fPae = 0;
4452	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
4453	break;
4454
4455	case CPUMCPUIDFEATURE_PAT:
4456	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4457	if (pLeaf)
4458	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
4459
4460	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4461	if ( pLeaf
4462	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4463	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
4464
4465	pVM->cpum.s.GuestFeatures.fPat = 0;
4466	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
4467	break;
4468
4469	case CPUMCPUIDFEATURE_LONG_MODE:
4470	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4471	if (pLeaf)
4472	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4473	pVM->cpum.s.GuestFeatures.fLongMode = 0;
4474	break;
4475
4476	case CPUMCPUIDFEATURE_LAHF:
4477	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4478	if (pLeaf)
4479	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4480	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
4481	break;
4482
4483	case CPUMCPUIDFEATURE_RDTSCP:
4484	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4485	if (pLeaf)
4486	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4487	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
4488	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
4489	break;
4490
4491	case CPUMCPUIDFEATURE_HVP:
4492	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4493	if (pLeaf)
4494	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
4495	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
4496	break;
4497
4498	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4499	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4500	if (pLeaf)
4501	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
4502	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
4503	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
4504	break;
4505
4506	default:
4507	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4508	break;
4509	}
4510
4511	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4512	{
4513	PVMCPU pVCpu = &pVM->aCpus[i];
4514	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4515	}
4516	}
4517
4518
4519
4520	/*
4521	*
4522	*
4523	* Saved state related code.
4524	* Saved state related code.
4525	* Saved state related code.
4526	*
4527	*
4528	*/
4529
4530	/**
4531	* Called both in pass 0 and the final pass.
4532	*
4533	* @param pVM The cross context VM structure.
4534	* @param pSSM The saved state handle.
4535	*/
4536	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4537	{
4538	/*
4539	* Save all the CPU ID leaves.
4540	*/
4541	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4542	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4543	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4544	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4545
4546	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4547
4548	/*
4549	* Save a good portion of the raw CPU IDs as well as they may come in
4550	* handy when validating features for raw mode.
4551	*/
4552	CPUMCPUID aRawStd[16];
4553	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4554	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4555	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4556	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4557
4558	CPUMCPUID aRawExt[32];
4559	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4560	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4561	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4562	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4563	}
4564
4565
4566	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4567	{
4568	uint32_t cCpuIds;
4569	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4570	if (RT_SUCCESS(rc))
4571	{
4572	if (cCpuIds < 64)
4573	{
4574	for (uint32_t i = 0; i < cCpuIds; i++)
4575	{
4576	CPUMCPUID CpuId;
4577	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4578	if (RT_FAILURE(rc))
4579	break;
4580
4581	CPUMCPUIDLEAF NewLeaf;
4582	NewLeaf.uLeaf = uBase + i;
4583	NewLeaf.uSubLeaf = 0;
4584	NewLeaf.fSubLeafMask = 0;
4585	NewLeaf.uEax = CpuId.uEax;
4586	NewLeaf.uEbx = CpuId.uEbx;
4587	NewLeaf.uEcx = CpuId.uEcx;
4588	NewLeaf.uEdx = CpuId.uEdx;
4589	NewLeaf.fFlags = 0;
4590	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4591	}
4592	}
4593	else
4594	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4595	}
4596	if (RT_FAILURE(rc))
4597	{
4598	RTMemFree(*ppaLeaves);
4599	*ppaLeaves = NULL;
4600	*pcLeaves = 0;
4601	}
4602	return rc;
4603	}
4604
4605
4606	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4607	{
4608	*ppaLeaves = NULL;
4609	*pcLeaves = 0;
4610
4611	int rc;
4612	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4613	{
4614	/*
4615	* The new format. Starts by declaring the leave size and count.
4616	*/
4617	uint32_t cbLeaf;
4618	SSMR3GetU32(pSSM, &cbLeaf);
4619	uint32_t cLeaves;
4620	rc = SSMR3GetU32(pSSM, &cLeaves);
4621	if (RT_SUCCESS(rc))
4622	{
4623	if (cbLeaf == sizeof(**ppaLeaves))
4624	{
4625	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4626	{
4627	/*
4628	* Load the leaves one by one.
4629	*
4630	* The uPrev stuff is a kludge for working around a week worth of bad saved
4631	* states during the CPUID revamp in March 2015. We saved too many leaves
4632	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4633	* garbage entires at the end of the array when restoring. We also had
4634	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
4635	* this kludge doesn't deal correctly with that, but who cares...
4636	*/
4637	uint32_t uPrev = 0;
4638	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4639	{
4640	CPUMCPUIDLEAF Leaf;
4641	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
4642	if (RT_SUCCESS(rc))
4643	{
4644	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
4645	\|\| Leaf.uLeaf >= uPrev)
4646	{
4647	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4648	uPrev = Leaf.uLeaf;
4649	}
4650	else
4651	uPrev = UINT32_MAX;
4652	}
4653	}
4654	}
4655	else
4656	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
4657	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
4658	}
4659	else
4660	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
4661	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
4662	}
4663	}
4664	else
4665	{
4666	/*
4667	* The old format with its three inflexible arrays.
4668	*/
4669	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
4670	if (RT_SUCCESS(rc))
4671	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
4672	if (RT_SUCCESS(rc))
4673	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
4674	if (RT_SUCCESS(rc))
4675	{
4676	/*
4677	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
4678	*/
4679	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
4680	if ( pLeaf
4681	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
4682	{
4683	CPUMCPUIDLEAF Leaf;
4684	Leaf.uLeaf = 4;
4685	Leaf.fSubLeafMask = UINT32_MAX;
4686	Leaf.uSubLeaf = 0;
4687	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
4688	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
4689	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
4690	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
4691	\| UINT32_C(63); /* system coherency line size - 1 */
4692	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
4693	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
4694	\| (UINT32_C(1) << 5) /* cache level */
4695	\| UINT32_C(1); /* cache type (data) */
4696	Leaf.fFlags = 0;
4697	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4698	if (RT_SUCCESS(rc))
4699	{
4700	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
4701	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4702	}
4703	if (RT_SUCCESS(rc))
4704	{
4705	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
4706	Leaf.uEcx = 4095; /* sets - 1 */
4707	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
4708	Leaf.uEbx \|= UINT32_C(23) << 22;
4709	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
4710	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
4711	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
4712	Leaf.uEax \|= UINT32_C(2) << 5;
4713	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4714	}
4715	}
4716	}
4717	}
4718	return rc;
4719	}
4720
4721
4722	/**
4723	* Loads the CPU ID leaves saved by pass 0, inner worker.
4724	*
4725	* @returns VBox status code.
4726	* @param pVM The cross context VM structure.
4727	* @param pSSM The saved state handle.
4728	* @param uVersion The format version.
4729	* @param paLeaves Guest CPUID leaves loaded from the state.
4730	* @param cLeaves The number of leaves in @a paLeaves.
4731	*/
4732	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
4733	{
4734	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4735
4736	/*
4737	* Continue loading the state into stack buffers.
4738	*/
4739	CPUMCPUID GuestDefCpuId;
4740	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
4741	AssertRCReturn(rc, rc);
4742
4743	CPUMCPUID aRawStd[16];
4744	uint32_t cRawStd;
4745	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
4746	if (cRawStd > RT_ELEMENTS(aRawStd))
4747	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4748	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
4749	AssertRCReturn(rc, rc);
4750	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
4751	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4752
4753	CPUMCPUID aRawExt[32];
4754	uint32_t cRawExt;
4755	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
4756	if (cRawExt > RT_ELEMENTS(aRawExt))
4757	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4758	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
4759	AssertRCReturn(rc, rc);
4760	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
4761	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4762
4763	/*
4764	* Get the raw CPU IDs for the current host.
4765	*/
4766	CPUMCPUID aHostRawStd[16];
4767	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
4768	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
4769
4770	CPUMCPUID aHostRawExt[32];
4771	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
4772	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
4773	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4774
4775	/*
4776	* Get the host and guest overrides so we don't reject the state because
4777	* some feature was enabled thru these interfaces.
4778	* Note! We currently only need the feature leaves, so skip rest.
4779	*/
4780	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4781	CPUMCPUID aHostOverrideStd[2];
4782	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4783	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4784
4785	CPUMCPUID aHostOverrideExt[2];
4786	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4787	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4788
4789	/*
4790	* This can be skipped.
4791	*/
4792	bool fStrictCpuIdChecks;
4793	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
4794
4795	/*
4796	* Define a bunch of macros for simplifying the santizing/checking code below.
4797	*/
4798	/* Generic expression + failure message. */
4799	#define CPUID_CHECK_RET(expr, fmt) \
4800	do { \
4801	if (!(expr)) \
4802	{ \
4803	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
4804	if (fStrictCpuIdChecks) \
4805	{ \
4806	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4807	RTStrFree(pszMsg); \
4808	return rcCpuid; \
4809	} \
4810	LogRel(("CPUM: %s\n", pszMsg)); \
4811	RTStrFree(pszMsg); \
4812	} \
4813	} while (0)
4814	#define CPUID_CHECK_WRN(expr, fmt) \
4815	do { \
4816	if (!(expr)) \
4817	LogRel(fmt); \
4818	} while (0)
4819
4820	/* For comparing two values and bitch if they differs. */
4821	#define CPUID_CHECK2_RET(what, host, saved) \
4822	do { \
4823	if ((host) != (saved)) \
4824	{ \
4825	if (fStrictCpuIdChecks) \
4826	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4827	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
4828	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4829	} \
4830	} while (0)
4831	#define CPUID_CHECK2_WRN(what, host, saved) \
4832	do { \
4833	if ((host) != (saved)) \
4834	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4835	} while (0)
4836
4837	/* For checking raw cpu features (raw mode). */
4838	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
4839	do { \
4840	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4841	{ \
4842	if (fStrictCpuIdChecks) \
4843	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4844	N_(#bit " mismatch: host=%d saved=%d"), \
4845	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
4846	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4847	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4848	} \
4849	} while (0)
4850	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
4851	do { \
4852	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4853	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4854	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4855	} while (0)
4856	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
4857
4858	/* For checking guest features. */
4859	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
4860	do { \
4861	if ( (aGuestCpuId##set [1].reg & bit) \
4862	&& !(aHostRaw##set [1].reg & bit) \
4863	&& !(aHostOverride##set [1].reg & bit) \
4864	) \
4865	{ \
4866	if (fStrictCpuIdChecks) \
4867	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4868	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4869	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4870	} \
4871	} while (0)
4872	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
4873	do { \
4874	if ( (aGuestCpuId##set [1].reg & bit) \
4875	&& !(aHostRaw##set [1].reg & bit) \
4876	&& !(aHostOverride##set [1].reg & bit) \
4877	) \
4878	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4879	} while (0)
4880	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
4881	do { \
4882	if ( (aGuestCpuId##set [1].reg & bit) \
4883	&& !(aHostRaw##set [1].reg & bit) \
4884	&& !(aHostOverride##set [1].reg & bit) \
4885	) \
4886	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4887	} while (0)
4888	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
4889
4890	/* For checking guest features if AMD guest CPU. */
4891	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
4892	do { \
4893	if ( (aGuestCpuId##set [1].reg & bit) \
4894	&& fGuestAmd \
4895	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4896	&& !(aHostOverride##set [1].reg & bit) \
4897	) \
4898	{ \
4899	if (fStrictCpuIdChecks) \
4900	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4901	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4902	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4903	} \
4904	} while (0)
4905	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
4906	do { \
4907	if ( (aGuestCpuId##set [1].reg & bit) \
4908	&& fGuestAmd \
4909	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4910	&& !(aHostOverride##set [1].reg & bit) \
4911	) \
4912	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4913	} while (0)
4914	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
4915	do { \
4916	if ( (aGuestCpuId##set [1].reg & bit) \
4917	&& fGuestAmd \
4918	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4919	&& !(aHostOverride##set [1].reg & bit) \
4920	) \
4921	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4922	} while (0)
4923	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
4924
4925	/* For checking AMD features which have a corresponding bit in the standard
4926	range. (Intel defines very few bits in the extended feature sets.) */
4927	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
4928	do { \
4929	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4930	&& !(fHostAmd \
4931	? aHostRawExt[1].reg & (ExtBit) \
4932	: aHostRawStd[1].reg & (StdBit)) \
4933	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4934	) \
4935	{ \
4936	if (fStrictCpuIdChecks) \
4937	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4938	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
4939	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4940	} \
4941	} while (0)
4942	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
4943	do { \
4944	if ( (aGuestCpuId[1].reg & (ExtBit)) \
4945	&& !(fHostAmd \
4946	? aHostRawExt[1].reg & (ExtBit) \
4947	: aHostRawStd[1].reg & (StdBit)) \
4948	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4949	) \
4950	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4951	} while (0)
4952	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
4953	do { \
4954	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4955	&& !(fHostAmd \
4956	? aHostRawExt[1].reg & (ExtBit) \
4957	: aHostRawStd[1].reg & (StdBit)) \
4958	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4959	) \
4960	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4961	} while (0)
4962	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
4963
4964	/*
4965	* For raw-mode we'll require that the CPUs are very similar since we don't
4966	* intercept CPUID instructions for user mode applications.
4967	*/
4968	if (!HMIsEnabled(pVM))
4969	{
4970	/* CPUID(0) */
4971	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
4972	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
4973	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
4974	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
4975	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
4976	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
4977	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
4978	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
4979	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
4980
4981	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
4982
4983	/* CPUID(1).eax */
4984	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
4985	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
4986	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
4987
4988	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
4989	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
4990	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
4991
4992	/* CPUID(1).ecx */
4993	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
4994	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
4995	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
4996	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4997	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
4998	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
4999	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
5000	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
5001	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
5002	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
5003	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
5004	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
5005	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
5006	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
5007	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
5008	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
5009	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5010	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5011	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
5012	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
5013	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
5014	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5015	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
5016	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
5017	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5018	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
5019	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
5020	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5021	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
5022	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5023	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5024	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
5025
5026	/* CPUID(1).edx */
5027	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5028	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5029	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
5030	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5031	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
5032	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
5033	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5034	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5035	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
5036	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5037	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5038	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5039	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5040	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5041	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5042	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
5043	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5044	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5045	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5046	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
5047	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5048	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
5049	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
5050	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
5051	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
5052	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
5053	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
5054	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
5055	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
5056	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
5057	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
5058	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
5059
5060	/* CPUID(2) - config, mostly about caches. ignore. */
5061	/* CPUID(3) - processor serial number. ignore. */
5062	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
5063	/* CPUID(5) - mwait/monitor config. ignore. */
5064	/* CPUID(6) - power management. ignore. */
5065	/* CPUID(7) - ???. ignore. */
5066	/* CPUID(8) - ???. ignore. */
5067	/* CPUID(9) - DCA. ignore for now. */
5068	/* CPUID(a) - PeMo info. ignore for now. */
5069	/* CPUID(b) - topology info - takes ECX as input. ignore. */
5070
5071	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
5072	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
5073	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
5074	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
5075	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
5076	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
5077	{
5078	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
5079	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
5080	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
5081	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
5082	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
5083	}
5084
5085	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
5086	Note! Intel have/is marking many of the fields here as reserved. We
5087	will verify them as if it's an AMD CPU. */
5088	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
5089	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
5090	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
5091	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
5092	{
5093	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
5094	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
5095	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
5096	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5097	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
5098	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
5099	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
5100
5101	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
5102	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
5103	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
5104	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
5105	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
5106	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5107
5108	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
5109	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
5110	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
5111	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
5112
5113	/* CPUID(0x80000001).ecx */
5114	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
5115	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
5116	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
5117	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
5118	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
5119	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
5120	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
5121	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
5122	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
5123	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
5124	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
5125	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
5126	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
5127	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
5128	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5129	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5130	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5131	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5132	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5133	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5134	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5135	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5136	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5137	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5138	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5139	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5140	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5141	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5142	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5143	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5144	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5145	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5146
5147	/* CPUID(0x80000001).edx */
5148	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
5149	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
5150	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
5151	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
5152	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
5153	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
5154	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
5155	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
5156	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
5157	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
5158	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5159	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
5160	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
5161	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
5162	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
5163	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
5164	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
5165	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
5166	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5167	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5168	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5169	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
5170	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5171	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
5172	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
5173	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5174	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5175	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5176	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
5177	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5178	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5179	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5180
5181	/** @todo verify the rest as well. */
5182	}
5183	}
5184
5185
5186
5187	/*
5188	* Verify that we can support the features already exposed to the guest on
5189	* this host.
5190	*
5191	* Most of the features we're emulating requires intercepting instruction
5192	* and doing it the slow way, so there is no need to warn when they aren't
5193	* present in the host CPU. Thus we use IGN instead of EMU on these.
5194	*
5195	* Trailing comments:
5196	* "EMU" - Possible to emulate, could be lots of work and very slow.
5197	* "EMU?" - Can this be emulated?
5198	*/
5199	CPUMCPUID aGuestCpuIdStd[2];
5200	RT_ZERO(aGuestCpuIdStd);
5201	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5202
5203	/* CPUID(1).ecx */
5204	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5205	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5206	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5207	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5208	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5209	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5210	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5211	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5212	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5213	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5214	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5215	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5216	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5217	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5218	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5219	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5220	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5221	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5222	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5223	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5224	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5225	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5226	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5227	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5228	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5229	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5230	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5231	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5232	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5233	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5234	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5235	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5236
5237	/* CPUID(1).edx */
5238	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5239	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5240	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5241	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5242	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5243	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5244	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5245	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5246	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5247	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5248	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5249	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5250	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5251	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5252	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5253	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5254	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5255	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5256	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5257	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5258	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5259	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5260	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5261	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5262	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5263	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5264	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5265	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5266	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5267	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5268	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5269	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5270
5271	/* CPUID(0x80000000). */
5272	CPUMCPUID aGuestCpuIdExt[2];
5273	RT_ZERO(aGuestCpuIdExt);
5274	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5275	{
5276	/** @todo deal with no 0x80000001 on the host. */
5277	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5278	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5279
5280	/* CPUID(0x80000001).ecx */
5281	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5282	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5283	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5284	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5285	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5286	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5287	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5288	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5289	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5290	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5291	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5292	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5293	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5294	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5295	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5296	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5297	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5298	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5299	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5300	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5301	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5302	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5303	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5304	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5305	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5306	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5307	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5308	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5309	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5310	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5311	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5312	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5313
5314	/* CPUID(0x80000001).edx */
5315	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5316	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5317	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5318	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5319	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5320	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5321	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5322	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5323	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5324	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5325	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5326	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5327	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5328	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5329	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5330	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5331	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5332	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5333	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5334	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5335	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5336	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5337	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5338	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5339	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5340	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5341	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5342	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5343	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5344	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5345	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5346	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5347	}
5348
5349	/** @todo check leaf 7 */
5350
5351	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5352	* ECX=0: EAX - Valid bits in XCR0[31:0].
5353	* EBX - Maximum state size as per current XCR0 value.
5354	* ECX - Maximum state size for all supported features.
5355	* EDX - Valid bits in XCR0[63:32].
5356	* ECX=1: EAX - Various X-features.
5357	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5358	* ECX - Valid bits in IA32_XSS[31:0].
5359	* EDX - Valid bits in IA32_XSS[63:32].
5360	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5361	* if the bit invalid all four registers are set to zero.
5362	* EAX - The state size for this feature.
5363	* EBX - The state byte offset of this feature.
5364	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5365	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5366	*/
5367	uint64_t fGuestXcr0Mask = 0;
5368	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5369	if ( pCurLeaf
5370	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5371	&& ( pCurLeaf->uEax
5372	\|\| pCurLeaf->uEbx
5373	\|\| pCurLeaf->uEcx
5374	\|\| pCurLeaf->uEdx) )
5375	{
5376	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5377	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5378	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5379	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5380	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5381	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5382	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5383	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5384
5385	/* We don't support any additional features yet. */
5386	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5387	if (pCurLeaf && pCurLeaf->uEax)
5388	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5389	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5390	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5391	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5392	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5393	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5394
5395
5396	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5397	{
5398	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5399	if (pCurLeaf)
5400	{
5401	/* If advertised, the state component offset and size must match the one used by host. */
5402	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5403	{
5404	CPUMCPUID RawHost;
5405	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5406	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5407	if ( RawHost.uEbx != pCurLeaf->uEbx
5408	\|\| RawHost.uEax != pCurLeaf->uEax)
5409	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5410	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5411	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5412	}
5413	}
5414	}
5415	}
5416	/* Clear leaf 0xd just in case we're loading an old state... */
5417	else if (pCurLeaf)
5418	{
5419	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5420	{
5421	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5422	if (pCurLeaf)
5423	{
5424	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5425	\|\| ( pCurLeaf->uEax == 0
5426	&& pCurLeaf->uEbx == 0
5427	&& pCurLeaf->uEcx == 0
5428	&& pCurLeaf->uEdx == 0),
5429	("uVersion=%#x; %#x %#x %#x %#x\n",
5430	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5431	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5432	}
5433	}
5434	}
5435
5436	/* Update the fXStateGuestMask value for the VM. */
5437	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5438	{
5439	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5440	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5441	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5442	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5443	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5444	}
5445
5446	#undef CPUID_CHECK_RET
5447	#undef CPUID_CHECK_WRN
5448	#undef CPUID_CHECK2_RET
5449	#undef CPUID_CHECK2_WRN
5450	#undef CPUID_RAW_FEATURE_RET
5451	#undef CPUID_RAW_FEATURE_WRN
5452	#undef CPUID_RAW_FEATURE_IGN
5453	#undef CPUID_GST_FEATURE_RET
5454	#undef CPUID_GST_FEATURE_WRN
5455	#undef CPUID_GST_FEATURE_EMU
5456	#undef CPUID_GST_FEATURE_IGN
5457	#undef CPUID_GST_FEATURE2_RET
5458	#undef CPUID_GST_FEATURE2_WRN
5459	#undef CPUID_GST_FEATURE2_EMU
5460	#undef CPUID_GST_FEATURE2_IGN
5461	#undef CPUID_GST_AMD_FEATURE_RET
5462	#undef CPUID_GST_AMD_FEATURE_WRN
5463	#undef CPUID_GST_AMD_FEATURE_EMU
5464	#undef CPUID_GST_AMD_FEATURE_IGN
5465
5466	/*
5467	* We're good, commit the CPU ID leaves.
5468	*/
5469	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5470	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5471	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5472	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
5473	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5474	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
5475	AssertLogRelRCReturn(rc, rc);
5476
5477	return VINF_SUCCESS;
5478	}
5479
5480
5481	/**
5482	* Loads the CPU ID leaves saved by pass 0.
5483	*
5484	* @returns VBox status code.
5485	* @param pVM The cross context VM structure.
5486	* @param pSSM The saved state handle.
5487	* @param uVersion The format version.
5488	*/
5489	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5490	{
5491	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5492
5493	/*
5494	* Load the CPUID leaves array first and call worker to do the rest, just so
5495	* we can free the memory when we need to without ending up in column 1000.
5496	*/
5497	PCPUMCPUIDLEAF paLeaves;
5498	uint32_t cLeaves;
5499	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5500	AssertRC(rc);
5501	if (RT_SUCCESS(rc))
5502	{
5503	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
5504	RTMemFree(paLeaves);
5505	}
5506	return rc;
5507	}
5508
5509
5510
5511	/**
5512	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5513	*
5514	* @returns VBox status code.
5515	* @param pVM The cross context VM structure.
5516	* @param pSSM The saved state handle.
5517	* @param uVersion The format version.
5518	*/
5519	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5520	{
5521	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5522
5523	/*
5524	* Restore the CPUID leaves.
5525	*
5526	* Note that we support restoring less than the current amount of standard
5527	* leaves because we've been allowed more is newer version of VBox.
5528	*/
5529	uint32_t cElements;
5530	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5531	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5532	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5533	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5534
5535	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5536	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5537	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5538	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5539
5540	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5541	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5542	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5543	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5544
5545	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5546
5547	/*
5548	* Check that the basic cpuid id information is unchanged.
5549	*/
5550	/** @todo we should check the 64 bits capabilities too! */
5551	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5552	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5553	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5554	uint32_t au32CpuIdSaved[8];
5555	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5556	if (RT_SUCCESS(rc))
5557	{
5558	/* Ignore CPU stepping. */
5559	au32CpuId[4] &= 0xfffffff0;
5560	au32CpuIdSaved[4] &= 0xfffffff0;
5561
5562	/* Ignore APIC ID (AMD specs). */
5563	au32CpuId[5] &= ~0xff000000;
5564	au32CpuIdSaved[5] &= ~0xff000000;
5565
5566	/* Ignore the number of Logical CPUs (AMD specs). */
5567	au32CpuId[5] &= ~0x00ff0000;
5568	au32CpuIdSaved[5] &= ~0x00ff0000;
5569
5570	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5571	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5572	\| X86_CPUID_FEATURE_ECX_VMX
5573	\| X86_CPUID_FEATURE_ECX_SMX
5574	\| X86_CPUID_FEATURE_ECX_EST
5575	\| X86_CPUID_FEATURE_ECX_TM2
5576	\| X86_CPUID_FEATURE_ECX_CNTXID
5577	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5578	\| X86_CPUID_FEATURE_ECX_PDCM
5579	\| X86_CPUID_FEATURE_ECX_DCA
5580	\| X86_CPUID_FEATURE_ECX_X2APIC
5581	);
5582	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5583	\| X86_CPUID_FEATURE_ECX_VMX
5584	\| X86_CPUID_FEATURE_ECX_SMX
5585	\| X86_CPUID_FEATURE_ECX_EST
5586	\| X86_CPUID_FEATURE_ECX_TM2
5587	\| X86_CPUID_FEATURE_ECX_CNTXID
5588	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5589	\| X86_CPUID_FEATURE_ECX_PDCM
5590	\| X86_CPUID_FEATURE_ECX_DCA
5591	\| X86_CPUID_FEATURE_ECX_X2APIC
5592	);
5593
5594	/* Make sure we don't forget to update the masks when enabling
5595	* features in the future.
5596	*/
5597	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5598	( X86_CPUID_FEATURE_ECX_DTES64
5599	\| X86_CPUID_FEATURE_ECX_VMX
5600	\| X86_CPUID_FEATURE_ECX_SMX
5601	\| X86_CPUID_FEATURE_ECX_EST
5602	\| X86_CPUID_FEATURE_ECX_TM2
5603	\| X86_CPUID_FEATURE_ECX_CNTXID
5604	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5605	\| X86_CPUID_FEATURE_ECX_PDCM
5606	\| X86_CPUID_FEATURE_ECX_DCA
5607	\| X86_CPUID_FEATURE_ECX_X2APIC
5608	)));
5609	/* do the compare */
5610	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5611	{
5612	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5613	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5614	"Saved=%.*Rhxs\n"
5615	"Real =%.*Rhxs\n",
5616	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5617	sizeof(au32CpuId), au32CpuId));
5618	else
5619	{
5620	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5621	"Saved=%.*Rhxs\n"
5622	"Real =%.*Rhxs\n",
5623	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5624	sizeof(au32CpuId), au32CpuId));
5625	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5626	}
5627	}
5628	}
5629
5630	return rc;
5631	}
5632
5633
5634
5635	/*
5636	*
5637	*
5638	* CPUID Info Handler.
5639	* CPUID Info Handler.
5640	* CPUID Info Handler.
5641	*
5642	*
5643	*/
5644
5645
5646
5647	/**
5648	* Get L1 cache / TLS associativity.
5649	*/
5650	static const char getCacheAss(unsigned u, char pszBuf)
5651	{
5652	if (u == 0)
5653	return "res0 ";
5654	if (u == 1)
5655	return "direct";
5656	if (u == 255)
5657	return "fully";
5658	if (u >= 256)
5659	return "???";
5660
5661	RTStrPrintf(pszBuf, 16, "%d way", u);
5662	return pszBuf;
5663	}
5664
5665
5666	/**
5667	* Get L2 cache associativity.
5668	*/
5669	const char *getL2CacheAss(unsigned u)
5670	{
5671	switch (u)
5672	{
5673	case 0: return "off ";
5674	case 1: return "direct";
5675	case 2: return "2 way ";
5676	case 3: return "res3 ";
5677	case 4: return "4 way ";
5678	case 5: return "res5 ";
5679	case 6: return "8 way ";
5680	case 7: return "res7 ";
5681	case 8: return "16 way";
5682	case 9: return "res9 ";
5683	case 10: return "res10 ";
5684	case 11: return "res11 ";
5685	case 12: return "res12 ";
5686	case 13: return "res13 ";
5687	case 14: return "res14 ";
5688	case 15: return "fully ";
5689	default: return "????";
5690	}
5691	}
5692
5693
5694	/** CPUID(1).EDX field descriptions. */
5695	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
5696	{
5697	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5698	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5699	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5700	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5701	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5702	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
5703	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5704	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5705	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5706	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5707	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
5708	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5709	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5710	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5711	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5712	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5713	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5714	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
5715	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
5716	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
5717	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
5718	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5719	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
5720	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
5721	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
5722	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
5723	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
5724	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
5725	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
5726	DBGFREGSUBFIELD_TERMINATOR()
5727	};
5728
5729	/** CPUID(1).ECX field descriptions. */
5730	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
5731	{
5732	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
5733	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
5734	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
5735	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
5736	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
5737	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
5738	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
5739	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
5740	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
5741	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
5742	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
5743	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
5744	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
5745	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
5746	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
5747	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
5748	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
5749	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
5750	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
5751	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
5752	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
5753	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
5754	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
5755	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
5756	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
5757	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
5758	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
5759	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
5760	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
5761	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
5762	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
5763	DBGFREGSUBFIELD_TERMINATOR()
5764	};
5765
5766	/** CPUID(7,0).EBX field descriptions. */
5767	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
5768	{
5769	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
5770	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
5771	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
5772	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
5773	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
5774	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
5775	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
5776	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
5777	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
5778	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
5779	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
5780	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
5781	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
5782	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
5783	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
5784	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
5785	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
5786	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
5787	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
5788	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
5789	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
5790	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
5791	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
5792	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
5793	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
5794	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
5795	DBGFREGSUBFIELD_TERMINATOR()
5796	};
5797
5798	/** CPUID(7,0).ECX field descriptions. */
5799	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
5800	{
5801	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
5802	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
5803	DBGFREGSUBFIELD_RO("OSPKU\0" "CR4.PKU mirror", 4, 1, 0),
5804	DBGFREGSUBFIELD_TERMINATOR()
5805	};
5806
5807
5808	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
5809	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
5810	{
5811	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
5812	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
5813	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
5814	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
5815	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
5816	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
5817	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
5818	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
5819	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
5820	DBGFREGSUBFIELD_TERMINATOR()
5821	};
5822
5823	/** CPUID(13,1).EAX field descriptions. */
5824	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
5825	{
5826	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
5827	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
5828	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
5829	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
5830	DBGFREGSUBFIELD_TERMINATOR()
5831	};
5832
5833
5834	/** CPUID(0x80000001,0).EDX field descriptions. */
5835	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
5836	{
5837	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5838	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5839	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5840	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5841	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5842	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
5843	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5844	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5845	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5846	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5847	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
5848	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5849	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5850	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5851	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5852	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5853	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5854	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
5855	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
5856	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5857	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
5858	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
5859	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
5860	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
5861	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
5862	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
5863	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
5864	DBGFREGSUBFIELD_TERMINATOR()
5865	};
5866
5867	/** CPUID(0x80000001,0).ECX field descriptions. */
5868	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
5869	{
5870	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
5871	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
5872	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
5873	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
5874	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
5875	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
5876	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
5877	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
5878	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
5879	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
5880	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
5881	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
5882	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
5883	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
5884	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
5885	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
5886	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
5887	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
5888	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
5889	DBGFREGSUBFIELD_TERMINATOR()
5890	};
5891
5892
5893	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
5894	const char *pszLeadIn, uint32_t cchWidth)
5895	{
5896	if (pszLeadIn)
5897	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5898
5899	for (uint32_t iBit = 0; iBit < 32; iBit++)
5900	if (RT_BIT_32(iBit) & uVal)
5901	{
5902	while ( pDesc->pszName != NULL
5903	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5904	pDesc++;
5905	if ( pDesc->pszName != NULL
5906	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5907	{
5908	if (pDesc->cBits == 1)
5909	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5910	else
5911	{
5912	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
5913	if (pDesc->cBits < 32)
5914	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5915	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
5916	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5917	}
5918	}
5919	else
5920	pHlp->pfnPrintf(pHlp, " %u", iBit);
5921	}
5922	if (pszLeadIn)
5923	pHlp->pfnPrintf(pHlp, "\n");
5924	}
5925
5926
5927	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5928	const char *pszLeadIn, uint32_t cchWidth)
5929	{
5930	if (pszLeadIn)
5931	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5932
5933	for (uint32_t iBit = 0; iBit < 64; iBit++)
5934	if (RT_BIT_64(iBit) & uVal)
5935	{
5936	while ( pDesc->pszName != NULL
5937	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5938	pDesc++;
5939	if ( pDesc->pszName != NULL
5940	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5941	{
5942	if (pDesc->cBits == 1)
5943	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5944	else
5945	{
5946	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
5947	if (pDesc->cBits < 64)
5948	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
5949	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
5950	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5951	}
5952	}
5953	else
5954	pHlp->pfnPrintf(pHlp, " %u", iBit);
5955	}
5956	if (pszLeadIn)
5957	pHlp->pfnPrintf(pHlp, "\n");
5958	}
5959
5960
5961	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5962	const char *pszLeadIn, uint32_t cchWidth)
5963	{
5964	if (!uVal)
5965	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5966	else
5967	{
5968	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5969	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
5970	pHlp->pfnPrintf(pHlp, " )\n");
5971	}
5972	}
5973
5974
5975	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
5976	uint32_t cchWidth)
5977	{
5978	uint32_t uCombined = uVal1 \| uVal2;
5979	for (uint32_t iBit = 0; iBit < 32; iBit++)
5980	if ( (RT_BIT_32(iBit) & uCombined)
5981	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
5982	{
5983	while ( pDesc->pszName != NULL
5984	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5985	pDesc++;
5986
5987	if ( pDesc->pszName != NULL
5988	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5989	{
5990	size_t cchMnemonic = strlen(pDesc->pszName);
5991	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
5992	size_t cchDesc = strlen(pszDesc);
5993	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
5994	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
5995	if (pDesc->cBits < 32)
5996	{
5997	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5998	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5999	}
6000
6001	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6002	pDesc->pszName, pszDesc,
6003	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6004	uFieldValue1, uFieldValue2);
6005
6006	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6007	pDesc++;
6008	}
6009	else
6010	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6011	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6012	}
6013	}
6014
6015
6016	/**
6017	* Produces a detailed summary of standard leaf 0x00000001.
6018	*
6019	* @param pHlp The info helper functions.
6020	* @param pCurLeaf The 0x00000001 leaf.
6021	* @param fVerbose Whether to be very verbose or not.
6022	* @param fIntel Set if intel CPU.
6023	*/
6024	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6025	{
6026	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6027	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6028	uint32_t uEAX = pCurLeaf->uEax;
6029	uint32_t uEBX = pCurLeaf->uEbx;
6030
6031	pHlp->pfnPrintf(pHlp,
6032	"%36s %2d \tExtended: %d \tEffective: %d\n"
6033	"%36s %2d \tExtended: %d \tEffective: %d\n"
6034	"%36s %d\n"
6035	"%36s %d (%s)\n"
6036	"%36s %#04x\n"
6037	"%36s %d\n"
6038	"%36s %d\n"
6039	"%36s %#04x\n"
6040	,
6041	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6042	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6043	"Stepping:", ASMGetCpuStepping(uEAX),
6044	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6045	"APIC ID:", (uEBX >> 24) & 0xff,
6046	"Logical CPUs:",(uEBX >> 16) & 0xff,
6047	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6048	"Brand ID:", (uEBX >> 0) & 0xff);
6049	if (fVerbose)
6050	{
6051	CPUMCPUID Host;
6052	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6053	pHlp->pfnPrintf(pHlp, "Features\n");
6054	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6055	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6056	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6057	}
6058	else
6059	{
6060	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6061	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6062	}
6063	}
6064
6065
6066	/**
6067	* Produces a detailed summary of standard leaf 0x00000007.
6068	*
6069	* @param pHlp The info helper functions.
6070	* @param paLeaves The CPUID leaves array.
6071	* @param cLeaves The number of leaves in the array.
6072	* @param pCurLeaf The first 0x00000007 leaf.
6073	* @param fVerbose Whether to be very verbose or not.
6074	*/
6075	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6076	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6077	{
6078	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6079	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6080	for (;;)
6081	{
6082	CPUMCPUID Host;
6083	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6084
6085	switch (pCurLeaf->uSubLeaf)
6086	{
6087	case 0:
6088	if (fVerbose)
6089	{
6090	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6091	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6092	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6093	if (pCurLeaf->uEdx \|\| Host.uEdx)
6094	pHlp->pfnPrintf(pHlp, "%36 %#x (%#x)\n", "Ext Features EDX:", pCurLeaf->uEdx, Host.uEdx);
6095	}
6096	else
6097	{
6098	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6099	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6100	if (pCurLeaf->uEdx)
6101	pHlp->pfnPrintf(pHlp, "%36 %#x\n", "Ext Features EDX:", pCurLeaf->uEdx);
6102	}
6103	break;
6104
6105	default:
6106	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6107	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6108	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6109	break;
6110
6111	}
6112
6113	/* advance. */
6114	pCurLeaf++;
6115	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6116	\|\| pCurLeaf->uLeaf != 0x7)
6117	break;
6118	}
6119	}
6120
6121
6122	/**
6123	* Produces a detailed summary of standard leaf 0x0000000d.
6124	*
6125	* @param pHlp The info helper functions.
6126	* @param paLeaves The CPUID leaves array.
6127	* @param cLeaves The number of leaves in the array.
6128	* @param pCurLeaf The first 0x00000007 leaf.
6129	* @param fVerbose Whether to be very verbose or not.
6130	*/
6131	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6132	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6133	{
6134	RT_NOREF_PV(fVerbose);
6135	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6136	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6137	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6138	{
6139	CPUMCPUID Host;
6140	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6141
6142	switch (uSubLeaf)
6143	{
6144	case 0:
6145	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6146	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6147	pCurLeaf->uEbx, pCurLeaf->uEcx);
6148	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6149
6150	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6151	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6152	"Valid XCR0 bits, guest:", 42);
6153	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6154	"Valid XCR0 bits, host:", 42);
6155	break;
6156
6157	case 1:
6158	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6159	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6160	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6161
6162	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6163	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6164	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6165
6166	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6167	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6168	" Valid IA32_XSS bits, guest:", 42);
6169	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6170	" Valid IA32_XSS bits, host:", 42);
6171	break;
6172
6173	default:
6174	if ( pCurLeaf
6175	&& pCurLeaf->uSubLeaf == uSubLeaf
6176	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6177	{
6178	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6179	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6180	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6181	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6182	if (pCurLeaf->uEdx)
6183	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6184	pHlp->pfnPrintf(pHlp, " --");
6185	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6186	pHlp->pfnPrintf(pHlp, "\n");
6187	}
6188	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6189	{
6190	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6191	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6192	if (Host.uEcx & ~RT_BIT_32(0))
6193	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6194	if (Host.uEdx)
6195	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6196	pHlp->pfnPrintf(pHlp, " --");
6197	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6198	pHlp->pfnPrintf(pHlp, "\n");
6199	}
6200	break;
6201
6202	}
6203
6204	/* advance. */
6205	if (pCurLeaf)
6206	{
6207	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6208	&& pCurLeaf->uSubLeaf <= uSubLeaf
6209	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6210	pCurLeaf++;
6211	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6212	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6213	pCurLeaf = NULL;
6214	}
6215	}
6216	}
6217
6218
6219	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6220	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6221	{
6222	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6223	&& pCurLeaf->uLeaf <= uUpToLeaf)
6224	{
6225	pHlp->pfnPrintf(pHlp,
6226	" %s\n"
6227	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6228	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6229	&& pCurLeaf->uLeaf <= uUpToLeaf)
6230	{
6231	CPUMCPUID Host;
6232	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6233	pHlp->pfnPrintf(pHlp,
6234	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6235	"Hst: %08x %08x %08x %08x\n",
6236	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6237	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6238	pCurLeaf++;
6239	}
6240	}
6241
6242	return pCurLeaf;
6243	}
6244
6245
6246	/**
6247	* Display the guest CpuId leaves.
6248	*
6249	* @param pVM The cross context VM structure.
6250	* @param pHlp The info helper functions.
6251	* @param pszArgs "terse", "default" or "verbose".
6252	*/
6253	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6254	{
6255	/*
6256	* Parse the argument.
6257	*/
6258	unsigned iVerbosity = 1;
6259	if (pszArgs)
6260	{
6261	pszArgs = RTStrStripL(pszArgs);
6262	if (!strcmp(pszArgs, "terse"))
6263	iVerbosity--;
6264	else if (!strcmp(pszArgs, "verbose"))
6265	iVerbosity++;
6266	}
6267
6268	uint32_t uLeaf;
6269	CPUMCPUID Host;
6270	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6271	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6272	PCCPUMCPUIDLEAF pCurLeaf;
6273	PCCPUMCPUIDLEAF pNextLeaf;
6274	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6275	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6276	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6277
6278	/*
6279	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6280	*/
6281	uint32_t cHstMax = ASMCpuId_EAX(0);
6282	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6283	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6284	pHlp->pfnPrintf(pHlp,
6285	" Raw Standard CPUID Leaves\n"
6286	" Leaf/sub-leaf eax ebx ecx edx\n");
6287	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6288	{
6289	uint32_t cMaxSubLeaves = 1;
6290	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6291	cMaxSubLeaves = 16;
6292	else if (uLeaf == 0xd)
6293	cMaxSubLeaves = 128;
6294
6295	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6296	{
6297	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6298	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6299	&& pCurLeaf->uLeaf == uLeaf
6300	&& pCurLeaf->uSubLeaf == uSubLeaf)
6301	{
6302	pHlp->pfnPrintf(pHlp,
6303	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6304	"Hst: %08x %08x %08x %08x\n",
6305	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6306	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6307	pCurLeaf++;
6308	}
6309	else if ( uLeaf != 0xd
6310	\|\| uSubLeaf <= 1
6311	\|\| Host.uEbx != 0 )
6312	pHlp->pfnPrintf(pHlp,
6313	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6314	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6315
6316	/* Done? */
6317	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6318	\|\| pCurLeaf->uLeaf != uLeaf)
6319	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6320	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6321	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6322	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6323	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6324	)
6325	)
6326	break;
6327	}
6328	}
6329	pNextLeaf = pCurLeaf;
6330
6331	/*
6332	* If verbose, decode it.
6333	*/
6334	if (iVerbosity && paLeaves[0].uLeaf == 0)
6335	pHlp->pfnPrintf(pHlp,
6336	"%36s %.04s%.04s%.04s\n"
6337	"%36s 0x00000000-%#010x\n"
6338	,
6339	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6340	"Supports:", paLeaves[0].uEax);
6341
6342	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6343	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6344
6345	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6346	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6347
6348	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6349	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6350
6351	pCurLeaf = pNextLeaf;
6352
6353	/*
6354	* Hypervisor leaves.
6355	*
6356	* Unlike most of the other leaves reported, the guest hypervisor leaves
6357	* aren't a subset of the host CPUID bits.
6358	*/
6359	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6360
6361	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6362	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6363	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6364	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6365	cMax = RT_MAX(cHstMax, cGstMax);
6366	if (cMax >= UINT32_C(0x40000000))
6367	{
6368	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6369
6370	/** @todo dump these in more detail. */
6371
6372	pCurLeaf = pNextLeaf;
6373	}
6374
6375
6376	/*
6377	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6378	* Implemented after AMD specs.
6379	*/
6380	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6381
6382	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6383	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6384	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6385	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6386	cMax = RT_MAX(cHstMax, cGstMax);
6387	if (cMax >= UINT32_C(0x80000000))
6388	{
6389
6390	pHlp->pfnPrintf(pHlp,
6391	" Raw Extended CPUID Leaves\n"
6392	" Leaf/sub-leaf eax ebx ecx edx\n");
6393	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6394	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6395	{
6396	uint32_t cMaxSubLeaves = 1;
6397	if (uLeaf == UINT32_C(0x8000001d))
6398	cMaxSubLeaves = 16;
6399
6400	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6401	{
6402	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6403	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6404	&& pCurLeaf->uLeaf == uLeaf
6405	&& pCurLeaf->uSubLeaf == uSubLeaf)
6406	{
6407	pHlp->pfnPrintf(pHlp,
6408	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6409	"Hst: %08x %08x %08x %08x\n",
6410	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6411	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6412	pCurLeaf++;
6413	}
6414	else if ( uLeaf != 0xd
6415	\|\| uSubLeaf <= 1
6416	\|\| Host.uEbx != 0 )
6417	pHlp->pfnPrintf(pHlp,
6418	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6419	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6420
6421	/* Done? */
6422	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6423	\|\| pCurLeaf->uLeaf != uLeaf)
6424	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6425	break;
6426	}
6427	}
6428	pNextLeaf = pCurLeaf;
6429
6430	/*
6431	* Understandable output
6432	*/
6433	if (iVerbosity)
6434	pHlp->pfnPrintf(pHlp,
6435	"Ext Name: %.4s%.4s%.4s\n"
6436	"Ext Supports: 0x80000000-%#010x\n",
6437	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6438
6439	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6440	if (iVerbosity && pCurLeaf)
6441	{
6442	uint32_t uEAX = pCurLeaf->uEax;
6443	pHlp->pfnPrintf(pHlp,
6444	"Family: %d \tExtended: %d \tEffective: %d\n"
6445	"Model: %d \tExtended: %d \tEffective: %d\n"
6446	"Stepping: %d\n"
6447	"Brand ID: %#05x\n",
6448	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6449	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6450	ASMGetCpuStepping(uEAX),
6451	pCurLeaf->uEbx & 0xfff);
6452
6453	if (iVerbosity == 1)
6454	{
6455	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6456	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6457	}
6458	else
6459	{
6460	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6461	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6462	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6463	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6464	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6465	}
6466	}
6467
6468	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6469	{
6470	char szString[443+1] = {0};
6471	uint32_t pu32 = (uint32_t )szString;
6472	*pu32++ = pCurLeaf->uEax;
6473	*pu32++ = pCurLeaf->uEbx;
6474	*pu32++ = pCurLeaf->uEcx;
6475	*pu32++ = pCurLeaf->uEdx;
6476	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6477	if (pCurLeaf)
6478	{
6479	*pu32++ = pCurLeaf->uEax;
6480	*pu32++ = pCurLeaf->uEbx;
6481	*pu32++ = pCurLeaf->uEcx;
6482	*pu32++ = pCurLeaf->uEdx;
6483	}
6484	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6485	if (pCurLeaf)
6486	{
6487	*pu32++ = pCurLeaf->uEax;
6488	*pu32++ = pCurLeaf->uEbx;
6489	*pu32++ = pCurLeaf->uEcx;
6490	*pu32++ = pCurLeaf->uEdx;
6491	}
6492	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6493	}
6494
6495	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6496	{
6497	uint32_t uEAX = pCurLeaf->uEax;
6498	uint32_t uEBX = pCurLeaf->uEbx;
6499	uint32_t uECX = pCurLeaf->uEcx;
6500	uint32_t uEDX = pCurLeaf->uEdx;
6501	char sz1[32];
6502	char sz2[32];
6503
6504	pHlp->pfnPrintf(pHlp,
6505	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6506	"TLB 2/4M Data: %s %3d entries\n",
6507	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6508	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6509	pHlp->pfnPrintf(pHlp,
6510	"TLB 4K Instr/Uni: %s %3d entries\n"
6511	"TLB 4K Data: %s %3d entries\n",
6512	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6513	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6514	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6515	"L1 Instr Cache Lines Per Tag: %d\n"
6516	"L1 Instr Cache Associativity: %s\n"
6517	"L1 Instr Cache Size: %d KB\n",
6518	(uEDX >> 0) & 0xff,
6519	(uEDX >> 8) & 0xff,
6520	getCacheAss((uEDX >> 16) & 0xff, sz1),
6521	(uEDX >> 24) & 0xff);
6522	pHlp->pfnPrintf(pHlp,
6523	"L1 Data Cache Line Size: %d bytes\n"
6524	"L1 Data Cache Lines Per Tag: %d\n"
6525	"L1 Data Cache Associativity: %s\n"
6526	"L1 Data Cache Size: %d KB\n",
6527	(uECX >> 0) & 0xff,
6528	(uECX >> 8) & 0xff,
6529	getCacheAss((uECX >> 16) & 0xff, sz1),
6530	(uECX >> 24) & 0xff);
6531	}
6532
6533	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6534	{
6535	uint32_t uEAX = pCurLeaf->uEax;
6536	uint32_t uEBX = pCurLeaf->uEbx;
6537	uint32_t uEDX = pCurLeaf->uEdx;
6538
6539	pHlp->pfnPrintf(pHlp,
6540	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6541	"L2 TLB 2/4M Data: %s %4d entries\n",
6542	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6543	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6544	pHlp->pfnPrintf(pHlp,
6545	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6546	"L2 TLB 4K Data: %s %4d entries\n",
6547	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6548	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6549	pHlp->pfnPrintf(pHlp,
6550	"L2 Cache Line Size: %d bytes\n"
6551	"L2 Cache Lines Per Tag: %d\n"
6552	"L2 Cache Associativity: %s\n"
6553	"L2 Cache Size: %d KB\n",
6554	(uEDX >> 0) & 0xff,
6555	(uEDX >> 8) & 0xf,
6556	getL2CacheAss((uEDX >> 12) & 0xf),
6557	(uEDX >> 16) & 0xffff);
6558	}
6559
6560	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
6561	{
6562	uint32_t uEDX = pCurLeaf->uEdx;
6563
6564	pHlp->pfnPrintf(pHlp, "APM Features: ");
6565	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
6566	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
6567	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
6568	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
6569	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
6570	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
6571	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " MC");
6572	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " HWPSTATE");
6573	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TscInvariant");
6574	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " CPB");
6575	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " EffFreqRO");
6576	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PFI");
6577	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PA");
6578	for (unsigned iBit = 13; iBit < 32; iBit++)
6579	if (uEDX & RT_BIT(iBit))
6580	pHlp->pfnPrintf(pHlp, " %d", iBit);
6581	pHlp->pfnPrintf(pHlp, "\n");
6582
6583	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6584	pHlp->pfnPrintf(pHlp, "Host Invariant-TSC support: %RTbool\n",
6585	cHstMax >= UINT32_C(0x80000007) && (Host.uEdx & RT_BIT(8)));
6586
6587	}
6588
6589	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0)) != NULL)
6590	{
6591	uint32_t uEAX = pCurLeaf->uEax;
6592	uint32_t uECX = pCurLeaf->uEcx;
6593
6594	pHlp->pfnPrintf(pHlp,
6595	"Physical Address Width: %d bits\n"
6596	"Virtual Address Width: %d bits\n"
6597	"Guest Physical Address Width: %d bits\n",
6598	(uEAX >> 0) & 0xff,
6599	(uEAX >> 8) & 0xff,
6600	(uEAX >> 16) & 0xff);
6601	pHlp->pfnPrintf(pHlp,
6602	"Physical Core Count: %d\n",
6603	((uECX >> 0) & 0xff) + 1);
6604	}
6605
6606	pCurLeaf = pNextLeaf;
6607	}
6608
6609
6610
6611	/*
6612	* Centaur.
6613	*/
6614	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
6615
6616	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6617	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
6618	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
6619	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
6620	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
6621	cMax = RT_MAX(cHstMax, cGstMax);
6622	if (cMax >= UINT32_C(0xc0000000))
6623	{
6624	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
6625
6626	/*
6627	* Understandable output
6628	*/
6629	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
6630	pHlp->pfnPrintf(pHlp,
6631	"Centaur Supports: 0xc0000000-%#010x\n",
6632	pCurLeaf->uEax);
6633
6634	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
6635	{
6636	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6637	uint32_t uEdxGst = pCurLeaf->uEdx;
6638	uint32_t uEdxHst = Host.uEdx;
6639
6640	if (iVerbosity == 1)
6641	{
6642	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
6643	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
6644	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
6645	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
6646	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
6647	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
6648	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
6649	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
6650	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
6651	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6652	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
6653	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
6654	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
6655	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
6656	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
6657	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
6658	for (unsigned iBit = 14; iBit < 32; iBit++)
6659	if (uEdxGst & RT_BIT(iBit))
6660	pHlp->pfnPrintf(pHlp, " %d", iBit);
6661	pHlp->pfnPrintf(pHlp, "\n");
6662	}
6663	else
6664	{
6665	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
6666	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
6667	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
6668	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
6669	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
6670	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
6671	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
6672	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
6673	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
6674	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6675	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
6676	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
6677	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
6678	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
6679	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
6680	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
6681	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
6682	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
6683	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
6684	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
6685	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
6686	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
6687	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
6688	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
6689	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
6690	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
6691	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
6692	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
6693	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
6694	for (unsigned iBit = 27; iBit < 32; iBit++)
6695	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
6696	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
6697	pHlp->pfnPrintf(pHlp, "\n");
6698	}
6699	}
6700
6701	pCurLeaf = pNextLeaf;
6702	}
6703
6704	/*
6705	* The remainder.
6706	*/
6707	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
6708	}
6709
6710
6711
6712
6713
6714	/*
6715	*
6716	*
6717	* PATM interfaces.
6718	* PATM interfaces.
6719	* PATM interfaces.
6720	*
6721	*
6722	*/
6723
6724
6725	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
6726	/** @name Patchmanager CPUID legacy table APIs
6727	* @{
6728	*/
6729
6730	/**
6731	* Gets a pointer to the default CPUID leaf.
6732	*
6733	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
6734	* @param pVM The cross context VM structure.
6735	* @remark Intended for PATM only.
6736	*/
6737	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
6738	{
6739	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
6740	}
6741
6742
6743	/**
6744	* Gets a number of standard CPUID leaves (PATM only).
6745	*
6746	* @returns Number of leaves.
6747	* @param pVM The cross context VM structure.
6748	* @remark Intended for PATM - legacy, don't use in new code.
6749	*/
6750	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
6751	{
6752	RT_NOREF_PV(pVM);
6753	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
6754	}
6755
6756
6757	/**
6758	* Gets a number of extended CPUID leaves (PATM only).
6759	*
6760	* @returns Number of leaves.
6761	* @param pVM The cross context VM structure.
6762	* @remark Intended for PATM - legacy, don't use in new code.
6763	*/
6764	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
6765	{
6766	RT_NOREF_PV(pVM);
6767	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
6768	}
6769
6770
6771	/**
6772	* Gets a number of centaur CPUID leaves.
6773	*
6774	* @returns Number of leaves.
6775	* @param pVM The cross context VM structure.
6776	* @remark Intended for PATM - legacy, don't use in new code.
6777	*/
6778	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
6779	{
6780	RT_NOREF_PV(pVM);
6781	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
6782	}
6783
6784
6785	/**
6786	* Gets a pointer to the array of standard CPUID leaves.
6787	*
6788	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
6789	*
6790	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
6791	* @param pVM The cross context VM structure.
6792	* @remark Intended for PATM - legacy, don't use in new code.
6793	*/
6794	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
6795	{
6796	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
6797	}
6798
6799
6800	/**
6801	* Gets a pointer to the array of extended CPUID leaves.
6802	*
6803	* CPUMGetGuestCpuIdExtMax() give the size of the array.
6804	*
6805	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
6806	* @param pVM The cross context VM structure.
6807	* @remark Intended for PATM - legacy, don't use in new code.
6808	*/
6809	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
6810	{
6811	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
6812	}
6813
6814
6815	/**
6816	* Gets a pointer to the array of centaur CPUID leaves.
6817	*
6818	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
6819	*
6820	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
6821	* @param pVM The cross context VM structure.
6822	* @remark Intended for PATM - legacy, don't use in new code.
6823	*/
6824	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
6825	{
6826	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
6827	}
6828
6829	/** @} */
6830	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
6831
6832	#endif /* VBOX_IN_VMM */
6833

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 66095

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