CPUMR3CpuId.cpp@ 66215

Last change on this file since 66215 was 66215, checked in by vboxsync, 8 years ago
CPUMR3CpuId.cpp: Fixed typo in unused paranoid code.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 313.4 KB

Line
1	/* $Id: CPUMR3CpuId.cpp 66215 2017-03-22 21:33:09Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/ssm.h>
27	#include "CPUMInternal.h"
28	#include <VBox/vmm/vm.h>
29	#include <VBox/vmm/mm.h>
30
31	#include <VBox/err.h>
32	#include <iprt/asm-amd64-x86.h>
33	#include <iprt/ctype.h>
34	#include <iprt/mem.h>
35	#include <iprt/string.h>
36
37
38	/*********************************************************************************************************************************
39	* Defined Constants And Macros *
40	*********************************************************************************************************************************/
41	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
42	#define CPUM_CPUID_MAX_LEAVES 2048
43	/* Max size we accept for the XSAVE area. */
44	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
45	/* Min size we accept for the XSAVE area. */
46	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
47
48
49	/*********************************************************************************************************************************
50	* Global Variables *
51	*********************************************************************************************************************************/
52	/**
53	* The intel pentium family.
54	*/
55	static const CPUMMICROARCH g_aenmIntelFamily06[] =
56	{
57	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
58	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
59	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
60	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
61	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
63	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
64	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
65	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
66	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
67	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
68	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
69	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
70	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
71	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
72	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
73	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
74	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
79	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
80	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
81	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
82	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
83	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
84	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
86	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
87	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
88	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
89	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
90	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
91	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
95	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
96	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
97	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
98	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
99	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
100	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
102	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
103	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
104	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
105	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
106	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
107	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
111	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
112	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
113	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
114	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
115	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
116	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
118	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
119	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
120	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
121	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
122	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
123	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
127	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
128	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
129	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
130	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
131	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
132	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
134	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
135	/* [78(0x4e)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed */
136	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / unconfirmed, Broadwell-E */
137	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
138	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
139	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed server cpu */
143	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
144	/* [87(0x57)] = */ kCpumMicroarch_Intel_Unknown,
145	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
146	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
147	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
148	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / unconfirmed */
150	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
151	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
152	/* [95(0x5f)] = */ kCpumMicroarch_Intel_Unknown,
153	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
154	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
155	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [99(0x64)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x65)] = */ kCpumMicroarch_Intel_Unknown,
159	/* [99(0x66)] = / kCpumMicroarch_Intel_Core7_Cannonlake, / unconfirmed */
160	};
161
162
163
164	/**
165	* Figures out the (sub-)micro architecture given a bit of CPUID info.
166	*
167	* @returns Micro architecture.
168	* @param enmVendor The CPU vendor .
169	* @param bFamily The CPU family.
170	* @param bModel The CPU model.
171	* @param bStepping The CPU stepping.
172	*/
173	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
174	uint8_t bModel, uint8_t bStepping)
175	{
176	if (enmVendor == CPUMCPUVENDOR_AMD)
177	{
178	switch (bFamily)
179	{
180	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
181	case 0x03: return kCpumMicroarch_AMD_Am386;
182	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
183	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
184	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
185	case 0x06:
186	switch (bModel)
187	{
188	case 0: return kCpumMicroarch_AMD_K7_Palomino;
189	case 1: return kCpumMicroarch_AMD_K7_Palomino;
190	case 2: return kCpumMicroarch_AMD_K7_Palomino;
191	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
192	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
193	case 6: return kCpumMicroarch_AMD_K7_Palomino;
194	case 7: return kCpumMicroarch_AMD_K7_Morgan;
195	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
196	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
197	}
198	return kCpumMicroarch_AMD_K7_Unknown;
199	case 0x0f:
200	/*
201	* This family is a friggin mess. Trying my best to make some
202	* sense out of it. Too much happened in the 0x0f family to
203	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
204	*
205	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
206	* cpu-world.com, and other places:
207	* - 130nm:
208	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
209	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
210	* - Newcastle: FC0/DH-CG (errum #180: FE0/DH-CG), FF0/DH-CG
211	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
212	* - Odessa: FC0/DH-CG (errum #180: FE0/DH-CG)
213	* - Paris: FF0/DH-CG, FC0/DH-CG (errum #180: FE0/DH-CG),
214	* - 90nm:
215	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
216	* - Oakville: 10FC0/DH-D0.
217	* - Georgetown: 10FC0/DH-D0.
218	* - Sonora: 10FC0/DH-D0.
219	* - Venus: 20F71/SH-E4
220	* - Troy: 20F51/SH-E4
221	* - Athens: 20F51/SH-E4
222	* - San Diego: 20F71/SH-E4.
223	* - Lancaster: 20F42/SH-E5
224	* - Newark: 20F42/SH-E5.
225	* - Albany: 20FC2/DH-E6.
226	* - Roma: 20FC2/DH-E6.
227	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
228	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
229	* - 90nm introducing Dual core:
230	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
231	* - Italy: 20F10/JH-E1, 20F12/JH-E6
232	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
233	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
234	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
235	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
236	* - Santa Ana: 40F32/JH-F2, /-F3
237	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
238	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
239	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
240	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
241	* - Keene: 40FC2/DH-F2.
242	* - Richmond: 40FC2/DH-F2
243	* - Taylor: 40F82/BH-F2
244	* - Trinidad: 40F82/BH-F2
245	*
246	* - 65nm:
247	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
248	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
249	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
250	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
251	* - Sherman: /-G1, 70FC2/DH-G2.
252	* - Huron: 70FF2/DH-G2.
253	*/
254	if (bModel < 0x10)
255	return kCpumMicroarch_AMD_K8_130nm;
256	if (bModel >= 0x60 && bModel < 0x80)
257	return kCpumMicroarch_AMD_K8_65nm;
258	if (bModel >= 0x40)
259	return kCpumMicroarch_AMD_K8_90nm_AMDV;
260	switch (bModel)
261	{
262	case 0x21:
263	case 0x23:
264	case 0x2b:
265	case 0x2f:
266	case 0x37:
267	case 0x3f:
268	return kCpumMicroarch_AMD_K8_90nm_DualCore;
269	}
270	return kCpumMicroarch_AMD_K8_90nm;
271	case 0x10:
272	return kCpumMicroarch_AMD_K10;
273	case 0x11:
274	return kCpumMicroarch_AMD_K10_Lion;
275	case 0x12:
276	return kCpumMicroarch_AMD_K10_Llano;
277	case 0x14:
278	return kCpumMicroarch_AMD_Bobcat;
279	case 0x15:
280	switch (bModel)
281	{
282	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
283	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
284	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
285	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
286	case 0x11: /* ?? */
287	case 0x12: /* ?? */
288	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
289	}
290	return kCpumMicroarch_AMD_15h_Unknown;
291	case 0x16:
292	return kCpumMicroarch_AMD_Jaguar;
293	case 0x17:
294	return kCpumMicroarch_AMD_Zen_Ryzen;
295	}
296	return kCpumMicroarch_AMD_Unknown;
297	}
298
299	if (enmVendor == CPUMCPUVENDOR_INTEL)
300	{
301	switch (bFamily)
302	{
303	case 3:
304	return kCpumMicroarch_Intel_80386;
305	case 4:
306	return kCpumMicroarch_Intel_80486;
307	case 5:
308	return kCpumMicroarch_Intel_P5;
309	case 6:
310	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
311	return g_aenmIntelFamily06[bModel];
312	return kCpumMicroarch_Intel_Atom_Unknown;
313	case 15:
314	switch (bModel)
315	{
316	case 0: return kCpumMicroarch_Intel_NB_Willamette;
317	case 1: return kCpumMicroarch_Intel_NB_Willamette;
318	case 2: return kCpumMicroarch_Intel_NB_Northwood;
319	case 3: return kCpumMicroarch_Intel_NB_Prescott;
320	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
321	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
322	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
323	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
324	default: return kCpumMicroarch_Intel_NB_Unknown;
325	}
326	break;
327	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
328	case 0:
329	return kCpumMicroarch_Intel_8086;
330	case 1:
331	return kCpumMicroarch_Intel_80186;
332	case 2:
333	return kCpumMicroarch_Intel_80286;
334	}
335	return kCpumMicroarch_Intel_Unknown;
336	}
337
338	if (enmVendor == CPUMCPUVENDOR_VIA)
339	{
340	switch (bFamily)
341	{
342	case 5:
343	switch (bModel)
344	{
345	case 1: return kCpumMicroarch_Centaur_C6;
346	case 4: return kCpumMicroarch_Centaur_C6;
347	case 8: return kCpumMicroarch_Centaur_C2;
348	case 9: return kCpumMicroarch_Centaur_C3;
349	}
350	break;
351
352	case 6:
353	switch (bModel)
354	{
355	case 5: return kCpumMicroarch_VIA_C3_M2;
356	case 6: return kCpumMicroarch_VIA_C3_C5A;
357	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
358	case 8: return kCpumMicroarch_VIA_C3_C5N;
359	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
360	case 10: return kCpumMicroarch_VIA_C7_C5J;
361	case 15: return kCpumMicroarch_VIA_Isaiah;
362	}
363	break;
364	}
365	return kCpumMicroarch_VIA_Unknown;
366	}
367
368	if (enmVendor == CPUMCPUVENDOR_CYRIX)
369	{
370	switch (bFamily)
371	{
372	case 4:
373	switch (bModel)
374	{
375	case 9: return kCpumMicroarch_Cyrix_5x86;
376	}
377	break;
378
379	case 5:
380	switch (bModel)
381	{
382	case 2: return kCpumMicroarch_Cyrix_M1;
383	case 4: return kCpumMicroarch_Cyrix_MediaGX;
384	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
385	}
386	break;
387
388	case 6:
389	switch (bModel)
390	{
391	case 0: return kCpumMicroarch_Cyrix_M2;
392	}
393	break;
394
395	}
396	return kCpumMicroarch_Cyrix_Unknown;
397	}
398
399	return kCpumMicroarch_Unknown;
400	}
401
402
403	/**
404	* Translates a microarchitecture enum value to the corresponding string
405	* constant.
406	*
407	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
408	* NULL if the value is invalid.
409	*
410	* @param enmMicroarch The enum value to convert.
411	*/
412	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
413	{
414	switch (enmMicroarch)
415	{
416	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
417	CASE_RET_STR(kCpumMicroarch_Intel_8086);
418	CASE_RET_STR(kCpumMicroarch_Intel_80186);
419	CASE_RET_STR(kCpumMicroarch_Intel_80286);
420	CASE_RET_STR(kCpumMicroarch_Intel_80386);
421	CASE_RET_STR(kCpumMicroarch_Intel_80486);
422	CASE_RET_STR(kCpumMicroarch_Intel_P5);
423
424	CASE_RET_STR(kCpumMicroarch_Intel_P6);
425	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
426	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
427
428	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
429	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
430	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
431
432	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
433	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
434
435	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
436	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
437	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
438	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
439	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
440	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
441	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
442	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Cannonlake);
443
444	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
445	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
446	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
447	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
448	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
449	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
450	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
451
452	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
453	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
454	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
455	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
456	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
457	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
458	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
459
460	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
461
462	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
463	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
464	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
465	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
466	CASE_RET_STR(kCpumMicroarch_AMD_K5);
467	CASE_RET_STR(kCpumMicroarch_AMD_K6);
468
469	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
470	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
471	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
472	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
473	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
474	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
475	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
476
477	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
478	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
479	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
480	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
481	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
482
483	CASE_RET_STR(kCpumMicroarch_AMD_K10);
484	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
485	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
486	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
487	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
488
489	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
490	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
491	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
492	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
493	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
494
495	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
496
497	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
498
499	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
500
501	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
502	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
503	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
504	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
505	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
506	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
507	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
508	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
509	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
510	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
511	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
512	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
513	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
514
515	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
516	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
517	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
518	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
519	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
520	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
521
522	CASE_RET_STR(kCpumMicroarch_NEC_V20);
523	CASE_RET_STR(kCpumMicroarch_NEC_V30);
524
525	CASE_RET_STR(kCpumMicroarch_Unknown);
526
527	#undef CASE_RET_STR
528	case kCpumMicroarch_Invalid:
529	case kCpumMicroarch_Intel_End:
530	case kCpumMicroarch_Intel_Core7_End:
531	case kCpumMicroarch_Intel_Atom_End:
532	case kCpumMicroarch_Intel_P6_Core_Atom_End:
533	case kCpumMicroarch_Intel_NB_End:
534	case kCpumMicroarch_AMD_K7_End:
535	case kCpumMicroarch_AMD_K8_End:
536	case kCpumMicroarch_AMD_15h_End:
537	case kCpumMicroarch_AMD_16h_End:
538	case kCpumMicroarch_AMD_Zen_End:
539	case kCpumMicroarch_AMD_End:
540	case kCpumMicroarch_VIA_End:
541	case kCpumMicroarch_Cyrix_End:
542	case kCpumMicroarch_NEC_End:
543	case kCpumMicroarch_32BitHack:
544	break;
545	/* no default! */
546	}
547
548	return NULL;
549	}
550
551
552
553	/**
554	* Gets a matching leaf in the CPUID leaf array.
555	*
556	* @returns Pointer to the matching leaf, or NULL if not found.
557	* @param paLeaves The CPUID leaves to search. This is sorted.
558	* @param cLeaves The number of leaves in the array.
559	* @param uLeaf The leaf to locate.
560	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
561	*/
562	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
563	{
564	/* Lazy bird does linear lookup here since this is only used for the
565	occational CPUID overrides. */
566	for (uint32_t i = 0; i < cLeaves; i++)
567	if ( paLeaves[i].uLeaf == uLeaf
568	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
569	return &paLeaves[i];
570	return NULL;
571	}
572
573
574	#ifndef IN_VBOX_CPU_REPORT
575	/**
576	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
577	*
578	* @returns true if found, false it not.
579	* @param paLeaves The CPUID leaves to search. This is sorted.
580	* @param cLeaves The number of leaves in the array.
581	* @param uLeaf The leaf to locate.
582	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
583	* @param pLegacy The legacy output leaf.
584	*/
585	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
586	PCPUMCPUID pLegacy)
587	{
588	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
589	if (pLeaf)
590	{
591	pLegacy->uEax = pLeaf->uEax;
592	pLegacy->uEbx = pLeaf->uEbx;
593	pLegacy->uEcx = pLeaf->uEcx;
594	pLegacy->uEdx = pLeaf->uEdx;
595	return true;
596	}
597	return false;
598	}
599	#endif /* IN_VBOX_CPU_REPORT */
600
601
602	/**
603	* Ensures that the CPUID leaf array can hold one more leaf.
604	*
605	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
606	* failure.
607	* @param pVM The cross context VM structure. If NULL, use
608	* the process heap, otherwise the VM's hyper heap.
609	* @param ppaLeaves Pointer to the variable holding the array pointer
610	* (input/output).
611	* @param cLeaves The current array size.
612	*
613	* @remarks This function will automatically update the R0 and RC pointers when
614	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
615	* be the corresponding VM's CPUID arrays (which is asserted).
616	*/
617	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
618	{
619	/*
620	* If pVM is not specified, we're on the regular heap and can waste a
621	* little space to speed things up.
622	*/
623	uint32_t cAllocated;
624	if (!pVM)
625	{
626	cAllocated = RT_ALIGN(cLeaves, 16);
627	if (cLeaves + 1 > cAllocated)
628	{
629	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
630	if (pvNew)
631	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
632	else
633	{
634	RTMemFree(*ppaLeaves);
635	*ppaLeaves = NULL;
636	}
637	}
638	}
639	/*
640	* Otherwise, we're on the hyper heap and are probably just inserting
641	* one or two leaves and should conserve space.
642	*/
643	else
644	{
645	#ifdef IN_VBOX_CPU_REPORT
646	AssertReleaseFailed();
647	#else
648	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
649	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
650
651	size_t cb = cLeaves * sizeof(**ppaLeaves);
652	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
653	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
654	if (RT_SUCCESS(rc))
655	{
656	/* Update the R0 and RC pointers. */
657	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
658	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
659	}
660	else
661	{
662	*ppaLeaves = NULL;
663	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
664	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
665	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
666	}
667	#endif
668	}
669	return *ppaLeaves;
670	}
671
672
673	/**
674	* Append a CPUID leaf or sub-leaf.
675	*
676	* ASSUMES linear insertion order, so we'll won't need to do any searching or
677	* replace anything. Use cpumR3CpuIdInsert() for those cases.
678	*
679	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
680	* the caller need do no more work.
681	* @param ppaLeaves Pointer to the pointer to the array of sorted
682	* CPUID leaves and sub-leaves.
683	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
684	* @param uLeaf The leaf we're adding.
685	* @param uSubLeaf The sub-leaf number.
686	* @param fSubLeafMask The sub-leaf mask.
687	* @param uEax The EAX value.
688	* @param uEbx The EBX value.
689	* @param uEcx The ECX value.
690	* @param uEdx The EDX value.
691	* @param fFlags The flags.
692	*/
693	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
694	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
695	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
696	{
697	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
698	return VERR_NO_MEMORY;
699
700	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
701	Assert( *pcLeaves == 0
702	\|\| pNew[-1].uLeaf < uLeaf
703	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
704
705	pNew->uLeaf = uLeaf;
706	pNew->uSubLeaf = uSubLeaf;
707	pNew->fSubLeafMask = fSubLeafMask;
708	pNew->uEax = uEax;
709	pNew->uEbx = uEbx;
710	pNew->uEcx = uEcx;
711	pNew->uEdx = uEdx;
712	pNew->fFlags = fFlags;
713
714	*pcLeaves += 1;
715	return VINF_SUCCESS;
716	}
717
718
719	/**
720	* Checks that we've updated the CPUID leaves array correctly.
721	*
722	* This is a no-op in non-strict builds.
723	*
724	* @param paLeaves The leaves array.
725	* @param cLeaves The number of leaves.
726	*/
727	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
728	{
729	#ifdef VBOX_STRICT
730	for (uint32_t i = 1; i < cLeaves; i++)
731	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
732	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
733	else
734	{
735	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
736	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
737	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
738	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
739	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
740	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
741	}
742	#else
743	NOREF(paLeaves);
744	NOREF(cLeaves);
745	#endif
746	}
747
748
749	/**
750	* Inserts a CPU ID leaf, replacing any existing ones.
751	*
752	* When inserting a simple leaf where we already got a series of sub-leaves with
753	* the same leaf number (eax), the simple leaf will replace the whole series.
754	*
755	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
756	* host-context heap and has only been allocated/reallocated by the
757	* cpumR3CpuIdEnsureSpace function.
758	*
759	* @returns VBox status code.
760	* @param pVM The cross context VM structure. If NULL, use
761	* the process heap, otherwise the VM's hyper heap.
762	* @param ppaLeaves Pointer to the pointer to the array of sorted
763	* CPUID leaves and sub-leaves. Must be NULL if using
764	* the hyper heap.
765	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
766	* be NULL if using the hyper heap.
767	* @param pNewLeaf Pointer to the data of the new leaf we're about to
768	* insert.
769	*/
770	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
771	{
772	/*
773	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
774	*/
775	if (pVM)
776	{
777	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
778	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
779
780	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
781	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
782	}
783
784	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
785	uint32_t cLeaves = *pcLeaves;
786
787	/*
788	* Validate the new leaf a little.
789	*/
790	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
791	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
792	VERR_INVALID_FLAGS);
793	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
794	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
795	VERR_INVALID_PARAMETER);
796	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
797	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
798	VERR_INVALID_PARAMETER);
799	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
800	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
801	VERR_INVALID_PARAMETER);
802
803	/*
804	* Find insertion point. The lazy bird uses the same excuse as in
805	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
806	*/
807	uint32_t i;
808	if ( cLeaves > 0
809	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
810	{
811	/* Add at end. */
812	i = cLeaves;
813	}
814	else if ( cLeaves > 0
815	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
816	{
817	/* Either replacing the last leaf or dealing with sub-leaves. Spool
818	back to the first sub-leaf to pretend we did the linear search. */
819	i = cLeaves - 1;
820	while ( i > 0
821	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
822	i--;
823	}
824	else
825	{
826	/* Linear search from the start. */
827	i = 0;
828	while ( i < cLeaves
829	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
830	i++;
831	}
832	if ( i < cLeaves
833	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
834	{
835	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
836	{
837	/*
838	* The sub-leaf mask differs, replace all existing leaves with the
839	* same leaf number.
840	*/
841	uint32_t c = 1;
842	while ( i + c < cLeaves
843	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
844	c++;
845	if (c > 1 && i + c < cLeaves)
846	{
847	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
848	*pcLeaves = cLeaves -= c - 1;
849	}
850
851	paLeaves[i] = *pNewLeaf;
852	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
853	return VINF_SUCCESS;
854	}
855
856	/* Find sub-leaf insertion point. */
857	while ( i < cLeaves
858	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
859	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
860	i++;
861
862	/*
863	* If we've got an exactly matching leaf, replace it.
864	*/
865	if ( i < cLeaves
866	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
867	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
868	{
869	paLeaves[i] = *pNewLeaf;
870	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
871	return VINF_SUCCESS;
872	}
873	}
874
875	/*
876	* Adding a new leaf at 'i'.
877	*/
878	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
879	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
880	if (!paLeaves)
881	return VERR_NO_MEMORY;
882
883	if (i < cLeaves)
884	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
885	*pcLeaves += 1;
886	paLeaves[i] = *pNewLeaf;
887
888	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
889	return VINF_SUCCESS;
890	}
891
892
893	#ifndef IN_VBOX_CPU_REPORT
894	/**
895	* Removes a range of CPUID leaves.
896	*
897	* This will not reallocate the array.
898	*
899	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
900	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
901	* @param uFirst The first leaf.
902	* @param uLast The last leaf.
903	*/
904	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
905	{
906	uint32_t cLeaves = *pcLeaves;
907
908	Assert(uFirst <= uLast);
909
910	/*
911	* Find the first one.
912	*/
913	uint32_t iFirst = 0;
914	while ( iFirst < cLeaves
915	&& paLeaves[iFirst].uLeaf < uFirst)
916	iFirst++;
917
918	/*
919	* Find the end (last + 1).
920	*/
921	uint32_t iEnd = iFirst;
922	while ( iEnd < cLeaves
923	&& paLeaves[iEnd].uLeaf <= uLast)
924	iEnd++;
925
926	/*
927	* Adjust the array if anything needs removing.
928	*/
929	if (iFirst < iEnd)
930	{
931	if (iEnd < cLeaves)
932	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
933	*pcLeaves = cLeaves -= (iEnd - iFirst);
934	}
935
936	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
937	}
938	#endif /* IN_VBOX_CPU_REPORT */
939
940
941	/**
942	* Checks if ECX make a difference when reading a given CPUID leaf.
943	*
944	* @returns @c true if it does, @c false if it doesn't.
945	* @param uLeaf The leaf we're reading.
946	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
947	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
948	* final sub-leaf (for leaf 0xb only).
949	*/
950	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
951	{
952	*pfFinalEcxUnchanged = false;
953
954	uint32_t auCur[4];
955	uint32_t auPrev[4];
956	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
957
958	/* Look for sub-leaves. */
959	uint32_t uSubLeaf = 1;
960	for (;;)
961	{
962	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
963	if (memcmp(auCur, auPrev, sizeof(auCur)))
964	break;
965
966	/* Advance / give up. */
967	uSubLeaf++;
968	if (uSubLeaf >= 64)
969	{
970	*pcSubLeaves = 1;
971	return false;
972	}
973	}
974
975	/* Count sub-leaves. */
976	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
977	uint32_t cRepeats = 0;
978	uSubLeaf = 0;
979	for (;;)
980	{
981	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
982
983	/* Figuring out when to stop isn't entirely straight forward as we need
984	to cover undocumented behavior up to a point and implementation shortcuts. */
985
986	/* 1. Look for more than 4 repeating value sets. */
987	if ( auCur[0] == auPrev[0]
988	&& auCur[1] == auPrev[1]
989	&& ( auCur[2] == auPrev[2]
990	\|\| ( auCur[2] == uSubLeaf
991	&& auPrev[2] == uSubLeaf - 1) )
992	&& auCur[3] == auPrev[3])
993	{
994	if ( uLeaf != 0xd
995	\|\| uSubLeaf >= 64
996	\|\| ( auCur[0] == 0
997	&& auCur[1] == 0
998	&& auCur[2] == 0
999	&& auCur[3] == 0
1000	&& auPrev[2] == 0) )
1001	cRepeats++;
1002	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1003	break;
1004	}
1005	else
1006	cRepeats = 0;
1007
1008	/* 2. Look for zero values. */
1009	if ( auCur[0] == 0
1010	&& auCur[1] == 0
1011	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1012	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1013	&& uSubLeaf >= cMinLeaves)
1014	{
1015	cRepeats = 0;
1016	break;
1017	}
1018
1019	/* 3. Leaf 0xb level type 0 check. */
1020	if ( uLeaf == 0xb
1021	&& (auCur[2] & 0xff00) == 0
1022	&& (auPrev[2] & 0xff00) == 0)
1023	{
1024	cRepeats = 0;
1025	break;
1026	}
1027
1028	/* 99. Give up. */
1029	if (uSubLeaf >= 128)
1030	{
1031	#ifndef IN_VBOX_CPU_REPORT
1032	/* Ok, limit it according to the documentation if possible just to
1033	avoid annoying users with these detection issues. */
1034	uint32_t cDocLimit = UINT32_MAX;
1035	if (uLeaf == 0x4)
1036	cDocLimit = 4;
1037	else if (uLeaf == 0x7)
1038	cDocLimit = 1;
1039	else if (uLeaf == 0xd)
1040	cDocLimit = 63;
1041	else if (uLeaf == 0xf)
1042	cDocLimit = 2;
1043	if (cDocLimit != UINT32_MAX)
1044	{
1045	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1046	*pcSubLeaves = cDocLimit + 3;
1047	return true;
1048	}
1049	#endif
1050	*pcSubLeaves = UINT32_MAX;
1051	return true;
1052	}
1053
1054	/* Advance. */
1055	uSubLeaf++;
1056	memcpy(auPrev, auCur, sizeof(auCur));
1057	}
1058
1059	/* Standard exit. */
1060	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1061	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1062	if (*pcSubLeaves == 0)
1063	*pcSubLeaves = 1;
1064	return true;
1065	}
1066
1067
1068	/**
1069	* Gets a CPU ID leaf.
1070	*
1071	* @returns VBox status code.
1072	* @param pVM The cross context VM structure.
1073	* @param pLeaf Where to store the found leaf.
1074	* @param uLeaf The leaf to locate.
1075	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1076	*/
1077	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1078	{
1079	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1080	uLeaf, uSubLeaf);
1081	if (pcLeaf)
1082	{
1083	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1084	return VINF_SUCCESS;
1085	}
1086
1087	return VERR_NOT_FOUND;
1088	}
1089
1090
1091	/**
1092	* Inserts a CPU ID leaf, replacing any existing ones.
1093	*
1094	* @returns VBox status code.
1095	* @param pVM The cross context VM structure.
1096	* @param pNewLeaf Pointer to the leaf being inserted.
1097	*/
1098	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1099	{
1100	/*
1101	* Validate parameters.
1102	*/
1103	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1104	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1105
1106	/*
1107	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1108	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1109	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1110	*/
1111	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1112	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1113	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1114	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1115	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1116	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1117	{
1118	return VERR_NOT_SUPPORTED;
1119	}
1120
1121	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1122	}
1123
1124	/**
1125	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1126	*
1127	* @returns VBox status code.
1128	* @param ppaLeaves Where to return the array pointer on success.
1129	* Use RTMemFree to release.
1130	* @param pcLeaves Where to return the size of the array on
1131	* success.
1132	*/
1133	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1134	{
1135	*ppaLeaves = NULL;
1136	*pcLeaves = 0;
1137
1138	/*
1139	* Try out various candidates. This must be sorted!
1140	*/
1141	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1142	{
1143	{ UINT32_C(0x00000000), false },
1144	{ UINT32_C(0x10000000), false },
1145	{ UINT32_C(0x20000000), false },
1146	{ UINT32_C(0x30000000), false },
1147	{ UINT32_C(0x40000000), false },
1148	{ UINT32_C(0x50000000), false },
1149	{ UINT32_C(0x60000000), false },
1150	{ UINT32_C(0x70000000), false },
1151	{ UINT32_C(0x80000000), false },
1152	{ UINT32_C(0x80860000), false },
1153	{ UINT32_C(0x8ffffffe), true },
1154	{ UINT32_C(0x8fffffff), true },
1155	{ UINT32_C(0x90000000), false },
1156	{ UINT32_C(0xa0000000), false },
1157	{ UINT32_C(0xb0000000), false },
1158	{ UINT32_C(0xc0000000), false },
1159	{ UINT32_C(0xd0000000), false },
1160	{ UINT32_C(0xe0000000), false },
1161	{ UINT32_C(0xf0000000), false },
1162	};
1163
1164	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1165	{
1166	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1167	uint32_t uEax, uEbx, uEcx, uEdx;
1168	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1169
1170	/*
1171	* Does EAX look like a typical leaf count value?
1172	*/
1173	if ( uEax > uLeaf
1174	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1175	{
1176	/* Yes, dump them. */
1177	uint32_t cLeaves = uEax - uLeaf + 1;
1178	while (cLeaves-- > 0)
1179	{
1180	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1181
1182	uint32_t fFlags = 0;
1183
1184	/* There are currently three known leaves containing an APIC ID
1185	that needs EMT specific attention */
1186	if (uLeaf == 1)
1187	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1188	else if (uLeaf == 0xb && uEcx != 0)
1189	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1190	else if ( uLeaf == UINT32_C(0x8000001e)
1191	&& ( uEax
1192	\|\| uEbx
1193	\|\| uEdx
1194	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1195	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1196
1197	/* The APIC bit is per-VCpu and needs flagging. */
1198	if (uLeaf == 1)
1199	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1200	else if ( uLeaf == UINT32_C(0x80000001)
1201	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1202	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1203	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1204
1205	/* Check three times here to reduce the chance of CPU migration
1206	resulting in false positives with things like the APIC ID. */
1207	uint32_t cSubLeaves;
1208	bool fFinalEcxUnchanged;
1209	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1210	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1211	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1212	{
1213	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1214	{
1215	/* This shouldn't happen. But in case it does, file all
1216	relevant details in the release log. */
1217	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1218	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1219	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1220	{
1221	uint32_t auTmp[4];
1222	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1223	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1224	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1225	}
1226	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1227	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1228	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1229	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1230	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1231	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1232	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1233	}
1234
1235	if (fFinalEcxUnchanged)
1236	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1237
1238	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1239	{
1240	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1241	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1242	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1243	if (RT_FAILURE(rc))
1244	return rc;
1245	}
1246	}
1247	else
1248	{
1249	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1250	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1251	if (RT_FAILURE(rc))
1252	return rc;
1253	}
1254
1255	/* next */
1256	uLeaf++;
1257	}
1258	}
1259	/*
1260	* Special CPUIDs needs special handling as they don't follow the
1261	* leaf count principle used above.
1262	*/
1263	else if (s_aCandidates[iOuter].fSpecial)
1264	{
1265	bool fKeep = false;
1266	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1267	fKeep = true;
1268	else if ( uLeaf == 0x8fffffff
1269	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1270	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1271	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1272	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1273	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1274	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1275	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1276	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1277	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1278	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1279	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1280	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1281	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1282	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1283	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1284	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1285	fKeep = true;
1286	if (fKeep)
1287	{
1288	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1289	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1290	if (RT_FAILURE(rc))
1291	return rc;
1292	}
1293	}
1294	}
1295
1296	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1297	return VINF_SUCCESS;
1298	}
1299
1300
1301	/**
1302	* Determines the method the CPU uses to handle unknown CPUID leaves.
1303	*
1304	* @returns VBox status code.
1305	* @param penmUnknownMethod Where to return the method.
1306	* @param pDefUnknown Where to return default unknown values. This
1307	* will be set, even if the resulting method
1308	* doesn't actually needs it.
1309	*/
1310	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1311	{
1312	uint32_t uLastStd = ASMCpuId_EAX(0);
1313	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1314	if (!ASMIsValidExtRange(uLastExt))
1315	uLastExt = 0x80000000;
1316
1317	uint32_t auChecks[] =
1318	{
1319	uLastStd + 1,
1320	uLastStd + 5,
1321	uLastStd + 8,
1322	uLastStd + 32,
1323	uLastStd + 251,
1324	uLastExt + 1,
1325	uLastExt + 8,
1326	uLastExt + 15,
1327	uLastExt + 63,
1328	uLastExt + 255,
1329	0x7fbbffcc,
1330	0x833f7872,
1331	0xefff2353,
1332	0x35779456,
1333	0x1ef6d33e,
1334	};
1335
1336	static const uint32_t s_auValues[] =
1337	{
1338	0xa95d2156,
1339	0x00000001,
1340	0x00000002,
1341	0x00000008,
1342	0x00000000,
1343	0x55773399,
1344	0x93401769,
1345	0x12039587,
1346	};
1347
1348	/*
1349	* Simple method, all zeros.
1350	*/
1351	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1352	pDefUnknown->uEax = 0;
1353	pDefUnknown->uEbx = 0;
1354	pDefUnknown->uEcx = 0;
1355	pDefUnknown->uEdx = 0;
1356
1357	/*
1358	* Intel has been observed returning the last standard leaf.
1359	*/
1360	uint32_t auLast[4];
1361	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1362
1363	uint32_t cChecks = RT_ELEMENTS(auChecks);
1364	while (cChecks > 0)
1365	{
1366	uint32_t auCur[4];
1367	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1368	if (memcmp(auCur, auLast, sizeof(auCur)))
1369	break;
1370	cChecks--;
1371	}
1372	if (cChecks == 0)
1373	{
1374	/* Now, what happens when the input changes? Esp. ECX. */
1375	uint32_t cTotal = 0;
1376	uint32_t cSame = 0;
1377	uint32_t cLastWithEcx = 0;
1378	uint32_t cNeither = 0;
1379	uint32_t cValues = RT_ELEMENTS(s_auValues);
1380	while (cValues > 0)
1381	{
1382	uint32_t uValue = s_auValues[cValues - 1];
1383	uint32_t auLastWithEcx[4];
1384	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1385	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1386
1387	cChecks = RT_ELEMENTS(auChecks);
1388	while (cChecks > 0)
1389	{
1390	uint32_t auCur[4];
1391	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1392	if (!memcmp(auCur, auLast, sizeof(auCur)))
1393	{
1394	cSame++;
1395	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1396	cLastWithEcx++;
1397	}
1398	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1399	cLastWithEcx++;
1400	else
1401	cNeither++;
1402	cTotal++;
1403	cChecks--;
1404	}
1405	cValues--;
1406	}
1407
1408	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1409	if (cSame == cTotal)
1410	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1411	else if (cLastWithEcx == cTotal)
1412	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1413	else
1414	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1415	pDefUnknown->uEax = auLast[0];
1416	pDefUnknown->uEbx = auLast[1];
1417	pDefUnknown->uEcx = auLast[2];
1418	pDefUnknown->uEdx = auLast[3];
1419	return VINF_SUCCESS;
1420	}
1421
1422	/*
1423	* Unchanged register values?
1424	*/
1425	cChecks = RT_ELEMENTS(auChecks);
1426	while (cChecks > 0)
1427	{
1428	uint32_t const uLeaf = auChecks[cChecks - 1];
1429	uint32_t cValues = RT_ELEMENTS(s_auValues);
1430	while (cValues > 0)
1431	{
1432	uint32_t uValue = s_auValues[cValues - 1];
1433	uint32_t auCur[4];
1434	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1435	if ( auCur[0] != uLeaf
1436	\|\| auCur[1] != uValue
1437	\|\| auCur[2] != uValue
1438	\|\| auCur[3] != uValue)
1439	break;
1440	cValues--;
1441	}
1442	if (cValues != 0)
1443	break;
1444	cChecks--;
1445	}
1446	if (cChecks == 0)
1447	{
1448	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1449	return VINF_SUCCESS;
1450	}
1451
1452	/*
1453	* Just go with the simple method.
1454	*/
1455	return VINF_SUCCESS;
1456	}
1457
1458
1459	/**
1460	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1461	*
1462	* @returns Read only name string.
1463	* @param enmUnknownMethod The method to translate.
1464	*/
1465	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1466	{
1467	switch (enmUnknownMethod)
1468	{
1469	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1470	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1471	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1472	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1473
1474	case CPUMUNKNOWNCPUID_INVALID:
1475	case CPUMUNKNOWNCPUID_END:
1476	case CPUMUNKNOWNCPUID_32BIT_HACK:
1477	break;
1478	}
1479	return "Invalid-unknown-CPUID-method";
1480	}
1481
1482
1483	/**
1484	* Detect the CPU vendor give n the
1485	*
1486	* @returns The vendor.
1487	* @param uEAX EAX from CPUID(0).
1488	* @param uEBX EBX from CPUID(0).
1489	* @param uECX ECX from CPUID(0).
1490	* @param uEDX EDX from CPUID(0).
1491	*/
1492	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1493	{
1494	if (ASMIsValidStdRange(uEAX))
1495	{
1496	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1497	return CPUMCPUVENDOR_AMD;
1498
1499	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1500	return CPUMCPUVENDOR_INTEL;
1501
1502	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1503	return CPUMCPUVENDOR_VIA;
1504
1505	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1506	&& uECX == UINT32_C(0x64616574)
1507	&& uEDX == UINT32_C(0x736E4978))
1508	return CPUMCPUVENDOR_CYRIX;
1509
1510	/* "Geode by NSC", example: family 5, model 9. */
1511
1512	/** @todo detect the other buggers... */
1513	}
1514
1515	return CPUMCPUVENDOR_UNKNOWN;
1516	}
1517
1518
1519	/**
1520	* Translates a CPU vendor enum value into the corresponding string constant.
1521	*
1522	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1523	* value name. This can be useful when generating code.
1524	*
1525	* @returns Read only name string.
1526	* @param enmVendor The CPU vendor value.
1527	*/
1528	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1529	{
1530	switch (enmVendor)
1531	{
1532	case CPUMCPUVENDOR_INTEL: return "INTEL";
1533	case CPUMCPUVENDOR_AMD: return "AMD";
1534	case CPUMCPUVENDOR_VIA: return "VIA";
1535	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1536	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1537
1538	case CPUMCPUVENDOR_INVALID:
1539	case CPUMCPUVENDOR_32BIT_HACK:
1540	break;
1541	}
1542	return "Invalid-cpu-vendor";
1543	}
1544
1545
1546	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1547	{
1548	/* Could do binary search, doing linear now because I'm lazy. */
1549	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1550	while (cLeaves-- > 0)
1551	{
1552	if (pLeaf->uLeaf == uLeaf)
1553	return pLeaf;
1554	pLeaf++;
1555	}
1556	return NULL;
1557	}
1558
1559
1560	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1561	{
1562	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1563	if ( !pLeaf
1564	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1565	return pLeaf;
1566
1567	/* Linear sub-leaf search. Lazy as usual. */
1568	cLeaves -= pLeaf - paLeaves;
1569	while ( cLeaves-- > 0
1570	&& pLeaf->uLeaf == uLeaf)
1571	{
1572	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1573	return pLeaf;
1574	pLeaf++;
1575	}
1576
1577	return NULL;
1578	}
1579
1580
1581	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1582	{
1583	RT_ZERO(*pFeatures);
1584	if (cLeaves >= 2)
1585	{
1586	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1587	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1588	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1589	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1590	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1591	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1592
1593	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1594	pStd0Leaf->uEbx,
1595	pStd0Leaf->uEcx,
1596	pStd0Leaf->uEdx);
1597	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1598	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1599	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1600	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1601	pFeatures->uFamily,
1602	pFeatures->uModel,
1603	pFeatures->uStepping);
1604
1605	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1606	if (pLeaf)
1607	pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff;
1608	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1609	pFeatures->cMaxPhysAddrWidth = 36;
1610	else
1611	pFeatures->cMaxPhysAddrWidth = 32;
1612
1613	/* Standard features. */
1614	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1615	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1616	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1617	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1618	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1619	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1620	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1621	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1622	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1623	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1624	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1625	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1626	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1627	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1628	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1629	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1630	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1631	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1632	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1633	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1634	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1635	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1636	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1637
1638	/* Structured extended features. */
1639	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1640	if (pSxfLeaf0)
1641	{
1642	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEcx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1643	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEcx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1644	}
1645
1646	/* MWAIT/MONITOR leaf. */
1647	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1648	if (pMWaitLeaf)
1649	{
1650	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1651	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1652	}
1653
1654	/* Extended features. */
1655	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1656	if (pExtLeaf)
1657	{
1658	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1659	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1660	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1661	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1662	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1663	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1664	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1665	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1666	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1667	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1668	}
1669
1670	if ( pExtLeaf
1671	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1672	{
1673	/* AMD features. */
1674	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1675	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1676	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1677	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1678	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1679	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1680	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1681	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1682	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1683	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1684	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1685	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1686	if (pFeatures->fSvm)
1687	{
1688	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1689	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1690	pFeatures->svm.feat.u = pSvmLeaf->uEdx;
1691	pFeatures->svm.uMaxAsid = pSvmLeaf->uEbx;
1692	}
1693	}
1694
1695	/*
1696	* Quirks.
1697	*/
1698	pFeatures->fLeakyFxSR = pExtLeaf
1699	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1700	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1701	&& pFeatures->uFamily >= 6 /* K7 and up */;
1702
1703	/*
1704	* Max extended (/FPU) state.
1705	*/
1706	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1707	if (pFeatures->fXSaveRstor)
1708	{
1709	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1710	if (pXStateLeaf0)
1711	{
1712	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1713	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1714	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1715	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1716	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1717	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1718	{
1719	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1720
1721	/* (paranoia:) */
1722	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1723	if ( pXStateLeaf1
1724	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1725	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1726	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1727	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1728	}
1729	else
1730	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1731	pFeatures->fXSaveRstor = 0);
1732	}
1733	else
1734	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1735	pFeatures->fXSaveRstor = 0);
1736	}
1737	}
1738	else
1739	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1740	return VINF_SUCCESS;
1741	}
1742
1743
1744	/*
1745	*
1746	* Init related code.
1747	* Init related code.
1748	* Init related code.
1749	*
1750	*
1751	*/
1752	#ifdef VBOX_IN_VMM
1753
1754
1755	/**
1756	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1757	*
1758	* This ignores the fSubLeafMask.
1759	*
1760	* @returns Pointer to the matching leaf, or NULL if not found.
1761	* @param paLeaves The CPUID leaves to search. This is sorted.
1762	* @param cLeaves The number of leaves in the array.
1763	* @param uLeaf The leaf to locate.
1764	* @param uSubLeaf The subleaf to locate.
1765	*/
1766	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1767	{
1768	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1769	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1770	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1771	if (iEnd)
1772	{
1773	uint32_t iBegin = 0;
1774	for (;;)
1775	{
1776	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1777	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1778	if (uNeedle < uCur)
1779	{
1780	if (i > iBegin)
1781	iEnd = i;
1782	else
1783	break;
1784	}
1785	else if (uNeedle > uCur)
1786	{
1787	if (i + 1 < iEnd)
1788	iBegin = i + 1;
1789	else
1790	break;
1791	}
1792	else
1793	return &paLeaves[i];
1794	}
1795	}
1796	return NULL;
1797	}
1798
1799
1800	/**
1801	* Loads MSR range overrides.
1802	*
1803	* This must be called before the MSR ranges are moved from the normal heap to
1804	* the hyper heap!
1805	*
1806	* @returns VBox status code (VMSetError called).
1807	* @param pVM The cross context VM structure.
1808	* @param pMsrNode The CFGM node with the MSR overrides.
1809	*/
1810	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1811	{
1812	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1813	{
1814	/*
1815	* Assemble a valid MSR range.
1816	*/
1817	CPUMMSRRANGE MsrRange;
1818	MsrRange.offCpumCpu = 0;
1819	MsrRange.fReserved = 0;
1820
1821	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1822	if (RT_FAILURE(rc))
1823	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1824
1825	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1826	if (RT_FAILURE(rc))
1827	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1828	MsrRange.szName, rc);
1829
1830	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1831	if (RT_FAILURE(rc))
1832	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1833	MsrRange.szName, rc);
1834
1835	char szType[32];
1836	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1837	if (RT_FAILURE(rc))
1838	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1839	MsrRange.szName, rc);
1840	if (!RTStrICmp(szType, "FixedValue"))
1841	{
1842	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1843	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1844
1845	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1846	if (RT_FAILURE(rc))
1847	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1848	MsrRange.szName, rc);
1849
1850	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1851	if (RT_FAILURE(rc))
1852	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1853	MsrRange.szName, rc);
1854
1855	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1856	if (RT_FAILURE(rc))
1857	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1858	MsrRange.szName, rc);
1859	}
1860	else
1861	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1862	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1863
1864	/*
1865	* Insert the range into the table (replaces/splits/shrinks existing
1866	* MSR ranges).
1867	*/
1868	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1869	&MsrRange);
1870	if (RT_FAILURE(rc))
1871	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
1872	}
1873
1874	return VINF_SUCCESS;
1875	}
1876
1877
1878	/**
1879	* Loads CPUID leaf overrides.
1880	*
1881	* This must be called before the CPUID leaves are moved from the normal
1882	* heap to the hyper heap!
1883	*
1884	* @returns VBox status code (VMSetError called).
1885	* @param pVM The cross context VM structure.
1886	* @param pParentNode The CFGM node with the CPUID leaves.
1887	* @param pszLabel How to label the overrides we're loading.
1888	*/
1889	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
1890	{
1891	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1892	{
1893	/*
1894	* Get the leaf and subleaf numbers.
1895	*/
1896	char szName[128];
1897	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
1898	if (RT_FAILURE(rc))
1899	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
1900
1901	/* The leaf number is either specified directly or thru the node name. */
1902	uint32_t uLeaf;
1903	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
1904	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1905	{
1906	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
1907	if (rc != VINF_SUCCESS)
1908	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
1909	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
1910	}
1911	else if (RT_FAILURE(rc))
1912	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
1913	pszLabel, szName, rc);
1914
1915	uint32_t uSubLeaf;
1916	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
1917	if (RT_FAILURE(rc))
1918	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
1919	pszLabel, szName, rc);
1920
1921	uint32_t fSubLeafMask;
1922	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
1923	if (RT_FAILURE(rc))
1924	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
1925	pszLabel, szName, rc);
1926
1927	/*
1928	* Look up the specified leaf, since the output register values
1929	* defaults to any existing values. This allows overriding a single
1930	* register, without needing to know the other values.
1931	*/
1932	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
1933	CPUMCPUIDLEAF Leaf;
1934	if (pLeaf)
1935	Leaf = *pLeaf;
1936	else
1937	RT_ZERO(Leaf);
1938	Leaf.uLeaf = uLeaf;
1939	Leaf.uSubLeaf = uSubLeaf;
1940	Leaf.fSubLeafMask = fSubLeafMask;
1941
1942	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
1943	if (RT_FAILURE(rc))
1944	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
1945	pszLabel, szName, rc);
1946	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
1947	if (RT_FAILURE(rc))
1948	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
1949	pszLabel, szName, rc);
1950	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
1951	if (RT_FAILURE(rc))
1952	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
1953	pszLabel, szName, rc);
1954	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
1955	if (RT_FAILURE(rc))
1956	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
1957	pszLabel, szName, rc);
1958
1959	/*
1960	* Insert the leaf into the table (replaces existing ones).
1961	*/
1962	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1963	&Leaf);
1964	if (RT_FAILURE(rc))
1965	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
1966	}
1967
1968	return VINF_SUCCESS;
1969	}
1970
1971
1972
1973	/**
1974	* Fetches overrides for a CPUID leaf.
1975	*
1976	* @returns VBox status code.
1977	* @param pLeaf The leaf to load the overrides into.
1978	* @param pCfgNode The CFGM node containing the overrides
1979	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
1980	* @param iLeaf The CPUID leaf number.
1981	*/
1982	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
1983	{
1984	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
1985	if (pLeafNode)
1986	{
1987	uint32_t u32;
1988	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
1989	if (RT_SUCCESS(rc))
1990	pLeaf->uEax = u32;
1991	else
1992	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1993
1994	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
1995	if (RT_SUCCESS(rc))
1996	pLeaf->uEbx = u32;
1997	else
1998	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
1999
2000	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2001	if (RT_SUCCESS(rc))
2002	pLeaf->uEcx = u32;
2003	else
2004	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2005
2006	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2007	if (RT_SUCCESS(rc))
2008	pLeaf->uEdx = u32;
2009	else
2010	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2011
2012	}
2013	return VINF_SUCCESS;
2014	}
2015
2016
2017	/**
2018	* Load the overrides for a set of CPUID leaves.
2019	*
2020	* @returns VBox status code.
2021	* @param paLeaves The leaf array.
2022	* @param cLeaves The number of leaves.
2023	* @param uStart The start leaf number.
2024	* @param pCfgNode The CFGM node containing the overrides
2025	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2026	*/
2027	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2028	{
2029	for (uint32_t i = 0; i < cLeaves; i++)
2030	{
2031	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2032	if (RT_FAILURE(rc))
2033	return rc;
2034	}
2035
2036	return VINF_SUCCESS;
2037	}
2038
2039
2040	/**
2041	* Installs the CPUID leaves and explods the data into structures like
2042	* GuestFeatures and CPUMCTX::aoffXState.
2043	*
2044	* @returns VBox status code.
2045	* @param pVM The cross context VM structure.
2046	* @param pCpum The CPUM part of @a VM.
2047	* @param paLeaves The leaves. These will be copied (but not freed).
2048	* @param cLeaves The number of leaves.
2049	*/
2050	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
2051	{
2052	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2053
2054	/*
2055	* Install the CPUID information.
2056	*/
2057	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2058	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2059
2060	AssertLogRelRCReturn(rc, rc);
2061	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2062	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2063	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2064	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2065	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2066
2067	/*
2068	* Update the default CPUID leaf if necessary.
2069	*/
2070	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2071	{
2072	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2073	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2074	{
2075	/* We don't use CPUID(0).eax here because of the NT hack that only
2076	changes that value without actually removing any leaves. */
2077	uint32_t i = 0;
2078	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2079	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2080	{
2081	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2082	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2083	i++;
2084	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2085	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2086	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2087	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2088	}
2089	break;
2090	}
2091	default:
2092	break;
2093	}
2094
2095	/*
2096	* Explode the guest CPU features.
2097	*/
2098	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
2099	AssertLogRelRCReturn(rc, rc);
2100
2101	/*
2102	* Adjust the scalable bus frequency according to the CPUID information
2103	* we're now using.
2104	*/
2105	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2106	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2107	? UINT64_C(100000000) /* 100MHz */
2108	: UINT64_C(133333333); /* 133MHz */
2109
2110	/*
2111	* Populate the legacy arrays. Currently used for everything, later only
2112	* for patch manager.
2113	*/
2114	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2115	{
2116	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2117	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2118	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2119	};
2120	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2121	{
2122	uint32_t cLeft = aOldRanges[i].cCpuIds;
2123	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2124	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2125	while (cLeft-- > 0)
2126	{
2127	uLeaf--;
2128	pLegacyLeaf--;
2129
2130	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2131	if (pLeaf)
2132	{
2133	pLegacyLeaf->uEax = pLeaf->uEax;
2134	pLegacyLeaf->uEbx = pLeaf->uEbx;
2135	pLegacyLeaf->uEcx = pLeaf->uEcx;
2136	pLegacyLeaf->uEdx = pLeaf->uEdx;
2137	}
2138	else
2139	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2140	}
2141	}
2142
2143	/*
2144	* Configure XSAVE offsets according to the CPUID info.
2145	*/
2146	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2147	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2148	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2149	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2150	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2151	{
2152	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2153	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2154	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2155	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2156	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2157	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2158	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2159	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2160	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2161	pCpum->GuestFeatures.cbMaxExtendedState),
2162	VERR_CPUM_IPE_1);
2163	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2164	}
2165	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2166
2167	/* Copy the CPU #0 data to the other CPUs. */
2168	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2169	{
2170	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2171	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2172	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2173	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2174	}
2175
2176	return VINF_SUCCESS;
2177	}
2178
2179
2180	/** @name Instruction Set Extension Options
2181	* @{ */
2182	/** Configuration option type (extended boolean, really). */
2183	typedef uint8_t CPUMISAEXTCFG;
2184	/** Always disable the extension. */
2185	#define CPUMISAEXTCFG_DISABLED false
2186	/** Enable the extension if it's supported by the host CPU. */
2187	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2188	/** Enable the extension if it's supported by the host CPU, but don't let
2189	* the portable CPUID feature disable it. */
2190	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2191	/** Always enable the extension. */
2192	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2193	/** @} */
2194
2195	/**
2196	* CPUID Configuration (from CFGM).
2197	*
2198	* @remarks The members aren't document since we would only be duplicating the
2199	* \@cfgm entries in cpumR3CpuIdReadConfig.
2200	*/
2201	typedef struct CPUMCPUIDCONFIG
2202	{
2203	bool fNt4LeafLimit;
2204	bool fInvariantTsc;
2205
2206	CPUMISAEXTCFG enmCmpXchg16b;
2207	CPUMISAEXTCFG enmMonitor;
2208	CPUMISAEXTCFG enmMWaitExtensions;
2209	CPUMISAEXTCFG enmSse41;
2210	CPUMISAEXTCFG enmSse42;
2211	CPUMISAEXTCFG enmAvx;
2212	CPUMISAEXTCFG enmAvx2;
2213	CPUMISAEXTCFG enmXSave;
2214	CPUMISAEXTCFG enmAesNi;
2215	CPUMISAEXTCFG enmPClMul;
2216	CPUMISAEXTCFG enmPopCnt;
2217	CPUMISAEXTCFG enmMovBe;
2218	CPUMISAEXTCFG enmRdRand;
2219	CPUMISAEXTCFG enmRdSeed;
2220	CPUMISAEXTCFG enmCLFlushOpt;
2221
2222	CPUMISAEXTCFG enmAbm;
2223	CPUMISAEXTCFG enmSse4A;
2224	CPUMISAEXTCFG enmMisAlnSse;
2225	CPUMISAEXTCFG enm3dNowPrf;
2226	CPUMISAEXTCFG enmAmdExtMmx;
2227	CPUMISAEXTCFG enmSvm;
2228
2229	uint32_t uMaxStdLeaf;
2230	uint32_t uMaxExtLeaf;
2231	uint32_t uMaxCentaurLeaf;
2232	uint32_t uMaxIntelFamilyModelStep;
2233	char szCpuName[128];
2234	} CPUMCPUIDCONFIG;
2235	/** Pointer to CPUID config (from CFGM). */
2236	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2237
2238
2239	/**
2240	* Mini CPU selection support for making Mac OS X happy.
2241	*
2242	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2243	*
2244	* @param pCpum The CPUM instance data.
2245	* @param pConfig The CPUID configuration we've read from CFGM.
2246	*/
2247	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2248	{
2249	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2250	{
2251	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2252	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2253	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2254	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2255	0);
2256	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2257	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2258	{
2259	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2260	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2261	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2262	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2263	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2264	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2265	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2266	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2267	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2268	pStdFeatureLeaf->uEax = uNew;
2269	}
2270	}
2271	}
2272
2273
2274
2275	/**
2276	* Limit it the number of entries, zapping the remainder.
2277	*
2278	* The limits are masking off stuff about power saving and similar, this
2279	* is perhaps a bit crudely done as there is probably some relatively harmless
2280	* info too in these leaves (like words about having a constant TSC).
2281	*
2282	* @param pCpum The CPUM instance data.
2283	* @param pConfig The CPUID configuration we've read from CFGM.
2284	*/
2285	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2286	{
2287	/*
2288	* Standard leaves.
2289	*/
2290	uint32_t uSubLeaf = 0;
2291	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2292	if (pCurLeaf)
2293	{
2294	uint32_t uLimit = pCurLeaf->uEax;
2295	if (uLimit <= UINT32_C(0x000fffff))
2296	{
2297	if (uLimit > pConfig->uMaxStdLeaf)
2298	{
2299	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2300	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2301	uLimit + 1, UINT32_C(0x000fffff));
2302	}
2303
2304	/* NT4 hack, no zapping of extra leaves here. */
2305	if (pConfig->fNt4LeafLimit && uLimit > 3)
2306	pCurLeaf->uEax = uLimit = 3;
2307
2308	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2309	pCurLeaf->uEax = uLimit;
2310	}
2311	else
2312	{
2313	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2314	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2315	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2316	}
2317	}
2318
2319	/*
2320	* Extended leaves.
2321	*/
2322	uSubLeaf = 0;
2323	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2324	if (pCurLeaf)
2325	{
2326	uint32_t uLimit = pCurLeaf->uEax;
2327	if ( uLimit >= UINT32_C(0x80000000)
2328	&& uLimit <= UINT32_C(0x800fffff))
2329	{
2330	if (uLimit > pConfig->uMaxExtLeaf)
2331	{
2332	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2333	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2334	uLimit + 1, UINT32_C(0x800fffff));
2335	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2336	pCurLeaf->uEax = uLimit;
2337	}
2338	}
2339	else
2340	{
2341	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2342	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2343	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2344	}
2345	}
2346
2347	/*
2348	* Centaur leaves (VIA).
2349	*/
2350	uSubLeaf = 0;
2351	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2352	if (pCurLeaf)
2353	{
2354	uint32_t uLimit = pCurLeaf->uEax;
2355	if ( uLimit >= UINT32_C(0xc0000000)
2356	&& uLimit <= UINT32_C(0xc00fffff))
2357	{
2358	if (uLimit > pConfig->uMaxCentaurLeaf)
2359	{
2360	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2361	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2362	uLimit + 1, UINT32_C(0xcfffffff));
2363	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2364	pCurLeaf->uEax = uLimit;
2365	}
2366	}
2367	else
2368	{
2369	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2370	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2371	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2372	}
2373	}
2374	}
2375
2376
2377	/**
2378	* Clears a CPUID leaf and all sub-leaves (to zero).
2379	*
2380	* @param pCpum The CPUM instance data.
2381	* @param uLeaf The leaf to clear.
2382	*/
2383	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2384	{
2385	uint32_t uSubLeaf = 0;
2386	PCPUMCPUIDLEAF pCurLeaf;
2387	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2388	{
2389	pCurLeaf->uEax = 0;
2390	pCurLeaf->uEbx = 0;
2391	pCurLeaf->uEcx = 0;
2392	pCurLeaf->uEdx = 0;
2393	uSubLeaf++;
2394	}
2395	}
2396
2397
2398	/**
2399	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2400	* the given leaf.
2401	*
2402	* @returns pLeaf.
2403	* @param pCpum The CPUM instance data.
2404	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2405	*/
2406	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2407	{
2408	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2409	if (pLeaf->fSubLeafMask != 0)
2410	{
2411	/*
2412	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2413	* Log everything while we're at it.
2414	*/
2415	LogRel(("CPUM:\n"
2416	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2417	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2418	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2419	for (;;)
2420	{
2421	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2422	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2423	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2424	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2425	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2426	break;
2427	pSubLeaf++;
2428	}
2429	LogRel(("CPUM:\n"));
2430
2431	/*
2432	* Remove the offending sub-leaves.
2433	*/
2434	if (pSubLeaf != pLeaf)
2435	{
2436	if (pSubLeaf != pLast)
2437	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2438	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2439	}
2440
2441	/*
2442	* Convert the first sub-leaf into a single leaf.
2443	*/
2444	pLeaf->uSubLeaf = 0;
2445	pLeaf->fSubLeafMask = 0;
2446	}
2447	return pLeaf;
2448	}
2449
2450
2451	/**
2452	* Sanitizes and adjust the CPUID leaves.
2453	*
2454	* Drop features that aren't virtualized (or virtualizable). Adjust information
2455	* and capabilities to fit the virtualized hardware. Remove information the
2456	* guest shouldn't have (because it's wrong in the virtual world or because it
2457	* gives away host details) or that we don't have documentation for and no idea
2458	* what means.
2459	*
2460	* @returns VBox status code.
2461	* @param pVM The cross context VM structure (for cCpus).
2462	* @param pCpum The CPUM instance data.
2463	* @param pConfig The CPUID configuration we've read from CFGM.
2464	*/
2465	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2466	{
2467	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2468	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2469	{ \
2470	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2471	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2472	}
2473	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2474	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2475	{ \
2476	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2477	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2478	}
2479	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2480	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2481	&& ((a_pLeafReg) & (fBitMask)) \
2482	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2483	{ \
2484	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2485	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2486	}
2487	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2488
2489	/* Cpuid 1:
2490	* EAX: CPU model, family and stepping.
2491	*
2492	* ECX + EDX: Supported features. Only report features we can support.
2493	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2494	* options may require adjusting (i.e. stripping what was enabled).
2495	*
2496	* EBX: Branding, CLFLUSH line size, logical processors per package and
2497	* initial APIC ID.
2498	*/
2499	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2500	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2501	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2502
2503	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2504	\| X86_CPUID_FEATURE_EDX_VME
2505	\| X86_CPUID_FEATURE_EDX_DE
2506	\| X86_CPUID_FEATURE_EDX_PSE
2507	\| X86_CPUID_FEATURE_EDX_TSC
2508	\| X86_CPUID_FEATURE_EDX_MSR
2509	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2510	\| X86_CPUID_FEATURE_EDX_MCE
2511	\| X86_CPUID_FEATURE_EDX_CX8
2512	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2513	//\| RT_BIT_32(10) - not defined
2514	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2515	//\| X86_CPUID_FEATURE_EDX_SEP
2516	\| X86_CPUID_FEATURE_EDX_MTRR
2517	\| X86_CPUID_FEATURE_EDX_PGE
2518	\| X86_CPUID_FEATURE_EDX_MCA
2519	\| X86_CPUID_FEATURE_EDX_CMOV
2520	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2521	\| X86_CPUID_FEATURE_EDX_PSE36
2522	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2523	\| X86_CPUID_FEATURE_EDX_CLFSH
2524	//\| RT_BIT_32(20) - not defined
2525	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2526	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2527	\| X86_CPUID_FEATURE_EDX_MMX
2528	\| X86_CPUID_FEATURE_EDX_FXSR
2529	\| X86_CPUID_FEATURE_EDX_SSE
2530	\| X86_CPUID_FEATURE_EDX_SSE2
2531	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2532	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading/cores - see below.
2533	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2534	//\| RT_BIT_32(30) - not defined
2535	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2536	;
2537	pStdFeatureLeaf->uEcx &= 0
2538	\| X86_CPUID_FEATURE_ECX_SSE3
2539	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2540	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2541	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2542	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2543	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2544	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized yet.
2545	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2546	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2547	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2548	\| X86_CPUID_FEATURE_ECX_SSSE3
2549	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2550	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2551	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2552	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2553	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2554	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2555	//\| X86_CPUID_FEATURE_ECX_PCID - not implemented yet.
2556	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2557	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2558	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2559	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2560	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2561	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2562	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2563	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2564	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2565	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2566	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2567	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2568	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2569	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2570	;
2571
2572	if (pCpum->u8PortableCpuIdLevel > 0)
2573	{
2574	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2575	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2576	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2577	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2578	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2579	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2580	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2581	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2582	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2583	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2584	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2585	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2586	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2587	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2588	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2589	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2590	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2591	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2592
2593	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2594	\| X86_CPUID_FEATURE_EDX_PSN
2595	\| X86_CPUID_FEATURE_EDX_DS
2596	\| X86_CPUID_FEATURE_EDX_ACPI
2597	\| X86_CPUID_FEATURE_EDX_SS
2598	\| X86_CPUID_FEATURE_EDX_TM
2599	\| X86_CPUID_FEATURE_EDX_PBE
2600	)));
2601	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2602	\| X86_CPUID_FEATURE_ECX_CPLDS
2603	\| X86_CPUID_FEATURE_ECX_VMX
2604	\| X86_CPUID_FEATURE_ECX_SMX
2605	\| X86_CPUID_FEATURE_ECX_EST
2606	\| X86_CPUID_FEATURE_ECX_TM2
2607	\| X86_CPUID_FEATURE_ECX_CNTXID
2608	\| X86_CPUID_FEATURE_ECX_FMA
2609	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2610	\| X86_CPUID_FEATURE_ECX_PDCM
2611	\| X86_CPUID_FEATURE_ECX_DCA
2612	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2613	)));
2614	}
2615
2616	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2617	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2618	#ifdef VBOX_WITH_MULTI_CORE
2619	if (pVM->cCpus > 1)
2620	{
2621	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2622	core times the number of CPU cores per processor */
2623	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2624	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
2625	}
2626	#endif
2627
2628	/* Force standard feature bits. */
2629	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2630	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2631	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2632	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2633	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2634	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2635	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2636	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2637	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2638	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2639	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2640	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2641	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2642	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2643	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2644	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2645	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2646	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2647	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2648	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2649	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2650	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2651
2652	pStdFeatureLeaf = NULL; /* Must refetch! */
2653
2654	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2655	* AMD:
2656	* EAX: CPU model, family and stepping.
2657	*
2658	* ECX + EDX: Supported features. Only report features we can support.
2659	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2660	* options may require adjusting (i.e. stripping what was enabled).
2661	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2662	*
2663	* EBX: Branding ID and package type (or reserved).
2664	*
2665	* Intel and probably most others:
2666	* EAX: 0
2667	* EBX: 0
2668	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2669	*/
2670	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2671	if (pExtFeatureLeaf)
2672	{
2673	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2674
2675	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2676	\| X86_CPUID_AMD_FEATURE_EDX_VME
2677	\| X86_CPUID_AMD_FEATURE_EDX_DE
2678	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2679	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2680	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2681	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2682	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2683	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2684	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2685	//\| RT_BIT_32(10) - reserved
2686	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2687	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2688	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2689	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2690	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2691	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2692	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2693	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2694	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2695	//\| RT_BIT_32(18) - reserved
2696	//\| RT_BIT_32(19) - reserved
2697	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2698	//\| RT_BIT_32(21) - reserved
2699	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2700	\| X86_CPUID_AMD_FEATURE_EDX_MMX
2701	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
2702	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
2703	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2704	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2705	//\| RT_BIT_32(28) - reserved
2706	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2707	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2708	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
2709	;
2710	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2711	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2712	\| (pConfig->enmSvm ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
2713	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2714	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
2715	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2716	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2717	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2718	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2719	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2720	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2721	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
2722	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
2723	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2724	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
2725	//\| RT_BIT_32(14) - reserved
2726	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2727	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2728	//\| RT_BIT_32(17) - reserved
2729	//\| RT_BIT_32(18) - reserved
2730	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2731	//\| RT_BIT_32(20) - reserved
2732	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2733	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2734	//\| RT_BIT_32(23) - reserved
2735	//\| RT_BIT_32(24) - reserved
2736	//\| RT_BIT_32(25) - reserved
2737	//\| RT_BIT_32(26) - reserved
2738	//\| RT_BIT_32(27) - reserved
2739	//\| RT_BIT_32(28) - reserved
2740	//\| RT_BIT_32(29) - reserved
2741	//\| RT_BIT_32(30) - reserved
2742	//\| RT_BIT_32(31) - reserved
2743	;
2744	#ifdef VBOX_WITH_MULTI_CORE
2745	if ( pVM->cCpus > 1
2746	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2747	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2748	#endif
2749
2750	if (pCpum->u8PortableCpuIdLevel > 0)
2751	{
2752	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2753	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM, pConfig->enmSvm);
2754	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2755	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2756	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2757	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2758	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2759	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2760	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2761	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2762	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2763	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2764	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2765	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2766	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2767	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2768
2769	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2770	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2771	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2772	\| X86_CPUID_AMD_FEATURE_ECX_IBS
2773	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2774	\| X86_CPUID_AMD_FEATURE_ECX_WDT
2775	\| X86_CPUID_AMD_FEATURE_ECX_LWP
2776	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
2777	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2778	\| UINT32_C(0xff964000)
2779	)));
2780	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2781	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2782	\| RT_BIT(18)
2783	\| RT_BIT(19)
2784	\| RT_BIT(21)
2785	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2786	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2787	\| RT_BIT(28)
2788	)));
2789	}
2790
2791	/* Force extended feature bits. */
2792	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2793	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
2794	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2795	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2796	if (pConfig->enmSvm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2797	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SVM;
2798	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2799	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2800	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2801	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2802	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2803	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2804	if (pConfig->enmSvm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2805	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SVM;
2806	}
2807	pExtFeatureLeaf = NULL; /* Must refetch! */
2808
2809
2810	/* Cpuid 2:
2811	* Intel: (Nondeterministic) Cache and TLB information
2812	* AMD: Reserved
2813	* VIA: Reserved
2814	* Safe to expose.
2815	*/
2816	uint32_t uSubLeaf = 0;
2817	PCPUMCPUIDLEAF pCurLeaf;
2818	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2819	{
2820	if ((pCurLeaf->uEax & 0xff) > 1)
2821	{
2822	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2823	pCurLeaf->uEax &= UINT32_C(0xffffff01);
2824	}
2825	uSubLeaf++;
2826	}
2827
2828	/* Cpuid 3:
2829	* Intel: EAX, EBX - reserved (transmeta uses these)
2830	* ECX, EDX - Processor Serial Number if available, otherwise reserved
2831	* AMD: Reserved
2832	* VIA: Reserved
2833	* Safe to expose
2834	*/
2835	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2836	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
2837	{
2838	uSubLeaf = 0;
2839	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
2840	{
2841	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2842	if (pCpum->u8PortableCpuIdLevel > 0)
2843	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2844	uSubLeaf++;
2845	}
2846	}
2847
2848	/* Cpuid 4 + ECX:
2849	* Intel: Deterministic Cache Parameters Leaf.
2850	* AMD: Reserved
2851	* VIA: Reserved
2852	* Safe to expose, except for EAX:
2853	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
2854	* Bits 31-26: Maximum number of processor cores in this physical package**
2855	* Note: These SMP values are constant regardless of ECX
2856	*/
2857	uSubLeaf = 0;
2858	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
2859	{
2860	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
2861	#ifdef VBOX_WITH_MULTI_CORE
2862	if ( pVM->cCpus > 1
2863	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2864	{
2865	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
2866	/* One logical processor with possibly multiple cores. */
2867	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
2868	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
2869	}
2870	#endif
2871	uSubLeaf++;
2872	}
2873
2874	/* Cpuid 5: Monitor/mwait Leaf
2875	* Intel: ECX, EDX - reserved
2876	* EAX, EBX - Smallest and largest monitor line size
2877	* AMD: EDX - reserved
2878	* EAX, EBX - Smallest and largest monitor line size
2879	* ECX - extensions (ignored for now)
2880	* VIA: Reserved
2881	* Safe to expose
2882	*/
2883	uSubLeaf = 0;
2884	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
2885	{
2886	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2887	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
2888	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2889
2890	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2891	if (pConfig->enmMWaitExtensions)
2892	{
2893	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
2894	/** @todo for now we just expose host's MWAIT C-states, although conceptually
2895	it shall be part of our power management virtualization model */
2896	#if 0
2897	/* MWAIT sub C-states */
2898	pCurLeaf->uEdx =
2899	(0 << 0) /* 0 in C0 */ \|
2900	(2 << 4) /* 2 in C1 */ \|
2901	(2 << 8) /* 2 in C2 */ \|
2902	(2 << 12) /* 2 in C3 */ \|
2903	(0 << 16) /* 0 in C4 */
2904	;
2905	#endif
2906	}
2907	else
2908	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2909	uSubLeaf++;
2910	}
2911
2912	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
2913	* Intel: Various stuff.
2914	* AMD: EAX, EBX, EDX - reserved.
2915	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
2916	* present. Same as intel.
2917	* VIA: ??
2918	*
2919	* We clear everything here for now.
2920	*/
2921	cpumR3CpuIdZeroLeaf(pCpum, 6);
2922
2923	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
2924	* EAX: Number of sub leaves.
2925	* EBX+ECX+EDX: Feature flags
2926	*
2927	* We only have documentation for one sub-leaf, so clear all other (no need
2928	* to remove them as such, just set them to zero).
2929	*
2930	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2931	* options may require adjusting (i.e. stripping what was enabled).
2932	*/
2933	uSubLeaf = 0;
2934	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
2935	{
2936	switch (uSubLeaf)
2937	{
2938	case 0:
2939	{
2940	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
2941	pCurLeaf->uEbx &= 0
2942	//\| X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
2943	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
2944	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
2945	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
2946	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
2947	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
2948	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
2949	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
2950	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
2951	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
2952	//\| X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
2953	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
2954	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
2955	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
2956	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
2957	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
2958	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
2959	//\| RT_BIT(17) - reserved
2960	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
2961	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
2962	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
2963	//\| RT_BIT(21) - reserved
2964	//\| RT_BIT(22) - reserved
2965	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
2966	//\| RT_BIT(24) - reserved
2967	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
2968	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
2969	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
2970	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
2971	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
2972	//\| RT_BIT(30) - reserved
2973	//\| RT_BIT(31) - reserved
2974	;
2975	pCurLeaf->uEcx &= 0
2976	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
2977	;
2978	pCurLeaf->uEdx &= 0;
2979
2980	if (pCpum->u8PortableCpuIdLevel > 0)
2981	{
2982	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
2983	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
2984	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
2985	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
2986	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
2987	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
2988	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
2989	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
2990	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
2991	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
2992	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
2993	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
2994	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
2995	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
2996	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
2997	}
2998
2999	/* Force standard feature bits. */
3000	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3001	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3002	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3003	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3004	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3005	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3006	break;
3007	}
3008
3009	default:
3010	/* Invalid index, all values are zero. */
3011	pCurLeaf->uEax = 0;
3012	pCurLeaf->uEbx = 0;
3013	pCurLeaf->uEcx = 0;
3014	pCurLeaf->uEdx = 0;
3015	break;
3016	}
3017	uSubLeaf++;
3018	}
3019
3020	/* Cpuid 8: Marked as reserved by Intel and AMD.
3021	* We zero this since we don't know what it may have been used for.
3022	*/
3023	cpumR3CpuIdZeroLeaf(pCpum, 8);
3024
3025	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3026	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3027	* EBX, ECX, EDX - reserved.
3028	* AMD: Reserved
3029	* VIA: ??
3030	*
3031	* We zero this.
3032	*/
3033	cpumR3CpuIdZeroLeaf(pCpum, 9);
3034
3035	/* Cpuid 0xa: Architectural Performance Monitor Features
3036	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3037	* EBX, ECX, EDX - reserved.
3038	* AMD: Reserved
3039	* VIA: ??
3040	*
3041	* We zero this, for now at least.
3042	*/
3043	cpumR3CpuIdZeroLeaf(pCpum, 10);
3044
3045	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3046	* Intel: EAX - APCI ID shift right for next level.
3047	* EBX - Factory configured cores/threads at this level.
3048	* ECX - Level number (same as input) and level type (1,2,0).
3049	* EDX - Extended initial APIC ID.
3050	* AMD: Reserved
3051	* VIA: ??
3052	*/
3053	uSubLeaf = 0;
3054	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3055	{
3056	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3057	{
3058	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3059	if (bLevelType == 1)
3060	{
3061	/* Thread level - we don't do threads at the moment. */
3062	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3063	pCurLeaf->uEbx = 1;
3064	}
3065	else if (bLevelType == 2)
3066	{
3067	/* Core level. */
3068	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3069	#ifdef VBOX_WITH_MULTI_CORE
3070	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3071	pCurLeaf->uEax++;
3072	#endif
3073	pCurLeaf->uEbx = pVM->cCpus;
3074	}
3075	else
3076	{
3077	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3078	pCurLeaf->uEax = 0;
3079	pCurLeaf->uEbx = 0;
3080	pCurLeaf->uEcx = 0;
3081	}
3082	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3083	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3084	}
3085	else
3086	{
3087	pCurLeaf->uEax = 0;
3088	pCurLeaf->uEbx = 0;
3089	pCurLeaf->uEcx = 0;
3090	pCurLeaf->uEdx = 0;
3091	}
3092	uSubLeaf++;
3093	}
3094
3095	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3096	* We zero this since we don't know what it may have been used for.
3097	*/
3098	cpumR3CpuIdZeroLeaf(pCpum, 12);
3099
3100	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3101	* ECX=0: EAX - Valid bits in XCR0[31:0].
3102	* EBX - Maximum state size as per current XCR0 value.
3103	* ECX - Maximum state size for all supported features.
3104	* EDX - Valid bits in XCR0[63:32].
3105	* ECX=1: EAX - Various X-features.
3106	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3107	* ECX - Valid bits in IA32_XSS[31:0].
3108	* EDX - Valid bits in IA32_XSS[63:32].
3109	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3110	* if the bit invalid all four registers are set to zero.
3111	* EAX - The state size for this feature.
3112	* EBX - The state byte offset of this feature.
3113	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3114	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3115	*
3116	* Clear them all as we don't currently implement extended CPU state.
3117	*/
3118	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3119	uint64_t fGuestXcr0Mask = 0;
3120	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3121	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3122	{
3123	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3124	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3125	fGuestXcr0Mask \|= XSAVE_C_YMM;
3126	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3127	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3128	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3129	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3130
3131	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3132	}
3133	pStdFeatureLeaf = NULL;
3134	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3135
3136	/* Work the sub-leaves. */
3137	uint32_t cbXSaveMax = sizeof(X86FXSTATE);
3138	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3139	{
3140	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3141	if (pCurLeaf)
3142	{
3143	if (fGuestXcr0Mask)
3144	{
3145	switch (uSubLeaf)
3146	{
3147	case 0:
3148	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3149	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3150	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3151	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3152	VERR_CPUM_IPE_1);
3153	cbXSaveMax = pCurLeaf->uEcx;
3154	AssertLogRelMsgReturn(cbXSaveMax <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMax >= CPUM_MIN_XSAVE_AREA_SIZE,
3155	("%#x max=%#x\n", cbXSaveMax, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3156	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMax,
3157	("ebx=%#x cbXSaveMax=%#x\n", pCurLeaf->uEbx, cbXSaveMax),
3158	VERR_CPUM_IPE_2);
3159	continue;
3160	case 1:
3161	pCurLeaf->uEax &= 0;
3162	pCurLeaf->uEcx &= 0;
3163	pCurLeaf->uEdx &= 0;
3164	/** @todo what about checking ebx? */
3165	continue;
3166	default:
3167	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3168	{
3169	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMax
3170	&& pCurLeaf->uEax > 0
3171	&& pCurLeaf->uEbx < cbXSaveMax
3172	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3173	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMax,
3174	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3175	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMax),
3176	VERR_CPUM_IPE_2);
3177	AssertLogRel(!(pCurLeaf->uEcx & 1));
3178	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3179	pCurLeaf->uEdx = 0; /* it's reserved... */
3180	continue;
3181	}
3182	break;
3183	}
3184	}
3185
3186	/* Clear the leaf. */
3187	pCurLeaf->uEax = 0;
3188	pCurLeaf->uEbx = 0;
3189	pCurLeaf->uEcx = 0;
3190	pCurLeaf->uEdx = 0;
3191	}
3192	}
3193
3194	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3195	* We zero this since we don't know what it may have been used for.
3196	*/
3197	cpumR3CpuIdZeroLeaf(pCpum, 14);
3198
3199	/* Cpuid 0xf + ECX: Platform qualifity of service monitoring (PQM).
3200	* We zero this as we don't currently virtualize PQM.
3201	*/
3202	cpumR3CpuIdZeroLeaf(pCpum, 15);
3203
3204	/* Cpuid 0x10 + ECX: Platform qualifity of service enforcement (PQE).
3205	* We zero this as we don't currently virtualize PQE.
3206	*/
3207	cpumR3CpuIdZeroLeaf(pCpum, 16);
3208
3209	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3210	* We zero this since we don't know what it may have been used for.
3211	*/
3212	cpumR3CpuIdZeroLeaf(pCpum, 17);
3213
3214	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3215	* We zero this as we don't currently virtualize this.
3216	*/
3217	cpumR3CpuIdZeroLeaf(pCpum, 18);
3218
3219	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3220	* We zero this since we don't know what it may have been used for.
3221	*/
3222	cpumR3CpuIdZeroLeaf(pCpum, 19);
3223
3224	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3225	* We zero this as we don't currently virtualize this.
3226	*/
3227	cpumR3CpuIdZeroLeaf(pCpum, 20);
3228
3229	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3230	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3231	* EAX - denominator (unsigned).
3232	* EBX - numerator (unsigned).
3233	* ECX, EDX - reserved.
3234	* AMD: Reserved / undefined / not implemented.
3235	* VIA: Reserved / undefined / not implemented.
3236	* We zero this as we don't currently virtualize this.
3237	*/
3238	cpumR3CpuIdZeroLeaf(pCpum, 21);
3239
3240	/* Cpuid 0x16: Processor frequency info
3241	* Intel: EAX - Core base frequency in MHz.
3242	* EBX - Core maximum frequency in MHz.
3243	* ECX - Bus (reference) frequency in MHz.
3244	* EDX - Reserved.
3245	* AMD: Reserved / undefined / not implemented.
3246	* VIA: Reserved / undefined / not implemented.
3247	* We zero this as we don't currently virtualize this.
3248	*/
3249	cpumR3CpuIdZeroLeaf(pCpum, 22);
3250
3251	/* Cpuid 0x17..0x10000000: Unknown.
3252	* We don't know these and what they mean, so remove them. */
3253	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3254	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3255
3256
3257	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3258	* We remove all these as we're a hypervisor and must provide our own.
3259	*/
3260	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3261	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3262
3263
3264	/* Cpuid 0x80000000 is harmless. */
3265
3266	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3267
3268	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3269
3270	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3271	* Safe to pass on to the guest.
3272	*
3273	* AMD: 0x800000005 L1 cache information
3274	* 0x800000006 L2/L3 cache information
3275	* Intel: 0x800000005 reserved
3276	* 0x800000006 L2 cache information
3277	* VIA: 0x800000005 TLB and L1 cache information
3278	* 0x800000006 L2 cache information
3279	*/
3280
3281	/* Cpuid 0x800000007: Advanced Power Management Information.
3282	* AMD: EAX: Processor feedback capabilities.
3283	* EBX: RAS capabilites.
3284	* ECX: Advanced power monitoring interface.
3285	* EDX: Enhanced power management capabilities.
3286	* Intel: EAX, EBX, ECX - reserved.
3287	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3288	* VIA: Reserved
3289	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3290	*/
3291	uSubLeaf = 0;
3292	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3293	{
3294	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3295	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3296	{
3297	pCurLeaf->uEdx &= 0
3298	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3299	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3300	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3301	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3302	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3303	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3304	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3305	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3306	#if 0 /*
3307	* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
3308	* Linux kernels blindly assume that the AMD performance counters work
3309	* if this is set for 64 bits guests. (Can't really find a CPUID feature
3310	* bit for them though.)
3311	*/
3312	/** @todo need to recheck this with new MSR emulation. */
3313	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3314	#endif
3315	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3316	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3317	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3318	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3319	\| 0;
3320	}
3321	else
3322	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3323	if (pConfig->fInvariantTsc)
3324	pCurLeaf->uEdx \|= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3325	uSubLeaf++;
3326	}
3327
3328	/* Cpuid 0x80000008:
3329	* AMD: EBX, EDX - reserved
3330	* EAX: Virtual/Physical/Guest address Size
3331	* ECX: Number of cores + APICIdCoreIdSize
3332	* Intel: EAX: Virtual/Physical address Size
3333	* EBX, ECX, EDX - reserved
3334	* VIA: EAX: Virtual/Physical address Size
3335	* EBX, ECX, EDX - reserved
3336	*
3337	* We only expose the virtual+pysical address size to the guest atm.
3338	* On AMD we set the core count, but not the apic id stuff as we're
3339	* currently not doing the apic id assignments in a complatible manner.
3340	*/
3341	uSubLeaf = 0;
3342	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3343	{
3344	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3345	pCurLeaf->uEbx = 0; /* reserved */
3346	pCurLeaf->uEdx = 0; /* reserved */
3347
3348	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3349	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3350	pCurLeaf->uEcx = 0;
3351	#ifdef VBOX_WITH_MULTI_CORE
3352	if ( pVM->cCpus > 1
3353	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3354	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3355	#endif
3356	uSubLeaf++;
3357	}
3358
3359	/* Cpuid 0x80000009: Reserved
3360	* We zero this since we don't know what it may have been used for.
3361	*/
3362	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3363
3364	/* Cpuid 0x8000000a: SVM Information
3365	* AMD: EAX - SVM revision.
3366	* EBX - Number of ASIDs.
3367	* ECX - Reserved.
3368	* EDX - SVM Feature identification.
3369	*/
3370	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3371	if (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
3372	{
3373	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3374	pSvmFeatureLeaf->uEax = 0x1;
3375	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3376	pSvmFeatureLeaf->uEcx = 0;
3377	pSvmFeatureLeaf->uEdx = 0; /** @todo Support SVM features */
3378	}
3379	else
3380	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3381
3382	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3383	* We clear these as we don't know what purpose they might have. */
3384	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3385	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3386
3387	/* Cpuid 0x80000019: TLB configuration
3388	* Seems to be harmless, pass them thru as is. */
3389
3390	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3391	* Strip anything we don't know what is or addresses feature we don't implement. */
3392	uSubLeaf = 0;
3393	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3394	{
3395	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3396	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3397	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3398	;
3399	pCurLeaf->uEbx = 0; /* reserved */
3400	pCurLeaf->uEcx = 0; /* reserved */
3401	pCurLeaf->uEdx = 0; /* reserved */
3402	uSubLeaf++;
3403	}
3404
3405	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3406	* Clear this as we don't currently virtualize this feature. */
3407	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3408
3409	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3410	* Clear this as we don't currently virtualize this feature. */
3411	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3412
3413	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3414	* We need to sanitize the cores per cache (EAX[25:14]).
3415	*
3416	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3417	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3418	* slightly different meaning.
3419	*/
3420	uSubLeaf = 0;
3421	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3422	{
3423	#ifdef VBOX_WITH_MULTI_CORE
3424	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3425	if (cCores > pVM->cCpus)
3426	cCores = pVM->cCpus;
3427	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3428	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3429	#else
3430	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3431	#endif
3432	uSubLeaf++;
3433	}
3434
3435	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3436	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3437	* setup, we have one compute unit with all the cores in it. Single node.
3438	*/
3439	uSubLeaf = 0;
3440	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3441	{
3442	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3443	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3444	{
3445	#ifdef VBOX_WITH_MULTI_CORE
3446	pCurLeaf->uEbx = pVM->cCpus < 0x100
3447	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3448	#else
3449	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3450	#endif
3451	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3452	}
3453	else
3454	{
3455	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3456	pCurLeaf->uEbx = 0; /* Reserved. */
3457	pCurLeaf->uEcx = 0; /* Reserved. */
3458	}
3459	pCurLeaf->uEdx = 0; /* Reserved. */
3460	uSubLeaf++;
3461	}
3462
3463	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3464	* We don't know these and what they mean, so remove them. */
3465	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3466	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3467
3468	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3469	* Just pass it thru for now. */
3470
3471	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3472	* Just pass it thru for now. */
3473
3474	/* Cpuid 0xc0000000: Centaur stuff.
3475	* Harmless, pass it thru. */
3476
3477	/* Cpuid 0xc0000001: Centaur features.
3478	* VIA: EAX - Family, model, stepping.
3479	* EDX - Centaur extended feature flags. Nothing interesting, except may
3480	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3481	* EBX, ECX - reserved.
3482	* We keep EAX but strips the rest.
3483	*/
3484	uSubLeaf = 0;
3485	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3486	{
3487	pCurLeaf->uEbx = 0;
3488	pCurLeaf->uEcx = 0;
3489	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3490	uSubLeaf++;
3491	}
3492
3493	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3494	* We only have fixed stale values, but should be harmless. */
3495
3496	/* Cpuid 0xc0000003: Reserved.
3497	* We zero this since we don't know what it may have been used for.
3498	*/
3499	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3500
3501	/* Cpuid 0xc0000004: Centaur Performance Info.
3502	* We only have fixed stale values, but should be harmless. */
3503
3504
3505	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3506	* We don't know these and what they mean, so remove them. */
3507	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3508	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3509
3510	return VINF_SUCCESS;
3511	#undef PORTABLE_DISABLE_FEATURE_BIT
3512	#undef PORTABLE_CLEAR_BITS_WHEN
3513	}
3514
3515
3516	/**
3517	* Reads a value in /CPUM/IsaExts/ node.
3518	*
3519	* @returns VBox status code (error message raised).
3520	* @param pVM The cross context VM structure. (For errors.)
3521	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3522	* @param pszValueName The value / extension name.
3523	* @param penmValue Where to return the choice.
3524	* @param enmDefault The default choice.
3525	*/
3526	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3527	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3528	{
3529	/*
3530	* Try integer encoding first.
3531	*/
3532	uint64_t uValue;
3533	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3534	if (RT_SUCCESS(rc))
3535	switch (uValue)
3536	{
3537	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3538	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3539	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3540	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3541	default:
3542	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3543	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3544	pszValueName, uValue);
3545	}
3546	/*
3547	* If missing, use default.
3548	*/
3549	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3550	*penmValue = enmDefault;
3551	else
3552	{
3553	if (rc == VERR_CFGM_NOT_INTEGER)
3554	{
3555	/*
3556	* Not an integer, try read it as a string.
3557	*/
3558	char szValue[32];
3559	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3560	if (RT_SUCCESS(rc))
3561	{
3562	RTStrToLower(szValue);
3563	size_t cchValue = strlen(szValue);
3564	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3565	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3566	*penmValue = CPUMISAEXTCFG_DISABLED;
3567	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3568	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3569	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3570	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3571	else if (EQ("portable"))
3572	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3573	else if (EQ("default") \|\| EQ("def"))
3574	*penmValue = enmDefault;
3575	else
3576	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3577	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3578	pszValueName, uValue);
3579	#undef EQ
3580	}
3581	}
3582	if (RT_FAILURE(rc))
3583	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3584	}
3585	return VINF_SUCCESS;
3586	}
3587
3588
3589	/**
3590	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3591	*
3592	* @returns VBox status code (error message raised).
3593	* @param pVM The cross context VM structure. (For errors.)
3594	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3595	* @param pszValueName The value / extension name.
3596	* @param penmValue Where to return the choice.
3597	* @param enmDefault The default choice.
3598	* @param fAllowed Allowed choice. Applied both to the result and to
3599	* the default value.
3600	*/
3601	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3602	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3603	{
3604	int rc;
3605	if (fAllowed)
3606	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3607	else
3608	{
3609	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3610	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3611	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3612	*penmValue = CPUMISAEXTCFG_DISABLED;
3613	}
3614	return rc;
3615	}
3616
3617
3618	/**
3619	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3620	*
3621	* @returns VBox status code (error message raised).
3622	* @param pVM The cross context VM structure. (For errors.)
3623	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3624	* @param pCpumCfg The /CPUM node (can be NULL).
3625	* @param pszValueName The value / extension name.
3626	* @param penmValue Where to return the choice.
3627	* @param enmDefault The default choice.
3628	*/
3629	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3630	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3631	{
3632	if (CFGMR3Exists(pCpumCfg, pszValueName))
3633	{
3634	if (!CFGMR3Exists(pIsaExts, pszValueName))
3635	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3636	else
3637	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3638	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3639	pszValueName, pszValueName);
3640
3641	bool fLegacy;
3642	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3643	if (RT_SUCCESS(rc))
3644	{
3645	*penmValue = fLegacy;
3646	return VINF_SUCCESS;
3647	}
3648	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3649	}
3650
3651	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3652	}
3653
3654
3655	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3656	{
3657	int rc;
3658
3659	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3660	* When non-zero CPUID features that could cause portability issues will be
3661	* stripped. The higher the value the more features gets stripped. Higher
3662	* values should only be used when older CPUs are involved since it may
3663	* harm performance and maybe also cause problems with specific guests. */
3664	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
3665	AssertLogRelRCReturn(rc, rc);
3666
3667	/** @cfgm{/CPUM/GuestCpuName, string}
3668	* The name of the CPU we're to emulate. The default is the host CPU.
3669	* Note! CPUs other than "host" one is currently unsupported. */
3670	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3671	AssertLogRelRCReturn(rc, rc);
3672
3673	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3674	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3675	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3676	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3677	*/
3678	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3679	AssertLogRelRCReturn(rc, rc);
3680
3681	/** @cfgm{/CPUM/InvariantTsc, boolean, complicated}
3682	* Set the invariant TSC flag in 0x80000007 if true, otherwas take default
3683	* action. By default the flag is passed thru as is from the host CPU, except
3684	* on AMD CPUs where it's suppressed to avoid trouble from linux assuming we
3685	* virtualize performance counters.
3686	*/
3687	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, false);
3688	AssertLogRelRCReturn(rc, rc);
3689
3690	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3691	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
3692	* probably going to be a temporary hack, so don't depend on this.
3693	* The 1st byte of the value is the stepping, the 2nd byte value is the model
3694	* number and the 3rd byte value is the family, and the 4th value must be zero.
3695	*/
3696	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3697	AssertLogRelRCReturn(rc, rc);
3698
3699	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3700	* The last standard leaf to keep. The actual last value that is stored in EAX
3701	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3702	* removed. (This works independently of and differently from NT4LeafLimit.)
3703	* The default is usually set to what we're able to reasonably sanitize.
3704	*/
3705	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3706	AssertLogRelRCReturn(rc, rc);
3707
3708	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3709	* The last extended leaf to keep. The actual last value that is stored in EAX
3710	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3711	* leaf are removed. The default is set to what we're able to sanitize.
3712	*/
3713	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3714	AssertLogRelRCReturn(rc, rc);
3715
3716	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3717	* The last extended leaf to keep. The actual last value that is stored in EAX
3718	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3719	* leaf are removed. The default is set to what we're able to sanitize.
3720	*/
3721	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3722	AssertLogRelRCReturn(rc, rc);
3723
3724
3725	/*
3726	* Instruction Set Architecture (ISA) Extensions.
3727	*/
3728	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3729	if (pIsaExts)
3730	{
3731	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3732	"CMPXCHG16B"
3733	"\|MONITOR"
3734	"\|MWaitExtensions"
3735	"\|SSE4.1"
3736	"\|SSE4.2"
3737	"\|XSAVE"
3738	"\|AVX"
3739	"\|AVX2"
3740	"\|AESNI"
3741	"\|PCLMUL"
3742	"\|POPCNT"
3743	"\|MOVBE"
3744	"\|RDRAND"
3745	"\|RDSEED"
3746	"\|CLFLUSHOPT"
3747	"\|ABM"
3748	"\|SSE4A"
3749	"\|MISALNSSE"
3750	"\|3DNOWPRF"
3751	"\|AXMMX"
3752	"\|SVM"
3753	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
3754	if (RT_FAILURE(rc))
3755	return rc;
3756	}
3757
3758	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
3759	* Expose CMPXCHG16B to the guest if supported by the host. For the time
3760	* being the default is to only do this for VMs with nested paging and AMD-V or
3761	* unrestricted guest mode.
3762	*/
3763	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
3764	AssertLogRelRCReturn(rc, rc);
3765
3766	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
3767	* Expose MONITOR/MWAIT instructions to the guest.
3768	*/
3769	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
3770	AssertLogRelRCReturn(rc, rc);
3771
3772	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
3773	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
3774	* break on interrupt feature (bit 1).
3775	*/
3776	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
3777	AssertLogRelRCReturn(rc, rc);
3778
3779	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
3780	* Expose SSE4.1 to the guest if available.
3781	*/
3782	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
3783	AssertLogRelRCReturn(rc, rc);
3784
3785	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
3786	* Expose SSE4.2 to the guest if available.
3787	*/
3788	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
3789	AssertLogRelRCReturn(rc, rc);
3790
3791	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
3792	&& pVM->cpum.s.HostFeatures.fXSaveRstor
3793	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
3794	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
3795	&& !HMIsLongModeAllowed(pVM)
3796	#endif
3797	;
3798	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
3799
3800	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
3801	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
3802	* default is to only expose this to VMs with nested paging and AMD-V or
3803	* unrestricted guest execution mode. Not possible to force this one without
3804	* host support at the moment.
3805	*/
3806	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
3807	fMayHaveXSave /fAllowed/);
3808	AssertLogRelRCReturn(rc, rc);
3809
3810	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
3811	* Expose the AVX instruction set extensions to the guest if available and
3812	* XSAVE is exposed too. For the time being the default is to only expose this
3813	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3814	*/
3815	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
3816	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3817	AssertLogRelRCReturn(rc, rc);
3818
3819	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
3820	* Expose the AVX2 instruction set extensions to the guest if available and
3821	* XSAVE is exposed too. For the time being the default is to only expose this
3822	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3823	*/
3824	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec && false /* temporarily */,
3825	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3826	AssertLogRelRCReturn(rc, rc);
3827
3828	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
3829	* Whether to expose the AES instructions to the guest. For the time being the
3830	* default is to only do this for VMs with nested paging and AMD-V or
3831	* unrestricted guest mode.
3832	*/
3833	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
3834	AssertLogRelRCReturn(rc, rc);
3835
3836	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
3837	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
3838	* being the default is to only do this for VMs with nested paging and AMD-V or
3839	* unrestricted guest mode.
3840	*/
3841	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
3842	AssertLogRelRCReturn(rc, rc);
3843
3844	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
3845	* Whether to expose the POPCNT instructions to the guest. For the time
3846	* being the default is to only do this for VMs with nested paging and AMD-V or
3847	* unrestricted guest mode.
3848	*/
3849	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
3850	AssertLogRelRCReturn(rc, rc);
3851
3852	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
3853	* Whether to expose the MOVBE instructions to the guest. For the time
3854	* being the default is to only do this for VMs with nested paging and AMD-V or
3855	* unrestricted guest mode.
3856	*/
3857	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
3858	AssertLogRelRCReturn(rc, rc);
3859
3860	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
3861	* Whether to expose the RDRAND instructions to the guest. For the time being
3862	* the default is to only do this for VMs with nested paging and AMD-V or
3863	* unrestricted guest mode.
3864	*/
3865	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
3866	AssertLogRelRCReturn(rc, rc);
3867
3868	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
3869	* Whether to expose the RDSEED instructions to the guest. For the time being
3870	* the default is to only do this for VMs with nested paging and AMD-V or
3871	* unrestricted guest mode.
3872	*/
3873	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
3874	AssertLogRelRCReturn(rc, rc);
3875
3876	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
3877	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
3878	* being the default is to only do this for VMs with nested paging and AMD-V or
3879	* unrestricted guest mode.
3880	*/
3881	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
3882	AssertLogRelRCReturn(rc, rc);
3883
3884
3885	/* AMD: */
3886
3887	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
3888	* Whether to expose the AMD ABM instructions to the guest. For the time
3889	* being the default is to only do this for VMs with nested paging and AMD-V or
3890	* unrestricted guest mode.
3891	*/
3892	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
3893	AssertLogRelRCReturn(rc, rc);
3894
3895	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
3896	* Whether to expose the AMD SSE4A instructions to the guest. For the time
3897	* being the default is to only do this for VMs with nested paging and AMD-V or
3898	* unrestricted guest mode.
3899	*/
3900	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
3901	AssertLogRelRCReturn(rc, rc);
3902
3903	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
3904	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
3905	* the time being the default is to only do this for VMs with nested paging and
3906	* AMD-V or unrestricted guest mode.
3907	*/
3908	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
3909	AssertLogRelRCReturn(rc, rc);
3910
3911	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
3912	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
3913	* For the time being the default is to only do this for VMs with nested paging
3914	* and AMD-V or unrestricted guest mode.
3915	*/
3916	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
3917	AssertLogRelRCReturn(rc, rc);
3918
3919	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
3920	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
3921	* the default is to only do this for VMs with nested paging and AMD-V or
3922	* unrestricted guest mode.
3923	*/
3924	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
3925	AssertLogRelRCReturn(rc, rc);
3926
3927	#ifdef VBOX_WITH_NESTED_HWVIRT
3928	/** @cfgm{/CPUM/IsaExts/SVM, isaextcfg, depends}
3929	* Whether to expose the AMD's hardware virtualization (SVM) instructions to the
3930	* guest. For the time being, the default is to only do this for VMs with nested
3931	* paging and AMD-V.
3932	*/
3933	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SVM", &pConfig->enmSvm, fNestedPagingAndFullGuestExec);
3934	AssertLogRelRCReturn(rc, rc);
3935	#endif
3936
3937	return VINF_SUCCESS;
3938	}
3939
3940
3941	/**
3942	* Initializes the emulated CPU's CPUID & MSR information.
3943	*
3944	* @returns VBox status code.
3945	* @param pVM The cross context VM structure.
3946	*/
3947	int cpumR3InitCpuIdAndMsrs(PVM pVM)
3948	{
3949	PCPUM pCpum = &pVM->cpum.s;
3950	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
3951
3952	/*
3953	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
3954	* on construction and manage everything from here on.
3955	*/
3956	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
3957	pVM->aCpus[iCpu].cpum.s.fCpuIdApicFeatureVisible = true;
3958
3959	/*
3960	* Read the configuration.
3961	*/
3962	CPUMCPUIDCONFIG Config;
3963	RT_ZERO(Config);
3964
3965	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
3966	AssertRCReturn(rc, rc);
3967
3968	/*
3969	* Get the guest CPU data from the database and/or the host.
3970	*
3971	* The CPUID and MSRs are currently living on the regular heap to avoid
3972	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
3973	* API for the hyper heap). This means special cleanup considerations.
3974	*/
3975	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
3976	if (RT_FAILURE(rc))
3977	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
3978	? VMSetError(pVM, rc, RT_SRC_POS,
3979	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
3980	: rc;
3981
3982	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
3983	* Overrides the guest MSRs.
3984	*/
3985	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
3986
3987	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
3988	* Overrides the CPUID leaf values (from the host CPU usually) used for
3989	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
3990	* values when moving a VM to a different machine. Another use is restricting
3991	* (or extending) the feature set exposed to the guest. */
3992	if (RT_SUCCESS(rc))
3993	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
3994
3995	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
3996	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
3997	"Found unsupported configuration node '/CPUM/CPUID/'. "
3998	"Please use IMachine::setCPUIDLeaf() instead.");
3999
4000	/*
4001	* Pre-explode the CPUID info.
4002	*/
4003	if (RT_SUCCESS(rc))
4004	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
4005
4006	/*
4007	* Sanitize the cpuid information passed on to the guest.
4008	*/
4009	if (RT_SUCCESS(rc))
4010	{
4011	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4012	if (RT_SUCCESS(rc))
4013	{
4014	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4015	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4016	}
4017	}
4018
4019	/*
4020	* MSR fudging.
4021	*/
4022	if (RT_SUCCESS(rc))
4023	{
4024	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4025	* Fudges some common MSRs if not present in the selected CPU database entry.
4026	* This is for trying to keep VMs running when moved between different hosts
4027	* and different CPU vendors. */
4028	bool fEnable;
4029	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4030	if (RT_SUCCESS(rc) && fEnable)
4031	{
4032	rc = cpumR3MsrApplyFudge(pVM);
4033	AssertLogRelRC(rc);
4034	}
4035	}
4036	if (RT_SUCCESS(rc))
4037	{
4038	/*
4039	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4040	* guest CPU features again.
4041	*/
4042	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4043	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4044	pCpum->GuestInfo.cCpuIdLeaves);
4045	RTMemFree(pvFree);
4046
4047	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4048	int rc2 = MMHyperDupMem(pVM, pvFree,
4049	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4050	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4051	RTMemFree(pvFree);
4052	AssertLogRelRCReturn(rc1, rc1);
4053	AssertLogRelRCReturn(rc2, rc2);
4054
4055	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4056	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4057
4058
4059	/*
4060	* Some more configuration that we're applying at the end of everything
4061	* via the CPUMSetGuestCpuIdFeature API.
4062	*/
4063
4064	/* Check if PAE was explicitely enabled by the user. */
4065	bool fEnable;
4066	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4067	AssertRCReturn(rc, rc);
4068	if (fEnable)
4069	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4070
4071	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4072	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4073	AssertRCReturn(rc, rc);
4074	if (fEnable)
4075	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4076
4077	return VINF_SUCCESS;
4078	}
4079
4080	/*
4081	* Failed before switching to hyper heap.
4082	*/
4083	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4084	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4085	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4086	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4087	return rc;
4088	}
4089
4090
4091	/**
4092	* Sets a CPUID feature bit during VM initialization.
4093	*
4094	* Since the CPUID feature bits are generally related to CPU features, other
4095	* CPUM configuration like MSRs can also be modified by calls to this API.
4096	*
4097	* @param pVM The cross context VM structure.
4098	* @param enmFeature The feature to set.
4099	*/
4100	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4101	{
4102	PCPUMCPUIDLEAF pLeaf;
4103	PCPUMMSRRANGE pMsrRange;
4104
4105	switch (enmFeature)
4106	{
4107	/*
4108	* Set the APIC bit in both feature masks.
4109	*/
4110	case CPUMCPUIDFEATURE_APIC:
4111	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4112	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4113	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4114
4115	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4116	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4117	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4118
4119	pVM->cpum.s.GuestFeatures.fApic = 1;
4120
4121	/* Make sure we've got the APICBASE MSR present. */
4122	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4123	if (!pMsrRange)
4124	{
4125	static CPUMMSRRANGE const s_ApicBase =
4126	{
4127	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4128	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4129	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4130	/.szName = / "IA32_APIC_BASE"
4131	};
4132	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4133	AssertLogRelRC(rc);
4134	}
4135
4136	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4137	break;
4138
4139	/*
4140	* Set the x2APIC bit in the standard feature mask.
4141	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4142	*/
4143	case CPUMCPUIDFEATURE_X2APIC:
4144	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4145	if (pLeaf)
4146	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4147	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4148
4149	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4150	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4151	if (pMsrRange)
4152	{
4153	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4154	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4155	}
4156
4157	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4158	break;
4159
4160	/*
4161	* Set the sysenter/sysexit bit in the standard feature mask.
4162	* Assumes the caller knows what it's doing! (host must support these)
4163	*/
4164	case CPUMCPUIDFEATURE_SEP:
4165	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4166	{
4167	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4168	return;
4169	}
4170
4171	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4172	if (pLeaf)
4173	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4174	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4175	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4176	break;
4177
4178	/*
4179	* Set the syscall/sysret bit in the extended feature mask.
4180	* Assumes the caller knows what it's doing! (host must support these)
4181	*/
4182	case CPUMCPUIDFEATURE_SYSCALL:
4183	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4184	if ( !pLeaf
4185	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4186	{
4187	#if HC_ARCH_BITS == 32
4188	/* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit
4189	mode by Intel, even when the cpu is capable of doing so in
4190	64-bit mode. Long mode requires syscall support. */
4191	if (!pVM->cpum.s.HostFeatures.fLongMode)
4192	#endif
4193	{
4194	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4195	return;
4196	}
4197	}
4198
4199	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4200	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4201	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4202	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4203	break;
4204
4205	/*
4206	* Set the PAE bit in both feature masks.
4207	* Assumes the caller knows what it's doing! (host must support these)
4208	*/
4209	case CPUMCPUIDFEATURE_PAE:
4210	if (!pVM->cpum.s.HostFeatures.fPae)
4211	{
4212	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4213	return;
4214	}
4215
4216	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4217	if (pLeaf)
4218	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4219
4220	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4221	if ( pLeaf
4222	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4223	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4224
4225	pVM->cpum.s.GuestFeatures.fPae = 1;
4226	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4227	break;
4228
4229	/*
4230	* Set the LONG MODE bit in the extended feature mask.
4231	* Assumes the caller knows what it's doing! (host must support these)
4232	*/
4233	case CPUMCPUIDFEATURE_LONG_MODE:
4234	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4235	if ( !pLeaf
4236	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4237	{
4238	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4239	return;
4240	}
4241
4242	/* Valid for both Intel and AMD. */
4243	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4244	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4245	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4246	break;
4247
4248	/*
4249	* Set the NX/XD bit in the extended feature mask.
4250	* Assumes the caller knows what it's doing! (host must support these)
4251	*/
4252	case CPUMCPUIDFEATURE_NX:
4253	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4254	if ( !pLeaf
4255	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4256	{
4257	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4258	return;
4259	}
4260
4261	/* Valid for both Intel and AMD. */
4262	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4263	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4264	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4265	break;
4266
4267
4268	/*
4269	* Set the LAHF/SAHF support in 64-bit mode.
4270	* Assumes the caller knows what it's doing! (host must support this)
4271	*/
4272	case CPUMCPUIDFEATURE_LAHF:
4273	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4274	if ( !pLeaf
4275	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4276	{
4277	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4278	return;
4279	}
4280
4281	/* Valid for both Intel and AMD. */
4282	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4283	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4284	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4285	break;
4286
4287	/*
4288	* Set the page attribute table bit. This is alternative page level
4289	* cache control that doesn't much matter when everything is
4290	* virtualized, though it may when passing thru device memory.
4291	*/
4292	case CPUMCPUIDFEATURE_PAT:
4293	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4294	if (pLeaf)
4295	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4296
4297	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4298	if ( pLeaf
4299	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4300	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4301
4302	pVM->cpum.s.GuestFeatures.fPat = 1;
4303	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4304	break;
4305
4306	/*
4307	* Set the RDTSCP support bit.
4308	* Assumes the caller knows what it's doing! (host must support this)
4309	*/
4310	case CPUMCPUIDFEATURE_RDTSCP:
4311	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4312	if ( !pLeaf
4313	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4314	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4315	{
4316	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4317	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4318	return;
4319	}
4320
4321	/* Valid for both Intel and AMD. */
4322	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4323	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4324	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4325	break;
4326
4327	/*
4328	* Set the Hypervisor Present bit in the standard feature mask.
4329	*/
4330	case CPUMCPUIDFEATURE_HVP:
4331	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4332	if (pLeaf)
4333	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4334	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4335	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4336	break;
4337
4338	/*
4339	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4340	* This currently includes the Present bit and MWAITBREAK bit as well.
4341	*/
4342	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4343	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4344	if ( !pLeaf
4345	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4346	{
4347	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4348	return;
4349	}
4350
4351	/* Valid for both Intel and AMD. */
4352	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4353	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4354	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4355	break;
4356
4357	default:
4358	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4359	break;
4360	}
4361
4362	/** @todo can probably kill this as this API is now init time only... */
4363	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4364	{
4365	PVMCPU pVCpu = &pVM->aCpus[i];
4366	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4367	}
4368	}
4369
4370
4371	/**
4372	* Queries a CPUID feature bit.
4373	*
4374	* @returns boolean for feature presence
4375	* @param pVM The cross context VM structure.
4376	* @param enmFeature The feature to query.
4377	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4378	*/
4379	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4380	{
4381	switch (enmFeature)
4382	{
4383	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4384	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4385	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4386	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4387	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4388	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4389	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4390	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4391	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4392	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4393	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4394	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4395
4396	case CPUMCPUIDFEATURE_INVALID:
4397	case CPUMCPUIDFEATURE_32BIT_HACK:
4398	break;
4399	}
4400	AssertFailed();
4401	return false;
4402	}
4403
4404
4405	/**
4406	* Clears a CPUID feature bit.
4407	*
4408	* @param pVM The cross context VM structure.
4409	* @param enmFeature The feature to clear.
4410	*
4411	* @deprecated Probably better to default the feature to disabled and only allow
4412	* setting (enabling) it during construction.
4413	*/
4414	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4415	{
4416	PCPUMCPUIDLEAF pLeaf;
4417	switch (enmFeature)
4418	{
4419	case CPUMCPUIDFEATURE_APIC:
4420	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
4421	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4422	if (pLeaf)
4423	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
4424
4425	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4426	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4427	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4428
4429	pVM->cpum.s.GuestFeatures.fApic = 0;
4430	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4431	break;
4432
4433	case CPUMCPUIDFEATURE_X2APIC:
4434	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4435	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4436	if (pLeaf)
4437	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
4438	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
4439	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
4440	break;
4441
4442	case CPUMCPUIDFEATURE_PAE:
4443	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4444	if (pLeaf)
4445	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
4446
4447	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4448	if ( pLeaf
4449	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4450	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
4451
4452	pVM->cpum.s.GuestFeatures.fPae = 0;
4453	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
4454	break;
4455
4456	case CPUMCPUIDFEATURE_PAT:
4457	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4458	if (pLeaf)
4459	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
4460
4461	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4462	if ( pLeaf
4463	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4464	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
4465
4466	pVM->cpum.s.GuestFeatures.fPat = 0;
4467	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
4468	break;
4469
4470	case CPUMCPUIDFEATURE_LONG_MODE:
4471	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4472	if (pLeaf)
4473	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4474	pVM->cpum.s.GuestFeatures.fLongMode = 0;
4475	break;
4476
4477	case CPUMCPUIDFEATURE_LAHF:
4478	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4479	if (pLeaf)
4480	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4481	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
4482	break;
4483
4484	case CPUMCPUIDFEATURE_RDTSCP:
4485	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4486	if (pLeaf)
4487	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4488	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
4489	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
4490	break;
4491
4492	case CPUMCPUIDFEATURE_HVP:
4493	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4494	if (pLeaf)
4495	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
4496	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
4497	break;
4498
4499	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4500	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4501	if (pLeaf)
4502	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
4503	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
4504	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
4505	break;
4506
4507	default:
4508	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4509	break;
4510	}
4511
4512	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4513	{
4514	PVMCPU pVCpu = &pVM->aCpus[i];
4515	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4516	}
4517	}
4518
4519
4520
4521	/*
4522	*
4523	*
4524	* Saved state related code.
4525	* Saved state related code.
4526	* Saved state related code.
4527	*
4528	*
4529	*/
4530
4531	/**
4532	* Called both in pass 0 and the final pass.
4533	*
4534	* @param pVM The cross context VM structure.
4535	* @param pSSM The saved state handle.
4536	*/
4537	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4538	{
4539	/*
4540	* Save all the CPU ID leaves.
4541	*/
4542	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4543	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4544	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4545	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4546
4547	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4548
4549	/*
4550	* Save a good portion of the raw CPU IDs as well as they may come in
4551	* handy when validating features for raw mode.
4552	*/
4553	CPUMCPUID aRawStd[16];
4554	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4555	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4556	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4557	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4558
4559	CPUMCPUID aRawExt[32];
4560	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4561	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4562	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4563	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4564	}
4565
4566
4567	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4568	{
4569	uint32_t cCpuIds;
4570	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4571	if (RT_SUCCESS(rc))
4572	{
4573	if (cCpuIds < 64)
4574	{
4575	for (uint32_t i = 0; i < cCpuIds; i++)
4576	{
4577	CPUMCPUID CpuId;
4578	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4579	if (RT_FAILURE(rc))
4580	break;
4581
4582	CPUMCPUIDLEAF NewLeaf;
4583	NewLeaf.uLeaf = uBase + i;
4584	NewLeaf.uSubLeaf = 0;
4585	NewLeaf.fSubLeafMask = 0;
4586	NewLeaf.uEax = CpuId.uEax;
4587	NewLeaf.uEbx = CpuId.uEbx;
4588	NewLeaf.uEcx = CpuId.uEcx;
4589	NewLeaf.uEdx = CpuId.uEdx;
4590	NewLeaf.fFlags = 0;
4591	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4592	}
4593	}
4594	else
4595	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4596	}
4597	if (RT_FAILURE(rc))
4598	{
4599	RTMemFree(*ppaLeaves);
4600	*ppaLeaves = NULL;
4601	*pcLeaves = 0;
4602	}
4603	return rc;
4604	}
4605
4606
4607	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4608	{
4609	*ppaLeaves = NULL;
4610	*pcLeaves = 0;
4611
4612	int rc;
4613	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4614	{
4615	/*
4616	* The new format. Starts by declaring the leave size and count.
4617	*/
4618	uint32_t cbLeaf;
4619	SSMR3GetU32(pSSM, &cbLeaf);
4620	uint32_t cLeaves;
4621	rc = SSMR3GetU32(pSSM, &cLeaves);
4622	if (RT_SUCCESS(rc))
4623	{
4624	if (cbLeaf == sizeof(**ppaLeaves))
4625	{
4626	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4627	{
4628	/*
4629	* Load the leaves one by one.
4630	*
4631	* The uPrev stuff is a kludge for working around a week worth of bad saved
4632	* states during the CPUID revamp in March 2015. We saved too many leaves
4633	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4634	* garbage entires at the end of the array when restoring. We also had
4635	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
4636	* this kludge doesn't deal correctly with that, but who cares...
4637	*/
4638	uint32_t uPrev = 0;
4639	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4640	{
4641	CPUMCPUIDLEAF Leaf;
4642	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
4643	if (RT_SUCCESS(rc))
4644	{
4645	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
4646	\|\| Leaf.uLeaf >= uPrev)
4647	{
4648	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4649	uPrev = Leaf.uLeaf;
4650	}
4651	else
4652	uPrev = UINT32_MAX;
4653	}
4654	}
4655	}
4656	else
4657	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
4658	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
4659	}
4660	else
4661	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
4662	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
4663	}
4664	}
4665	else
4666	{
4667	/*
4668	* The old format with its three inflexible arrays.
4669	*/
4670	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
4671	if (RT_SUCCESS(rc))
4672	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
4673	if (RT_SUCCESS(rc))
4674	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
4675	if (RT_SUCCESS(rc))
4676	{
4677	/*
4678	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
4679	*/
4680	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
4681	if ( pLeaf
4682	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
4683	{
4684	CPUMCPUIDLEAF Leaf;
4685	Leaf.uLeaf = 4;
4686	Leaf.fSubLeafMask = UINT32_MAX;
4687	Leaf.uSubLeaf = 0;
4688	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
4689	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
4690	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
4691	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
4692	\| UINT32_C(63); /* system coherency line size - 1 */
4693	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
4694	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
4695	\| (UINT32_C(1) << 5) /* cache level */
4696	\| UINT32_C(1); /* cache type (data) */
4697	Leaf.fFlags = 0;
4698	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4699	if (RT_SUCCESS(rc))
4700	{
4701	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
4702	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4703	}
4704	if (RT_SUCCESS(rc))
4705	{
4706	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
4707	Leaf.uEcx = 4095; /* sets - 1 */
4708	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
4709	Leaf.uEbx \|= UINT32_C(23) << 22;
4710	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
4711	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
4712	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
4713	Leaf.uEax \|= UINT32_C(2) << 5;
4714	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4715	}
4716	}
4717	}
4718	}
4719	return rc;
4720	}
4721
4722
4723	/**
4724	* Loads the CPU ID leaves saved by pass 0, inner worker.
4725	*
4726	* @returns VBox status code.
4727	* @param pVM The cross context VM structure.
4728	* @param pSSM The saved state handle.
4729	* @param uVersion The format version.
4730	* @param paLeaves Guest CPUID leaves loaded from the state.
4731	* @param cLeaves The number of leaves in @a paLeaves.
4732	*/
4733	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
4734	{
4735	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4736
4737	/*
4738	* Continue loading the state into stack buffers.
4739	*/
4740	CPUMCPUID GuestDefCpuId;
4741	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
4742	AssertRCReturn(rc, rc);
4743
4744	CPUMCPUID aRawStd[16];
4745	uint32_t cRawStd;
4746	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
4747	if (cRawStd > RT_ELEMENTS(aRawStd))
4748	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4749	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
4750	AssertRCReturn(rc, rc);
4751	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
4752	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4753
4754	CPUMCPUID aRawExt[32];
4755	uint32_t cRawExt;
4756	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
4757	if (cRawExt > RT_ELEMENTS(aRawExt))
4758	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4759	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
4760	AssertRCReturn(rc, rc);
4761	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
4762	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4763
4764	/*
4765	* Get the raw CPU IDs for the current host.
4766	*/
4767	CPUMCPUID aHostRawStd[16];
4768	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
4769	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
4770
4771	CPUMCPUID aHostRawExt[32];
4772	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
4773	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
4774	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4775
4776	/*
4777	* Get the host and guest overrides so we don't reject the state because
4778	* some feature was enabled thru these interfaces.
4779	* Note! We currently only need the feature leaves, so skip rest.
4780	*/
4781	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4782	CPUMCPUID aHostOverrideStd[2];
4783	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4784	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4785
4786	CPUMCPUID aHostOverrideExt[2];
4787	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4788	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4789
4790	/*
4791	* This can be skipped.
4792	*/
4793	bool fStrictCpuIdChecks;
4794	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
4795
4796	/*
4797	* Define a bunch of macros for simplifying the santizing/checking code below.
4798	*/
4799	/* Generic expression + failure message. */
4800	#define CPUID_CHECK_RET(expr, fmt) \
4801	do { \
4802	if (!(expr)) \
4803	{ \
4804	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
4805	if (fStrictCpuIdChecks) \
4806	{ \
4807	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4808	RTStrFree(pszMsg); \
4809	return rcCpuid; \
4810	} \
4811	LogRel(("CPUM: %s\n", pszMsg)); \
4812	RTStrFree(pszMsg); \
4813	} \
4814	} while (0)
4815	#define CPUID_CHECK_WRN(expr, fmt) \
4816	do { \
4817	if (!(expr)) \
4818	LogRel(fmt); \
4819	} while (0)
4820
4821	/* For comparing two values and bitch if they differs. */
4822	#define CPUID_CHECK2_RET(what, host, saved) \
4823	do { \
4824	if ((host) != (saved)) \
4825	{ \
4826	if (fStrictCpuIdChecks) \
4827	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4828	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
4829	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4830	} \
4831	} while (0)
4832	#define CPUID_CHECK2_WRN(what, host, saved) \
4833	do { \
4834	if ((host) != (saved)) \
4835	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4836	} while (0)
4837
4838	/* For checking raw cpu features (raw mode). */
4839	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
4840	do { \
4841	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4842	{ \
4843	if (fStrictCpuIdChecks) \
4844	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4845	N_(#bit " mismatch: host=%d saved=%d"), \
4846	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
4847	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4848	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4849	} \
4850	} while (0)
4851	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
4852	do { \
4853	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4854	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4855	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4856	} while (0)
4857	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
4858
4859	/* For checking guest features. */
4860	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
4861	do { \
4862	if ( (aGuestCpuId##set [1].reg & bit) \
4863	&& !(aHostRaw##set [1].reg & bit) \
4864	&& !(aHostOverride##set [1].reg & bit) \
4865	) \
4866	{ \
4867	if (fStrictCpuIdChecks) \
4868	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4869	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4870	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4871	} \
4872	} while (0)
4873	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
4874	do { \
4875	if ( (aGuestCpuId##set [1].reg & bit) \
4876	&& !(aHostRaw##set [1].reg & bit) \
4877	&& !(aHostOverride##set [1].reg & bit) \
4878	) \
4879	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4880	} while (0)
4881	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
4882	do { \
4883	if ( (aGuestCpuId##set [1].reg & bit) \
4884	&& !(aHostRaw##set [1].reg & bit) \
4885	&& !(aHostOverride##set [1].reg & bit) \
4886	) \
4887	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4888	} while (0)
4889	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
4890
4891	/* For checking guest features if AMD guest CPU. */
4892	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
4893	do { \
4894	if ( (aGuestCpuId##set [1].reg & bit) \
4895	&& fGuestAmd \
4896	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4897	&& !(aHostOverride##set [1].reg & bit) \
4898	) \
4899	{ \
4900	if (fStrictCpuIdChecks) \
4901	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4902	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4903	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4904	} \
4905	} while (0)
4906	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
4907	do { \
4908	if ( (aGuestCpuId##set [1].reg & bit) \
4909	&& fGuestAmd \
4910	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4911	&& !(aHostOverride##set [1].reg & bit) \
4912	) \
4913	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4914	} while (0)
4915	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
4916	do { \
4917	if ( (aGuestCpuId##set [1].reg & bit) \
4918	&& fGuestAmd \
4919	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4920	&& !(aHostOverride##set [1].reg & bit) \
4921	) \
4922	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4923	} while (0)
4924	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
4925
4926	/* For checking AMD features which have a corresponding bit in the standard
4927	range. (Intel defines very few bits in the extended feature sets.) */
4928	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
4929	do { \
4930	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4931	&& !(fHostAmd \
4932	? aHostRawExt[1].reg & (ExtBit) \
4933	: aHostRawStd[1].reg & (StdBit)) \
4934	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4935	) \
4936	{ \
4937	if (fStrictCpuIdChecks) \
4938	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4939	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
4940	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4941	} \
4942	} while (0)
4943	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
4944	do { \
4945	if ( (aGuestCpuId[1].reg & (ExtBit)) \
4946	&& !(fHostAmd \
4947	? aHostRawExt[1].reg & (ExtBit) \
4948	: aHostRawStd[1].reg & (StdBit)) \
4949	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4950	) \
4951	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4952	} while (0)
4953	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
4954	do { \
4955	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4956	&& !(fHostAmd \
4957	? aHostRawExt[1].reg & (ExtBit) \
4958	: aHostRawStd[1].reg & (StdBit)) \
4959	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4960	) \
4961	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4962	} while (0)
4963	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
4964
4965	/*
4966	* For raw-mode we'll require that the CPUs are very similar since we don't
4967	* intercept CPUID instructions for user mode applications.
4968	*/
4969	if (!HMIsEnabled(pVM))
4970	{
4971	/* CPUID(0) */
4972	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
4973	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
4974	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
4975	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
4976	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
4977	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
4978	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
4979	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
4980	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
4981
4982	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
4983
4984	/* CPUID(1).eax */
4985	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
4986	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
4987	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
4988
4989	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
4990	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
4991	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
4992
4993	/* CPUID(1).ecx */
4994	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
4995	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
4996	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
4997	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4998	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
4999	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
5000	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
5001	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
5002	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
5003	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
5004	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
5005	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
5006	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
5007	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
5008	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
5009	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
5010	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5011	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5012	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
5013	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
5014	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
5015	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5016	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
5017	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
5018	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5019	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
5020	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
5021	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5022	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
5023	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5024	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5025	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
5026
5027	/* CPUID(1).edx */
5028	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5029	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5030	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
5031	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5032	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
5033	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
5034	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5035	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5036	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
5037	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5038	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5039	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5040	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5041	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5042	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5043	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
5044	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5045	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5046	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5047	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
5048	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5049	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
5050	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
5051	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
5052	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
5053	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
5054	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
5055	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
5056	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
5057	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
5058	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
5059	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
5060
5061	/* CPUID(2) - config, mostly about caches. ignore. */
5062	/* CPUID(3) - processor serial number. ignore. */
5063	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
5064	/* CPUID(5) - mwait/monitor config. ignore. */
5065	/* CPUID(6) - power management. ignore. */
5066	/* CPUID(7) - ???. ignore. */
5067	/* CPUID(8) - ???. ignore. */
5068	/* CPUID(9) - DCA. ignore for now. */
5069	/* CPUID(a) - PeMo info. ignore for now. */
5070	/* CPUID(b) - topology info - takes ECX as input. ignore. */
5071
5072	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
5073	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
5074	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
5075	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
5076	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
5077	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
5078	{
5079	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
5080	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
5081	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
5082	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
5083	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
5084	}
5085
5086	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
5087	Note! Intel have/is marking many of the fields here as reserved. We
5088	will verify them as if it's an AMD CPU. */
5089	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
5090	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
5091	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
5092	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
5093	{
5094	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
5095	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
5096	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
5097	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5098	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
5099	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
5100	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
5101
5102	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
5103	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
5104	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
5105	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
5106	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
5107	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5108
5109	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
5110	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
5111	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
5112	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
5113
5114	/* CPUID(0x80000001).ecx */
5115	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
5116	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
5117	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
5118	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
5119	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
5120	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
5121	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
5122	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
5123	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
5124	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
5125	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
5126	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
5127	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
5128	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
5129	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5130	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5131	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5132	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5133	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5134	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5135	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5136	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5137	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5138	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5139	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5140	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5141	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5142	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5143	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5144	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5145	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5146	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5147
5148	/* CPUID(0x80000001).edx */
5149	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
5150	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
5151	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
5152	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
5153	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
5154	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
5155	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
5156	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
5157	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
5158	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
5159	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5160	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
5161	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
5162	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
5163	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
5164	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
5165	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
5166	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
5167	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5168	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5169	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5170	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
5171	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5172	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
5173	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
5174	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5175	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5176	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5177	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
5178	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5179	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5180	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5181
5182	/** @todo verify the rest as well. */
5183	}
5184	}
5185
5186
5187
5188	/*
5189	* Verify that we can support the features already exposed to the guest on
5190	* this host.
5191	*
5192	* Most of the features we're emulating requires intercepting instruction
5193	* and doing it the slow way, so there is no need to warn when they aren't
5194	* present in the host CPU. Thus we use IGN instead of EMU on these.
5195	*
5196	* Trailing comments:
5197	* "EMU" - Possible to emulate, could be lots of work and very slow.
5198	* "EMU?" - Can this be emulated?
5199	*/
5200	CPUMCPUID aGuestCpuIdStd[2];
5201	RT_ZERO(aGuestCpuIdStd);
5202	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5203
5204	/* CPUID(1).ecx */
5205	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5206	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5207	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5208	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5209	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5210	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5211	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5212	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5213	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5214	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5215	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5216	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5217	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5218	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5219	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5220	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5221	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5222	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5223	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5224	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5225	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5226	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5227	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5228	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5229	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5230	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5231	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5232	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5233	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5234	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5235	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5236	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5237
5238	/* CPUID(1).edx */
5239	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5240	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5241	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5242	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5243	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5244	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5245	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5246	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5247	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5248	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5249	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5250	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5251	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5252	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5253	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5254	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5255	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5256	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5257	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5258	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5259	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5260	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5261	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5262	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5263	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5264	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5265	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5266	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5267	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5268	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5269	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5270	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5271
5272	/* CPUID(0x80000000). */
5273	CPUMCPUID aGuestCpuIdExt[2];
5274	RT_ZERO(aGuestCpuIdExt);
5275	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5276	{
5277	/** @todo deal with no 0x80000001 on the host. */
5278	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5279	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5280
5281	/* CPUID(0x80000001).ecx */
5282	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5283	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5284	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5285	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5286	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5287	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5288	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5289	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5290	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5291	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5292	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5293	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5294	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5295	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5296	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5297	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5298	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5299	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5300	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5301	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5302	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5303	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5304	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5305	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5306	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5307	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5308	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5309	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5310	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5311	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5312	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5313	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5314
5315	/* CPUID(0x80000001).edx */
5316	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5317	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5318	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5319	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5320	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5321	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5322	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5323	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5324	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5325	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5326	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5327	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5328	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5329	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5330	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5331	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5332	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5333	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5334	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5335	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5336	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5337	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5338	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5339	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5340	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5341	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5342	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5343	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5344	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5345	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5346	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5347	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5348	}
5349
5350	/** @todo check leaf 7 */
5351
5352	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5353	* ECX=0: EAX - Valid bits in XCR0[31:0].
5354	* EBX - Maximum state size as per current XCR0 value.
5355	* ECX - Maximum state size for all supported features.
5356	* EDX - Valid bits in XCR0[63:32].
5357	* ECX=1: EAX - Various X-features.
5358	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5359	* ECX - Valid bits in IA32_XSS[31:0].
5360	* EDX - Valid bits in IA32_XSS[63:32].
5361	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5362	* if the bit invalid all four registers are set to zero.
5363	* EAX - The state size for this feature.
5364	* EBX - The state byte offset of this feature.
5365	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5366	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5367	*/
5368	uint64_t fGuestXcr0Mask = 0;
5369	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5370	if ( pCurLeaf
5371	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5372	&& ( pCurLeaf->uEax
5373	\|\| pCurLeaf->uEbx
5374	\|\| pCurLeaf->uEcx
5375	\|\| pCurLeaf->uEdx) )
5376	{
5377	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5378	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5379	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5380	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5381	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5382	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5383	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5384	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5385
5386	/* We don't support any additional features yet. */
5387	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5388	if (pCurLeaf && pCurLeaf->uEax)
5389	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5390	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5391	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5392	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5393	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5394	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5395
5396
5397	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5398	{
5399	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5400	if (pCurLeaf)
5401	{
5402	/* If advertised, the state component offset and size must match the one used by host. */
5403	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5404	{
5405	CPUMCPUID RawHost;
5406	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5407	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5408	if ( RawHost.uEbx != pCurLeaf->uEbx
5409	\|\| RawHost.uEax != pCurLeaf->uEax)
5410	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5411	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5412	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5413	}
5414	}
5415	}
5416	}
5417	/* Clear leaf 0xd just in case we're loading an old state... */
5418	else if (pCurLeaf)
5419	{
5420	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5421	{
5422	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5423	if (pCurLeaf)
5424	{
5425	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5426	\|\| ( pCurLeaf->uEax == 0
5427	&& pCurLeaf->uEbx == 0
5428	&& pCurLeaf->uEcx == 0
5429	&& pCurLeaf->uEdx == 0),
5430	("uVersion=%#x; %#x %#x %#x %#x\n",
5431	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5432	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5433	}
5434	}
5435	}
5436
5437	/* Update the fXStateGuestMask value for the VM. */
5438	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5439	{
5440	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5441	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5442	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5443	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5444	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5445	}
5446
5447	#undef CPUID_CHECK_RET
5448	#undef CPUID_CHECK_WRN
5449	#undef CPUID_CHECK2_RET
5450	#undef CPUID_CHECK2_WRN
5451	#undef CPUID_RAW_FEATURE_RET
5452	#undef CPUID_RAW_FEATURE_WRN
5453	#undef CPUID_RAW_FEATURE_IGN
5454	#undef CPUID_GST_FEATURE_RET
5455	#undef CPUID_GST_FEATURE_WRN
5456	#undef CPUID_GST_FEATURE_EMU
5457	#undef CPUID_GST_FEATURE_IGN
5458	#undef CPUID_GST_FEATURE2_RET
5459	#undef CPUID_GST_FEATURE2_WRN
5460	#undef CPUID_GST_FEATURE2_EMU
5461	#undef CPUID_GST_FEATURE2_IGN
5462	#undef CPUID_GST_AMD_FEATURE_RET
5463	#undef CPUID_GST_AMD_FEATURE_WRN
5464	#undef CPUID_GST_AMD_FEATURE_EMU
5465	#undef CPUID_GST_AMD_FEATURE_IGN
5466
5467	/*
5468	* We're good, commit the CPU ID leaves.
5469	*/
5470	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5471	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5472	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5473	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
5474	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5475	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
5476	AssertLogRelRCReturn(rc, rc);
5477
5478	return VINF_SUCCESS;
5479	}
5480
5481
5482	/**
5483	* Loads the CPU ID leaves saved by pass 0.
5484	*
5485	* @returns VBox status code.
5486	* @param pVM The cross context VM structure.
5487	* @param pSSM The saved state handle.
5488	* @param uVersion The format version.
5489	*/
5490	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5491	{
5492	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5493
5494	/*
5495	* Load the CPUID leaves array first and call worker to do the rest, just so
5496	* we can free the memory when we need to without ending up in column 1000.
5497	*/
5498	PCPUMCPUIDLEAF paLeaves;
5499	uint32_t cLeaves;
5500	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5501	AssertRC(rc);
5502	if (RT_SUCCESS(rc))
5503	{
5504	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
5505	RTMemFree(paLeaves);
5506	}
5507	return rc;
5508	}
5509
5510
5511
5512	/**
5513	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5514	*
5515	* @returns VBox status code.
5516	* @param pVM The cross context VM structure.
5517	* @param pSSM The saved state handle.
5518	* @param uVersion The format version.
5519	*/
5520	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5521	{
5522	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5523
5524	/*
5525	* Restore the CPUID leaves.
5526	*
5527	* Note that we support restoring less than the current amount of standard
5528	* leaves because we've been allowed more is newer version of VBox.
5529	*/
5530	uint32_t cElements;
5531	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5532	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5533	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5534	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5535
5536	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5537	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5538	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5539	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5540
5541	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5542	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5543	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5544	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5545
5546	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5547
5548	/*
5549	* Check that the basic cpuid id information is unchanged.
5550	*/
5551	/** @todo we should check the 64 bits capabilities too! */
5552	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5553	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5554	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5555	uint32_t au32CpuIdSaved[8];
5556	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5557	if (RT_SUCCESS(rc))
5558	{
5559	/* Ignore CPU stepping. */
5560	au32CpuId[4] &= 0xfffffff0;
5561	au32CpuIdSaved[4] &= 0xfffffff0;
5562
5563	/* Ignore APIC ID (AMD specs). */
5564	au32CpuId[5] &= ~0xff000000;
5565	au32CpuIdSaved[5] &= ~0xff000000;
5566
5567	/* Ignore the number of Logical CPUs (AMD specs). */
5568	au32CpuId[5] &= ~0x00ff0000;
5569	au32CpuIdSaved[5] &= ~0x00ff0000;
5570
5571	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5572	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5573	\| X86_CPUID_FEATURE_ECX_VMX
5574	\| X86_CPUID_FEATURE_ECX_SMX
5575	\| X86_CPUID_FEATURE_ECX_EST
5576	\| X86_CPUID_FEATURE_ECX_TM2
5577	\| X86_CPUID_FEATURE_ECX_CNTXID
5578	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5579	\| X86_CPUID_FEATURE_ECX_PDCM
5580	\| X86_CPUID_FEATURE_ECX_DCA
5581	\| X86_CPUID_FEATURE_ECX_X2APIC
5582	);
5583	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5584	\| X86_CPUID_FEATURE_ECX_VMX
5585	\| X86_CPUID_FEATURE_ECX_SMX
5586	\| X86_CPUID_FEATURE_ECX_EST
5587	\| X86_CPUID_FEATURE_ECX_TM2
5588	\| X86_CPUID_FEATURE_ECX_CNTXID
5589	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5590	\| X86_CPUID_FEATURE_ECX_PDCM
5591	\| X86_CPUID_FEATURE_ECX_DCA
5592	\| X86_CPUID_FEATURE_ECX_X2APIC
5593	);
5594
5595	/* Make sure we don't forget to update the masks when enabling
5596	* features in the future.
5597	*/
5598	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5599	( X86_CPUID_FEATURE_ECX_DTES64
5600	\| X86_CPUID_FEATURE_ECX_VMX
5601	\| X86_CPUID_FEATURE_ECX_SMX
5602	\| X86_CPUID_FEATURE_ECX_EST
5603	\| X86_CPUID_FEATURE_ECX_TM2
5604	\| X86_CPUID_FEATURE_ECX_CNTXID
5605	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5606	\| X86_CPUID_FEATURE_ECX_PDCM
5607	\| X86_CPUID_FEATURE_ECX_DCA
5608	\| X86_CPUID_FEATURE_ECX_X2APIC
5609	)));
5610	/* do the compare */
5611	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5612	{
5613	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5614	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5615	"Saved=%.*Rhxs\n"
5616	"Real =%.*Rhxs\n",
5617	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5618	sizeof(au32CpuId), au32CpuId));
5619	else
5620	{
5621	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5622	"Saved=%.*Rhxs\n"
5623	"Real =%.*Rhxs\n",
5624	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5625	sizeof(au32CpuId), au32CpuId));
5626	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5627	}
5628	}
5629	}
5630
5631	return rc;
5632	}
5633
5634
5635
5636	/*
5637	*
5638	*
5639	* CPUID Info Handler.
5640	* CPUID Info Handler.
5641	* CPUID Info Handler.
5642	*
5643	*
5644	*/
5645
5646
5647
5648	/**
5649	* Get L1 cache / TLS associativity.
5650	*/
5651	static const char getCacheAss(unsigned u, char pszBuf)
5652	{
5653	if (u == 0)
5654	return "res0 ";
5655	if (u == 1)
5656	return "direct";
5657	if (u == 255)
5658	return "fully";
5659	if (u >= 256)
5660	return "???";
5661
5662	RTStrPrintf(pszBuf, 16, "%d way", u);
5663	return pszBuf;
5664	}
5665
5666
5667	/**
5668	* Get L2 cache associativity.
5669	*/
5670	const char *getL2CacheAss(unsigned u)
5671	{
5672	switch (u)
5673	{
5674	case 0: return "off ";
5675	case 1: return "direct";
5676	case 2: return "2 way ";
5677	case 3: return "res3 ";
5678	case 4: return "4 way ";
5679	case 5: return "res5 ";
5680	case 6: return "8 way ";
5681	case 7: return "res7 ";
5682	case 8: return "16 way";
5683	case 9: return "res9 ";
5684	case 10: return "res10 ";
5685	case 11: return "res11 ";
5686	case 12: return "res12 ";
5687	case 13: return "res13 ";
5688	case 14: return "res14 ";
5689	case 15: return "fully ";
5690	default: return "????";
5691	}
5692	}
5693
5694
5695	/** CPUID(1).EDX field descriptions. */
5696	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
5697	{
5698	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5699	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5700	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5701	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5702	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5703	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
5704	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5705	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5706	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5707	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5708	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
5709	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5710	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5711	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5712	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5713	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5714	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5715	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
5716	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
5717	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
5718	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
5719	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5720	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
5721	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
5722	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
5723	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
5724	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
5725	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
5726	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
5727	DBGFREGSUBFIELD_TERMINATOR()
5728	};
5729
5730	/** CPUID(1).ECX field descriptions. */
5731	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
5732	{
5733	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
5734	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
5735	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
5736	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
5737	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
5738	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
5739	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
5740	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
5741	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
5742	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
5743	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
5744	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
5745	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
5746	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
5747	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
5748	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
5749	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
5750	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
5751	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
5752	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
5753	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
5754	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
5755	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
5756	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
5757	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
5758	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
5759	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
5760	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
5761	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
5762	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
5763	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
5764	DBGFREGSUBFIELD_TERMINATOR()
5765	};
5766
5767	/** CPUID(7,0).EBX field descriptions. */
5768	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
5769	{
5770	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
5771	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
5772	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
5773	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
5774	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
5775	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
5776	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
5777	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
5778	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
5779	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
5780	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
5781	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
5782	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
5783	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
5784	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
5785	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
5786	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
5787	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
5788	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
5789	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
5790	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
5791	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
5792	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
5793	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
5794	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
5795	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
5796	DBGFREGSUBFIELD_TERMINATOR()
5797	};
5798
5799	/** CPUID(7,0).ECX field descriptions. */
5800	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
5801	{
5802	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
5803	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
5804	DBGFREGSUBFIELD_RO("OSPKU\0" "CR4.PKU mirror", 4, 1, 0),
5805	DBGFREGSUBFIELD_TERMINATOR()
5806	};
5807
5808
5809	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
5810	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
5811	{
5812	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
5813	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
5814	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
5815	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
5816	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
5817	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
5818	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
5819	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
5820	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
5821	DBGFREGSUBFIELD_TERMINATOR()
5822	};
5823
5824	/** CPUID(13,1).EAX field descriptions. */
5825	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
5826	{
5827	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
5828	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
5829	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
5830	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
5831	DBGFREGSUBFIELD_TERMINATOR()
5832	};
5833
5834
5835	/** CPUID(0x80000001,0).EDX field descriptions. */
5836	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
5837	{
5838	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5839	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5840	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5841	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5842	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5843	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
5844	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5845	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5846	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5847	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5848	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
5849	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5850	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5851	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5852	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5853	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5854	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5855	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
5856	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
5857	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5858	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
5859	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
5860	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
5861	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
5862	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
5863	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
5864	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
5865	DBGFREGSUBFIELD_TERMINATOR()
5866	};
5867
5868	/** CPUID(0x80000001,0).ECX field descriptions. */
5869	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
5870	{
5871	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
5872	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
5873	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
5874	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
5875	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
5876	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
5877	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
5878	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
5879	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
5880	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
5881	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
5882	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
5883	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
5884	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
5885	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
5886	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
5887	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
5888	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
5889	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
5890	DBGFREGSUBFIELD_TERMINATOR()
5891	};
5892
5893
5894	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
5895	const char *pszLeadIn, uint32_t cchWidth)
5896	{
5897	if (pszLeadIn)
5898	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5899
5900	for (uint32_t iBit = 0; iBit < 32; iBit++)
5901	if (RT_BIT_32(iBit) & uVal)
5902	{
5903	while ( pDesc->pszName != NULL
5904	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5905	pDesc++;
5906	if ( pDesc->pszName != NULL
5907	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5908	{
5909	if (pDesc->cBits == 1)
5910	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5911	else
5912	{
5913	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
5914	if (pDesc->cBits < 32)
5915	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5916	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
5917	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5918	}
5919	}
5920	else
5921	pHlp->pfnPrintf(pHlp, " %u", iBit);
5922	}
5923	if (pszLeadIn)
5924	pHlp->pfnPrintf(pHlp, "\n");
5925	}
5926
5927
5928	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5929	const char *pszLeadIn, uint32_t cchWidth)
5930	{
5931	if (pszLeadIn)
5932	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5933
5934	for (uint32_t iBit = 0; iBit < 64; iBit++)
5935	if (RT_BIT_64(iBit) & uVal)
5936	{
5937	while ( pDesc->pszName != NULL
5938	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5939	pDesc++;
5940	if ( pDesc->pszName != NULL
5941	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5942	{
5943	if (pDesc->cBits == 1)
5944	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5945	else
5946	{
5947	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
5948	if (pDesc->cBits < 64)
5949	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
5950	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
5951	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5952	}
5953	}
5954	else
5955	pHlp->pfnPrintf(pHlp, " %u", iBit);
5956	}
5957	if (pszLeadIn)
5958	pHlp->pfnPrintf(pHlp, "\n");
5959	}
5960
5961
5962	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5963	const char *pszLeadIn, uint32_t cchWidth)
5964	{
5965	if (!uVal)
5966	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5967	else
5968	{
5969	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5970	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
5971	pHlp->pfnPrintf(pHlp, " )\n");
5972	}
5973	}
5974
5975
5976	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
5977	uint32_t cchWidth)
5978	{
5979	uint32_t uCombined = uVal1 \| uVal2;
5980	for (uint32_t iBit = 0; iBit < 32; iBit++)
5981	if ( (RT_BIT_32(iBit) & uCombined)
5982	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
5983	{
5984	while ( pDesc->pszName != NULL
5985	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5986	pDesc++;
5987
5988	if ( pDesc->pszName != NULL
5989	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5990	{
5991	size_t cchMnemonic = strlen(pDesc->pszName);
5992	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
5993	size_t cchDesc = strlen(pszDesc);
5994	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
5995	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
5996	if (pDesc->cBits < 32)
5997	{
5998	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5999	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6000	}
6001
6002	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6003	pDesc->pszName, pszDesc,
6004	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6005	uFieldValue1, uFieldValue2);
6006
6007	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6008	pDesc++;
6009	}
6010	else
6011	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6012	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6013	}
6014	}
6015
6016
6017	/**
6018	* Produces a detailed summary of standard leaf 0x00000001.
6019	*
6020	* @param pHlp The info helper functions.
6021	* @param pCurLeaf The 0x00000001 leaf.
6022	* @param fVerbose Whether to be very verbose or not.
6023	* @param fIntel Set if intel CPU.
6024	*/
6025	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6026	{
6027	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6028	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6029	uint32_t uEAX = pCurLeaf->uEax;
6030	uint32_t uEBX = pCurLeaf->uEbx;
6031
6032	pHlp->pfnPrintf(pHlp,
6033	"%36s %2d \tExtended: %d \tEffective: %d\n"
6034	"%36s %2d \tExtended: %d \tEffective: %d\n"
6035	"%36s %d\n"
6036	"%36s %d (%s)\n"
6037	"%36s %#04x\n"
6038	"%36s %d\n"
6039	"%36s %d\n"
6040	"%36s %#04x\n"
6041	,
6042	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6043	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6044	"Stepping:", ASMGetCpuStepping(uEAX),
6045	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6046	"APIC ID:", (uEBX >> 24) & 0xff,
6047	"Logical CPUs:",(uEBX >> 16) & 0xff,
6048	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6049	"Brand ID:", (uEBX >> 0) & 0xff);
6050	if (fVerbose)
6051	{
6052	CPUMCPUID Host;
6053	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6054	pHlp->pfnPrintf(pHlp, "Features\n");
6055	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6056	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6057	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6058	}
6059	else
6060	{
6061	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6062	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6063	}
6064	}
6065
6066
6067	/**
6068	* Produces a detailed summary of standard leaf 0x00000007.
6069	*
6070	* @param pHlp The info helper functions.
6071	* @param paLeaves The CPUID leaves array.
6072	* @param cLeaves The number of leaves in the array.
6073	* @param pCurLeaf The first 0x00000007 leaf.
6074	* @param fVerbose Whether to be very verbose or not.
6075	*/
6076	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6077	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6078	{
6079	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6080	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6081	for (;;)
6082	{
6083	CPUMCPUID Host;
6084	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6085
6086	switch (pCurLeaf->uSubLeaf)
6087	{
6088	case 0:
6089	if (fVerbose)
6090	{
6091	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6092	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6093	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6094	if (pCurLeaf->uEdx \|\| Host.uEdx)
6095	pHlp->pfnPrintf(pHlp, "%36 %#x (%#x)\n", "Ext Features EDX:", pCurLeaf->uEdx, Host.uEdx);
6096	}
6097	else
6098	{
6099	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6100	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6101	if (pCurLeaf->uEdx)
6102	pHlp->pfnPrintf(pHlp, "%36 %#x\n", "Ext Features EDX:", pCurLeaf->uEdx);
6103	}
6104	break;
6105
6106	default:
6107	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6108	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6109	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6110	break;
6111
6112	}
6113
6114	/* advance. */
6115	pCurLeaf++;
6116	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6117	\|\| pCurLeaf->uLeaf != 0x7)
6118	break;
6119	}
6120	}
6121
6122
6123	/**
6124	* Produces a detailed summary of standard leaf 0x0000000d.
6125	*
6126	* @param pHlp The info helper functions.
6127	* @param paLeaves The CPUID leaves array.
6128	* @param cLeaves The number of leaves in the array.
6129	* @param pCurLeaf The first 0x00000007 leaf.
6130	* @param fVerbose Whether to be very verbose or not.
6131	*/
6132	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6133	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6134	{
6135	RT_NOREF_PV(fVerbose);
6136	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6137	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6138	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6139	{
6140	CPUMCPUID Host;
6141	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6142
6143	switch (uSubLeaf)
6144	{
6145	case 0:
6146	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6147	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6148	pCurLeaf->uEbx, pCurLeaf->uEcx);
6149	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6150
6151	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6152	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6153	"Valid XCR0 bits, guest:", 42);
6154	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6155	"Valid XCR0 bits, host:", 42);
6156	break;
6157
6158	case 1:
6159	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6160	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6161	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6162
6163	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6164	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6165	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6166
6167	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6168	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6169	" Valid IA32_XSS bits, guest:", 42);
6170	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6171	" Valid IA32_XSS bits, host:", 42);
6172	break;
6173
6174	default:
6175	if ( pCurLeaf
6176	&& pCurLeaf->uSubLeaf == uSubLeaf
6177	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6178	{
6179	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6180	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6181	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6182	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6183	if (pCurLeaf->uEdx)
6184	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6185	pHlp->pfnPrintf(pHlp, " --");
6186	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6187	pHlp->pfnPrintf(pHlp, "\n");
6188	}
6189	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6190	{
6191	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6192	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6193	if (Host.uEcx & ~RT_BIT_32(0))
6194	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6195	if (Host.uEdx)
6196	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6197	pHlp->pfnPrintf(pHlp, " --");
6198	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6199	pHlp->pfnPrintf(pHlp, "\n");
6200	}
6201	break;
6202
6203	}
6204
6205	/* advance. */
6206	if (pCurLeaf)
6207	{
6208	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6209	&& pCurLeaf->uSubLeaf <= uSubLeaf
6210	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6211	pCurLeaf++;
6212	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6213	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6214	pCurLeaf = NULL;
6215	}
6216	}
6217	}
6218
6219
6220	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6221	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6222	{
6223	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6224	&& pCurLeaf->uLeaf <= uUpToLeaf)
6225	{
6226	pHlp->pfnPrintf(pHlp,
6227	" %s\n"
6228	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6229	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6230	&& pCurLeaf->uLeaf <= uUpToLeaf)
6231	{
6232	CPUMCPUID Host;
6233	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6234	pHlp->pfnPrintf(pHlp,
6235	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6236	"Hst: %08x %08x %08x %08x\n",
6237	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6238	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6239	pCurLeaf++;
6240	}
6241	}
6242
6243	return pCurLeaf;
6244	}
6245
6246
6247	/**
6248	* Display the guest CpuId leaves.
6249	*
6250	* @param pVM The cross context VM structure.
6251	* @param pHlp The info helper functions.
6252	* @param pszArgs "terse", "default" or "verbose".
6253	*/
6254	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6255	{
6256	/*
6257	* Parse the argument.
6258	*/
6259	unsigned iVerbosity = 1;
6260	if (pszArgs)
6261	{
6262	pszArgs = RTStrStripL(pszArgs);
6263	if (!strcmp(pszArgs, "terse"))
6264	iVerbosity--;
6265	else if (!strcmp(pszArgs, "verbose"))
6266	iVerbosity++;
6267	}
6268
6269	uint32_t uLeaf;
6270	CPUMCPUID Host;
6271	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6272	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6273	PCCPUMCPUIDLEAF pCurLeaf;
6274	PCCPUMCPUIDLEAF pNextLeaf;
6275	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6276	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6277	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6278
6279	/*
6280	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6281	*/
6282	uint32_t cHstMax = ASMCpuId_EAX(0);
6283	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6284	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6285	pHlp->pfnPrintf(pHlp,
6286	" Raw Standard CPUID Leaves\n"
6287	" Leaf/sub-leaf eax ebx ecx edx\n");
6288	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6289	{
6290	uint32_t cMaxSubLeaves = 1;
6291	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6292	cMaxSubLeaves = 16;
6293	else if (uLeaf == 0xd)
6294	cMaxSubLeaves = 128;
6295
6296	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6297	{
6298	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6299	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6300	&& pCurLeaf->uLeaf == uLeaf
6301	&& pCurLeaf->uSubLeaf == uSubLeaf)
6302	{
6303	pHlp->pfnPrintf(pHlp,
6304	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6305	"Hst: %08x %08x %08x %08x\n",
6306	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6307	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6308	pCurLeaf++;
6309	}
6310	else if ( uLeaf != 0xd
6311	\|\| uSubLeaf <= 1
6312	\|\| Host.uEbx != 0 )
6313	pHlp->pfnPrintf(pHlp,
6314	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6315	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6316
6317	/* Done? */
6318	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6319	\|\| pCurLeaf->uLeaf != uLeaf)
6320	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6321	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6322	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6323	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6324	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6325	)
6326	)
6327	break;
6328	}
6329	}
6330	pNextLeaf = pCurLeaf;
6331
6332	/*
6333	* If verbose, decode it.
6334	*/
6335	if (iVerbosity && paLeaves[0].uLeaf == 0)
6336	pHlp->pfnPrintf(pHlp,
6337	"%36s %.04s%.04s%.04s\n"
6338	"%36s 0x00000000-%#010x\n"
6339	,
6340	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6341	"Supports:", paLeaves[0].uEax);
6342
6343	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6344	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6345
6346	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6347	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6348
6349	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6350	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6351
6352	pCurLeaf = pNextLeaf;
6353
6354	/*
6355	* Hypervisor leaves.
6356	*
6357	* Unlike most of the other leaves reported, the guest hypervisor leaves
6358	* aren't a subset of the host CPUID bits.
6359	*/
6360	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6361
6362	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6363	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6364	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6365	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6366	cMax = RT_MAX(cHstMax, cGstMax);
6367	if (cMax >= UINT32_C(0x40000000))
6368	{
6369	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6370
6371	/** @todo dump these in more detail. */
6372
6373	pCurLeaf = pNextLeaf;
6374	}
6375
6376
6377	/*
6378	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6379	* Implemented after AMD specs.
6380	*/
6381	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6382
6383	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6384	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6385	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6386	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6387	cMax = RT_MAX(cHstMax, cGstMax);
6388	if (cMax >= UINT32_C(0x80000000))
6389	{
6390
6391	pHlp->pfnPrintf(pHlp,
6392	" Raw Extended CPUID Leaves\n"
6393	" Leaf/sub-leaf eax ebx ecx edx\n");
6394	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6395	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6396	{
6397	uint32_t cMaxSubLeaves = 1;
6398	if (uLeaf == UINT32_C(0x8000001d))
6399	cMaxSubLeaves = 16;
6400
6401	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6402	{
6403	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6404	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6405	&& pCurLeaf->uLeaf == uLeaf
6406	&& pCurLeaf->uSubLeaf == uSubLeaf)
6407	{
6408	pHlp->pfnPrintf(pHlp,
6409	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6410	"Hst: %08x %08x %08x %08x\n",
6411	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6412	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6413	pCurLeaf++;
6414	}
6415	else if ( uLeaf != 0xd
6416	\|\| uSubLeaf <= 1
6417	\|\| Host.uEbx != 0 )
6418	pHlp->pfnPrintf(pHlp,
6419	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6420	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6421
6422	/* Done? */
6423	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6424	\|\| pCurLeaf->uLeaf != uLeaf)
6425	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6426	break;
6427	}
6428	}
6429	pNextLeaf = pCurLeaf;
6430
6431	/*
6432	* Understandable output
6433	*/
6434	if (iVerbosity)
6435	pHlp->pfnPrintf(pHlp,
6436	"Ext Name: %.4s%.4s%.4s\n"
6437	"Ext Supports: 0x80000000-%#010x\n",
6438	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6439
6440	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6441	if (iVerbosity && pCurLeaf)
6442	{
6443	uint32_t uEAX = pCurLeaf->uEax;
6444	pHlp->pfnPrintf(pHlp,
6445	"Family: %d \tExtended: %d \tEffective: %d\n"
6446	"Model: %d \tExtended: %d \tEffective: %d\n"
6447	"Stepping: %d\n"
6448	"Brand ID: %#05x\n",
6449	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6450	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6451	ASMGetCpuStepping(uEAX),
6452	pCurLeaf->uEbx & 0xfff);
6453
6454	if (iVerbosity == 1)
6455	{
6456	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6457	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6458	}
6459	else
6460	{
6461	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6462	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6463	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6464	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6465	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6466	}
6467	}
6468
6469	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6470	{
6471	char szString[443+1] = {0};
6472	uint32_t pu32 = (uint32_t )szString;
6473	*pu32++ = pCurLeaf->uEax;
6474	*pu32++ = pCurLeaf->uEbx;
6475	*pu32++ = pCurLeaf->uEcx;
6476	*pu32++ = pCurLeaf->uEdx;
6477	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6478	if (pCurLeaf)
6479	{
6480	*pu32++ = pCurLeaf->uEax;
6481	*pu32++ = pCurLeaf->uEbx;
6482	*pu32++ = pCurLeaf->uEcx;
6483	*pu32++ = pCurLeaf->uEdx;
6484	}
6485	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6486	if (pCurLeaf)
6487	{
6488	*pu32++ = pCurLeaf->uEax;
6489	*pu32++ = pCurLeaf->uEbx;
6490	*pu32++ = pCurLeaf->uEcx;
6491	*pu32++ = pCurLeaf->uEdx;
6492	}
6493	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6494	}
6495
6496	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6497	{
6498	uint32_t uEAX = pCurLeaf->uEax;
6499	uint32_t uEBX = pCurLeaf->uEbx;
6500	uint32_t uECX = pCurLeaf->uEcx;
6501	uint32_t uEDX = pCurLeaf->uEdx;
6502	char sz1[32];
6503	char sz2[32];
6504
6505	pHlp->pfnPrintf(pHlp,
6506	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6507	"TLB 2/4M Data: %s %3d entries\n",
6508	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6509	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6510	pHlp->pfnPrintf(pHlp,
6511	"TLB 4K Instr/Uni: %s %3d entries\n"
6512	"TLB 4K Data: %s %3d entries\n",
6513	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6514	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6515	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6516	"L1 Instr Cache Lines Per Tag: %d\n"
6517	"L1 Instr Cache Associativity: %s\n"
6518	"L1 Instr Cache Size: %d KB\n",
6519	(uEDX >> 0) & 0xff,
6520	(uEDX >> 8) & 0xff,
6521	getCacheAss((uEDX >> 16) & 0xff, sz1),
6522	(uEDX >> 24) & 0xff);
6523	pHlp->pfnPrintf(pHlp,
6524	"L1 Data Cache Line Size: %d bytes\n"
6525	"L1 Data Cache Lines Per Tag: %d\n"
6526	"L1 Data Cache Associativity: %s\n"
6527	"L1 Data Cache Size: %d KB\n",
6528	(uECX >> 0) & 0xff,
6529	(uECX >> 8) & 0xff,
6530	getCacheAss((uECX >> 16) & 0xff, sz1),
6531	(uECX >> 24) & 0xff);
6532	}
6533
6534	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6535	{
6536	uint32_t uEAX = pCurLeaf->uEax;
6537	uint32_t uEBX = pCurLeaf->uEbx;
6538	uint32_t uEDX = pCurLeaf->uEdx;
6539
6540	pHlp->pfnPrintf(pHlp,
6541	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6542	"L2 TLB 2/4M Data: %s %4d entries\n",
6543	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6544	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6545	pHlp->pfnPrintf(pHlp,
6546	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6547	"L2 TLB 4K Data: %s %4d entries\n",
6548	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6549	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6550	pHlp->pfnPrintf(pHlp,
6551	"L2 Cache Line Size: %d bytes\n"
6552	"L2 Cache Lines Per Tag: %d\n"
6553	"L2 Cache Associativity: %s\n"
6554	"L2 Cache Size: %d KB\n",
6555	(uEDX >> 0) & 0xff,
6556	(uEDX >> 8) & 0xf,
6557	getL2CacheAss((uEDX >> 12) & 0xf),
6558	(uEDX >> 16) & 0xffff);
6559	}
6560
6561	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
6562	{
6563	uint32_t uEDX = pCurLeaf->uEdx;
6564
6565	pHlp->pfnPrintf(pHlp, "APM Features: ");
6566	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
6567	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
6568	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
6569	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
6570	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
6571	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
6572	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " MC");
6573	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " HWPSTATE");
6574	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TscInvariant");
6575	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " CPB");
6576	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " EffFreqRO");
6577	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PFI");
6578	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PA");
6579	for (unsigned iBit = 13; iBit < 32; iBit++)
6580	if (uEDX & RT_BIT(iBit))
6581	pHlp->pfnPrintf(pHlp, " %d", iBit);
6582	pHlp->pfnPrintf(pHlp, "\n");
6583
6584	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6585	pHlp->pfnPrintf(pHlp, "Host Invariant-TSC support: %RTbool\n",
6586	cHstMax >= UINT32_C(0x80000007) && (Host.uEdx & RT_BIT(8)));
6587
6588	}
6589
6590	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0)) != NULL)
6591	{
6592	uint32_t uEAX = pCurLeaf->uEax;
6593	uint32_t uECX = pCurLeaf->uEcx;
6594
6595	pHlp->pfnPrintf(pHlp,
6596	"Physical Address Width: %d bits\n"
6597	"Virtual Address Width: %d bits\n"
6598	"Guest Physical Address Width: %d bits\n",
6599	(uEAX >> 0) & 0xff,
6600	(uEAX >> 8) & 0xff,
6601	(uEAX >> 16) & 0xff);
6602	pHlp->pfnPrintf(pHlp,
6603	"Physical Core Count: %d\n",
6604	((uECX >> 0) & 0xff) + 1);
6605	}
6606
6607	pCurLeaf = pNextLeaf;
6608	}
6609
6610
6611
6612	/*
6613	* Centaur.
6614	*/
6615	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
6616
6617	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6618	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
6619	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
6620	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
6621	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
6622	cMax = RT_MAX(cHstMax, cGstMax);
6623	if (cMax >= UINT32_C(0xc0000000))
6624	{
6625	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
6626
6627	/*
6628	* Understandable output
6629	*/
6630	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
6631	pHlp->pfnPrintf(pHlp,
6632	"Centaur Supports: 0xc0000000-%#010x\n",
6633	pCurLeaf->uEax);
6634
6635	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
6636	{
6637	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6638	uint32_t uEdxGst = pCurLeaf->uEdx;
6639	uint32_t uEdxHst = Host.uEdx;
6640
6641	if (iVerbosity == 1)
6642	{
6643	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
6644	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
6645	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
6646	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
6647	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
6648	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
6649	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
6650	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
6651	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
6652	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6653	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
6654	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
6655	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
6656	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
6657	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
6658	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
6659	for (unsigned iBit = 14; iBit < 32; iBit++)
6660	if (uEdxGst & RT_BIT(iBit))
6661	pHlp->pfnPrintf(pHlp, " %d", iBit);
6662	pHlp->pfnPrintf(pHlp, "\n");
6663	}
6664	else
6665	{
6666	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
6667	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
6668	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
6669	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
6670	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
6671	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
6672	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
6673	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
6674	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
6675	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6676	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
6677	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
6678	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
6679	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
6680	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
6681	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
6682	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
6683	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
6684	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
6685	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
6686	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
6687	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
6688	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
6689	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
6690	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
6691	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
6692	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
6693	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
6694	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
6695	for (unsigned iBit = 27; iBit < 32; iBit++)
6696	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
6697	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
6698	pHlp->pfnPrintf(pHlp, "\n");
6699	}
6700	}
6701
6702	pCurLeaf = pNextLeaf;
6703	}
6704
6705	/*
6706	* The remainder.
6707	*/
6708	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
6709	}
6710
6711
6712
6713
6714
6715	/*
6716	*
6717	*
6718	* PATM interfaces.
6719	* PATM interfaces.
6720	* PATM interfaces.
6721	*
6722	*
6723	*/
6724
6725
6726	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
6727	/** @name Patchmanager CPUID legacy table APIs
6728	* @{
6729	*/
6730
6731	/**
6732	* Gets a pointer to the default CPUID leaf.
6733	*
6734	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
6735	* @param pVM The cross context VM structure.
6736	* @remark Intended for PATM only.
6737	*/
6738	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
6739	{
6740	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
6741	}
6742
6743
6744	/**
6745	* Gets a number of standard CPUID leaves (PATM only).
6746	*
6747	* @returns Number of leaves.
6748	* @param pVM The cross context VM structure.
6749	* @remark Intended for PATM - legacy, don't use in new code.
6750	*/
6751	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
6752	{
6753	RT_NOREF_PV(pVM);
6754	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
6755	}
6756
6757
6758	/**
6759	* Gets a number of extended CPUID leaves (PATM only).
6760	*
6761	* @returns Number of leaves.
6762	* @param pVM The cross context VM structure.
6763	* @remark Intended for PATM - legacy, don't use in new code.
6764	*/
6765	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
6766	{
6767	RT_NOREF_PV(pVM);
6768	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
6769	}
6770
6771
6772	/**
6773	* Gets a number of centaur CPUID leaves.
6774	*
6775	* @returns Number of leaves.
6776	* @param pVM The cross context VM structure.
6777	* @remark Intended for PATM - legacy, don't use in new code.
6778	*/
6779	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
6780	{
6781	RT_NOREF_PV(pVM);
6782	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
6783	}
6784
6785
6786	/**
6787	* Gets a pointer to the array of standard CPUID leaves.
6788	*
6789	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
6790	*
6791	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
6792	* @param pVM The cross context VM structure.
6793	* @remark Intended for PATM - legacy, don't use in new code.
6794	*/
6795	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
6796	{
6797	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
6798	}
6799
6800
6801	/**
6802	* Gets a pointer to the array of extended CPUID leaves.
6803	*
6804	* CPUMGetGuestCpuIdExtMax() give the size of the array.
6805	*
6806	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
6807	* @param pVM The cross context VM structure.
6808	* @remark Intended for PATM - legacy, don't use in new code.
6809	*/
6810	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
6811	{
6812	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
6813	}
6814
6815
6816	/**
6817	* Gets a pointer to the array of centaur CPUID leaves.
6818	*
6819	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
6820	*
6821	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
6822	* @param pVM The cross context VM structure.
6823	* @remark Intended for PATM - legacy, don't use in new code.
6824	*/
6825	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
6826	{
6827	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
6828	}
6829
6830	/** @} */
6831	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
6832
6833	#endif /* VBOX_IN_VMM */
6834

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 66215

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