CPUMR3CpuId.cpp@ 70323

Last change on this file since 70323 was 70254, checked in by vboxsync, 7 years ago
VMM: Match the AMD specs exactly whenever possible for SVM specific feature, renamed to plural "Decode assists".
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 318.8 KB

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1	/* $Id: CPUMR3CpuId.cpp 70254 2017-12-21 05:54:03Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/ssm.h>
27	#include "CPUMInternal.h"
28	#include <VBox/vmm/vm.h>
29	#include <VBox/vmm/mm.h>
30	#include <VBox/sup.h>
31
32	#include <VBox/err.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/ctype.h>
35	#include <iprt/mem.h>
36	#include <iprt/string.h>
37
38
39	/*********************************************************************************************************************************
40	* Defined Constants And Macros *
41	*********************************************************************************************************************************/
42	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
43	#define CPUM_CPUID_MAX_LEAVES 2048
44	/* Max size we accept for the XSAVE area. */
45	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
46	/* Min size we accept for the XSAVE area. */
47	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
48
49
50	/*********************************************************************************************************************************
51	* Global Variables *
52	*********************************************************************************************************************************/
53	/**
54	* The intel pentium family.
55	*/
56	static const CPUMMICROARCH g_aenmIntelFamily06[] =
57	{
58	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
59	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
60	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
61	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
62	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
63	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
64	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
65	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
66	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
67	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
68	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
69	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
70	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
71	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
72	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
73	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
74	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
80	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
81	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
82	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
83	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
85	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
86	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
87	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
88	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
89	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
90	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
91	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
96	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
97	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
98	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
99	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
101	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
102	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
103	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
104	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
105	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
106	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
107	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
112	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
113	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
114	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
115	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
117	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
118	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
119	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
120	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
121	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
122	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
123	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
128	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
130	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
131	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
133	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
134	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
135	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
136	/* [78(0x4e)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed */
137	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / unconfirmed, Broadwell-E */
138	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
139	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed server cpu */
144	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
145	/* [87(0x57)] = */ kCpumMicroarch_Intel_Unknown,
146	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
147	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
149	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
150	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / unconfirmed */
151	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
152	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
153	/* [95(0x5f)] = */ kCpumMicroarch_Intel_Unknown,
154	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
155	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x64)] = */ kCpumMicroarch_Intel_Unknown,
159	/* [99(0x65)] = */ kCpumMicroarch_Intel_Unknown,
160	/* [99(0x66)] = / kCpumMicroarch_Intel_Core7_Cannonlake, / unconfirmed */
161	};
162
163
164
165	/**
166	* Figures out the (sub-)micro architecture given a bit of CPUID info.
167	*
168	* @returns Micro architecture.
169	* @param enmVendor The CPU vendor .
170	* @param bFamily The CPU family.
171	* @param bModel The CPU model.
172	* @param bStepping The CPU stepping.
173	*/
174	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
175	uint8_t bModel, uint8_t bStepping)
176	{
177	if (enmVendor == CPUMCPUVENDOR_AMD)
178	{
179	switch (bFamily)
180	{
181	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
182	case 0x03: return kCpumMicroarch_AMD_Am386;
183	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
184	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
185	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
186	case 0x06:
187	switch (bModel)
188	{
189	case 0: return kCpumMicroarch_AMD_K7_Palomino;
190	case 1: return kCpumMicroarch_AMD_K7_Palomino;
191	case 2: return kCpumMicroarch_AMD_K7_Palomino;
192	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
193	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
194	case 6: return kCpumMicroarch_AMD_K7_Palomino;
195	case 7: return kCpumMicroarch_AMD_K7_Morgan;
196	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
197	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
198	}
199	return kCpumMicroarch_AMD_K7_Unknown;
200	case 0x0f:
201	/*
202	* This family is a friggin mess. Trying my best to make some
203	* sense out of it. Too much happened in the 0x0f family to
204	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
205	*
206	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
207	* cpu-world.com, and other places:
208	* - 130nm:
209	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
210	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
211	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
212	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
213	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
214	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
215	* - 90nm:
216	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
217	* - Oakville: 10FC0/DH-D0.
218	* - Georgetown: 10FC0/DH-D0.
219	* - Sonora: 10FC0/DH-D0.
220	* - Venus: 20F71/SH-E4
221	* - Troy: 20F51/SH-E4
222	* - Athens: 20F51/SH-E4
223	* - San Diego: 20F71/SH-E4.
224	* - Lancaster: 20F42/SH-E5
225	* - Newark: 20F42/SH-E5.
226	* - Albany: 20FC2/DH-E6.
227	* - Roma: 20FC2/DH-E6.
228	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
229	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
230	* - 90nm introducing Dual core:
231	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
232	* - Italy: 20F10/JH-E1, 20F12/JH-E6
233	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
234	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
235	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
236	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
237	* - Santa Ana: 40F32/JH-F2, /-F3
238	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
239	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
240	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
241	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
242	* - Keene: 40FC2/DH-F2.
243	* - Richmond: 40FC2/DH-F2
244	* - Taylor: 40F82/BH-F2
245	* - Trinidad: 40F82/BH-F2
246	*
247	* - 65nm:
248	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
249	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
250	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
251	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
252	* - Sherman: /-G1, 70FC2/DH-G2.
253	* - Huron: 70FF2/DH-G2.
254	*/
255	if (bModel < 0x10)
256	return kCpumMicroarch_AMD_K8_130nm;
257	if (bModel >= 0x60 && bModel < 0x80)
258	return kCpumMicroarch_AMD_K8_65nm;
259	if (bModel >= 0x40)
260	return kCpumMicroarch_AMD_K8_90nm_AMDV;
261	switch (bModel)
262	{
263	case 0x21:
264	case 0x23:
265	case 0x2b:
266	case 0x2f:
267	case 0x37:
268	case 0x3f:
269	return kCpumMicroarch_AMD_K8_90nm_DualCore;
270	}
271	return kCpumMicroarch_AMD_K8_90nm;
272	case 0x10:
273	return kCpumMicroarch_AMD_K10;
274	case 0x11:
275	return kCpumMicroarch_AMD_K10_Lion;
276	case 0x12:
277	return kCpumMicroarch_AMD_K10_Llano;
278	case 0x14:
279	return kCpumMicroarch_AMD_Bobcat;
280	case 0x15:
281	switch (bModel)
282	{
283	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
284	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
285	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
286	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
287	case 0x11: /* ?? */
288	case 0x12: /* ?? */
289	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
290	}
291	return kCpumMicroarch_AMD_15h_Unknown;
292	case 0x16:
293	return kCpumMicroarch_AMD_Jaguar;
294	case 0x17:
295	return kCpumMicroarch_AMD_Zen_Ryzen;
296	}
297	return kCpumMicroarch_AMD_Unknown;
298	}
299
300	if (enmVendor == CPUMCPUVENDOR_INTEL)
301	{
302	switch (bFamily)
303	{
304	case 3:
305	return kCpumMicroarch_Intel_80386;
306	case 4:
307	return kCpumMicroarch_Intel_80486;
308	case 5:
309	return kCpumMicroarch_Intel_P5;
310	case 6:
311	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
312	return g_aenmIntelFamily06[bModel];
313	return kCpumMicroarch_Intel_Atom_Unknown;
314	case 15:
315	switch (bModel)
316	{
317	case 0: return kCpumMicroarch_Intel_NB_Willamette;
318	case 1: return kCpumMicroarch_Intel_NB_Willamette;
319	case 2: return kCpumMicroarch_Intel_NB_Northwood;
320	case 3: return kCpumMicroarch_Intel_NB_Prescott;
321	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
322	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
323	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
324	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
325	default: return kCpumMicroarch_Intel_NB_Unknown;
326	}
327	break;
328	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
329	case 0:
330	return kCpumMicroarch_Intel_8086;
331	case 1:
332	return kCpumMicroarch_Intel_80186;
333	case 2:
334	return kCpumMicroarch_Intel_80286;
335	}
336	return kCpumMicroarch_Intel_Unknown;
337	}
338
339	if (enmVendor == CPUMCPUVENDOR_VIA)
340	{
341	switch (bFamily)
342	{
343	case 5:
344	switch (bModel)
345	{
346	case 1: return kCpumMicroarch_Centaur_C6;
347	case 4: return kCpumMicroarch_Centaur_C6;
348	case 8: return kCpumMicroarch_Centaur_C2;
349	case 9: return kCpumMicroarch_Centaur_C3;
350	}
351	break;
352
353	case 6:
354	switch (bModel)
355	{
356	case 5: return kCpumMicroarch_VIA_C3_M2;
357	case 6: return kCpumMicroarch_VIA_C3_C5A;
358	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
359	case 8: return kCpumMicroarch_VIA_C3_C5N;
360	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
361	case 10: return kCpumMicroarch_VIA_C7_C5J;
362	case 15: return kCpumMicroarch_VIA_Isaiah;
363	}
364	break;
365	}
366	return kCpumMicroarch_VIA_Unknown;
367	}
368
369	if (enmVendor == CPUMCPUVENDOR_CYRIX)
370	{
371	switch (bFamily)
372	{
373	case 4:
374	switch (bModel)
375	{
376	case 9: return kCpumMicroarch_Cyrix_5x86;
377	}
378	break;
379
380	case 5:
381	switch (bModel)
382	{
383	case 2: return kCpumMicroarch_Cyrix_M1;
384	case 4: return kCpumMicroarch_Cyrix_MediaGX;
385	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
386	}
387	break;
388
389	case 6:
390	switch (bModel)
391	{
392	case 0: return kCpumMicroarch_Cyrix_M2;
393	}
394	break;
395
396	}
397	return kCpumMicroarch_Cyrix_Unknown;
398	}
399
400	return kCpumMicroarch_Unknown;
401	}
402
403
404	/**
405	* Translates a microarchitecture enum value to the corresponding string
406	* constant.
407	*
408	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
409	* NULL if the value is invalid.
410	*
411	* @param enmMicroarch The enum value to convert.
412	*/
413	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
414	{
415	switch (enmMicroarch)
416	{
417	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
418	CASE_RET_STR(kCpumMicroarch_Intel_8086);
419	CASE_RET_STR(kCpumMicroarch_Intel_80186);
420	CASE_RET_STR(kCpumMicroarch_Intel_80286);
421	CASE_RET_STR(kCpumMicroarch_Intel_80386);
422	CASE_RET_STR(kCpumMicroarch_Intel_80486);
423	CASE_RET_STR(kCpumMicroarch_Intel_P5);
424
425	CASE_RET_STR(kCpumMicroarch_Intel_P6);
426	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
427	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
428
429	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
430	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
431	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
432
433	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
434	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
435
436	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
437	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
438	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
439	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
440	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
441	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
442	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
443	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Cannonlake);
444
445	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
446	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
447	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
448	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
449	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
450	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
451	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
452
453	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
454	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
455	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
456	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
457	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
458	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
459	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
460
461	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
462
463	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
464	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
465	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
466	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
467	CASE_RET_STR(kCpumMicroarch_AMD_K5);
468	CASE_RET_STR(kCpumMicroarch_AMD_K6);
469
470	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
471	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
472	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
473	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
474	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
475	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
476	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
477
478	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
479	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
480	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
481	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
482	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
483
484	CASE_RET_STR(kCpumMicroarch_AMD_K10);
485	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
486	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
487	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
488	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
489
490	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
491	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
492	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
493	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
494	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
495
496	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
497
498	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
499
500	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
501
502	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
503	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
504	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
505	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
506	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
507	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
508	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
509	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
510	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
511	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
512	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
513	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
514	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
515
516	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
517	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
518	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
519	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
520	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
521	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
522
523	CASE_RET_STR(kCpumMicroarch_NEC_V20);
524	CASE_RET_STR(kCpumMicroarch_NEC_V30);
525
526	CASE_RET_STR(kCpumMicroarch_Unknown);
527
528	#undef CASE_RET_STR
529	case kCpumMicroarch_Invalid:
530	case kCpumMicroarch_Intel_End:
531	case kCpumMicroarch_Intel_Core2_End:
532	case kCpumMicroarch_Intel_Core7_End:
533	case kCpumMicroarch_Intel_Atom_End:
534	case kCpumMicroarch_Intel_P6_Core_Atom_End:
535	case kCpumMicroarch_Intel_NB_End:
536	case kCpumMicroarch_AMD_K7_End:
537	case kCpumMicroarch_AMD_K8_End:
538	case kCpumMicroarch_AMD_15h_End:
539	case kCpumMicroarch_AMD_16h_End:
540	case kCpumMicroarch_AMD_Zen_End:
541	case kCpumMicroarch_AMD_End:
542	case kCpumMicroarch_VIA_End:
543	case kCpumMicroarch_Cyrix_End:
544	case kCpumMicroarch_NEC_End:
545	case kCpumMicroarch_32BitHack:
546	break;
547	/* no default! */
548	}
549
550	return NULL;
551	}
552
553
554	/**
555	* Determins the host CPU MXCSR mask.
556	*
557	* @returns MXCSR mask.
558	*/
559	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
560	{
561	if ( ASMHasCpuId()
562	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
563	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
564	{
565	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
566	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
567	RT_ZERO(*pState);
568	ASMFxSave(pState);
569	if (pState->MXCSR_MASK == 0)
570	return 0xffbf;
571	return pState->MXCSR_MASK;
572	}
573	return 0;
574	}
575
576
577	/**
578	* Gets a matching leaf in the CPUID leaf array.
579	*
580	* @returns Pointer to the matching leaf, or NULL if not found.
581	* @param paLeaves The CPUID leaves to search. This is sorted.
582	* @param cLeaves The number of leaves in the array.
583	* @param uLeaf The leaf to locate.
584	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
585	*/
586	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
587	{
588	/* Lazy bird does linear lookup here since this is only used for the
589	occational CPUID overrides. */
590	for (uint32_t i = 0; i < cLeaves; i++)
591	if ( paLeaves[i].uLeaf == uLeaf
592	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
593	return &paLeaves[i];
594	return NULL;
595	}
596
597
598	#ifndef IN_VBOX_CPU_REPORT
599	/**
600	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
601	*
602	* @returns true if found, false it not.
603	* @param paLeaves The CPUID leaves to search. This is sorted.
604	* @param cLeaves The number of leaves in the array.
605	* @param uLeaf The leaf to locate.
606	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
607	* @param pLegacy The legacy output leaf.
608	*/
609	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
610	PCPUMCPUID pLegacy)
611	{
612	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
613	if (pLeaf)
614	{
615	pLegacy->uEax = pLeaf->uEax;
616	pLegacy->uEbx = pLeaf->uEbx;
617	pLegacy->uEcx = pLeaf->uEcx;
618	pLegacy->uEdx = pLeaf->uEdx;
619	return true;
620	}
621	return false;
622	}
623	#endif /* IN_VBOX_CPU_REPORT */
624
625
626	/**
627	* Ensures that the CPUID leaf array can hold one more leaf.
628	*
629	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
630	* failure.
631	* @param pVM The cross context VM structure. If NULL, use
632	* the process heap, otherwise the VM's hyper heap.
633	* @param ppaLeaves Pointer to the variable holding the array pointer
634	* (input/output).
635	* @param cLeaves The current array size.
636	*
637	* @remarks This function will automatically update the R0 and RC pointers when
638	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
639	* be the corresponding VM's CPUID arrays (which is asserted).
640	*/
641	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
642	{
643	/*
644	* If pVM is not specified, we're on the regular heap and can waste a
645	* little space to speed things up.
646	*/
647	uint32_t cAllocated;
648	if (!pVM)
649	{
650	cAllocated = RT_ALIGN(cLeaves, 16);
651	if (cLeaves + 1 > cAllocated)
652	{
653	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
654	if (pvNew)
655	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
656	else
657	{
658	RTMemFree(*ppaLeaves);
659	*ppaLeaves = NULL;
660	}
661	}
662	}
663	/*
664	* Otherwise, we're on the hyper heap and are probably just inserting
665	* one or two leaves and should conserve space.
666	*/
667	else
668	{
669	#ifdef IN_VBOX_CPU_REPORT
670	AssertReleaseFailed();
671	#else
672	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
673	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
674
675	size_t cb = cLeaves * sizeof(**ppaLeaves);
676	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
677	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
678	if (RT_SUCCESS(rc))
679	{
680	/* Update the R0 and RC pointers. */
681	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
682	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
683	}
684	else
685	{
686	*ppaLeaves = NULL;
687	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
688	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
689	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
690	}
691	#endif
692	}
693	return *ppaLeaves;
694	}
695
696
697	/**
698	* Append a CPUID leaf or sub-leaf.
699	*
700	* ASSUMES linear insertion order, so we'll won't need to do any searching or
701	* replace anything. Use cpumR3CpuIdInsert() for those cases.
702	*
703	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
704	* the caller need do no more work.
705	* @param ppaLeaves Pointer to the pointer to the array of sorted
706	* CPUID leaves and sub-leaves.
707	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
708	* @param uLeaf The leaf we're adding.
709	* @param uSubLeaf The sub-leaf number.
710	* @param fSubLeafMask The sub-leaf mask.
711	* @param uEax The EAX value.
712	* @param uEbx The EBX value.
713	* @param uEcx The ECX value.
714	* @param uEdx The EDX value.
715	* @param fFlags The flags.
716	*/
717	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
718	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
719	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
720	{
721	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
722	return VERR_NO_MEMORY;
723
724	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
725	Assert( *pcLeaves == 0
726	\|\| pNew[-1].uLeaf < uLeaf
727	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
728
729	pNew->uLeaf = uLeaf;
730	pNew->uSubLeaf = uSubLeaf;
731	pNew->fSubLeafMask = fSubLeafMask;
732	pNew->uEax = uEax;
733	pNew->uEbx = uEbx;
734	pNew->uEcx = uEcx;
735	pNew->uEdx = uEdx;
736	pNew->fFlags = fFlags;
737
738	*pcLeaves += 1;
739	return VINF_SUCCESS;
740	}
741
742
743	/**
744	* Checks that we've updated the CPUID leaves array correctly.
745	*
746	* This is a no-op in non-strict builds.
747	*
748	* @param paLeaves The leaves array.
749	* @param cLeaves The number of leaves.
750	*/
751	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
752	{
753	#ifdef VBOX_STRICT
754	for (uint32_t i = 1; i < cLeaves; i++)
755	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
756	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
757	else
758	{
759	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
760	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
761	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
762	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
763	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
764	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
765	}
766	#else
767	NOREF(paLeaves);
768	NOREF(cLeaves);
769	#endif
770	}
771
772
773	/**
774	* Inserts a CPU ID leaf, replacing any existing ones.
775	*
776	* When inserting a simple leaf where we already got a series of sub-leaves with
777	* the same leaf number (eax), the simple leaf will replace the whole series.
778	*
779	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
780	* host-context heap and has only been allocated/reallocated by the
781	* cpumR3CpuIdEnsureSpace function.
782	*
783	* @returns VBox status code.
784	* @param pVM The cross context VM structure. If NULL, use
785	* the process heap, otherwise the VM's hyper heap.
786	* @param ppaLeaves Pointer to the pointer to the array of sorted
787	* CPUID leaves and sub-leaves. Must be NULL if using
788	* the hyper heap.
789	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
790	* be NULL if using the hyper heap.
791	* @param pNewLeaf Pointer to the data of the new leaf we're about to
792	* insert.
793	*/
794	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
795	{
796	/*
797	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
798	*/
799	if (pVM)
800	{
801	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
802	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
803
804	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
805	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
806	}
807
808	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
809	uint32_t cLeaves = *pcLeaves;
810
811	/*
812	* Validate the new leaf a little.
813	*/
814	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
815	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
816	VERR_INVALID_FLAGS);
817	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
818	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
819	VERR_INVALID_PARAMETER);
820	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
821	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
822	VERR_INVALID_PARAMETER);
823	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
824	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
825	VERR_INVALID_PARAMETER);
826
827	/*
828	* Find insertion point. The lazy bird uses the same excuse as in
829	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
830	*/
831	uint32_t i;
832	if ( cLeaves > 0
833	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
834	{
835	/* Add at end. */
836	i = cLeaves;
837	}
838	else if ( cLeaves > 0
839	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
840	{
841	/* Either replacing the last leaf or dealing with sub-leaves. Spool
842	back to the first sub-leaf to pretend we did the linear search. */
843	i = cLeaves - 1;
844	while ( i > 0
845	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
846	i--;
847	}
848	else
849	{
850	/* Linear search from the start. */
851	i = 0;
852	while ( i < cLeaves
853	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
854	i++;
855	}
856	if ( i < cLeaves
857	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
858	{
859	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
860	{
861	/*
862	* The sub-leaf mask differs, replace all existing leaves with the
863	* same leaf number.
864	*/
865	uint32_t c = 1;
866	while ( i + c < cLeaves
867	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
868	c++;
869	if (c > 1 && i + c < cLeaves)
870	{
871	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
872	*pcLeaves = cLeaves -= c - 1;
873	}
874
875	paLeaves[i] = *pNewLeaf;
876	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
877	return VINF_SUCCESS;
878	}
879
880	/* Find sub-leaf insertion point. */
881	while ( i < cLeaves
882	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
883	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
884	i++;
885
886	/*
887	* If we've got an exactly matching leaf, replace it.
888	*/
889	if ( i < cLeaves
890	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
891	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
892	{
893	paLeaves[i] = *pNewLeaf;
894	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
895	return VINF_SUCCESS;
896	}
897	}
898
899	/*
900	* Adding a new leaf at 'i'.
901	*/
902	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
903	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
904	if (!paLeaves)
905	return VERR_NO_MEMORY;
906
907	if (i < cLeaves)
908	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
909	*pcLeaves += 1;
910	paLeaves[i] = *pNewLeaf;
911
912	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
913	return VINF_SUCCESS;
914	}
915
916
917	#ifndef IN_VBOX_CPU_REPORT
918	/**
919	* Removes a range of CPUID leaves.
920	*
921	* This will not reallocate the array.
922	*
923	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
924	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
925	* @param uFirst The first leaf.
926	* @param uLast The last leaf.
927	*/
928	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
929	{
930	uint32_t cLeaves = *pcLeaves;
931
932	Assert(uFirst <= uLast);
933
934	/*
935	* Find the first one.
936	*/
937	uint32_t iFirst = 0;
938	while ( iFirst < cLeaves
939	&& paLeaves[iFirst].uLeaf < uFirst)
940	iFirst++;
941
942	/*
943	* Find the end (last + 1).
944	*/
945	uint32_t iEnd = iFirst;
946	while ( iEnd < cLeaves
947	&& paLeaves[iEnd].uLeaf <= uLast)
948	iEnd++;
949
950	/*
951	* Adjust the array if anything needs removing.
952	*/
953	if (iFirst < iEnd)
954	{
955	if (iEnd < cLeaves)
956	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
957	*pcLeaves = cLeaves -= (iEnd - iFirst);
958	}
959
960	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
961	}
962	#endif /* IN_VBOX_CPU_REPORT */
963
964
965	/**
966	* Checks if ECX make a difference when reading a given CPUID leaf.
967	*
968	* @returns @c true if it does, @c false if it doesn't.
969	* @param uLeaf The leaf we're reading.
970	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
971	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
972	* final sub-leaf (for leaf 0xb only).
973	*/
974	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
975	{
976	*pfFinalEcxUnchanged = false;
977
978	uint32_t auCur[4];
979	uint32_t auPrev[4];
980	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
981
982	/* Look for sub-leaves. */
983	uint32_t uSubLeaf = 1;
984	for (;;)
985	{
986	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
987	if (memcmp(auCur, auPrev, sizeof(auCur)))
988	break;
989
990	/* Advance / give up. */
991	uSubLeaf++;
992	if (uSubLeaf >= 64)
993	{
994	*pcSubLeaves = 1;
995	return false;
996	}
997	}
998
999	/* Count sub-leaves. */
1000	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1001	uint32_t cRepeats = 0;
1002	uSubLeaf = 0;
1003	for (;;)
1004	{
1005	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1006
1007	/* Figuring out when to stop isn't entirely straight forward as we need
1008	to cover undocumented behavior up to a point and implementation shortcuts. */
1009
1010	/* 1. Look for more than 4 repeating value sets. */
1011	if ( auCur[0] == auPrev[0]
1012	&& auCur[1] == auPrev[1]
1013	&& ( auCur[2] == auPrev[2]
1014	\|\| ( auCur[2] == uSubLeaf
1015	&& auPrev[2] == uSubLeaf - 1) )
1016	&& auCur[3] == auPrev[3])
1017	{
1018	if ( uLeaf != 0xd
1019	\|\| uSubLeaf >= 64
1020	\|\| ( auCur[0] == 0
1021	&& auCur[1] == 0
1022	&& auCur[2] == 0
1023	&& auCur[3] == 0
1024	&& auPrev[2] == 0) )
1025	cRepeats++;
1026	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1027	break;
1028	}
1029	else
1030	cRepeats = 0;
1031
1032	/* 2. Look for zero values. */
1033	if ( auCur[0] == 0
1034	&& auCur[1] == 0
1035	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1036	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1037	&& uSubLeaf >= cMinLeaves)
1038	{
1039	cRepeats = 0;
1040	break;
1041	}
1042
1043	/* 3. Leaf 0xb level type 0 check. */
1044	if ( uLeaf == 0xb
1045	&& (auCur[2] & 0xff00) == 0
1046	&& (auPrev[2] & 0xff00) == 0)
1047	{
1048	cRepeats = 0;
1049	break;
1050	}
1051
1052	/* 99. Give up. */
1053	if (uSubLeaf >= 128)
1054	{
1055	#ifndef IN_VBOX_CPU_REPORT
1056	/* Ok, limit it according to the documentation if possible just to
1057	avoid annoying users with these detection issues. */
1058	uint32_t cDocLimit = UINT32_MAX;
1059	if (uLeaf == 0x4)
1060	cDocLimit = 4;
1061	else if (uLeaf == 0x7)
1062	cDocLimit = 1;
1063	else if (uLeaf == 0xd)
1064	cDocLimit = 63;
1065	else if (uLeaf == 0xf)
1066	cDocLimit = 2;
1067	if (cDocLimit != UINT32_MAX)
1068	{
1069	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1070	*pcSubLeaves = cDocLimit + 3;
1071	return true;
1072	}
1073	#endif
1074	*pcSubLeaves = UINT32_MAX;
1075	return true;
1076	}
1077
1078	/* Advance. */
1079	uSubLeaf++;
1080	memcpy(auPrev, auCur, sizeof(auCur));
1081	}
1082
1083	/* Standard exit. */
1084	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1085	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1086	if (*pcSubLeaves == 0)
1087	*pcSubLeaves = 1;
1088	return true;
1089	}
1090
1091
1092	/**
1093	* Gets a CPU ID leaf.
1094	*
1095	* @returns VBox status code.
1096	* @param pVM The cross context VM structure.
1097	* @param pLeaf Where to store the found leaf.
1098	* @param uLeaf The leaf to locate.
1099	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1100	*/
1101	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1102	{
1103	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1104	uLeaf, uSubLeaf);
1105	if (pcLeaf)
1106	{
1107	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1108	return VINF_SUCCESS;
1109	}
1110
1111	return VERR_NOT_FOUND;
1112	}
1113
1114
1115	/**
1116	* Inserts a CPU ID leaf, replacing any existing ones.
1117	*
1118	* @returns VBox status code.
1119	* @param pVM The cross context VM structure.
1120	* @param pNewLeaf Pointer to the leaf being inserted.
1121	*/
1122	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1123	{
1124	/*
1125	* Validate parameters.
1126	*/
1127	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1128	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1129
1130	/*
1131	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1132	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1133	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1134	*/
1135	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1136	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1137	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1138	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1139	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1140	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1141	{
1142	return VERR_NOT_SUPPORTED;
1143	}
1144
1145	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1146	}
1147
1148	/**
1149	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1150	*
1151	* @returns VBox status code.
1152	* @param ppaLeaves Where to return the array pointer on success.
1153	* Use RTMemFree to release.
1154	* @param pcLeaves Where to return the size of the array on
1155	* success.
1156	*/
1157	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1158	{
1159	*ppaLeaves = NULL;
1160	*pcLeaves = 0;
1161
1162	/*
1163	* Try out various candidates. This must be sorted!
1164	*/
1165	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1166	{
1167	{ UINT32_C(0x00000000), false },
1168	{ UINT32_C(0x10000000), false },
1169	{ UINT32_C(0x20000000), false },
1170	{ UINT32_C(0x30000000), false },
1171	{ UINT32_C(0x40000000), false },
1172	{ UINT32_C(0x50000000), false },
1173	{ UINT32_C(0x60000000), false },
1174	{ UINT32_C(0x70000000), false },
1175	{ UINT32_C(0x80000000), false },
1176	{ UINT32_C(0x80860000), false },
1177	{ UINT32_C(0x8ffffffe), true },
1178	{ UINT32_C(0x8fffffff), true },
1179	{ UINT32_C(0x90000000), false },
1180	{ UINT32_C(0xa0000000), false },
1181	{ UINT32_C(0xb0000000), false },
1182	{ UINT32_C(0xc0000000), false },
1183	{ UINT32_C(0xd0000000), false },
1184	{ UINT32_C(0xe0000000), false },
1185	{ UINT32_C(0xf0000000), false },
1186	};
1187
1188	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1189	{
1190	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1191	uint32_t uEax, uEbx, uEcx, uEdx;
1192	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1193
1194	/*
1195	* Does EAX look like a typical leaf count value?
1196	*/
1197	if ( uEax > uLeaf
1198	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1199	{
1200	/* Yes, dump them. */
1201	uint32_t cLeaves = uEax - uLeaf + 1;
1202	while (cLeaves-- > 0)
1203	{
1204	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1205
1206	uint32_t fFlags = 0;
1207
1208	/* There are currently three known leaves containing an APIC ID
1209	that needs EMT specific attention */
1210	if (uLeaf == 1)
1211	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1212	else if (uLeaf == 0xb && uEcx != 0)
1213	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1214	else if ( uLeaf == UINT32_C(0x8000001e)
1215	&& ( uEax
1216	\|\| uEbx
1217	\|\| uEdx
1218	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1219	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1220
1221	/* The APIC bit is per-VCpu and needs flagging. */
1222	if (uLeaf == 1)
1223	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1224	else if ( uLeaf == UINT32_C(0x80000001)
1225	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1226	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1227	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1228
1229	/* Check three times here to reduce the chance of CPU migration
1230	resulting in false positives with things like the APIC ID. */
1231	uint32_t cSubLeaves;
1232	bool fFinalEcxUnchanged;
1233	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1234	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1235	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1236	{
1237	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1238	{
1239	/* This shouldn't happen. But in case it does, file all
1240	relevant details in the release log. */
1241	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1242	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1243	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1244	{
1245	uint32_t auTmp[4];
1246	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1247	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1248	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1249	}
1250	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1251	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1252	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1253	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1254	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1255	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1256	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1257	}
1258
1259	if (fFinalEcxUnchanged)
1260	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1261
1262	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1263	{
1264	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1265	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1266	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1267	if (RT_FAILURE(rc))
1268	return rc;
1269	}
1270	}
1271	else
1272	{
1273	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1274	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1275	if (RT_FAILURE(rc))
1276	return rc;
1277	}
1278
1279	/* next */
1280	uLeaf++;
1281	}
1282	}
1283	/*
1284	* Special CPUIDs needs special handling as they don't follow the
1285	* leaf count principle used above.
1286	*/
1287	else if (s_aCandidates[iOuter].fSpecial)
1288	{
1289	bool fKeep = false;
1290	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1291	fKeep = true;
1292	else if ( uLeaf == 0x8fffffff
1293	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1294	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1295	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1296	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1297	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1298	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1299	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1300	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1301	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1302	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1303	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1304	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1305	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1306	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1307	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1308	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1309	fKeep = true;
1310	if (fKeep)
1311	{
1312	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1313	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1314	if (RT_FAILURE(rc))
1315	return rc;
1316	}
1317	}
1318	}
1319
1320	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1321	return VINF_SUCCESS;
1322	}
1323
1324
1325	/**
1326	* Determines the method the CPU uses to handle unknown CPUID leaves.
1327	*
1328	* @returns VBox status code.
1329	* @param penmUnknownMethod Where to return the method.
1330	* @param pDefUnknown Where to return default unknown values. This
1331	* will be set, even if the resulting method
1332	* doesn't actually needs it.
1333	*/
1334	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1335	{
1336	uint32_t uLastStd = ASMCpuId_EAX(0);
1337	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1338	if (!ASMIsValidExtRange(uLastExt))
1339	uLastExt = 0x80000000;
1340
1341	uint32_t auChecks[] =
1342	{
1343	uLastStd + 1,
1344	uLastStd + 5,
1345	uLastStd + 8,
1346	uLastStd + 32,
1347	uLastStd + 251,
1348	uLastExt + 1,
1349	uLastExt + 8,
1350	uLastExt + 15,
1351	uLastExt + 63,
1352	uLastExt + 255,
1353	0x7fbbffcc,
1354	0x833f7872,
1355	0xefff2353,
1356	0x35779456,
1357	0x1ef6d33e,
1358	};
1359
1360	static const uint32_t s_auValues[] =
1361	{
1362	0xa95d2156,
1363	0x00000001,
1364	0x00000002,
1365	0x00000008,
1366	0x00000000,
1367	0x55773399,
1368	0x93401769,
1369	0x12039587,
1370	};
1371
1372	/*
1373	* Simple method, all zeros.
1374	*/
1375	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1376	pDefUnknown->uEax = 0;
1377	pDefUnknown->uEbx = 0;
1378	pDefUnknown->uEcx = 0;
1379	pDefUnknown->uEdx = 0;
1380
1381	/*
1382	* Intel has been observed returning the last standard leaf.
1383	*/
1384	uint32_t auLast[4];
1385	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1386
1387	uint32_t cChecks = RT_ELEMENTS(auChecks);
1388	while (cChecks > 0)
1389	{
1390	uint32_t auCur[4];
1391	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1392	if (memcmp(auCur, auLast, sizeof(auCur)))
1393	break;
1394	cChecks--;
1395	}
1396	if (cChecks == 0)
1397	{
1398	/* Now, what happens when the input changes? Esp. ECX. */
1399	uint32_t cTotal = 0;
1400	uint32_t cSame = 0;
1401	uint32_t cLastWithEcx = 0;
1402	uint32_t cNeither = 0;
1403	uint32_t cValues = RT_ELEMENTS(s_auValues);
1404	while (cValues > 0)
1405	{
1406	uint32_t uValue = s_auValues[cValues - 1];
1407	uint32_t auLastWithEcx[4];
1408	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1409	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1410
1411	cChecks = RT_ELEMENTS(auChecks);
1412	while (cChecks > 0)
1413	{
1414	uint32_t auCur[4];
1415	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1416	if (!memcmp(auCur, auLast, sizeof(auCur)))
1417	{
1418	cSame++;
1419	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1420	cLastWithEcx++;
1421	}
1422	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1423	cLastWithEcx++;
1424	else
1425	cNeither++;
1426	cTotal++;
1427	cChecks--;
1428	}
1429	cValues--;
1430	}
1431
1432	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1433	if (cSame == cTotal)
1434	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1435	else if (cLastWithEcx == cTotal)
1436	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1437	else
1438	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1439	pDefUnknown->uEax = auLast[0];
1440	pDefUnknown->uEbx = auLast[1];
1441	pDefUnknown->uEcx = auLast[2];
1442	pDefUnknown->uEdx = auLast[3];
1443	return VINF_SUCCESS;
1444	}
1445
1446	/*
1447	* Unchanged register values?
1448	*/
1449	cChecks = RT_ELEMENTS(auChecks);
1450	while (cChecks > 0)
1451	{
1452	uint32_t const uLeaf = auChecks[cChecks - 1];
1453	uint32_t cValues = RT_ELEMENTS(s_auValues);
1454	while (cValues > 0)
1455	{
1456	uint32_t uValue = s_auValues[cValues - 1];
1457	uint32_t auCur[4];
1458	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1459	if ( auCur[0] != uLeaf
1460	\|\| auCur[1] != uValue
1461	\|\| auCur[2] != uValue
1462	\|\| auCur[3] != uValue)
1463	break;
1464	cValues--;
1465	}
1466	if (cValues != 0)
1467	break;
1468	cChecks--;
1469	}
1470	if (cChecks == 0)
1471	{
1472	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1473	return VINF_SUCCESS;
1474	}
1475
1476	/*
1477	* Just go with the simple method.
1478	*/
1479	return VINF_SUCCESS;
1480	}
1481
1482
1483	/**
1484	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1485	*
1486	* @returns Read only name string.
1487	* @param enmUnknownMethod The method to translate.
1488	*/
1489	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1490	{
1491	switch (enmUnknownMethod)
1492	{
1493	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1494	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1495	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1496	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1497
1498	case CPUMUNKNOWNCPUID_INVALID:
1499	case CPUMUNKNOWNCPUID_END:
1500	case CPUMUNKNOWNCPUID_32BIT_HACK:
1501	break;
1502	}
1503	return "Invalid-unknown-CPUID-method";
1504	}
1505
1506
1507	/**
1508	* Detect the CPU vendor give n the
1509	*
1510	* @returns The vendor.
1511	* @param uEAX EAX from CPUID(0).
1512	* @param uEBX EBX from CPUID(0).
1513	* @param uECX ECX from CPUID(0).
1514	* @param uEDX EDX from CPUID(0).
1515	*/
1516	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1517	{
1518	if (ASMIsValidStdRange(uEAX))
1519	{
1520	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1521	return CPUMCPUVENDOR_AMD;
1522
1523	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1524	return CPUMCPUVENDOR_INTEL;
1525
1526	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1527	return CPUMCPUVENDOR_VIA;
1528
1529	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1530	&& uECX == UINT32_C(0x64616574)
1531	&& uEDX == UINT32_C(0x736E4978))
1532	return CPUMCPUVENDOR_CYRIX;
1533
1534	/* "Geode by NSC", example: family 5, model 9. */
1535
1536	/** @todo detect the other buggers... */
1537	}
1538
1539	return CPUMCPUVENDOR_UNKNOWN;
1540	}
1541
1542
1543	/**
1544	* Translates a CPU vendor enum value into the corresponding string constant.
1545	*
1546	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1547	* value name. This can be useful when generating code.
1548	*
1549	* @returns Read only name string.
1550	* @param enmVendor The CPU vendor value.
1551	*/
1552	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1553	{
1554	switch (enmVendor)
1555	{
1556	case CPUMCPUVENDOR_INTEL: return "INTEL";
1557	case CPUMCPUVENDOR_AMD: return "AMD";
1558	case CPUMCPUVENDOR_VIA: return "VIA";
1559	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1560	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1561
1562	case CPUMCPUVENDOR_INVALID:
1563	case CPUMCPUVENDOR_32BIT_HACK:
1564	break;
1565	}
1566	return "Invalid-cpu-vendor";
1567	}
1568
1569
1570	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1571	{
1572	/* Could do binary search, doing linear now because I'm lazy. */
1573	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1574	while (cLeaves-- > 0)
1575	{
1576	if (pLeaf->uLeaf == uLeaf)
1577	return pLeaf;
1578	pLeaf++;
1579	}
1580	return NULL;
1581	}
1582
1583
1584	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1585	{
1586	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1587	if ( !pLeaf
1588	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1589	return pLeaf;
1590
1591	/* Linear sub-leaf search. Lazy as usual. */
1592	cLeaves -= pLeaf - paLeaves;
1593	while ( cLeaves-- > 0
1594	&& pLeaf->uLeaf == uLeaf)
1595	{
1596	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1597	return pLeaf;
1598	pLeaf++;
1599	}
1600
1601	return NULL;
1602	}
1603
1604
1605	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1606	{
1607	RT_ZERO(*pFeatures);
1608	if (cLeaves >= 2)
1609	{
1610	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1611	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1612	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1613	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1614	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1615	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1616
1617	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1618	pStd0Leaf->uEbx,
1619	pStd0Leaf->uEcx,
1620	pStd0Leaf->uEdx);
1621	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1622	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1623	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1624	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1625	pFeatures->uFamily,
1626	pFeatures->uModel,
1627	pFeatures->uStepping);
1628
1629	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1630	if (pLeaf)
1631	pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff;
1632	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1633	pFeatures->cMaxPhysAddrWidth = 36;
1634	else
1635	pFeatures->cMaxPhysAddrWidth = 32;
1636
1637	/* Standard features. */
1638	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1639	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1640	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1641	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1642	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1643	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1644	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1645	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1646	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1647	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1648	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1649	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1650	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1651	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1652	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1653	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1654	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1655	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1656	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1657	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1658	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1659	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1660	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1661	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1662
1663	/* Structured extended features. */
1664	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1665	if (pSxfLeaf0)
1666	{
1667	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1668	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1669	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1670	}
1671
1672	/* MWAIT/MONITOR leaf. */
1673	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1674	if (pMWaitLeaf)
1675	{
1676	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1677	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1678	}
1679
1680	/* Extended features. */
1681	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1682	if (pExtLeaf)
1683	{
1684	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1685	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1686	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1687	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1688	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1689	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1690	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1691	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1692	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1693	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1694	}
1695
1696	if ( pExtLeaf
1697	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1698	{
1699	/* AMD features. */
1700	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1701	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1702	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1703	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1704	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1705	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1706	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1707	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1708	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1709	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1710	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1711	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1712	if (pFeatures->fSvm)
1713	{
1714	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1715	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1716	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1717	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1718	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1719	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1720	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1721	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1722	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1723	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1724	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1725	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1726	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1727	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1728	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1729	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1730	}
1731	}
1732
1733	/*
1734	* Quirks.
1735	*/
1736	pFeatures->fLeakyFxSR = pExtLeaf
1737	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1738	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1739	&& pFeatures->uFamily >= 6 /* K7 and up */;
1740
1741	/*
1742	* Max extended (/FPU) state.
1743	*/
1744	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1745	if (pFeatures->fXSaveRstor)
1746	{
1747	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1748	if (pXStateLeaf0)
1749	{
1750	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1751	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1752	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1753	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1754	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1755	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1756	{
1757	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1758
1759	/* (paranoia:) */
1760	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1761	if ( pXStateLeaf1
1762	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1763	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1764	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1765	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1766	}
1767	else
1768	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1769	pFeatures->fXSaveRstor = 0);
1770	}
1771	else
1772	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1773	pFeatures->fXSaveRstor = 0);
1774	}
1775	}
1776	else
1777	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1778	return VINF_SUCCESS;
1779	}
1780
1781
1782	/*
1783	*
1784	* Init related code.
1785	* Init related code.
1786	* Init related code.
1787	*
1788	*
1789	*/
1790	#ifdef VBOX_IN_VMM
1791
1792
1793	/**
1794	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1795	*
1796	* This ignores the fSubLeafMask.
1797	*
1798	* @returns Pointer to the matching leaf, or NULL if not found.
1799	* @param paLeaves The CPUID leaves to search. This is sorted.
1800	* @param cLeaves The number of leaves in the array.
1801	* @param uLeaf The leaf to locate.
1802	* @param uSubLeaf The subleaf to locate.
1803	*/
1804	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1805	{
1806	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1807	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1808	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1809	if (iEnd)
1810	{
1811	uint32_t iBegin = 0;
1812	for (;;)
1813	{
1814	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1815	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1816	if (uNeedle < uCur)
1817	{
1818	if (i > iBegin)
1819	iEnd = i;
1820	else
1821	break;
1822	}
1823	else if (uNeedle > uCur)
1824	{
1825	if (i + 1 < iEnd)
1826	iBegin = i + 1;
1827	else
1828	break;
1829	}
1830	else
1831	return &paLeaves[i];
1832	}
1833	}
1834	return NULL;
1835	}
1836
1837
1838	/**
1839	* Loads MSR range overrides.
1840	*
1841	* This must be called before the MSR ranges are moved from the normal heap to
1842	* the hyper heap!
1843	*
1844	* @returns VBox status code (VMSetError called).
1845	* @param pVM The cross context VM structure.
1846	* @param pMsrNode The CFGM node with the MSR overrides.
1847	*/
1848	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1849	{
1850	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1851	{
1852	/*
1853	* Assemble a valid MSR range.
1854	*/
1855	CPUMMSRRANGE MsrRange;
1856	MsrRange.offCpumCpu = 0;
1857	MsrRange.fReserved = 0;
1858
1859	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1860	if (RT_FAILURE(rc))
1861	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1862
1863	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1864	if (RT_FAILURE(rc))
1865	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1866	MsrRange.szName, rc);
1867
1868	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1869	if (RT_FAILURE(rc))
1870	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1871	MsrRange.szName, rc);
1872
1873	char szType[32];
1874	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1875	if (RT_FAILURE(rc))
1876	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1877	MsrRange.szName, rc);
1878	if (!RTStrICmp(szType, "FixedValue"))
1879	{
1880	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1881	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1882
1883	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1884	if (RT_FAILURE(rc))
1885	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1886	MsrRange.szName, rc);
1887
1888	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1889	if (RT_FAILURE(rc))
1890	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1891	MsrRange.szName, rc);
1892
1893	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1894	if (RT_FAILURE(rc))
1895	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1896	MsrRange.szName, rc);
1897	}
1898	else
1899	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1900	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1901
1902	/*
1903	* Insert the range into the table (replaces/splits/shrinks existing
1904	* MSR ranges).
1905	*/
1906	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1907	&MsrRange);
1908	if (RT_FAILURE(rc))
1909	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
1910	}
1911
1912	return VINF_SUCCESS;
1913	}
1914
1915
1916	/**
1917	* Loads CPUID leaf overrides.
1918	*
1919	* This must be called before the CPUID leaves are moved from the normal
1920	* heap to the hyper heap!
1921	*
1922	* @returns VBox status code (VMSetError called).
1923	* @param pVM The cross context VM structure.
1924	* @param pParentNode The CFGM node with the CPUID leaves.
1925	* @param pszLabel How to label the overrides we're loading.
1926	*/
1927	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
1928	{
1929	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1930	{
1931	/*
1932	* Get the leaf and subleaf numbers.
1933	*/
1934	char szName[128];
1935	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
1936	if (RT_FAILURE(rc))
1937	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
1938
1939	/* The leaf number is either specified directly or thru the node name. */
1940	uint32_t uLeaf;
1941	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
1942	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1943	{
1944	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
1945	if (rc != VINF_SUCCESS)
1946	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
1947	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
1948	}
1949	else if (RT_FAILURE(rc))
1950	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
1951	pszLabel, szName, rc);
1952
1953	uint32_t uSubLeaf;
1954	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
1955	if (RT_FAILURE(rc))
1956	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
1957	pszLabel, szName, rc);
1958
1959	uint32_t fSubLeafMask;
1960	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
1961	if (RT_FAILURE(rc))
1962	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
1963	pszLabel, szName, rc);
1964
1965	/*
1966	* Look up the specified leaf, since the output register values
1967	* defaults to any existing values. This allows overriding a single
1968	* register, without needing to know the other values.
1969	*/
1970	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
1971	CPUMCPUIDLEAF Leaf;
1972	if (pLeaf)
1973	Leaf = *pLeaf;
1974	else
1975	RT_ZERO(Leaf);
1976	Leaf.uLeaf = uLeaf;
1977	Leaf.uSubLeaf = uSubLeaf;
1978	Leaf.fSubLeafMask = fSubLeafMask;
1979
1980	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
1981	if (RT_FAILURE(rc))
1982	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
1983	pszLabel, szName, rc);
1984	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
1985	if (RT_FAILURE(rc))
1986	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
1987	pszLabel, szName, rc);
1988	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
1989	if (RT_FAILURE(rc))
1990	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
1991	pszLabel, szName, rc);
1992	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
1993	if (RT_FAILURE(rc))
1994	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
1995	pszLabel, szName, rc);
1996
1997	/*
1998	* Insert the leaf into the table (replaces existing ones).
1999	*/
2000	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2001	&Leaf);
2002	if (RT_FAILURE(rc))
2003	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2004	}
2005
2006	return VINF_SUCCESS;
2007	}
2008
2009
2010
2011	/**
2012	* Fetches overrides for a CPUID leaf.
2013	*
2014	* @returns VBox status code.
2015	* @param pLeaf The leaf to load the overrides into.
2016	* @param pCfgNode The CFGM node containing the overrides
2017	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2018	* @param iLeaf The CPUID leaf number.
2019	*/
2020	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2021	{
2022	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2023	if (pLeafNode)
2024	{
2025	uint32_t u32;
2026	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2027	if (RT_SUCCESS(rc))
2028	pLeaf->uEax = u32;
2029	else
2030	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2031
2032	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2033	if (RT_SUCCESS(rc))
2034	pLeaf->uEbx = u32;
2035	else
2036	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2037
2038	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2039	if (RT_SUCCESS(rc))
2040	pLeaf->uEcx = u32;
2041	else
2042	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2043
2044	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2045	if (RT_SUCCESS(rc))
2046	pLeaf->uEdx = u32;
2047	else
2048	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2049
2050	}
2051	return VINF_SUCCESS;
2052	}
2053
2054
2055	/**
2056	* Load the overrides for a set of CPUID leaves.
2057	*
2058	* @returns VBox status code.
2059	* @param paLeaves The leaf array.
2060	* @param cLeaves The number of leaves.
2061	* @param uStart The start leaf number.
2062	* @param pCfgNode The CFGM node containing the overrides
2063	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2064	*/
2065	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2066	{
2067	for (uint32_t i = 0; i < cLeaves; i++)
2068	{
2069	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2070	if (RT_FAILURE(rc))
2071	return rc;
2072	}
2073
2074	return VINF_SUCCESS;
2075	}
2076
2077
2078	/**
2079	* Installs the CPUID leaves and explods the data into structures like
2080	* GuestFeatures and CPUMCTX::aoffXState.
2081	*
2082	* @returns VBox status code.
2083	* @param pVM The cross context VM structure.
2084	* @param pCpum The CPUM part of @a VM.
2085	* @param paLeaves The leaves. These will be copied (but not freed).
2086	* @param cLeaves The number of leaves.
2087	*/
2088	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
2089	{
2090	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2091
2092	/*
2093	* Install the CPUID information.
2094	*/
2095	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2096	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2097
2098	AssertLogRelRCReturn(rc, rc);
2099	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2100	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2101	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2102	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2103	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2104
2105	/*
2106	* Update the default CPUID leaf if necessary.
2107	*/
2108	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2109	{
2110	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2111	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2112	{
2113	/* We don't use CPUID(0).eax here because of the NT hack that only
2114	changes that value without actually removing any leaves. */
2115	uint32_t i = 0;
2116	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2117	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2118	{
2119	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2120	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2121	i++;
2122	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2123	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2124	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2125	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2126	}
2127	break;
2128	}
2129	default:
2130	break;
2131	}
2132
2133	/*
2134	* Explode the guest CPU features.
2135	*/
2136	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
2137	AssertLogRelRCReturn(rc, rc);
2138
2139	/*
2140	* Adjust the scalable bus frequency according to the CPUID information
2141	* we're now using.
2142	*/
2143	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2144	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2145	? UINT64_C(100000000) /* 100MHz */
2146	: UINT64_C(133333333); /* 133MHz */
2147
2148	/*
2149	* Populate the legacy arrays. Currently used for everything, later only
2150	* for patch manager.
2151	*/
2152	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2153	{
2154	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2155	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2156	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2157	};
2158	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2159	{
2160	uint32_t cLeft = aOldRanges[i].cCpuIds;
2161	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2162	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2163	while (cLeft-- > 0)
2164	{
2165	uLeaf--;
2166	pLegacyLeaf--;
2167
2168	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2169	if (pLeaf)
2170	{
2171	pLegacyLeaf->uEax = pLeaf->uEax;
2172	pLegacyLeaf->uEbx = pLeaf->uEbx;
2173	pLegacyLeaf->uEcx = pLeaf->uEcx;
2174	pLegacyLeaf->uEdx = pLeaf->uEdx;
2175	}
2176	else
2177	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2178	}
2179	}
2180
2181	/*
2182	* Configure XSAVE offsets according to the CPUID info.
2183	*/
2184	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2185	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2186	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2187	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2188	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2189	{
2190	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2191	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2192	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2193	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2194	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2195	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2196	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2197	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2198	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2199	pCpum->GuestFeatures.cbMaxExtendedState),
2200	VERR_CPUM_IPE_1);
2201	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2202	}
2203	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2204
2205	/* Copy the CPU #0 data to the other CPUs. */
2206	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2207	{
2208	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2209	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2210	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2211	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2212	}
2213
2214	return VINF_SUCCESS;
2215	}
2216
2217
2218	/** @name Instruction Set Extension Options
2219	* @{ */
2220	/** Configuration option type (extended boolean, really). */
2221	typedef uint8_t CPUMISAEXTCFG;
2222	/** Always disable the extension. */
2223	#define CPUMISAEXTCFG_DISABLED false
2224	/** Enable the extension if it's supported by the host CPU. */
2225	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2226	/** Enable the extension if it's supported by the host CPU, but don't let
2227	* the portable CPUID feature disable it. */
2228	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2229	/** Always enable the extension. */
2230	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2231	/** @} */
2232
2233	/**
2234	* CPUID Configuration (from CFGM).
2235	*
2236	* @remarks The members aren't document since we would only be duplicating the
2237	* \@cfgm entries in cpumR3CpuIdReadConfig.
2238	*/
2239	typedef struct CPUMCPUIDCONFIG
2240	{
2241	bool fNt4LeafLimit;
2242	bool fInvariantTsc;
2243	bool fForceVme;
2244
2245	CPUMISAEXTCFG enmCmpXchg16b;
2246	CPUMISAEXTCFG enmMonitor;
2247	CPUMISAEXTCFG enmMWaitExtensions;
2248	CPUMISAEXTCFG enmSse41;
2249	CPUMISAEXTCFG enmSse42;
2250	CPUMISAEXTCFG enmAvx;
2251	CPUMISAEXTCFG enmAvx2;
2252	CPUMISAEXTCFG enmXSave;
2253	CPUMISAEXTCFG enmAesNi;
2254	CPUMISAEXTCFG enmPClMul;
2255	CPUMISAEXTCFG enmPopCnt;
2256	CPUMISAEXTCFG enmMovBe;
2257	CPUMISAEXTCFG enmRdRand;
2258	CPUMISAEXTCFG enmRdSeed;
2259	CPUMISAEXTCFG enmCLFlushOpt;
2260
2261	CPUMISAEXTCFG enmAbm;
2262	CPUMISAEXTCFG enmSse4A;
2263	CPUMISAEXTCFG enmMisAlnSse;
2264	CPUMISAEXTCFG enm3dNowPrf;
2265	CPUMISAEXTCFG enmAmdExtMmx;
2266	CPUMISAEXTCFG enmSvm;
2267
2268	uint32_t uMaxStdLeaf;
2269	uint32_t uMaxExtLeaf;
2270	uint32_t uMaxCentaurLeaf;
2271	uint32_t uMaxIntelFamilyModelStep;
2272	char szCpuName[128];
2273	} CPUMCPUIDCONFIG;
2274	/** Pointer to CPUID config (from CFGM). */
2275	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2276
2277
2278	/**
2279	* Mini CPU selection support for making Mac OS X happy.
2280	*
2281	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2282	*
2283	* @param pCpum The CPUM instance data.
2284	* @param pConfig The CPUID configuration we've read from CFGM.
2285	*/
2286	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2287	{
2288	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2289	{
2290	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2291	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2292	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2293	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2294	0);
2295	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2296	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2297	{
2298	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2299	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2300	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2301	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2302	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2303	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2304	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2305	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2306	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2307	pStdFeatureLeaf->uEax = uNew;
2308	}
2309	}
2310	}
2311
2312
2313
2314	/**
2315	* Limit it the number of entries, zapping the remainder.
2316	*
2317	* The limits are masking off stuff about power saving and similar, this
2318	* is perhaps a bit crudely done as there is probably some relatively harmless
2319	* info too in these leaves (like words about having a constant TSC).
2320	*
2321	* @param pCpum The CPUM instance data.
2322	* @param pConfig The CPUID configuration we've read from CFGM.
2323	*/
2324	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2325	{
2326	/*
2327	* Standard leaves.
2328	*/
2329	uint32_t uSubLeaf = 0;
2330	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2331	if (pCurLeaf)
2332	{
2333	uint32_t uLimit = pCurLeaf->uEax;
2334	if (uLimit <= UINT32_C(0x000fffff))
2335	{
2336	if (uLimit > pConfig->uMaxStdLeaf)
2337	{
2338	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2339	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2340	uLimit + 1, UINT32_C(0x000fffff));
2341	}
2342
2343	/* NT4 hack, no zapping of extra leaves here. */
2344	if (pConfig->fNt4LeafLimit && uLimit > 3)
2345	pCurLeaf->uEax = uLimit = 3;
2346
2347	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2348	pCurLeaf->uEax = uLimit;
2349	}
2350	else
2351	{
2352	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2353	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2354	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2355	}
2356	}
2357
2358	/*
2359	* Extended leaves.
2360	*/
2361	uSubLeaf = 0;
2362	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2363	if (pCurLeaf)
2364	{
2365	uint32_t uLimit = pCurLeaf->uEax;
2366	if ( uLimit >= UINT32_C(0x80000000)
2367	&& uLimit <= UINT32_C(0x800fffff))
2368	{
2369	if (uLimit > pConfig->uMaxExtLeaf)
2370	{
2371	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2372	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2373	uLimit + 1, UINT32_C(0x800fffff));
2374	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2375	pCurLeaf->uEax = uLimit;
2376	}
2377	}
2378	else
2379	{
2380	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2381	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2382	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2383	}
2384	}
2385
2386	/*
2387	* Centaur leaves (VIA).
2388	*/
2389	uSubLeaf = 0;
2390	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2391	if (pCurLeaf)
2392	{
2393	uint32_t uLimit = pCurLeaf->uEax;
2394	if ( uLimit >= UINT32_C(0xc0000000)
2395	&& uLimit <= UINT32_C(0xc00fffff))
2396	{
2397	if (uLimit > pConfig->uMaxCentaurLeaf)
2398	{
2399	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2400	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2401	uLimit + 1, UINT32_C(0xcfffffff));
2402	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2403	pCurLeaf->uEax = uLimit;
2404	}
2405	}
2406	else
2407	{
2408	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2409	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2410	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2411	}
2412	}
2413	}
2414
2415
2416	/**
2417	* Clears a CPUID leaf and all sub-leaves (to zero).
2418	*
2419	* @param pCpum The CPUM instance data.
2420	* @param uLeaf The leaf to clear.
2421	*/
2422	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2423	{
2424	uint32_t uSubLeaf = 0;
2425	PCPUMCPUIDLEAF pCurLeaf;
2426	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2427	{
2428	pCurLeaf->uEax = 0;
2429	pCurLeaf->uEbx = 0;
2430	pCurLeaf->uEcx = 0;
2431	pCurLeaf->uEdx = 0;
2432	uSubLeaf++;
2433	}
2434	}
2435
2436
2437	/**
2438	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2439	* the given leaf.
2440	*
2441	* @returns pLeaf.
2442	* @param pCpum The CPUM instance data.
2443	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2444	*/
2445	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2446	{
2447	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2448	if (pLeaf->fSubLeafMask != 0)
2449	{
2450	/*
2451	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2452	* Log everything while we're at it.
2453	*/
2454	LogRel(("CPUM:\n"
2455	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2456	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2457	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2458	for (;;)
2459	{
2460	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2461	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2462	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2463	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2464	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2465	break;
2466	pSubLeaf++;
2467	}
2468	LogRel(("CPUM:\n"));
2469
2470	/*
2471	* Remove the offending sub-leaves.
2472	*/
2473	if (pSubLeaf != pLeaf)
2474	{
2475	if (pSubLeaf != pLast)
2476	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2477	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2478	}
2479
2480	/*
2481	* Convert the first sub-leaf into a single leaf.
2482	*/
2483	pLeaf->uSubLeaf = 0;
2484	pLeaf->fSubLeafMask = 0;
2485	}
2486	return pLeaf;
2487	}
2488
2489
2490	/**
2491	* Sanitizes and adjust the CPUID leaves.
2492	*
2493	* Drop features that aren't virtualized (or virtualizable). Adjust information
2494	* and capabilities to fit the virtualized hardware. Remove information the
2495	* guest shouldn't have (because it's wrong in the virtual world or because it
2496	* gives away host details) or that we don't have documentation for and no idea
2497	* what means.
2498	*
2499	* @returns VBox status code.
2500	* @param pVM The cross context VM structure (for cCpus).
2501	* @param pCpum The CPUM instance data.
2502	* @param pConfig The CPUID configuration we've read from CFGM.
2503	*/
2504	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2505	{
2506	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2507	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2508	{ \
2509	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2510	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2511	}
2512	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2513	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2514	{ \
2515	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2516	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2517	}
2518	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2519	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2520	&& ((a_pLeafReg) & (fBitMask)) \
2521	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2522	{ \
2523	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2524	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2525	}
2526	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2527
2528	/* Cpuid 1:
2529	* EAX: CPU model, family and stepping.
2530	*
2531	* ECX + EDX: Supported features. Only report features we can support.
2532	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2533	* options may require adjusting (i.e. stripping what was enabled).
2534	*
2535	* EBX: Branding, CLFLUSH line size, logical processors per package and
2536	* initial APIC ID.
2537	*/
2538	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2539	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2540	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2541
2542	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2543	\| X86_CPUID_FEATURE_EDX_VME
2544	\| X86_CPUID_FEATURE_EDX_DE
2545	\| X86_CPUID_FEATURE_EDX_PSE
2546	\| X86_CPUID_FEATURE_EDX_TSC
2547	\| X86_CPUID_FEATURE_EDX_MSR
2548	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2549	\| X86_CPUID_FEATURE_EDX_MCE
2550	\| X86_CPUID_FEATURE_EDX_CX8
2551	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2552	//\| RT_BIT_32(10) - not defined
2553	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2554	//\| X86_CPUID_FEATURE_EDX_SEP
2555	\| X86_CPUID_FEATURE_EDX_MTRR
2556	\| X86_CPUID_FEATURE_EDX_PGE
2557	\| X86_CPUID_FEATURE_EDX_MCA
2558	\| X86_CPUID_FEATURE_EDX_CMOV
2559	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2560	\| X86_CPUID_FEATURE_EDX_PSE36
2561	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2562	\| X86_CPUID_FEATURE_EDX_CLFSH
2563	//\| RT_BIT_32(20) - not defined
2564	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2565	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2566	\| X86_CPUID_FEATURE_EDX_MMX
2567	\| X86_CPUID_FEATURE_EDX_FXSR
2568	\| X86_CPUID_FEATURE_EDX_SSE
2569	\| X86_CPUID_FEATURE_EDX_SSE2
2570	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2571	\| X86_CPUID_FEATURE_EDX_HTT
2572	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2573	//\| RT_BIT_32(30) - not defined
2574	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2575	;
2576	pStdFeatureLeaf->uEcx &= 0
2577	\| X86_CPUID_FEATURE_ECX_SSE3
2578	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2579	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2580	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2581	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2582	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2583	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized yet.
2584	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2585	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2586	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2587	\| X86_CPUID_FEATURE_ECX_SSSE3
2588	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2589	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2590	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2591	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2592	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2593	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2594	//\| X86_CPUID_FEATURE_ECX_PCID - not implemented yet.
2595	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2596	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2597	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2598	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2599	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2600	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2601	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2602	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2603	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2604	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2605	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2606	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2607	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2608	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2609	;
2610
2611	if (pCpum->u8PortableCpuIdLevel > 0)
2612	{
2613	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2614	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2615	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2616	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2617	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2618	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2619	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2620	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2621	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2622	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2623	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2624	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2625	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2626	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2627	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2628	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2629	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2630	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2631
2632	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2633	\| X86_CPUID_FEATURE_EDX_PSN
2634	\| X86_CPUID_FEATURE_EDX_DS
2635	\| X86_CPUID_FEATURE_EDX_ACPI
2636	\| X86_CPUID_FEATURE_EDX_SS
2637	\| X86_CPUID_FEATURE_EDX_TM
2638	\| X86_CPUID_FEATURE_EDX_PBE
2639	)));
2640	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2641	\| X86_CPUID_FEATURE_ECX_CPLDS
2642	\| X86_CPUID_FEATURE_ECX_VMX
2643	\| X86_CPUID_FEATURE_ECX_SMX
2644	\| X86_CPUID_FEATURE_ECX_EST
2645	\| X86_CPUID_FEATURE_ECX_TM2
2646	\| X86_CPUID_FEATURE_ECX_CNTXID
2647	\| X86_CPUID_FEATURE_ECX_FMA
2648	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2649	\| X86_CPUID_FEATURE_ECX_PDCM
2650	\| X86_CPUID_FEATURE_ECX_DCA
2651	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2652	)));
2653	}
2654
2655	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2656	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2657
2658	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2659	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2660	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2661	*/
2662	#ifdef VBOX_WITH_MULTI_CORE
2663	if (pVM->cCpus > 1)
2664	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2665	#endif
2666	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2667	{
2668	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2669	core times the number of CPU cores per processor */
2670	#ifdef VBOX_WITH_MULTI_CORE
2671	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2672	#else
2673	/* Single logical processor in a package. */
2674	pStdFeatureLeaf->uEbx \|= (1 << 16);
2675	#endif
2676	}
2677
2678	uint32_t uMicrocodeRev;
2679	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2680	if (RT_SUCCESS(rc))
2681	{
2682	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2683	}
2684	else
2685	{
2686	uMicrocodeRev = 0;
2687	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2688	}
2689
2690	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2691	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2692	*/
2693	if ( (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen)
2694	&& uMicrocodeRev < 0x8001126
2695	&& !pConfig->fForceVme)
2696	{
2697	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2698	LogRel(("CPUM: Zen VME workaround engaged\n"));
2699	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2700	}
2701
2702	/* Force standard feature bits. */
2703	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2704	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2705	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2706	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2707	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2708	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2709	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2710	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2711	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2712	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2713	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2714	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2715	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2716	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2717	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2718	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2719	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2720	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2721	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2722	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2723	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2724	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2725
2726	pStdFeatureLeaf = NULL; /* Must refetch! */
2727
2728	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2729	* AMD:
2730	* EAX: CPU model, family and stepping.
2731	*
2732	* ECX + EDX: Supported features. Only report features we can support.
2733	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2734	* options may require adjusting (i.e. stripping what was enabled).
2735	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2736	*
2737	* EBX: Branding ID and package type (or reserved).
2738	*
2739	* Intel and probably most others:
2740	* EAX: 0
2741	* EBX: 0
2742	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2743	*/
2744	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2745	if (pExtFeatureLeaf)
2746	{
2747	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2748
2749	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2750	\| X86_CPUID_AMD_FEATURE_EDX_VME
2751	\| X86_CPUID_AMD_FEATURE_EDX_DE
2752	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2753	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2754	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2755	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2756	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2757	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2758	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2759	//\| RT_BIT_32(10) - reserved
2760	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2761	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2762	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2763	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2764	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2765	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2766	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2767	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2768	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2769	//\| RT_BIT_32(18) - reserved
2770	//\| RT_BIT_32(19) - reserved
2771	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2772	//\| RT_BIT_32(21) - reserved
2773	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2774	\| X86_CPUID_AMD_FEATURE_EDX_MMX
2775	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
2776	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
2777	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2778	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2779	//\| RT_BIT_32(28) - reserved
2780	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2781	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2782	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
2783	;
2784	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2785	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2786	\| (pConfig->enmSvm ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
2787	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2788	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
2789	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2790	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2791	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2792	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2793	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2794	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2795	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
2796	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
2797	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2798	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
2799	//\| RT_BIT_32(14) - reserved
2800	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2801	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2802	//\| RT_BIT_32(17) - reserved
2803	//\| RT_BIT_32(18) - reserved
2804	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2805	//\| RT_BIT_32(20) - reserved
2806	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2807	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2808	//\| RT_BIT_32(23) - reserved
2809	//\| RT_BIT_32(24) - reserved
2810	//\| RT_BIT_32(25) - reserved
2811	//\| RT_BIT_32(26) - reserved
2812	//\| RT_BIT_32(27) - reserved
2813	//\| RT_BIT_32(28) - reserved
2814	//\| RT_BIT_32(29) - reserved
2815	//\| RT_BIT_32(30) - reserved
2816	//\| RT_BIT_32(31) - reserved
2817	;
2818	#ifdef VBOX_WITH_MULTI_CORE
2819	if ( pVM->cCpus > 1
2820	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2821	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2822	#endif
2823
2824	if (pCpum->u8PortableCpuIdLevel > 0)
2825	{
2826	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2827	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM, pConfig->enmSvm);
2828	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2829	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2830	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2831	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2832	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2833	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2834	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2835	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2836	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2837	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2838	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2839	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2840	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2841	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2842
2843	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2844	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2845	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2846	\| X86_CPUID_AMD_FEATURE_ECX_IBS
2847	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2848	\| X86_CPUID_AMD_FEATURE_ECX_WDT
2849	\| X86_CPUID_AMD_FEATURE_ECX_LWP
2850	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
2851	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2852	\| UINT32_C(0xff964000)
2853	)));
2854	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2855	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2856	\| RT_BIT(18)
2857	\| RT_BIT(19)
2858	\| RT_BIT(21)
2859	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2860	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2861	\| RT_BIT(28)
2862	)));
2863	}
2864
2865	/* Force extended feature bits. */
2866	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2867	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
2868	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2869	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2870	if (pConfig->enmSvm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2871	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SVM;
2872	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2873	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2874	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2875	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2876	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2877	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2878	if (pConfig->enmSvm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2879	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SVM;
2880	}
2881	pExtFeatureLeaf = NULL; /* Must refetch! */
2882
2883
2884	/* Cpuid 2:
2885	* Intel: (Nondeterministic) Cache and TLB information
2886	* AMD: Reserved
2887	* VIA: Reserved
2888	* Safe to expose.
2889	*/
2890	uint32_t uSubLeaf = 0;
2891	PCPUMCPUIDLEAF pCurLeaf;
2892	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2893	{
2894	if ((pCurLeaf->uEax & 0xff) > 1)
2895	{
2896	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2897	pCurLeaf->uEax &= UINT32_C(0xffffff01);
2898	}
2899	uSubLeaf++;
2900	}
2901
2902	/* Cpuid 3:
2903	* Intel: EAX, EBX - reserved (transmeta uses these)
2904	* ECX, EDX - Processor Serial Number if available, otherwise reserved
2905	* AMD: Reserved
2906	* VIA: Reserved
2907	* Safe to expose
2908	*/
2909	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2910	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
2911	{
2912	uSubLeaf = 0;
2913	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
2914	{
2915	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2916	if (pCpum->u8PortableCpuIdLevel > 0)
2917	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2918	uSubLeaf++;
2919	}
2920	}
2921
2922	/* Cpuid 4 + ECX:
2923	* Intel: Deterministic Cache Parameters Leaf.
2924	* AMD: Reserved
2925	* VIA: Reserved
2926	* Safe to expose, except for EAX:
2927	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
2928	* Bits 31-26: Maximum number of processor cores in this physical package**
2929	* Note: These SMP values are constant regardless of ECX
2930	*/
2931	uSubLeaf = 0;
2932	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
2933	{
2934	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
2935	#ifdef VBOX_WITH_MULTI_CORE
2936	if ( pVM->cCpus > 1
2937	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2938	{
2939	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
2940	/* One logical processor with possibly multiple cores. */
2941	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
2942	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
2943	}
2944	#endif
2945	uSubLeaf++;
2946	}
2947
2948	/* Cpuid 5: Monitor/mwait Leaf
2949	* Intel: ECX, EDX - reserved
2950	* EAX, EBX - Smallest and largest monitor line size
2951	* AMD: EDX - reserved
2952	* EAX, EBX - Smallest and largest monitor line size
2953	* ECX - extensions (ignored for now)
2954	* VIA: Reserved
2955	* Safe to expose
2956	*/
2957	uSubLeaf = 0;
2958	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
2959	{
2960	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2961	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
2962	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2963
2964	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2965	if (pConfig->enmMWaitExtensions)
2966	{
2967	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
2968	/** @todo for now we just expose host's MWAIT C-states, although conceptually
2969	it shall be part of our power management virtualization model */
2970	#if 0
2971	/* MWAIT sub C-states */
2972	pCurLeaf->uEdx =
2973	(0 << 0) /* 0 in C0 */ \|
2974	(2 << 4) /* 2 in C1 */ \|
2975	(2 << 8) /* 2 in C2 */ \|
2976	(2 << 12) /* 2 in C3 */ \|
2977	(0 << 16) /* 0 in C4 */
2978	;
2979	#endif
2980	}
2981	else
2982	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2983	uSubLeaf++;
2984	}
2985
2986	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
2987	* Intel: Various stuff.
2988	* AMD: EAX, EBX, EDX - reserved.
2989	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
2990	* present. Same as intel.
2991	* VIA: ??
2992	*
2993	* We clear everything here for now.
2994	*/
2995	cpumR3CpuIdZeroLeaf(pCpum, 6);
2996
2997	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
2998	* EAX: Number of sub leaves.
2999	* EBX+ECX+EDX: Feature flags
3000	*
3001	* We only have documentation for one sub-leaf, so clear all other (no need
3002	* to remove them as such, just set them to zero).
3003	*
3004	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3005	* options may require adjusting (i.e. stripping what was enabled).
3006	*/
3007	uSubLeaf = 0;
3008	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3009	{
3010	switch (uSubLeaf)
3011	{
3012	case 0:
3013	{
3014	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3015	pCurLeaf->uEbx &= 0
3016	//\| X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
3017	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3018	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3019	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3020	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3021	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3022	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3023	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3024	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3025	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3026	//\| X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
3027	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3028	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3029	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3030	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3031	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3032	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3033	//\| RT_BIT(17) - reserved
3034	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3035	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3036	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3037	//\| RT_BIT(21) - reserved
3038	//\| RT_BIT(22) - reserved
3039	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3040	//\| RT_BIT(24) - reserved
3041	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3042	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3043	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3044	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3045	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3046	//\| RT_BIT(30) - reserved
3047	//\| RT_BIT(31) - reserved
3048	;
3049	pCurLeaf->uEcx &= 0
3050	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3051	;
3052	pCurLeaf->uEdx &= 0;
3053
3054	if (pCpum->u8PortableCpuIdLevel > 0)
3055	{
3056	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
3057	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3058	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3059	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3060	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3061	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
3062	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3063	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3064	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3065	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3066	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3067	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3068	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3069	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3070	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3071	}
3072
3073	/* Force standard feature bits. */
3074	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3075	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3076	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3077	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3078	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3079	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3080	break;
3081	}
3082
3083	default:
3084	/* Invalid index, all values are zero. */
3085	pCurLeaf->uEax = 0;
3086	pCurLeaf->uEbx = 0;
3087	pCurLeaf->uEcx = 0;
3088	pCurLeaf->uEdx = 0;
3089	break;
3090	}
3091	uSubLeaf++;
3092	}
3093
3094	/* Cpuid 8: Marked as reserved by Intel and AMD.
3095	* We zero this since we don't know what it may have been used for.
3096	*/
3097	cpumR3CpuIdZeroLeaf(pCpum, 8);
3098
3099	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3100	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3101	* EBX, ECX, EDX - reserved.
3102	* AMD: Reserved
3103	* VIA: ??
3104	*
3105	* We zero this.
3106	*/
3107	cpumR3CpuIdZeroLeaf(pCpum, 9);
3108
3109	/* Cpuid 0xa: Architectural Performance Monitor Features
3110	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3111	* EBX, ECX, EDX - reserved.
3112	* AMD: Reserved
3113	* VIA: ??
3114	*
3115	* We zero this, for now at least.
3116	*/
3117	cpumR3CpuIdZeroLeaf(pCpum, 10);
3118
3119	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3120	* Intel: EAX - APCI ID shift right for next level.
3121	* EBX - Factory configured cores/threads at this level.
3122	* ECX - Level number (same as input) and level type (1,2,0).
3123	* EDX - Extended initial APIC ID.
3124	* AMD: Reserved
3125	* VIA: ??
3126	*/
3127	uSubLeaf = 0;
3128	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3129	{
3130	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3131	{
3132	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3133	if (bLevelType == 1)
3134	{
3135	/* Thread level - we don't do threads at the moment. */
3136	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3137	pCurLeaf->uEbx = 1;
3138	}
3139	else if (bLevelType == 2)
3140	{
3141	/* Core level. */
3142	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3143	#ifdef VBOX_WITH_MULTI_CORE
3144	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3145	pCurLeaf->uEax++;
3146	#endif
3147	pCurLeaf->uEbx = pVM->cCpus;
3148	}
3149	else
3150	{
3151	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3152	pCurLeaf->uEax = 0;
3153	pCurLeaf->uEbx = 0;
3154	pCurLeaf->uEcx = 0;
3155	}
3156	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3157	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3158	}
3159	else
3160	{
3161	pCurLeaf->uEax = 0;
3162	pCurLeaf->uEbx = 0;
3163	pCurLeaf->uEcx = 0;
3164	pCurLeaf->uEdx = 0;
3165	}
3166	uSubLeaf++;
3167	}
3168
3169	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3170	* We zero this since we don't know what it may have been used for.
3171	*/
3172	cpumR3CpuIdZeroLeaf(pCpum, 12);
3173
3174	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3175	* ECX=0: EAX - Valid bits in XCR0[31:0].
3176	* EBX - Maximum state size as per current XCR0 value.
3177	* ECX - Maximum state size for all supported features.
3178	* EDX - Valid bits in XCR0[63:32].
3179	* ECX=1: EAX - Various X-features.
3180	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3181	* ECX - Valid bits in IA32_XSS[31:0].
3182	* EDX - Valid bits in IA32_XSS[63:32].
3183	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3184	* if the bit invalid all four registers are set to zero.
3185	* EAX - The state size for this feature.
3186	* EBX - The state byte offset of this feature.
3187	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3188	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3189	*
3190	* Clear them all as we don't currently implement extended CPU state.
3191	*/
3192	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3193	uint64_t fGuestXcr0Mask = 0;
3194	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3195	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3196	{
3197	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3198	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3199	fGuestXcr0Mask \|= XSAVE_C_YMM;
3200	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3201	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3202	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3203	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3204
3205	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3206	}
3207	pStdFeatureLeaf = NULL;
3208	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3209
3210	/* Work the sub-leaves. */
3211	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3212	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3213	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3214	{
3215	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3216	if (pCurLeaf)
3217	{
3218	if (fGuestXcr0Mask)
3219	{
3220	switch (uSubLeaf)
3221	{
3222	case 0:
3223	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3224	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3225	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3226	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3227	VERR_CPUM_IPE_1);
3228	cbXSaveMaxActual = pCurLeaf->uEcx;
3229	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3230	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3231	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3232	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3233	VERR_CPUM_IPE_2);
3234	continue;
3235	case 1:
3236	pCurLeaf->uEax &= 0;
3237	pCurLeaf->uEcx &= 0;
3238	pCurLeaf->uEdx &= 0;
3239	/** @todo what about checking ebx? */
3240	continue;
3241	default:
3242	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3243	{
3244	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3245	&& pCurLeaf->uEax > 0
3246	&& pCurLeaf->uEbx < cbXSaveMaxActual
3247	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3248	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3249	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3250	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3251	VERR_CPUM_IPE_2);
3252	AssertLogRel(!(pCurLeaf->uEcx & 1));
3253	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3254	pCurLeaf->uEdx = 0; /* it's reserved... */
3255	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3256	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3257	continue;
3258	}
3259	break;
3260	}
3261	}
3262
3263	/* Clear the leaf. */
3264	pCurLeaf->uEax = 0;
3265	pCurLeaf->uEbx = 0;
3266	pCurLeaf->uEcx = 0;
3267	pCurLeaf->uEdx = 0;
3268	}
3269	}
3270
3271	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3272	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3273	{
3274	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3275	if (pCurLeaf)
3276	{
3277	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3278	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3279	pCurLeaf->uEbx = cbXSaveMaxReport;
3280	pCurLeaf->uEcx = cbXSaveMaxReport;
3281	}
3282	}
3283
3284	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3285	* We zero this since we don't know what it may have been used for.
3286	*/
3287	cpumR3CpuIdZeroLeaf(pCpum, 14);
3288
3289	/* Cpuid 0xf + ECX: Platform qualifity of service monitoring (PQM).
3290	* We zero this as we don't currently virtualize PQM.
3291	*/
3292	cpumR3CpuIdZeroLeaf(pCpum, 15);
3293
3294	/* Cpuid 0x10 + ECX: Platform qualifity of service enforcement (PQE).
3295	* We zero this as we don't currently virtualize PQE.
3296	*/
3297	cpumR3CpuIdZeroLeaf(pCpum, 16);
3298
3299	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3300	* We zero this since we don't know what it may have been used for.
3301	*/
3302	cpumR3CpuIdZeroLeaf(pCpum, 17);
3303
3304	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3305	* We zero this as we don't currently virtualize this.
3306	*/
3307	cpumR3CpuIdZeroLeaf(pCpum, 18);
3308
3309	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3310	* We zero this since we don't know what it may have been used for.
3311	*/
3312	cpumR3CpuIdZeroLeaf(pCpum, 19);
3313
3314	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3315	* We zero this as we don't currently virtualize this.
3316	*/
3317	cpumR3CpuIdZeroLeaf(pCpum, 20);
3318
3319	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3320	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3321	* EAX - denominator (unsigned).
3322	* EBX - numerator (unsigned).
3323	* ECX, EDX - reserved.
3324	* AMD: Reserved / undefined / not implemented.
3325	* VIA: Reserved / undefined / not implemented.
3326	* We zero this as we don't currently virtualize this.
3327	*/
3328	cpumR3CpuIdZeroLeaf(pCpum, 21);
3329
3330	/* Cpuid 0x16: Processor frequency info
3331	* Intel: EAX - Core base frequency in MHz.
3332	* EBX - Core maximum frequency in MHz.
3333	* ECX - Bus (reference) frequency in MHz.
3334	* EDX - Reserved.
3335	* AMD: Reserved / undefined / not implemented.
3336	* VIA: Reserved / undefined / not implemented.
3337	* We zero this as we don't currently virtualize this.
3338	*/
3339	cpumR3CpuIdZeroLeaf(pCpum, 22);
3340
3341	/* Cpuid 0x17..0x10000000: Unknown.
3342	* We don't know these and what they mean, so remove them. */
3343	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3344	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3345
3346
3347	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3348	* We remove all these as we're a hypervisor and must provide our own.
3349	*/
3350	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3351	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3352
3353
3354	/* Cpuid 0x80000000 is harmless. */
3355
3356	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3357
3358	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3359
3360	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3361	* Safe to pass on to the guest.
3362	*
3363	* AMD: 0x800000005 L1 cache information
3364	* 0x800000006 L2/L3 cache information
3365	* Intel: 0x800000005 reserved
3366	* 0x800000006 L2 cache information
3367	* VIA: 0x800000005 TLB and L1 cache information
3368	* 0x800000006 L2 cache information
3369	*/
3370
3371	/* Cpuid 0x800000007: Advanced Power Management Information.
3372	* AMD: EAX: Processor feedback capabilities.
3373	* EBX: RAS capabilites.
3374	* ECX: Advanced power monitoring interface.
3375	* EDX: Enhanced power management capabilities.
3376	* Intel: EAX, EBX, ECX - reserved.
3377	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3378	* VIA: Reserved
3379	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3380	*/
3381	uSubLeaf = 0;
3382	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3383	{
3384	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3385	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3386	{
3387	pCurLeaf->uEdx &= 0
3388	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3389	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3390	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3391	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3392	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3393	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3394	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3395	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3396	#if 0 /*
3397	* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
3398	* Linux kernels blindly assume that the AMD performance counters work
3399	* if this is set for 64 bits guests. (Can't really find a CPUID feature
3400	* bit for them though.)
3401	*/
3402	/** @todo need to recheck this with new MSR emulation. */
3403	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3404	#endif
3405	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3406	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3407	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3408	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3409	\| 0;
3410	}
3411	else
3412	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3413	if (pConfig->fInvariantTsc)
3414	pCurLeaf->uEdx \|= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3415	uSubLeaf++;
3416	}
3417
3418	/* Cpuid 0x80000008:
3419	* AMD: EBX, EDX - reserved
3420	* EAX: Virtual/Physical/Guest address Size
3421	* ECX: Number of cores + APICIdCoreIdSize
3422	* Intel: EAX: Virtual/Physical address Size
3423	* EBX, ECX, EDX - reserved
3424	* VIA: EAX: Virtual/Physical address Size
3425	* EBX, ECX, EDX - reserved
3426	*
3427	* We only expose the virtual+pysical address size to the guest atm.
3428	* On AMD we set the core count, but not the apic id stuff as we're
3429	* currently not doing the apic id assignments in a complatible manner.
3430	*/
3431	uSubLeaf = 0;
3432	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3433	{
3434	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3435	pCurLeaf->uEbx = 0; /* reserved */
3436	pCurLeaf->uEdx = 0; /* reserved */
3437
3438	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3439	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3440	pCurLeaf->uEcx = 0;
3441	#ifdef VBOX_WITH_MULTI_CORE
3442	if ( pVM->cCpus > 1
3443	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3444	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3445	#endif
3446	uSubLeaf++;
3447	}
3448
3449	/* Cpuid 0x80000009: Reserved
3450	* We zero this since we don't know what it may have been used for.
3451	*/
3452	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3453
3454	/* Cpuid 0x8000000a: SVM Information
3455	* AMD: EAX - SVM revision.
3456	* EBX - Number of ASIDs.
3457	* ECX - Reserved.
3458	* EDX - SVM Feature identification.
3459	*/
3460	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3461	if (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
3462	{
3463	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3464	pSvmFeatureLeaf->uEax = 0x1;
3465	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3466	pSvmFeatureLeaf->uEcx = 0;
3467	pSvmFeatureLeaf->uEdx = 0; /** @todo Support SVM features */
3468	}
3469	else
3470	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3471
3472	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3473	* We clear these as we don't know what purpose they might have. */
3474	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3475	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3476
3477	/* Cpuid 0x80000019: TLB configuration
3478	* Seems to be harmless, pass them thru as is. */
3479
3480	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3481	* Strip anything we don't know what is or addresses feature we don't implement. */
3482	uSubLeaf = 0;
3483	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3484	{
3485	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3486	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3487	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3488	;
3489	pCurLeaf->uEbx = 0; /* reserved */
3490	pCurLeaf->uEcx = 0; /* reserved */
3491	pCurLeaf->uEdx = 0; /* reserved */
3492	uSubLeaf++;
3493	}
3494
3495	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3496	* Clear this as we don't currently virtualize this feature. */
3497	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3498
3499	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3500	* Clear this as we don't currently virtualize this feature. */
3501	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3502
3503	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3504	* We need to sanitize the cores per cache (EAX[25:14]).
3505	*
3506	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3507	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3508	* slightly different meaning.
3509	*/
3510	uSubLeaf = 0;
3511	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3512	{
3513	#ifdef VBOX_WITH_MULTI_CORE
3514	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3515	if (cCores > pVM->cCpus)
3516	cCores = pVM->cCpus;
3517	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3518	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3519	#else
3520	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3521	#endif
3522	uSubLeaf++;
3523	}
3524
3525	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3526	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3527	* setup, we have one compute unit with all the cores in it. Single node.
3528	*/
3529	uSubLeaf = 0;
3530	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3531	{
3532	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3533	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3534	{
3535	#ifdef VBOX_WITH_MULTI_CORE
3536	pCurLeaf->uEbx = pVM->cCpus < 0x100
3537	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3538	#else
3539	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3540	#endif
3541	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3542	}
3543	else
3544	{
3545	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3546	pCurLeaf->uEbx = 0; /* Reserved. */
3547	pCurLeaf->uEcx = 0; /* Reserved. */
3548	}
3549	pCurLeaf->uEdx = 0; /* Reserved. */
3550	uSubLeaf++;
3551	}
3552
3553	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3554	* We don't know these and what they mean, so remove them. */
3555	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3556	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3557
3558	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3559	* Just pass it thru for now. */
3560
3561	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3562	* Just pass it thru for now. */
3563
3564	/* Cpuid 0xc0000000: Centaur stuff.
3565	* Harmless, pass it thru. */
3566
3567	/* Cpuid 0xc0000001: Centaur features.
3568	* VIA: EAX - Family, model, stepping.
3569	* EDX - Centaur extended feature flags. Nothing interesting, except may
3570	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3571	* EBX, ECX - reserved.
3572	* We keep EAX but strips the rest.
3573	*/
3574	uSubLeaf = 0;
3575	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3576	{
3577	pCurLeaf->uEbx = 0;
3578	pCurLeaf->uEcx = 0;
3579	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3580	uSubLeaf++;
3581	}
3582
3583	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3584	* We only have fixed stale values, but should be harmless. */
3585
3586	/* Cpuid 0xc0000003: Reserved.
3587	* We zero this since we don't know what it may have been used for.
3588	*/
3589	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3590
3591	/* Cpuid 0xc0000004: Centaur Performance Info.
3592	* We only have fixed stale values, but should be harmless. */
3593
3594
3595	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3596	* We don't know these and what they mean, so remove them. */
3597	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3598	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3599
3600	return VINF_SUCCESS;
3601	#undef PORTABLE_DISABLE_FEATURE_BIT
3602	#undef PORTABLE_CLEAR_BITS_WHEN
3603	}
3604
3605
3606	/**
3607	* Reads a value in /CPUM/IsaExts/ node.
3608	*
3609	* @returns VBox status code (error message raised).
3610	* @param pVM The cross context VM structure. (For errors.)
3611	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3612	* @param pszValueName The value / extension name.
3613	* @param penmValue Where to return the choice.
3614	* @param enmDefault The default choice.
3615	*/
3616	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3617	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3618	{
3619	/*
3620	* Try integer encoding first.
3621	*/
3622	uint64_t uValue;
3623	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3624	if (RT_SUCCESS(rc))
3625	switch (uValue)
3626	{
3627	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3628	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3629	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3630	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3631	default:
3632	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3633	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3634	pszValueName, uValue);
3635	}
3636	/*
3637	* If missing, use default.
3638	*/
3639	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3640	*penmValue = enmDefault;
3641	else
3642	{
3643	if (rc == VERR_CFGM_NOT_INTEGER)
3644	{
3645	/*
3646	* Not an integer, try read it as a string.
3647	*/
3648	char szValue[32];
3649	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3650	if (RT_SUCCESS(rc))
3651	{
3652	RTStrToLower(szValue);
3653	size_t cchValue = strlen(szValue);
3654	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3655	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3656	*penmValue = CPUMISAEXTCFG_DISABLED;
3657	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3658	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3659	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3660	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3661	else if (EQ("portable"))
3662	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3663	else if (EQ("default") \|\| EQ("def"))
3664	*penmValue = enmDefault;
3665	else
3666	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3667	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3668	pszValueName, uValue);
3669	#undef EQ
3670	}
3671	}
3672	if (RT_FAILURE(rc))
3673	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3674	}
3675	return VINF_SUCCESS;
3676	}
3677
3678
3679	/**
3680	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3681	*
3682	* @returns VBox status code (error message raised).
3683	* @param pVM The cross context VM structure. (For errors.)
3684	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3685	* @param pszValueName The value / extension name.
3686	* @param penmValue Where to return the choice.
3687	* @param enmDefault The default choice.
3688	* @param fAllowed Allowed choice. Applied both to the result and to
3689	* the default value.
3690	*/
3691	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3692	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3693	{
3694	int rc;
3695	if (fAllowed)
3696	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3697	else
3698	{
3699	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3700	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3701	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3702	*penmValue = CPUMISAEXTCFG_DISABLED;
3703	}
3704	return rc;
3705	}
3706
3707
3708	/**
3709	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3710	*
3711	* @returns VBox status code (error message raised).
3712	* @param pVM The cross context VM structure. (For errors.)
3713	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3714	* @param pCpumCfg The /CPUM node (can be NULL).
3715	* @param pszValueName The value / extension name.
3716	* @param penmValue Where to return the choice.
3717	* @param enmDefault The default choice.
3718	*/
3719	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3720	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3721	{
3722	if (CFGMR3Exists(pCpumCfg, pszValueName))
3723	{
3724	if (!CFGMR3Exists(pIsaExts, pszValueName))
3725	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3726	else
3727	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3728	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3729	pszValueName, pszValueName);
3730
3731	bool fLegacy;
3732	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3733	if (RT_SUCCESS(rc))
3734	{
3735	*penmValue = fLegacy;
3736	return VINF_SUCCESS;
3737	}
3738	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3739	}
3740
3741	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3742	}
3743
3744
3745	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3746	{
3747	int rc;
3748
3749	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3750	* When non-zero CPUID features that could cause portability issues will be
3751	* stripped. The higher the value the more features gets stripped. Higher
3752	* values should only be used when older CPUs are involved since it may
3753	* harm performance and maybe also cause problems with specific guests. */
3754	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
3755	AssertLogRelRCReturn(rc, rc);
3756
3757	/** @cfgm{/CPUM/GuestCpuName, string}
3758	* The name of the CPU we're to emulate. The default is the host CPU.
3759	* Note! CPUs other than "host" one is currently unsupported. */
3760	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3761	AssertLogRelRCReturn(rc, rc);
3762
3763	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3764	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3765	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3766	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3767	*/
3768	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3769	AssertLogRelRCReturn(rc, rc);
3770
3771	/** @cfgm{/CPUM/InvariantTsc, boolean, complicated}
3772	* Set the invariant TSC flag in 0x80000007 if true, otherwas take default
3773	* action. By default the flag is passed thru as is from the host CPU, except
3774	* on AMD CPUs where it's suppressed to avoid trouble from linux assuming we
3775	* virtualize performance counters.
3776	*/
3777	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, false);
3778	AssertLogRelRCReturn(rc, rc);
3779
3780	/** @cfgm{/CPUM/ForceVme, boolean, false}
3781	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
3782	* By default the flag is passed thru as is from the host CPU, except
3783	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
3784	* guests and DOS boxes in general.
3785	*/
3786	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
3787	AssertLogRelRCReturn(rc, rc);
3788
3789	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3790	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
3791	* probably going to be a temporary hack, so don't depend on this.
3792	* The 1st byte of the value is the stepping, the 2nd byte value is the model
3793	* number and the 3rd byte value is the family, and the 4th value must be zero.
3794	*/
3795	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3796	AssertLogRelRCReturn(rc, rc);
3797
3798	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3799	* The last standard leaf to keep. The actual last value that is stored in EAX
3800	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3801	* removed. (This works independently of and differently from NT4LeafLimit.)
3802	* The default is usually set to what we're able to reasonably sanitize.
3803	*/
3804	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3805	AssertLogRelRCReturn(rc, rc);
3806
3807	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3808	* The last extended leaf to keep. The actual last value that is stored in EAX
3809	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3810	* leaf are removed. The default is set to what we're able to sanitize.
3811	*/
3812	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3813	AssertLogRelRCReturn(rc, rc);
3814
3815	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3816	* The last extended leaf to keep. The actual last value that is stored in EAX
3817	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3818	* leaf are removed. The default is set to what we're able to sanitize.
3819	*/
3820	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3821	AssertLogRelRCReturn(rc, rc);
3822
3823
3824	/*
3825	* Instruction Set Architecture (ISA) Extensions.
3826	*/
3827	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3828	if (pIsaExts)
3829	{
3830	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3831	"CMPXCHG16B"
3832	"\|MONITOR"
3833	"\|MWaitExtensions"
3834	"\|SSE4.1"
3835	"\|SSE4.2"
3836	"\|XSAVE"
3837	"\|AVX"
3838	"\|AVX2"
3839	"\|AESNI"
3840	"\|PCLMUL"
3841	"\|POPCNT"
3842	"\|MOVBE"
3843	"\|RDRAND"
3844	"\|RDSEED"
3845	"\|CLFLUSHOPT"
3846	"\|ABM"
3847	"\|SSE4A"
3848	"\|MISALNSSE"
3849	"\|3DNOWPRF"
3850	"\|AXMMX"
3851	"\|SVM"
3852	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
3853	if (RT_FAILURE(rc))
3854	return rc;
3855	}
3856
3857	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
3858	* Expose CMPXCHG16B to the guest if supported by the host. For the time
3859	* being the default is to only do this for VMs with nested paging and AMD-V or
3860	* unrestricted guest mode.
3861	*/
3862	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
3863	AssertLogRelRCReturn(rc, rc);
3864
3865	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
3866	* Expose MONITOR/MWAIT instructions to the guest.
3867	*/
3868	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
3869	AssertLogRelRCReturn(rc, rc);
3870
3871	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
3872	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
3873	* break on interrupt feature (bit 1).
3874	*/
3875	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
3876	AssertLogRelRCReturn(rc, rc);
3877
3878	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
3879	* Expose SSE4.1 to the guest if available.
3880	*/
3881	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
3882	AssertLogRelRCReturn(rc, rc);
3883
3884	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
3885	* Expose SSE4.2 to the guest if available.
3886	*/
3887	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
3888	AssertLogRelRCReturn(rc, rc);
3889
3890	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
3891	&& pVM->cpum.s.HostFeatures.fXSaveRstor
3892	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
3893	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
3894	&& !HMIsLongModeAllowed(pVM)
3895	#endif
3896	;
3897	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
3898
3899	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
3900	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
3901	* default is to only expose this to VMs with nested paging and AMD-V or
3902	* unrestricted guest execution mode. Not possible to force this one without
3903	* host support at the moment.
3904	*/
3905	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
3906	fMayHaveXSave /fAllowed/);
3907	AssertLogRelRCReturn(rc, rc);
3908
3909	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
3910	* Expose the AVX instruction set extensions to the guest if available and
3911	* XSAVE is exposed too. For the time being the default is to only expose this
3912	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3913	*/
3914	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
3915	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3916	AssertLogRelRCReturn(rc, rc);
3917
3918	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
3919	* Expose the AVX2 instruction set extensions to the guest if available and
3920	* XSAVE is exposed too. For the time being the default is to only expose this
3921	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3922	*/
3923	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
3924	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3925	AssertLogRelRCReturn(rc, rc);
3926
3927	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
3928	* Whether to expose the AES instructions to the guest. For the time being the
3929	* default is to only do this for VMs with nested paging and AMD-V or
3930	* unrestricted guest mode.
3931	*/
3932	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
3933	AssertLogRelRCReturn(rc, rc);
3934
3935	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
3936	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
3937	* being the default is to only do this for VMs with nested paging and AMD-V or
3938	* unrestricted guest mode.
3939	*/
3940	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
3941	AssertLogRelRCReturn(rc, rc);
3942
3943	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
3944	* Whether to expose the POPCNT instructions to the guest. For the time
3945	* being the default is to only do this for VMs with nested paging and AMD-V or
3946	* unrestricted guest mode.
3947	*/
3948	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
3949	AssertLogRelRCReturn(rc, rc);
3950
3951	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
3952	* Whether to expose the MOVBE instructions to the guest. For the time
3953	* being the default is to only do this for VMs with nested paging and AMD-V or
3954	* unrestricted guest mode.
3955	*/
3956	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
3957	AssertLogRelRCReturn(rc, rc);
3958
3959	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
3960	* Whether to expose the RDRAND instructions to the guest. For the time being
3961	* the default is to only do this for VMs with nested paging and AMD-V or
3962	* unrestricted guest mode.
3963	*/
3964	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
3965	AssertLogRelRCReturn(rc, rc);
3966
3967	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
3968	* Whether to expose the RDSEED instructions to the guest. For the time being
3969	* the default is to only do this for VMs with nested paging and AMD-V or
3970	* unrestricted guest mode.
3971	*/
3972	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
3973	AssertLogRelRCReturn(rc, rc);
3974
3975	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
3976	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
3977	* being the default is to only do this for VMs with nested paging and AMD-V or
3978	* unrestricted guest mode.
3979	*/
3980	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
3981	AssertLogRelRCReturn(rc, rc);
3982
3983
3984	/* AMD: */
3985
3986	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
3987	* Whether to expose the AMD ABM instructions to the guest. For the time
3988	* being the default is to only do this for VMs with nested paging and AMD-V or
3989	* unrestricted guest mode.
3990	*/
3991	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
3992	AssertLogRelRCReturn(rc, rc);
3993
3994	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
3995	* Whether to expose the AMD SSE4A instructions to the guest. For the time
3996	* being the default is to only do this for VMs with nested paging and AMD-V or
3997	* unrestricted guest mode.
3998	*/
3999	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4000	AssertLogRelRCReturn(rc, rc);
4001
4002	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4003	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4004	* the time being the default is to only do this for VMs with nested paging and
4005	* AMD-V or unrestricted guest mode.
4006	*/
4007	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4008	AssertLogRelRCReturn(rc, rc);
4009
4010	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4011	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4012	* For the time being the default is to only do this for VMs with nested paging
4013	* and AMD-V or unrestricted guest mode.
4014	*/
4015	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4016	AssertLogRelRCReturn(rc, rc);
4017
4018	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4019	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4020	* the default is to only do this for VMs with nested paging and AMD-V or
4021	* unrestricted guest mode.
4022	*/
4023	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4024	AssertLogRelRCReturn(rc, rc);
4025
4026	#ifdef VBOX_WITH_NESTED_HWVIRT
4027	/** @cfgm{/CPUM/IsaExts/SVM, isaextcfg, depends}
4028	* Whether to expose the AMD's hardware virtualization (SVM) instructions to the
4029	* guest. For the time being, the default is to only do this for VMs with nested
4030	* paging and AMD-V.
4031	*/
4032	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SVM", &pConfig->enmSvm, fNestedPagingAndFullGuestExec);
4033	AssertLogRelRCReturn(rc, rc);
4034	#endif
4035
4036	return VINF_SUCCESS;
4037	}
4038
4039
4040	/**
4041	* Initializes the emulated CPU's CPUID & MSR information.
4042	*
4043	* @returns VBox status code.
4044	* @param pVM The cross context VM structure.
4045	*/
4046	int cpumR3InitCpuIdAndMsrs(PVM pVM)
4047	{
4048	PCPUM pCpum = &pVM->cpum.s;
4049	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4050
4051	/*
4052	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4053	* on construction and manage everything from here on.
4054	*/
4055	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
4056	pVM->aCpus[iCpu].cpum.s.fCpuIdApicFeatureVisible = true;
4057
4058	/*
4059	* Read the configuration.
4060	*/
4061	CPUMCPUIDCONFIG Config;
4062	RT_ZERO(Config);
4063
4064	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4065	AssertRCReturn(rc, rc);
4066
4067	/*
4068	* Get the guest CPU data from the database and/or the host.
4069	*
4070	* The CPUID and MSRs are currently living on the regular heap to avoid
4071	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4072	* API for the hyper heap). This means special cleanup considerations.
4073	*/
4074	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4075	if (RT_FAILURE(rc))
4076	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4077	? VMSetError(pVM, rc, RT_SRC_POS,
4078	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4079	: rc;
4080
4081	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4082	{
4083	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4084	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4085	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4086	}
4087	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4088
4089	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4090	* Overrides the guest MSRs.
4091	*/
4092	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4093
4094	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4095	* Overrides the CPUID leaf values (from the host CPU usually) used for
4096	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4097	* values when moving a VM to a different machine. Another use is restricting
4098	* (or extending) the feature set exposed to the guest. */
4099	if (RT_SUCCESS(rc))
4100	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4101
4102	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4103	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4104	"Found unsupported configuration node '/CPUM/CPUID/'. "
4105	"Please use IMachine::setCPUIDLeaf() instead.");
4106
4107	/*
4108	* Pre-explode the CPUID info.
4109	*/
4110	if (RT_SUCCESS(rc))
4111	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
4112
4113	/*
4114	* Sanitize the cpuid information passed on to the guest.
4115	*/
4116	if (RT_SUCCESS(rc))
4117	{
4118	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4119	if (RT_SUCCESS(rc))
4120	{
4121	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4122	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4123	}
4124	}
4125
4126	/*
4127	* MSR fudging.
4128	*/
4129	if (RT_SUCCESS(rc))
4130	{
4131	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4132	* Fudges some common MSRs if not present in the selected CPU database entry.
4133	* This is for trying to keep VMs running when moved between different hosts
4134	* and different CPU vendors. */
4135	bool fEnable;
4136	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4137	if (RT_SUCCESS(rc) && fEnable)
4138	{
4139	rc = cpumR3MsrApplyFudge(pVM);
4140	AssertLogRelRC(rc);
4141	}
4142	}
4143	if (RT_SUCCESS(rc))
4144	{
4145	/*
4146	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4147	* guest CPU features again.
4148	*/
4149	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4150	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4151	pCpum->GuestInfo.cCpuIdLeaves);
4152	RTMemFree(pvFree);
4153
4154	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4155	int rc2 = MMHyperDupMem(pVM, pvFree,
4156	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4157	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4158	RTMemFree(pvFree);
4159	AssertLogRelRCReturn(rc1, rc1);
4160	AssertLogRelRCReturn(rc2, rc2);
4161
4162	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4163	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4164
4165
4166	/*
4167	* Some more configuration that we're applying at the end of everything
4168	* via the CPUMSetGuestCpuIdFeature API.
4169	*/
4170
4171	/* Check if PAE was explicitely enabled by the user. */
4172	bool fEnable;
4173	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4174	AssertRCReturn(rc, rc);
4175	if (fEnable)
4176	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4177
4178	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4179	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4180	AssertRCReturn(rc, rc);
4181	if (fEnable)
4182	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4183
4184	return VINF_SUCCESS;
4185	}
4186
4187	/*
4188	* Failed before switching to hyper heap.
4189	*/
4190	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4191	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4192	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4193	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4194	return rc;
4195	}
4196
4197
4198	/**
4199	* Sets a CPUID feature bit during VM initialization.
4200	*
4201	* Since the CPUID feature bits are generally related to CPU features, other
4202	* CPUM configuration like MSRs can also be modified by calls to this API.
4203	*
4204	* @param pVM The cross context VM structure.
4205	* @param enmFeature The feature to set.
4206	*/
4207	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4208	{
4209	PCPUMCPUIDLEAF pLeaf;
4210	PCPUMMSRRANGE pMsrRange;
4211
4212	switch (enmFeature)
4213	{
4214	/*
4215	* Set the APIC bit in both feature masks.
4216	*/
4217	case CPUMCPUIDFEATURE_APIC:
4218	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4219	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4220	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4221
4222	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4223	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4224	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4225
4226	pVM->cpum.s.GuestFeatures.fApic = 1;
4227
4228	/* Make sure we've got the APICBASE MSR present. */
4229	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4230	if (!pMsrRange)
4231	{
4232	static CPUMMSRRANGE const s_ApicBase =
4233	{
4234	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4235	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4236	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4237	/.szName = / "IA32_APIC_BASE"
4238	};
4239	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4240	AssertLogRelRC(rc);
4241	}
4242
4243	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4244	break;
4245
4246	/*
4247	* Set the x2APIC bit in the standard feature mask.
4248	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4249	*/
4250	case CPUMCPUIDFEATURE_X2APIC:
4251	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4252	if (pLeaf)
4253	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4254	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4255
4256	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4257	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4258	if (pMsrRange)
4259	{
4260	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4261	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4262	}
4263
4264	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4265	break;
4266
4267	/*
4268	* Set the sysenter/sysexit bit in the standard feature mask.
4269	* Assumes the caller knows what it's doing! (host must support these)
4270	*/
4271	case CPUMCPUIDFEATURE_SEP:
4272	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4273	{
4274	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4275	return;
4276	}
4277
4278	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4279	if (pLeaf)
4280	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4281	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4282	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4283	break;
4284
4285	/*
4286	* Set the syscall/sysret bit in the extended feature mask.
4287	* Assumes the caller knows what it's doing! (host must support these)
4288	*/
4289	case CPUMCPUIDFEATURE_SYSCALL:
4290	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4291	if ( !pLeaf
4292	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4293	{
4294	#if HC_ARCH_BITS == 32
4295	/* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit
4296	mode by Intel, even when the cpu is capable of doing so in
4297	64-bit mode. Long mode requires syscall support. */
4298	if (!pVM->cpum.s.HostFeatures.fLongMode)
4299	#endif
4300	{
4301	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4302	return;
4303	}
4304	}
4305
4306	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4307	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4308	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4309	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4310	break;
4311
4312	/*
4313	* Set the PAE bit in both feature masks.
4314	* Assumes the caller knows what it's doing! (host must support these)
4315	*/
4316	case CPUMCPUIDFEATURE_PAE:
4317	if (!pVM->cpum.s.HostFeatures.fPae)
4318	{
4319	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4320	return;
4321	}
4322
4323	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4324	if (pLeaf)
4325	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4326
4327	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4328	if ( pLeaf
4329	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4330	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4331
4332	pVM->cpum.s.GuestFeatures.fPae = 1;
4333	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4334	break;
4335
4336	/*
4337	* Set the LONG MODE bit in the extended feature mask.
4338	* Assumes the caller knows what it's doing! (host must support these)
4339	*/
4340	case CPUMCPUIDFEATURE_LONG_MODE:
4341	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4342	if ( !pLeaf
4343	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4344	{
4345	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4346	return;
4347	}
4348
4349	/* Valid for both Intel and AMD. */
4350	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4351	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4352	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4353	break;
4354
4355	/*
4356	* Set the NX/XD bit in the extended feature mask.
4357	* Assumes the caller knows what it's doing! (host must support these)
4358	*/
4359	case CPUMCPUIDFEATURE_NX:
4360	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4361	if ( !pLeaf
4362	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4363	{
4364	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4365	return;
4366	}
4367
4368	/* Valid for both Intel and AMD. */
4369	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4370	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4371	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4372	break;
4373
4374
4375	/*
4376	* Set the LAHF/SAHF support in 64-bit mode.
4377	* Assumes the caller knows what it's doing! (host must support this)
4378	*/
4379	case CPUMCPUIDFEATURE_LAHF:
4380	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4381	if ( !pLeaf
4382	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4383	{
4384	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4385	return;
4386	}
4387
4388	/* Valid for both Intel and AMD. */
4389	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4390	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4391	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4392	break;
4393
4394	/*
4395	* Set the page attribute table bit. This is alternative page level
4396	* cache control that doesn't much matter when everything is
4397	* virtualized, though it may when passing thru device memory.
4398	*/
4399	case CPUMCPUIDFEATURE_PAT:
4400	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4401	if (pLeaf)
4402	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4403
4404	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4405	if ( pLeaf
4406	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4407	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4408
4409	pVM->cpum.s.GuestFeatures.fPat = 1;
4410	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4411	break;
4412
4413	/*
4414	* Set the RDTSCP support bit.
4415	* Assumes the caller knows what it's doing! (host must support this)
4416	*/
4417	case CPUMCPUIDFEATURE_RDTSCP:
4418	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4419	if ( !pLeaf
4420	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4421	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4422	{
4423	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4424	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4425	return;
4426	}
4427
4428	/* Valid for both Intel and AMD. */
4429	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4430	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4431	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4432	break;
4433
4434	/*
4435	* Set the Hypervisor Present bit in the standard feature mask.
4436	*/
4437	case CPUMCPUIDFEATURE_HVP:
4438	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4439	if (pLeaf)
4440	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4441	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4442	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4443	break;
4444
4445	/*
4446	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4447	* This currently includes the Present bit and MWAITBREAK bit as well.
4448	*/
4449	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4450	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4451	if ( !pLeaf
4452	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4453	{
4454	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4455	return;
4456	}
4457
4458	/* Valid for both Intel and AMD. */
4459	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4460	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4461	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4462	break;
4463
4464	default:
4465	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4466	break;
4467	}
4468
4469	/** @todo can probably kill this as this API is now init time only... */
4470	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4471	{
4472	PVMCPU pVCpu = &pVM->aCpus[i];
4473	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4474	}
4475	}
4476
4477
4478	/**
4479	* Queries a CPUID feature bit.
4480	*
4481	* @returns boolean for feature presence
4482	* @param pVM The cross context VM structure.
4483	* @param enmFeature The feature to query.
4484	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4485	*/
4486	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4487	{
4488	switch (enmFeature)
4489	{
4490	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4491	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4492	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4493	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4494	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4495	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4496	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4497	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4498	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4499	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4500	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4501	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4502
4503	case CPUMCPUIDFEATURE_INVALID:
4504	case CPUMCPUIDFEATURE_32BIT_HACK:
4505	break;
4506	}
4507	AssertFailed();
4508	return false;
4509	}
4510
4511
4512	/**
4513	* Clears a CPUID feature bit.
4514	*
4515	* @param pVM The cross context VM structure.
4516	* @param enmFeature The feature to clear.
4517	*
4518	* @deprecated Probably better to default the feature to disabled and only allow
4519	* setting (enabling) it during construction.
4520	*/
4521	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4522	{
4523	PCPUMCPUIDLEAF pLeaf;
4524	switch (enmFeature)
4525	{
4526	case CPUMCPUIDFEATURE_APIC:
4527	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
4528	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4529	if (pLeaf)
4530	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
4531
4532	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4533	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4534	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4535
4536	pVM->cpum.s.GuestFeatures.fApic = 0;
4537	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4538	break;
4539
4540	case CPUMCPUIDFEATURE_X2APIC:
4541	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4542	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4543	if (pLeaf)
4544	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
4545	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
4546	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
4547	break;
4548
4549	case CPUMCPUIDFEATURE_PAE:
4550	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4551	if (pLeaf)
4552	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
4553
4554	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4555	if ( pLeaf
4556	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4557	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
4558
4559	pVM->cpum.s.GuestFeatures.fPae = 0;
4560	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
4561	break;
4562
4563	case CPUMCPUIDFEATURE_PAT:
4564	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4565	if (pLeaf)
4566	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
4567
4568	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4569	if ( pLeaf
4570	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4571	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
4572
4573	pVM->cpum.s.GuestFeatures.fPat = 0;
4574	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
4575	break;
4576
4577	case CPUMCPUIDFEATURE_LONG_MODE:
4578	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4579	if (pLeaf)
4580	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4581	pVM->cpum.s.GuestFeatures.fLongMode = 0;
4582	break;
4583
4584	case CPUMCPUIDFEATURE_LAHF:
4585	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4586	if (pLeaf)
4587	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4588	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
4589	break;
4590
4591	case CPUMCPUIDFEATURE_RDTSCP:
4592	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4593	if (pLeaf)
4594	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4595	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
4596	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
4597	break;
4598
4599	case CPUMCPUIDFEATURE_HVP:
4600	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4601	if (pLeaf)
4602	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
4603	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
4604	break;
4605
4606	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4607	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4608	if (pLeaf)
4609	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
4610	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
4611	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
4612	break;
4613
4614	default:
4615	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4616	break;
4617	}
4618
4619	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4620	{
4621	PVMCPU pVCpu = &pVM->aCpus[i];
4622	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4623	}
4624	}
4625
4626
4627
4628	/*
4629	*
4630	*
4631	* Saved state related code.
4632	* Saved state related code.
4633	* Saved state related code.
4634	*
4635	*
4636	*/
4637
4638	/**
4639	* Called both in pass 0 and the final pass.
4640	*
4641	* @param pVM The cross context VM structure.
4642	* @param pSSM The saved state handle.
4643	*/
4644	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4645	{
4646	/*
4647	* Save all the CPU ID leaves.
4648	*/
4649	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4650	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4651	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4652	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4653
4654	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4655
4656	/*
4657	* Save a good portion of the raw CPU IDs as well as they may come in
4658	* handy when validating features for raw mode.
4659	*/
4660	CPUMCPUID aRawStd[16];
4661	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4662	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4663	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4664	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4665
4666	CPUMCPUID aRawExt[32];
4667	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4668	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4669	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4670	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4671	}
4672
4673
4674	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4675	{
4676	uint32_t cCpuIds;
4677	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4678	if (RT_SUCCESS(rc))
4679	{
4680	if (cCpuIds < 64)
4681	{
4682	for (uint32_t i = 0; i < cCpuIds; i++)
4683	{
4684	CPUMCPUID CpuId;
4685	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4686	if (RT_FAILURE(rc))
4687	break;
4688
4689	CPUMCPUIDLEAF NewLeaf;
4690	NewLeaf.uLeaf = uBase + i;
4691	NewLeaf.uSubLeaf = 0;
4692	NewLeaf.fSubLeafMask = 0;
4693	NewLeaf.uEax = CpuId.uEax;
4694	NewLeaf.uEbx = CpuId.uEbx;
4695	NewLeaf.uEcx = CpuId.uEcx;
4696	NewLeaf.uEdx = CpuId.uEdx;
4697	NewLeaf.fFlags = 0;
4698	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4699	}
4700	}
4701	else
4702	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4703	}
4704	if (RT_FAILURE(rc))
4705	{
4706	RTMemFree(*ppaLeaves);
4707	*ppaLeaves = NULL;
4708	*pcLeaves = 0;
4709	}
4710	return rc;
4711	}
4712
4713
4714	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4715	{
4716	*ppaLeaves = NULL;
4717	*pcLeaves = 0;
4718
4719	int rc;
4720	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4721	{
4722	/*
4723	* The new format. Starts by declaring the leave size and count.
4724	*/
4725	uint32_t cbLeaf;
4726	SSMR3GetU32(pSSM, &cbLeaf);
4727	uint32_t cLeaves;
4728	rc = SSMR3GetU32(pSSM, &cLeaves);
4729	if (RT_SUCCESS(rc))
4730	{
4731	if (cbLeaf == sizeof(**ppaLeaves))
4732	{
4733	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4734	{
4735	/*
4736	* Load the leaves one by one.
4737	*
4738	* The uPrev stuff is a kludge for working around a week worth of bad saved
4739	* states during the CPUID revamp in March 2015. We saved too many leaves
4740	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4741	* garbage entires at the end of the array when restoring. We also had
4742	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
4743	* this kludge doesn't deal correctly with that, but who cares...
4744	*/
4745	uint32_t uPrev = 0;
4746	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4747	{
4748	CPUMCPUIDLEAF Leaf;
4749	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
4750	if (RT_SUCCESS(rc))
4751	{
4752	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
4753	\|\| Leaf.uLeaf >= uPrev)
4754	{
4755	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4756	uPrev = Leaf.uLeaf;
4757	}
4758	else
4759	uPrev = UINT32_MAX;
4760	}
4761	}
4762	}
4763	else
4764	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
4765	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
4766	}
4767	else
4768	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
4769	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
4770	}
4771	}
4772	else
4773	{
4774	/*
4775	* The old format with its three inflexible arrays.
4776	*/
4777	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
4778	if (RT_SUCCESS(rc))
4779	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
4780	if (RT_SUCCESS(rc))
4781	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
4782	if (RT_SUCCESS(rc))
4783	{
4784	/*
4785	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
4786	*/
4787	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
4788	if ( pLeaf
4789	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
4790	{
4791	CPUMCPUIDLEAF Leaf;
4792	Leaf.uLeaf = 4;
4793	Leaf.fSubLeafMask = UINT32_MAX;
4794	Leaf.uSubLeaf = 0;
4795	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
4796	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
4797	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
4798	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
4799	\| UINT32_C(63); /* system coherency line size - 1 */
4800	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
4801	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
4802	\| (UINT32_C(1) << 5) /* cache level */
4803	\| UINT32_C(1); /* cache type (data) */
4804	Leaf.fFlags = 0;
4805	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4806	if (RT_SUCCESS(rc))
4807	{
4808	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
4809	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4810	}
4811	if (RT_SUCCESS(rc))
4812	{
4813	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
4814	Leaf.uEcx = 4095; /* sets - 1 */
4815	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
4816	Leaf.uEbx \|= UINT32_C(23) << 22;
4817	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
4818	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
4819	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
4820	Leaf.uEax \|= UINT32_C(2) << 5;
4821	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4822	}
4823	}
4824	}
4825	}
4826	return rc;
4827	}
4828
4829
4830	/**
4831	* Loads the CPU ID leaves saved by pass 0, inner worker.
4832	*
4833	* @returns VBox status code.
4834	* @param pVM The cross context VM structure.
4835	* @param pSSM The saved state handle.
4836	* @param uVersion The format version.
4837	* @param paLeaves Guest CPUID leaves loaded from the state.
4838	* @param cLeaves The number of leaves in @a paLeaves.
4839	*/
4840	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
4841	{
4842	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4843
4844	/*
4845	* Continue loading the state into stack buffers.
4846	*/
4847	CPUMCPUID GuestDefCpuId;
4848	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
4849	AssertRCReturn(rc, rc);
4850
4851	CPUMCPUID aRawStd[16];
4852	uint32_t cRawStd;
4853	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
4854	if (cRawStd > RT_ELEMENTS(aRawStd))
4855	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4856	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
4857	AssertRCReturn(rc, rc);
4858	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
4859	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4860
4861	CPUMCPUID aRawExt[32];
4862	uint32_t cRawExt;
4863	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
4864	if (cRawExt > RT_ELEMENTS(aRawExt))
4865	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4866	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
4867	AssertRCReturn(rc, rc);
4868	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
4869	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4870
4871	/*
4872	* Get the raw CPU IDs for the current host.
4873	*/
4874	CPUMCPUID aHostRawStd[16];
4875	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
4876	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
4877
4878	CPUMCPUID aHostRawExt[32];
4879	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
4880	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
4881	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4882
4883	/*
4884	* Get the host and guest overrides so we don't reject the state because
4885	* some feature was enabled thru these interfaces.
4886	* Note! We currently only need the feature leaves, so skip rest.
4887	*/
4888	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4889	CPUMCPUID aHostOverrideStd[2];
4890	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4891	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4892
4893	CPUMCPUID aHostOverrideExt[2];
4894	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4895	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4896
4897	/*
4898	* This can be skipped.
4899	*/
4900	bool fStrictCpuIdChecks;
4901	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
4902
4903	/*
4904	* Define a bunch of macros for simplifying the santizing/checking code below.
4905	*/
4906	/* Generic expression + failure message. */
4907	#define CPUID_CHECK_RET(expr, fmt) \
4908	do { \
4909	if (!(expr)) \
4910	{ \
4911	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
4912	if (fStrictCpuIdChecks) \
4913	{ \
4914	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4915	RTStrFree(pszMsg); \
4916	return rcCpuid; \
4917	} \
4918	LogRel(("CPUM: %s\n", pszMsg)); \
4919	RTStrFree(pszMsg); \
4920	} \
4921	} while (0)
4922	#define CPUID_CHECK_WRN(expr, fmt) \
4923	do { \
4924	if (!(expr)) \
4925	LogRel(fmt); \
4926	} while (0)
4927
4928	/* For comparing two values and bitch if they differs. */
4929	#define CPUID_CHECK2_RET(what, host, saved) \
4930	do { \
4931	if ((host) != (saved)) \
4932	{ \
4933	if (fStrictCpuIdChecks) \
4934	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4935	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
4936	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4937	} \
4938	} while (0)
4939	#define CPUID_CHECK2_WRN(what, host, saved) \
4940	do { \
4941	if ((host) != (saved)) \
4942	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4943	} while (0)
4944
4945	/* For checking raw cpu features (raw mode). */
4946	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
4947	do { \
4948	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4949	{ \
4950	if (fStrictCpuIdChecks) \
4951	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4952	N_(#bit " mismatch: host=%d saved=%d"), \
4953	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
4954	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4955	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4956	} \
4957	} while (0)
4958	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
4959	do { \
4960	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4961	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4962	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4963	} while (0)
4964	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
4965
4966	/* For checking guest features. */
4967	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
4968	do { \
4969	if ( (aGuestCpuId##set [1].reg & bit) \
4970	&& !(aHostRaw##set [1].reg & bit) \
4971	&& !(aHostOverride##set [1].reg & bit) \
4972	) \
4973	{ \
4974	if (fStrictCpuIdChecks) \
4975	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4976	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4977	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4978	} \
4979	} while (0)
4980	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
4981	do { \
4982	if ( (aGuestCpuId##set [1].reg & bit) \
4983	&& !(aHostRaw##set [1].reg & bit) \
4984	&& !(aHostOverride##set [1].reg & bit) \
4985	) \
4986	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4987	} while (0)
4988	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
4989	do { \
4990	if ( (aGuestCpuId##set [1].reg & bit) \
4991	&& !(aHostRaw##set [1].reg & bit) \
4992	&& !(aHostOverride##set [1].reg & bit) \
4993	) \
4994	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4995	} while (0)
4996	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
4997
4998	/* For checking guest features if AMD guest CPU. */
4999	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5000	do { \
5001	if ( (aGuestCpuId##set [1].reg & bit) \
5002	&& fGuestAmd \
5003	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5004	&& !(aHostOverride##set [1].reg & bit) \
5005	) \
5006	{ \
5007	if (fStrictCpuIdChecks) \
5008	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5009	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5010	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5011	} \
5012	} while (0)
5013	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5014	do { \
5015	if ( (aGuestCpuId##set [1].reg & bit) \
5016	&& fGuestAmd \
5017	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5018	&& !(aHostOverride##set [1].reg & bit) \
5019	) \
5020	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5021	} while (0)
5022	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5023	do { \
5024	if ( (aGuestCpuId##set [1].reg & bit) \
5025	&& fGuestAmd \
5026	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5027	&& !(aHostOverride##set [1].reg & bit) \
5028	) \
5029	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5030	} while (0)
5031	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5032
5033	/* For checking AMD features which have a corresponding bit in the standard
5034	range. (Intel defines very few bits in the extended feature sets.) */
5035	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5036	do { \
5037	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5038	&& !(fHostAmd \
5039	? aHostRawExt[1].reg & (ExtBit) \
5040	: aHostRawStd[1].reg & (StdBit)) \
5041	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5042	) \
5043	{ \
5044	if (fStrictCpuIdChecks) \
5045	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5046	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5047	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5048	} \
5049	} while (0)
5050	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5051	do { \
5052	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5053	&& !(fHostAmd \
5054	? aHostRawExt[1].reg & (ExtBit) \
5055	: aHostRawStd[1].reg & (StdBit)) \
5056	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5057	) \
5058	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5059	} while (0)
5060	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5061	do { \
5062	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5063	&& !(fHostAmd \
5064	? aHostRawExt[1].reg & (ExtBit) \
5065	: aHostRawStd[1].reg & (StdBit)) \
5066	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5067	) \
5068	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5069	} while (0)
5070	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5071
5072	/*
5073	* For raw-mode we'll require that the CPUs are very similar since we don't
5074	* intercept CPUID instructions for user mode applications.
5075	*/
5076	if (!HMIsEnabled(pVM))
5077	{
5078	/* CPUID(0) */
5079	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
5080	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
5081	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
5082	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5083	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
5084	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
5085	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
5086	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
5087	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5088
5089	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
5090
5091	/* CPUID(1).eax */
5092	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
5093	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
5094	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
5095
5096	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
5097	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
5098	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
5099
5100	/* CPUID(1).ecx */
5101	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
5102	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
5103	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
5104	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5105	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
5106	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
5107	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
5108	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
5109	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
5110	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
5111	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
5112	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
5113	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
5114	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
5115	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
5116	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
5117	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5118	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5119	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
5120	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
5121	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
5122	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5123	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
5124	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
5125	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5126	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
5127	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
5128	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5129	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
5130	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5131	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5132	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
5133
5134	/* CPUID(1).edx */
5135	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5136	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5137	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
5138	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5139	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
5140	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
5141	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5142	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5143	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
5144	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5145	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5146	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5147	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5148	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5149	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5150	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
5151	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5152	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5153	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5154	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
5155	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5156	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
5157	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
5158	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
5159	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
5160	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
5161	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
5162	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
5163	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
5164	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
5165	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
5166	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
5167
5168	/* CPUID(2) - config, mostly about caches. ignore. */
5169	/* CPUID(3) - processor serial number. ignore. */
5170	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
5171	/* CPUID(5) - mwait/monitor config. ignore. */
5172	/* CPUID(6) - power management. ignore. */
5173	/* CPUID(7) - ???. ignore. */
5174	/* CPUID(8) - ???. ignore. */
5175	/* CPUID(9) - DCA. ignore for now. */
5176	/* CPUID(a) - PeMo info. ignore for now. */
5177	/* CPUID(b) - topology info - takes ECX as input. ignore. */
5178
5179	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
5180	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
5181	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
5182	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
5183	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
5184	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
5185	{
5186	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
5187	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
5188	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
5189	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
5190	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
5191	}
5192
5193	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
5194	Note! Intel have/is marking many of the fields here as reserved. We
5195	will verify them as if it's an AMD CPU. */
5196	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
5197	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
5198	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
5199	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
5200	{
5201	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
5202	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
5203	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
5204	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5205	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
5206	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
5207	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
5208
5209	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
5210	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
5211	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
5212	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
5213	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
5214	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5215
5216	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
5217	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
5218	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
5219	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
5220
5221	/* CPUID(0x80000001).ecx */
5222	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
5223	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
5224	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
5225	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
5226	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
5227	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
5228	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
5229	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
5230	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
5231	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
5232	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
5233	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
5234	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
5235	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
5236	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5237	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5238	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5239	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5240	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5241	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5242	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5243	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5244	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5245	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5246	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5247	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5248	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5249	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5250	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5251	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5252	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5253	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5254
5255	/* CPUID(0x80000001).edx */
5256	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
5257	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
5258	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
5259	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
5260	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
5261	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
5262	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
5263	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
5264	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
5265	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
5266	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5267	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
5268	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
5269	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
5270	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
5271	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
5272	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
5273	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
5274	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5275	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5276	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5277	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
5278	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5279	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
5280	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
5281	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5282	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5283	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5284	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
5285	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5286	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5287	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5288
5289	/** @todo verify the rest as well. */
5290	}
5291	}
5292
5293
5294
5295	/*
5296	* Verify that we can support the features already exposed to the guest on
5297	* this host.
5298	*
5299	* Most of the features we're emulating requires intercepting instruction
5300	* and doing it the slow way, so there is no need to warn when they aren't
5301	* present in the host CPU. Thus we use IGN instead of EMU on these.
5302	*
5303	* Trailing comments:
5304	* "EMU" - Possible to emulate, could be lots of work and very slow.
5305	* "EMU?" - Can this be emulated?
5306	*/
5307	CPUMCPUID aGuestCpuIdStd[2];
5308	RT_ZERO(aGuestCpuIdStd);
5309	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5310
5311	/* CPUID(1).ecx */
5312	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5313	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5314	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5315	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5316	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5317	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5318	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5319	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5320	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5321	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5322	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5323	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5324	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5325	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5326	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5327	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5328	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5329	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5330	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5331	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5332	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5333	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5334	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5335	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5336	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5337	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5338	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5339	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5340	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5341	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5342	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5343	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5344
5345	/* CPUID(1).edx */
5346	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5347	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5348	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5349	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5350	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5351	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5352	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5353	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5354	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5355	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5356	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5357	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5358	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5359	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5360	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5361	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5362	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5363	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5364	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5365	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5366	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5367	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5368	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5369	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5370	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5371	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5372	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5373	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5374	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5375	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5376	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5377	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5378
5379	/* CPUID(0x80000000). */
5380	CPUMCPUID aGuestCpuIdExt[2];
5381	RT_ZERO(aGuestCpuIdExt);
5382	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5383	{
5384	/** @todo deal with no 0x80000001 on the host. */
5385	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5386	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5387
5388	/* CPUID(0x80000001).ecx */
5389	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5390	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5391	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5392	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5393	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5394	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5395	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5396	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5397	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5398	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5399	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5400	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5401	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5402	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5403	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5404	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5405	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5406	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5407	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5408	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5409	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5410	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5411	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5412	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5413	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5414	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5415	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5416	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5417	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5418	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5419	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5420	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5421
5422	/* CPUID(0x80000001).edx */
5423	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5424	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5425	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5426	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5427	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5428	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5429	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5430	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5431	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5432	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5433	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5434	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5435	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5436	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5437	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5438	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5439	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5440	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5441	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5442	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5443	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5444	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5445	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5446	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5447	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5448	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5449	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5450	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5451	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5452	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5453	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5454	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5455	}
5456
5457	/** @todo check leaf 7 */
5458
5459	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5460	* ECX=0: EAX - Valid bits in XCR0[31:0].
5461	* EBX - Maximum state size as per current XCR0 value.
5462	* ECX - Maximum state size for all supported features.
5463	* EDX - Valid bits in XCR0[63:32].
5464	* ECX=1: EAX - Various X-features.
5465	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5466	* ECX - Valid bits in IA32_XSS[31:0].
5467	* EDX - Valid bits in IA32_XSS[63:32].
5468	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5469	* if the bit invalid all four registers are set to zero.
5470	* EAX - The state size for this feature.
5471	* EBX - The state byte offset of this feature.
5472	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5473	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5474	*/
5475	uint64_t fGuestXcr0Mask = 0;
5476	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5477	if ( pCurLeaf
5478	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5479	&& ( pCurLeaf->uEax
5480	\|\| pCurLeaf->uEbx
5481	\|\| pCurLeaf->uEcx
5482	\|\| pCurLeaf->uEdx) )
5483	{
5484	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5485	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5486	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5487	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5488	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5489	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5490	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5491	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5492
5493	/* We don't support any additional features yet. */
5494	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5495	if (pCurLeaf && pCurLeaf->uEax)
5496	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5497	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5498	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5499	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5500	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5501	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5502
5503
5504	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5505	{
5506	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5507	if (pCurLeaf)
5508	{
5509	/* If advertised, the state component offset and size must match the one used by host. */
5510	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5511	{
5512	CPUMCPUID RawHost;
5513	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5514	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5515	if ( RawHost.uEbx != pCurLeaf->uEbx
5516	\|\| RawHost.uEax != pCurLeaf->uEax)
5517	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5518	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5519	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5520	}
5521	}
5522	}
5523	}
5524	/* Clear leaf 0xd just in case we're loading an old state... */
5525	else if (pCurLeaf)
5526	{
5527	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5528	{
5529	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5530	if (pCurLeaf)
5531	{
5532	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5533	\|\| ( pCurLeaf->uEax == 0
5534	&& pCurLeaf->uEbx == 0
5535	&& pCurLeaf->uEcx == 0
5536	&& pCurLeaf->uEdx == 0),
5537	("uVersion=%#x; %#x %#x %#x %#x\n",
5538	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5539	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5540	}
5541	}
5542	}
5543
5544	/* Update the fXStateGuestMask value for the VM. */
5545	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5546	{
5547	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5548	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5549	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5550	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5551	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5552	}
5553
5554	#undef CPUID_CHECK_RET
5555	#undef CPUID_CHECK_WRN
5556	#undef CPUID_CHECK2_RET
5557	#undef CPUID_CHECK2_WRN
5558	#undef CPUID_RAW_FEATURE_RET
5559	#undef CPUID_RAW_FEATURE_WRN
5560	#undef CPUID_RAW_FEATURE_IGN
5561	#undef CPUID_GST_FEATURE_RET
5562	#undef CPUID_GST_FEATURE_WRN
5563	#undef CPUID_GST_FEATURE_EMU
5564	#undef CPUID_GST_FEATURE_IGN
5565	#undef CPUID_GST_FEATURE2_RET
5566	#undef CPUID_GST_FEATURE2_WRN
5567	#undef CPUID_GST_FEATURE2_EMU
5568	#undef CPUID_GST_FEATURE2_IGN
5569	#undef CPUID_GST_AMD_FEATURE_RET
5570	#undef CPUID_GST_AMD_FEATURE_WRN
5571	#undef CPUID_GST_AMD_FEATURE_EMU
5572	#undef CPUID_GST_AMD_FEATURE_IGN
5573
5574	/*
5575	* We're good, commit the CPU ID leaves.
5576	*/
5577	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5578	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5579	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5580	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
5581	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5582	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
5583	AssertLogRelRCReturn(rc, rc);
5584
5585	return VINF_SUCCESS;
5586	}
5587
5588
5589	/**
5590	* Loads the CPU ID leaves saved by pass 0.
5591	*
5592	* @returns VBox status code.
5593	* @param pVM The cross context VM structure.
5594	* @param pSSM The saved state handle.
5595	* @param uVersion The format version.
5596	*/
5597	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5598	{
5599	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5600
5601	/*
5602	* Load the CPUID leaves array first and call worker to do the rest, just so
5603	* we can free the memory when we need to without ending up in column 1000.
5604	*/
5605	PCPUMCPUIDLEAF paLeaves;
5606	uint32_t cLeaves;
5607	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5608	AssertRC(rc);
5609	if (RT_SUCCESS(rc))
5610	{
5611	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
5612	RTMemFree(paLeaves);
5613	}
5614	return rc;
5615	}
5616
5617
5618
5619	/**
5620	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5621	*
5622	* @returns VBox status code.
5623	* @param pVM The cross context VM structure.
5624	* @param pSSM The saved state handle.
5625	* @param uVersion The format version.
5626	*/
5627	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5628	{
5629	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5630
5631	/*
5632	* Restore the CPUID leaves.
5633	*
5634	* Note that we support restoring less than the current amount of standard
5635	* leaves because we've been allowed more is newer version of VBox.
5636	*/
5637	uint32_t cElements;
5638	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5639	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5640	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5641	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5642
5643	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5644	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5645	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5646	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5647
5648	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5649	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5650	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5651	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5652
5653	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5654
5655	/*
5656	* Check that the basic cpuid id information is unchanged.
5657	*/
5658	/** @todo we should check the 64 bits capabilities too! */
5659	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5660	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5661	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5662	uint32_t au32CpuIdSaved[8];
5663	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5664	if (RT_SUCCESS(rc))
5665	{
5666	/* Ignore CPU stepping. */
5667	au32CpuId[4] &= 0xfffffff0;
5668	au32CpuIdSaved[4] &= 0xfffffff0;
5669
5670	/* Ignore APIC ID (AMD specs). */
5671	au32CpuId[5] &= ~0xff000000;
5672	au32CpuIdSaved[5] &= ~0xff000000;
5673
5674	/* Ignore the number of Logical CPUs (AMD specs). */
5675	au32CpuId[5] &= ~0x00ff0000;
5676	au32CpuIdSaved[5] &= ~0x00ff0000;
5677
5678	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5679	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5680	\| X86_CPUID_FEATURE_ECX_VMX
5681	\| X86_CPUID_FEATURE_ECX_SMX
5682	\| X86_CPUID_FEATURE_ECX_EST
5683	\| X86_CPUID_FEATURE_ECX_TM2
5684	\| X86_CPUID_FEATURE_ECX_CNTXID
5685	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5686	\| X86_CPUID_FEATURE_ECX_PDCM
5687	\| X86_CPUID_FEATURE_ECX_DCA
5688	\| X86_CPUID_FEATURE_ECX_X2APIC
5689	);
5690	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5691	\| X86_CPUID_FEATURE_ECX_VMX
5692	\| X86_CPUID_FEATURE_ECX_SMX
5693	\| X86_CPUID_FEATURE_ECX_EST
5694	\| X86_CPUID_FEATURE_ECX_TM2
5695	\| X86_CPUID_FEATURE_ECX_CNTXID
5696	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5697	\| X86_CPUID_FEATURE_ECX_PDCM
5698	\| X86_CPUID_FEATURE_ECX_DCA
5699	\| X86_CPUID_FEATURE_ECX_X2APIC
5700	);
5701
5702	/* Make sure we don't forget to update the masks when enabling
5703	* features in the future.
5704	*/
5705	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5706	( X86_CPUID_FEATURE_ECX_DTES64
5707	\| X86_CPUID_FEATURE_ECX_VMX
5708	\| X86_CPUID_FEATURE_ECX_SMX
5709	\| X86_CPUID_FEATURE_ECX_EST
5710	\| X86_CPUID_FEATURE_ECX_TM2
5711	\| X86_CPUID_FEATURE_ECX_CNTXID
5712	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5713	\| X86_CPUID_FEATURE_ECX_PDCM
5714	\| X86_CPUID_FEATURE_ECX_DCA
5715	\| X86_CPUID_FEATURE_ECX_X2APIC
5716	)));
5717	/* do the compare */
5718	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5719	{
5720	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5721	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5722	"Saved=%.*Rhxs\n"
5723	"Real =%.*Rhxs\n",
5724	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5725	sizeof(au32CpuId), au32CpuId));
5726	else
5727	{
5728	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5729	"Saved=%.*Rhxs\n"
5730	"Real =%.*Rhxs\n",
5731	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5732	sizeof(au32CpuId), au32CpuId));
5733	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5734	}
5735	}
5736	}
5737
5738	return rc;
5739	}
5740
5741
5742
5743	/*
5744	*
5745	*
5746	* CPUID Info Handler.
5747	* CPUID Info Handler.
5748	* CPUID Info Handler.
5749	*
5750	*
5751	*/
5752
5753
5754
5755	/**
5756	* Get L1 cache / TLS associativity.
5757	*/
5758	static const char getCacheAss(unsigned u, char pszBuf)
5759	{
5760	if (u == 0)
5761	return "res0 ";
5762	if (u == 1)
5763	return "direct";
5764	if (u == 255)
5765	return "fully";
5766	if (u >= 256)
5767	return "???";
5768
5769	RTStrPrintf(pszBuf, 16, "%d way", u);
5770	return pszBuf;
5771	}
5772
5773
5774	/**
5775	* Get L2 cache associativity.
5776	*/
5777	const char *getL2CacheAss(unsigned u)
5778	{
5779	switch (u)
5780	{
5781	case 0: return "off ";
5782	case 1: return "direct";
5783	case 2: return "2 way ";
5784	case 3: return "res3 ";
5785	case 4: return "4 way ";
5786	case 5: return "res5 ";
5787	case 6: return "8 way ";
5788	case 7: return "res7 ";
5789	case 8: return "16 way";
5790	case 9: return "res9 ";
5791	case 10: return "res10 ";
5792	case 11: return "res11 ";
5793	case 12: return "res12 ";
5794	case 13: return "res13 ";
5795	case 14: return "res14 ";
5796	case 15: return "fully ";
5797	default: return "????";
5798	}
5799	}
5800
5801
5802	/** CPUID(1).EDX field descriptions. */
5803	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
5804	{
5805	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5806	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5807	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5808	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5809	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5810	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
5811	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5812	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5813	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5814	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5815	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
5816	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5817	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5818	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5819	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5820	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5821	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5822	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
5823	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
5824	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
5825	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
5826	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5827	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
5828	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
5829	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
5830	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
5831	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
5832	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
5833	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
5834	DBGFREGSUBFIELD_TERMINATOR()
5835	};
5836
5837	/** CPUID(1).ECX field descriptions. */
5838	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
5839	{
5840	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
5841	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
5842	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
5843	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
5844	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
5845	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
5846	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
5847	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
5848	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
5849	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
5850	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
5851	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
5852	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
5853	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
5854	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
5855	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
5856	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
5857	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
5858	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
5859	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
5860	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
5861	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
5862	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
5863	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
5864	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
5865	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
5866	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
5867	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
5868	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
5869	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
5870	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
5871	DBGFREGSUBFIELD_TERMINATOR()
5872	};
5873
5874	/** CPUID(7,0).EBX field descriptions. */
5875	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
5876	{
5877	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
5878	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
5879	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
5880	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
5881	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
5882	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
5883	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
5884	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
5885	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
5886	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
5887	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
5888	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
5889	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
5890	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
5891	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
5892	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
5893	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
5894	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
5895	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
5896	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
5897	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
5898	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
5899	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
5900	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
5901	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
5902	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
5903	DBGFREGSUBFIELD_TERMINATOR()
5904	};
5905
5906	/** CPUID(7,0).ECX field descriptions. */
5907	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
5908	{
5909	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
5910	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
5911	DBGFREGSUBFIELD_RO("OSPKU\0" "CR4.PKU mirror", 4, 1, 0),
5912	DBGFREGSUBFIELD_TERMINATOR()
5913	};
5914
5915
5916	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
5917	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
5918	{
5919	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
5920	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
5921	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
5922	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
5923	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
5924	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
5925	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
5926	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
5927	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
5928	DBGFREGSUBFIELD_TERMINATOR()
5929	};
5930
5931	/** CPUID(13,1).EAX field descriptions. */
5932	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
5933	{
5934	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
5935	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
5936	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
5937	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
5938	DBGFREGSUBFIELD_TERMINATOR()
5939	};
5940
5941
5942	/** CPUID(0x80000001,0).EDX field descriptions. */
5943	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
5944	{
5945	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5946	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5947	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5948	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5949	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5950	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
5951	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5952	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5953	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5954	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5955	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
5956	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5957	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5958	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5959	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5960	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5961	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5962	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
5963	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
5964	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5965	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
5966	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
5967	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
5968	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
5969	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
5970	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
5971	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
5972	DBGFREGSUBFIELD_TERMINATOR()
5973	};
5974
5975	/** CPUID(0x80000001,0).ECX field descriptions. */
5976	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
5977	{
5978	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
5979	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
5980	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
5981	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
5982	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
5983	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
5984	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
5985	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
5986	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
5987	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
5988	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
5989	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
5990	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
5991	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
5992	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
5993	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
5994	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
5995	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
5996	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
5997	DBGFREGSUBFIELD_TERMINATOR()
5998	};
5999
6000
6001	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6002	const char *pszLeadIn, uint32_t cchWidth)
6003	{
6004	if (pszLeadIn)
6005	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6006
6007	for (uint32_t iBit = 0; iBit < 32; iBit++)
6008	if (RT_BIT_32(iBit) & uVal)
6009	{
6010	while ( pDesc->pszName != NULL
6011	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6012	pDesc++;
6013	if ( pDesc->pszName != NULL
6014	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6015	{
6016	if (pDesc->cBits == 1)
6017	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6018	else
6019	{
6020	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6021	if (pDesc->cBits < 32)
6022	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6023	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6024	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6025	}
6026	}
6027	else
6028	pHlp->pfnPrintf(pHlp, " %u", iBit);
6029	}
6030	if (pszLeadIn)
6031	pHlp->pfnPrintf(pHlp, "\n");
6032	}
6033
6034
6035	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6036	const char *pszLeadIn, uint32_t cchWidth)
6037	{
6038	if (pszLeadIn)
6039	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6040
6041	for (uint32_t iBit = 0; iBit < 64; iBit++)
6042	if (RT_BIT_64(iBit) & uVal)
6043	{
6044	while ( pDesc->pszName != NULL
6045	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6046	pDesc++;
6047	if ( pDesc->pszName != NULL
6048	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6049	{
6050	if (pDesc->cBits == 1)
6051	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6052	else
6053	{
6054	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6055	if (pDesc->cBits < 64)
6056	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6057	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6058	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6059	}
6060	}
6061	else
6062	pHlp->pfnPrintf(pHlp, " %u", iBit);
6063	}
6064	if (pszLeadIn)
6065	pHlp->pfnPrintf(pHlp, "\n");
6066	}
6067
6068
6069	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6070	const char *pszLeadIn, uint32_t cchWidth)
6071	{
6072	if (!uVal)
6073	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6074	else
6075	{
6076	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6077	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6078	pHlp->pfnPrintf(pHlp, " )\n");
6079	}
6080	}
6081
6082
6083	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6084	uint32_t cchWidth)
6085	{
6086	uint32_t uCombined = uVal1 \| uVal2;
6087	for (uint32_t iBit = 0; iBit < 32; iBit++)
6088	if ( (RT_BIT_32(iBit) & uCombined)
6089	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6090	{
6091	while ( pDesc->pszName != NULL
6092	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6093	pDesc++;
6094
6095	if ( pDesc->pszName != NULL
6096	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6097	{
6098	size_t cchMnemonic = strlen(pDesc->pszName);
6099	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6100	size_t cchDesc = strlen(pszDesc);
6101	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6102	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6103	if (pDesc->cBits < 32)
6104	{
6105	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6106	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6107	}
6108
6109	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6110	pDesc->pszName, pszDesc,
6111	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6112	uFieldValue1, uFieldValue2);
6113
6114	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6115	pDesc++;
6116	}
6117	else
6118	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6119	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6120	}
6121	}
6122
6123
6124	/**
6125	* Produces a detailed summary of standard leaf 0x00000001.
6126	*
6127	* @param pHlp The info helper functions.
6128	* @param pCurLeaf The 0x00000001 leaf.
6129	* @param fVerbose Whether to be very verbose or not.
6130	* @param fIntel Set if intel CPU.
6131	*/
6132	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6133	{
6134	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6135	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6136	uint32_t uEAX = pCurLeaf->uEax;
6137	uint32_t uEBX = pCurLeaf->uEbx;
6138
6139	pHlp->pfnPrintf(pHlp,
6140	"%36s %2d \tExtended: %d \tEffective: %d\n"
6141	"%36s %2d \tExtended: %d \tEffective: %d\n"
6142	"%36s %d\n"
6143	"%36s %d (%s)\n"
6144	"%36s %#04x\n"
6145	"%36s %d\n"
6146	"%36s %d\n"
6147	"%36s %#04x\n"
6148	,
6149	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6150	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6151	"Stepping:", ASMGetCpuStepping(uEAX),
6152	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6153	"APIC ID:", (uEBX >> 24) & 0xff,
6154	"Logical CPUs:",(uEBX >> 16) & 0xff,
6155	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6156	"Brand ID:", (uEBX >> 0) & 0xff);
6157	if (fVerbose)
6158	{
6159	CPUMCPUID Host;
6160	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6161	pHlp->pfnPrintf(pHlp, "Features\n");
6162	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6163	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6164	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6165	}
6166	else
6167	{
6168	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6169	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6170	}
6171	}
6172
6173
6174	/**
6175	* Produces a detailed summary of standard leaf 0x00000007.
6176	*
6177	* @param pHlp The info helper functions.
6178	* @param paLeaves The CPUID leaves array.
6179	* @param cLeaves The number of leaves in the array.
6180	* @param pCurLeaf The first 0x00000007 leaf.
6181	* @param fVerbose Whether to be very verbose or not.
6182	*/
6183	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6184	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6185	{
6186	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6187	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6188	for (;;)
6189	{
6190	CPUMCPUID Host;
6191	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6192
6193	switch (pCurLeaf->uSubLeaf)
6194	{
6195	case 0:
6196	if (fVerbose)
6197	{
6198	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6199	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6200	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6201	if (pCurLeaf->uEdx \|\| Host.uEdx)
6202	pHlp->pfnPrintf(pHlp, "%36 %#x (%#x)\n", "Ext Features EDX:", pCurLeaf->uEdx, Host.uEdx);
6203	}
6204	else
6205	{
6206	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6207	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6208	if (pCurLeaf->uEdx)
6209	pHlp->pfnPrintf(pHlp, "%36 %#x\n", "Ext Features EDX:", pCurLeaf->uEdx);
6210	}
6211	break;
6212
6213	default:
6214	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6215	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6216	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6217	break;
6218
6219	}
6220
6221	/* advance. */
6222	pCurLeaf++;
6223	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6224	\|\| pCurLeaf->uLeaf != 0x7)
6225	break;
6226	}
6227	}
6228
6229
6230	/**
6231	* Produces a detailed summary of standard leaf 0x0000000d.
6232	*
6233	* @param pHlp The info helper functions.
6234	* @param paLeaves The CPUID leaves array.
6235	* @param cLeaves The number of leaves in the array.
6236	* @param pCurLeaf The first 0x00000007 leaf.
6237	* @param fVerbose Whether to be very verbose or not.
6238	*/
6239	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6240	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6241	{
6242	RT_NOREF_PV(fVerbose);
6243	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6244	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6245	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6246	{
6247	CPUMCPUID Host;
6248	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6249
6250	switch (uSubLeaf)
6251	{
6252	case 0:
6253	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6254	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6255	pCurLeaf->uEbx, pCurLeaf->uEcx);
6256	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6257
6258	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6259	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6260	"Valid XCR0 bits, guest:", 42);
6261	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6262	"Valid XCR0 bits, host:", 42);
6263	break;
6264
6265	case 1:
6266	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6267	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6268	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6269
6270	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6271	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6272	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6273
6274	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6275	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6276	" Valid IA32_XSS bits, guest:", 42);
6277	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6278	" Valid IA32_XSS bits, host:", 42);
6279	break;
6280
6281	default:
6282	if ( pCurLeaf
6283	&& pCurLeaf->uSubLeaf == uSubLeaf
6284	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6285	{
6286	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6287	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6288	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6289	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6290	if (pCurLeaf->uEdx)
6291	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6292	pHlp->pfnPrintf(pHlp, " --");
6293	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6294	pHlp->pfnPrintf(pHlp, "\n");
6295	}
6296	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6297	{
6298	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6299	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6300	if (Host.uEcx & ~RT_BIT_32(0))
6301	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6302	if (Host.uEdx)
6303	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6304	pHlp->pfnPrintf(pHlp, " --");
6305	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6306	pHlp->pfnPrintf(pHlp, "\n");
6307	}
6308	break;
6309
6310	}
6311
6312	/* advance. */
6313	if (pCurLeaf)
6314	{
6315	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6316	&& pCurLeaf->uSubLeaf <= uSubLeaf
6317	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6318	pCurLeaf++;
6319	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6320	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6321	pCurLeaf = NULL;
6322	}
6323	}
6324	}
6325
6326
6327	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6328	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6329	{
6330	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6331	&& pCurLeaf->uLeaf <= uUpToLeaf)
6332	{
6333	pHlp->pfnPrintf(pHlp,
6334	" %s\n"
6335	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6336	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6337	&& pCurLeaf->uLeaf <= uUpToLeaf)
6338	{
6339	CPUMCPUID Host;
6340	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6341	pHlp->pfnPrintf(pHlp,
6342	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6343	"Hst: %08x %08x %08x %08x\n",
6344	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6345	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6346	pCurLeaf++;
6347	}
6348	}
6349
6350	return pCurLeaf;
6351	}
6352
6353
6354	/**
6355	* Display the guest CpuId leaves.
6356	*
6357	* @param pVM The cross context VM structure.
6358	* @param pHlp The info helper functions.
6359	* @param pszArgs "terse", "default" or "verbose".
6360	*/
6361	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6362	{
6363	/*
6364	* Parse the argument.
6365	*/
6366	unsigned iVerbosity = 1;
6367	if (pszArgs)
6368	{
6369	pszArgs = RTStrStripL(pszArgs);
6370	if (!strcmp(pszArgs, "terse"))
6371	iVerbosity--;
6372	else if (!strcmp(pszArgs, "verbose"))
6373	iVerbosity++;
6374	}
6375
6376	uint32_t uLeaf;
6377	CPUMCPUID Host;
6378	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6379	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6380	PCCPUMCPUIDLEAF pCurLeaf;
6381	PCCPUMCPUIDLEAF pNextLeaf;
6382	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6383	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6384	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6385
6386	/*
6387	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6388	*/
6389	uint32_t cHstMax = ASMCpuId_EAX(0);
6390	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6391	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6392	pHlp->pfnPrintf(pHlp,
6393	" Raw Standard CPUID Leaves\n"
6394	" Leaf/sub-leaf eax ebx ecx edx\n");
6395	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6396	{
6397	uint32_t cMaxSubLeaves = 1;
6398	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6399	cMaxSubLeaves = 16;
6400	else if (uLeaf == 0xd)
6401	cMaxSubLeaves = 128;
6402
6403	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6404	{
6405	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6406	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6407	&& pCurLeaf->uLeaf == uLeaf
6408	&& pCurLeaf->uSubLeaf == uSubLeaf)
6409	{
6410	pHlp->pfnPrintf(pHlp,
6411	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6412	"Hst: %08x %08x %08x %08x\n",
6413	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6414	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6415	pCurLeaf++;
6416	}
6417	else if ( uLeaf != 0xd
6418	\|\| uSubLeaf <= 1
6419	\|\| Host.uEbx != 0 )
6420	pHlp->pfnPrintf(pHlp,
6421	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6422	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6423
6424	/* Done? */
6425	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6426	\|\| pCurLeaf->uLeaf != uLeaf)
6427	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6428	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6429	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6430	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6431	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6432	)
6433	)
6434	break;
6435	}
6436	}
6437	pNextLeaf = pCurLeaf;
6438
6439	/*
6440	* If verbose, decode it.
6441	*/
6442	if (iVerbosity && paLeaves[0].uLeaf == 0)
6443	pHlp->pfnPrintf(pHlp,
6444	"%36s %.04s%.04s%.04s\n"
6445	"%36s 0x00000000-%#010x\n"
6446	,
6447	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6448	"Supports:", paLeaves[0].uEax);
6449
6450	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6451	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6452
6453	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6454	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6455
6456	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6457	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6458
6459	pCurLeaf = pNextLeaf;
6460
6461	/*
6462	* Hypervisor leaves.
6463	*
6464	* Unlike most of the other leaves reported, the guest hypervisor leaves
6465	* aren't a subset of the host CPUID bits.
6466	*/
6467	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6468
6469	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6470	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6471	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6472	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6473	cMax = RT_MAX(cHstMax, cGstMax);
6474	if (cMax >= UINT32_C(0x40000000))
6475	{
6476	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6477
6478	/** @todo dump these in more detail. */
6479
6480	pCurLeaf = pNextLeaf;
6481	}
6482
6483
6484	/*
6485	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6486	* Implemented after AMD specs.
6487	*/
6488	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6489
6490	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6491	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6492	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6493	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6494	cMax = RT_MAX(cHstMax, cGstMax);
6495	if (cMax >= UINT32_C(0x80000000))
6496	{
6497
6498	pHlp->pfnPrintf(pHlp,
6499	" Raw Extended CPUID Leaves\n"
6500	" Leaf/sub-leaf eax ebx ecx edx\n");
6501	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6502	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6503	{
6504	uint32_t cMaxSubLeaves = 1;
6505	if (uLeaf == UINT32_C(0x8000001d))
6506	cMaxSubLeaves = 16;
6507
6508	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6509	{
6510	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6511	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6512	&& pCurLeaf->uLeaf == uLeaf
6513	&& pCurLeaf->uSubLeaf == uSubLeaf)
6514	{
6515	pHlp->pfnPrintf(pHlp,
6516	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6517	"Hst: %08x %08x %08x %08x\n",
6518	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6519	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6520	pCurLeaf++;
6521	}
6522	else if ( uLeaf != 0xd
6523	\|\| uSubLeaf <= 1
6524	\|\| Host.uEbx != 0 )
6525	pHlp->pfnPrintf(pHlp,
6526	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6527	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6528
6529	/* Done? */
6530	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6531	\|\| pCurLeaf->uLeaf != uLeaf)
6532	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6533	break;
6534	}
6535	}
6536	pNextLeaf = pCurLeaf;
6537
6538	/*
6539	* Understandable output
6540	*/
6541	if (iVerbosity)
6542	pHlp->pfnPrintf(pHlp,
6543	"Ext Name: %.4s%.4s%.4s\n"
6544	"Ext Supports: 0x80000000-%#010x\n",
6545	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6546
6547	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6548	if (iVerbosity && pCurLeaf)
6549	{
6550	uint32_t uEAX = pCurLeaf->uEax;
6551	pHlp->pfnPrintf(pHlp,
6552	"Family: %d \tExtended: %d \tEffective: %d\n"
6553	"Model: %d \tExtended: %d \tEffective: %d\n"
6554	"Stepping: %d\n"
6555	"Brand ID: %#05x\n",
6556	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6557	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6558	ASMGetCpuStepping(uEAX),
6559	pCurLeaf->uEbx & 0xfff);
6560
6561	if (iVerbosity == 1)
6562	{
6563	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6564	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6565	}
6566	else
6567	{
6568	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6569	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6570	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6571	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6572	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6573	}
6574	}
6575
6576	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6577	{
6578	char szString[443+1] = {0};
6579	uint32_t pu32 = (uint32_t )szString;
6580	*pu32++ = pCurLeaf->uEax;
6581	*pu32++ = pCurLeaf->uEbx;
6582	*pu32++ = pCurLeaf->uEcx;
6583	*pu32++ = pCurLeaf->uEdx;
6584	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6585	if (pCurLeaf)
6586	{
6587	*pu32++ = pCurLeaf->uEax;
6588	*pu32++ = pCurLeaf->uEbx;
6589	*pu32++ = pCurLeaf->uEcx;
6590	*pu32++ = pCurLeaf->uEdx;
6591	}
6592	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6593	if (pCurLeaf)
6594	{
6595	*pu32++ = pCurLeaf->uEax;
6596	*pu32++ = pCurLeaf->uEbx;
6597	*pu32++ = pCurLeaf->uEcx;
6598	*pu32++ = pCurLeaf->uEdx;
6599	}
6600	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6601	}
6602
6603	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6604	{
6605	uint32_t uEAX = pCurLeaf->uEax;
6606	uint32_t uEBX = pCurLeaf->uEbx;
6607	uint32_t uECX = pCurLeaf->uEcx;
6608	uint32_t uEDX = pCurLeaf->uEdx;
6609	char sz1[32];
6610	char sz2[32];
6611
6612	pHlp->pfnPrintf(pHlp,
6613	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6614	"TLB 2/4M Data: %s %3d entries\n",
6615	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6616	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6617	pHlp->pfnPrintf(pHlp,
6618	"TLB 4K Instr/Uni: %s %3d entries\n"
6619	"TLB 4K Data: %s %3d entries\n",
6620	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6621	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6622	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6623	"L1 Instr Cache Lines Per Tag: %d\n"
6624	"L1 Instr Cache Associativity: %s\n"
6625	"L1 Instr Cache Size: %d KB\n",
6626	(uEDX >> 0) & 0xff,
6627	(uEDX >> 8) & 0xff,
6628	getCacheAss((uEDX >> 16) & 0xff, sz1),
6629	(uEDX >> 24) & 0xff);
6630	pHlp->pfnPrintf(pHlp,
6631	"L1 Data Cache Line Size: %d bytes\n"
6632	"L1 Data Cache Lines Per Tag: %d\n"
6633	"L1 Data Cache Associativity: %s\n"
6634	"L1 Data Cache Size: %d KB\n",
6635	(uECX >> 0) & 0xff,
6636	(uECX >> 8) & 0xff,
6637	getCacheAss((uECX >> 16) & 0xff, sz1),
6638	(uECX >> 24) & 0xff);
6639	}
6640
6641	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6642	{
6643	uint32_t uEAX = pCurLeaf->uEax;
6644	uint32_t uEBX = pCurLeaf->uEbx;
6645	uint32_t uEDX = pCurLeaf->uEdx;
6646
6647	pHlp->pfnPrintf(pHlp,
6648	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6649	"L2 TLB 2/4M Data: %s %4d entries\n",
6650	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6651	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6652	pHlp->pfnPrintf(pHlp,
6653	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6654	"L2 TLB 4K Data: %s %4d entries\n",
6655	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6656	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6657	pHlp->pfnPrintf(pHlp,
6658	"L2 Cache Line Size: %d bytes\n"
6659	"L2 Cache Lines Per Tag: %d\n"
6660	"L2 Cache Associativity: %s\n"
6661	"L2 Cache Size: %d KB\n",
6662	(uEDX >> 0) & 0xff,
6663	(uEDX >> 8) & 0xf,
6664	getL2CacheAss((uEDX >> 12) & 0xf),
6665	(uEDX >> 16) & 0xffff);
6666	}
6667
6668	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
6669	{
6670	uint32_t uEDX = pCurLeaf->uEdx;
6671
6672	pHlp->pfnPrintf(pHlp, "APM Features: ");
6673	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
6674	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
6675	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
6676	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
6677	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
6678	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
6679	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " MC");
6680	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " HWPSTATE");
6681	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TscInvariant");
6682	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " CPB");
6683	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " EffFreqRO");
6684	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PFI");
6685	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PA");
6686	for (unsigned iBit = 13; iBit < 32; iBit++)
6687	if (uEDX & RT_BIT(iBit))
6688	pHlp->pfnPrintf(pHlp, " %d", iBit);
6689	pHlp->pfnPrintf(pHlp, "\n");
6690
6691	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6692	pHlp->pfnPrintf(pHlp, "Host Invariant-TSC support: %RTbool\n",
6693	cHstMax >= UINT32_C(0x80000007) && (Host.uEdx & RT_BIT(8)));
6694
6695	}
6696
6697	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0)) != NULL)
6698	{
6699	uint32_t uEAX = pCurLeaf->uEax;
6700	uint32_t uECX = pCurLeaf->uEcx;
6701
6702	pHlp->pfnPrintf(pHlp,
6703	"Physical Address Width: %d bits\n"
6704	"Virtual Address Width: %d bits\n"
6705	"Guest Physical Address Width: %d bits\n",
6706	(uEAX >> 0) & 0xff,
6707	(uEAX >> 8) & 0xff,
6708	(uEAX >> 16) & 0xff);
6709	pHlp->pfnPrintf(pHlp,
6710	"Physical Core Count: %d\n",
6711	((uECX >> 0) & 0xff) + 1);
6712	}
6713
6714	pCurLeaf = pNextLeaf;
6715	}
6716
6717
6718
6719	/*
6720	* Centaur.
6721	*/
6722	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
6723
6724	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6725	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
6726	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
6727	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
6728	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
6729	cMax = RT_MAX(cHstMax, cGstMax);
6730	if (cMax >= UINT32_C(0xc0000000))
6731	{
6732	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
6733
6734	/*
6735	* Understandable output
6736	*/
6737	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
6738	pHlp->pfnPrintf(pHlp,
6739	"Centaur Supports: 0xc0000000-%#010x\n",
6740	pCurLeaf->uEax);
6741
6742	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
6743	{
6744	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6745	uint32_t uEdxGst = pCurLeaf->uEdx;
6746	uint32_t uEdxHst = Host.uEdx;
6747
6748	if (iVerbosity == 1)
6749	{
6750	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
6751	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
6752	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
6753	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
6754	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
6755	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
6756	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
6757	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
6758	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
6759	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6760	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
6761	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
6762	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
6763	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
6764	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
6765	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
6766	for (unsigned iBit = 14; iBit < 32; iBit++)
6767	if (uEdxGst & RT_BIT(iBit))
6768	pHlp->pfnPrintf(pHlp, " %d", iBit);
6769	pHlp->pfnPrintf(pHlp, "\n");
6770	}
6771	else
6772	{
6773	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
6774	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
6775	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
6776	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
6777	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
6778	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
6779	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
6780	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
6781	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
6782	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6783	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
6784	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
6785	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
6786	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
6787	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
6788	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
6789	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
6790	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
6791	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
6792	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
6793	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
6794	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
6795	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
6796	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
6797	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
6798	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
6799	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
6800	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
6801	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
6802	for (unsigned iBit = 27; iBit < 32; iBit++)
6803	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
6804	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
6805	pHlp->pfnPrintf(pHlp, "\n");
6806	}
6807	}
6808
6809	pCurLeaf = pNextLeaf;
6810	}
6811
6812	/*
6813	* The remainder.
6814	*/
6815	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
6816	}
6817
6818
6819
6820
6821
6822	/*
6823	*
6824	*
6825	* PATM interfaces.
6826	* PATM interfaces.
6827	* PATM interfaces.
6828	*
6829	*
6830	*/
6831
6832
6833	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
6834	/** @name Patchmanager CPUID legacy table APIs
6835	* @{
6836	*/
6837
6838	/**
6839	* Gets a pointer to the default CPUID leaf.
6840	*
6841	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
6842	* @param pVM The cross context VM structure.
6843	* @remark Intended for PATM only.
6844	*/
6845	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
6846	{
6847	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
6848	}
6849
6850
6851	/**
6852	* Gets a number of standard CPUID leaves (PATM only).
6853	*
6854	* @returns Number of leaves.
6855	* @param pVM The cross context VM structure.
6856	* @remark Intended for PATM - legacy, don't use in new code.
6857	*/
6858	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
6859	{
6860	RT_NOREF_PV(pVM);
6861	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
6862	}
6863
6864
6865	/**
6866	* Gets a number of extended CPUID leaves (PATM only).
6867	*
6868	* @returns Number of leaves.
6869	* @param pVM The cross context VM structure.
6870	* @remark Intended for PATM - legacy, don't use in new code.
6871	*/
6872	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
6873	{
6874	RT_NOREF_PV(pVM);
6875	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
6876	}
6877
6878
6879	/**
6880	* Gets a number of centaur CPUID leaves.
6881	*
6882	* @returns Number of leaves.
6883	* @param pVM The cross context VM structure.
6884	* @remark Intended for PATM - legacy, don't use in new code.
6885	*/
6886	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
6887	{
6888	RT_NOREF_PV(pVM);
6889	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
6890	}
6891
6892
6893	/**
6894	* Gets a pointer to the array of standard CPUID leaves.
6895	*
6896	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
6897	*
6898	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
6899	* @param pVM The cross context VM structure.
6900	* @remark Intended for PATM - legacy, don't use in new code.
6901	*/
6902	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
6903	{
6904	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
6905	}
6906
6907
6908	/**
6909	* Gets a pointer to the array of extended CPUID leaves.
6910	*
6911	* CPUMGetGuestCpuIdExtMax() give the size of the array.
6912	*
6913	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
6914	* @param pVM The cross context VM structure.
6915	* @remark Intended for PATM - legacy, don't use in new code.
6916	*/
6917	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
6918	{
6919	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
6920	}
6921
6922
6923	/**
6924	* Gets a pointer to the array of centaur CPUID leaves.
6925	*
6926	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
6927	*
6928	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
6929	* @param pVM The cross context VM structure.
6930	* @remark Intended for PATM - legacy, don't use in new code.
6931	*/
6932	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
6933	{
6934	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
6935	}
6936
6937	/** @} */
6938	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
6939
6940	#endif /* VBOX_IN_VMM */
6941

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 70323

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