CPUMR3CpuId.cpp@ 70450

Last change on this file since 70450 was 70450, checked in by vboxsync, 7 years ago
VMM/CPUMR3CpuId.cpp: Some new intel model numbers.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 322.7 KB

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1	/* $Id: CPUMR3CpuId.cpp 70450 2018-01-03 12:57:27Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/ssm.h>
27	#include "CPUMInternal.h"
28	#include <VBox/vmm/vm.h>
29	#include <VBox/vmm/mm.h>
30	#include <VBox/sup.h>
31
32	#include <VBox/err.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/ctype.h>
35	#include <iprt/mem.h>
36	#include <iprt/string.h>
37
38
39	/*********************************************************************************************************************************
40	* Defined Constants And Macros *
41	*********************************************************************************************************************************/
42	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
43	#define CPUM_CPUID_MAX_LEAVES 2048
44	/* Max size we accept for the XSAVE area. */
45	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
46	/* Min size we accept for the XSAVE area. */
47	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
48
49
50	/*********************************************************************************************************************************
51	* Global Variables *
52	*********************************************************************************************************************************/
53	/**
54	* The intel pentium family.
55	*/
56	static const CPUMMICROARCH g_aenmIntelFamily06[] =
57	{
58	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
59	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
60	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
61	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
62	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
63	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
64	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
65	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
66	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
67	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
68	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
69	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
70	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
71	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
72	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
73	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
74	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
80	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
81	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
82	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
83	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
85	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
86	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
87	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
88	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
89	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
90	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
91	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
96	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
97	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
98	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
99	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
101	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
102	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
103	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
104	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
105	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
106	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
107	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
112	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
113	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
114	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
115	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
117	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
118	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
119	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
120	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
121	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
122	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
123	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
128	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
130	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
131	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
133	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
134	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
135	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
136	/* [78(0x4e)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed */
137	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / unconfirmed, Broadwell-E */
138	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
139	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu */
144	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
145	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
146	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
147	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
149	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
150	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
151	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
152	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
153	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
154	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
155	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
158	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
159	/[101(0x65)] = / kCpumMicroarch_Intel_Unknown,
160	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_Cannonlake, /* unconfirmed */
161	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
162	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
163	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
164	/[106(0x6a)] = / kCpumMicroarch_Intel_Unknown,
165	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
166	/[108(0x6c)] = / kCpumMicroarch_Intel_Unknown,
167	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
168	/[110(0x6e)] = / kCpumMicroarch_Intel_Unknown,
169	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
170	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
171	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
172	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
173	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
174	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
175	/[117(0x75)] = / kCpumMicroarch_Intel_Unknown,
176	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
177	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
178	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
179	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
180	/[122(0x7a)] = / kCpumMicroarch_Intel_Unknown,
181	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
182	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
183	/[125(0x7d)] = / kCpumMicroarch_Intel_Unknown,
184	/[126(0x7e)] = / kCpumMicroarch_Intel_Unknown,
185	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
186	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
187	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
188	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
189	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
190	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
191	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
192	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
193	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
194	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
195	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
196	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
197	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
198	/[140(0x8c)] = / kCpumMicroarch_Intel_Unknown,
199	/[141(0x8d)] = / kCpumMicroarch_Intel_Unknown,
200	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
201	/[143(0x8f)] = / kCpumMicroarch_Intel_Unknown,
202	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
203	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
204	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
205	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
206	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
207	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
208	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
209	/[151(0x97)] = / kCpumMicroarch_Intel_Unknown,
210	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
211	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
212	/[154(0x9a)] = / kCpumMicroarch_Intel_Unknown,
213	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
214	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
215	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
216	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
217	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
218	};
219	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0x9f+1);
220
221
222	/**
223	* Figures out the (sub-)micro architecture given a bit of CPUID info.
224	*
225	* @returns Micro architecture.
226	* @param enmVendor The CPU vendor .
227	* @param bFamily The CPU family.
228	* @param bModel The CPU model.
229	* @param bStepping The CPU stepping.
230	*/
231	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
232	uint8_t bModel, uint8_t bStepping)
233	{
234	if (enmVendor == CPUMCPUVENDOR_AMD)
235	{
236	switch (bFamily)
237	{
238	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
239	case 0x03: return kCpumMicroarch_AMD_Am386;
240	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
241	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
242	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
243	case 0x06:
244	switch (bModel)
245	{
246	case 0: return kCpumMicroarch_AMD_K7_Palomino;
247	case 1: return kCpumMicroarch_AMD_K7_Palomino;
248	case 2: return kCpumMicroarch_AMD_K7_Palomino;
249	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
250	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
251	case 6: return kCpumMicroarch_AMD_K7_Palomino;
252	case 7: return kCpumMicroarch_AMD_K7_Morgan;
253	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
254	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
255	}
256	return kCpumMicroarch_AMD_K7_Unknown;
257	case 0x0f:
258	/*
259	* This family is a friggin mess. Trying my best to make some
260	* sense out of it. Too much happened in the 0x0f family to
261	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
262	*
263	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
264	* cpu-world.com, and other places:
265	* - 130nm:
266	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
267	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
268	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
269	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
270	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
271	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
272	* - 90nm:
273	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
274	* - Oakville: 10FC0/DH-D0.
275	* - Georgetown: 10FC0/DH-D0.
276	* - Sonora: 10FC0/DH-D0.
277	* - Venus: 20F71/SH-E4
278	* - Troy: 20F51/SH-E4
279	* - Athens: 20F51/SH-E4
280	* - San Diego: 20F71/SH-E4.
281	* - Lancaster: 20F42/SH-E5
282	* - Newark: 20F42/SH-E5.
283	* - Albany: 20FC2/DH-E6.
284	* - Roma: 20FC2/DH-E6.
285	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
286	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
287	* - 90nm introducing Dual core:
288	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
289	* - Italy: 20F10/JH-E1, 20F12/JH-E6
290	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
291	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
292	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
293	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
294	* - Santa Ana: 40F32/JH-F2, /-F3
295	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
296	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
297	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
298	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
299	* - Keene: 40FC2/DH-F2.
300	* - Richmond: 40FC2/DH-F2
301	* - Taylor: 40F82/BH-F2
302	* - Trinidad: 40F82/BH-F2
303	*
304	* - 65nm:
305	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
306	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
307	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
308	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
309	* - Sherman: /-G1, 70FC2/DH-G2.
310	* - Huron: 70FF2/DH-G2.
311	*/
312	if (bModel < 0x10)
313	return kCpumMicroarch_AMD_K8_130nm;
314	if (bModel >= 0x60 && bModel < 0x80)
315	return kCpumMicroarch_AMD_K8_65nm;
316	if (bModel >= 0x40)
317	return kCpumMicroarch_AMD_K8_90nm_AMDV;
318	switch (bModel)
319	{
320	case 0x21:
321	case 0x23:
322	case 0x2b:
323	case 0x2f:
324	case 0x37:
325	case 0x3f:
326	return kCpumMicroarch_AMD_K8_90nm_DualCore;
327	}
328	return kCpumMicroarch_AMD_K8_90nm;
329	case 0x10:
330	return kCpumMicroarch_AMD_K10;
331	case 0x11:
332	return kCpumMicroarch_AMD_K10_Lion;
333	case 0x12:
334	return kCpumMicroarch_AMD_K10_Llano;
335	case 0x14:
336	return kCpumMicroarch_AMD_Bobcat;
337	case 0x15:
338	switch (bModel)
339	{
340	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
341	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
342	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
343	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
344	case 0x11: /* ?? */
345	case 0x12: /* ?? */
346	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
347	}
348	return kCpumMicroarch_AMD_15h_Unknown;
349	case 0x16:
350	return kCpumMicroarch_AMD_Jaguar;
351	case 0x17:
352	return kCpumMicroarch_AMD_Zen_Ryzen;
353	}
354	return kCpumMicroarch_AMD_Unknown;
355	}
356
357	if (enmVendor == CPUMCPUVENDOR_INTEL)
358	{
359	switch (bFamily)
360	{
361	case 3:
362	return kCpumMicroarch_Intel_80386;
363	case 4:
364	return kCpumMicroarch_Intel_80486;
365	case 5:
366	return kCpumMicroarch_Intel_P5;
367	case 6:
368	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
369	{
370	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
371	if ( enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake
372	&& bStepping >= 0xa)
373	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
374	return enmMicroArch;
375	}
376	return kCpumMicroarch_Intel_Atom_Unknown;
377	case 15:
378	switch (bModel)
379	{
380	case 0: return kCpumMicroarch_Intel_NB_Willamette;
381	case 1: return kCpumMicroarch_Intel_NB_Willamette;
382	case 2: return kCpumMicroarch_Intel_NB_Northwood;
383	case 3: return kCpumMicroarch_Intel_NB_Prescott;
384	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
385	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
386	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
387	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
388	default: return kCpumMicroarch_Intel_NB_Unknown;
389	}
390	break;
391	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
392	case 0:
393	return kCpumMicroarch_Intel_8086;
394	case 1:
395	return kCpumMicroarch_Intel_80186;
396	case 2:
397	return kCpumMicroarch_Intel_80286;
398	}
399	return kCpumMicroarch_Intel_Unknown;
400	}
401
402	if (enmVendor == CPUMCPUVENDOR_VIA)
403	{
404	switch (bFamily)
405	{
406	case 5:
407	switch (bModel)
408	{
409	case 1: return kCpumMicroarch_Centaur_C6;
410	case 4: return kCpumMicroarch_Centaur_C6;
411	case 8: return kCpumMicroarch_Centaur_C2;
412	case 9: return kCpumMicroarch_Centaur_C3;
413	}
414	break;
415
416	case 6:
417	switch (bModel)
418	{
419	case 5: return kCpumMicroarch_VIA_C3_M2;
420	case 6: return kCpumMicroarch_VIA_C3_C5A;
421	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
422	case 8: return kCpumMicroarch_VIA_C3_C5N;
423	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
424	case 10: return kCpumMicroarch_VIA_C7_C5J;
425	case 15: return kCpumMicroarch_VIA_Isaiah;
426	}
427	break;
428	}
429	return kCpumMicroarch_VIA_Unknown;
430	}
431
432	if (enmVendor == CPUMCPUVENDOR_CYRIX)
433	{
434	switch (bFamily)
435	{
436	case 4:
437	switch (bModel)
438	{
439	case 9: return kCpumMicroarch_Cyrix_5x86;
440	}
441	break;
442
443	case 5:
444	switch (bModel)
445	{
446	case 2: return kCpumMicroarch_Cyrix_M1;
447	case 4: return kCpumMicroarch_Cyrix_MediaGX;
448	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
449	}
450	break;
451
452	case 6:
453	switch (bModel)
454	{
455	case 0: return kCpumMicroarch_Cyrix_M2;
456	}
457	break;
458
459	}
460	return kCpumMicroarch_Cyrix_Unknown;
461	}
462
463	return kCpumMicroarch_Unknown;
464	}
465
466
467	/**
468	* Translates a microarchitecture enum value to the corresponding string
469	* constant.
470	*
471	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
472	* NULL if the value is invalid.
473	*
474	* @param enmMicroarch The enum value to convert.
475	*/
476	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
477	{
478	switch (enmMicroarch)
479	{
480	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
481	CASE_RET_STR(kCpumMicroarch_Intel_8086);
482	CASE_RET_STR(kCpumMicroarch_Intel_80186);
483	CASE_RET_STR(kCpumMicroarch_Intel_80286);
484	CASE_RET_STR(kCpumMicroarch_Intel_80386);
485	CASE_RET_STR(kCpumMicroarch_Intel_80486);
486	CASE_RET_STR(kCpumMicroarch_Intel_P5);
487
488	CASE_RET_STR(kCpumMicroarch_Intel_P6);
489	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
490	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
491
492	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
493	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
494	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
495
496	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
497	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
498
499	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
500	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
501	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
502	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
503	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
504	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
505	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
506	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
507	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
508	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Cannonlake);
509
510	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
511	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
512	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
513	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
514	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
515	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
516	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
517
518	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
519	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
520	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
521	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
522	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
523
524	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
525	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
526	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
527	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
528	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
529	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
530	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
531
532	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
533
534	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
535	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
536	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
537	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
538	CASE_RET_STR(kCpumMicroarch_AMD_K5);
539	CASE_RET_STR(kCpumMicroarch_AMD_K6);
540
541	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
542	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
543	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
544	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
545	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
546	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
547	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
548
549	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
550	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
551	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
552	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
553	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
554
555	CASE_RET_STR(kCpumMicroarch_AMD_K10);
556	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
557	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
558	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
559	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
560
561	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
562	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
563	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
564	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
565	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
566
567	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
568
569	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
570
571	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
572
573	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
574	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
575	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
576	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
577	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
578	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
579	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
580	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
581	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
582	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
583	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
584	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
585	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
586
587	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
588	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
589	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
590	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
591	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
592	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
593
594	CASE_RET_STR(kCpumMicroarch_NEC_V20);
595	CASE_RET_STR(kCpumMicroarch_NEC_V30);
596
597	CASE_RET_STR(kCpumMicroarch_Unknown);
598
599	#undef CASE_RET_STR
600	case kCpumMicroarch_Invalid:
601	case kCpumMicroarch_Intel_End:
602	case kCpumMicroarch_Intel_Core2_End:
603	case kCpumMicroarch_Intel_Core7_End:
604	case kCpumMicroarch_Intel_Atom_End:
605	case kCpumMicroarch_Intel_P6_Core_Atom_End:
606	case kCpumMicroarch_Intel_Phi_End:
607	case kCpumMicroarch_Intel_NB_End:
608	case kCpumMicroarch_AMD_K7_End:
609	case kCpumMicroarch_AMD_K8_End:
610	case kCpumMicroarch_AMD_15h_End:
611	case kCpumMicroarch_AMD_16h_End:
612	case kCpumMicroarch_AMD_Zen_End:
613	case kCpumMicroarch_AMD_End:
614	case kCpumMicroarch_VIA_End:
615	case kCpumMicroarch_Cyrix_End:
616	case kCpumMicroarch_NEC_End:
617	case kCpumMicroarch_32BitHack:
618	break;
619	/* no default! */
620	}
621
622	return NULL;
623	}
624
625
626	/**
627	* Determins the host CPU MXCSR mask.
628	*
629	* @returns MXCSR mask.
630	*/
631	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
632	{
633	if ( ASMHasCpuId()
634	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
635	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
636	{
637	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
638	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
639	RT_ZERO(*pState);
640	ASMFxSave(pState);
641	if (pState->MXCSR_MASK == 0)
642	return 0xffbf;
643	return pState->MXCSR_MASK;
644	}
645	return 0;
646	}
647
648
649	/**
650	* Gets a matching leaf in the CPUID leaf array.
651	*
652	* @returns Pointer to the matching leaf, or NULL if not found.
653	* @param paLeaves The CPUID leaves to search. This is sorted.
654	* @param cLeaves The number of leaves in the array.
655	* @param uLeaf The leaf to locate.
656	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
657	*/
658	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
659	{
660	/* Lazy bird does linear lookup here since this is only used for the
661	occational CPUID overrides. */
662	for (uint32_t i = 0; i < cLeaves; i++)
663	if ( paLeaves[i].uLeaf == uLeaf
664	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
665	return &paLeaves[i];
666	return NULL;
667	}
668
669
670	#ifndef IN_VBOX_CPU_REPORT
671	/**
672	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
673	*
674	* @returns true if found, false it not.
675	* @param paLeaves The CPUID leaves to search. This is sorted.
676	* @param cLeaves The number of leaves in the array.
677	* @param uLeaf The leaf to locate.
678	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
679	* @param pLegacy The legacy output leaf.
680	*/
681	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
682	PCPUMCPUID pLegacy)
683	{
684	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
685	if (pLeaf)
686	{
687	pLegacy->uEax = pLeaf->uEax;
688	pLegacy->uEbx = pLeaf->uEbx;
689	pLegacy->uEcx = pLeaf->uEcx;
690	pLegacy->uEdx = pLeaf->uEdx;
691	return true;
692	}
693	return false;
694	}
695	#endif /* IN_VBOX_CPU_REPORT */
696
697
698	/**
699	* Ensures that the CPUID leaf array can hold one more leaf.
700	*
701	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
702	* failure.
703	* @param pVM The cross context VM structure. If NULL, use
704	* the process heap, otherwise the VM's hyper heap.
705	* @param ppaLeaves Pointer to the variable holding the array pointer
706	* (input/output).
707	* @param cLeaves The current array size.
708	*
709	* @remarks This function will automatically update the R0 and RC pointers when
710	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
711	* be the corresponding VM's CPUID arrays (which is asserted).
712	*/
713	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
714	{
715	/*
716	* If pVM is not specified, we're on the regular heap and can waste a
717	* little space to speed things up.
718	*/
719	uint32_t cAllocated;
720	if (!pVM)
721	{
722	cAllocated = RT_ALIGN(cLeaves, 16);
723	if (cLeaves + 1 > cAllocated)
724	{
725	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
726	if (pvNew)
727	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
728	else
729	{
730	RTMemFree(*ppaLeaves);
731	*ppaLeaves = NULL;
732	}
733	}
734	}
735	/*
736	* Otherwise, we're on the hyper heap and are probably just inserting
737	* one or two leaves and should conserve space.
738	*/
739	else
740	{
741	#ifdef IN_VBOX_CPU_REPORT
742	AssertReleaseFailed();
743	#else
744	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
745	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
746
747	size_t cb = cLeaves * sizeof(**ppaLeaves);
748	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
749	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
750	if (RT_SUCCESS(rc))
751	{
752	/* Update the R0 and RC pointers. */
753	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
754	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
755	}
756	else
757	{
758	*ppaLeaves = NULL;
759	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
760	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
761	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
762	}
763	#endif
764	}
765	return *ppaLeaves;
766	}
767
768
769	/**
770	* Append a CPUID leaf or sub-leaf.
771	*
772	* ASSUMES linear insertion order, so we'll won't need to do any searching or
773	* replace anything. Use cpumR3CpuIdInsert() for those cases.
774	*
775	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
776	* the caller need do no more work.
777	* @param ppaLeaves Pointer to the pointer to the array of sorted
778	* CPUID leaves and sub-leaves.
779	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
780	* @param uLeaf The leaf we're adding.
781	* @param uSubLeaf The sub-leaf number.
782	* @param fSubLeafMask The sub-leaf mask.
783	* @param uEax The EAX value.
784	* @param uEbx The EBX value.
785	* @param uEcx The ECX value.
786	* @param uEdx The EDX value.
787	* @param fFlags The flags.
788	*/
789	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
790	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
791	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
792	{
793	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
794	return VERR_NO_MEMORY;
795
796	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
797	Assert( *pcLeaves == 0
798	\|\| pNew[-1].uLeaf < uLeaf
799	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
800
801	pNew->uLeaf = uLeaf;
802	pNew->uSubLeaf = uSubLeaf;
803	pNew->fSubLeafMask = fSubLeafMask;
804	pNew->uEax = uEax;
805	pNew->uEbx = uEbx;
806	pNew->uEcx = uEcx;
807	pNew->uEdx = uEdx;
808	pNew->fFlags = fFlags;
809
810	*pcLeaves += 1;
811	return VINF_SUCCESS;
812	}
813
814
815	/**
816	* Checks that we've updated the CPUID leaves array correctly.
817	*
818	* This is a no-op in non-strict builds.
819	*
820	* @param paLeaves The leaves array.
821	* @param cLeaves The number of leaves.
822	*/
823	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
824	{
825	#ifdef VBOX_STRICT
826	for (uint32_t i = 1; i < cLeaves; i++)
827	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
828	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
829	else
830	{
831	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
832	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
833	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
834	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
835	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
836	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
837	}
838	#else
839	NOREF(paLeaves);
840	NOREF(cLeaves);
841	#endif
842	}
843
844
845	/**
846	* Inserts a CPU ID leaf, replacing any existing ones.
847	*
848	* When inserting a simple leaf where we already got a series of sub-leaves with
849	* the same leaf number (eax), the simple leaf will replace the whole series.
850	*
851	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
852	* host-context heap and has only been allocated/reallocated by the
853	* cpumR3CpuIdEnsureSpace function.
854	*
855	* @returns VBox status code.
856	* @param pVM The cross context VM structure. If NULL, use
857	* the process heap, otherwise the VM's hyper heap.
858	* @param ppaLeaves Pointer to the pointer to the array of sorted
859	* CPUID leaves and sub-leaves. Must be NULL if using
860	* the hyper heap.
861	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
862	* be NULL if using the hyper heap.
863	* @param pNewLeaf Pointer to the data of the new leaf we're about to
864	* insert.
865	*/
866	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
867	{
868	/*
869	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
870	*/
871	if (pVM)
872	{
873	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
874	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
875
876	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
877	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
878	}
879
880	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
881	uint32_t cLeaves = *pcLeaves;
882
883	/*
884	* Validate the new leaf a little.
885	*/
886	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
887	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
888	VERR_INVALID_FLAGS);
889	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
890	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
891	VERR_INVALID_PARAMETER);
892	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
893	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
894	VERR_INVALID_PARAMETER);
895	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
896	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
897	VERR_INVALID_PARAMETER);
898
899	/*
900	* Find insertion point. The lazy bird uses the same excuse as in
901	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
902	*/
903	uint32_t i;
904	if ( cLeaves > 0
905	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
906	{
907	/* Add at end. */
908	i = cLeaves;
909	}
910	else if ( cLeaves > 0
911	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
912	{
913	/* Either replacing the last leaf or dealing with sub-leaves. Spool
914	back to the first sub-leaf to pretend we did the linear search. */
915	i = cLeaves - 1;
916	while ( i > 0
917	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
918	i--;
919	}
920	else
921	{
922	/* Linear search from the start. */
923	i = 0;
924	while ( i < cLeaves
925	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
926	i++;
927	}
928	if ( i < cLeaves
929	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
930	{
931	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
932	{
933	/*
934	* The sub-leaf mask differs, replace all existing leaves with the
935	* same leaf number.
936	*/
937	uint32_t c = 1;
938	while ( i + c < cLeaves
939	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
940	c++;
941	if (c > 1 && i + c < cLeaves)
942	{
943	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
944	*pcLeaves = cLeaves -= c - 1;
945	}
946
947	paLeaves[i] = *pNewLeaf;
948	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
949	return VINF_SUCCESS;
950	}
951
952	/* Find sub-leaf insertion point. */
953	while ( i < cLeaves
954	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
955	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
956	i++;
957
958	/*
959	* If we've got an exactly matching leaf, replace it.
960	*/
961	if ( i < cLeaves
962	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
963	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
964	{
965	paLeaves[i] = *pNewLeaf;
966	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
967	return VINF_SUCCESS;
968	}
969	}
970
971	/*
972	* Adding a new leaf at 'i'.
973	*/
974	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
975	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
976	if (!paLeaves)
977	return VERR_NO_MEMORY;
978
979	if (i < cLeaves)
980	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
981	*pcLeaves += 1;
982	paLeaves[i] = *pNewLeaf;
983
984	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
985	return VINF_SUCCESS;
986	}
987
988
989	#ifndef IN_VBOX_CPU_REPORT
990	/**
991	* Removes a range of CPUID leaves.
992	*
993	* This will not reallocate the array.
994	*
995	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
996	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
997	* @param uFirst The first leaf.
998	* @param uLast The last leaf.
999	*/
1000	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1001	{
1002	uint32_t cLeaves = *pcLeaves;
1003
1004	Assert(uFirst <= uLast);
1005
1006	/*
1007	* Find the first one.
1008	*/
1009	uint32_t iFirst = 0;
1010	while ( iFirst < cLeaves
1011	&& paLeaves[iFirst].uLeaf < uFirst)
1012	iFirst++;
1013
1014	/*
1015	* Find the end (last + 1).
1016	*/
1017	uint32_t iEnd = iFirst;
1018	while ( iEnd < cLeaves
1019	&& paLeaves[iEnd].uLeaf <= uLast)
1020	iEnd++;
1021
1022	/*
1023	* Adjust the array if anything needs removing.
1024	*/
1025	if (iFirst < iEnd)
1026	{
1027	if (iEnd < cLeaves)
1028	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1029	*pcLeaves = cLeaves -= (iEnd - iFirst);
1030	}
1031
1032	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1033	}
1034	#endif /* IN_VBOX_CPU_REPORT */
1035
1036
1037	/**
1038	* Checks if ECX make a difference when reading a given CPUID leaf.
1039	*
1040	* @returns @c true if it does, @c false if it doesn't.
1041	* @param uLeaf The leaf we're reading.
1042	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1043	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1044	* final sub-leaf (for leaf 0xb only).
1045	*/
1046	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1047	{
1048	*pfFinalEcxUnchanged = false;
1049
1050	uint32_t auCur[4];
1051	uint32_t auPrev[4];
1052	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1053
1054	/* Look for sub-leaves. */
1055	uint32_t uSubLeaf = 1;
1056	for (;;)
1057	{
1058	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1059	if (memcmp(auCur, auPrev, sizeof(auCur)))
1060	break;
1061
1062	/* Advance / give up. */
1063	uSubLeaf++;
1064	if (uSubLeaf >= 64)
1065	{
1066	*pcSubLeaves = 1;
1067	return false;
1068	}
1069	}
1070
1071	/* Count sub-leaves. */
1072	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1073	uint32_t cRepeats = 0;
1074	uSubLeaf = 0;
1075	for (;;)
1076	{
1077	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1078
1079	/* Figuring out when to stop isn't entirely straight forward as we need
1080	to cover undocumented behavior up to a point and implementation shortcuts. */
1081
1082	/* 1. Look for more than 4 repeating value sets. */
1083	if ( auCur[0] == auPrev[0]
1084	&& auCur[1] == auPrev[1]
1085	&& ( auCur[2] == auPrev[2]
1086	\|\| ( auCur[2] == uSubLeaf
1087	&& auPrev[2] == uSubLeaf - 1) )
1088	&& auCur[3] == auPrev[3])
1089	{
1090	if ( uLeaf != 0xd
1091	\|\| uSubLeaf >= 64
1092	\|\| ( auCur[0] == 0
1093	&& auCur[1] == 0
1094	&& auCur[2] == 0
1095	&& auCur[3] == 0
1096	&& auPrev[2] == 0) )
1097	cRepeats++;
1098	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1099	break;
1100	}
1101	else
1102	cRepeats = 0;
1103
1104	/* 2. Look for zero values. */
1105	if ( auCur[0] == 0
1106	&& auCur[1] == 0
1107	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1108	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1109	&& uSubLeaf >= cMinLeaves)
1110	{
1111	cRepeats = 0;
1112	break;
1113	}
1114
1115	/* 3. Leaf 0xb level type 0 check. */
1116	if ( uLeaf == 0xb
1117	&& (auCur[2] & 0xff00) == 0
1118	&& (auPrev[2] & 0xff00) == 0)
1119	{
1120	cRepeats = 0;
1121	break;
1122	}
1123
1124	/* 99. Give up. */
1125	if (uSubLeaf >= 128)
1126	{
1127	#ifndef IN_VBOX_CPU_REPORT
1128	/* Ok, limit it according to the documentation if possible just to
1129	avoid annoying users with these detection issues. */
1130	uint32_t cDocLimit = UINT32_MAX;
1131	if (uLeaf == 0x4)
1132	cDocLimit = 4;
1133	else if (uLeaf == 0x7)
1134	cDocLimit = 1;
1135	else if (uLeaf == 0xd)
1136	cDocLimit = 63;
1137	else if (uLeaf == 0xf)
1138	cDocLimit = 2;
1139	if (cDocLimit != UINT32_MAX)
1140	{
1141	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1142	*pcSubLeaves = cDocLimit + 3;
1143	return true;
1144	}
1145	#endif
1146	*pcSubLeaves = UINT32_MAX;
1147	return true;
1148	}
1149
1150	/* Advance. */
1151	uSubLeaf++;
1152	memcpy(auPrev, auCur, sizeof(auCur));
1153	}
1154
1155	/* Standard exit. */
1156	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1157	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1158	if (*pcSubLeaves == 0)
1159	*pcSubLeaves = 1;
1160	return true;
1161	}
1162
1163
1164	/**
1165	* Gets a CPU ID leaf.
1166	*
1167	* @returns VBox status code.
1168	* @param pVM The cross context VM structure.
1169	* @param pLeaf Where to store the found leaf.
1170	* @param uLeaf The leaf to locate.
1171	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1172	*/
1173	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1174	{
1175	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1176	uLeaf, uSubLeaf);
1177	if (pcLeaf)
1178	{
1179	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1180	return VINF_SUCCESS;
1181	}
1182
1183	return VERR_NOT_FOUND;
1184	}
1185
1186
1187	/**
1188	* Inserts a CPU ID leaf, replacing any existing ones.
1189	*
1190	* @returns VBox status code.
1191	* @param pVM The cross context VM structure.
1192	* @param pNewLeaf Pointer to the leaf being inserted.
1193	*/
1194	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1195	{
1196	/*
1197	* Validate parameters.
1198	*/
1199	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1200	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1201
1202	/*
1203	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1204	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1205	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1206	*/
1207	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1208	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1209	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1210	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1211	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1212	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1213	{
1214	return VERR_NOT_SUPPORTED;
1215	}
1216
1217	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1218	}
1219
1220	/**
1221	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1222	*
1223	* @returns VBox status code.
1224	* @param ppaLeaves Where to return the array pointer on success.
1225	* Use RTMemFree to release.
1226	* @param pcLeaves Where to return the size of the array on
1227	* success.
1228	*/
1229	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1230	{
1231	*ppaLeaves = NULL;
1232	*pcLeaves = 0;
1233
1234	/*
1235	* Try out various candidates. This must be sorted!
1236	*/
1237	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1238	{
1239	{ UINT32_C(0x00000000), false },
1240	{ UINT32_C(0x10000000), false },
1241	{ UINT32_C(0x20000000), false },
1242	{ UINT32_C(0x30000000), false },
1243	{ UINT32_C(0x40000000), false },
1244	{ UINT32_C(0x50000000), false },
1245	{ UINT32_C(0x60000000), false },
1246	{ UINT32_C(0x70000000), false },
1247	{ UINT32_C(0x80000000), false },
1248	{ UINT32_C(0x80860000), false },
1249	{ UINT32_C(0x8ffffffe), true },
1250	{ UINT32_C(0x8fffffff), true },
1251	{ UINT32_C(0x90000000), false },
1252	{ UINT32_C(0xa0000000), false },
1253	{ UINT32_C(0xb0000000), false },
1254	{ UINT32_C(0xc0000000), false },
1255	{ UINT32_C(0xd0000000), false },
1256	{ UINT32_C(0xe0000000), false },
1257	{ UINT32_C(0xf0000000), false },
1258	};
1259
1260	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1261	{
1262	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1263	uint32_t uEax, uEbx, uEcx, uEdx;
1264	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1265
1266	/*
1267	* Does EAX look like a typical leaf count value?
1268	*/
1269	if ( uEax > uLeaf
1270	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1271	{
1272	/* Yes, dump them. */
1273	uint32_t cLeaves = uEax - uLeaf + 1;
1274	while (cLeaves-- > 0)
1275	{
1276	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1277
1278	uint32_t fFlags = 0;
1279
1280	/* There are currently three known leaves containing an APIC ID
1281	that needs EMT specific attention */
1282	if (uLeaf == 1)
1283	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1284	else if (uLeaf == 0xb && uEcx != 0)
1285	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1286	else if ( uLeaf == UINT32_C(0x8000001e)
1287	&& ( uEax
1288	\|\| uEbx
1289	\|\| uEdx
1290	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1291	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1292
1293	/* The APIC bit is per-VCpu and needs flagging. */
1294	if (uLeaf == 1)
1295	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1296	else if ( uLeaf == UINT32_C(0x80000001)
1297	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1298	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1299	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1300
1301	/* Check three times here to reduce the chance of CPU migration
1302	resulting in false positives with things like the APIC ID. */
1303	uint32_t cSubLeaves;
1304	bool fFinalEcxUnchanged;
1305	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1306	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1307	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1308	{
1309	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1310	{
1311	/* This shouldn't happen. But in case it does, file all
1312	relevant details in the release log. */
1313	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1314	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1315	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1316	{
1317	uint32_t auTmp[4];
1318	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1319	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1320	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1321	}
1322	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1323	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1324	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1325	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1326	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1327	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1328	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1329	}
1330
1331	if (fFinalEcxUnchanged)
1332	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1333
1334	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1335	{
1336	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1337	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1338	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1339	if (RT_FAILURE(rc))
1340	return rc;
1341	}
1342	}
1343	else
1344	{
1345	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1346	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1347	if (RT_FAILURE(rc))
1348	return rc;
1349	}
1350
1351	/* next */
1352	uLeaf++;
1353	}
1354	}
1355	/*
1356	* Special CPUIDs needs special handling as they don't follow the
1357	* leaf count principle used above.
1358	*/
1359	else if (s_aCandidates[iOuter].fSpecial)
1360	{
1361	bool fKeep = false;
1362	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1363	fKeep = true;
1364	else if ( uLeaf == 0x8fffffff
1365	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1366	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1367	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1368	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1369	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1370	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1371	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1372	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1373	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1374	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1375	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1376	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1377	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1378	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1379	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1380	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1381	fKeep = true;
1382	if (fKeep)
1383	{
1384	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1385	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1386	if (RT_FAILURE(rc))
1387	return rc;
1388	}
1389	}
1390	}
1391
1392	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1393	return VINF_SUCCESS;
1394	}
1395
1396
1397	/**
1398	* Determines the method the CPU uses to handle unknown CPUID leaves.
1399	*
1400	* @returns VBox status code.
1401	* @param penmUnknownMethod Where to return the method.
1402	* @param pDefUnknown Where to return default unknown values. This
1403	* will be set, even if the resulting method
1404	* doesn't actually needs it.
1405	*/
1406	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1407	{
1408	uint32_t uLastStd = ASMCpuId_EAX(0);
1409	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1410	if (!ASMIsValidExtRange(uLastExt))
1411	uLastExt = 0x80000000;
1412
1413	uint32_t auChecks[] =
1414	{
1415	uLastStd + 1,
1416	uLastStd + 5,
1417	uLastStd + 8,
1418	uLastStd + 32,
1419	uLastStd + 251,
1420	uLastExt + 1,
1421	uLastExt + 8,
1422	uLastExt + 15,
1423	uLastExt + 63,
1424	uLastExt + 255,
1425	0x7fbbffcc,
1426	0x833f7872,
1427	0xefff2353,
1428	0x35779456,
1429	0x1ef6d33e,
1430	};
1431
1432	static const uint32_t s_auValues[] =
1433	{
1434	0xa95d2156,
1435	0x00000001,
1436	0x00000002,
1437	0x00000008,
1438	0x00000000,
1439	0x55773399,
1440	0x93401769,
1441	0x12039587,
1442	};
1443
1444	/*
1445	* Simple method, all zeros.
1446	*/
1447	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1448	pDefUnknown->uEax = 0;
1449	pDefUnknown->uEbx = 0;
1450	pDefUnknown->uEcx = 0;
1451	pDefUnknown->uEdx = 0;
1452
1453	/*
1454	* Intel has been observed returning the last standard leaf.
1455	*/
1456	uint32_t auLast[4];
1457	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1458
1459	uint32_t cChecks = RT_ELEMENTS(auChecks);
1460	while (cChecks > 0)
1461	{
1462	uint32_t auCur[4];
1463	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1464	if (memcmp(auCur, auLast, sizeof(auCur)))
1465	break;
1466	cChecks--;
1467	}
1468	if (cChecks == 0)
1469	{
1470	/* Now, what happens when the input changes? Esp. ECX. */
1471	uint32_t cTotal = 0;
1472	uint32_t cSame = 0;
1473	uint32_t cLastWithEcx = 0;
1474	uint32_t cNeither = 0;
1475	uint32_t cValues = RT_ELEMENTS(s_auValues);
1476	while (cValues > 0)
1477	{
1478	uint32_t uValue = s_auValues[cValues - 1];
1479	uint32_t auLastWithEcx[4];
1480	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1481	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1482
1483	cChecks = RT_ELEMENTS(auChecks);
1484	while (cChecks > 0)
1485	{
1486	uint32_t auCur[4];
1487	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1488	if (!memcmp(auCur, auLast, sizeof(auCur)))
1489	{
1490	cSame++;
1491	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1492	cLastWithEcx++;
1493	}
1494	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1495	cLastWithEcx++;
1496	else
1497	cNeither++;
1498	cTotal++;
1499	cChecks--;
1500	}
1501	cValues--;
1502	}
1503
1504	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1505	if (cSame == cTotal)
1506	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1507	else if (cLastWithEcx == cTotal)
1508	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1509	else
1510	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1511	pDefUnknown->uEax = auLast[0];
1512	pDefUnknown->uEbx = auLast[1];
1513	pDefUnknown->uEcx = auLast[2];
1514	pDefUnknown->uEdx = auLast[3];
1515	return VINF_SUCCESS;
1516	}
1517
1518	/*
1519	* Unchanged register values?
1520	*/
1521	cChecks = RT_ELEMENTS(auChecks);
1522	while (cChecks > 0)
1523	{
1524	uint32_t const uLeaf = auChecks[cChecks - 1];
1525	uint32_t cValues = RT_ELEMENTS(s_auValues);
1526	while (cValues > 0)
1527	{
1528	uint32_t uValue = s_auValues[cValues - 1];
1529	uint32_t auCur[4];
1530	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1531	if ( auCur[0] != uLeaf
1532	\|\| auCur[1] != uValue
1533	\|\| auCur[2] != uValue
1534	\|\| auCur[3] != uValue)
1535	break;
1536	cValues--;
1537	}
1538	if (cValues != 0)
1539	break;
1540	cChecks--;
1541	}
1542	if (cChecks == 0)
1543	{
1544	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1545	return VINF_SUCCESS;
1546	}
1547
1548	/*
1549	* Just go with the simple method.
1550	*/
1551	return VINF_SUCCESS;
1552	}
1553
1554
1555	/**
1556	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1557	*
1558	* @returns Read only name string.
1559	* @param enmUnknownMethod The method to translate.
1560	*/
1561	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1562	{
1563	switch (enmUnknownMethod)
1564	{
1565	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1566	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1567	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1568	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1569
1570	case CPUMUNKNOWNCPUID_INVALID:
1571	case CPUMUNKNOWNCPUID_END:
1572	case CPUMUNKNOWNCPUID_32BIT_HACK:
1573	break;
1574	}
1575	return "Invalid-unknown-CPUID-method";
1576	}
1577
1578
1579	/**
1580	* Detect the CPU vendor give n the
1581	*
1582	* @returns The vendor.
1583	* @param uEAX EAX from CPUID(0).
1584	* @param uEBX EBX from CPUID(0).
1585	* @param uECX ECX from CPUID(0).
1586	* @param uEDX EDX from CPUID(0).
1587	*/
1588	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1589	{
1590	if (ASMIsValidStdRange(uEAX))
1591	{
1592	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1593	return CPUMCPUVENDOR_AMD;
1594
1595	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1596	return CPUMCPUVENDOR_INTEL;
1597
1598	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1599	return CPUMCPUVENDOR_VIA;
1600
1601	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1602	&& uECX == UINT32_C(0x64616574)
1603	&& uEDX == UINT32_C(0x736E4978))
1604	return CPUMCPUVENDOR_CYRIX;
1605
1606	/* "Geode by NSC", example: family 5, model 9. */
1607
1608	/** @todo detect the other buggers... */
1609	}
1610
1611	return CPUMCPUVENDOR_UNKNOWN;
1612	}
1613
1614
1615	/**
1616	* Translates a CPU vendor enum value into the corresponding string constant.
1617	*
1618	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1619	* value name. This can be useful when generating code.
1620	*
1621	* @returns Read only name string.
1622	* @param enmVendor The CPU vendor value.
1623	*/
1624	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1625	{
1626	switch (enmVendor)
1627	{
1628	case CPUMCPUVENDOR_INTEL: return "INTEL";
1629	case CPUMCPUVENDOR_AMD: return "AMD";
1630	case CPUMCPUVENDOR_VIA: return "VIA";
1631	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1632	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1633
1634	case CPUMCPUVENDOR_INVALID:
1635	case CPUMCPUVENDOR_32BIT_HACK:
1636	break;
1637	}
1638	return "Invalid-cpu-vendor";
1639	}
1640
1641
1642	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1643	{
1644	/* Could do binary search, doing linear now because I'm lazy. */
1645	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1646	while (cLeaves-- > 0)
1647	{
1648	if (pLeaf->uLeaf == uLeaf)
1649	return pLeaf;
1650	pLeaf++;
1651	}
1652	return NULL;
1653	}
1654
1655
1656	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1657	{
1658	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1659	if ( !pLeaf
1660	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1661	return pLeaf;
1662
1663	/* Linear sub-leaf search. Lazy as usual. */
1664	cLeaves -= pLeaf - paLeaves;
1665	while ( cLeaves-- > 0
1666	&& pLeaf->uLeaf == uLeaf)
1667	{
1668	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1669	return pLeaf;
1670	pLeaf++;
1671	}
1672
1673	return NULL;
1674	}
1675
1676
1677	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1678	{
1679	RT_ZERO(*pFeatures);
1680	if (cLeaves >= 2)
1681	{
1682	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1683	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1684	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1685	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1686	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1687	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1688
1689	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1690	pStd0Leaf->uEbx,
1691	pStd0Leaf->uEcx,
1692	pStd0Leaf->uEdx);
1693	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1694	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1695	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1696	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1697	pFeatures->uFamily,
1698	pFeatures->uModel,
1699	pFeatures->uStepping);
1700
1701	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1702	if (pLeaf)
1703	pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff;
1704	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1705	pFeatures->cMaxPhysAddrWidth = 36;
1706	else
1707	pFeatures->cMaxPhysAddrWidth = 32;
1708
1709	/* Standard features. */
1710	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1711	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1712	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1713	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1714	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1715	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1716	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1717	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1718	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1719	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1720	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1721	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1722	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1723	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1724	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1725	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1726	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1727	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1728	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1729	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1730	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1731	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1732	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1733	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1734
1735	/* Structured extended features. */
1736	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1737	if (pSxfLeaf0)
1738	{
1739	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1740	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1741	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1742	}
1743
1744	/* MWAIT/MONITOR leaf. */
1745	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1746	if (pMWaitLeaf)
1747	{
1748	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1749	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1750	}
1751
1752	/* Extended features. */
1753	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1754	if (pExtLeaf)
1755	{
1756	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1757	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1758	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1759	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1760	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1761	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1762	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1763	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1764	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1765	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1766	}
1767
1768	if ( pExtLeaf
1769	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1770	{
1771	/* AMD features. */
1772	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1773	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1774	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1775	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1776	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1777	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1778	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1779	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1780	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1781	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1782	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1783	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1784	if (pFeatures->fSvm)
1785	{
1786	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1787	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1788	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1789	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1790	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1791	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1792	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1793	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1794	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1795	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1796	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1797	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1798	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1799	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1800	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1801	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1802	}
1803	}
1804
1805	/*
1806	* Quirks.
1807	*/
1808	pFeatures->fLeakyFxSR = pExtLeaf
1809	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1810	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1811	&& pFeatures->uFamily >= 6 /* K7 and up */;
1812
1813	/*
1814	* Max extended (/FPU) state.
1815	*/
1816	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1817	if (pFeatures->fXSaveRstor)
1818	{
1819	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1820	if (pXStateLeaf0)
1821	{
1822	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1823	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1824	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1825	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1826	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1827	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1828	{
1829	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1830
1831	/* (paranoia:) */
1832	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1833	if ( pXStateLeaf1
1834	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1835	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1836	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1837	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1838	}
1839	else
1840	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1841	pFeatures->fXSaveRstor = 0);
1842	}
1843	else
1844	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1845	pFeatures->fXSaveRstor = 0);
1846	}
1847	}
1848	else
1849	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1850	return VINF_SUCCESS;
1851	}
1852
1853
1854	/*
1855	*
1856	* Init related code.
1857	* Init related code.
1858	* Init related code.
1859	*
1860	*
1861	*/
1862	#ifdef VBOX_IN_VMM
1863
1864
1865	/**
1866	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1867	*
1868	* This ignores the fSubLeafMask.
1869	*
1870	* @returns Pointer to the matching leaf, or NULL if not found.
1871	* @param paLeaves The CPUID leaves to search. This is sorted.
1872	* @param cLeaves The number of leaves in the array.
1873	* @param uLeaf The leaf to locate.
1874	* @param uSubLeaf The subleaf to locate.
1875	*/
1876	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1877	{
1878	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1879	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1880	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1881	if (iEnd)
1882	{
1883	uint32_t iBegin = 0;
1884	for (;;)
1885	{
1886	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1887	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1888	if (uNeedle < uCur)
1889	{
1890	if (i > iBegin)
1891	iEnd = i;
1892	else
1893	break;
1894	}
1895	else if (uNeedle > uCur)
1896	{
1897	if (i + 1 < iEnd)
1898	iBegin = i + 1;
1899	else
1900	break;
1901	}
1902	else
1903	return &paLeaves[i];
1904	}
1905	}
1906	return NULL;
1907	}
1908
1909
1910	/**
1911	* Loads MSR range overrides.
1912	*
1913	* This must be called before the MSR ranges are moved from the normal heap to
1914	* the hyper heap!
1915	*
1916	* @returns VBox status code (VMSetError called).
1917	* @param pVM The cross context VM structure.
1918	* @param pMsrNode The CFGM node with the MSR overrides.
1919	*/
1920	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1921	{
1922	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1923	{
1924	/*
1925	* Assemble a valid MSR range.
1926	*/
1927	CPUMMSRRANGE MsrRange;
1928	MsrRange.offCpumCpu = 0;
1929	MsrRange.fReserved = 0;
1930
1931	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1932	if (RT_FAILURE(rc))
1933	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1934
1935	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1936	if (RT_FAILURE(rc))
1937	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1938	MsrRange.szName, rc);
1939
1940	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1941	if (RT_FAILURE(rc))
1942	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1943	MsrRange.szName, rc);
1944
1945	char szType[32];
1946	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1947	if (RT_FAILURE(rc))
1948	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1949	MsrRange.szName, rc);
1950	if (!RTStrICmp(szType, "FixedValue"))
1951	{
1952	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1953	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1954
1955	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1956	if (RT_FAILURE(rc))
1957	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1958	MsrRange.szName, rc);
1959
1960	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1961	if (RT_FAILURE(rc))
1962	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1963	MsrRange.szName, rc);
1964
1965	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1966	if (RT_FAILURE(rc))
1967	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1968	MsrRange.szName, rc);
1969	}
1970	else
1971	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1972	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1973
1974	/*
1975	* Insert the range into the table (replaces/splits/shrinks existing
1976	* MSR ranges).
1977	*/
1978	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1979	&MsrRange);
1980	if (RT_FAILURE(rc))
1981	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
1982	}
1983
1984	return VINF_SUCCESS;
1985	}
1986
1987
1988	/**
1989	* Loads CPUID leaf overrides.
1990	*
1991	* This must be called before the CPUID leaves are moved from the normal
1992	* heap to the hyper heap!
1993	*
1994	* @returns VBox status code (VMSetError called).
1995	* @param pVM The cross context VM structure.
1996	* @param pParentNode The CFGM node with the CPUID leaves.
1997	* @param pszLabel How to label the overrides we're loading.
1998	*/
1999	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2000	{
2001	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2002	{
2003	/*
2004	* Get the leaf and subleaf numbers.
2005	*/
2006	char szName[128];
2007	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2008	if (RT_FAILURE(rc))
2009	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2010
2011	/* The leaf number is either specified directly or thru the node name. */
2012	uint32_t uLeaf;
2013	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2014	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2015	{
2016	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2017	if (rc != VINF_SUCCESS)
2018	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2019	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2020	}
2021	else if (RT_FAILURE(rc))
2022	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2023	pszLabel, szName, rc);
2024
2025	uint32_t uSubLeaf;
2026	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2027	if (RT_FAILURE(rc))
2028	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2029	pszLabel, szName, rc);
2030
2031	uint32_t fSubLeafMask;
2032	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2033	if (RT_FAILURE(rc))
2034	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2035	pszLabel, szName, rc);
2036
2037	/*
2038	* Look up the specified leaf, since the output register values
2039	* defaults to any existing values. This allows overriding a single
2040	* register, without needing to know the other values.
2041	*/
2042	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2043	CPUMCPUIDLEAF Leaf;
2044	if (pLeaf)
2045	Leaf = *pLeaf;
2046	else
2047	RT_ZERO(Leaf);
2048	Leaf.uLeaf = uLeaf;
2049	Leaf.uSubLeaf = uSubLeaf;
2050	Leaf.fSubLeafMask = fSubLeafMask;
2051
2052	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2053	if (RT_FAILURE(rc))
2054	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2055	pszLabel, szName, rc);
2056	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2057	if (RT_FAILURE(rc))
2058	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2059	pszLabel, szName, rc);
2060	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2061	if (RT_FAILURE(rc))
2062	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2063	pszLabel, szName, rc);
2064	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2065	if (RT_FAILURE(rc))
2066	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2067	pszLabel, szName, rc);
2068
2069	/*
2070	* Insert the leaf into the table (replaces existing ones).
2071	*/
2072	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2073	&Leaf);
2074	if (RT_FAILURE(rc))
2075	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2076	}
2077
2078	return VINF_SUCCESS;
2079	}
2080
2081
2082
2083	/**
2084	* Fetches overrides for a CPUID leaf.
2085	*
2086	* @returns VBox status code.
2087	* @param pLeaf The leaf to load the overrides into.
2088	* @param pCfgNode The CFGM node containing the overrides
2089	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2090	* @param iLeaf The CPUID leaf number.
2091	*/
2092	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2093	{
2094	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2095	if (pLeafNode)
2096	{
2097	uint32_t u32;
2098	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2099	if (RT_SUCCESS(rc))
2100	pLeaf->uEax = u32;
2101	else
2102	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2103
2104	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2105	if (RT_SUCCESS(rc))
2106	pLeaf->uEbx = u32;
2107	else
2108	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2109
2110	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2111	if (RT_SUCCESS(rc))
2112	pLeaf->uEcx = u32;
2113	else
2114	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2115
2116	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2117	if (RT_SUCCESS(rc))
2118	pLeaf->uEdx = u32;
2119	else
2120	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2121
2122	}
2123	return VINF_SUCCESS;
2124	}
2125
2126
2127	/**
2128	* Load the overrides for a set of CPUID leaves.
2129	*
2130	* @returns VBox status code.
2131	* @param paLeaves The leaf array.
2132	* @param cLeaves The number of leaves.
2133	* @param uStart The start leaf number.
2134	* @param pCfgNode The CFGM node containing the overrides
2135	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2136	*/
2137	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2138	{
2139	for (uint32_t i = 0; i < cLeaves; i++)
2140	{
2141	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2142	if (RT_FAILURE(rc))
2143	return rc;
2144	}
2145
2146	return VINF_SUCCESS;
2147	}
2148
2149
2150	/**
2151	* Installs the CPUID leaves and explods the data into structures like
2152	* GuestFeatures and CPUMCTX::aoffXState.
2153	*
2154	* @returns VBox status code.
2155	* @param pVM The cross context VM structure.
2156	* @param pCpum The CPUM part of @a VM.
2157	* @param paLeaves The leaves. These will be copied (but not freed).
2158	* @param cLeaves The number of leaves.
2159	*/
2160	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
2161	{
2162	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2163
2164	/*
2165	* Install the CPUID information.
2166	*/
2167	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2168	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2169
2170	AssertLogRelRCReturn(rc, rc);
2171	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2172	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2173	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2174	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2175	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2176
2177	/*
2178	* Update the default CPUID leaf if necessary.
2179	*/
2180	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2181	{
2182	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2183	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2184	{
2185	/* We don't use CPUID(0).eax here because of the NT hack that only
2186	changes that value without actually removing any leaves. */
2187	uint32_t i = 0;
2188	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2189	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2190	{
2191	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2192	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2193	i++;
2194	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2195	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2196	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2197	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2198	}
2199	break;
2200	}
2201	default:
2202	break;
2203	}
2204
2205	/*
2206	* Explode the guest CPU features.
2207	*/
2208	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
2209	AssertLogRelRCReturn(rc, rc);
2210
2211	/*
2212	* Adjust the scalable bus frequency according to the CPUID information
2213	* we're now using.
2214	*/
2215	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2216	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2217	? UINT64_C(100000000) /* 100MHz */
2218	: UINT64_C(133333333); /* 133MHz */
2219
2220	/*
2221	* Populate the legacy arrays. Currently used for everything, later only
2222	* for patch manager.
2223	*/
2224	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2225	{
2226	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2227	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2228	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2229	};
2230	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2231	{
2232	uint32_t cLeft = aOldRanges[i].cCpuIds;
2233	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2234	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2235	while (cLeft-- > 0)
2236	{
2237	uLeaf--;
2238	pLegacyLeaf--;
2239
2240	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2241	if (pLeaf)
2242	{
2243	pLegacyLeaf->uEax = pLeaf->uEax;
2244	pLegacyLeaf->uEbx = pLeaf->uEbx;
2245	pLegacyLeaf->uEcx = pLeaf->uEcx;
2246	pLegacyLeaf->uEdx = pLeaf->uEdx;
2247	}
2248	else
2249	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2250	}
2251	}
2252
2253	/*
2254	* Configure XSAVE offsets according to the CPUID info.
2255	*/
2256	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2257	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2258	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2259	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2260	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2261	{
2262	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2263	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2264	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2265	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2266	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2267	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2268	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2269	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2270	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2271	pCpum->GuestFeatures.cbMaxExtendedState),
2272	VERR_CPUM_IPE_1);
2273	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2274	}
2275	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2276
2277	/* Copy the CPU #0 data to the other CPUs. */
2278	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2279	{
2280	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2281	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2282	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2283	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2284	}
2285
2286	return VINF_SUCCESS;
2287	}
2288
2289
2290	/** @name Instruction Set Extension Options
2291	* @{ */
2292	/** Configuration option type (extended boolean, really). */
2293	typedef uint8_t CPUMISAEXTCFG;
2294	/** Always disable the extension. */
2295	#define CPUMISAEXTCFG_DISABLED false
2296	/** Enable the extension if it's supported by the host CPU. */
2297	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2298	/** Enable the extension if it's supported by the host CPU, but don't let
2299	* the portable CPUID feature disable it. */
2300	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2301	/** Always enable the extension. */
2302	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2303	/** @} */
2304
2305	/**
2306	* CPUID Configuration (from CFGM).
2307	*
2308	* @remarks The members aren't document since we would only be duplicating the
2309	* \@cfgm entries in cpumR3CpuIdReadConfig.
2310	*/
2311	typedef struct CPUMCPUIDCONFIG
2312	{
2313	bool fNt4LeafLimit;
2314	bool fInvariantTsc;
2315	bool fForceVme;
2316
2317	CPUMISAEXTCFG enmCmpXchg16b;
2318	CPUMISAEXTCFG enmMonitor;
2319	CPUMISAEXTCFG enmMWaitExtensions;
2320	CPUMISAEXTCFG enmSse41;
2321	CPUMISAEXTCFG enmSse42;
2322	CPUMISAEXTCFG enmAvx;
2323	CPUMISAEXTCFG enmAvx2;
2324	CPUMISAEXTCFG enmXSave;
2325	CPUMISAEXTCFG enmAesNi;
2326	CPUMISAEXTCFG enmPClMul;
2327	CPUMISAEXTCFG enmPopCnt;
2328	CPUMISAEXTCFG enmMovBe;
2329	CPUMISAEXTCFG enmRdRand;
2330	CPUMISAEXTCFG enmRdSeed;
2331	CPUMISAEXTCFG enmCLFlushOpt;
2332
2333	CPUMISAEXTCFG enmAbm;
2334	CPUMISAEXTCFG enmSse4A;
2335	CPUMISAEXTCFG enmMisAlnSse;
2336	CPUMISAEXTCFG enm3dNowPrf;
2337	CPUMISAEXTCFG enmAmdExtMmx;
2338	CPUMISAEXTCFG enmSvm;
2339
2340	uint32_t uMaxStdLeaf;
2341	uint32_t uMaxExtLeaf;
2342	uint32_t uMaxCentaurLeaf;
2343	uint32_t uMaxIntelFamilyModelStep;
2344	char szCpuName[128];
2345	} CPUMCPUIDCONFIG;
2346	/** Pointer to CPUID config (from CFGM). */
2347	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2348
2349
2350	/**
2351	* Mini CPU selection support for making Mac OS X happy.
2352	*
2353	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2354	*
2355	* @param pCpum The CPUM instance data.
2356	* @param pConfig The CPUID configuration we've read from CFGM.
2357	*/
2358	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2359	{
2360	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2361	{
2362	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2363	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2364	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2365	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2366	0);
2367	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2368	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2369	{
2370	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2371	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2372	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2373	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2374	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2375	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2376	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2377	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2378	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2379	pStdFeatureLeaf->uEax = uNew;
2380	}
2381	}
2382	}
2383
2384
2385
2386	/**
2387	* Limit it the number of entries, zapping the remainder.
2388	*
2389	* The limits are masking off stuff about power saving and similar, this
2390	* is perhaps a bit crudely done as there is probably some relatively harmless
2391	* info too in these leaves (like words about having a constant TSC).
2392	*
2393	* @param pCpum The CPUM instance data.
2394	* @param pConfig The CPUID configuration we've read from CFGM.
2395	*/
2396	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2397	{
2398	/*
2399	* Standard leaves.
2400	*/
2401	uint32_t uSubLeaf = 0;
2402	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2403	if (pCurLeaf)
2404	{
2405	uint32_t uLimit = pCurLeaf->uEax;
2406	if (uLimit <= UINT32_C(0x000fffff))
2407	{
2408	if (uLimit > pConfig->uMaxStdLeaf)
2409	{
2410	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2411	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2412	uLimit + 1, UINT32_C(0x000fffff));
2413	}
2414
2415	/* NT4 hack, no zapping of extra leaves here. */
2416	if (pConfig->fNt4LeafLimit && uLimit > 3)
2417	pCurLeaf->uEax = uLimit = 3;
2418
2419	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2420	pCurLeaf->uEax = uLimit;
2421	}
2422	else
2423	{
2424	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2425	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2426	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2427	}
2428	}
2429
2430	/*
2431	* Extended leaves.
2432	*/
2433	uSubLeaf = 0;
2434	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2435	if (pCurLeaf)
2436	{
2437	uint32_t uLimit = pCurLeaf->uEax;
2438	if ( uLimit >= UINT32_C(0x80000000)
2439	&& uLimit <= UINT32_C(0x800fffff))
2440	{
2441	if (uLimit > pConfig->uMaxExtLeaf)
2442	{
2443	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2444	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2445	uLimit + 1, UINT32_C(0x800fffff));
2446	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2447	pCurLeaf->uEax = uLimit;
2448	}
2449	}
2450	else
2451	{
2452	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2453	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2454	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2455	}
2456	}
2457
2458	/*
2459	* Centaur leaves (VIA).
2460	*/
2461	uSubLeaf = 0;
2462	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2463	if (pCurLeaf)
2464	{
2465	uint32_t uLimit = pCurLeaf->uEax;
2466	if ( uLimit >= UINT32_C(0xc0000000)
2467	&& uLimit <= UINT32_C(0xc00fffff))
2468	{
2469	if (uLimit > pConfig->uMaxCentaurLeaf)
2470	{
2471	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2472	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2473	uLimit + 1, UINT32_C(0xcfffffff));
2474	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2475	pCurLeaf->uEax = uLimit;
2476	}
2477	}
2478	else
2479	{
2480	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2481	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2482	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2483	}
2484	}
2485	}
2486
2487
2488	/**
2489	* Clears a CPUID leaf and all sub-leaves (to zero).
2490	*
2491	* @param pCpum The CPUM instance data.
2492	* @param uLeaf The leaf to clear.
2493	*/
2494	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2495	{
2496	uint32_t uSubLeaf = 0;
2497	PCPUMCPUIDLEAF pCurLeaf;
2498	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2499	{
2500	pCurLeaf->uEax = 0;
2501	pCurLeaf->uEbx = 0;
2502	pCurLeaf->uEcx = 0;
2503	pCurLeaf->uEdx = 0;
2504	uSubLeaf++;
2505	}
2506	}
2507
2508
2509	/**
2510	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2511	* the given leaf.
2512	*
2513	* @returns pLeaf.
2514	* @param pCpum The CPUM instance data.
2515	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2516	*/
2517	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2518	{
2519	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2520	if (pLeaf->fSubLeafMask != 0)
2521	{
2522	/*
2523	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2524	* Log everything while we're at it.
2525	*/
2526	LogRel(("CPUM:\n"
2527	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2528	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2529	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2530	for (;;)
2531	{
2532	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2533	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2534	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2535	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2536	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2537	break;
2538	pSubLeaf++;
2539	}
2540	LogRel(("CPUM:\n"));
2541
2542	/*
2543	* Remove the offending sub-leaves.
2544	*/
2545	if (pSubLeaf != pLeaf)
2546	{
2547	if (pSubLeaf != pLast)
2548	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2549	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2550	}
2551
2552	/*
2553	* Convert the first sub-leaf into a single leaf.
2554	*/
2555	pLeaf->uSubLeaf = 0;
2556	pLeaf->fSubLeafMask = 0;
2557	}
2558	return pLeaf;
2559	}
2560
2561
2562	/**
2563	* Sanitizes and adjust the CPUID leaves.
2564	*
2565	* Drop features that aren't virtualized (or virtualizable). Adjust information
2566	* and capabilities to fit the virtualized hardware. Remove information the
2567	* guest shouldn't have (because it's wrong in the virtual world or because it
2568	* gives away host details) or that we don't have documentation for and no idea
2569	* what means.
2570	*
2571	* @returns VBox status code.
2572	* @param pVM The cross context VM structure (for cCpus).
2573	* @param pCpum The CPUM instance data.
2574	* @param pConfig The CPUID configuration we've read from CFGM.
2575	*/
2576	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2577	{
2578	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2579	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2580	{ \
2581	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2582	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2583	}
2584	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2585	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2586	{ \
2587	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2588	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2589	}
2590	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2591	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2592	&& ((a_pLeafReg) & (fBitMask)) \
2593	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2594	{ \
2595	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2596	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2597	}
2598	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2599
2600	/* Cpuid 1:
2601	* EAX: CPU model, family and stepping.
2602	*
2603	* ECX + EDX: Supported features. Only report features we can support.
2604	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2605	* options may require adjusting (i.e. stripping what was enabled).
2606	*
2607	* EBX: Branding, CLFLUSH line size, logical processors per package and
2608	* initial APIC ID.
2609	*/
2610	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2611	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2612	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2613
2614	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2615	\| X86_CPUID_FEATURE_EDX_VME
2616	\| X86_CPUID_FEATURE_EDX_DE
2617	\| X86_CPUID_FEATURE_EDX_PSE
2618	\| X86_CPUID_FEATURE_EDX_TSC
2619	\| X86_CPUID_FEATURE_EDX_MSR
2620	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2621	\| X86_CPUID_FEATURE_EDX_MCE
2622	\| X86_CPUID_FEATURE_EDX_CX8
2623	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2624	//\| RT_BIT_32(10) - not defined
2625	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2626	//\| X86_CPUID_FEATURE_EDX_SEP
2627	\| X86_CPUID_FEATURE_EDX_MTRR
2628	\| X86_CPUID_FEATURE_EDX_PGE
2629	\| X86_CPUID_FEATURE_EDX_MCA
2630	\| X86_CPUID_FEATURE_EDX_CMOV
2631	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2632	\| X86_CPUID_FEATURE_EDX_PSE36
2633	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2634	\| X86_CPUID_FEATURE_EDX_CLFSH
2635	//\| RT_BIT_32(20) - not defined
2636	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2637	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2638	\| X86_CPUID_FEATURE_EDX_MMX
2639	\| X86_CPUID_FEATURE_EDX_FXSR
2640	\| X86_CPUID_FEATURE_EDX_SSE
2641	\| X86_CPUID_FEATURE_EDX_SSE2
2642	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2643	\| X86_CPUID_FEATURE_EDX_HTT
2644	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2645	//\| RT_BIT_32(30) - not defined
2646	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2647	;
2648	pStdFeatureLeaf->uEcx &= 0
2649	\| X86_CPUID_FEATURE_ECX_SSE3
2650	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2651	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2652	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2653	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2654	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2655	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized yet.
2656	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2657	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2658	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2659	\| X86_CPUID_FEATURE_ECX_SSSE3
2660	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2661	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2662	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2663	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2664	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2665	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2666	//\| X86_CPUID_FEATURE_ECX_PCID - not implemented yet.
2667	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2668	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2669	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2670	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2671	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2672	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2673	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2674	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2675	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2676	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2677	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2678	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2679	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2680	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2681	;
2682
2683	if (pCpum->u8PortableCpuIdLevel > 0)
2684	{
2685	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2686	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2687	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2688	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2689	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2690	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2691	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2692	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2693	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2694	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2695	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2696	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2697	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2698	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2699	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2700	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2701	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2702	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2703
2704	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2705	\| X86_CPUID_FEATURE_EDX_PSN
2706	\| X86_CPUID_FEATURE_EDX_DS
2707	\| X86_CPUID_FEATURE_EDX_ACPI
2708	\| X86_CPUID_FEATURE_EDX_SS
2709	\| X86_CPUID_FEATURE_EDX_TM
2710	\| X86_CPUID_FEATURE_EDX_PBE
2711	)));
2712	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2713	\| X86_CPUID_FEATURE_ECX_CPLDS
2714	\| X86_CPUID_FEATURE_ECX_VMX
2715	\| X86_CPUID_FEATURE_ECX_SMX
2716	\| X86_CPUID_FEATURE_ECX_EST
2717	\| X86_CPUID_FEATURE_ECX_TM2
2718	\| X86_CPUID_FEATURE_ECX_CNTXID
2719	\| X86_CPUID_FEATURE_ECX_FMA
2720	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2721	\| X86_CPUID_FEATURE_ECX_PDCM
2722	\| X86_CPUID_FEATURE_ECX_DCA
2723	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2724	)));
2725	}
2726
2727	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2728	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2729
2730	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2731	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2732	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2733	*/
2734	#ifdef VBOX_WITH_MULTI_CORE
2735	if (pVM->cCpus > 1)
2736	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2737	#endif
2738	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2739	{
2740	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2741	core times the number of CPU cores per processor */
2742	#ifdef VBOX_WITH_MULTI_CORE
2743	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2744	#else
2745	/* Single logical processor in a package. */
2746	pStdFeatureLeaf->uEbx \|= (1 << 16);
2747	#endif
2748	}
2749
2750	uint32_t uMicrocodeRev;
2751	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2752	if (RT_SUCCESS(rc))
2753	{
2754	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2755	}
2756	else
2757	{
2758	uMicrocodeRev = 0;
2759	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2760	}
2761
2762	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2763	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2764	*/
2765	if ( (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen)
2766	&& uMicrocodeRev < 0x8001126
2767	&& !pConfig->fForceVme)
2768	{
2769	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2770	LogRel(("CPUM: Zen VME workaround engaged\n"));
2771	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2772	}
2773
2774	/* Force standard feature bits. */
2775	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2776	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2777	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2778	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2779	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2780	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2781	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2782	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2783	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2784	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2785	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2786	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2787	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2788	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2789	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2790	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2791	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2792	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2793	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2794	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2795	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2796	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2797
2798	pStdFeatureLeaf = NULL; /* Must refetch! */
2799
2800	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2801	* AMD:
2802	* EAX: CPU model, family and stepping.
2803	*
2804	* ECX + EDX: Supported features. Only report features we can support.
2805	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2806	* options may require adjusting (i.e. stripping what was enabled).
2807	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2808	*
2809	* EBX: Branding ID and package type (or reserved).
2810	*
2811	* Intel and probably most others:
2812	* EAX: 0
2813	* EBX: 0
2814	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2815	*/
2816	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2817	if (pExtFeatureLeaf)
2818	{
2819	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2820
2821	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2822	\| X86_CPUID_AMD_FEATURE_EDX_VME
2823	\| X86_CPUID_AMD_FEATURE_EDX_DE
2824	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2825	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2826	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2827	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2828	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2829	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2830	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2831	//\| RT_BIT_32(10) - reserved
2832	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2833	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2834	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2835	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2836	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2837	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2838	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2839	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2840	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2841	//\| RT_BIT_32(18) - reserved
2842	//\| RT_BIT_32(19) - reserved
2843	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2844	//\| RT_BIT_32(21) - reserved
2845	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2846	\| X86_CPUID_AMD_FEATURE_EDX_MMX
2847	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
2848	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
2849	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2850	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2851	//\| RT_BIT_32(28) - reserved
2852	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2853	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2854	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
2855	;
2856	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2857	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2858	\| (pConfig->enmSvm ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
2859	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2860	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
2861	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2862	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2863	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2864	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2865	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2866	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2867	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
2868	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
2869	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2870	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
2871	//\| RT_BIT_32(14) - reserved
2872	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2873	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2874	//\| RT_BIT_32(17) - reserved
2875	//\| RT_BIT_32(18) - reserved
2876	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2877	//\| RT_BIT_32(20) - reserved
2878	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2879	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2880	//\| RT_BIT_32(23) - reserved
2881	//\| RT_BIT_32(24) - reserved
2882	//\| RT_BIT_32(25) - reserved
2883	//\| RT_BIT_32(26) - reserved
2884	//\| RT_BIT_32(27) - reserved
2885	//\| RT_BIT_32(28) - reserved
2886	//\| RT_BIT_32(29) - reserved
2887	//\| RT_BIT_32(30) - reserved
2888	//\| RT_BIT_32(31) - reserved
2889	;
2890	#ifdef VBOX_WITH_MULTI_CORE
2891	if ( pVM->cCpus > 1
2892	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2893	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2894	#endif
2895
2896	if (pCpum->u8PortableCpuIdLevel > 0)
2897	{
2898	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2899	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM, pConfig->enmSvm);
2900	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2901	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2902	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2903	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2904	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2905	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2906	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2907	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2908	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2909	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2910	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2911	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2912	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2913	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2914
2915	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2916	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2917	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2918	\| X86_CPUID_AMD_FEATURE_ECX_IBS
2919	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2920	\| X86_CPUID_AMD_FEATURE_ECX_WDT
2921	\| X86_CPUID_AMD_FEATURE_ECX_LWP
2922	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
2923	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2924	\| UINT32_C(0xff964000)
2925	)));
2926	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2927	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2928	\| RT_BIT(18)
2929	\| RT_BIT(19)
2930	\| RT_BIT(21)
2931	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2932	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2933	\| RT_BIT(28)
2934	)));
2935	}
2936
2937	/* Force extended feature bits. */
2938	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2939	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
2940	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2941	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2942	if (pConfig->enmSvm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2943	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SVM;
2944	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2945	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2946	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2947	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2948	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2949	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2950	if (pConfig->enmSvm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2951	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SVM;
2952	}
2953	pExtFeatureLeaf = NULL; /* Must refetch! */
2954
2955
2956	/* Cpuid 2:
2957	* Intel: (Nondeterministic) Cache and TLB information
2958	* AMD: Reserved
2959	* VIA: Reserved
2960	* Safe to expose.
2961	*/
2962	uint32_t uSubLeaf = 0;
2963	PCPUMCPUIDLEAF pCurLeaf;
2964	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2965	{
2966	if ((pCurLeaf->uEax & 0xff) > 1)
2967	{
2968	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2969	pCurLeaf->uEax &= UINT32_C(0xffffff01);
2970	}
2971	uSubLeaf++;
2972	}
2973
2974	/* Cpuid 3:
2975	* Intel: EAX, EBX - reserved (transmeta uses these)
2976	* ECX, EDX - Processor Serial Number if available, otherwise reserved
2977	* AMD: Reserved
2978	* VIA: Reserved
2979	* Safe to expose
2980	*/
2981	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2982	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
2983	{
2984	uSubLeaf = 0;
2985	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
2986	{
2987	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
2988	if (pCpum->u8PortableCpuIdLevel > 0)
2989	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
2990	uSubLeaf++;
2991	}
2992	}
2993
2994	/* Cpuid 4 + ECX:
2995	* Intel: Deterministic Cache Parameters Leaf.
2996	* AMD: Reserved
2997	* VIA: Reserved
2998	* Safe to expose, except for EAX:
2999	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3000	* Bits 31-26: Maximum number of processor cores in this physical package**
3001	* Note: These SMP values are constant regardless of ECX
3002	*/
3003	uSubLeaf = 0;
3004	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3005	{
3006	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3007	#ifdef VBOX_WITH_MULTI_CORE
3008	if ( pVM->cCpus > 1
3009	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3010	{
3011	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3012	/* One logical processor with possibly multiple cores. */
3013	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3014	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3015	}
3016	#endif
3017	uSubLeaf++;
3018	}
3019
3020	/* Cpuid 5: Monitor/mwait Leaf
3021	* Intel: ECX, EDX - reserved
3022	* EAX, EBX - Smallest and largest monitor line size
3023	* AMD: EDX - reserved
3024	* EAX, EBX - Smallest and largest monitor line size
3025	* ECX - extensions (ignored for now)
3026	* VIA: Reserved
3027	* Safe to expose
3028	*/
3029	uSubLeaf = 0;
3030	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3031	{
3032	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3033	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3034	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3035
3036	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3037	if (pConfig->enmMWaitExtensions)
3038	{
3039	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3040	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3041	it shall be part of our power management virtualization model */
3042	#if 0
3043	/* MWAIT sub C-states */
3044	pCurLeaf->uEdx =
3045	(0 << 0) /* 0 in C0 */ \|
3046	(2 << 4) /* 2 in C1 */ \|
3047	(2 << 8) /* 2 in C2 */ \|
3048	(2 << 12) /* 2 in C3 */ \|
3049	(0 << 16) /* 0 in C4 */
3050	;
3051	#endif
3052	}
3053	else
3054	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3055	uSubLeaf++;
3056	}
3057
3058	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3059	* Intel: Various stuff.
3060	* AMD: EAX, EBX, EDX - reserved.
3061	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3062	* present. Same as intel.
3063	* VIA: ??
3064	*
3065	* We clear everything here for now.
3066	*/
3067	cpumR3CpuIdZeroLeaf(pCpum, 6);
3068
3069	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3070	* EAX: Number of sub leaves.
3071	* EBX+ECX+EDX: Feature flags
3072	*
3073	* We only have documentation for one sub-leaf, so clear all other (no need
3074	* to remove them as such, just set them to zero).
3075	*
3076	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3077	* options may require adjusting (i.e. stripping what was enabled).
3078	*/
3079	uSubLeaf = 0;
3080	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3081	{
3082	switch (uSubLeaf)
3083	{
3084	case 0:
3085	{
3086	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3087	pCurLeaf->uEbx &= 0
3088	//\| X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
3089	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3090	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3091	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3092	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3093	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3094	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3095	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3096	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3097	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3098	//\| X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
3099	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3100	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3101	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3102	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3103	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3104	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3105	//\| RT_BIT(17) - reserved
3106	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3107	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3108	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3109	//\| RT_BIT(21) - reserved
3110	//\| RT_BIT(22) - reserved
3111	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3112	//\| RT_BIT(24) - reserved
3113	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3114	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3115	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3116	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3117	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3118	//\| RT_BIT(30) - reserved
3119	//\| RT_BIT(31) - reserved
3120	;
3121	pCurLeaf->uEcx &= 0
3122	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3123	;
3124	pCurLeaf->uEdx &= 0;
3125
3126	if (pCpum->u8PortableCpuIdLevel > 0)
3127	{
3128	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
3129	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3130	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3131	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3132	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3133	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
3134	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3135	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3136	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3137	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3138	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3139	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3140	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3141	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3142	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3143	}
3144
3145	/* Force standard feature bits. */
3146	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3147	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3148	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3149	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3150	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3151	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3152	break;
3153	}
3154
3155	default:
3156	/* Invalid index, all values are zero. */
3157	pCurLeaf->uEax = 0;
3158	pCurLeaf->uEbx = 0;
3159	pCurLeaf->uEcx = 0;
3160	pCurLeaf->uEdx = 0;
3161	break;
3162	}
3163	uSubLeaf++;
3164	}
3165
3166	/* Cpuid 8: Marked as reserved by Intel and AMD.
3167	* We zero this since we don't know what it may have been used for.
3168	*/
3169	cpumR3CpuIdZeroLeaf(pCpum, 8);
3170
3171	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3172	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3173	* EBX, ECX, EDX - reserved.
3174	* AMD: Reserved
3175	* VIA: ??
3176	*
3177	* We zero this.
3178	*/
3179	cpumR3CpuIdZeroLeaf(pCpum, 9);
3180
3181	/* Cpuid 0xa: Architectural Performance Monitor Features
3182	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3183	* EBX, ECX, EDX - reserved.
3184	* AMD: Reserved
3185	* VIA: ??
3186	*
3187	* We zero this, for now at least.
3188	*/
3189	cpumR3CpuIdZeroLeaf(pCpum, 10);
3190
3191	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3192	* Intel: EAX - APCI ID shift right for next level.
3193	* EBX - Factory configured cores/threads at this level.
3194	* ECX - Level number (same as input) and level type (1,2,0).
3195	* EDX - Extended initial APIC ID.
3196	* AMD: Reserved
3197	* VIA: ??
3198	*/
3199	uSubLeaf = 0;
3200	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3201	{
3202	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3203	{
3204	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3205	if (bLevelType == 1)
3206	{
3207	/* Thread level - we don't do threads at the moment. */
3208	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3209	pCurLeaf->uEbx = 1;
3210	}
3211	else if (bLevelType == 2)
3212	{
3213	/* Core level. */
3214	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3215	#ifdef VBOX_WITH_MULTI_CORE
3216	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3217	pCurLeaf->uEax++;
3218	#endif
3219	pCurLeaf->uEbx = pVM->cCpus;
3220	}
3221	else
3222	{
3223	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3224	pCurLeaf->uEax = 0;
3225	pCurLeaf->uEbx = 0;
3226	pCurLeaf->uEcx = 0;
3227	}
3228	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3229	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3230	}
3231	else
3232	{
3233	pCurLeaf->uEax = 0;
3234	pCurLeaf->uEbx = 0;
3235	pCurLeaf->uEcx = 0;
3236	pCurLeaf->uEdx = 0;
3237	}
3238	uSubLeaf++;
3239	}
3240
3241	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3242	* We zero this since we don't know what it may have been used for.
3243	*/
3244	cpumR3CpuIdZeroLeaf(pCpum, 12);
3245
3246	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3247	* ECX=0: EAX - Valid bits in XCR0[31:0].
3248	* EBX - Maximum state size as per current XCR0 value.
3249	* ECX - Maximum state size for all supported features.
3250	* EDX - Valid bits in XCR0[63:32].
3251	* ECX=1: EAX - Various X-features.
3252	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3253	* ECX - Valid bits in IA32_XSS[31:0].
3254	* EDX - Valid bits in IA32_XSS[63:32].
3255	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3256	* if the bit invalid all four registers are set to zero.
3257	* EAX - The state size for this feature.
3258	* EBX - The state byte offset of this feature.
3259	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3260	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3261	*
3262	* Clear them all as we don't currently implement extended CPU state.
3263	*/
3264	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3265	uint64_t fGuestXcr0Mask = 0;
3266	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3267	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3268	{
3269	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3270	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3271	fGuestXcr0Mask \|= XSAVE_C_YMM;
3272	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3273	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3274	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3275	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3276
3277	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3278	}
3279	pStdFeatureLeaf = NULL;
3280	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3281
3282	/* Work the sub-leaves. */
3283	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3284	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3285	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3286	{
3287	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3288	if (pCurLeaf)
3289	{
3290	if (fGuestXcr0Mask)
3291	{
3292	switch (uSubLeaf)
3293	{
3294	case 0:
3295	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3296	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3297	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3298	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3299	VERR_CPUM_IPE_1);
3300	cbXSaveMaxActual = pCurLeaf->uEcx;
3301	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3302	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3303	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3304	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3305	VERR_CPUM_IPE_2);
3306	continue;
3307	case 1:
3308	pCurLeaf->uEax &= 0;
3309	pCurLeaf->uEcx &= 0;
3310	pCurLeaf->uEdx &= 0;
3311	/** @todo what about checking ebx? */
3312	continue;
3313	default:
3314	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3315	{
3316	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3317	&& pCurLeaf->uEax > 0
3318	&& pCurLeaf->uEbx < cbXSaveMaxActual
3319	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3320	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3321	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3322	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3323	VERR_CPUM_IPE_2);
3324	AssertLogRel(!(pCurLeaf->uEcx & 1));
3325	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3326	pCurLeaf->uEdx = 0; /* it's reserved... */
3327	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3328	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3329	continue;
3330	}
3331	break;
3332	}
3333	}
3334
3335	/* Clear the leaf. */
3336	pCurLeaf->uEax = 0;
3337	pCurLeaf->uEbx = 0;
3338	pCurLeaf->uEcx = 0;
3339	pCurLeaf->uEdx = 0;
3340	}
3341	}
3342
3343	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3344	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3345	{
3346	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3347	if (pCurLeaf)
3348	{
3349	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3350	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3351	pCurLeaf->uEbx = cbXSaveMaxReport;
3352	pCurLeaf->uEcx = cbXSaveMaxReport;
3353	}
3354	}
3355
3356	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3357	* We zero this since we don't know what it may have been used for.
3358	*/
3359	cpumR3CpuIdZeroLeaf(pCpum, 14);
3360
3361	/* Cpuid 0xf + ECX: Platform qualifity of service monitoring (PQM).
3362	* We zero this as we don't currently virtualize PQM.
3363	*/
3364	cpumR3CpuIdZeroLeaf(pCpum, 15);
3365
3366	/* Cpuid 0x10 + ECX: Platform qualifity of service enforcement (PQE).
3367	* We zero this as we don't currently virtualize PQE.
3368	*/
3369	cpumR3CpuIdZeroLeaf(pCpum, 16);
3370
3371	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3372	* We zero this since we don't know what it may have been used for.
3373	*/
3374	cpumR3CpuIdZeroLeaf(pCpum, 17);
3375
3376	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3377	* We zero this as we don't currently virtualize this.
3378	*/
3379	cpumR3CpuIdZeroLeaf(pCpum, 18);
3380
3381	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3382	* We zero this since we don't know what it may have been used for.
3383	*/
3384	cpumR3CpuIdZeroLeaf(pCpum, 19);
3385
3386	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3387	* We zero this as we don't currently virtualize this.
3388	*/
3389	cpumR3CpuIdZeroLeaf(pCpum, 20);
3390
3391	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3392	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3393	* EAX - denominator (unsigned).
3394	* EBX - numerator (unsigned).
3395	* ECX, EDX - reserved.
3396	* AMD: Reserved / undefined / not implemented.
3397	* VIA: Reserved / undefined / not implemented.
3398	* We zero this as we don't currently virtualize this.
3399	*/
3400	cpumR3CpuIdZeroLeaf(pCpum, 21);
3401
3402	/* Cpuid 0x16: Processor frequency info
3403	* Intel: EAX - Core base frequency in MHz.
3404	* EBX - Core maximum frequency in MHz.
3405	* ECX - Bus (reference) frequency in MHz.
3406	* EDX - Reserved.
3407	* AMD: Reserved / undefined / not implemented.
3408	* VIA: Reserved / undefined / not implemented.
3409	* We zero this as we don't currently virtualize this.
3410	*/
3411	cpumR3CpuIdZeroLeaf(pCpum, 22);
3412
3413	/* Cpuid 0x17..0x10000000: Unknown.
3414	* We don't know these and what they mean, so remove them. */
3415	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3416	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3417
3418
3419	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3420	* We remove all these as we're a hypervisor and must provide our own.
3421	*/
3422	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3423	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3424
3425
3426	/* Cpuid 0x80000000 is harmless. */
3427
3428	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3429
3430	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3431
3432	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3433	* Safe to pass on to the guest.
3434	*
3435	* AMD: 0x800000005 L1 cache information
3436	* 0x800000006 L2/L3 cache information
3437	* Intel: 0x800000005 reserved
3438	* 0x800000006 L2 cache information
3439	* VIA: 0x800000005 TLB and L1 cache information
3440	* 0x800000006 L2 cache information
3441	*/
3442
3443	/* Cpuid 0x800000007: Advanced Power Management Information.
3444	* AMD: EAX: Processor feedback capabilities.
3445	* EBX: RAS capabilites.
3446	* ECX: Advanced power monitoring interface.
3447	* EDX: Enhanced power management capabilities.
3448	* Intel: EAX, EBX, ECX - reserved.
3449	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3450	* VIA: Reserved
3451	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3452	*/
3453	uSubLeaf = 0;
3454	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3455	{
3456	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3457	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3458	{
3459	pCurLeaf->uEdx &= 0
3460	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3461	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3462	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3463	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3464	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3465	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3466	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3467	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3468	#if 0 /*
3469	* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
3470	* Linux kernels blindly assume that the AMD performance counters work
3471	* if this is set for 64 bits guests. (Can't really find a CPUID feature
3472	* bit for them though.)
3473	*/
3474	/** @todo need to recheck this with new MSR emulation. */
3475	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3476	#endif
3477	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3478	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3479	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3480	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3481	\| 0;
3482	}
3483	else
3484	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3485	if (pConfig->fInvariantTsc)
3486	pCurLeaf->uEdx \|= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3487	uSubLeaf++;
3488	}
3489
3490	/* Cpuid 0x80000008:
3491	* AMD: EBX, EDX - reserved
3492	* EAX: Virtual/Physical/Guest address Size
3493	* ECX: Number of cores + APICIdCoreIdSize
3494	* Intel: EAX: Virtual/Physical address Size
3495	* EBX, ECX, EDX - reserved
3496	* VIA: EAX: Virtual/Physical address Size
3497	* EBX, ECX, EDX - reserved
3498	*
3499	* We only expose the virtual+pysical address size to the guest atm.
3500	* On AMD we set the core count, but not the apic id stuff as we're
3501	* currently not doing the apic id assignments in a complatible manner.
3502	*/
3503	uSubLeaf = 0;
3504	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3505	{
3506	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3507	pCurLeaf->uEbx = 0; /* reserved */
3508	pCurLeaf->uEdx = 0; /* reserved */
3509
3510	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3511	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3512	pCurLeaf->uEcx = 0;
3513	#ifdef VBOX_WITH_MULTI_CORE
3514	if ( pVM->cCpus > 1
3515	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3516	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3517	#endif
3518	uSubLeaf++;
3519	}
3520
3521	/* Cpuid 0x80000009: Reserved
3522	* We zero this since we don't know what it may have been used for.
3523	*/
3524	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3525
3526	/* Cpuid 0x8000000a: SVM Information
3527	* AMD: EAX - SVM revision.
3528	* EBX - Number of ASIDs.
3529	* ECX - Reserved.
3530	* EDX - SVM Feature identification.
3531	*/
3532	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3533	if (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
3534	{
3535	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3536	pSvmFeatureLeaf->uEax = 0x1;
3537	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3538	pSvmFeatureLeaf->uEcx = 0;
3539	pSvmFeatureLeaf->uEdx = 0; /** @todo Support SVM features */
3540	}
3541	else
3542	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3543
3544	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3545	* We clear these as we don't know what purpose they might have. */
3546	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3547	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3548
3549	/* Cpuid 0x80000019: TLB configuration
3550	* Seems to be harmless, pass them thru as is. */
3551
3552	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3553	* Strip anything we don't know what is or addresses feature we don't implement. */
3554	uSubLeaf = 0;
3555	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3556	{
3557	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3558	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3559	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3560	;
3561	pCurLeaf->uEbx = 0; /* reserved */
3562	pCurLeaf->uEcx = 0; /* reserved */
3563	pCurLeaf->uEdx = 0; /* reserved */
3564	uSubLeaf++;
3565	}
3566
3567	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3568	* Clear this as we don't currently virtualize this feature. */
3569	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3570
3571	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3572	* Clear this as we don't currently virtualize this feature. */
3573	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3574
3575	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3576	* We need to sanitize the cores per cache (EAX[25:14]).
3577	*
3578	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3579	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3580	* slightly different meaning.
3581	*/
3582	uSubLeaf = 0;
3583	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3584	{
3585	#ifdef VBOX_WITH_MULTI_CORE
3586	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3587	if (cCores > pVM->cCpus)
3588	cCores = pVM->cCpus;
3589	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3590	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3591	#else
3592	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3593	#endif
3594	uSubLeaf++;
3595	}
3596
3597	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3598	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3599	* setup, we have one compute unit with all the cores in it. Single node.
3600	*/
3601	uSubLeaf = 0;
3602	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3603	{
3604	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3605	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3606	{
3607	#ifdef VBOX_WITH_MULTI_CORE
3608	pCurLeaf->uEbx = pVM->cCpus < 0x100
3609	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3610	#else
3611	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3612	#endif
3613	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3614	}
3615	else
3616	{
3617	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3618	pCurLeaf->uEbx = 0; /* Reserved. */
3619	pCurLeaf->uEcx = 0; /* Reserved. */
3620	}
3621	pCurLeaf->uEdx = 0; /* Reserved. */
3622	uSubLeaf++;
3623	}
3624
3625	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3626	* We don't know these and what they mean, so remove them. */
3627	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3628	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3629
3630	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3631	* Just pass it thru for now. */
3632
3633	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3634	* Just pass it thru for now. */
3635
3636	/* Cpuid 0xc0000000: Centaur stuff.
3637	* Harmless, pass it thru. */
3638
3639	/* Cpuid 0xc0000001: Centaur features.
3640	* VIA: EAX - Family, model, stepping.
3641	* EDX - Centaur extended feature flags. Nothing interesting, except may
3642	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3643	* EBX, ECX - reserved.
3644	* We keep EAX but strips the rest.
3645	*/
3646	uSubLeaf = 0;
3647	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3648	{
3649	pCurLeaf->uEbx = 0;
3650	pCurLeaf->uEcx = 0;
3651	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3652	uSubLeaf++;
3653	}
3654
3655	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3656	* We only have fixed stale values, but should be harmless. */
3657
3658	/* Cpuid 0xc0000003: Reserved.
3659	* We zero this since we don't know what it may have been used for.
3660	*/
3661	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3662
3663	/* Cpuid 0xc0000004: Centaur Performance Info.
3664	* We only have fixed stale values, but should be harmless. */
3665
3666
3667	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3668	* We don't know these and what they mean, so remove them. */
3669	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3670	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3671
3672	return VINF_SUCCESS;
3673	#undef PORTABLE_DISABLE_FEATURE_BIT
3674	#undef PORTABLE_CLEAR_BITS_WHEN
3675	}
3676
3677
3678	/**
3679	* Reads a value in /CPUM/IsaExts/ node.
3680	*
3681	* @returns VBox status code (error message raised).
3682	* @param pVM The cross context VM structure. (For errors.)
3683	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3684	* @param pszValueName The value / extension name.
3685	* @param penmValue Where to return the choice.
3686	* @param enmDefault The default choice.
3687	*/
3688	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3689	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3690	{
3691	/*
3692	* Try integer encoding first.
3693	*/
3694	uint64_t uValue;
3695	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3696	if (RT_SUCCESS(rc))
3697	switch (uValue)
3698	{
3699	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3700	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3701	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3702	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3703	default:
3704	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3705	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3706	pszValueName, uValue);
3707	}
3708	/*
3709	* If missing, use default.
3710	*/
3711	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3712	*penmValue = enmDefault;
3713	else
3714	{
3715	if (rc == VERR_CFGM_NOT_INTEGER)
3716	{
3717	/*
3718	* Not an integer, try read it as a string.
3719	*/
3720	char szValue[32];
3721	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3722	if (RT_SUCCESS(rc))
3723	{
3724	RTStrToLower(szValue);
3725	size_t cchValue = strlen(szValue);
3726	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3727	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3728	*penmValue = CPUMISAEXTCFG_DISABLED;
3729	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3730	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3731	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3732	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3733	else if (EQ("portable"))
3734	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3735	else if (EQ("default") \|\| EQ("def"))
3736	*penmValue = enmDefault;
3737	else
3738	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3739	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3740	pszValueName, uValue);
3741	#undef EQ
3742	}
3743	}
3744	if (RT_FAILURE(rc))
3745	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3746	}
3747	return VINF_SUCCESS;
3748	}
3749
3750
3751	/**
3752	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3753	*
3754	* @returns VBox status code (error message raised).
3755	* @param pVM The cross context VM structure. (For errors.)
3756	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3757	* @param pszValueName The value / extension name.
3758	* @param penmValue Where to return the choice.
3759	* @param enmDefault The default choice.
3760	* @param fAllowed Allowed choice. Applied both to the result and to
3761	* the default value.
3762	*/
3763	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3764	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3765	{
3766	int rc;
3767	if (fAllowed)
3768	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3769	else
3770	{
3771	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3772	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3773	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3774	*penmValue = CPUMISAEXTCFG_DISABLED;
3775	}
3776	return rc;
3777	}
3778
3779
3780	/**
3781	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3782	*
3783	* @returns VBox status code (error message raised).
3784	* @param pVM The cross context VM structure. (For errors.)
3785	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3786	* @param pCpumCfg The /CPUM node (can be NULL).
3787	* @param pszValueName The value / extension name.
3788	* @param penmValue Where to return the choice.
3789	* @param enmDefault The default choice.
3790	*/
3791	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3792	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3793	{
3794	if (CFGMR3Exists(pCpumCfg, pszValueName))
3795	{
3796	if (!CFGMR3Exists(pIsaExts, pszValueName))
3797	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3798	else
3799	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3800	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3801	pszValueName, pszValueName);
3802
3803	bool fLegacy;
3804	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3805	if (RT_SUCCESS(rc))
3806	{
3807	*penmValue = fLegacy;
3808	return VINF_SUCCESS;
3809	}
3810	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3811	}
3812
3813	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3814	}
3815
3816
3817	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3818	{
3819	int rc;
3820
3821	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3822	* When non-zero CPUID features that could cause portability issues will be
3823	* stripped. The higher the value the more features gets stripped. Higher
3824	* values should only be used when older CPUs are involved since it may
3825	* harm performance and maybe also cause problems with specific guests. */
3826	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
3827	AssertLogRelRCReturn(rc, rc);
3828
3829	/** @cfgm{/CPUM/GuestCpuName, string}
3830	* The name of the CPU we're to emulate. The default is the host CPU.
3831	* Note! CPUs other than "host" one is currently unsupported. */
3832	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3833	AssertLogRelRCReturn(rc, rc);
3834
3835	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3836	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3837	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3838	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3839	*/
3840	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3841	AssertLogRelRCReturn(rc, rc);
3842
3843	/** @cfgm{/CPUM/InvariantTsc, boolean, complicated}
3844	* Set the invariant TSC flag in 0x80000007 if true, otherwas take default
3845	* action. By default the flag is passed thru as is from the host CPU, except
3846	* on AMD CPUs where it's suppressed to avoid trouble from linux assuming we
3847	* virtualize performance counters.
3848	*/
3849	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, false);
3850	AssertLogRelRCReturn(rc, rc);
3851
3852	/** @cfgm{/CPUM/ForceVme, boolean, false}
3853	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
3854	* By default the flag is passed thru as is from the host CPU, except
3855	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
3856	* guests and DOS boxes in general.
3857	*/
3858	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
3859	AssertLogRelRCReturn(rc, rc);
3860
3861	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3862	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
3863	* probably going to be a temporary hack, so don't depend on this.
3864	* The 1st byte of the value is the stepping, the 2nd byte value is the model
3865	* number and the 3rd byte value is the family, and the 4th value must be zero.
3866	*/
3867	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3868	AssertLogRelRCReturn(rc, rc);
3869
3870	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3871	* The last standard leaf to keep. The actual last value that is stored in EAX
3872	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3873	* removed. (This works independently of and differently from NT4LeafLimit.)
3874	* The default is usually set to what we're able to reasonably sanitize.
3875	*/
3876	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3877	AssertLogRelRCReturn(rc, rc);
3878
3879	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3880	* The last extended leaf to keep. The actual last value that is stored in EAX
3881	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3882	* leaf are removed. The default is set to what we're able to sanitize.
3883	*/
3884	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3885	AssertLogRelRCReturn(rc, rc);
3886
3887	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3888	* The last extended leaf to keep. The actual last value that is stored in EAX
3889	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3890	* leaf are removed. The default is set to what we're able to sanitize.
3891	*/
3892	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3893	AssertLogRelRCReturn(rc, rc);
3894
3895
3896	/*
3897	* Instruction Set Architecture (ISA) Extensions.
3898	*/
3899	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3900	if (pIsaExts)
3901	{
3902	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3903	"CMPXCHG16B"
3904	"\|MONITOR"
3905	"\|MWaitExtensions"
3906	"\|SSE4.1"
3907	"\|SSE4.2"
3908	"\|XSAVE"
3909	"\|AVX"
3910	"\|AVX2"
3911	"\|AESNI"
3912	"\|PCLMUL"
3913	"\|POPCNT"
3914	"\|MOVBE"
3915	"\|RDRAND"
3916	"\|RDSEED"
3917	"\|CLFLUSHOPT"
3918	"\|ABM"
3919	"\|SSE4A"
3920	"\|MISALNSSE"
3921	"\|3DNOWPRF"
3922	"\|AXMMX"
3923	"\|SVM"
3924	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
3925	if (RT_FAILURE(rc))
3926	return rc;
3927	}
3928
3929	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
3930	* Expose CMPXCHG16B to the guest if supported by the host. For the time
3931	* being the default is to only do this for VMs with nested paging and AMD-V or
3932	* unrestricted guest mode.
3933	*/
3934	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
3935	AssertLogRelRCReturn(rc, rc);
3936
3937	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
3938	* Expose MONITOR/MWAIT instructions to the guest.
3939	*/
3940	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
3941	AssertLogRelRCReturn(rc, rc);
3942
3943	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
3944	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
3945	* break on interrupt feature (bit 1).
3946	*/
3947	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
3948	AssertLogRelRCReturn(rc, rc);
3949
3950	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
3951	* Expose SSE4.1 to the guest if available.
3952	*/
3953	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
3954	AssertLogRelRCReturn(rc, rc);
3955
3956	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
3957	* Expose SSE4.2 to the guest if available.
3958	*/
3959	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
3960	AssertLogRelRCReturn(rc, rc);
3961
3962	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
3963	&& pVM->cpum.s.HostFeatures.fXSaveRstor
3964	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
3965	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
3966	&& !HMIsLongModeAllowed(pVM)
3967	#endif
3968	;
3969	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
3970
3971	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
3972	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
3973	* default is to only expose this to VMs with nested paging and AMD-V or
3974	* unrestricted guest execution mode. Not possible to force this one without
3975	* host support at the moment.
3976	*/
3977	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
3978	fMayHaveXSave /fAllowed/);
3979	AssertLogRelRCReturn(rc, rc);
3980
3981	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
3982	* Expose the AVX instruction set extensions to the guest if available and
3983	* XSAVE is exposed too. For the time being the default is to only expose this
3984	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3985	*/
3986	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
3987	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3988	AssertLogRelRCReturn(rc, rc);
3989
3990	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
3991	* Expose the AVX2 instruction set extensions to the guest if available and
3992	* XSAVE is exposed too. For the time being the default is to only expose this
3993	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
3994	*/
3995	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
3996	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
3997	AssertLogRelRCReturn(rc, rc);
3998
3999	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4000	* Whether to expose the AES instructions to the guest. For the time being the
4001	* default is to only do this for VMs with nested paging and AMD-V or
4002	* unrestricted guest mode.
4003	*/
4004	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4005	AssertLogRelRCReturn(rc, rc);
4006
4007	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4008	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4009	* being the default is to only do this for VMs with nested paging and AMD-V or
4010	* unrestricted guest mode.
4011	*/
4012	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4013	AssertLogRelRCReturn(rc, rc);
4014
4015	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4016	* Whether to expose the POPCNT instructions to the guest. For the time
4017	* being the default is to only do this for VMs with nested paging and AMD-V or
4018	* unrestricted guest mode.
4019	*/
4020	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4021	AssertLogRelRCReturn(rc, rc);
4022
4023	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4024	* Whether to expose the MOVBE instructions to the guest. For the time
4025	* being the default is to only do this for VMs with nested paging and AMD-V or
4026	* unrestricted guest mode.
4027	*/
4028	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4029	AssertLogRelRCReturn(rc, rc);
4030
4031	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4032	* Whether to expose the RDRAND instructions to the guest. For the time being
4033	* the default is to only do this for VMs with nested paging and AMD-V or
4034	* unrestricted guest mode.
4035	*/
4036	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4037	AssertLogRelRCReturn(rc, rc);
4038
4039	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4040	* Whether to expose the RDSEED instructions to the guest. For the time being
4041	* the default is to only do this for VMs with nested paging and AMD-V or
4042	* unrestricted guest mode.
4043	*/
4044	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4045	AssertLogRelRCReturn(rc, rc);
4046
4047	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4048	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4049	* being the default is to only do this for VMs with nested paging and AMD-V or
4050	* unrestricted guest mode.
4051	*/
4052	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4053	AssertLogRelRCReturn(rc, rc);
4054
4055
4056	/* AMD: */
4057
4058	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4059	* Whether to expose the AMD ABM instructions to the guest. For the time
4060	* being the default is to only do this for VMs with nested paging and AMD-V or
4061	* unrestricted guest mode.
4062	*/
4063	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4064	AssertLogRelRCReturn(rc, rc);
4065
4066	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4067	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4068	* being the default is to only do this for VMs with nested paging and AMD-V or
4069	* unrestricted guest mode.
4070	*/
4071	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4072	AssertLogRelRCReturn(rc, rc);
4073
4074	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4075	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4076	* the time being the default is to only do this for VMs with nested paging and
4077	* AMD-V or unrestricted guest mode.
4078	*/
4079	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4080	AssertLogRelRCReturn(rc, rc);
4081
4082	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4083	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4084	* For the time being the default is to only do this for VMs with nested paging
4085	* and AMD-V or unrestricted guest mode.
4086	*/
4087	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4088	AssertLogRelRCReturn(rc, rc);
4089
4090	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4091	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4092	* the default is to only do this for VMs with nested paging and AMD-V or
4093	* unrestricted guest mode.
4094	*/
4095	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4096	AssertLogRelRCReturn(rc, rc);
4097
4098	#ifdef VBOX_WITH_NESTED_HWVIRT
4099	/** @cfgm{/CPUM/IsaExts/SVM, isaextcfg, depends}
4100	* Whether to expose the AMD's hardware virtualization (SVM) instructions to the
4101	* guest. For the time being, the default is to only do this for VMs with nested
4102	* paging and AMD-V.
4103	*/
4104	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SVM", &pConfig->enmSvm, fNestedPagingAndFullGuestExec);
4105	AssertLogRelRCReturn(rc, rc);
4106	#endif
4107
4108	return VINF_SUCCESS;
4109	}
4110
4111
4112	/**
4113	* Initializes the emulated CPU's CPUID & MSR information.
4114	*
4115	* @returns VBox status code.
4116	* @param pVM The cross context VM structure.
4117	*/
4118	int cpumR3InitCpuIdAndMsrs(PVM pVM)
4119	{
4120	PCPUM pCpum = &pVM->cpum.s;
4121	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4122
4123	/*
4124	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4125	* on construction and manage everything from here on.
4126	*/
4127	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
4128	pVM->aCpus[iCpu].cpum.s.fCpuIdApicFeatureVisible = true;
4129
4130	/*
4131	* Read the configuration.
4132	*/
4133	CPUMCPUIDCONFIG Config;
4134	RT_ZERO(Config);
4135
4136	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4137	AssertRCReturn(rc, rc);
4138
4139	/*
4140	* Get the guest CPU data from the database and/or the host.
4141	*
4142	* The CPUID and MSRs are currently living on the regular heap to avoid
4143	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4144	* API for the hyper heap). This means special cleanup considerations.
4145	*/
4146	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4147	if (RT_FAILURE(rc))
4148	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4149	? VMSetError(pVM, rc, RT_SRC_POS,
4150	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4151	: rc;
4152
4153	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4154	{
4155	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4156	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4157	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4158	}
4159	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4160
4161	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4162	* Overrides the guest MSRs.
4163	*/
4164	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4165
4166	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4167	* Overrides the CPUID leaf values (from the host CPU usually) used for
4168	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4169	* values when moving a VM to a different machine. Another use is restricting
4170	* (or extending) the feature set exposed to the guest. */
4171	if (RT_SUCCESS(rc))
4172	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4173
4174	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4175	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4176	"Found unsupported configuration node '/CPUM/CPUID/'. "
4177	"Please use IMachine::setCPUIDLeaf() instead.");
4178
4179	/*
4180	* Pre-explode the CPUID info.
4181	*/
4182	if (RT_SUCCESS(rc))
4183	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
4184
4185	/*
4186	* Sanitize the cpuid information passed on to the guest.
4187	*/
4188	if (RT_SUCCESS(rc))
4189	{
4190	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4191	if (RT_SUCCESS(rc))
4192	{
4193	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4194	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4195	}
4196	}
4197
4198	/*
4199	* MSR fudging.
4200	*/
4201	if (RT_SUCCESS(rc))
4202	{
4203	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4204	* Fudges some common MSRs if not present in the selected CPU database entry.
4205	* This is for trying to keep VMs running when moved between different hosts
4206	* and different CPU vendors. */
4207	bool fEnable;
4208	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4209	if (RT_SUCCESS(rc) && fEnable)
4210	{
4211	rc = cpumR3MsrApplyFudge(pVM);
4212	AssertLogRelRC(rc);
4213	}
4214	}
4215	if (RT_SUCCESS(rc))
4216	{
4217	/*
4218	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4219	* guest CPU features again.
4220	*/
4221	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4222	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4223	pCpum->GuestInfo.cCpuIdLeaves);
4224	RTMemFree(pvFree);
4225
4226	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4227	int rc2 = MMHyperDupMem(pVM, pvFree,
4228	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4229	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4230	RTMemFree(pvFree);
4231	AssertLogRelRCReturn(rc1, rc1);
4232	AssertLogRelRCReturn(rc2, rc2);
4233
4234	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4235	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4236
4237
4238	/*
4239	* Some more configuration that we're applying at the end of everything
4240	* via the CPUMSetGuestCpuIdFeature API.
4241	*/
4242
4243	/* Check if PAE was explicitely enabled by the user. */
4244	bool fEnable;
4245	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4246	AssertRCReturn(rc, rc);
4247	if (fEnable)
4248	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4249
4250	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4251	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4252	AssertRCReturn(rc, rc);
4253	if (fEnable)
4254	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4255
4256	return VINF_SUCCESS;
4257	}
4258
4259	/*
4260	* Failed before switching to hyper heap.
4261	*/
4262	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4263	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4264	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4265	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4266	return rc;
4267	}
4268
4269
4270	/**
4271	* Sets a CPUID feature bit during VM initialization.
4272	*
4273	* Since the CPUID feature bits are generally related to CPU features, other
4274	* CPUM configuration like MSRs can also be modified by calls to this API.
4275	*
4276	* @param pVM The cross context VM structure.
4277	* @param enmFeature The feature to set.
4278	*/
4279	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4280	{
4281	PCPUMCPUIDLEAF pLeaf;
4282	PCPUMMSRRANGE pMsrRange;
4283
4284	switch (enmFeature)
4285	{
4286	/*
4287	* Set the APIC bit in both feature masks.
4288	*/
4289	case CPUMCPUIDFEATURE_APIC:
4290	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4291	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4292	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4293
4294	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4295	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4296	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4297
4298	pVM->cpum.s.GuestFeatures.fApic = 1;
4299
4300	/* Make sure we've got the APICBASE MSR present. */
4301	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4302	if (!pMsrRange)
4303	{
4304	static CPUMMSRRANGE const s_ApicBase =
4305	{
4306	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4307	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4308	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4309	/.szName = / "IA32_APIC_BASE"
4310	};
4311	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4312	AssertLogRelRC(rc);
4313	}
4314
4315	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4316	break;
4317
4318	/*
4319	* Set the x2APIC bit in the standard feature mask.
4320	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4321	*/
4322	case CPUMCPUIDFEATURE_X2APIC:
4323	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4324	if (pLeaf)
4325	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4326	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4327
4328	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4329	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4330	if (pMsrRange)
4331	{
4332	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4333	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4334	}
4335
4336	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4337	break;
4338
4339	/*
4340	* Set the sysenter/sysexit bit in the standard feature mask.
4341	* Assumes the caller knows what it's doing! (host must support these)
4342	*/
4343	case CPUMCPUIDFEATURE_SEP:
4344	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4345	{
4346	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4347	return;
4348	}
4349
4350	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4351	if (pLeaf)
4352	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4353	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4354	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4355	break;
4356
4357	/*
4358	* Set the syscall/sysret bit in the extended feature mask.
4359	* Assumes the caller knows what it's doing! (host must support these)
4360	*/
4361	case CPUMCPUIDFEATURE_SYSCALL:
4362	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4363	if ( !pLeaf
4364	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4365	{
4366	#if HC_ARCH_BITS == 32
4367	/* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit
4368	mode by Intel, even when the cpu is capable of doing so in
4369	64-bit mode. Long mode requires syscall support. */
4370	if (!pVM->cpum.s.HostFeatures.fLongMode)
4371	#endif
4372	{
4373	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4374	return;
4375	}
4376	}
4377
4378	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4379	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4380	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4381	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4382	break;
4383
4384	/*
4385	* Set the PAE bit in both feature masks.
4386	* Assumes the caller knows what it's doing! (host must support these)
4387	*/
4388	case CPUMCPUIDFEATURE_PAE:
4389	if (!pVM->cpum.s.HostFeatures.fPae)
4390	{
4391	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4392	return;
4393	}
4394
4395	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4396	if (pLeaf)
4397	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4398
4399	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4400	if ( pLeaf
4401	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4402	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4403
4404	pVM->cpum.s.GuestFeatures.fPae = 1;
4405	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4406	break;
4407
4408	/*
4409	* Set the LONG MODE bit in the extended feature mask.
4410	* Assumes the caller knows what it's doing! (host must support these)
4411	*/
4412	case CPUMCPUIDFEATURE_LONG_MODE:
4413	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4414	if ( !pLeaf
4415	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4416	{
4417	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4418	return;
4419	}
4420
4421	/* Valid for both Intel and AMD. */
4422	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4423	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4424	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4425	break;
4426
4427	/*
4428	* Set the NX/XD bit in the extended feature mask.
4429	* Assumes the caller knows what it's doing! (host must support these)
4430	*/
4431	case CPUMCPUIDFEATURE_NX:
4432	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4433	if ( !pLeaf
4434	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4435	{
4436	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4437	return;
4438	}
4439
4440	/* Valid for both Intel and AMD. */
4441	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4442	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4443	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4444	break;
4445
4446
4447	/*
4448	* Set the LAHF/SAHF support in 64-bit mode.
4449	* Assumes the caller knows what it's doing! (host must support this)
4450	*/
4451	case CPUMCPUIDFEATURE_LAHF:
4452	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4453	if ( !pLeaf
4454	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4455	{
4456	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4457	return;
4458	}
4459
4460	/* Valid for both Intel and AMD. */
4461	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4462	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4463	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4464	break;
4465
4466	/*
4467	* Set the page attribute table bit. This is alternative page level
4468	* cache control that doesn't much matter when everything is
4469	* virtualized, though it may when passing thru device memory.
4470	*/
4471	case CPUMCPUIDFEATURE_PAT:
4472	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4473	if (pLeaf)
4474	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4475
4476	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4477	if ( pLeaf
4478	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4479	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4480
4481	pVM->cpum.s.GuestFeatures.fPat = 1;
4482	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4483	break;
4484
4485	/*
4486	* Set the RDTSCP support bit.
4487	* Assumes the caller knows what it's doing! (host must support this)
4488	*/
4489	case CPUMCPUIDFEATURE_RDTSCP:
4490	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4491	if ( !pLeaf
4492	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4493	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4494	{
4495	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4496	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4497	return;
4498	}
4499
4500	/* Valid for both Intel and AMD. */
4501	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4502	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4503	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4504	break;
4505
4506	/*
4507	* Set the Hypervisor Present bit in the standard feature mask.
4508	*/
4509	case CPUMCPUIDFEATURE_HVP:
4510	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4511	if (pLeaf)
4512	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4513	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4514	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4515	break;
4516
4517	/*
4518	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4519	* This currently includes the Present bit and MWAITBREAK bit as well.
4520	*/
4521	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4522	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4523	if ( !pLeaf
4524	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4525	{
4526	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4527	return;
4528	}
4529
4530	/* Valid for both Intel and AMD. */
4531	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4532	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4533	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4534	break;
4535
4536	default:
4537	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4538	break;
4539	}
4540
4541	/** @todo can probably kill this as this API is now init time only... */
4542	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4543	{
4544	PVMCPU pVCpu = &pVM->aCpus[i];
4545	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4546	}
4547	}
4548
4549
4550	/**
4551	* Queries a CPUID feature bit.
4552	*
4553	* @returns boolean for feature presence
4554	* @param pVM The cross context VM structure.
4555	* @param enmFeature The feature to query.
4556	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4557	*/
4558	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4559	{
4560	switch (enmFeature)
4561	{
4562	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4563	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4564	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4565	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4566	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4567	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4568	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4569	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4570	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4571	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4572	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4573	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4574
4575	case CPUMCPUIDFEATURE_INVALID:
4576	case CPUMCPUIDFEATURE_32BIT_HACK:
4577	break;
4578	}
4579	AssertFailed();
4580	return false;
4581	}
4582
4583
4584	/**
4585	* Clears a CPUID feature bit.
4586	*
4587	* @param pVM The cross context VM structure.
4588	* @param enmFeature The feature to clear.
4589	*
4590	* @deprecated Probably better to default the feature to disabled and only allow
4591	* setting (enabling) it during construction.
4592	*/
4593	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4594	{
4595	PCPUMCPUIDLEAF pLeaf;
4596	switch (enmFeature)
4597	{
4598	case CPUMCPUIDFEATURE_APIC:
4599	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
4600	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4601	if (pLeaf)
4602	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
4603
4604	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4605	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4606	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4607
4608	pVM->cpum.s.GuestFeatures.fApic = 0;
4609	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4610	break;
4611
4612	case CPUMCPUIDFEATURE_X2APIC:
4613	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4614	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4615	if (pLeaf)
4616	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
4617	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
4618	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
4619	break;
4620
4621	case CPUMCPUIDFEATURE_PAE:
4622	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4623	if (pLeaf)
4624	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
4625
4626	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4627	if ( pLeaf
4628	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4629	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
4630
4631	pVM->cpum.s.GuestFeatures.fPae = 0;
4632	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
4633	break;
4634
4635	case CPUMCPUIDFEATURE_PAT:
4636	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4637	if (pLeaf)
4638	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
4639
4640	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4641	if ( pLeaf
4642	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4643	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
4644
4645	pVM->cpum.s.GuestFeatures.fPat = 0;
4646	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
4647	break;
4648
4649	case CPUMCPUIDFEATURE_LONG_MODE:
4650	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4651	if (pLeaf)
4652	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4653	pVM->cpum.s.GuestFeatures.fLongMode = 0;
4654	break;
4655
4656	case CPUMCPUIDFEATURE_LAHF:
4657	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4658	if (pLeaf)
4659	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4660	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
4661	break;
4662
4663	case CPUMCPUIDFEATURE_RDTSCP:
4664	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4665	if (pLeaf)
4666	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4667	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
4668	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
4669	break;
4670
4671	case CPUMCPUIDFEATURE_HVP:
4672	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4673	if (pLeaf)
4674	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
4675	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
4676	break;
4677
4678	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4679	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4680	if (pLeaf)
4681	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
4682	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
4683	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
4684	break;
4685
4686	default:
4687	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4688	break;
4689	}
4690
4691	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4692	{
4693	PVMCPU pVCpu = &pVM->aCpus[i];
4694	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4695	}
4696	}
4697
4698
4699
4700	/*
4701	*
4702	*
4703	* Saved state related code.
4704	* Saved state related code.
4705	* Saved state related code.
4706	*
4707	*
4708	*/
4709
4710	/**
4711	* Called both in pass 0 and the final pass.
4712	*
4713	* @param pVM The cross context VM structure.
4714	* @param pSSM The saved state handle.
4715	*/
4716	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4717	{
4718	/*
4719	* Save all the CPU ID leaves.
4720	*/
4721	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4722	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4723	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4724	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4725
4726	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4727
4728	/*
4729	* Save a good portion of the raw CPU IDs as well as they may come in
4730	* handy when validating features for raw mode.
4731	*/
4732	CPUMCPUID aRawStd[16];
4733	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4734	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4735	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4736	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4737
4738	CPUMCPUID aRawExt[32];
4739	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4740	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4741	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4742	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4743	}
4744
4745
4746	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4747	{
4748	uint32_t cCpuIds;
4749	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4750	if (RT_SUCCESS(rc))
4751	{
4752	if (cCpuIds < 64)
4753	{
4754	for (uint32_t i = 0; i < cCpuIds; i++)
4755	{
4756	CPUMCPUID CpuId;
4757	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4758	if (RT_FAILURE(rc))
4759	break;
4760
4761	CPUMCPUIDLEAF NewLeaf;
4762	NewLeaf.uLeaf = uBase + i;
4763	NewLeaf.uSubLeaf = 0;
4764	NewLeaf.fSubLeafMask = 0;
4765	NewLeaf.uEax = CpuId.uEax;
4766	NewLeaf.uEbx = CpuId.uEbx;
4767	NewLeaf.uEcx = CpuId.uEcx;
4768	NewLeaf.uEdx = CpuId.uEdx;
4769	NewLeaf.fFlags = 0;
4770	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4771	}
4772	}
4773	else
4774	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4775	}
4776	if (RT_FAILURE(rc))
4777	{
4778	RTMemFree(*ppaLeaves);
4779	*ppaLeaves = NULL;
4780	*pcLeaves = 0;
4781	}
4782	return rc;
4783	}
4784
4785
4786	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4787	{
4788	*ppaLeaves = NULL;
4789	*pcLeaves = 0;
4790
4791	int rc;
4792	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4793	{
4794	/*
4795	* The new format. Starts by declaring the leave size and count.
4796	*/
4797	uint32_t cbLeaf;
4798	SSMR3GetU32(pSSM, &cbLeaf);
4799	uint32_t cLeaves;
4800	rc = SSMR3GetU32(pSSM, &cLeaves);
4801	if (RT_SUCCESS(rc))
4802	{
4803	if (cbLeaf == sizeof(**ppaLeaves))
4804	{
4805	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4806	{
4807	/*
4808	* Load the leaves one by one.
4809	*
4810	* The uPrev stuff is a kludge for working around a week worth of bad saved
4811	* states during the CPUID revamp in March 2015. We saved too many leaves
4812	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4813	* garbage entires at the end of the array when restoring. We also had
4814	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
4815	* this kludge doesn't deal correctly with that, but who cares...
4816	*/
4817	uint32_t uPrev = 0;
4818	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4819	{
4820	CPUMCPUIDLEAF Leaf;
4821	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
4822	if (RT_SUCCESS(rc))
4823	{
4824	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
4825	\|\| Leaf.uLeaf >= uPrev)
4826	{
4827	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4828	uPrev = Leaf.uLeaf;
4829	}
4830	else
4831	uPrev = UINT32_MAX;
4832	}
4833	}
4834	}
4835	else
4836	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
4837	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
4838	}
4839	else
4840	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
4841	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
4842	}
4843	}
4844	else
4845	{
4846	/*
4847	* The old format with its three inflexible arrays.
4848	*/
4849	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
4850	if (RT_SUCCESS(rc))
4851	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
4852	if (RT_SUCCESS(rc))
4853	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
4854	if (RT_SUCCESS(rc))
4855	{
4856	/*
4857	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
4858	*/
4859	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
4860	if ( pLeaf
4861	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
4862	{
4863	CPUMCPUIDLEAF Leaf;
4864	Leaf.uLeaf = 4;
4865	Leaf.fSubLeafMask = UINT32_MAX;
4866	Leaf.uSubLeaf = 0;
4867	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
4868	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
4869	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
4870	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
4871	\| UINT32_C(63); /* system coherency line size - 1 */
4872	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
4873	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
4874	\| (UINT32_C(1) << 5) /* cache level */
4875	\| UINT32_C(1); /* cache type (data) */
4876	Leaf.fFlags = 0;
4877	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4878	if (RT_SUCCESS(rc))
4879	{
4880	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
4881	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4882	}
4883	if (RT_SUCCESS(rc))
4884	{
4885	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
4886	Leaf.uEcx = 4095; /* sets - 1 */
4887	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
4888	Leaf.uEbx \|= UINT32_C(23) << 22;
4889	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
4890	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
4891	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
4892	Leaf.uEax \|= UINT32_C(2) << 5;
4893	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4894	}
4895	}
4896	}
4897	}
4898	return rc;
4899	}
4900
4901
4902	/**
4903	* Loads the CPU ID leaves saved by pass 0, inner worker.
4904	*
4905	* @returns VBox status code.
4906	* @param pVM The cross context VM structure.
4907	* @param pSSM The saved state handle.
4908	* @param uVersion The format version.
4909	* @param paLeaves Guest CPUID leaves loaded from the state.
4910	* @param cLeaves The number of leaves in @a paLeaves.
4911	*/
4912	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
4913	{
4914	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4915
4916	/*
4917	* Continue loading the state into stack buffers.
4918	*/
4919	CPUMCPUID GuestDefCpuId;
4920	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
4921	AssertRCReturn(rc, rc);
4922
4923	CPUMCPUID aRawStd[16];
4924	uint32_t cRawStd;
4925	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
4926	if (cRawStd > RT_ELEMENTS(aRawStd))
4927	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4928	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
4929	AssertRCReturn(rc, rc);
4930	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
4931	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4932
4933	CPUMCPUID aRawExt[32];
4934	uint32_t cRawExt;
4935	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
4936	if (cRawExt > RT_ELEMENTS(aRawExt))
4937	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4938	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
4939	AssertRCReturn(rc, rc);
4940	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
4941	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4942
4943	/*
4944	* Get the raw CPU IDs for the current host.
4945	*/
4946	CPUMCPUID aHostRawStd[16];
4947	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
4948	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
4949
4950	CPUMCPUID aHostRawExt[32];
4951	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
4952	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
4953	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4954
4955	/*
4956	* Get the host and guest overrides so we don't reject the state because
4957	* some feature was enabled thru these interfaces.
4958	* Note! We currently only need the feature leaves, so skip rest.
4959	*/
4960	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4961	CPUMCPUID aHostOverrideStd[2];
4962	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4963	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4964
4965	CPUMCPUID aHostOverrideExt[2];
4966	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4967	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4968
4969	/*
4970	* This can be skipped.
4971	*/
4972	bool fStrictCpuIdChecks;
4973	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
4974
4975	/*
4976	* Define a bunch of macros for simplifying the santizing/checking code below.
4977	*/
4978	/* Generic expression + failure message. */
4979	#define CPUID_CHECK_RET(expr, fmt) \
4980	do { \
4981	if (!(expr)) \
4982	{ \
4983	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
4984	if (fStrictCpuIdChecks) \
4985	{ \
4986	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4987	RTStrFree(pszMsg); \
4988	return rcCpuid; \
4989	} \
4990	LogRel(("CPUM: %s\n", pszMsg)); \
4991	RTStrFree(pszMsg); \
4992	} \
4993	} while (0)
4994	#define CPUID_CHECK_WRN(expr, fmt) \
4995	do { \
4996	if (!(expr)) \
4997	LogRel(fmt); \
4998	} while (0)
4999
5000	/* For comparing two values and bitch if they differs. */
5001	#define CPUID_CHECK2_RET(what, host, saved) \
5002	do { \
5003	if ((host) != (saved)) \
5004	{ \
5005	if (fStrictCpuIdChecks) \
5006	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5007	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5008	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5009	} \
5010	} while (0)
5011	#define CPUID_CHECK2_WRN(what, host, saved) \
5012	do { \
5013	if ((host) != (saved)) \
5014	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5015	} while (0)
5016
5017	/* For checking raw cpu features (raw mode). */
5018	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5019	do { \
5020	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5021	{ \
5022	if (fStrictCpuIdChecks) \
5023	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5024	N_(#bit " mismatch: host=%d saved=%d"), \
5025	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5026	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5027	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5028	} \
5029	} while (0)
5030	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5031	do { \
5032	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5033	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5034	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5035	} while (0)
5036	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5037
5038	/* For checking guest features. */
5039	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5040	do { \
5041	if ( (aGuestCpuId##set [1].reg & bit) \
5042	&& !(aHostRaw##set [1].reg & bit) \
5043	&& !(aHostOverride##set [1].reg & bit) \
5044	) \
5045	{ \
5046	if (fStrictCpuIdChecks) \
5047	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5048	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5049	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5050	} \
5051	} while (0)
5052	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5053	do { \
5054	if ( (aGuestCpuId##set [1].reg & bit) \
5055	&& !(aHostRaw##set [1].reg & bit) \
5056	&& !(aHostOverride##set [1].reg & bit) \
5057	) \
5058	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5059	} while (0)
5060	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5061	do { \
5062	if ( (aGuestCpuId##set [1].reg & bit) \
5063	&& !(aHostRaw##set [1].reg & bit) \
5064	&& !(aHostOverride##set [1].reg & bit) \
5065	) \
5066	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5067	} while (0)
5068	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5069
5070	/* For checking guest features if AMD guest CPU. */
5071	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5072	do { \
5073	if ( (aGuestCpuId##set [1].reg & bit) \
5074	&& fGuestAmd \
5075	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5076	&& !(aHostOverride##set [1].reg & bit) \
5077	) \
5078	{ \
5079	if (fStrictCpuIdChecks) \
5080	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5081	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5082	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5083	} \
5084	} while (0)
5085	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5086	do { \
5087	if ( (aGuestCpuId##set [1].reg & bit) \
5088	&& fGuestAmd \
5089	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5090	&& !(aHostOverride##set [1].reg & bit) \
5091	) \
5092	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5093	} while (0)
5094	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5095	do { \
5096	if ( (aGuestCpuId##set [1].reg & bit) \
5097	&& fGuestAmd \
5098	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5099	&& !(aHostOverride##set [1].reg & bit) \
5100	) \
5101	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5102	} while (0)
5103	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5104
5105	/* For checking AMD features which have a corresponding bit in the standard
5106	range. (Intel defines very few bits in the extended feature sets.) */
5107	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5108	do { \
5109	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5110	&& !(fHostAmd \
5111	? aHostRawExt[1].reg & (ExtBit) \
5112	: aHostRawStd[1].reg & (StdBit)) \
5113	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5114	) \
5115	{ \
5116	if (fStrictCpuIdChecks) \
5117	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5118	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5119	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5120	} \
5121	} while (0)
5122	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5123	do { \
5124	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5125	&& !(fHostAmd \
5126	? aHostRawExt[1].reg & (ExtBit) \
5127	: aHostRawStd[1].reg & (StdBit)) \
5128	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5129	) \
5130	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5131	} while (0)
5132	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5133	do { \
5134	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5135	&& !(fHostAmd \
5136	? aHostRawExt[1].reg & (ExtBit) \
5137	: aHostRawStd[1].reg & (StdBit)) \
5138	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5139	) \
5140	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5141	} while (0)
5142	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5143
5144	/*
5145	* For raw-mode we'll require that the CPUs are very similar since we don't
5146	* intercept CPUID instructions for user mode applications.
5147	*/
5148	if (!HMIsEnabled(pVM))
5149	{
5150	/* CPUID(0) */
5151	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
5152	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
5153	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
5154	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5155	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
5156	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
5157	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
5158	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
5159	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5160
5161	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
5162
5163	/* CPUID(1).eax */
5164	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
5165	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
5166	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
5167
5168	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
5169	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
5170	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
5171
5172	/* CPUID(1).ecx */
5173	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
5174	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
5175	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
5176	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5177	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
5178	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
5179	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
5180	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
5181	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
5182	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
5183	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
5184	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
5185	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
5186	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
5187	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
5188	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
5189	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5190	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5191	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
5192	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
5193	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
5194	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5195	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
5196	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
5197	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5198	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
5199	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
5200	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5201	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
5202	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5203	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5204	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
5205
5206	/* CPUID(1).edx */
5207	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5208	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5209	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
5210	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5211	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
5212	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
5213	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5214	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5215	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
5216	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5217	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5218	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5219	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5220	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5221	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5222	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
5223	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5224	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5225	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5226	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
5227	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5228	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
5229	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
5230	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
5231	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
5232	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
5233	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
5234	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
5235	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
5236	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
5237	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
5238	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
5239
5240	/* CPUID(2) - config, mostly about caches. ignore. */
5241	/* CPUID(3) - processor serial number. ignore. */
5242	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
5243	/* CPUID(5) - mwait/monitor config. ignore. */
5244	/* CPUID(6) - power management. ignore. */
5245	/* CPUID(7) - ???. ignore. */
5246	/* CPUID(8) - ???. ignore. */
5247	/* CPUID(9) - DCA. ignore for now. */
5248	/* CPUID(a) - PeMo info. ignore for now. */
5249	/* CPUID(b) - topology info - takes ECX as input. ignore. */
5250
5251	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
5252	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
5253	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
5254	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
5255	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
5256	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
5257	{
5258	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
5259	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
5260	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
5261	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
5262	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
5263	}
5264
5265	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
5266	Note! Intel have/is marking many of the fields here as reserved. We
5267	will verify them as if it's an AMD CPU. */
5268	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
5269	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
5270	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
5271	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
5272	{
5273	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
5274	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
5275	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
5276	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5277	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
5278	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
5279	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
5280
5281	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
5282	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
5283	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
5284	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
5285	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
5286	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5287
5288	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
5289	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
5290	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
5291	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
5292
5293	/* CPUID(0x80000001).ecx */
5294	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
5295	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
5296	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
5297	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
5298	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
5299	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
5300	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
5301	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
5302	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
5303	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
5304	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
5305	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
5306	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
5307	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
5308	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5309	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5310	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5311	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5312	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5313	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5314	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5315	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5316	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5317	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5318	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5319	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5320	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5321	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5322	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5323	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5324	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5325	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5326
5327	/* CPUID(0x80000001).edx */
5328	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
5329	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
5330	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
5331	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
5332	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
5333	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
5334	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
5335	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
5336	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
5337	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
5338	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5339	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
5340	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
5341	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
5342	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
5343	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
5344	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
5345	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
5346	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5347	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5348	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5349	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
5350	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5351	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
5352	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
5353	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5354	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5355	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5356	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
5357	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5358	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5359	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5360
5361	/** @todo verify the rest as well. */
5362	}
5363	}
5364
5365
5366
5367	/*
5368	* Verify that we can support the features already exposed to the guest on
5369	* this host.
5370	*
5371	* Most of the features we're emulating requires intercepting instruction
5372	* and doing it the slow way, so there is no need to warn when they aren't
5373	* present in the host CPU. Thus we use IGN instead of EMU on these.
5374	*
5375	* Trailing comments:
5376	* "EMU" - Possible to emulate, could be lots of work and very slow.
5377	* "EMU?" - Can this be emulated?
5378	*/
5379	CPUMCPUID aGuestCpuIdStd[2];
5380	RT_ZERO(aGuestCpuIdStd);
5381	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5382
5383	/* CPUID(1).ecx */
5384	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5385	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5386	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5387	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5388	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5389	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5390	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5391	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5392	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5393	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5394	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5395	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5396	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5397	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5398	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5399	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5400	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5401	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5402	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5403	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5404	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5405	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5406	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5407	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5408	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5409	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5410	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5411	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5412	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5413	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5414	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5415	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5416
5417	/* CPUID(1).edx */
5418	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5419	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5420	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5421	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5422	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5423	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5424	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5425	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5426	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5427	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5428	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5429	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5430	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5431	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5432	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5433	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5434	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5435	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5436	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5437	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5438	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5439	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5440	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5441	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5442	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5443	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5444	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5445	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5446	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5447	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5448	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5449	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5450
5451	/* CPUID(0x80000000). */
5452	CPUMCPUID aGuestCpuIdExt[2];
5453	RT_ZERO(aGuestCpuIdExt);
5454	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5455	{
5456	/** @todo deal with no 0x80000001 on the host. */
5457	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5458	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5459
5460	/* CPUID(0x80000001).ecx */
5461	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5462	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5463	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5464	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5465	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5466	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5467	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5468	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5469	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5470	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5471	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5472	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5473	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5474	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5475	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5476	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5477	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5478	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5479	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5480	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5481	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5482	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5483	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5484	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5485	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5486	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5487	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5488	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5489	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5490	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5491	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5492	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5493
5494	/* CPUID(0x80000001).edx */
5495	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5496	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5497	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5498	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5499	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5500	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5501	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5502	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5503	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5504	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5505	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5506	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5507	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5508	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5509	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5510	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5511	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5512	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5513	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5514	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5515	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5516	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5517	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5518	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5519	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5520	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5521	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5522	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5523	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5524	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5525	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5526	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5527	}
5528
5529	/** @todo check leaf 7 */
5530
5531	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5532	* ECX=0: EAX - Valid bits in XCR0[31:0].
5533	* EBX - Maximum state size as per current XCR0 value.
5534	* ECX - Maximum state size for all supported features.
5535	* EDX - Valid bits in XCR0[63:32].
5536	* ECX=1: EAX - Various X-features.
5537	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5538	* ECX - Valid bits in IA32_XSS[31:0].
5539	* EDX - Valid bits in IA32_XSS[63:32].
5540	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5541	* if the bit invalid all four registers are set to zero.
5542	* EAX - The state size for this feature.
5543	* EBX - The state byte offset of this feature.
5544	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5545	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5546	*/
5547	uint64_t fGuestXcr0Mask = 0;
5548	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5549	if ( pCurLeaf
5550	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5551	&& ( pCurLeaf->uEax
5552	\|\| pCurLeaf->uEbx
5553	\|\| pCurLeaf->uEcx
5554	\|\| pCurLeaf->uEdx) )
5555	{
5556	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5557	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5558	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5559	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5560	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5561	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5562	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5563	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5564
5565	/* We don't support any additional features yet. */
5566	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5567	if (pCurLeaf && pCurLeaf->uEax)
5568	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5569	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5570	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5571	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5572	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5573	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5574
5575
5576	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5577	{
5578	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5579	if (pCurLeaf)
5580	{
5581	/* If advertised, the state component offset and size must match the one used by host. */
5582	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5583	{
5584	CPUMCPUID RawHost;
5585	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5586	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5587	if ( RawHost.uEbx != pCurLeaf->uEbx
5588	\|\| RawHost.uEax != pCurLeaf->uEax)
5589	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5590	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5591	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5592	}
5593	}
5594	}
5595	}
5596	/* Clear leaf 0xd just in case we're loading an old state... */
5597	else if (pCurLeaf)
5598	{
5599	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5600	{
5601	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5602	if (pCurLeaf)
5603	{
5604	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5605	\|\| ( pCurLeaf->uEax == 0
5606	&& pCurLeaf->uEbx == 0
5607	&& pCurLeaf->uEcx == 0
5608	&& pCurLeaf->uEdx == 0),
5609	("uVersion=%#x; %#x %#x %#x %#x\n",
5610	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5611	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5612	}
5613	}
5614	}
5615
5616	/* Update the fXStateGuestMask value for the VM. */
5617	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5618	{
5619	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5620	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5621	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5622	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5623	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5624	}
5625
5626	#undef CPUID_CHECK_RET
5627	#undef CPUID_CHECK_WRN
5628	#undef CPUID_CHECK2_RET
5629	#undef CPUID_CHECK2_WRN
5630	#undef CPUID_RAW_FEATURE_RET
5631	#undef CPUID_RAW_FEATURE_WRN
5632	#undef CPUID_RAW_FEATURE_IGN
5633	#undef CPUID_GST_FEATURE_RET
5634	#undef CPUID_GST_FEATURE_WRN
5635	#undef CPUID_GST_FEATURE_EMU
5636	#undef CPUID_GST_FEATURE_IGN
5637	#undef CPUID_GST_FEATURE2_RET
5638	#undef CPUID_GST_FEATURE2_WRN
5639	#undef CPUID_GST_FEATURE2_EMU
5640	#undef CPUID_GST_FEATURE2_IGN
5641	#undef CPUID_GST_AMD_FEATURE_RET
5642	#undef CPUID_GST_AMD_FEATURE_WRN
5643	#undef CPUID_GST_AMD_FEATURE_EMU
5644	#undef CPUID_GST_AMD_FEATURE_IGN
5645
5646	/*
5647	* We're good, commit the CPU ID leaves.
5648	*/
5649	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5650	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5651	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5652	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
5653	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5654	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
5655	AssertLogRelRCReturn(rc, rc);
5656
5657	return VINF_SUCCESS;
5658	}
5659
5660
5661	/**
5662	* Loads the CPU ID leaves saved by pass 0.
5663	*
5664	* @returns VBox status code.
5665	* @param pVM The cross context VM structure.
5666	* @param pSSM The saved state handle.
5667	* @param uVersion The format version.
5668	*/
5669	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5670	{
5671	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5672
5673	/*
5674	* Load the CPUID leaves array first and call worker to do the rest, just so
5675	* we can free the memory when we need to without ending up in column 1000.
5676	*/
5677	PCPUMCPUIDLEAF paLeaves;
5678	uint32_t cLeaves;
5679	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5680	AssertRC(rc);
5681	if (RT_SUCCESS(rc))
5682	{
5683	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
5684	RTMemFree(paLeaves);
5685	}
5686	return rc;
5687	}
5688
5689
5690
5691	/**
5692	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5693	*
5694	* @returns VBox status code.
5695	* @param pVM The cross context VM structure.
5696	* @param pSSM The saved state handle.
5697	* @param uVersion The format version.
5698	*/
5699	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5700	{
5701	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5702
5703	/*
5704	* Restore the CPUID leaves.
5705	*
5706	* Note that we support restoring less than the current amount of standard
5707	* leaves because we've been allowed more is newer version of VBox.
5708	*/
5709	uint32_t cElements;
5710	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5711	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5712	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5713	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5714
5715	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5716	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5717	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5718	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5719
5720	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5721	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5722	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5723	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5724
5725	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5726
5727	/*
5728	* Check that the basic cpuid id information is unchanged.
5729	*/
5730	/** @todo we should check the 64 bits capabilities too! */
5731	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5732	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5733	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5734	uint32_t au32CpuIdSaved[8];
5735	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5736	if (RT_SUCCESS(rc))
5737	{
5738	/* Ignore CPU stepping. */
5739	au32CpuId[4] &= 0xfffffff0;
5740	au32CpuIdSaved[4] &= 0xfffffff0;
5741
5742	/* Ignore APIC ID (AMD specs). */
5743	au32CpuId[5] &= ~0xff000000;
5744	au32CpuIdSaved[5] &= ~0xff000000;
5745
5746	/* Ignore the number of Logical CPUs (AMD specs). */
5747	au32CpuId[5] &= ~0x00ff0000;
5748	au32CpuIdSaved[5] &= ~0x00ff0000;
5749
5750	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5751	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5752	\| X86_CPUID_FEATURE_ECX_VMX
5753	\| X86_CPUID_FEATURE_ECX_SMX
5754	\| X86_CPUID_FEATURE_ECX_EST
5755	\| X86_CPUID_FEATURE_ECX_TM2
5756	\| X86_CPUID_FEATURE_ECX_CNTXID
5757	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5758	\| X86_CPUID_FEATURE_ECX_PDCM
5759	\| X86_CPUID_FEATURE_ECX_DCA
5760	\| X86_CPUID_FEATURE_ECX_X2APIC
5761	);
5762	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5763	\| X86_CPUID_FEATURE_ECX_VMX
5764	\| X86_CPUID_FEATURE_ECX_SMX
5765	\| X86_CPUID_FEATURE_ECX_EST
5766	\| X86_CPUID_FEATURE_ECX_TM2
5767	\| X86_CPUID_FEATURE_ECX_CNTXID
5768	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5769	\| X86_CPUID_FEATURE_ECX_PDCM
5770	\| X86_CPUID_FEATURE_ECX_DCA
5771	\| X86_CPUID_FEATURE_ECX_X2APIC
5772	);
5773
5774	/* Make sure we don't forget to update the masks when enabling
5775	* features in the future.
5776	*/
5777	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5778	( X86_CPUID_FEATURE_ECX_DTES64
5779	\| X86_CPUID_FEATURE_ECX_VMX
5780	\| X86_CPUID_FEATURE_ECX_SMX
5781	\| X86_CPUID_FEATURE_ECX_EST
5782	\| X86_CPUID_FEATURE_ECX_TM2
5783	\| X86_CPUID_FEATURE_ECX_CNTXID
5784	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5785	\| X86_CPUID_FEATURE_ECX_PDCM
5786	\| X86_CPUID_FEATURE_ECX_DCA
5787	\| X86_CPUID_FEATURE_ECX_X2APIC
5788	)));
5789	/* do the compare */
5790	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5791	{
5792	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5793	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5794	"Saved=%.*Rhxs\n"
5795	"Real =%.*Rhxs\n",
5796	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5797	sizeof(au32CpuId), au32CpuId));
5798	else
5799	{
5800	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5801	"Saved=%.*Rhxs\n"
5802	"Real =%.*Rhxs\n",
5803	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5804	sizeof(au32CpuId), au32CpuId));
5805	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5806	}
5807	}
5808	}
5809
5810	return rc;
5811	}
5812
5813
5814
5815	/*
5816	*
5817	*
5818	* CPUID Info Handler.
5819	* CPUID Info Handler.
5820	* CPUID Info Handler.
5821	*
5822	*
5823	*/
5824
5825
5826
5827	/**
5828	* Get L1 cache / TLS associativity.
5829	*/
5830	static const char getCacheAss(unsigned u, char pszBuf)
5831	{
5832	if (u == 0)
5833	return "res0 ";
5834	if (u == 1)
5835	return "direct";
5836	if (u == 255)
5837	return "fully";
5838	if (u >= 256)
5839	return "???";
5840
5841	RTStrPrintf(pszBuf, 16, "%d way", u);
5842	return pszBuf;
5843	}
5844
5845
5846	/**
5847	* Get L2 cache associativity.
5848	*/
5849	const char *getL2CacheAss(unsigned u)
5850	{
5851	switch (u)
5852	{
5853	case 0: return "off ";
5854	case 1: return "direct";
5855	case 2: return "2 way ";
5856	case 3: return "res3 ";
5857	case 4: return "4 way ";
5858	case 5: return "res5 ";
5859	case 6: return "8 way ";
5860	case 7: return "res7 ";
5861	case 8: return "16 way";
5862	case 9: return "res9 ";
5863	case 10: return "res10 ";
5864	case 11: return "res11 ";
5865	case 12: return "res12 ";
5866	case 13: return "res13 ";
5867	case 14: return "res14 ";
5868	case 15: return "fully ";
5869	default: return "????";
5870	}
5871	}
5872
5873
5874	/** CPUID(1).EDX field descriptions. */
5875	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
5876	{
5877	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5878	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5879	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5880	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5881	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5882	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
5883	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5884	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5885	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5886	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5887	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
5888	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5889	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5890	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5891	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5892	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5893	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5894	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
5895	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
5896	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
5897	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
5898	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5899	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
5900	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
5901	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
5902	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
5903	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
5904	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
5905	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
5906	DBGFREGSUBFIELD_TERMINATOR()
5907	};
5908
5909	/** CPUID(1).ECX field descriptions. */
5910	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
5911	{
5912	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
5913	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
5914	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
5915	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
5916	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
5917	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
5918	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
5919	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
5920	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
5921	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
5922	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
5923	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
5924	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
5925	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
5926	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
5927	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
5928	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
5929	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
5930	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
5931	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
5932	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
5933	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
5934	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
5935	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
5936	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
5937	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
5938	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
5939	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
5940	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
5941	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
5942	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
5943	DBGFREGSUBFIELD_TERMINATOR()
5944	};
5945
5946	/** CPUID(7,0).EBX field descriptions. */
5947	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
5948	{
5949	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
5950	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
5951	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
5952	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
5953	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
5954	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
5955	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
5956	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
5957	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
5958	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
5959	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
5960	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
5961	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
5962	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
5963	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
5964	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
5965	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
5966	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
5967	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
5968	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
5969	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
5970	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
5971	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
5972	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
5973	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
5974	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
5975	DBGFREGSUBFIELD_TERMINATOR()
5976	};
5977
5978	/** CPUID(7,0).ECX field descriptions. */
5979	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
5980	{
5981	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
5982	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
5983	DBGFREGSUBFIELD_RO("OSPKU\0" "CR4.PKU mirror", 4, 1, 0),
5984	DBGFREGSUBFIELD_TERMINATOR()
5985	};
5986
5987
5988	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
5989	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
5990	{
5991	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
5992	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
5993	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
5994	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
5995	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
5996	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
5997	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
5998	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
5999	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6000	DBGFREGSUBFIELD_TERMINATOR()
6001	};
6002
6003	/** CPUID(13,1).EAX field descriptions. */
6004	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6005	{
6006	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6007	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6008	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6009	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6010	DBGFREGSUBFIELD_TERMINATOR()
6011	};
6012
6013
6014	/** CPUID(0x80000001,0).EDX field descriptions. */
6015	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6016	{
6017	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6018	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6019	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6020	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6021	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6022	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6023	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6024	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6025	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6026	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6027	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6028	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6029	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6030	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6031	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6032	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6033	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6034	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6035	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6036	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6037	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6038	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6039	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6040	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6041	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6042	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6043	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6044	DBGFREGSUBFIELD_TERMINATOR()
6045	};
6046
6047	/** CPUID(0x80000001,0).ECX field descriptions. */
6048	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6049	{
6050	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6051	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6052	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6053	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6054	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6055	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6056	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6057	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6058	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6059	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6060	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6061	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6062	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6063	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6064	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6065	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6066	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6067	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6068	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6069	DBGFREGSUBFIELD_TERMINATOR()
6070	};
6071
6072
6073	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6074	const char *pszLeadIn, uint32_t cchWidth)
6075	{
6076	if (pszLeadIn)
6077	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6078
6079	for (uint32_t iBit = 0; iBit < 32; iBit++)
6080	if (RT_BIT_32(iBit) & uVal)
6081	{
6082	while ( pDesc->pszName != NULL
6083	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6084	pDesc++;
6085	if ( pDesc->pszName != NULL
6086	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6087	{
6088	if (pDesc->cBits == 1)
6089	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6090	else
6091	{
6092	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6093	if (pDesc->cBits < 32)
6094	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6095	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6096	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6097	}
6098	}
6099	else
6100	pHlp->pfnPrintf(pHlp, " %u", iBit);
6101	}
6102	if (pszLeadIn)
6103	pHlp->pfnPrintf(pHlp, "\n");
6104	}
6105
6106
6107	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6108	const char *pszLeadIn, uint32_t cchWidth)
6109	{
6110	if (pszLeadIn)
6111	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6112
6113	for (uint32_t iBit = 0; iBit < 64; iBit++)
6114	if (RT_BIT_64(iBit) & uVal)
6115	{
6116	while ( pDesc->pszName != NULL
6117	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6118	pDesc++;
6119	if ( pDesc->pszName != NULL
6120	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6121	{
6122	if (pDesc->cBits == 1)
6123	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6124	else
6125	{
6126	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6127	if (pDesc->cBits < 64)
6128	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6129	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6130	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6131	}
6132	}
6133	else
6134	pHlp->pfnPrintf(pHlp, " %u", iBit);
6135	}
6136	if (pszLeadIn)
6137	pHlp->pfnPrintf(pHlp, "\n");
6138	}
6139
6140
6141	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6142	const char *pszLeadIn, uint32_t cchWidth)
6143	{
6144	if (!uVal)
6145	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6146	else
6147	{
6148	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6149	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6150	pHlp->pfnPrintf(pHlp, " )\n");
6151	}
6152	}
6153
6154
6155	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6156	uint32_t cchWidth)
6157	{
6158	uint32_t uCombined = uVal1 \| uVal2;
6159	for (uint32_t iBit = 0; iBit < 32; iBit++)
6160	if ( (RT_BIT_32(iBit) & uCombined)
6161	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6162	{
6163	while ( pDesc->pszName != NULL
6164	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6165	pDesc++;
6166
6167	if ( pDesc->pszName != NULL
6168	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6169	{
6170	size_t cchMnemonic = strlen(pDesc->pszName);
6171	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6172	size_t cchDesc = strlen(pszDesc);
6173	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6174	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6175	if (pDesc->cBits < 32)
6176	{
6177	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6178	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6179	}
6180
6181	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6182	pDesc->pszName, pszDesc,
6183	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6184	uFieldValue1, uFieldValue2);
6185
6186	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6187	pDesc++;
6188	}
6189	else
6190	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6191	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6192	}
6193	}
6194
6195
6196	/**
6197	* Produces a detailed summary of standard leaf 0x00000001.
6198	*
6199	* @param pHlp The info helper functions.
6200	* @param pCurLeaf The 0x00000001 leaf.
6201	* @param fVerbose Whether to be very verbose or not.
6202	* @param fIntel Set if intel CPU.
6203	*/
6204	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6205	{
6206	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6207	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6208	uint32_t uEAX = pCurLeaf->uEax;
6209	uint32_t uEBX = pCurLeaf->uEbx;
6210
6211	pHlp->pfnPrintf(pHlp,
6212	"%36s %2d \tExtended: %d \tEffective: %d\n"
6213	"%36s %2d \tExtended: %d \tEffective: %d\n"
6214	"%36s %d\n"
6215	"%36s %d (%s)\n"
6216	"%36s %#04x\n"
6217	"%36s %d\n"
6218	"%36s %d\n"
6219	"%36s %#04x\n"
6220	,
6221	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6222	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6223	"Stepping:", ASMGetCpuStepping(uEAX),
6224	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6225	"APIC ID:", (uEBX >> 24) & 0xff,
6226	"Logical CPUs:",(uEBX >> 16) & 0xff,
6227	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6228	"Brand ID:", (uEBX >> 0) & 0xff);
6229	if (fVerbose)
6230	{
6231	CPUMCPUID Host;
6232	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6233	pHlp->pfnPrintf(pHlp, "Features\n");
6234	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6235	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6236	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6237	}
6238	else
6239	{
6240	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6241	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6242	}
6243	}
6244
6245
6246	/**
6247	* Produces a detailed summary of standard leaf 0x00000007.
6248	*
6249	* @param pHlp The info helper functions.
6250	* @param paLeaves The CPUID leaves array.
6251	* @param cLeaves The number of leaves in the array.
6252	* @param pCurLeaf The first 0x00000007 leaf.
6253	* @param fVerbose Whether to be very verbose or not.
6254	*/
6255	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6256	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6257	{
6258	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6259	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6260	for (;;)
6261	{
6262	CPUMCPUID Host;
6263	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6264
6265	switch (pCurLeaf->uSubLeaf)
6266	{
6267	case 0:
6268	if (fVerbose)
6269	{
6270	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6271	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6272	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6273	if (pCurLeaf->uEdx \|\| Host.uEdx)
6274	pHlp->pfnPrintf(pHlp, "%36 %#x (%#x)\n", "Ext Features EDX:", pCurLeaf->uEdx, Host.uEdx);
6275	}
6276	else
6277	{
6278	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6279	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6280	if (pCurLeaf->uEdx)
6281	pHlp->pfnPrintf(pHlp, "%36 %#x\n", "Ext Features EDX:", pCurLeaf->uEdx);
6282	}
6283	break;
6284
6285	default:
6286	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6287	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6288	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6289	break;
6290
6291	}
6292
6293	/* advance. */
6294	pCurLeaf++;
6295	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6296	\|\| pCurLeaf->uLeaf != 0x7)
6297	break;
6298	}
6299	}
6300
6301
6302	/**
6303	* Produces a detailed summary of standard leaf 0x0000000d.
6304	*
6305	* @param pHlp The info helper functions.
6306	* @param paLeaves The CPUID leaves array.
6307	* @param cLeaves The number of leaves in the array.
6308	* @param pCurLeaf The first 0x00000007 leaf.
6309	* @param fVerbose Whether to be very verbose or not.
6310	*/
6311	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6312	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6313	{
6314	RT_NOREF_PV(fVerbose);
6315	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6316	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6317	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6318	{
6319	CPUMCPUID Host;
6320	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6321
6322	switch (uSubLeaf)
6323	{
6324	case 0:
6325	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6326	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6327	pCurLeaf->uEbx, pCurLeaf->uEcx);
6328	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6329
6330	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6331	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6332	"Valid XCR0 bits, guest:", 42);
6333	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6334	"Valid XCR0 bits, host:", 42);
6335	break;
6336
6337	case 1:
6338	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6339	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6340	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6341
6342	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6343	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6344	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6345
6346	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6347	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6348	" Valid IA32_XSS bits, guest:", 42);
6349	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6350	" Valid IA32_XSS bits, host:", 42);
6351	break;
6352
6353	default:
6354	if ( pCurLeaf
6355	&& pCurLeaf->uSubLeaf == uSubLeaf
6356	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6357	{
6358	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6359	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6360	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6361	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6362	if (pCurLeaf->uEdx)
6363	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6364	pHlp->pfnPrintf(pHlp, " --");
6365	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6366	pHlp->pfnPrintf(pHlp, "\n");
6367	}
6368	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6369	{
6370	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6371	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6372	if (Host.uEcx & ~RT_BIT_32(0))
6373	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6374	if (Host.uEdx)
6375	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6376	pHlp->pfnPrintf(pHlp, " --");
6377	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6378	pHlp->pfnPrintf(pHlp, "\n");
6379	}
6380	break;
6381
6382	}
6383
6384	/* advance. */
6385	if (pCurLeaf)
6386	{
6387	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6388	&& pCurLeaf->uSubLeaf <= uSubLeaf
6389	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6390	pCurLeaf++;
6391	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6392	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6393	pCurLeaf = NULL;
6394	}
6395	}
6396	}
6397
6398
6399	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6400	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6401	{
6402	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6403	&& pCurLeaf->uLeaf <= uUpToLeaf)
6404	{
6405	pHlp->pfnPrintf(pHlp,
6406	" %s\n"
6407	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6408	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6409	&& pCurLeaf->uLeaf <= uUpToLeaf)
6410	{
6411	CPUMCPUID Host;
6412	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6413	pHlp->pfnPrintf(pHlp,
6414	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6415	"Hst: %08x %08x %08x %08x\n",
6416	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6417	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6418	pCurLeaf++;
6419	}
6420	}
6421
6422	return pCurLeaf;
6423	}
6424
6425
6426	/**
6427	* Display the guest CpuId leaves.
6428	*
6429	* @param pVM The cross context VM structure.
6430	* @param pHlp The info helper functions.
6431	* @param pszArgs "terse", "default" or "verbose".
6432	*/
6433	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6434	{
6435	/*
6436	* Parse the argument.
6437	*/
6438	unsigned iVerbosity = 1;
6439	if (pszArgs)
6440	{
6441	pszArgs = RTStrStripL(pszArgs);
6442	if (!strcmp(pszArgs, "terse"))
6443	iVerbosity--;
6444	else if (!strcmp(pszArgs, "verbose"))
6445	iVerbosity++;
6446	}
6447
6448	uint32_t uLeaf;
6449	CPUMCPUID Host;
6450	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6451	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6452	PCCPUMCPUIDLEAF pCurLeaf;
6453	PCCPUMCPUIDLEAF pNextLeaf;
6454	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6455	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6456	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6457
6458	/*
6459	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6460	*/
6461	uint32_t cHstMax = ASMCpuId_EAX(0);
6462	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6463	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6464	pHlp->pfnPrintf(pHlp,
6465	" Raw Standard CPUID Leaves\n"
6466	" Leaf/sub-leaf eax ebx ecx edx\n");
6467	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6468	{
6469	uint32_t cMaxSubLeaves = 1;
6470	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6471	cMaxSubLeaves = 16;
6472	else if (uLeaf == 0xd)
6473	cMaxSubLeaves = 128;
6474
6475	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6476	{
6477	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6478	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6479	&& pCurLeaf->uLeaf == uLeaf
6480	&& pCurLeaf->uSubLeaf == uSubLeaf)
6481	{
6482	pHlp->pfnPrintf(pHlp,
6483	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6484	"Hst: %08x %08x %08x %08x\n",
6485	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6486	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6487	pCurLeaf++;
6488	}
6489	else if ( uLeaf != 0xd
6490	\|\| uSubLeaf <= 1
6491	\|\| Host.uEbx != 0 )
6492	pHlp->pfnPrintf(pHlp,
6493	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6494	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6495
6496	/* Done? */
6497	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6498	\|\| pCurLeaf->uLeaf != uLeaf)
6499	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6500	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6501	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6502	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6503	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6504	)
6505	)
6506	break;
6507	}
6508	}
6509	pNextLeaf = pCurLeaf;
6510
6511	/*
6512	* If verbose, decode it.
6513	*/
6514	if (iVerbosity && paLeaves[0].uLeaf == 0)
6515	pHlp->pfnPrintf(pHlp,
6516	"%36s %.04s%.04s%.04s\n"
6517	"%36s 0x00000000-%#010x\n"
6518	,
6519	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6520	"Supports:", paLeaves[0].uEax);
6521
6522	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6523	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6524
6525	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6526	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6527
6528	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6529	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6530
6531	pCurLeaf = pNextLeaf;
6532
6533	/*
6534	* Hypervisor leaves.
6535	*
6536	* Unlike most of the other leaves reported, the guest hypervisor leaves
6537	* aren't a subset of the host CPUID bits.
6538	*/
6539	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6540
6541	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6542	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6543	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6544	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6545	cMax = RT_MAX(cHstMax, cGstMax);
6546	if (cMax >= UINT32_C(0x40000000))
6547	{
6548	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6549
6550	/** @todo dump these in more detail. */
6551
6552	pCurLeaf = pNextLeaf;
6553	}
6554
6555
6556	/*
6557	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6558	* Implemented after AMD specs.
6559	*/
6560	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6561
6562	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6563	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6564	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6565	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6566	cMax = RT_MAX(cHstMax, cGstMax);
6567	if (cMax >= UINT32_C(0x80000000))
6568	{
6569
6570	pHlp->pfnPrintf(pHlp,
6571	" Raw Extended CPUID Leaves\n"
6572	" Leaf/sub-leaf eax ebx ecx edx\n");
6573	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6574	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6575	{
6576	uint32_t cMaxSubLeaves = 1;
6577	if (uLeaf == UINT32_C(0x8000001d))
6578	cMaxSubLeaves = 16;
6579
6580	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6581	{
6582	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6583	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6584	&& pCurLeaf->uLeaf == uLeaf
6585	&& pCurLeaf->uSubLeaf == uSubLeaf)
6586	{
6587	pHlp->pfnPrintf(pHlp,
6588	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6589	"Hst: %08x %08x %08x %08x\n",
6590	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6591	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6592	pCurLeaf++;
6593	}
6594	else if ( uLeaf != 0xd
6595	\|\| uSubLeaf <= 1
6596	\|\| Host.uEbx != 0 )
6597	pHlp->pfnPrintf(pHlp,
6598	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6599	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6600
6601	/* Done? */
6602	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6603	\|\| pCurLeaf->uLeaf != uLeaf)
6604	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6605	break;
6606	}
6607	}
6608	pNextLeaf = pCurLeaf;
6609
6610	/*
6611	* Understandable output
6612	*/
6613	if (iVerbosity)
6614	pHlp->pfnPrintf(pHlp,
6615	"Ext Name: %.4s%.4s%.4s\n"
6616	"Ext Supports: 0x80000000-%#010x\n",
6617	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6618
6619	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6620	if (iVerbosity && pCurLeaf)
6621	{
6622	uint32_t uEAX = pCurLeaf->uEax;
6623	pHlp->pfnPrintf(pHlp,
6624	"Family: %d \tExtended: %d \tEffective: %d\n"
6625	"Model: %d \tExtended: %d \tEffective: %d\n"
6626	"Stepping: %d\n"
6627	"Brand ID: %#05x\n",
6628	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6629	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6630	ASMGetCpuStepping(uEAX),
6631	pCurLeaf->uEbx & 0xfff);
6632
6633	if (iVerbosity == 1)
6634	{
6635	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6636	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6637	}
6638	else
6639	{
6640	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6641	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6642	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6643	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6644	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6645	}
6646	}
6647
6648	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6649	{
6650	char szString[443+1] = {0};
6651	uint32_t pu32 = (uint32_t )szString;
6652	*pu32++ = pCurLeaf->uEax;
6653	*pu32++ = pCurLeaf->uEbx;
6654	*pu32++ = pCurLeaf->uEcx;
6655	*pu32++ = pCurLeaf->uEdx;
6656	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6657	if (pCurLeaf)
6658	{
6659	*pu32++ = pCurLeaf->uEax;
6660	*pu32++ = pCurLeaf->uEbx;
6661	*pu32++ = pCurLeaf->uEcx;
6662	*pu32++ = pCurLeaf->uEdx;
6663	}
6664	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6665	if (pCurLeaf)
6666	{
6667	*pu32++ = pCurLeaf->uEax;
6668	*pu32++ = pCurLeaf->uEbx;
6669	*pu32++ = pCurLeaf->uEcx;
6670	*pu32++ = pCurLeaf->uEdx;
6671	}
6672	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6673	}
6674
6675	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6676	{
6677	uint32_t uEAX = pCurLeaf->uEax;
6678	uint32_t uEBX = pCurLeaf->uEbx;
6679	uint32_t uECX = pCurLeaf->uEcx;
6680	uint32_t uEDX = pCurLeaf->uEdx;
6681	char sz1[32];
6682	char sz2[32];
6683
6684	pHlp->pfnPrintf(pHlp,
6685	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6686	"TLB 2/4M Data: %s %3d entries\n",
6687	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6688	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6689	pHlp->pfnPrintf(pHlp,
6690	"TLB 4K Instr/Uni: %s %3d entries\n"
6691	"TLB 4K Data: %s %3d entries\n",
6692	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6693	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6694	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6695	"L1 Instr Cache Lines Per Tag: %d\n"
6696	"L1 Instr Cache Associativity: %s\n"
6697	"L1 Instr Cache Size: %d KB\n",
6698	(uEDX >> 0) & 0xff,
6699	(uEDX >> 8) & 0xff,
6700	getCacheAss((uEDX >> 16) & 0xff, sz1),
6701	(uEDX >> 24) & 0xff);
6702	pHlp->pfnPrintf(pHlp,
6703	"L1 Data Cache Line Size: %d bytes\n"
6704	"L1 Data Cache Lines Per Tag: %d\n"
6705	"L1 Data Cache Associativity: %s\n"
6706	"L1 Data Cache Size: %d KB\n",
6707	(uECX >> 0) & 0xff,
6708	(uECX >> 8) & 0xff,
6709	getCacheAss((uECX >> 16) & 0xff, sz1),
6710	(uECX >> 24) & 0xff);
6711	}
6712
6713	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6714	{
6715	uint32_t uEAX = pCurLeaf->uEax;
6716	uint32_t uEBX = pCurLeaf->uEbx;
6717	uint32_t uEDX = pCurLeaf->uEdx;
6718
6719	pHlp->pfnPrintf(pHlp,
6720	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6721	"L2 TLB 2/4M Data: %s %4d entries\n",
6722	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6723	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6724	pHlp->pfnPrintf(pHlp,
6725	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6726	"L2 TLB 4K Data: %s %4d entries\n",
6727	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6728	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6729	pHlp->pfnPrintf(pHlp,
6730	"L2 Cache Line Size: %d bytes\n"
6731	"L2 Cache Lines Per Tag: %d\n"
6732	"L2 Cache Associativity: %s\n"
6733	"L2 Cache Size: %d KB\n",
6734	(uEDX >> 0) & 0xff,
6735	(uEDX >> 8) & 0xf,
6736	getL2CacheAss((uEDX >> 12) & 0xf),
6737	(uEDX >> 16) & 0xffff);
6738	}
6739
6740	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
6741	{
6742	uint32_t uEDX = pCurLeaf->uEdx;
6743
6744	pHlp->pfnPrintf(pHlp, "APM Features: ");
6745	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
6746	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
6747	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
6748	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
6749	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
6750	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
6751	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " MC");
6752	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " HWPSTATE");
6753	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TscInvariant");
6754	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " CPB");
6755	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " EffFreqRO");
6756	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PFI");
6757	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PA");
6758	for (unsigned iBit = 13; iBit < 32; iBit++)
6759	if (uEDX & RT_BIT(iBit))
6760	pHlp->pfnPrintf(pHlp, " %d", iBit);
6761	pHlp->pfnPrintf(pHlp, "\n");
6762
6763	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6764	pHlp->pfnPrintf(pHlp, "Host Invariant-TSC support: %RTbool\n",
6765	cHstMax >= UINT32_C(0x80000007) && (Host.uEdx & RT_BIT(8)));
6766
6767	}
6768
6769	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0)) != NULL)
6770	{
6771	uint32_t uEAX = pCurLeaf->uEax;
6772	uint32_t uECX = pCurLeaf->uEcx;
6773
6774	pHlp->pfnPrintf(pHlp,
6775	"Physical Address Width: %d bits\n"
6776	"Virtual Address Width: %d bits\n"
6777	"Guest Physical Address Width: %d bits\n",
6778	(uEAX >> 0) & 0xff,
6779	(uEAX >> 8) & 0xff,
6780	(uEAX >> 16) & 0xff);
6781	pHlp->pfnPrintf(pHlp,
6782	"Physical Core Count: %d\n",
6783	((uECX >> 0) & 0xff) + 1);
6784	}
6785
6786	pCurLeaf = pNextLeaf;
6787	}
6788
6789
6790
6791	/*
6792	* Centaur.
6793	*/
6794	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
6795
6796	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6797	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
6798	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
6799	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
6800	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
6801	cMax = RT_MAX(cHstMax, cGstMax);
6802	if (cMax >= UINT32_C(0xc0000000))
6803	{
6804	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
6805
6806	/*
6807	* Understandable output
6808	*/
6809	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
6810	pHlp->pfnPrintf(pHlp,
6811	"Centaur Supports: 0xc0000000-%#010x\n",
6812	pCurLeaf->uEax);
6813
6814	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
6815	{
6816	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6817	uint32_t uEdxGst = pCurLeaf->uEdx;
6818	uint32_t uEdxHst = Host.uEdx;
6819
6820	if (iVerbosity == 1)
6821	{
6822	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
6823	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
6824	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
6825	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
6826	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
6827	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
6828	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
6829	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
6830	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
6831	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6832	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
6833	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
6834	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
6835	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
6836	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
6837	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
6838	for (unsigned iBit = 14; iBit < 32; iBit++)
6839	if (uEdxGst & RT_BIT(iBit))
6840	pHlp->pfnPrintf(pHlp, " %d", iBit);
6841	pHlp->pfnPrintf(pHlp, "\n");
6842	}
6843	else
6844	{
6845	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
6846	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
6847	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
6848	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
6849	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
6850	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
6851	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
6852	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
6853	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
6854	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6855	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
6856	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
6857	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
6858	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
6859	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
6860	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
6861	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
6862	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
6863	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
6864	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
6865	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
6866	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
6867	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
6868	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
6869	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
6870	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
6871	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
6872	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
6873	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
6874	for (unsigned iBit = 27; iBit < 32; iBit++)
6875	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
6876	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
6877	pHlp->pfnPrintf(pHlp, "\n");
6878	}
6879	}
6880
6881	pCurLeaf = pNextLeaf;
6882	}
6883
6884	/*
6885	* The remainder.
6886	*/
6887	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
6888	}
6889
6890
6891
6892
6893
6894	/*
6895	*
6896	*
6897	* PATM interfaces.
6898	* PATM interfaces.
6899	* PATM interfaces.
6900	*
6901	*
6902	*/
6903
6904
6905	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
6906	/** @name Patchmanager CPUID legacy table APIs
6907	* @{
6908	*/
6909
6910	/**
6911	* Gets a pointer to the default CPUID leaf.
6912	*
6913	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
6914	* @param pVM The cross context VM structure.
6915	* @remark Intended for PATM only.
6916	*/
6917	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
6918	{
6919	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
6920	}
6921
6922
6923	/**
6924	* Gets a number of standard CPUID leaves (PATM only).
6925	*
6926	* @returns Number of leaves.
6927	* @param pVM The cross context VM structure.
6928	* @remark Intended for PATM - legacy, don't use in new code.
6929	*/
6930	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
6931	{
6932	RT_NOREF_PV(pVM);
6933	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
6934	}
6935
6936
6937	/**
6938	* Gets a number of extended CPUID leaves (PATM only).
6939	*
6940	* @returns Number of leaves.
6941	* @param pVM The cross context VM structure.
6942	* @remark Intended for PATM - legacy, don't use in new code.
6943	*/
6944	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
6945	{
6946	RT_NOREF_PV(pVM);
6947	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
6948	}
6949
6950
6951	/**
6952	* Gets a number of centaur CPUID leaves.
6953	*
6954	* @returns Number of leaves.
6955	* @param pVM The cross context VM structure.
6956	* @remark Intended for PATM - legacy, don't use in new code.
6957	*/
6958	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
6959	{
6960	RT_NOREF_PV(pVM);
6961	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
6962	}
6963
6964
6965	/**
6966	* Gets a pointer to the array of standard CPUID leaves.
6967	*
6968	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
6969	*
6970	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
6971	* @param pVM The cross context VM structure.
6972	* @remark Intended for PATM - legacy, don't use in new code.
6973	*/
6974	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
6975	{
6976	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
6977	}
6978
6979
6980	/**
6981	* Gets a pointer to the array of extended CPUID leaves.
6982	*
6983	* CPUMGetGuestCpuIdExtMax() give the size of the array.
6984	*
6985	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
6986	* @param pVM The cross context VM structure.
6987	* @remark Intended for PATM - legacy, don't use in new code.
6988	*/
6989	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
6990	{
6991	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
6992	}
6993
6994
6995	/**
6996	* Gets a pointer to the array of centaur CPUID leaves.
6997	*
6998	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
6999	*
7000	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
7001	* @param pVM The cross context VM structure.
7002	* @remark Intended for PATM - legacy, don't use in new code.
7003	*/
7004	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
7005	{
7006	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
7007	}
7008
7009	/** @} */
7010	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
7011
7012	#endif /* VBOX_IN_VMM */
7013

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 70450

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