CPUMR3CpuId.cpp@ 70720

Last change on this file since 70720 was 70720, checked in by vboxsync, 7 years ago
VMM/CPUM: Nested Hw.virt: Log when nested hw.virt is disabled when the VM doesn't have nested-paging or unrestricted guest exec. enabled.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 328.1 KB

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1	/* $Id: CPUMR3CpuId.cpp 70720 2018-01-24 04:47:50Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/ssm.h>
27	#include "CPUMInternal.h"
28	#include <VBox/vmm/vm.h>
29	#include <VBox/vmm/mm.h>
30	#include <VBox/sup.h>
31
32	#include <VBox/err.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/ctype.h>
35	#include <iprt/mem.h>
36	#include <iprt/string.h>
37
38
39	/*********************************************************************************************************************************
40	* Defined Constants And Macros *
41	*********************************************************************************************************************************/
42	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
43	#define CPUM_CPUID_MAX_LEAVES 2048
44	/* Max size we accept for the XSAVE area. */
45	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
46	/* Min size we accept for the XSAVE area. */
47	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
48
49
50	/*********************************************************************************************************************************
51	* Global Variables *
52	*********************************************************************************************************************************/
53	/**
54	* The intel pentium family.
55	*/
56	static const CPUMMICROARCH g_aenmIntelFamily06[] =
57	{
58	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
59	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
60	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
61	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
62	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
63	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
64	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
65	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
66	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
67	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
68	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
69	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
70	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
71	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
72	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
73	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
74	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
80	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
81	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
82	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
83	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
85	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
86	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
87	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
88	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
89	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
90	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
91	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
96	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
97	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
98	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
99	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
101	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
102	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
103	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
104	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
105	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
106	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
107	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
112	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
113	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
114	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
115	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
117	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
118	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
119	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
120	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
121	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
122	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
123	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
128	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
130	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
131	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
133	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
134	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
135	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
136	/* [78(0x4e)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed */
137	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / unconfirmed, Broadwell-E */
138	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
139	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu */
144	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
145	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
146	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
147	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
149	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
150	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
151	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
152	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
153	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
154	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
155	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
158	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
159	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
160	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
161	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
162	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
163	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
164	/[106(0x6a)] = / kCpumMicroarch_Intel_Unknown,
165	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
166	/[108(0x6c)] = / kCpumMicroarch_Intel_Unknown,
167	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
168	/[110(0x6e)] = / kCpumMicroarch_Intel_Unknown,
169	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
170	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
171	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
172	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
173	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
174	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
175	/[117(0x75)] = / kCpumMicroarch_Intel_Unknown,
176	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
177	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
178	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
179	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
180	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
181	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
182	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
183	/[125(0x7d)] = / kCpumMicroarch_Intel_Unknown,
184	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
185	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
186	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
187	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
188	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
189	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
190	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
191	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
192	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
193	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
194	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
195	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
196	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
197	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
198	/[140(0x8c)] = / kCpumMicroarch_Intel_Unknown,
199	/[141(0x8d)] = / kCpumMicroarch_Intel_Unknown,
200	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
201	/[143(0x8f)] = / kCpumMicroarch_Intel_Unknown,
202	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
203	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
204	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
205	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
206	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
207	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
208	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
209	/[151(0x97)] = / kCpumMicroarch_Intel_Unknown,
210	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
211	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
212	/[154(0x9a)] = / kCpumMicroarch_Intel_Unknown,
213	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
214	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
215	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
216	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
217	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
218	};
219	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0x9f+1);
220
221
222	/**
223	* Figures out the (sub-)micro architecture given a bit of CPUID info.
224	*
225	* @returns Micro architecture.
226	* @param enmVendor The CPU vendor .
227	* @param bFamily The CPU family.
228	* @param bModel The CPU model.
229	* @param bStepping The CPU stepping.
230	*/
231	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
232	uint8_t bModel, uint8_t bStepping)
233	{
234	if (enmVendor == CPUMCPUVENDOR_AMD)
235	{
236	switch (bFamily)
237	{
238	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
239	case 0x03: return kCpumMicroarch_AMD_Am386;
240	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
241	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
242	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
243	case 0x06:
244	switch (bModel)
245	{
246	case 0: return kCpumMicroarch_AMD_K7_Palomino;
247	case 1: return kCpumMicroarch_AMD_K7_Palomino;
248	case 2: return kCpumMicroarch_AMD_K7_Palomino;
249	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
250	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
251	case 6: return kCpumMicroarch_AMD_K7_Palomino;
252	case 7: return kCpumMicroarch_AMD_K7_Morgan;
253	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
254	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
255	}
256	return kCpumMicroarch_AMD_K7_Unknown;
257	case 0x0f:
258	/*
259	* This family is a friggin mess. Trying my best to make some
260	* sense out of it. Too much happened in the 0x0f family to
261	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
262	*
263	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
264	* cpu-world.com, and other places:
265	* - 130nm:
266	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
267	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
268	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
269	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
270	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
271	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
272	* - 90nm:
273	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
274	* - Oakville: 10FC0/DH-D0.
275	* - Georgetown: 10FC0/DH-D0.
276	* - Sonora: 10FC0/DH-D0.
277	* - Venus: 20F71/SH-E4
278	* - Troy: 20F51/SH-E4
279	* - Athens: 20F51/SH-E4
280	* - San Diego: 20F71/SH-E4.
281	* - Lancaster: 20F42/SH-E5
282	* - Newark: 20F42/SH-E5.
283	* - Albany: 20FC2/DH-E6.
284	* - Roma: 20FC2/DH-E6.
285	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
286	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
287	* - 90nm introducing Dual core:
288	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
289	* - Italy: 20F10/JH-E1, 20F12/JH-E6
290	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
291	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
292	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
293	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
294	* - Santa Ana: 40F32/JH-F2, /-F3
295	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
296	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
297	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
298	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
299	* - Keene: 40FC2/DH-F2.
300	* - Richmond: 40FC2/DH-F2
301	* - Taylor: 40F82/BH-F2
302	* - Trinidad: 40F82/BH-F2
303	*
304	* - 65nm:
305	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
306	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
307	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
308	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
309	* - Sherman: /-G1, 70FC2/DH-G2.
310	* - Huron: 70FF2/DH-G2.
311	*/
312	if (bModel < 0x10)
313	return kCpumMicroarch_AMD_K8_130nm;
314	if (bModel >= 0x60 && bModel < 0x80)
315	return kCpumMicroarch_AMD_K8_65nm;
316	if (bModel >= 0x40)
317	return kCpumMicroarch_AMD_K8_90nm_AMDV;
318	switch (bModel)
319	{
320	case 0x21:
321	case 0x23:
322	case 0x2b:
323	case 0x2f:
324	case 0x37:
325	case 0x3f:
326	return kCpumMicroarch_AMD_K8_90nm_DualCore;
327	}
328	return kCpumMicroarch_AMD_K8_90nm;
329	case 0x10:
330	return kCpumMicroarch_AMD_K10;
331	case 0x11:
332	return kCpumMicroarch_AMD_K10_Lion;
333	case 0x12:
334	return kCpumMicroarch_AMD_K10_Llano;
335	case 0x14:
336	return kCpumMicroarch_AMD_Bobcat;
337	case 0x15:
338	switch (bModel)
339	{
340	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
341	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
342	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
343	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
344	case 0x11: /* ?? */
345	case 0x12: /* ?? */
346	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
347	}
348	return kCpumMicroarch_AMD_15h_Unknown;
349	case 0x16:
350	return kCpumMicroarch_AMD_Jaguar;
351	case 0x17:
352	return kCpumMicroarch_AMD_Zen_Ryzen;
353	}
354	return kCpumMicroarch_AMD_Unknown;
355	}
356
357	if (enmVendor == CPUMCPUVENDOR_INTEL)
358	{
359	switch (bFamily)
360	{
361	case 3:
362	return kCpumMicroarch_Intel_80386;
363	case 4:
364	return kCpumMicroarch_Intel_80486;
365	case 5:
366	return kCpumMicroarch_Intel_P5;
367	case 6:
368	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
369	{
370	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
371	if ( enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake
372	&& bStepping >= 0xa)
373	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
374	return enmMicroArch;
375	}
376	return kCpumMicroarch_Intel_Atom_Unknown;
377	case 15:
378	switch (bModel)
379	{
380	case 0: return kCpumMicroarch_Intel_NB_Willamette;
381	case 1: return kCpumMicroarch_Intel_NB_Willamette;
382	case 2: return kCpumMicroarch_Intel_NB_Northwood;
383	case 3: return kCpumMicroarch_Intel_NB_Prescott;
384	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
385	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
386	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
387	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
388	default: return kCpumMicroarch_Intel_NB_Unknown;
389	}
390	break;
391	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
392	case 0:
393	return kCpumMicroarch_Intel_8086;
394	case 1:
395	return kCpumMicroarch_Intel_80186;
396	case 2:
397	return kCpumMicroarch_Intel_80286;
398	}
399	return kCpumMicroarch_Intel_Unknown;
400	}
401
402	if (enmVendor == CPUMCPUVENDOR_VIA)
403	{
404	switch (bFamily)
405	{
406	case 5:
407	switch (bModel)
408	{
409	case 1: return kCpumMicroarch_Centaur_C6;
410	case 4: return kCpumMicroarch_Centaur_C6;
411	case 8: return kCpumMicroarch_Centaur_C2;
412	case 9: return kCpumMicroarch_Centaur_C3;
413	}
414	break;
415
416	case 6:
417	switch (bModel)
418	{
419	case 5: return kCpumMicroarch_VIA_C3_M2;
420	case 6: return kCpumMicroarch_VIA_C3_C5A;
421	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
422	case 8: return kCpumMicroarch_VIA_C3_C5N;
423	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
424	case 10: return kCpumMicroarch_VIA_C7_C5J;
425	case 15: return kCpumMicroarch_VIA_Isaiah;
426	}
427	break;
428	}
429	return kCpumMicroarch_VIA_Unknown;
430	}
431
432	if (enmVendor == CPUMCPUVENDOR_CYRIX)
433	{
434	switch (bFamily)
435	{
436	case 4:
437	switch (bModel)
438	{
439	case 9: return kCpumMicroarch_Cyrix_5x86;
440	}
441	break;
442
443	case 5:
444	switch (bModel)
445	{
446	case 2: return kCpumMicroarch_Cyrix_M1;
447	case 4: return kCpumMicroarch_Cyrix_MediaGX;
448	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
449	}
450	break;
451
452	case 6:
453	switch (bModel)
454	{
455	case 0: return kCpumMicroarch_Cyrix_M2;
456	}
457	break;
458
459	}
460	return kCpumMicroarch_Cyrix_Unknown;
461	}
462
463	return kCpumMicroarch_Unknown;
464	}
465
466
467	/**
468	* Translates a microarchitecture enum value to the corresponding string
469	* constant.
470	*
471	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
472	* NULL if the value is invalid.
473	*
474	* @param enmMicroarch The enum value to convert.
475	*/
476	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
477	{
478	switch (enmMicroarch)
479	{
480	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
481	CASE_RET_STR(kCpumMicroarch_Intel_8086);
482	CASE_RET_STR(kCpumMicroarch_Intel_80186);
483	CASE_RET_STR(kCpumMicroarch_Intel_80286);
484	CASE_RET_STR(kCpumMicroarch_Intel_80386);
485	CASE_RET_STR(kCpumMicroarch_Intel_80486);
486	CASE_RET_STR(kCpumMicroarch_Intel_P5);
487
488	CASE_RET_STR(kCpumMicroarch_Intel_P6);
489	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
490	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
491
492	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
493	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
494	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
495
496	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
497	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
498
499	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
500	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
501	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
502	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
503	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
504	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
505	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
506	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
507	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
508	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
509	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
510	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
511
512	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
513	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
514	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
515	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
516	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
517	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
518	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
519	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
520
521	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
522	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
523	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
524	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
525	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
526
527	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
528	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
529	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
530	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
531	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
532	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
533	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
534
535	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
536
537	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
538	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
539	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
540	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
541	CASE_RET_STR(kCpumMicroarch_AMD_K5);
542	CASE_RET_STR(kCpumMicroarch_AMD_K6);
543
544	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
545	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
546	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
547	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
548	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
549	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
550	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
551
552	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
553	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
554	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
555	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
556	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
557
558	CASE_RET_STR(kCpumMicroarch_AMD_K10);
559	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
560	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
561	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
562	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
563
564	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
565	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
566	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
567	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
568	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
569
570	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
571
572	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
573
574	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
575
576	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
577	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
578	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
579	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
580	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
581	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
582	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
583	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
584	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
585	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
586	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
587	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
588	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
589
590	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
591	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
592	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
593	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
594	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
595	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
596
597	CASE_RET_STR(kCpumMicroarch_NEC_V20);
598	CASE_RET_STR(kCpumMicroarch_NEC_V30);
599
600	CASE_RET_STR(kCpumMicroarch_Unknown);
601
602	#undef CASE_RET_STR
603	case kCpumMicroarch_Invalid:
604	case kCpumMicroarch_Intel_End:
605	case kCpumMicroarch_Intel_Core2_End:
606	case kCpumMicroarch_Intel_Core7_End:
607	case kCpumMicroarch_Intel_Atom_End:
608	case kCpumMicroarch_Intel_P6_Core_Atom_End:
609	case kCpumMicroarch_Intel_Phi_End:
610	case kCpumMicroarch_Intel_NB_End:
611	case kCpumMicroarch_AMD_K7_End:
612	case kCpumMicroarch_AMD_K8_End:
613	case kCpumMicroarch_AMD_15h_End:
614	case kCpumMicroarch_AMD_16h_End:
615	case kCpumMicroarch_AMD_Zen_End:
616	case kCpumMicroarch_AMD_End:
617	case kCpumMicroarch_VIA_End:
618	case kCpumMicroarch_Cyrix_End:
619	case kCpumMicroarch_NEC_End:
620	case kCpumMicroarch_32BitHack:
621	break;
622	/* no default! */
623	}
624
625	return NULL;
626	}
627
628
629	/**
630	* Determins the host CPU MXCSR mask.
631	*
632	* @returns MXCSR mask.
633	*/
634	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
635	{
636	if ( ASMHasCpuId()
637	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
638	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
639	{
640	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
641	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
642	RT_ZERO(*pState);
643	ASMFxSave(pState);
644	if (pState->MXCSR_MASK == 0)
645	return 0xffbf;
646	return pState->MXCSR_MASK;
647	}
648	return 0;
649	}
650
651
652	/**
653	* Gets a matching leaf in the CPUID leaf array.
654	*
655	* @returns Pointer to the matching leaf, or NULL if not found.
656	* @param paLeaves The CPUID leaves to search. This is sorted.
657	* @param cLeaves The number of leaves in the array.
658	* @param uLeaf The leaf to locate.
659	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
660	*/
661	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
662	{
663	/* Lazy bird does linear lookup here since this is only used for the
664	occational CPUID overrides. */
665	for (uint32_t i = 0; i < cLeaves; i++)
666	if ( paLeaves[i].uLeaf == uLeaf
667	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
668	return &paLeaves[i];
669	return NULL;
670	}
671
672
673	#ifndef IN_VBOX_CPU_REPORT
674	/**
675	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
676	*
677	* @returns true if found, false it not.
678	* @param paLeaves The CPUID leaves to search. This is sorted.
679	* @param cLeaves The number of leaves in the array.
680	* @param uLeaf The leaf to locate.
681	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
682	* @param pLegacy The legacy output leaf.
683	*/
684	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
685	PCPUMCPUID pLegacy)
686	{
687	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
688	if (pLeaf)
689	{
690	pLegacy->uEax = pLeaf->uEax;
691	pLegacy->uEbx = pLeaf->uEbx;
692	pLegacy->uEcx = pLeaf->uEcx;
693	pLegacy->uEdx = pLeaf->uEdx;
694	return true;
695	}
696	return false;
697	}
698	#endif /* IN_VBOX_CPU_REPORT */
699
700
701	/**
702	* Ensures that the CPUID leaf array can hold one more leaf.
703	*
704	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
705	* failure.
706	* @param pVM The cross context VM structure. If NULL, use
707	* the process heap, otherwise the VM's hyper heap.
708	* @param ppaLeaves Pointer to the variable holding the array pointer
709	* (input/output).
710	* @param cLeaves The current array size.
711	*
712	* @remarks This function will automatically update the R0 and RC pointers when
713	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
714	* be the corresponding VM's CPUID arrays (which is asserted).
715	*/
716	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
717	{
718	/*
719	* If pVM is not specified, we're on the regular heap and can waste a
720	* little space to speed things up.
721	*/
722	uint32_t cAllocated;
723	if (!pVM)
724	{
725	cAllocated = RT_ALIGN(cLeaves, 16);
726	if (cLeaves + 1 > cAllocated)
727	{
728	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
729	if (pvNew)
730	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
731	else
732	{
733	RTMemFree(*ppaLeaves);
734	*ppaLeaves = NULL;
735	}
736	}
737	}
738	/*
739	* Otherwise, we're on the hyper heap and are probably just inserting
740	* one or two leaves and should conserve space.
741	*/
742	else
743	{
744	#ifdef IN_VBOX_CPU_REPORT
745	AssertReleaseFailed();
746	#else
747	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
748	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
749
750	size_t cb = cLeaves * sizeof(**ppaLeaves);
751	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
752	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
753	if (RT_SUCCESS(rc))
754	{
755	/* Update the R0 and RC pointers. */
756	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
757	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
758	}
759	else
760	{
761	*ppaLeaves = NULL;
762	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
763	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
764	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
765	}
766	#endif
767	}
768	return *ppaLeaves;
769	}
770
771
772	/**
773	* Append a CPUID leaf or sub-leaf.
774	*
775	* ASSUMES linear insertion order, so we'll won't need to do any searching or
776	* replace anything. Use cpumR3CpuIdInsert() for those cases.
777	*
778	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
779	* the caller need do no more work.
780	* @param ppaLeaves Pointer to the pointer to the array of sorted
781	* CPUID leaves and sub-leaves.
782	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
783	* @param uLeaf The leaf we're adding.
784	* @param uSubLeaf The sub-leaf number.
785	* @param fSubLeafMask The sub-leaf mask.
786	* @param uEax The EAX value.
787	* @param uEbx The EBX value.
788	* @param uEcx The ECX value.
789	* @param uEdx The EDX value.
790	* @param fFlags The flags.
791	*/
792	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
793	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
794	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
795	{
796	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
797	return VERR_NO_MEMORY;
798
799	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
800	Assert( *pcLeaves == 0
801	\|\| pNew[-1].uLeaf < uLeaf
802	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
803
804	pNew->uLeaf = uLeaf;
805	pNew->uSubLeaf = uSubLeaf;
806	pNew->fSubLeafMask = fSubLeafMask;
807	pNew->uEax = uEax;
808	pNew->uEbx = uEbx;
809	pNew->uEcx = uEcx;
810	pNew->uEdx = uEdx;
811	pNew->fFlags = fFlags;
812
813	*pcLeaves += 1;
814	return VINF_SUCCESS;
815	}
816
817
818	/**
819	* Checks that we've updated the CPUID leaves array correctly.
820	*
821	* This is a no-op in non-strict builds.
822	*
823	* @param paLeaves The leaves array.
824	* @param cLeaves The number of leaves.
825	*/
826	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
827	{
828	#ifdef VBOX_STRICT
829	for (uint32_t i = 1; i < cLeaves; i++)
830	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
831	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
832	else
833	{
834	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
835	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
836	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
837	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
838	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
839	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
840	}
841	#else
842	NOREF(paLeaves);
843	NOREF(cLeaves);
844	#endif
845	}
846
847
848	/**
849	* Inserts a CPU ID leaf, replacing any existing ones.
850	*
851	* When inserting a simple leaf where we already got a series of sub-leaves with
852	* the same leaf number (eax), the simple leaf will replace the whole series.
853	*
854	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
855	* host-context heap and has only been allocated/reallocated by the
856	* cpumR3CpuIdEnsureSpace function.
857	*
858	* @returns VBox status code.
859	* @param pVM The cross context VM structure. If NULL, use
860	* the process heap, otherwise the VM's hyper heap.
861	* @param ppaLeaves Pointer to the pointer to the array of sorted
862	* CPUID leaves and sub-leaves. Must be NULL if using
863	* the hyper heap.
864	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
865	* be NULL if using the hyper heap.
866	* @param pNewLeaf Pointer to the data of the new leaf we're about to
867	* insert.
868	*/
869	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
870	{
871	/*
872	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
873	*/
874	if (pVM)
875	{
876	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
877	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
878
879	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
880	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
881	}
882
883	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
884	uint32_t cLeaves = *pcLeaves;
885
886	/*
887	* Validate the new leaf a little.
888	*/
889	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
890	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
891	VERR_INVALID_FLAGS);
892	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
893	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
894	VERR_INVALID_PARAMETER);
895	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
896	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
897	VERR_INVALID_PARAMETER);
898	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
899	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
900	VERR_INVALID_PARAMETER);
901
902	/*
903	* Find insertion point. The lazy bird uses the same excuse as in
904	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
905	*/
906	uint32_t i;
907	if ( cLeaves > 0
908	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
909	{
910	/* Add at end. */
911	i = cLeaves;
912	}
913	else if ( cLeaves > 0
914	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
915	{
916	/* Either replacing the last leaf or dealing with sub-leaves. Spool
917	back to the first sub-leaf to pretend we did the linear search. */
918	i = cLeaves - 1;
919	while ( i > 0
920	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
921	i--;
922	}
923	else
924	{
925	/* Linear search from the start. */
926	i = 0;
927	while ( i < cLeaves
928	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
929	i++;
930	}
931	if ( i < cLeaves
932	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
933	{
934	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
935	{
936	/*
937	* The sub-leaf mask differs, replace all existing leaves with the
938	* same leaf number.
939	*/
940	uint32_t c = 1;
941	while ( i + c < cLeaves
942	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
943	c++;
944	if (c > 1 && i + c < cLeaves)
945	{
946	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
947	*pcLeaves = cLeaves -= c - 1;
948	}
949
950	paLeaves[i] = *pNewLeaf;
951	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
952	return VINF_SUCCESS;
953	}
954
955	/* Find sub-leaf insertion point. */
956	while ( i < cLeaves
957	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
958	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
959	i++;
960
961	/*
962	* If we've got an exactly matching leaf, replace it.
963	*/
964	if ( i < cLeaves
965	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
966	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
967	{
968	paLeaves[i] = *pNewLeaf;
969	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
970	return VINF_SUCCESS;
971	}
972	}
973
974	/*
975	* Adding a new leaf at 'i'.
976	*/
977	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
978	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
979	if (!paLeaves)
980	return VERR_NO_MEMORY;
981
982	if (i < cLeaves)
983	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
984	*pcLeaves += 1;
985	paLeaves[i] = *pNewLeaf;
986
987	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
988	return VINF_SUCCESS;
989	}
990
991
992	#ifndef IN_VBOX_CPU_REPORT
993	/**
994	* Removes a range of CPUID leaves.
995	*
996	* This will not reallocate the array.
997	*
998	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
999	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1000	* @param uFirst The first leaf.
1001	* @param uLast The last leaf.
1002	*/
1003	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1004	{
1005	uint32_t cLeaves = *pcLeaves;
1006
1007	Assert(uFirst <= uLast);
1008
1009	/*
1010	* Find the first one.
1011	*/
1012	uint32_t iFirst = 0;
1013	while ( iFirst < cLeaves
1014	&& paLeaves[iFirst].uLeaf < uFirst)
1015	iFirst++;
1016
1017	/*
1018	* Find the end (last + 1).
1019	*/
1020	uint32_t iEnd = iFirst;
1021	while ( iEnd < cLeaves
1022	&& paLeaves[iEnd].uLeaf <= uLast)
1023	iEnd++;
1024
1025	/*
1026	* Adjust the array if anything needs removing.
1027	*/
1028	if (iFirst < iEnd)
1029	{
1030	if (iEnd < cLeaves)
1031	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1032	*pcLeaves = cLeaves -= (iEnd - iFirst);
1033	}
1034
1035	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1036	}
1037	#endif /* IN_VBOX_CPU_REPORT */
1038
1039
1040	/**
1041	* Checks if ECX make a difference when reading a given CPUID leaf.
1042	*
1043	* @returns @c true if it does, @c false if it doesn't.
1044	* @param uLeaf The leaf we're reading.
1045	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1046	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1047	* final sub-leaf (for leaf 0xb only).
1048	*/
1049	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1050	{
1051	*pfFinalEcxUnchanged = false;
1052
1053	uint32_t auCur[4];
1054	uint32_t auPrev[4];
1055	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1056
1057	/* Look for sub-leaves. */
1058	uint32_t uSubLeaf = 1;
1059	for (;;)
1060	{
1061	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1062	if (memcmp(auCur, auPrev, sizeof(auCur)))
1063	break;
1064
1065	/* Advance / give up. */
1066	uSubLeaf++;
1067	if (uSubLeaf >= 64)
1068	{
1069	*pcSubLeaves = 1;
1070	return false;
1071	}
1072	}
1073
1074	/* Count sub-leaves. */
1075	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1076	uint32_t cRepeats = 0;
1077	uSubLeaf = 0;
1078	for (;;)
1079	{
1080	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1081
1082	/* Figuring out when to stop isn't entirely straight forward as we need
1083	to cover undocumented behavior up to a point and implementation shortcuts. */
1084
1085	/* 1. Look for more than 4 repeating value sets. */
1086	if ( auCur[0] == auPrev[0]
1087	&& auCur[1] == auPrev[1]
1088	&& ( auCur[2] == auPrev[2]
1089	\|\| ( auCur[2] == uSubLeaf
1090	&& auPrev[2] == uSubLeaf - 1) )
1091	&& auCur[3] == auPrev[3])
1092	{
1093	if ( uLeaf != 0xd
1094	\|\| uSubLeaf >= 64
1095	\|\| ( auCur[0] == 0
1096	&& auCur[1] == 0
1097	&& auCur[2] == 0
1098	&& auCur[3] == 0
1099	&& auPrev[2] == 0) )
1100	cRepeats++;
1101	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1102	break;
1103	}
1104	else
1105	cRepeats = 0;
1106
1107	/* 2. Look for zero values. */
1108	if ( auCur[0] == 0
1109	&& auCur[1] == 0
1110	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1111	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1112	&& uSubLeaf >= cMinLeaves)
1113	{
1114	cRepeats = 0;
1115	break;
1116	}
1117
1118	/* 3. Leaf 0xb level type 0 check. */
1119	if ( uLeaf == 0xb
1120	&& (auCur[2] & 0xff00) == 0
1121	&& (auPrev[2] & 0xff00) == 0)
1122	{
1123	cRepeats = 0;
1124	break;
1125	}
1126
1127	/* 99. Give up. */
1128	if (uSubLeaf >= 128)
1129	{
1130	#ifndef IN_VBOX_CPU_REPORT
1131	/* Ok, limit it according to the documentation if possible just to
1132	avoid annoying users with these detection issues. */
1133	uint32_t cDocLimit = UINT32_MAX;
1134	if (uLeaf == 0x4)
1135	cDocLimit = 4;
1136	else if (uLeaf == 0x7)
1137	cDocLimit = 1;
1138	else if (uLeaf == 0xd)
1139	cDocLimit = 63;
1140	else if (uLeaf == 0xf)
1141	cDocLimit = 2;
1142	if (cDocLimit != UINT32_MAX)
1143	{
1144	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1145	*pcSubLeaves = cDocLimit + 3;
1146	return true;
1147	}
1148	#endif
1149	*pcSubLeaves = UINT32_MAX;
1150	return true;
1151	}
1152
1153	/* Advance. */
1154	uSubLeaf++;
1155	memcpy(auPrev, auCur, sizeof(auCur));
1156	}
1157
1158	/* Standard exit. */
1159	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1160	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1161	if (*pcSubLeaves == 0)
1162	*pcSubLeaves = 1;
1163	return true;
1164	}
1165
1166
1167	/**
1168	* Gets a CPU ID leaf.
1169	*
1170	* @returns VBox status code.
1171	* @param pVM The cross context VM structure.
1172	* @param pLeaf Where to store the found leaf.
1173	* @param uLeaf The leaf to locate.
1174	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1175	*/
1176	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1177	{
1178	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1179	uLeaf, uSubLeaf);
1180	if (pcLeaf)
1181	{
1182	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1183	return VINF_SUCCESS;
1184	}
1185
1186	return VERR_NOT_FOUND;
1187	}
1188
1189
1190	/**
1191	* Inserts a CPU ID leaf, replacing any existing ones.
1192	*
1193	* @returns VBox status code.
1194	* @param pVM The cross context VM structure.
1195	* @param pNewLeaf Pointer to the leaf being inserted.
1196	*/
1197	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1198	{
1199	/*
1200	* Validate parameters.
1201	*/
1202	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1203	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1204
1205	/*
1206	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1207	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1208	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1209	*/
1210	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1211	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1212	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1213	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1214	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1215	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1216	{
1217	return VERR_NOT_SUPPORTED;
1218	}
1219
1220	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1221	}
1222
1223	/**
1224	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1225	*
1226	* @returns VBox status code.
1227	* @param ppaLeaves Where to return the array pointer on success.
1228	* Use RTMemFree to release.
1229	* @param pcLeaves Where to return the size of the array on
1230	* success.
1231	*/
1232	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1233	{
1234	*ppaLeaves = NULL;
1235	*pcLeaves = 0;
1236
1237	/*
1238	* Try out various candidates. This must be sorted!
1239	*/
1240	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1241	{
1242	{ UINT32_C(0x00000000), false },
1243	{ UINT32_C(0x10000000), false },
1244	{ UINT32_C(0x20000000), false },
1245	{ UINT32_C(0x30000000), false },
1246	{ UINT32_C(0x40000000), false },
1247	{ UINT32_C(0x50000000), false },
1248	{ UINT32_C(0x60000000), false },
1249	{ UINT32_C(0x70000000), false },
1250	{ UINT32_C(0x80000000), false },
1251	{ UINT32_C(0x80860000), false },
1252	{ UINT32_C(0x8ffffffe), true },
1253	{ UINT32_C(0x8fffffff), true },
1254	{ UINT32_C(0x90000000), false },
1255	{ UINT32_C(0xa0000000), false },
1256	{ UINT32_C(0xb0000000), false },
1257	{ UINT32_C(0xc0000000), false },
1258	{ UINT32_C(0xd0000000), false },
1259	{ UINT32_C(0xe0000000), false },
1260	{ UINT32_C(0xf0000000), false },
1261	};
1262
1263	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1264	{
1265	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1266	uint32_t uEax, uEbx, uEcx, uEdx;
1267	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1268
1269	/*
1270	* Does EAX look like a typical leaf count value?
1271	*/
1272	if ( uEax > uLeaf
1273	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1274	{
1275	/* Yes, dump them. */
1276	uint32_t cLeaves = uEax - uLeaf + 1;
1277	while (cLeaves-- > 0)
1278	{
1279	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1280
1281	uint32_t fFlags = 0;
1282
1283	/* There are currently three known leaves containing an APIC ID
1284	that needs EMT specific attention */
1285	if (uLeaf == 1)
1286	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1287	else if (uLeaf == 0xb && uEcx != 0)
1288	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1289	else if ( uLeaf == UINT32_C(0x8000001e)
1290	&& ( uEax
1291	\|\| uEbx
1292	\|\| uEdx
1293	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1294	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1295
1296	/* The APIC bit is per-VCpu and needs flagging. */
1297	if (uLeaf == 1)
1298	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1299	else if ( uLeaf == UINT32_C(0x80000001)
1300	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1301	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1302	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1303
1304	/* Check three times here to reduce the chance of CPU migration
1305	resulting in false positives with things like the APIC ID. */
1306	uint32_t cSubLeaves;
1307	bool fFinalEcxUnchanged;
1308	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1309	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1310	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1311	{
1312	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1313	{
1314	/* This shouldn't happen. But in case it does, file all
1315	relevant details in the release log. */
1316	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1317	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1318	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1319	{
1320	uint32_t auTmp[4];
1321	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1322	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1323	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1324	}
1325	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1326	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1327	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1328	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1329	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1330	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1331	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1332	}
1333
1334	if (fFinalEcxUnchanged)
1335	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1336
1337	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1338	{
1339	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1340	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1341	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1342	if (RT_FAILURE(rc))
1343	return rc;
1344	}
1345	}
1346	else
1347	{
1348	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1349	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1350	if (RT_FAILURE(rc))
1351	return rc;
1352	}
1353
1354	/* next */
1355	uLeaf++;
1356	}
1357	}
1358	/*
1359	* Special CPUIDs needs special handling as they don't follow the
1360	* leaf count principle used above.
1361	*/
1362	else if (s_aCandidates[iOuter].fSpecial)
1363	{
1364	bool fKeep = false;
1365	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1366	fKeep = true;
1367	else if ( uLeaf == 0x8fffffff
1368	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1369	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1370	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1371	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1372	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1373	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1374	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1375	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1376	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1377	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1378	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1379	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1380	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1381	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1382	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1383	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1384	fKeep = true;
1385	if (fKeep)
1386	{
1387	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1388	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1389	if (RT_FAILURE(rc))
1390	return rc;
1391	}
1392	}
1393	}
1394
1395	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1396	return VINF_SUCCESS;
1397	}
1398
1399
1400	/**
1401	* Determines the method the CPU uses to handle unknown CPUID leaves.
1402	*
1403	* @returns VBox status code.
1404	* @param penmUnknownMethod Where to return the method.
1405	* @param pDefUnknown Where to return default unknown values. This
1406	* will be set, even if the resulting method
1407	* doesn't actually needs it.
1408	*/
1409	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1410	{
1411	uint32_t uLastStd = ASMCpuId_EAX(0);
1412	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1413	if (!ASMIsValidExtRange(uLastExt))
1414	uLastExt = 0x80000000;
1415
1416	uint32_t auChecks[] =
1417	{
1418	uLastStd + 1,
1419	uLastStd + 5,
1420	uLastStd + 8,
1421	uLastStd + 32,
1422	uLastStd + 251,
1423	uLastExt + 1,
1424	uLastExt + 8,
1425	uLastExt + 15,
1426	uLastExt + 63,
1427	uLastExt + 255,
1428	0x7fbbffcc,
1429	0x833f7872,
1430	0xefff2353,
1431	0x35779456,
1432	0x1ef6d33e,
1433	};
1434
1435	static const uint32_t s_auValues[] =
1436	{
1437	0xa95d2156,
1438	0x00000001,
1439	0x00000002,
1440	0x00000008,
1441	0x00000000,
1442	0x55773399,
1443	0x93401769,
1444	0x12039587,
1445	};
1446
1447	/*
1448	* Simple method, all zeros.
1449	*/
1450	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1451	pDefUnknown->uEax = 0;
1452	pDefUnknown->uEbx = 0;
1453	pDefUnknown->uEcx = 0;
1454	pDefUnknown->uEdx = 0;
1455
1456	/*
1457	* Intel has been observed returning the last standard leaf.
1458	*/
1459	uint32_t auLast[4];
1460	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1461
1462	uint32_t cChecks = RT_ELEMENTS(auChecks);
1463	while (cChecks > 0)
1464	{
1465	uint32_t auCur[4];
1466	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1467	if (memcmp(auCur, auLast, sizeof(auCur)))
1468	break;
1469	cChecks--;
1470	}
1471	if (cChecks == 0)
1472	{
1473	/* Now, what happens when the input changes? Esp. ECX. */
1474	uint32_t cTotal = 0;
1475	uint32_t cSame = 0;
1476	uint32_t cLastWithEcx = 0;
1477	uint32_t cNeither = 0;
1478	uint32_t cValues = RT_ELEMENTS(s_auValues);
1479	while (cValues > 0)
1480	{
1481	uint32_t uValue = s_auValues[cValues - 1];
1482	uint32_t auLastWithEcx[4];
1483	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1484	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1485
1486	cChecks = RT_ELEMENTS(auChecks);
1487	while (cChecks > 0)
1488	{
1489	uint32_t auCur[4];
1490	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1491	if (!memcmp(auCur, auLast, sizeof(auCur)))
1492	{
1493	cSame++;
1494	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1495	cLastWithEcx++;
1496	}
1497	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1498	cLastWithEcx++;
1499	else
1500	cNeither++;
1501	cTotal++;
1502	cChecks--;
1503	}
1504	cValues--;
1505	}
1506
1507	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1508	if (cSame == cTotal)
1509	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1510	else if (cLastWithEcx == cTotal)
1511	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1512	else
1513	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1514	pDefUnknown->uEax = auLast[0];
1515	pDefUnknown->uEbx = auLast[1];
1516	pDefUnknown->uEcx = auLast[2];
1517	pDefUnknown->uEdx = auLast[3];
1518	return VINF_SUCCESS;
1519	}
1520
1521	/*
1522	* Unchanged register values?
1523	*/
1524	cChecks = RT_ELEMENTS(auChecks);
1525	while (cChecks > 0)
1526	{
1527	uint32_t const uLeaf = auChecks[cChecks - 1];
1528	uint32_t cValues = RT_ELEMENTS(s_auValues);
1529	while (cValues > 0)
1530	{
1531	uint32_t uValue = s_auValues[cValues - 1];
1532	uint32_t auCur[4];
1533	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1534	if ( auCur[0] != uLeaf
1535	\|\| auCur[1] != uValue
1536	\|\| auCur[2] != uValue
1537	\|\| auCur[3] != uValue)
1538	break;
1539	cValues--;
1540	}
1541	if (cValues != 0)
1542	break;
1543	cChecks--;
1544	}
1545	if (cChecks == 0)
1546	{
1547	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1548	return VINF_SUCCESS;
1549	}
1550
1551	/*
1552	* Just go with the simple method.
1553	*/
1554	return VINF_SUCCESS;
1555	}
1556
1557
1558	/**
1559	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1560	*
1561	* @returns Read only name string.
1562	* @param enmUnknownMethod The method to translate.
1563	*/
1564	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1565	{
1566	switch (enmUnknownMethod)
1567	{
1568	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1569	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1570	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1571	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1572
1573	case CPUMUNKNOWNCPUID_INVALID:
1574	case CPUMUNKNOWNCPUID_END:
1575	case CPUMUNKNOWNCPUID_32BIT_HACK:
1576	break;
1577	}
1578	return "Invalid-unknown-CPUID-method";
1579	}
1580
1581
1582	/**
1583	* Detect the CPU vendor give n the
1584	*
1585	* @returns The vendor.
1586	* @param uEAX EAX from CPUID(0).
1587	* @param uEBX EBX from CPUID(0).
1588	* @param uECX ECX from CPUID(0).
1589	* @param uEDX EDX from CPUID(0).
1590	*/
1591	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1592	{
1593	if (ASMIsValidStdRange(uEAX))
1594	{
1595	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1596	return CPUMCPUVENDOR_AMD;
1597
1598	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1599	return CPUMCPUVENDOR_INTEL;
1600
1601	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1602	return CPUMCPUVENDOR_VIA;
1603
1604	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1605	&& uECX == UINT32_C(0x64616574)
1606	&& uEDX == UINT32_C(0x736E4978))
1607	return CPUMCPUVENDOR_CYRIX;
1608
1609	/* "Geode by NSC", example: family 5, model 9. */
1610
1611	/** @todo detect the other buggers... */
1612	}
1613
1614	return CPUMCPUVENDOR_UNKNOWN;
1615	}
1616
1617
1618	/**
1619	* Translates a CPU vendor enum value into the corresponding string constant.
1620	*
1621	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1622	* value name. This can be useful when generating code.
1623	*
1624	* @returns Read only name string.
1625	* @param enmVendor The CPU vendor value.
1626	*/
1627	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1628	{
1629	switch (enmVendor)
1630	{
1631	case CPUMCPUVENDOR_INTEL: return "INTEL";
1632	case CPUMCPUVENDOR_AMD: return "AMD";
1633	case CPUMCPUVENDOR_VIA: return "VIA";
1634	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1635	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1636
1637	case CPUMCPUVENDOR_INVALID:
1638	case CPUMCPUVENDOR_32BIT_HACK:
1639	break;
1640	}
1641	return "Invalid-cpu-vendor";
1642	}
1643
1644
1645	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1646	{
1647	/* Could do binary search, doing linear now because I'm lazy. */
1648	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1649	while (cLeaves-- > 0)
1650	{
1651	if (pLeaf->uLeaf == uLeaf)
1652	return pLeaf;
1653	pLeaf++;
1654	}
1655	return NULL;
1656	}
1657
1658
1659	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1660	{
1661	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1662	if ( !pLeaf
1663	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1664	return pLeaf;
1665
1666	/* Linear sub-leaf search. Lazy as usual. */
1667	cLeaves -= pLeaf - paLeaves;
1668	while ( cLeaves-- > 0
1669	&& pLeaf->uLeaf == uLeaf)
1670	{
1671	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1672	return pLeaf;
1673	pLeaf++;
1674	}
1675
1676	return NULL;
1677	}
1678
1679
1680	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1681	{
1682	RT_ZERO(*pFeatures);
1683	if (cLeaves >= 2)
1684	{
1685	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1686	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1687	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1688	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1689	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1690	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1691
1692	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1693	pStd0Leaf->uEbx,
1694	pStd0Leaf->uEcx,
1695	pStd0Leaf->uEdx);
1696	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1697	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1698	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1699	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1700	pFeatures->uFamily,
1701	pFeatures->uModel,
1702	pFeatures->uStepping);
1703
1704	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1705	if (pExtLeaf8)
1706	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1707	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1708	pFeatures->cMaxPhysAddrWidth = 36;
1709	else
1710	pFeatures->cMaxPhysAddrWidth = 32;
1711
1712	/* Standard features. */
1713	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1714	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1715	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1716	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1717	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1718	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1719	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1720	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1721	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1722	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1723	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1724	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1725	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1726	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1727	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1728	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1729	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1730	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1731	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1732	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1733	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1734	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1735	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1736	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1737	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1738
1739	/* Structured extended features. */
1740	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1741	if (pSxfLeaf0)
1742	{
1743	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1744	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1745	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1746	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1747	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1748
1749	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1750	pFeatures->fIbrs = pFeatures->fIbpb;
1751	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1752	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1753	}
1754
1755	/* MWAIT/MONITOR leaf. */
1756	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1757	if (pMWaitLeaf)
1758	{
1759	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1760	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1761	}
1762
1763	/* Extended features. */
1764	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1765	if (pExtLeaf)
1766	{
1767	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1768	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1769	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1770	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1771	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1772	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1773	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1774	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1775	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1776	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1777	}
1778
1779	if ( pExtLeaf
1780	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1781	{
1782	/* AMD features. */
1783	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1784	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1785	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1786	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1787	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1788	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1789	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1790	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1791	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1792	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1793	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1794	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1795	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1796	if (pFeatures->fSvm)
1797	{
1798	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1799	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1800	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1801	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1802	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1803	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1804	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1805	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1806	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1807	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1808	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1809	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1810	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1811	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1812	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1813	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1814	}
1815	}
1816
1817	/*
1818	* Quirks.
1819	*/
1820	pFeatures->fLeakyFxSR = pExtLeaf
1821	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1822	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1823	&& pFeatures->uFamily >= 6 /* K7 and up */;
1824
1825	/*
1826	* Max extended (/FPU) state.
1827	*/
1828	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1829	if (pFeatures->fXSaveRstor)
1830	{
1831	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1832	if (pXStateLeaf0)
1833	{
1834	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1835	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1836	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1837	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1838	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1839	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1840	{
1841	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1842
1843	/* (paranoia:) */
1844	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1845	if ( pXStateLeaf1
1846	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1847	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1848	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1849	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1850	}
1851	else
1852	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1853	pFeatures->fXSaveRstor = 0);
1854	}
1855	else
1856	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1857	pFeatures->fXSaveRstor = 0);
1858	}
1859	}
1860	else
1861	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1862	return VINF_SUCCESS;
1863	}
1864
1865
1866	/*
1867	*
1868	* Init related code.
1869	* Init related code.
1870	* Init related code.
1871	*
1872	*
1873	*/
1874	#ifdef VBOX_IN_VMM
1875
1876
1877	/**
1878	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1879	*
1880	* This ignores the fSubLeafMask.
1881	*
1882	* @returns Pointer to the matching leaf, or NULL if not found.
1883	* @param paLeaves The CPUID leaves to search. This is sorted.
1884	* @param cLeaves The number of leaves in the array.
1885	* @param uLeaf The leaf to locate.
1886	* @param uSubLeaf The subleaf to locate.
1887	*/
1888	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1889	{
1890	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1891	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1892	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1893	if (iEnd)
1894	{
1895	uint32_t iBegin = 0;
1896	for (;;)
1897	{
1898	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1899	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1900	if (uNeedle < uCur)
1901	{
1902	if (i > iBegin)
1903	iEnd = i;
1904	else
1905	break;
1906	}
1907	else if (uNeedle > uCur)
1908	{
1909	if (i + 1 < iEnd)
1910	iBegin = i + 1;
1911	else
1912	break;
1913	}
1914	else
1915	return &paLeaves[i];
1916	}
1917	}
1918	return NULL;
1919	}
1920
1921
1922	/**
1923	* Loads MSR range overrides.
1924	*
1925	* This must be called before the MSR ranges are moved from the normal heap to
1926	* the hyper heap!
1927	*
1928	* @returns VBox status code (VMSetError called).
1929	* @param pVM The cross context VM structure.
1930	* @param pMsrNode The CFGM node with the MSR overrides.
1931	*/
1932	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1933	{
1934	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1935	{
1936	/*
1937	* Assemble a valid MSR range.
1938	*/
1939	CPUMMSRRANGE MsrRange;
1940	MsrRange.offCpumCpu = 0;
1941	MsrRange.fReserved = 0;
1942
1943	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1944	if (RT_FAILURE(rc))
1945	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1946
1947	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1948	if (RT_FAILURE(rc))
1949	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1950	MsrRange.szName, rc);
1951
1952	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1953	if (RT_FAILURE(rc))
1954	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1955	MsrRange.szName, rc);
1956
1957	char szType[32];
1958	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1959	if (RT_FAILURE(rc))
1960	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1961	MsrRange.szName, rc);
1962	if (!RTStrICmp(szType, "FixedValue"))
1963	{
1964	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1965	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1966
1967	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1968	if (RT_FAILURE(rc))
1969	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1970	MsrRange.szName, rc);
1971
1972	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1973	if (RT_FAILURE(rc))
1974	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1975	MsrRange.szName, rc);
1976
1977	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1978	if (RT_FAILURE(rc))
1979	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1980	MsrRange.szName, rc);
1981	}
1982	else
1983	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1984	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1985
1986	/*
1987	* Insert the range into the table (replaces/splits/shrinks existing
1988	* MSR ranges).
1989	*/
1990	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1991	&MsrRange);
1992	if (RT_FAILURE(rc))
1993	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
1994	}
1995
1996	return VINF_SUCCESS;
1997	}
1998
1999
2000	/**
2001	* Loads CPUID leaf overrides.
2002	*
2003	* This must be called before the CPUID leaves are moved from the normal
2004	* heap to the hyper heap!
2005	*
2006	* @returns VBox status code (VMSetError called).
2007	* @param pVM The cross context VM structure.
2008	* @param pParentNode The CFGM node with the CPUID leaves.
2009	* @param pszLabel How to label the overrides we're loading.
2010	*/
2011	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2012	{
2013	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2014	{
2015	/*
2016	* Get the leaf and subleaf numbers.
2017	*/
2018	char szName[128];
2019	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2020	if (RT_FAILURE(rc))
2021	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2022
2023	/* The leaf number is either specified directly or thru the node name. */
2024	uint32_t uLeaf;
2025	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2026	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2027	{
2028	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2029	if (rc != VINF_SUCCESS)
2030	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2031	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2032	}
2033	else if (RT_FAILURE(rc))
2034	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2035	pszLabel, szName, rc);
2036
2037	uint32_t uSubLeaf;
2038	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2039	if (RT_FAILURE(rc))
2040	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2041	pszLabel, szName, rc);
2042
2043	uint32_t fSubLeafMask;
2044	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2045	if (RT_FAILURE(rc))
2046	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2047	pszLabel, szName, rc);
2048
2049	/*
2050	* Look up the specified leaf, since the output register values
2051	* defaults to any existing values. This allows overriding a single
2052	* register, without needing to know the other values.
2053	*/
2054	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2055	CPUMCPUIDLEAF Leaf;
2056	if (pLeaf)
2057	Leaf = *pLeaf;
2058	else
2059	RT_ZERO(Leaf);
2060	Leaf.uLeaf = uLeaf;
2061	Leaf.uSubLeaf = uSubLeaf;
2062	Leaf.fSubLeafMask = fSubLeafMask;
2063
2064	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2065	if (RT_FAILURE(rc))
2066	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2067	pszLabel, szName, rc);
2068	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2069	if (RT_FAILURE(rc))
2070	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2071	pszLabel, szName, rc);
2072	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2073	if (RT_FAILURE(rc))
2074	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2075	pszLabel, szName, rc);
2076	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2077	if (RT_FAILURE(rc))
2078	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2079	pszLabel, szName, rc);
2080
2081	/*
2082	* Insert the leaf into the table (replaces existing ones).
2083	*/
2084	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2085	&Leaf);
2086	if (RT_FAILURE(rc))
2087	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2088	}
2089
2090	return VINF_SUCCESS;
2091	}
2092
2093
2094
2095	/**
2096	* Fetches overrides for a CPUID leaf.
2097	*
2098	* @returns VBox status code.
2099	* @param pLeaf The leaf to load the overrides into.
2100	* @param pCfgNode The CFGM node containing the overrides
2101	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2102	* @param iLeaf The CPUID leaf number.
2103	*/
2104	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2105	{
2106	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2107	if (pLeafNode)
2108	{
2109	uint32_t u32;
2110	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2111	if (RT_SUCCESS(rc))
2112	pLeaf->uEax = u32;
2113	else
2114	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2115
2116	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2117	if (RT_SUCCESS(rc))
2118	pLeaf->uEbx = u32;
2119	else
2120	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2121
2122	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2123	if (RT_SUCCESS(rc))
2124	pLeaf->uEcx = u32;
2125	else
2126	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2127
2128	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2129	if (RT_SUCCESS(rc))
2130	pLeaf->uEdx = u32;
2131	else
2132	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2133
2134	}
2135	return VINF_SUCCESS;
2136	}
2137
2138
2139	/**
2140	* Load the overrides for a set of CPUID leaves.
2141	*
2142	* @returns VBox status code.
2143	* @param paLeaves The leaf array.
2144	* @param cLeaves The number of leaves.
2145	* @param uStart The start leaf number.
2146	* @param pCfgNode The CFGM node containing the overrides
2147	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2148	*/
2149	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2150	{
2151	for (uint32_t i = 0; i < cLeaves; i++)
2152	{
2153	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2154	if (RT_FAILURE(rc))
2155	return rc;
2156	}
2157
2158	return VINF_SUCCESS;
2159	}
2160
2161
2162	/**
2163	* Installs the CPUID leaves and explods the data into structures like
2164	* GuestFeatures and CPUMCTX::aoffXState.
2165	*
2166	* @returns VBox status code.
2167	* @param pVM The cross context VM structure.
2168	* @param pCpum The CPUM part of @a VM.
2169	* @param paLeaves The leaves. These will be copied (but not freed).
2170	* @param cLeaves The number of leaves.
2171	*/
2172	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
2173	{
2174	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2175
2176	/*
2177	* Install the CPUID information.
2178	*/
2179	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2180	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2181
2182	AssertLogRelRCReturn(rc, rc);
2183	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2184	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2185	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2186	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2187	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2188
2189	/*
2190	* Update the default CPUID leaf if necessary.
2191	*/
2192	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2193	{
2194	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2195	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2196	{
2197	/* We don't use CPUID(0).eax here because of the NT hack that only
2198	changes that value without actually removing any leaves. */
2199	uint32_t i = 0;
2200	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2201	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2202	{
2203	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2204	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2205	i++;
2206	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2207	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2208	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2209	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2210	}
2211	break;
2212	}
2213	default:
2214	break;
2215	}
2216
2217	/*
2218	* Explode the guest CPU features.
2219	*/
2220	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
2221	AssertLogRelRCReturn(rc, rc);
2222
2223	/*
2224	* Adjust the scalable bus frequency according to the CPUID information
2225	* we're now using.
2226	*/
2227	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2228	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2229	? UINT64_C(100000000) /* 100MHz */
2230	: UINT64_C(133333333); /* 133MHz */
2231
2232	/*
2233	* Populate the legacy arrays. Currently used for everything, later only
2234	* for patch manager.
2235	*/
2236	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2237	{
2238	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2239	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2240	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2241	};
2242	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2243	{
2244	uint32_t cLeft = aOldRanges[i].cCpuIds;
2245	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2246	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2247	while (cLeft-- > 0)
2248	{
2249	uLeaf--;
2250	pLegacyLeaf--;
2251
2252	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2253	if (pLeaf)
2254	{
2255	pLegacyLeaf->uEax = pLeaf->uEax;
2256	pLegacyLeaf->uEbx = pLeaf->uEbx;
2257	pLegacyLeaf->uEcx = pLeaf->uEcx;
2258	pLegacyLeaf->uEdx = pLeaf->uEdx;
2259	}
2260	else
2261	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2262	}
2263	}
2264
2265	/*
2266	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2267	*/
2268	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2269	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2270	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2271	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2272	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2273	{
2274	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2275	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2276	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2277	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2278	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2279	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2280	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2281	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2282	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2283	pCpum->GuestFeatures.cbMaxExtendedState),
2284	VERR_CPUM_IPE_1);
2285	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2286	}
2287	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2288
2289	/* Copy the CPU #0 data to the other CPUs. */
2290	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2291	{
2292	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2293	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2294	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2295	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2296	}
2297
2298	return VINF_SUCCESS;
2299	}
2300
2301
2302	/** @name Instruction Set Extension Options
2303	* @{ */
2304	/** Configuration option type (extended boolean, really). */
2305	typedef uint8_t CPUMISAEXTCFG;
2306	/** Always disable the extension. */
2307	#define CPUMISAEXTCFG_DISABLED false
2308	/** Enable the extension if it's supported by the host CPU. */
2309	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2310	/** Enable the extension if it's supported by the host CPU, but don't let
2311	* the portable CPUID feature disable it. */
2312	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2313	/** Always enable the extension. */
2314	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2315	/** @} */
2316
2317	/**
2318	* CPUID Configuration (from CFGM).
2319	*
2320	* @remarks The members aren't document since we would only be duplicating the
2321	* \@cfgm entries in cpumR3CpuIdReadConfig.
2322	*/
2323	typedef struct CPUMCPUIDCONFIG
2324	{
2325	bool fNt4LeafLimit;
2326	bool fInvariantTsc;
2327	bool fForceVme;
2328	bool fNestedHWVirt;
2329
2330	CPUMISAEXTCFG enmCmpXchg16b;
2331	CPUMISAEXTCFG enmMonitor;
2332	CPUMISAEXTCFG enmMWaitExtensions;
2333	CPUMISAEXTCFG enmSse41;
2334	CPUMISAEXTCFG enmSse42;
2335	CPUMISAEXTCFG enmAvx;
2336	CPUMISAEXTCFG enmAvx2;
2337	CPUMISAEXTCFG enmXSave;
2338	CPUMISAEXTCFG enmAesNi;
2339	CPUMISAEXTCFG enmPClMul;
2340	CPUMISAEXTCFG enmPopCnt;
2341	CPUMISAEXTCFG enmMovBe;
2342	CPUMISAEXTCFG enmRdRand;
2343	CPUMISAEXTCFG enmRdSeed;
2344	CPUMISAEXTCFG enmCLFlushOpt;
2345	CPUMISAEXTCFG enmFsGsBase;
2346	CPUMISAEXTCFG enmPcid;
2347	CPUMISAEXTCFG enmInvpcid;
2348
2349	CPUMISAEXTCFG enmAbm;
2350	CPUMISAEXTCFG enmSse4A;
2351	CPUMISAEXTCFG enmMisAlnSse;
2352	CPUMISAEXTCFG enm3dNowPrf;
2353	CPUMISAEXTCFG enmAmdExtMmx;
2354
2355	uint32_t uMaxStdLeaf;
2356	uint32_t uMaxExtLeaf;
2357	uint32_t uMaxCentaurLeaf;
2358	uint32_t uMaxIntelFamilyModelStep;
2359	char szCpuName[128];
2360	} CPUMCPUIDCONFIG;
2361	/** Pointer to CPUID config (from CFGM). */
2362	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2363
2364
2365	/**
2366	* Mini CPU selection support for making Mac OS X happy.
2367	*
2368	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2369	*
2370	* @param pCpum The CPUM instance data.
2371	* @param pConfig The CPUID configuration we've read from CFGM.
2372	*/
2373	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2374	{
2375	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2376	{
2377	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2378	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2379	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2380	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2381	0);
2382	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2383	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2384	{
2385	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2386	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2387	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2388	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2389	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2390	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2391	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2392	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2393	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2394	pStdFeatureLeaf->uEax = uNew;
2395	}
2396	}
2397	}
2398
2399
2400
2401	/**
2402	* Limit it the number of entries, zapping the remainder.
2403	*
2404	* The limits are masking off stuff about power saving and similar, this
2405	* is perhaps a bit crudely done as there is probably some relatively harmless
2406	* info too in these leaves (like words about having a constant TSC).
2407	*
2408	* @param pCpum The CPUM instance data.
2409	* @param pConfig The CPUID configuration we've read from CFGM.
2410	*/
2411	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2412	{
2413	/*
2414	* Standard leaves.
2415	*/
2416	uint32_t uSubLeaf = 0;
2417	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2418	if (pCurLeaf)
2419	{
2420	uint32_t uLimit = pCurLeaf->uEax;
2421	if (uLimit <= UINT32_C(0x000fffff))
2422	{
2423	if (uLimit > pConfig->uMaxStdLeaf)
2424	{
2425	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2426	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2427	uLimit + 1, UINT32_C(0x000fffff));
2428	}
2429
2430	/* NT4 hack, no zapping of extra leaves here. */
2431	if (pConfig->fNt4LeafLimit && uLimit > 3)
2432	pCurLeaf->uEax = uLimit = 3;
2433
2434	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2435	pCurLeaf->uEax = uLimit;
2436	}
2437	else
2438	{
2439	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2440	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2441	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2442	}
2443	}
2444
2445	/*
2446	* Extended leaves.
2447	*/
2448	uSubLeaf = 0;
2449	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2450	if (pCurLeaf)
2451	{
2452	uint32_t uLimit = pCurLeaf->uEax;
2453	if ( uLimit >= UINT32_C(0x80000000)
2454	&& uLimit <= UINT32_C(0x800fffff))
2455	{
2456	if (uLimit > pConfig->uMaxExtLeaf)
2457	{
2458	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2459	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2460	uLimit + 1, UINT32_C(0x800fffff));
2461	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2462	pCurLeaf->uEax = uLimit;
2463	}
2464	}
2465	else
2466	{
2467	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2468	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2469	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2470	}
2471	}
2472
2473	/*
2474	* Centaur leaves (VIA).
2475	*/
2476	uSubLeaf = 0;
2477	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2478	if (pCurLeaf)
2479	{
2480	uint32_t uLimit = pCurLeaf->uEax;
2481	if ( uLimit >= UINT32_C(0xc0000000)
2482	&& uLimit <= UINT32_C(0xc00fffff))
2483	{
2484	if (uLimit > pConfig->uMaxCentaurLeaf)
2485	{
2486	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2487	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2488	uLimit + 1, UINT32_C(0xcfffffff));
2489	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2490	pCurLeaf->uEax = uLimit;
2491	}
2492	}
2493	else
2494	{
2495	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2496	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2497	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2498	}
2499	}
2500	}
2501
2502
2503	/**
2504	* Clears a CPUID leaf and all sub-leaves (to zero).
2505	*
2506	* @param pCpum The CPUM instance data.
2507	* @param uLeaf The leaf to clear.
2508	*/
2509	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2510	{
2511	uint32_t uSubLeaf = 0;
2512	PCPUMCPUIDLEAF pCurLeaf;
2513	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2514	{
2515	pCurLeaf->uEax = 0;
2516	pCurLeaf->uEbx = 0;
2517	pCurLeaf->uEcx = 0;
2518	pCurLeaf->uEdx = 0;
2519	uSubLeaf++;
2520	}
2521	}
2522
2523
2524	/**
2525	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2526	* the given leaf.
2527	*
2528	* @returns pLeaf.
2529	* @param pCpum The CPUM instance data.
2530	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2531	*/
2532	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2533	{
2534	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2535	if (pLeaf->fSubLeafMask != 0)
2536	{
2537	/*
2538	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2539	* Log everything while we're at it.
2540	*/
2541	LogRel(("CPUM:\n"
2542	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2543	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2544	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2545	for (;;)
2546	{
2547	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2548	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2549	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2550	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2551	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2552	break;
2553	pSubLeaf++;
2554	}
2555	LogRel(("CPUM:\n"));
2556
2557	/*
2558	* Remove the offending sub-leaves.
2559	*/
2560	if (pSubLeaf != pLeaf)
2561	{
2562	if (pSubLeaf != pLast)
2563	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2564	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2565	}
2566
2567	/*
2568	* Convert the first sub-leaf into a single leaf.
2569	*/
2570	pLeaf->uSubLeaf = 0;
2571	pLeaf->fSubLeafMask = 0;
2572	}
2573	return pLeaf;
2574	}
2575
2576
2577	/**
2578	* Sanitizes and adjust the CPUID leaves.
2579	*
2580	* Drop features that aren't virtualized (or virtualizable). Adjust information
2581	* and capabilities to fit the virtualized hardware. Remove information the
2582	* guest shouldn't have (because it's wrong in the virtual world or because it
2583	* gives away host details) or that we don't have documentation for and no idea
2584	* what means.
2585	*
2586	* @returns VBox status code.
2587	* @param pVM The cross context VM structure (for cCpus).
2588	* @param pCpum The CPUM instance data.
2589	* @param pConfig The CPUID configuration we've read from CFGM.
2590	*/
2591	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2592	{
2593	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2594	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2595	{ \
2596	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2597	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2598	}
2599	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2600	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2601	{ \
2602	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2603	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2604	}
2605	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2606	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2607	&& ((a_pLeafReg) & (fBitMask)) \
2608	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2609	{ \
2610	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2611	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2612	}
2613	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2614
2615	/* Cpuid 1:
2616	* EAX: CPU model, family and stepping.
2617	*
2618	* ECX + EDX: Supported features. Only report features we can support.
2619	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2620	* options may require adjusting (i.e. stripping what was enabled).
2621	*
2622	* EBX: Branding, CLFLUSH line size, logical processors per package and
2623	* initial APIC ID.
2624	*/
2625	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2626	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2627	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2628
2629	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2630	\| X86_CPUID_FEATURE_EDX_VME
2631	\| X86_CPUID_FEATURE_EDX_DE
2632	\| X86_CPUID_FEATURE_EDX_PSE
2633	\| X86_CPUID_FEATURE_EDX_TSC
2634	\| X86_CPUID_FEATURE_EDX_MSR
2635	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2636	\| X86_CPUID_FEATURE_EDX_MCE
2637	\| X86_CPUID_FEATURE_EDX_CX8
2638	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2639	//\| RT_BIT_32(10) - not defined
2640	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2641	//\| X86_CPUID_FEATURE_EDX_SEP
2642	\| X86_CPUID_FEATURE_EDX_MTRR
2643	\| X86_CPUID_FEATURE_EDX_PGE
2644	\| X86_CPUID_FEATURE_EDX_MCA
2645	\| X86_CPUID_FEATURE_EDX_CMOV
2646	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2647	\| X86_CPUID_FEATURE_EDX_PSE36
2648	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2649	\| X86_CPUID_FEATURE_EDX_CLFSH
2650	//\| RT_BIT_32(20) - not defined
2651	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2652	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2653	\| X86_CPUID_FEATURE_EDX_MMX
2654	\| X86_CPUID_FEATURE_EDX_FXSR
2655	\| X86_CPUID_FEATURE_EDX_SSE
2656	\| X86_CPUID_FEATURE_EDX_SSE2
2657	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2658	\| X86_CPUID_FEATURE_EDX_HTT
2659	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2660	//\| RT_BIT_32(30) - not defined
2661	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2662	;
2663	pStdFeatureLeaf->uEcx &= 0
2664	\| X86_CPUID_FEATURE_ECX_SSE3
2665	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2666	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2667	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2668	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2669	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2670	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized yet.
2671	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2672	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2673	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2674	\| X86_CPUID_FEATURE_ECX_SSSE3
2675	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2676	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2677	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2678	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2679	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2680	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2681	\| (pConfig->enmPcid ? X86_CPUID_FEATURE_ECX_PCID : 0)
2682	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2683	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2684	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2685	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2686	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2687	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2688	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2689	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2690	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2691	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2692	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2693	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2694	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2695	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2696	;
2697
2698	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2699	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2700	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2701	{
2702	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2703	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2704	}
2705
2706	if (pCpum->u8PortableCpuIdLevel > 0)
2707	{
2708	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2709	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2710	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2711	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2712	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2713	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2714	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2715	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2716	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2717	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2718	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2719	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2720	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2721	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2722	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2723	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2724	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2725	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2726	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2727
2728	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2729	\| X86_CPUID_FEATURE_EDX_PSN
2730	\| X86_CPUID_FEATURE_EDX_DS
2731	\| X86_CPUID_FEATURE_EDX_ACPI
2732	\| X86_CPUID_FEATURE_EDX_SS
2733	\| X86_CPUID_FEATURE_EDX_TM
2734	\| X86_CPUID_FEATURE_EDX_PBE
2735	)));
2736	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2737	\| X86_CPUID_FEATURE_ECX_CPLDS
2738	\| X86_CPUID_FEATURE_ECX_VMX
2739	\| X86_CPUID_FEATURE_ECX_SMX
2740	\| X86_CPUID_FEATURE_ECX_EST
2741	\| X86_CPUID_FEATURE_ECX_TM2
2742	\| X86_CPUID_FEATURE_ECX_CNTXID
2743	\| X86_CPUID_FEATURE_ECX_FMA
2744	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2745	\| X86_CPUID_FEATURE_ECX_PDCM
2746	\| X86_CPUID_FEATURE_ECX_DCA
2747	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2748	)));
2749	}
2750
2751	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2752	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2753
2754	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2755	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2756	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2757	*/
2758	#ifdef VBOX_WITH_MULTI_CORE
2759	if (pVM->cCpus > 1)
2760	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2761	#endif
2762	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2763	{
2764	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2765	core times the number of CPU cores per processor */
2766	#ifdef VBOX_WITH_MULTI_CORE
2767	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2768	#else
2769	/* Single logical processor in a package. */
2770	pStdFeatureLeaf->uEbx \|= (1 << 16);
2771	#endif
2772	}
2773
2774	uint32_t uMicrocodeRev;
2775	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2776	if (RT_SUCCESS(rc))
2777	{
2778	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2779	}
2780	else
2781	{
2782	uMicrocodeRev = 0;
2783	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2784	}
2785
2786	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2787	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2788	*/
2789	if ( (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen)
2790	&& uMicrocodeRev < 0x8001126
2791	&& !pConfig->fForceVme)
2792	{
2793	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2794	LogRel(("CPUM: Zen VME workaround engaged\n"));
2795	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2796	}
2797
2798	/* Force standard feature bits. */
2799	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2800	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2801	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2802	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2803	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2804	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2805	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2806	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2807	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2808	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2809	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2810	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2811	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2812	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2813	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2814	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2815	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2816	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2817	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2818	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2819	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2820	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2821
2822	pStdFeatureLeaf = NULL; /* Must refetch! */
2823
2824	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2825	* AMD:
2826	* EAX: CPU model, family and stepping.
2827	*
2828	* ECX + EDX: Supported features. Only report features we can support.
2829	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2830	* options may require adjusting (i.e. stripping what was enabled).
2831	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2832	*
2833	* EBX: Branding ID and package type (or reserved).
2834	*
2835	* Intel and probably most others:
2836	* EAX: 0
2837	* EBX: 0
2838	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2839	*/
2840	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2841	if (pExtFeatureLeaf)
2842	{
2843	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2844
2845	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2846	\| X86_CPUID_AMD_FEATURE_EDX_VME
2847	\| X86_CPUID_AMD_FEATURE_EDX_DE
2848	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2849	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2850	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2851	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2852	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2853	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2854	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2855	//\| RT_BIT_32(10) - reserved
2856	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2857	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2858	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2859	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2860	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2861	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2862	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2863	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2864	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2865	//\| RT_BIT_32(18) - reserved
2866	//\| RT_BIT_32(19) - reserved
2867	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2868	//\| RT_BIT_32(21) - reserved
2869	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2870	\| X86_CPUID_AMD_FEATURE_EDX_MMX
2871	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
2872	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
2873	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2874	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2875	//\| RT_BIT_32(28) - reserved
2876	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2877	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2878	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
2879	;
2880	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2881	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2882	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
2883	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2884	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
2885	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2886	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2887	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2888	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2889	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2890	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2891	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
2892	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
2893	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2894	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
2895	//\| RT_BIT_32(14) - reserved
2896	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2897	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2898	//\| RT_BIT_32(17) - reserved
2899	//\| RT_BIT_32(18) - reserved
2900	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2901	//\| RT_BIT_32(20) - reserved
2902	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2903	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2904	//\| RT_BIT_32(23) - reserved
2905	//\| RT_BIT_32(24) - reserved
2906	//\| RT_BIT_32(25) - reserved
2907	//\| RT_BIT_32(26) - reserved
2908	//\| RT_BIT_32(27) - reserved
2909	//\| RT_BIT_32(28) - reserved
2910	//\| RT_BIT_32(29) - reserved
2911	//\| RT_BIT_32(30) - reserved
2912	//\| RT_BIT_32(31) - reserved
2913	;
2914	#ifdef VBOX_WITH_MULTI_CORE
2915	if ( pVM->cCpus > 1
2916	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2917	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2918	#endif
2919
2920	if (pCpum->u8PortableCpuIdLevel > 0)
2921	{
2922	CPUMISAEXTCFG enmSvm = pConfig->fNestedHWVirt ? CPUMISAEXTCFG_ENABLED_SUPPORTED : CPUMISAEXTCFG_DISABLED;
2923	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2924	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM, enmSvm);
2925	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2926	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2927	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2928	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2929	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2930	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2931	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2932	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2933	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2934	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2935	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2936	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2937	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2938	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2939
2940	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2941	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2942	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2943	\| X86_CPUID_AMD_FEATURE_ECX_IBS
2944	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2945	\| X86_CPUID_AMD_FEATURE_ECX_WDT
2946	\| X86_CPUID_AMD_FEATURE_ECX_LWP
2947	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
2948	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2949	\| UINT32_C(0xff964000)
2950	)));
2951	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2952	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2953	\| RT_BIT(18)
2954	\| RT_BIT(19)
2955	\| RT_BIT(21)
2956	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2957	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2958	\| RT_BIT(28)
2959	)));
2960	}
2961
2962	/* Force extended feature bits. */
2963	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2964	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
2965	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2966	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2967	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2968	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2969	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2970	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2971	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2972	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2973	}
2974	pExtFeatureLeaf = NULL; /* Must refetch! */
2975
2976
2977	/* Cpuid 2:
2978	* Intel: (Nondeterministic) Cache and TLB information
2979	* AMD: Reserved
2980	* VIA: Reserved
2981	* Safe to expose.
2982	*/
2983	uint32_t uSubLeaf = 0;
2984	PCPUMCPUIDLEAF pCurLeaf;
2985	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2986	{
2987	if ((pCurLeaf->uEax & 0xff) > 1)
2988	{
2989	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2990	pCurLeaf->uEax &= UINT32_C(0xffffff01);
2991	}
2992	uSubLeaf++;
2993	}
2994
2995	/* Cpuid 3:
2996	* Intel: EAX, EBX - reserved (transmeta uses these)
2997	* ECX, EDX - Processor Serial Number if available, otherwise reserved
2998	* AMD: Reserved
2999	* VIA: Reserved
3000	* Safe to expose
3001	*/
3002	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3003	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3004	{
3005	uSubLeaf = 0;
3006	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3007	{
3008	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3009	if (pCpum->u8PortableCpuIdLevel > 0)
3010	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3011	uSubLeaf++;
3012	}
3013	}
3014
3015	/* Cpuid 4 + ECX:
3016	* Intel: Deterministic Cache Parameters Leaf.
3017	* AMD: Reserved
3018	* VIA: Reserved
3019	* Safe to expose, except for EAX:
3020	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3021	* Bits 31-26: Maximum number of processor cores in this physical package**
3022	* Note: These SMP values are constant regardless of ECX
3023	*/
3024	uSubLeaf = 0;
3025	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3026	{
3027	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3028	#ifdef VBOX_WITH_MULTI_CORE
3029	if ( pVM->cCpus > 1
3030	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3031	{
3032	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3033	/* One logical processor with possibly multiple cores. */
3034	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3035	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3036	}
3037	#endif
3038	uSubLeaf++;
3039	}
3040
3041	/* Cpuid 5: Monitor/mwait Leaf
3042	* Intel: ECX, EDX - reserved
3043	* EAX, EBX - Smallest and largest monitor line size
3044	* AMD: EDX - reserved
3045	* EAX, EBX - Smallest and largest monitor line size
3046	* ECX - extensions (ignored for now)
3047	* VIA: Reserved
3048	* Safe to expose
3049	*/
3050	uSubLeaf = 0;
3051	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3052	{
3053	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3054	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3055	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3056
3057	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3058	if (pConfig->enmMWaitExtensions)
3059	{
3060	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3061	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3062	it shall be part of our power management virtualization model */
3063	#if 0
3064	/* MWAIT sub C-states */
3065	pCurLeaf->uEdx =
3066	(0 << 0) /* 0 in C0 */ \|
3067	(2 << 4) /* 2 in C1 */ \|
3068	(2 << 8) /* 2 in C2 */ \|
3069	(2 << 12) /* 2 in C3 */ \|
3070	(0 << 16) /* 0 in C4 */
3071	;
3072	#endif
3073	}
3074	else
3075	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3076	uSubLeaf++;
3077	}
3078
3079	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3080	* Intel: Various stuff.
3081	* AMD: EAX, EBX, EDX - reserved.
3082	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3083	* present. Same as intel.
3084	* VIA: ??
3085	*
3086	* We clear everything here for now.
3087	*/
3088	cpumR3CpuIdZeroLeaf(pCpum, 6);
3089
3090	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3091	* EAX: Number of sub leaves.
3092	* EBX+ECX+EDX: Feature flags
3093	*
3094	* We only have documentation for one sub-leaf, so clear all other (no need
3095	* to remove them as such, just set them to zero).
3096	*
3097	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3098	* options may require adjusting (i.e. stripping what was enabled).
3099	*/
3100	uSubLeaf = 0;
3101	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3102	{
3103	switch (uSubLeaf)
3104	{
3105	case 0:
3106	{
3107	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3108	pCurLeaf->uEbx &= 0
3109	\| (pConfig->enmFsGsBase ? X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE : 0)
3110	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3111	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3112	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3113	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3114	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3115	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3116	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3117	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3118	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3119	\| (pConfig->enmInvpcid ? X86_CPUID_STEXT_FEATURE_EBX_INVPCID : 0)
3120	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3121	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3122	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3123	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3124	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3125	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3126	//\| RT_BIT(17) - reserved
3127	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3128	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3129	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3130	//\| RT_BIT(21) - reserved
3131	//\| RT_BIT(22) - reserved
3132	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3133	//\| RT_BIT(24) - reserved
3134	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3135	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3136	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3137	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3138	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3139	//\| RT_BIT(30) - reserved
3140	//\| RT_BIT(31) - reserved
3141	;
3142	pCurLeaf->uEcx &= 0
3143	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3144	;
3145	pCurLeaf->uEdx &= 0; /** @todo X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB, X86_CPUID_STEXT_FEATURE_EDX_STIBP and X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP */
3146
3147	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3148	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3149	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3150	{
3151	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3152	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to workaround buggy guests\n"));
3153	}
3154
3155	if (pCpum->u8PortableCpuIdLevel > 0)
3156	{
3157	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3158	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3159	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3160	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3161	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3162	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3163	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3164	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3165	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3166	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3167	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3168	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3169	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3170	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3171	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3172	}
3173
3174	/* Force standard feature bits. */
3175	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3176	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3177	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3178	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3179	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3180	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3181	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3182	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3183	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3184	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3185	break;
3186	}
3187
3188	default:
3189	/* Invalid index, all values are zero. */
3190	pCurLeaf->uEax = 0;
3191	pCurLeaf->uEbx = 0;
3192	pCurLeaf->uEcx = 0;
3193	pCurLeaf->uEdx = 0;
3194	break;
3195	}
3196	uSubLeaf++;
3197	}
3198
3199	/* Cpuid 8: Marked as reserved by Intel and AMD.
3200	* We zero this since we don't know what it may have been used for.
3201	*/
3202	cpumR3CpuIdZeroLeaf(pCpum, 8);
3203
3204	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3205	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3206	* EBX, ECX, EDX - reserved.
3207	* AMD: Reserved
3208	* VIA: ??
3209	*
3210	* We zero this.
3211	*/
3212	cpumR3CpuIdZeroLeaf(pCpum, 9);
3213
3214	/* Cpuid 0xa: Architectural Performance Monitor Features
3215	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3216	* EBX, ECX, EDX - reserved.
3217	* AMD: Reserved
3218	* VIA: ??
3219	*
3220	* We zero this, for now at least.
3221	*/
3222	cpumR3CpuIdZeroLeaf(pCpum, 10);
3223
3224	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3225	* Intel: EAX - APCI ID shift right for next level.
3226	* EBX - Factory configured cores/threads at this level.
3227	* ECX - Level number (same as input) and level type (1,2,0).
3228	* EDX - Extended initial APIC ID.
3229	* AMD: Reserved
3230	* VIA: ??
3231	*/
3232	uSubLeaf = 0;
3233	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3234	{
3235	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3236	{
3237	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3238	if (bLevelType == 1)
3239	{
3240	/* Thread level - we don't do threads at the moment. */
3241	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3242	pCurLeaf->uEbx = 1;
3243	}
3244	else if (bLevelType == 2)
3245	{
3246	/* Core level. */
3247	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3248	#ifdef VBOX_WITH_MULTI_CORE
3249	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3250	pCurLeaf->uEax++;
3251	#endif
3252	pCurLeaf->uEbx = pVM->cCpus;
3253	}
3254	else
3255	{
3256	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3257	pCurLeaf->uEax = 0;
3258	pCurLeaf->uEbx = 0;
3259	pCurLeaf->uEcx = 0;
3260	}
3261	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3262	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3263	}
3264	else
3265	{
3266	pCurLeaf->uEax = 0;
3267	pCurLeaf->uEbx = 0;
3268	pCurLeaf->uEcx = 0;
3269	pCurLeaf->uEdx = 0;
3270	}
3271	uSubLeaf++;
3272	}
3273
3274	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3275	* We zero this since we don't know what it may have been used for.
3276	*/
3277	cpumR3CpuIdZeroLeaf(pCpum, 12);
3278
3279	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3280	* ECX=0: EAX - Valid bits in XCR0[31:0].
3281	* EBX - Maximum state size as per current XCR0 value.
3282	* ECX - Maximum state size for all supported features.
3283	* EDX - Valid bits in XCR0[63:32].
3284	* ECX=1: EAX - Various X-features.
3285	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3286	* ECX - Valid bits in IA32_XSS[31:0].
3287	* EDX - Valid bits in IA32_XSS[63:32].
3288	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3289	* if the bit invalid all four registers are set to zero.
3290	* EAX - The state size for this feature.
3291	* EBX - The state byte offset of this feature.
3292	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3293	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3294	*
3295	* Clear them all as we don't currently implement extended CPU state.
3296	*/
3297	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3298	uint64_t fGuestXcr0Mask = 0;
3299	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3300	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3301	{
3302	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3303	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3304	fGuestXcr0Mask \|= XSAVE_C_YMM;
3305	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3306	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3307	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3308	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3309
3310	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3311	}
3312	pStdFeatureLeaf = NULL;
3313	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3314
3315	/* Work the sub-leaves. */
3316	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3317	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3318	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3319	{
3320	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3321	if (pCurLeaf)
3322	{
3323	if (fGuestXcr0Mask)
3324	{
3325	switch (uSubLeaf)
3326	{
3327	case 0:
3328	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3329	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3330	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3331	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3332	VERR_CPUM_IPE_1);
3333	cbXSaveMaxActual = pCurLeaf->uEcx;
3334	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3335	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3336	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3337	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3338	VERR_CPUM_IPE_2);
3339	continue;
3340	case 1:
3341	pCurLeaf->uEax &= 0;
3342	pCurLeaf->uEcx &= 0;
3343	pCurLeaf->uEdx &= 0;
3344	/** @todo what about checking ebx? */
3345	continue;
3346	default:
3347	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3348	{
3349	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3350	&& pCurLeaf->uEax > 0
3351	&& pCurLeaf->uEbx < cbXSaveMaxActual
3352	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3353	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3354	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3355	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3356	VERR_CPUM_IPE_2);
3357	AssertLogRel(!(pCurLeaf->uEcx & 1));
3358	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3359	pCurLeaf->uEdx = 0; /* it's reserved... */
3360	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3361	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3362	continue;
3363	}
3364	break;
3365	}
3366	}
3367
3368	/* Clear the leaf. */
3369	pCurLeaf->uEax = 0;
3370	pCurLeaf->uEbx = 0;
3371	pCurLeaf->uEcx = 0;
3372	pCurLeaf->uEdx = 0;
3373	}
3374	}
3375
3376	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3377	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3378	{
3379	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3380	if (pCurLeaf)
3381	{
3382	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3383	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3384	pCurLeaf->uEbx = cbXSaveMaxReport;
3385	pCurLeaf->uEcx = cbXSaveMaxReport;
3386	}
3387	}
3388
3389	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3390	* We zero this since we don't know what it may have been used for.
3391	*/
3392	cpumR3CpuIdZeroLeaf(pCpum, 14);
3393
3394	/* Cpuid 0xf + ECX: Platform qualifity of service monitoring (PQM).
3395	* We zero this as we don't currently virtualize PQM.
3396	*/
3397	cpumR3CpuIdZeroLeaf(pCpum, 15);
3398
3399	/* Cpuid 0x10 + ECX: Platform qualifity of service enforcement (PQE).
3400	* We zero this as we don't currently virtualize PQE.
3401	*/
3402	cpumR3CpuIdZeroLeaf(pCpum, 16);
3403
3404	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3405	* We zero this since we don't know what it may have been used for.
3406	*/
3407	cpumR3CpuIdZeroLeaf(pCpum, 17);
3408
3409	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3410	* We zero this as we don't currently virtualize this.
3411	*/
3412	cpumR3CpuIdZeroLeaf(pCpum, 18);
3413
3414	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3415	* We zero this since we don't know what it may have been used for.
3416	*/
3417	cpumR3CpuIdZeroLeaf(pCpum, 19);
3418
3419	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3420	* We zero this as we don't currently virtualize this.
3421	*/
3422	cpumR3CpuIdZeroLeaf(pCpum, 20);
3423
3424	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3425	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3426	* EAX - denominator (unsigned).
3427	* EBX - numerator (unsigned).
3428	* ECX, EDX - reserved.
3429	* AMD: Reserved / undefined / not implemented.
3430	* VIA: Reserved / undefined / not implemented.
3431	* We zero this as we don't currently virtualize this.
3432	*/
3433	cpumR3CpuIdZeroLeaf(pCpum, 21);
3434
3435	/* Cpuid 0x16: Processor frequency info
3436	* Intel: EAX - Core base frequency in MHz.
3437	* EBX - Core maximum frequency in MHz.
3438	* ECX - Bus (reference) frequency in MHz.
3439	* EDX - Reserved.
3440	* AMD: Reserved / undefined / not implemented.
3441	* VIA: Reserved / undefined / not implemented.
3442	* We zero this as we don't currently virtualize this.
3443	*/
3444	cpumR3CpuIdZeroLeaf(pCpum, 22);
3445
3446	/* Cpuid 0x17..0x10000000: Unknown.
3447	* We don't know these and what they mean, so remove them. */
3448	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3449	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3450
3451
3452	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3453	* We remove all these as we're a hypervisor and must provide our own.
3454	*/
3455	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3456	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3457
3458
3459	/* Cpuid 0x80000000 is harmless. */
3460
3461	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3462
3463	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3464
3465	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3466	* Safe to pass on to the guest.
3467	*
3468	* AMD: 0x800000005 L1 cache information
3469	* 0x800000006 L2/L3 cache information
3470	* Intel: 0x800000005 reserved
3471	* 0x800000006 L2 cache information
3472	* VIA: 0x800000005 TLB and L1 cache information
3473	* 0x800000006 L2 cache information
3474	*/
3475
3476	/* Cpuid 0x800000007: Advanced Power Management Information.
3477	* AMD: EAX: Processor feedback capabilities.
3478	* EBX: RAS capabilites.
3479	* ECX: Advanced power monitoring interface.
3480	* EDX: Enhanced power management capabilities.
3481	* Intel: EAX, EBX, ECX - reserved.
3482	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3483	* VIA: Reserved
3484	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3485	*/
3486	uSubLeaf = 0;
3487	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3488	{
3489	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3490	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3491	{
3492	pCurLeaf->uEdx &= 0
3493	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3494	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3495	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3496	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3497	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3498	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3499	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3500	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3501	#if 0 /*
3502	* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
3503	* Linux kernels blindly assume that the AMD performance counters work
3504	* if this is set for 64 bits guests. (Can't really find a CPUID feature
3505	* bit for them though.)
3506	*/
3507	/** @todo need to recheck this with new MSR emulation. */
3508	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3509	#endif
3510	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3511	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3512	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3513	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3514	\| 0;
3515	}
3516	else
3517	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3518	if (pConfig->fInvariantTsc)
3519	pCurLeaf->uEdx \|= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3520	uSubLeaf++;
3521	}
3522
3523	/* Cpuid 0x80000008:
3524	* AMD: EBX, EDX - reserved
3525	* EAX: Virtual/Physical/Guest address Size
3526	* ECX: Number of cores + APICIdCoreIdSize
3527	* Intel: EAX: Virtual/Physical address Size
3528	* EBX, ECX, EDX - reserved
3529	* VIA: EAX: Virtual/Physical address Size
3530	* EBX, ECX, EDX - reserved
3531	*
3532	* We only expose the virtual+pysical address size to the guest atm.
3533	* On AMD we set the core count, but not the apic id stuff as we're
3534	* currently not doing the apic id assignments in a complatible manner.
3535	*/
3536	uSubLeaf = 0;
3537	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3538	{
3539	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3540	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3541	pCurLeaf->uEdx = 0; /* reserved */
3542
3543	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3544	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3545	pCurLeaf->uEcx = 0;
3546	#ifdef VBOX_WITH_MULTI_CORE
3547	if ( pVM->cCpus > 1
3548	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3549	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3550	#endif
3551	uSubLeaf++;
3552	}
3553
3554	/* Cpuid 0x80000009: Reserved
3555	* We zero this since we don't know what it may have been used for.
3556	*/
3557	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3558
3559	/* Cpuid 0x8000000a: SVM Information
3560	* AMD: EAX - SVM revision.
3561	* EBX - Number of ASIDs.
3562	* ECX - Reserved.
3563	* EDX - SVM Feature identification.
3564	*/
3565	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3566	if (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
3567	{
3568	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3569	pSvmFeatureLeaf->uEax = 0x1;
3570	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3571	pSvmFeatureLeaf->uEcx = 0;
3572	pSvmFeatureLeaf->uEdx = 0; /** @todo Support SVM features */
3573	}
3574	else
3575	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3576
3577	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3578	* We clear these as we don't know what purpose they might have. */
3579	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3580	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3581
3582	/* Cpuid 0x80000019: TLB configuration
3583	* Seems to be harmless, pass them thru as is. */
3584
3585	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3586	* Strip anything we don't know what is or addresses feature we don't implement. */
3587	uSubLeaf = 0;
3588	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3589	{
3590	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3591	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3592	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3593	;
3594	pCurLeaf->uEbx = 0; /* reserved */
3595	pCurLeaf->uEcx = 0; /* reserved */
3596	pCurLeaf->uEdx = 0; /* reserved */
3597	uSubLeaf++;
3598	}
3599
3600	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3601	* Clear this as we don't currently virtualize this feature. */
3602	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3603
3604	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3605	* Clear this as we don't currently virtualize this feature. */
3606	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3607
3608	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3609	* We need to sanitize the cores per cache (EAX[25:14]).
3610	*
3611	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3612	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3613	* slightly different meaning.
3614	*/
3615	uSubLeaf = 0;
3616	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3617	{
3618	#ifdef VBOX_WITH_MULTI_CORE
3619	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3620	if (cCores > pVM->cCpus)
3621	cCores = pVM->cCpus;
3622	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3623	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3624	#else
3625	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3626	#endif
3627	uSubLeaf++;
3628	}
3629
3630	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3631	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3632	* setup, we have one compute unit with all the cores in it. Single node.
3633	*/
3634	uSubLeaf = 0;
3635	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3636	{
3637	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3638	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3639	{
3640	#ifdef VBOX_WITH_MULTI_CORE
3641	pCurLeaf->uEbx = pVM->cCpus < 0x100
3642	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3643	#else
3644	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3645	#endif
3646	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3647	}
3648	else
3649	{
3650	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3651	pCurLeaf->uEbx = 0; /* Reserved. */
3652	pCurLeaf->uEcx = 0; /* Reserved. */
3653	}
3654	pCurLeaf->uEdx = 0; /* Reserved. */
3655	uSubLeaf++;
3656	}
3657
3658	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3659	* We don't know these and what they mean, so remove them. */
3660	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3661	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3662
3663	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3664	* Just pass it thru for now. */
3665
3666	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3667	* Just pass it thru for now. */
3668
3669	/* Cpuid 0xc0000000: Centaur stuff.
3670	* Harmless, pass it thru. */
3671
3672	/* Cpuid 0xc0000001: Centaur features.
3673	* VIA: EAX - Family, model, stepping.
3674	* EDX - Centaur extended feature flags. Nothing interesting, except may
3675	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3676	* EBX, ECX - reserved.
3677	* We keep EAX but strips the rest.
3678	*/
3679	uSubLeaf = 0;
3680	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3681	{
3682	pCurLeaf->uEbx = 0;
3683	pCurLeaf->uEcx = 0;
3684	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3685	uSubLeaf++;
3686	}
3687
3688	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3689	* We only have fixed stale values, but should be harmless. */
3690
3691	/* Cpuid 0xc0000003: Reserved.
3692	* We zero this since we don't know what it may have been used for.
3693	*/
3694	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3695
3696	/* Cpuid 0xc0000004: Centaur Performance Info.
3697	* We only have fixed stale values, but should be harmless. */
3698
3699
3700	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3701	* We don't know these and what they mean, so remove them. */
3702	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3703	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3704
3705	return VINF_SUCCESS;
3706	#undef PORTABLE_DISABLE_FEATURE_BIT
3707	#undef PORTABLE_CLEAR_BITS_WHEN
3708	}
3709
3710
3711	/**
3712	* Reads a value in /CPUM/IsaExts/ node.
3713	*
3714	* @returns VBox status code (error message raised).
3715	* @param pVM The cross context VM structure. (For errors.)
3716	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3717	* @param pszValueName The value / extension name.
3718	* @param penmValue Where to return the choice.
3719	* @param enmDefault The default choice.
3720	*/
3721	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3722	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3723	{
3724	/*
3725	* Try integer encoding first.
3726	*/
3727	uint64_t uValue;
3728	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3729	if (RT_SUCCESS(rc))
3730	switch (uValue)
3731	{
3732	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3733	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3734	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3735	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3736	default:
3737	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3738	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3739	pszValueName, uValue);
3740	}
3741	/*
3742	* If missing, use default.
3743	*/
3744	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3745	*penmValue = enmDefault;
3746	else
3747	{
3748	if (rc == VERR_CFGM_NOT_INTEGER)
3749	{
3750	/*
3751	* Not an integer, try read it as a string.
3752	*/
3753	char szValue[32];
3754	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3755	if (RT_SUCCESS(rc))
3756	{
3757	RTStrToLower(szValue);
3758	size_t cchValue = strlen(szValue);
3759	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3760	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3761	*penmValue = CPUMISAEXTCFG_DISABLED;
3762	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3763	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3764	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3765	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3766	else if (EQ("portable"))
3767	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3768	else if (EQ("default") \|\| EQ("def"))
3769	*penmValue = enmDefault;
3770	else
3771	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3772	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3773	pszValueName, uValue);
3774	#undef EQ
3775	}
3776	}
3777	if (RT_FAILURE(rc))
3778	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3779	}
3780	return VINF_SUCCESS;
3781	}
3782
3783
3784	/**
3785	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3786	*
3787	* @returns VBox status code (error message raised).
3788	* @param pVM The cross context VM structure. (For errors.)
3789	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3790	* @param pszValueName The value / extension name.
3791	* @param penmValue Where to return the choice.
3792	* @param enmDefault The default choice.
3793	* @param fAllowed Allowed choice. Applied both to the result and to
3794	* the default value.
3795	*/
3796	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3797	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3798	{
3799	int rc;
3800	if (fAllowed)
3801	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3802	else
3803	{
3804	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3805	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3806	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3807	*penmValue = CPUMISAEXTCFG_DISABLED;
3808	}
3809	return rc;
3810	}
3811
3812
3813	/**
3814	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3815	*
3816	* @returns VBox status code (error message raised).
3817	* @param pVM The cross context VM structure. (For errors.)
3818	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3819	* @param pCpumCfg The /CPUM node (can be NULL).
3820	* @param pszValueName The value / extension name.
3821	* @param penmValue Where to return the choice.
3822	* @param enmDefault The default choice.
3823	*/
3824	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3825	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3826	{
3827	if (CFGMR3Exists(pCpumCfg, pszValueName))
3828	{
3829	if (!CFGMR3Exists(pIsaExts, pszValueName))
3830	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3831	else
3832	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3833	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3834	pszValueName, pszValueName);
3835
3836	bool fLegacy;
3837	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3838	if (RT_SUCCESS(rc))
3839	{
3840	*penmValue = fLegacy;
3841	return VINF_SUCCESS;
3842	}
3843	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3844	}
3845
3846	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3847	}
3848
3849
3850	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3851	{
3852	int rc;
3853
3854	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3855	* When non-zero CPUID features that could cause portability issues will be
3856	* stripped. The higher the value the more features gets stripped. Higher
3857	* values should only be used when older CPUs are involved since it may
3858	* harm performance and maybe also cause problems with specific guests. */
3859	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
3860	AssertLogRelRCReturn(rc, rc);
3861
3862	/** @cfgm{/CPUM/GuestCpuName, string}
3863	* The name of the CPU we're to emulate. The default is the host CPU.
3864	* Note! CPUs other than "host" one is currently unsupported. */
3865	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3866	AssertLogRelRCReturn(rc, rc);
3867
3868	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3869	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3870	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3871	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3872	*/
3873	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3874	AssertLogRelRCReturn(rc, rc);
3875
3876	/** @cfgm{/CPUM/InvariantTsc, boolean, complicated}
3877	* Set the invariant TSC flag in 0x80000007 if true, otherwas take default
3878	* action. By default the flag is passed thru as is from the host CPU, except
3879	* on AMD CPUs where it's suppressed to avoid trouble from linux assuming we
3880	* virtualize performance counters.
3881	*/
3882	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, false);
3883	AssertLogRelRCReturn(rc, rc);
3884
3885	/** @cfgm{/CPUM/ForceVme, boolean, false}
3886	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
3887	* By default the flag is passed thru as is from the host CPU, except
3888	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
3889	* guests and DOS boxes in general.
3890	*/
3891	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
3892	AssertLogRelRCReturn(rc, rc);
3893
3894	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3895	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
3896	* probably going to be a temporary hack, so don't depend on this.
3897	* The 1st byte of the value is the stepping, the 2nd byte value is the model
3898	* number and the 3rd byte value is the family, and the 4th value must be zero.
3899	*/
3900	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3901	AssertLogRelRCReturn(rc, rc);
3902
3903	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3904	* The last standard leaf to keep. The actual last value that is stored in EAX
3905	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3906	* removed. (This works independently of and differently from NT4LeafLimit.)
3907	* The default is usually set to what we're able to reasonably sanitize.
3908	*/
3909	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3910	AssertLogRelRCReturn(rc, rc);
3911
3912	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3913	* The last extended leaf to keep. The actual last value that is stored in EAX
3914	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3915	* leaf are removed. The default is set to what we're able to sanitize.
3916	*/
3917	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3918	AssertLogRelRCReturn(rc, rc);
3919
3920	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3921	* The last extended leaf to keep. The actual last value that is stored in EAX
3922	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3923	* leaf are removed. The default is set to what we're able to sanitize.
3924	*/
3925	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3926	AssertLogRelRCReturn(rc, rc);
3927
3928	#ifdef VBOX_WITH_NESTED_HWVIRT
3929	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
3930	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
3931	* The default is false, and when enabled requires nested paging and AMD-V or
3932	* unrestricted guest mode.
3933	*/
3934	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
3935	AssertLogRelRCReturn(rc, rc);
3936	if ( pConfig->fNestedHWVirt
3937	&& !fNestedPagingAndFullGuestExec)
3938	{
3939	LogRel(("CPUM: Warning! Can't turn on nested VT-x/AMD-V without nested-paging and unrestricted guest execution!\n"));
3940	pConfig->fNestedHWVirt = false;
3941	}
3942	#endif
3943
3944	/*
3945	* Instruction Set Architecture (ISA) Extensions.
3946	*/
3947	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3948	if (pIsaExts)
3949	{
3950	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3951	"CMPXCHG16B"
3952	"\|MONITOR"
3953	"\|MWaitExtensions"
3954	"\|SSE4.1"
3955	"\|SSE4.2"
3956	"\|XSAVE"
3957	"\|AVX"
3958	"\|AVX2"
3959	"\|AESNI"
3960	"\|PCLMUL"
3961	"\|POPCNT"
3962	"\|MOVBE"
3963	"\|RDRAND"
3964	"\|RDSEED"
3965	"\|CLFLUSHOPT"
3966	"\|FSGSBASE"
3967	"\|PCID"
3968	"\|INVPCID"
3969	"\|ABM"
3970	"\|SSE4A"
3971	"\|MISALNSSE"
3972	"\|3DNOWPRF"
3973	"\|AXMMX"
3974	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
3975	if (RT_FAILURE(rc))
3976	return rc;
3977	}
3978
3979	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
3980	* Expose CMPXCHG16B to the guest if supported by the host. For the time
3981	* being the default is to only do this for VMs with nested paging and AMD-V or
3982	* unrestricted guest mode.
3983	*/
3984	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
3985	AssertLogRelRCReturn(rc, rc);
3986
3987	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
3988	* Expose MONITOR/MWAIT instructions to the guest.
3989	*/
3990	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
3991	AssertLogRelRCReturn(rc, rc);
3992
3993	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
3994	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
3995	* break on interrupt feature (bit 1).
3996	*/
3997	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
3998	AssertLogRelRCReturn(rc, rc);
3999
4000	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4001	* Expose SSE4.1 to the guest if available.
4002	*/
4003	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4004	AssertLogRelRCReturn(rc, rc);
4005
4006	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4007	* Expose SSE4.2 to the guest if available.
4008	*/
4009	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4010	AssertLogRelRCReturn(rc, rc);
4011
4012	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4013	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4014	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
4015	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
4016	&& !HMIsLongModeAllowed(pVM)
4017	#endif
4018	;
4019	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4020
4021	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4022	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4023	* default is to only expose this to VMs with nested paging and AMD-V or
4024	* unrestricted guest execution mode. Not possible to force this one without
4025	* host support at the moment.
4026	*/
4027	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4028	fMayHaveXSave /fAllowed/);
4029	AssertLogRelRCReturn(rc, rc);
4030
4031	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4032	* Expose the AVX instruction set extensions to the guest if available and
4033	* XSAVE is exposed too. For the time being the default is to only expose this
4034	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4035	*/
4036	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4037	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4038	AssertLogRelRCReturn(rc, rc);
4039
4040	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4041	* Expose the AVX2 instruction set extensions to the guest if available and
4042	* XSAVE is exposed too. For the time being the default is to only expose this
4043	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4044	*/
4045	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4046	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4047	AssertLogRelRCReturn(rc, rc);
4048
4049	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4050	* Whether to expose the AES instructions to the guest. For the time being the
4051	* default is to only do this for VMs with nested paging and AMD-V or
4052	* unrestricted guest mode.
4053	*/
4054	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4055	AssertLogRelRCReturn(rc, rc);
4056
4057	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4058	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4059	* being the default is to only do this for VMs with nested paging and AMD-V or
4060	* unrestricted guest mode.
4061	*/
4062	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4063	AssertLogRelRCReturn(rc, rc);
4064
4065	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4066	* Whether to expose the POPCNT instructions to the guest. For the time
4067	* being the default is to only do this for VMs with nested paging and AMD-V or
4068	* unrestricted guest mode.
4069	*/
4070	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4071	AssertLogRelRCReturn(rc, rc);
4072
4073	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4074	* Whether to expose the MOVBE instructions to the guest. For the time
4075	* being the default is to only do this for VMs with nested paging and AMD-V or
4076	* unrestricted guest mode.
4077	*/
4078	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4079	AssertLogRelRCReturn(rc, rc);
4080
4081	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4082	* Whether to expose the RDRAND instructions to the guest. For the time being
4083	* the default is to only do this for VMs with nested paging and AMD-V or
4084	* unrestricted guest mode.
4085	*/
4086	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4087	AssertLogRelRCReturn(rc, rc);
4088
4089	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4090	* Whether to expose the RDSEED instructions to the guest. For the time being
4091	* the default is to only do this for VMs with nested paging and AMD-V or
4092	* unrestricted guest mode.
4093	*/
4094	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4095	AssertLogRelRCReturn(rc, rc);
4096
4097	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4098	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4099	* being the default is to only do this for VMs with nested paging and AMD-V or
4100	* unrestricted guest mode.
4101	*/
4102	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4103	AssertLogRelRCReturn(rc, rc);
4104
4105	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4106	* Whether to expose the read/write FSGSBASE instructions to the guest.
4107	*/
4108	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4109	AssertLogRelRCReturn(rc, rc);
4110
4111	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4112	* Whether to expose the PCID feature to the guest.
4113	*/
4114	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4115	AssertLogRelRCReturn(rc, rc);
4116
4117	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4118	* Whether to expose the INVPCID instruction to the guest.
4119	*/
4120	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4121	AssertLogRelRCReturn(rc, rc);
4122
4123
4124	/* AMD: */
4125
4126	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4127	* Whether to expose the AMD ABM instructions to the guest. For the time
4128	* being the default is to only do this for VMs with nested paging and AMD-V or
4129	* unrestricted guest mode.
4130	*/
4131	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4132	AssertLogRelRCReturn(rc, rc);
4133
4134	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4135	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4136	* being the default is to only do this for VMs with nested paging and AMD-V or
4137	* unrestricted guest mode.
4138	*/
4139	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4140	AssertLogRelRCReturn(rc, rc);
4141
4142	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4143	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4144	* the time being the default is to only do this for VMs with nested paging and
4145	* AMD-V or unrestricted guest mode.
4146	*/
4147	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4148	AssertLogRelRCReturn(rc, rc);
4149
4150	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4151	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4152	* For the time being the default is to only do this for VMs with nested paging
4153	* and AMD-V or unrestricted guest mode.
4154	*/
4155	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4156	AssertLogRelRCReturn(rc, rc);
4157
4158	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4159	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4160	* the default is to only do this for VMs with nested paging and AMD-V or
4161	* unrestricted guest mode.
4162	*/
4163	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4164	AssertLogRelRCReturn(rc, rc);
4165
4166	return VINF_SUCCESS;
4167	}
4168
4169
4170	/**
4171	* Initializes the emulated CPU's CPUID & MSR information.
4172	*
4173	* @returns VBox status code.
4174	* @param pVM The cross context VM structure.
4175	*/
4176	int cpumR3InitCpuIdAndMsrs(PVM pVM)
4177	{
4178	PCPUM pCpum = &pVM->cpum.s;
4179	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4180
4181	/*
4182	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4183	* on construction and manage everything from here on.
4184	*/
4185	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
4186	pVM->aCpus[iCpu].cpum.s.fCpuIdApicFeatureVisible = true;
4187
4188	/*
4189	* Read the configuration.
4190	*/
4191	CPUMCPUIDCONFIG Config;
4192	RT_ZERO(Config);
4193
4194	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4195	AssertRCReturn(rc, rc);
4196
4197	/*
4198	* Get the guest CPU data from the database and/or the host.
4199	*
4200	* The CPUID and MSRs are currently living on the regular heap to avoid
4201	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4202	* API for the hyper heap). This means special cleanup considerations.
4203	*/
4204	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4205	if (RT_FAILURE(rc))
4206	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4207	? VMSetError(pVM, rc, RT_SRC_POS,
4208	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4209	: rc;
4210
4211	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4212	{
4213	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4214	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4215	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4216	}
4217	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4218
4219	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4220	* Overrides the guest MSRs.
4221	*/
4222	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4223
4224	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4225	* Overrides the CPUID leaf values (from the host CPU usually) used for
4226	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4227	* values when moving a VM to a different machine. Another use is restricting
4228	* (or extending) the feature set exposed to the guest. */
4229	if (RT_SUCCESS(rc))
4230	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4231
4232	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4233	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4234	"Found unsupported configuration node '/CPUM/CPUID/'. "
4235	"Please use IMachine::setCPUIDLeaf() instead.");
4236
4237	/*
4238	* Pre-explode the CPUID info.
4239	*/
4240	if (RT_SUCCESS(rc))
4241	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
4242
4243	/*
4244	* Sanitize the cpuid information passed on to the guest.
4245	*/
4246	if (RT_SUCCESS(rc))
4247	{
4248	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4249	if (RT_SUCCESS(rc))
4250	{
4251	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4252	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4253	}
4254	}
4255
4256	/*
4257	* MSR fudging.
4258	*/
4259	if (RT_SUCCESS(rc))
4260	{
4261	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4262	* Fudges some common MSRs if not present in the selected CPU database entry.
4263	* This is for trying to keep VMs running when moved between different hosts
4264	* and different CPU vendors. */
4265	bool fEnable;
4266	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4267	if (RT_SUCCESS(rc) && fEnable)
4268	{
4269	rc = cpumR3MsrApplyFudge(pVM);
4270	AssertLogRelRC(rc);
4271	}
4272	}
4273	if (RT_SUCCESS(rc))
4274	{
4275	/*
4276	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4277	* guest CPU features again.
4278	*/
4279	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4280	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4281	pCpum->GuestInfo.cCpuIdLeaves);
4282	RTMemFree(pvFree);
4283
4284	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4285	int rc2 = MMHyperDupMem(pVM, pvFree,
4286	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4287	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4288	RTMemFree(pvFree);
4289	AssertLogRelRCReturn(rc1, rc1);
4290	AssertLogRelRCReturn(rc2, rc2);
4291
4292	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4293	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4294
4295
4296	/*
4297	* Some more configuration that we're applying at the end of everything
4298	* via the CPUMSetGuestCpuIdFeature API.
4299	*/
4300
4301	/* Check if PAE was explicitely enabled by the user. */
4302	bool fEnable;
4303	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4304	AssertRCReturn(rc, rc);
4305	if (fEnable)
4306	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4307
4308	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4309	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4310	AssertRCReturn(rc, rc);
4311	if (fEnable)
4312	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4313
4314	return VINF_SUCCESS;
4315	}
4316
4317	/*
4318	* Failed before switching to hyper heap.
4319	*/
4320	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4321	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4322	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4323	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4324	return rc;
4325	}
4326
4327
4328	/**
4329	* Sets a CPUID feature bit during VM initialization.
4330	*
4331	* Since the CPUID feature bits are generally related to CPU features, other
4332	* CPUM configuration like MSRs can also be modified by calls to this API.
4333	*
4334	* @param pVM The cross context VM structure.
4335	* @param enmFeature The feature to set.
4336	*/
4337	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4338	{
4339	PCPUMCPUIDLEAF pLeaf;
4340	PCPUMMSRRANGE pMsrRange;
4341
4342	switch (enmFeature)
4343	{
4344	/*
4345	* Set the APIC bit in both feature masks.
4346	*/
4347	case CPUMCPUIDFEATURE_APIC:
4348	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4349	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4350	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4351
4352	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4353	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4354	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4355
4356	pVM->cpum.s.GuestFeatures.fApic = 1;
4357
4358	/* Make sure we've got the APICBASE MSR present. */
4359	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4360	if (!pMsrRange)
4361	{
4362	static CPUMMSRRANGE const s_ApicBase =
4363	{
4364	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4365	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4366	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4367	/.szName = / "IA32_APIC_BASE"
4368	};
4369	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4370	AssertLogRelRC(rc);
4371	}
4372
4373	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4374	break;
4375
4376	/*
4377	* Set the x2APIC bit in the standard feature mask.
4378	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4379	*/
4380	case CPUMCPUIDFEATURE_X2APIC:
4381	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4382	if (pLeaf)
4383	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4384	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4385
4386	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4387	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4388	if (pMsrRange)
4389	{
4390	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4391	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4392	}
4393
4394	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4395	break;
4396
4397	/*
4398	* Set the sysenter/sysexit bit in the standard feature mask.
4399	* Assumes the caller knows what it's doing! (host must support these)
4400	*/
4401	case CPUMCPUIDFEATURE_SEP:
4402	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4403	{
4404	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4405	return;
4406	}
4407
4408	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4409	if (pLeaf)
4410	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4411	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4412	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4413	break;
4414
4415	/*
4416	* Set the syscall/sysret bit in the extended feature mask.
4417	* Assumes the caller knows what it's doing! (host must support these)
4418	*/
4419	case CPUMCPUIDFEATURE_SYSCALL:
4420	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4421	if ( !pLeaf
4422	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4423	{
4424	#if HC_ARCH_BITS == 32
4425	/* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit
4426	mode by Intel, even when the cpu is capable of doing so in
4427	64-bit mode. Long mode requires syscall support. */
4428	if (!pVM->cpum.s.HostFeatures.fLongMode)
4429	#endif
4430	{
4431	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4432	return;
4433	}
4434	}
4435
4436	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4437	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4438	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4439	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4440	break;
4441
4442	/*
4443	* Set the PAE bit in both feature masks.
4444	* Assumes the caller knows what it's doing! (host must support these)
4445	*/
4446	case CPUMCPUIDFEATURE_PAE:
4447	if (!pVM->cpum.s.HostFeatures.fPae)
4448	{
4449	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4450	return;
4451	}
4452
4453	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4454	if (pLeaf)
4455	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4456
4457	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4458	if ( pLeaf
4459	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4460	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4461
4462	pVM->cpum.s.GuestFeatures.fPae = 1;
4463	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4464	break;
4465
4466	/*
4467	* Set the LONG MODE bit in the extended feature mask.
4468	* Assumes the caller knows what it's doing! (host must support these)
4469	*/
4470	case CPUMCPUIDFEATURE_LONG_MODE:
4471	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4472	if ( !pLeaf
4473	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4474	{
4475	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4476	return;
4477	}
4478
4479	/* Valid for both Intel and AMD. */
4480	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4481	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4482	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4483	break;
4484
4485	/*
4486	* Set the NX/XD bit in the extended feature mask.
4487	* Assumes the caller knows what it's doing! (host must support these)
4488	*/
4489	case CPUMCPUIDFEATURE_NX:
4490	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4491	if ( !pLeaf
4492	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4493	{
4494	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4495	return;
4496	}
4497
4498	/* Valid for both Intel and AMD. */
4499	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4500	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4501	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4502	break;
4503
4504
4505	/*
4506	* Set the LAHF/SAHF support in 64-bit mode.
4507	* Assumes the caller knows what it's doing! (host must support this)
4508	*/
4509	case CPUMCPUIDFEATURE_LAHF:
4510	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4511	if ( !pLeaf
4512	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4513	{
4514	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4515	return;
4516	}
4517
4518	/* Valid for both Intel and AMD. */
4519	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4520	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4521	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4522	break;
4523
4524	/*
4525	* Set the page attribute table bit. This is alternative page level
4526	* cache control that doesn't much matter when everything is
4527	* virtualized, though it may when passing thru device memory.
4528	*/
4529	case CPUMCPUIDFEATURE_PAT:
4530	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4531	if (pLeaf)
4532	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4533
4534	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4535	if ( pLeaf
4536	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4537	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4538
4539	pVM->cpum.s.GuestFeatures.fPat = 1;
4540	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4541	break;
4542
4543	/*
4544	* Set the RDTSCP support bit.
4545	* Assumes the caller knows what it's doing! (host must support this)
4546	*/
4547	case CPUMCPUIDFEATURE_RDTSCP:
4548	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4549	if ( !pLeaf
4550	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4551	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4552	{
4553	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4554	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4555	return;
4556	}
4557
4558	/* Valid for both Intel and AMD. */
4559	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4560	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4561	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4562	break;
4563
4564	/*
4565	* Set the Hypervisor Present bit in the standard feature mask.
4566	*/
4567	case CPUMCPUIDFEATURE_HVP:
4568	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4569	if (pLeaf)
4570	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4571	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4572	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4573	break;
4574
4575	/*
4576	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4577	* This currently includes the Present bit and MWAITBREAK bit as well.
4578	*/
4579	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4580	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4581	if ( !pLeaf
4582	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4583	{
4584	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4585	return;
4586	}
4587
4588	/* Valid for both Intel and AMD. */
4589	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4590	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4591	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4592	break;
4593
4594	default:
4595	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4596	break;
4597	}
4598
4599	/** @todo can probably kill this as this API is now init time only... */
4600	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4601	{
4602	PVMCPU pVCpu = &pVM->aCpus[i];
4603	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4604	}
4605	}
4606
4607
4608	/**
4609	* Queries a CPUID feature bit.
4610	*
4611	* @returns boolean for feature presence
4612	* @param pVM The cross context VM structure.
4613	* @param enmFeature The feature to query.
4614	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4615	*/
4616	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4617	{
4618	switch (enmFeature)
4619	{
4620	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4621	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4622	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4623	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4624	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4625	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4626	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4627	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4628	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4629	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4630	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4631	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4632
4633	case CPUMCPUIDFEATURE_INVALID:
4634	case CPUMCPUIDFEATURE_32BIT_HACK:
4635	break;
4636	}
4637	AssertFailed();
4638	return false;
4639	}
4640
4641
4642	/**
4643	* Clears a CPUID feature bit.
4644	*
4645	* @param pVM The cross context VM structure.
4646	* @param enmFeature The feature to clear.
4647	*
4648	* @deprecated Probably better to default the feature to disabled and only allow
4649	* setting (enabling) it during construction.
4650	*/
4651	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4652	{
4653	PCPUMCPUIDLEAF pLeaf;
4654	switch (enmFeature)
4655	{
4656	case CPUMCPUIDFEATURE_APIC:
4657	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
4658	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4659	if (pLeaf)
4660	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
4661
4662	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4663	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4664	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4665
4666	pVM->cpum.s.GuestFeatures.fApic = 0;
4667	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4668	break;
4669
4670	case CPUMCPUIDFEATURE_X2APIC:
4671	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4672	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4673	if (pLeaf)
4674	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
4675	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
4676	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
4677	break;
4678
4679	case CPUMCPUIDFEATURE_PAE:
4680	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4681	if (pLeaf)
4682	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
4683
4684	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4685	if ( pLeaf
4686	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4687	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
4688
4689	pVM->cpum.s.GuestFeatures.fPae = 0;
4690	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
4691	break;
4692
4693	case CPUMCPUIDFEATURE_PAT:
4694	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4695	if (pLeaf)
4696	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
4697
4698	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4699	if ( pLeaf
4700	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4701	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
4702
4703	pVM->cpum.s.GuestFeatures.fPat = 0;
4704	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
4705	break;
4706
4707	case CPUMCPUIDFEATURE_LONG_MODE:
4708	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4709	if (pLeaf)
4710	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4711	pVM->cpum.s.GuestFeatures.fLongMode = 0;
4712	break;
4713
4714	case CPUMCPUIDFEATURE_LAHF:
4715	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4716	if (pLeaf)
4717	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4718	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
4719	break;
4720
4721	case CPUMCPUIDFEATURE_RDTSCP:
4722	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4723	if (pLeaf)
4724	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4725	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
4726	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
4727	break;
4728
4729	case CPUMCPUIDFEATURE_HVP:
4730	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4731	if (pLeaf)
4732	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
4733	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
4734	break;
4735
4736	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4737	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4738	if (pLeaf)
4739	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
4740	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
4741	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
4742	break;
4743
4744	default:
4745	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4746	break;
4747	}
4748
4749	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4750	{
4751	PVMCPU pVCpu = &pVM->aCpus[i];
4752	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4753	}
4754	}
4755
4756
4757
4758	/*
4759	*
4760	*
4761	* Saved state related code.
4762	* Saved state related code.
4763	* Saved state related code.
4764	*
4765	*
4766	*/
4767
4768	/**
4769	* Called both in pass 0 and the final pass.
4770	*
4771	* @param pVM The cross context VM structure.
4772	* @param pSSM The saved state handle.
4773	*/
4774	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4775	{
4776	/*
4777	* Save all the CPU ID leaves.
4778	*/
4779	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4780	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4781	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4782	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4783
4784	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4785
4786	/*
4787	* Save a good portion of the raw CPU IDs as well as they may come in
4788	* handy when validating features for raw mode.
4789	*/
4790	CPUMCPUID aRawStd[16];
4791	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4792	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4793	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4794	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4795
4796	CPUMCPUID aRawExt[32];
4797	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4798	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4799	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4800	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4801	}
4802
4803
4804	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4805	{
4806	uint32_t cCpuIds;
4807	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4808	if (RT_SUCCESS(rc))
4809	{
4810	if (cCpuIds < 64)
4811	{
4812	for (uint32_t i = 0; i < cCpuIds; i++)
4813	{
4814	CPUMCPUID CpuId;
4815	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4816	if (RT_FAILURE(rc))
4817	break;
4818
4819	CPUMCPUIDLEAF NewLeaf;
4820	NewLeaf.uLeaf = uBase + i;
4821	NewLeaf.uSubLeaf = 0;
4822	NewLeaf.fSubLeafMask = 0;
4823	NewLeaf.uEax = CpuId.uEax;
4824	NewLeaf.uEbx = CpuId.uEbx;
4825	NewLeaf.uEcx = CpuId.uEcx;
4826	NewLeaf.uEdx = CpuId.uEdx;
4827	NewLeaf.fFlags = 0;
4828	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4829	}
4830	}
4831	else
4832	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4833	}
4834	if (RT_FAILURE(rc))
4835	{
4836	RTMemFree(*ppaLeaves);
4837	*ppaLeaves = NULL;
4838	*pcLeaves = 0;
4839	}
4840	return rc;
4841	}
4842
4843
4844	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4845	{
4846	*ppaLeaves = NULL;
4847	*pcLeaves = 0;
4848
4849	int rc;
4850	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4851	{
4852	/*
4853	* The new format. Starts by declaring the leave size and count.
4854	*/
4855	uint32_t cbLeaf;
4856	SSMR3GetU32(pSSM, &cbLeaf);
4857	uint32_t cLeaves;
4858	rc = SSMR3GetU32(pSSM, &cLeaves);
4859	if (RT_SUCCESS(rc))
4860	{
4861	if (cbLeaf == sizeof(**ppaLeaves))
4862	{
4863	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4864	{
4865	/*
4866	* Load the leaves one by one.
4867	*
4868	* The uPrev stuff is a kludge for working around a week worth of bad saved
4869	* states during the CPUID revamp in March 2015. We saved too many leaves
4870	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4871	* garbage entires at the end of the array when restoring. We also had
4872	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
4873	* this kludge doesn't deal correctly with that, but who cares...
4874	*/
4875	uint32_t uPrev = 0;
4876	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4877	{
4878	CPUMCPUIDLEAF Leaf;
4879	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
4880	if (RT_SUCCESS(rc))
4881	{
4882	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
4883	\|\| Leaf.uLeaf >= uPrev)
4884	{
4885	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4886	uPrev = Leaf.uLeaf;
4887	}
4888	else
4889	uPrev = UINT32_MAX;
4890	}
4891	}
4892	}
4893	else
4894	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
4895	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
4896	}
4897	else
4898	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
4899	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
4900	}
4901	}
4902	else
4903	{
4904	/*
4905	* The old format with its three inflexible arrays.
4906	*/
4907	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
4908	if (RT_SUCCESS(rc))
4909	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
4910	if (RT_SUCCESS(rc))
4911	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
4912	if (RT_SUCCESS(rc))
4913	{
4914	/*
4915	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
4916	*/
4917	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
4918	if ( pLeaf
4919	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
4920	{
4921	CPUMCPUIDLEAF Leaf;
4922	Leaf.uLeaf = 4;
4923	Leaf.fSubLeafMask = UINT32_MAX;
4924	Leaf.uSubLeaf = 0;
4925	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
4926	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
4927	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
4928	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
4929	\| UINT32_C(63); /* system coherency line size - 1 */
4930	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
4931	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
4932	\| (UINT32_C(1) << 5) /* cache level */
4933	\| UINT32_C(1); /* cache type (data) */
4934	Leaf.fFlags = 0;
4935	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4936	if (RT_SUCCESS(rc))
4937	{
4938	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
4939	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4940	}
4941	if (RT_SUCCESS(rc))
4942	{
4943	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
4944	Leaf.uEcx = 4095; /* sets - 1 */
4945	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
4946	Leaf.uEbx \|= UINT32_C(23) << 22;
4947	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
4948	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
4949	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
4950	Leaf.uEax \|= UINT32_C(2) << 5;
4951	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4952	}
4953	}
4954	}
4955	}
4956	return rc;
4957	}
4958
4959
4960	/**
4961	* Loads the CPU ID leaves saved by pass 0, inner worker.
4962	*
4963	* @returns VBox status code.
4964	* @param pVM The cross context VM structure.
4965	* @param pSSM The saved state handle.
4966	* @param uVersion The format version.
4967	* @param paLeaves Guest CPUID leaves loaded from the state.
4968	* @param cLeaves The number of leaves in @a paLeaves.
4969	*/
4970	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
4971	{
4972	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4973
4974	/*
4975	* Continue loading the state into stack buffers.
4976	*/
4977	CPUMCPUID GuestDefCpuId;
4978	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
4979	AssertRCReturn(rc, rc);
4980
4981	CPUMCPUID aRawStd[16];
4982	uint32_t cRawStd;
4983	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
4984	if (cRawStd > RT_ELEMENTS(aRawStd))
4985	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4986	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
4987	AssertRCReturn(rc, rc);
4988	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
4989	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4990
4991	CPUMCPUID aRawExt[32];
4992	uint32_t cRawExt;
4993	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
4994	if (cRawExt > RT_ELEMENTS(aRawExt))
4995	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4996	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
4997	AssertRCReturn(rc, rc);
4998	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
4999	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5000
5001	/*
5002	* Get the raw CPU IDs for the current host.
5003	*/
5004	CPUMCPUID aHostRawStd[16];
5005	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5006	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5007
5008	CPUMCPUID aHostRawExt[32];
5009	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5010	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5011	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5012
5013	/*
5014	* Get the host and guest overrides so we don't reject the state because
5015	* some feature was enabled thru these interfaces.
5016	* Note! We currently only need the feature leaves, so skip rest.
5017	*/
5018	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5019	CPUMCPUID aHostOverrideStd[2];
5020	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5021	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5022
5023	CPUMCPUID aHostOverrideExt[2];
5024	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5025	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5026
5027	/*
5028	* This can be skipped.
5029	*/
5030	bool fStrictCpuIdChecks;
5031	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5032
5033	/*
5034	* Define a bunch of macros for simplifying the santizing/checking code below.
5035	*/
5036	/* Generic expression + failure message. */
5037	#define CPUID_CHECK_RET(expr, fmt) \
5038	do { \
5039	if (!(expr)) \
5040	{ \
5041	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5042	if (fStrictCpuIdChecks) \
5043	{ \
5044	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5045	RTStrFree(pszMsg); \
5046	return rcCpuid; \
5047	} \
5048	LogRel(("CPUM: %s\n", pszMsg)); \
5049	RTStrFree(pszMsg); \
5050	} \
5051	} while (0)
5052	#define CPUID_CHECK_WRN(expr, fmt) \
5053	do { \
5054	if (!(expr)) \
5055	LogRel(fmt); \
5056	} while (0)
5057
5058	/* For comparing two values and bitch if they differs. */
5059	#define CPUID_CHECK2_RET(what, host, saved) \
5060	do { \
5061	if ((host) != (saved)) \
5062	{ \
5063	if (fStrictCpuIdChecks) \
5064	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5065	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5066	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5067	} \
5068	} while (0)
5069	#define CPUID_CHECK2_WRN(what, host, saved) \
5070	do { \
5071	if ((host) != (saved)) \
5072	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5073	} while (0)
5074
5075	/* For checking raw cpu features (raw mode). */
5076	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5077	do { \
5078	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5079	{ \
5080	if (fStrictCpuIdChecks) \
5081	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5082	N_(#bit " mismatch: host=%d saved=%d"), \
5083	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5084	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5085	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5086	} \
5087	} while (0)
5088	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5089	do { \
5090	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5091	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5092	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5093	} while (0)
5094	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5095
5096	/* For checking guest features. */
5097	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5098	do { \
5099	if ( (aGuestCpuId##set [1].reg & bit) \
5100	&& !(aHostRaw##set [1].reg & bit) \
5101	&& !(aHostOverride##set [1].reg & bit) \
5102	) \
5103	{ \
5104	if (fStrictCpuIdChecks) \
5105	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5106	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5107	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5108	} \
5109	} while (0)
5110	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5111	do { \
5112	if ( (aGuestCpuId##set [1].reg & bit) \
5113	&& !(aHostRaw##set [1].reg & bit) \
5114	&& !(aHostOverride##set [1].reg & bit) \
5115	) \
5116	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5117	} while (0)
5118	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5119	do { \
5120	if ( (aGuestCpuId##set [1].reg & bit) \
5121	&& !(aHostRaw##set [1].reg & bit) \
5122	&& !(aHostOverride##set [1].reg & bit) \
5123	) \
5124	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5125	} while (0)
5126	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5127
5128	/* For checking guest features if AMD guest CPU. */
5129	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5130	do { \
5131	if ( (aGuestCpuId##set [1].reg & bit) \
5132	&& fGuestAmd \
5133	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5134	&& !(aHostOverride##set [1].reg & bit) \
5135	) \
5136	{ \
5137	if (fStrictCpuIdChecks) \
5138	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5139	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5140	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5141	} \
5142	} while (0)
5143	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5144	do { \
5145	if ( (aGuestCpuId##set [1].reg & bit) \
5146	&& fGuestAmd \
5147	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5148	&& !(aHostOverride##set [1].reg & bit) \
5149	) \
5150	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5151	} while (0)
5152	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5153	do { \
5154	if ( (aGuestCpuId##set [1].reg & bit) \
5155	&& fGuestAmd \
5156	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5157	&& !(aHostOverride##set [1].reg & bit) \
5158	) \
5159	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5160	} while (0)
5161	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5162
5163	/* For checking AMD features which have a corresponding bit in the standard
5164	range. (Intel defines very few bits in the extended feature sets.) */
5165	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5166	do { \
5167	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5168	&& !(fHostAmd \
5169	? aHostRawExt[1].reg & (ExtBit) \
5170	: aHostRawStd[1].reg & (StdBit)) \
5171	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5172	) \
5173	{ \
5174	if (fStrictCpuIdChecks) \
5175	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5176	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5177	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5178	} \
5179	} while (0)
5180	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5181	do { \
5182	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5183	&& !(fHostAmd \
5184	? aHostRawExt[1].reg & (ExtBit) \
5185	: aHostRawStd[1].reg & (StdBit)) \
5186	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5187	) \
5188	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5189	} while (0)
5190	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5191	do { \
5192	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5193	&& !(fHostAmd \
5194	? aHostRawExt[1].reg & (ExtBit) \
5195	: aHostRawStd[1].reg & (StdBit)) \
5196	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5197	) \
5198	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5199	} while (0)
5200	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5201
5202	/*
5203	* For raw-mode we'll require that the CPUs are very similar since we don't
5204	* intercept CPUID instructions for user mode applications.
5205	*/
5206	if (!HMIsEnabled(pVM))
5207	{
5208	/* CPUID(0) */
5209	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
5210	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
5211	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
5212	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5213	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
5214	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
5215	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
5216	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
5217	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5218
5219	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
5220
5221	/* CPUID(1).eax */
5222	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
5223	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
5224	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
5225
5226	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
5227	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
5228	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
5229
5230	/* CPUID(1).ecx */
5231	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
5232	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
5233	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
5234	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5235	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
5236	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
5237	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
5238	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
5239	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
5240	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
5241	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
5242	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
5243	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
5244	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
5245	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
5246	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
5247	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5248	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5249	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
5250	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
5251	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
5252	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5253	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
5254	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
5255	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5256	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
5257	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
5258	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5259	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
5260	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5261	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5262	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
5263
5264	/* CPUID(1).edx */
5265	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5266	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5267	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
5268	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5269	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
5270	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
5271	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5272	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5273	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
5274	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5275	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5276	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5277	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5278	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5279	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5280	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
5281	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5282	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5283	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5284	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
5285	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5286	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
5287	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
5288	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
5289	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
5290	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
5291	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
5292	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
5293	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
5294	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
5295	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
5296	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
5297
5298	/* CPUID(2) - config, mostly about caches. ignore. */
5299	/* CPUID(3) - processor serial number. ignore. */
5300	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
5301	/* CPUID(5) - mwait/monitor config. ignore. */
5302	/* CPUID(6) - power management. ignore. */
5303	/* CPUID(7) - ???. ignore. */
5304	/* CPUID(8) - ???. ignore. */
5305	/* CPUID(9) - DCA. ignore for now. */
5306	/* CPUID(a) - PeMo info. ignore for now. */
5307	/* CPUID(b) - topology info - takes ECX as input. ignore. */
5308
5309	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
5310	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
5311	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
5312	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
5313	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
5314	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
5315	{
5316	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
5317	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
5318	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
5319	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
5320	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
5321	}
5322
5323	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
5324	Note! Intel have/is marking many of the fields here as reserved. We
5325	will verify them as if it's an AMD CPU. */
5326	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
5327	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
5328	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
5329	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
5330	{
5331	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
5332	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
5333	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
5334	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5335	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
5336	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
5337	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
5338
5339	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
5340	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
5341	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
5342	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
5343	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
5344	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5345
5346	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
5347	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
5348	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
5349	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
5350
5351	/* CPUID(0x80000001).ecx */
5352	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
5353	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
5354	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
5355	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
5356	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
5357	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
5358	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
5359	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
5360	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
5361	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
5362	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
5363	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
5364	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
5365	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
5366	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5367	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5368	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5369	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5370	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5371	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5372	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5373	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5374	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5375	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5376	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5377	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5378	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5379	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5380	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5381	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5382	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5383	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5384
5385	/* CPUID(0x80000001).edx */
5386	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
5387	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
5388	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
5389	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
5390	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
5391	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
5392	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
5393	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
5394	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
5395	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
5396	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5397	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
5398	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
5399	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
5400	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
5401	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
5402	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
5403	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
5404	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5405	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5406	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5407	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
5408	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5409	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
5410	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
5411	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5412	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5413	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5414	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
5415	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5416	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5417	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5418
5419	/** @todo verify the rest as well. */
5420	}
5421	}
5422
5423
5424
5425	/*
5426	* Verify that we can support the features already exposed to the guest on
5427	* this host.
5428	*
5429	* Most of the features we're emulating requires intercepting instruction
5430	* and doing it the slow way, so there is no need to warn when they aren't
5431	* present in the host CPU. Thus we use IGN instead of EMU on these.
5432	*
5433	* Trailing comments:
5434	* "EMU" - Possible to emulate, could be lots of work and very slow.
5435	* "EMU?" - Can this be emulated?
5436	*/
5437	CPUMCPUID aGuestCpuIdStd[2];
5438	RT_ZERO(aGuestCpuIdStd);
5439	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5440
5441	/* CPUID(1).ecx */
5442	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5443	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5444	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5445	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5446	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5447	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5448	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5449	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5450	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5451	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5452	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5453	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5454	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5455	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5456	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5457	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5458	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5459	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5460	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5461	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5462	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5463	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5464	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5465	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5466	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5467	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5468	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5469	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5470	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5471	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5472	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5473	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5474
5475	/* CPUID(1).edx */
5476	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5477	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5478	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5479	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5480	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5481	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5482	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5483	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5484	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5485	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5486	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5487	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5488	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5489	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5490	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5491	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5492	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5493	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5494	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5495	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5496	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5497	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5498	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5499	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5500	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5501	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5502	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5503	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5504	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5505	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5506	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5507	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5508
5509	/* CPUID(0x80000000). */
5510	CPUMCPUID aGuestCpuIdExt[2];
5511	RT_ZERO(aGuestCpuIdExt);
5512	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5513	{
5514	/** @todo deal with no 0x80000001 on the host. */
5515	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5516	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5517
5518	/* CPUID(0x80000001).ecx */
5519	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5520	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5521	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5522	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5523	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5524	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5525	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5526	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5527	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5528	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5529	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5530	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5531	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5532	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5533	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5534	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5535	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5536	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5537	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5538	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5539	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5540	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5541	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5542	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5543	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5544	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5545	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5546	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5547	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5548	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5549	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5550	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5551
5552	/* CPUID(0x80000001).edx */
5553	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5554	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5555	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5556	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5557	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5558	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5559	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5560	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5561	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5562	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5563	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5564	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5565	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5566	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5567	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5568	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5569	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5570	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5571	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5572	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5573	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5574	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5575	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5576	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5577	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5578	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5579	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5580	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5581	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5582	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5583	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5584	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5585	}
5586
5587	/** @todo check leaf 7 */
5588
5589	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5590	* ECX=0: EAX - Valid bits in XCR0[31:0].
5591	* EBX - Maximum state size as per current XCR0 value.
5592	* ECX - Maximum state size for all supported features.
5593	* EDX - Valid bits in XCR0[63:32].
5594	* ECX=1: EAX - Various X-features.
5595	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5596	* ECX - Valid bits in IA32_XSS[31:0].
5597	* EDX - Valid bits in IA32_XSS[63:32].
5598	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5599	* if the bit invalid all four registers are set to zero.
5600	* EAX - The state size for this feature.
5601	* EBX - The state byte offset of this feature.
5602	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5603	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5604	*/
5605	uint64_t fGuestXcr0Mask = 0;
5606	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5607	if ( pCurLeaf
5608	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5609	&& ( pCurLeaf->uEax
5610	\|\| pCurLeaf->uEbx
5611	\|\| pCurLeaf->uEcx
5612	\|\| pCurLeaf->uEdx) )
5613	{
5614	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5615	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5616	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5617	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5618	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5619	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5620	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5621	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5622
5623	/* We don't support any additional features yet. */
5624	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5625	if (pCurLeaf && pCurLeaf->uEax)
5626	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5627	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5628	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5629	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5630	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5631	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5632
5633
5634	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5635	{
5636	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5637	if (pCurLeaf)
5638	{
5639	/* If advertised, the state component offset and size must match the one used by host. */
5640	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5641	{
5642	CPUMCPUID RawHost;
5643	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5644	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5645	if ( RawHost.uEbx != pCurLeaf->uEbx
5646	\|\| RawHost.uEax != pCurLeaf->uEax)
5647	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5648	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5649	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5650	}
5651	}
5652	}
5653	}
5654	/* Clear leaf 0xd just in case we're loading an old state... */
5655	else if (pCurLeaf)
5656	{
5657	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5658	{
5659	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5660	if (pCurLeaf)
5661	{
5662	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5663	\|\| ( pCurLeaf->uEax == 0
5664	&& pCurLeaf->uEbx == 0
5665	&& pCurLeaf->uEcx == 0
5666	&& pCurLeaf->uEdx == 0),
5667	("uVersion=%#x; %#x %#x %#x %#x\n",
5668	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5669	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5670	}
5671	}
5672	}
5673
5674	/* Update the fXStateGuestMask value for the VM. */
5675	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5676	{
5677	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5678	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5679	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5680	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5681	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5682	}
5683
5684	#undef CPUID_CHECK_RET
5685	#undef CPUID_CHECK_WRN
5686	#undef CPUID_CHECK2_RET
5687	#undef CPUID_CHECK2_WRN
5688	#undef CPUID_RAW_FEATURE_RET
5689	#undef CPUID_RAW_FEATURE_WRN
5690	#undef CPUID_RAW_FEATURE_IGN
5691	#undef CPUID_GST_FEATURE_RET
5692	#undef CPUID_GST_FEATURE_WRN
5693	#undef CPUID_GST_FEATURE_EMU
5694	#undef CPUID_GST_FEATURE_IGN
5695	#undef CPUID_GST_FEATURE2_RET
5696	#undef CPUID_GST_FEATURE2_WRN
5697	#undef CPUID_GST_FEATURE2_EMU
5698	#undef CPUID_GST_FEATURE2_IGN
5699	#undef CPUID_GST_AMD_FEATURE_RET
5700	#undef CPUID_GST_AMD_FEATURE_WRN
5701	#undef CPUID_GST_AMD_FEATURE_EMU
5702	#undef CPUID_GST_AMD_FEATURE_IGN
5703
5704	/*
5705	* We're good, commit the CPU ID leaves.
5706	*/
5707	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5708	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5709	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5710	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
5711	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5712	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
5713	AssertLogRelRCReturn(rc, rc);
5714
5715	return VINF_SUCCESS;
5716	}
5717
5718
5719	/**
5720	* Loads the CPU ID leaves saved by pass 0.
5721	*
5722	* @returns VBox status code.
5723	* @param pVM The cross context VM structure.
5724	* @param pSSM The saved state handle.
5725	* @param uVersion The format version.
5726	*/
5727	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5728	{
5729	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5730
5731	/*
5732	* Load the CPUID leaves array first and call worker to do the rest, just so
5733	* we can free the memory when we need to without ending up in column 1000.
5734	*/
5735	PCPUMCPUIDLEAF paLeaves;
5736	uint32_t cLeaves;
5737	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5738	AssertRC(rc);
5739	if (RT_SUCCESS(rc))
5740	{
5741	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
5742	RTMemFree(paLeaves);
5743	}
5744	return rc;
5745	}
5746
5747
5748
5749	/**
5750	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5751	*
5752	* @returns VBox status code.
5753	* @param pVM The cross context VM structure.
5754	* @param pSSM The saved state handle.
5755	* @param uVersion The format version.
5756	*/
5757	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5758	{
5759	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5760
5761	/*
5762	* Restore the CPUID leaves.
5763	*
5764	* Note that we support restoring less than the current amount of standard
5765	* leaves because we've been allowed more is newer version of VBox.
5766	*/
5767	uint32_t cElements;
5768	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5769	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5770	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5771	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5772
5773	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5774	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5775	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5776	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5777
5778	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5779	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5780	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5781	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5782
5783	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5784
5785	/*
5786	* Check that the basic cpuid id information is unchanged.
5787	*/
5788	/** @todo we should check the 64 bits capabilities too! */
5789	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5790	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5791	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5792	uint32_t au32CpuIdSaved[8];
5793	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5794	if (RT_SUCCESS(rc))
5795	{
5796	/* Ignore CPU stepping. */
5797	au32CpuId[4] &= 0xfffffff0;
5798	au32CpuIdSaved[4] &= 0xfffffff0;
5799
5800	/* Ignore APIC ID (AMD specs). */
5801	au32CpuId[5] &= ~0xff000000;
5802	au32CpuIdSaved[5] &= ~0xff000000;
5803
5804	/* Ignore the number of Logical CPUs (AMD specs). */
5805	au32CpuId[5] &= ~0x00ff0000;
5806	au32CpuIdSaved[5] &= ~0x00ff0000;
5807
5808	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5809	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5810	\| X86_CPUID_FEATURE_ECX_VMX
5811	\| X86_CPUID_FEATURE_ECX_SMX
5812	\| X86_CPUID_FEATURE_ECX_EST
5813	\| X86_CPUID_FEATURE_ECX_TM2
5814	\| X86_CPUID_FEATURE_ECX_CNTXID
5815	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5816	\| X86_CPUID_FEATURE_ECX_PDCM
5817	\| X86_CPUID_FEATURE_ECX_DCA
5818	\| X86_CPUID_FEATURE_ECX_X2APIC
5819	);
5820	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5821	\| X86_CPUID_FEATURE_ECX_VMX
5822	\| X86_CPUID_FEATURE_ECX_SMX
5823	\| X86_CPUID_FEATURE_ECX_EST
5824	\| X86_CPUID_FEATURE_ECX_TM2
5825	\| X86_CPUID_FEATURE_ECX_CNTXID
5826	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5827	\| X86_CPUID_FEATURE_ECX_PDCM
5828	\| X86_CPUID_FEATURE_ECX_DCA
5829	\| X86_CPUID_FEATURE_ECX_X2APIC
5830	);
5831
5832	/* Make sure we don't forget to update the masks when enabling
5833	* features in the future.
5834	*/
5835	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5836	( X86_CPUID_FEATURE_ECX_DTES64
5837	\| X86_CPUID_FEATURE_ECX_VMX
5838	\| X86_CPUID_FEATURE_ECX_SMX
5839	\| X86_CPUID_FEATURE_ECX_EST
5840	\| X86_CPUID_FEATURE_ECX_TM2
5841	\| X86_CPUID_FEATURE_ECX_CNTXID
5842	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5843	\| X86_CPUID_FEATURE_ECX_PDCM
5844	\| X86_CPUID_FEATURE_ECX_DCA
5845	\| X86_CPUID_FEATURE_ECX_X2APIC
5846	)));
5847	/* do the compare */
5848	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5849	{
5850	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5851	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5852	"Saved=%.*Rhxs\n"
5853	"Real =%.*Rhxs\n",
5854	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5855	sizeof(au32CpuId), au32CpuId));
5856	else
5857	{
5858	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5859	"Saved=%.*Rhxs\n"
5860	"Real =%.*Rhxs\n",
5861	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5862	sizeof(au32CpuId), au32CpuId));
5863	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5864	}
5865	}
5866	}
5867
5868	return rc;
5869	}
5870
5871
5872
5873	/*
5874	*
5875	*
5876	* CPUID Info Handler.
5877	* CPUID Info Handler.
5878	* CPUID Info Handler.
5879	*
5880	*
5881	*/
5882
5883
5884
5885	/**
5886	* Get L1 cache / TLS associativity.
5887	*/
5888	static const char getCacheAss(unsigned u, char pszBuf)
5889	{
5890	if (u == 0)
5891	return "res0 ";
5892	if (u == 1)
5893	return "direct";
5894	if (u == 255)
5895	return "fully";
5896	if (u >= 256)
5897	return "???";
5898
5899	RTStrPrintf(pszBuf, 16, "%d way", u);
5900	return pszBuf;
5901	}
5902
5903
5904	/**
5905	* Get L2 cache associativity.
5906	*/
5907	const char *getL2CacheAss(unsigned u)
5908	{
5909	switch (u)
5910	{
5911	case 0: return "off ";
5912	case 1: return "direct";
5913	case 2: return "2 way ";
5914	case 3: return "res3 ";
5915	case 4: return "4 way ";
5916	case 5: return "res5 ";
5917	case 6: return "8 way ";
5918	case 7: return "res7 ";
5919	case 8: return "16 way";
5920	case 9: return "res9 ";
5921	case 10: return "res10 ";
5922	case 11: return "res11 ";
5923	case 12: return "res12 ";
5924	case 13: return "res13 ";
5925	case 14: return "res14 ";
5926	case 15: return "fully ";
5927	default: return "????";
5928	}
5929	}
5930
5931
5932	/** CPUID(1).EDX field descriptions. */
5933	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
5934	{
5935	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5936	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5937	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5938	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5939	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5940	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
5941	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5942	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5943	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5944	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5945	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
5946	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5947	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5948	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5949	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5950	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5951	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5952	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
5953	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
5954	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
5955	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
5956	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5957	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
5958	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
5959	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
5960	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
5961	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
5962	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
5963	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
5964	DBGFREGSUBFIELD_TERMINATOR()
5965	};
5966
5967	/** CPUID(1).ECX field descriptions. */
5968	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
5969	{
5970	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
5971	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
5972	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
5973	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
5974	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
5975	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
5976	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
5977	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
5978	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
5979	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
5980	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
5981	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
5982	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
5983	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
5984	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
5985	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
5986	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
5987	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
5988	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
5989	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
5990	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
5991	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
5992	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
5993	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
5994	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
5995	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
5996	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
5997	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
5998	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
5999	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6000	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6001	DBGFREGSUBFIELD_TERMINATOR()
6002	};
6003
6004	/** CPUID(7,0).EBX field descriptions. */
6005	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6006	{
6007	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6008	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6009	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6010	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6011	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6012	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6013	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6014	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6015	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6016	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6017	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6018	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6019	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6020	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6021	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6022	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6023	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6024	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6025	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6026	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6027	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6028	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6029	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6030	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6031	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6032	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6033	DBGFREGSUBFIELD_TERMINATOR()
6034	};
6035
6036	/** CPUID(7,0).ECX field descriptions. */
6037	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6038	{
6039	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6040	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6041	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6042	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6043	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6044	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6045	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6046	DBGFREGSUBFIELD_TERMINATOR()
6047	};
6048
6049	/** CPUID(7,0).EDX field descriptions. */
6050	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6051	{
6052	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6053	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6054	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6055	DBGFREGSUBFIELD_TERMINATOR()
6056	};
6057
6058
6059	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6060	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6061	{
6062	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6063	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6064	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6065	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6066	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6067	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6068	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6069	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6070	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6071	DBGFREGSUBFIELD_TERMINATOR()
6072	};
6073
6074	/** CPUID(13,1).EAX field descriptions. */
6075	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6076	{
6077	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6078	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6079	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6080	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6081	DBGFREGSUBFIELD_TERMINATOR()
6082	};
6083
6084
6085	/** CPUID(0x80000001,0).EDX field descriptions. */
6086	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6087	{
6088	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6089	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6090	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6091	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6092	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6093	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6094	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6095	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6096	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6097	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6098	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6099	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6100	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6101	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6102	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6103	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6104	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6105	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6106	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6107	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6108	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6109	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6110	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6111	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6112	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6113	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6114	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6115	DBGFREGSUBFIELD_TERMINATOR()
6116	};
6117
6118	/** CPUID(0x80000001,0).ECX field descriptions. */
6119	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6120	{
6121	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6122	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6123	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6124	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6125	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6126	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6127	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6128	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6129	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6130	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6131	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6132	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6133	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6134	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6135	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6136	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6137	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6138	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6139	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6140	DBGFREGSUBFIELD_TERMINATOR()
6141	};
6142
6143	/** CPUID(0x80000008,0).EBX field descriptions. */
6144	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6145	{
6146	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6147	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6148	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6149	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6150	DBGFREGSUBFIELD_TERMINATOR()
6151	};
6152
6153
6154	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6155	const char *pszLeadIn, uint32_t cchWidth)
6156	{
6157	if (pszLeadIn)
6158	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6159
6160	for (uint32_t iBit = 0; iBit < 32; iBit++)
6161	if (RT_BIT_32(iBit) & uVal)
6162	{
6163	while ( pDesc->pszName != NULL
6164	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6165	pDesc++;
6166	if ( pDesc->pszName != NULL
6167	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6168	{
6169	if (pDesc->cBits == 1)
6170	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6171	else
6172	{
6173	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6174	if (pDesc->cBits < 32)
6175	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6176	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6177	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6178	}
6179	}
6180	else
6181	pHlp->pfnPrintf(pHlp, " %u", iBit);
6182	}
6183	if (pszLeadIn)
6184	pHlp->pfnPrintf(pHlp, "\n");
6185	}
6186
6187
6188	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6189	const char *pszLeadIn, uint32_t cchWidth)
6190	{
6191	if (pszLeadIn)
6192	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6193
6194	for (uint32_t iBit = 0; iBit < 64; iBit++)
6195	if (RT_BIT_64(iBit) & uVal)
6196	{
6197	while ( pDesc->pszName != NULL
6198	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6199	pDesc++;
6200	if ( pDesc->pszName != NULL
6201	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6202	{
6203	if (pDesc->cBits == 1)
6204	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6205	else
6206	{
6207	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6208	if (pDesc->cBits < 64)
6209	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6210	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6211	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6212	}
6213	}
6214	else
6215	pHlp->pfnPrintf(pHlp, " %u", iBit);
6216	}
6217	if (pszLeadIn)
6218	pHlp->pfnPrintf(pHlp, "\n");
6219	}
6220
6221
6222	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6223	const char *pszLeadIn, uint32_t cchWidth)
6224	{
6225	if (!uVal)
6226	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6227	else
6228	{
6229	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6230	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6231	pHlp->pfnPrintf(pHlp, " )\n");
6232	}
6233	}
6234
6235
6236	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6237	uint32_t cchWidth)
6238	{
6239	uint32_t uCombined = uVal1 \| uVal2;
6240	for (uint32_t iBit = 0; iBit < 32; iBit++)
6241	if ( (RT_BIT_32(iBit) & uCombined)
6242	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6243	{
6244	while ( pDesc->pszName != NULL
6245	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6246	pDesc++;
6247
6248	if ( pDesc->pszName != NULL
6249	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6250	{
6251	size_t cchMnemonic = strlen(pDesc->pszName);
6252	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6253	size_t cchDesc = strlen(pszDesc);
6254	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6255	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6256	if (pDesc->cBits < 32)
6257	{
6258	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6259	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6260	}
6261
6262	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6263	pDesc->pszName, pszDesc,
6264	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6265	uFieldValue1, uFieldValue2);
6266
6267	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6268	pDesc++;
6269	}
6270	else
6271	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6272	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6273	}
6274	}
6275
6276
6277	/**
6278	* Produces a detailed summary of standard leaf 0x00000001.
6279	*
6280	* @param pHlp The info helper functions.
6281	* @param pCurLeaf The 0x00000001 leaf.
6282	* @param fVerbose Whether to be very verbose or not.
6283	* @param fIntel Set if intel CPU.
6284	*/
6285	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6286	{
6287	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6288	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6289	uint32_t uEAX = pCurLeaf->uEax;
6290	uint32_t uEBX = pCurLeaf->uEbx;
6291
6292	pHlp->pfnPrintf(pHlp,
6293	"%36s %2d \tExtended: %d \tEffective: %d\n"
6294	"%36s %2d \tExtended: %d \tEffective: %d\n"
6295	"%36s %d\n"
6296	"%36s %d (%s)\n"
6297	"%36s %#04x\n"
6298	"%36s %d\n"
6299	"%36s %d\n"
6300	"%36s %#04x\n"
6301	,
6302	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6303	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6304	"Stepping:", ASMGetCpuStepping(uEAX),
6305	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6306	"APIC ID:", (uEBX >> 24) & 0xff,
6307	"Logical CPUs:",(uEBX >> 16) & 0xff,
6308	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6309	"Brand ID:", (uEBX >> 0) & 0xff);
6310	if (fVerbose)
6311	{
6312	CPUMCPUID Host;
6313	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6314	pHlp->pfnPrintf(pHlp, "Features\n");
6315	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6316	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6317	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6318	}
6319	else
6320	{
6321	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6322	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6323	}
6324	}
6325
6326
6327	/**
6328	* Produces a detailed summary of standard leaf 0x00000007.
6329	*
6330	* @param pHlp The info helper functions.
6331	* @param paLeaves The CPUID leaves array.
6332	* @param cLeaves The number of leaves in the array.
6333	* @param pCurLeaf The first 0x00000007 leaf.
6334	* @param fVerbose Whether to be very verbose or not.
6335	*/
6336	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6337	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6338	{
6339	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6340	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6341	for (;;)
6342	{
6343	CPUMCPUID Host;
6344	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6345
6346	switch (pCurLeaf->uSubLeaf)
6347	{
6348	case 0:
6349	if (fVerbose)
6350	{
6351	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6352	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6353	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6354	if (pCurLeaf->uEdx \|\| Host.uEdx)
6355	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6356	}
6357	else
6358	{
6359	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6360	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6361	if (pCurLeaf->uEdx)
6362	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6363	}
6364	break;
6365
6366	default:
6367	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6368	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6369	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6370	break;
6371
6372	}
6373
6374	/* advance. */
6375	pCurLeaf++;
6376	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6377	\|\| pCurLeaf->uLeaf != 0x7)
6378	break;
6379	}
6380	}
6381
6382
6383	/**
6384	* Produces a detailed summary of standard leaf 0x0000000d.
6385	*
6386	* @param pHlp The info helper functions.
6387	* @param paLeaves The CPUID leaves array.
6388	* @param cLeaves The number of leaves in the array.
6389	* @param pCurLeaf The first 0x00000007 leaf.
6390	* @param fVerbose Whether to be very verbose or not.
6391	*/
6392	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6393	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6394	{
6395	RT_NOREF_PV(fVerbose);
6396	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6397	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6398	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6399	{
6400	CPUMCPUID Host;
6401	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6402
6403	switch (uSubLeaf)
6404	{
6405	case 0:
6406	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6407	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6408	pCurLeaf->uEbx, pCurLeaf->uEcx);
6409	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6410
6411	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6412	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6413	"Valid XCR0 bits, guest:", 42);
6414	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6415	"Valid XCR0 bits, host:", 42);
6416	break;
6417
6418	case 1:
6419	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6420	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6421	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6422
6423	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6424	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6425	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6426
6427	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6428	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6429	" Valid IA32_XSS bits, guest:", 42);
6430	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6431	" Valid IA32_XSS bits, host:", 42);
6432	break;
6433
6434	default:
6435	if ( pCurLeaf
6436	&& pCurLeaf->uSubLeaf == uSubLeaf
6437	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6438	{
6439	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6440	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6441	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6442	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6443	if (pCurLeaf->uEdx)
6444	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6445	pHlp->pfnPrintf(pHlp, " --");
6446	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6447	pHlp->pfnPrintf(pHlp, "\n");
6448	}
6449	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6450	{
6451	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6452	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6453	if (Host.uEcx & ~RT_BIT_32(0))
6454	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6455	if (Host.uEdx)
6456	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6457	pHlp->pfnPrintf(pHlp, " --");
6458	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6459	pHlp->pfnPrintf(pHlp, "\n");
6460	}
6461	break;
6462
6463	}
6464
6465	/* advance. */
6466	if (pCurLeaf)
6467	{
6468	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6469	&& pCurLeaf->uSubLeaf <= uSubLeaf
6470	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6471	pCurLeaf++;
6472	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6473	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6474	pCurLeaf = NULL;
6475	}
6476	}
6477	}
6478
6479
6480	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6481	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6482	{
6483	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6484	&& pCurLeaf->uLeaf <= uUpToLeaf)
6485	{
6486	pHlp->pfnPrintf(pHlp,
6487	" %s\n"
6488	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6489	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6490	&& pCurLeaf->uLeaf <= uUpToLeaf)
6491	{
6492	CPUMCPUID Host;
6493	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6494	pHlp->pfnPrintf(pHlp,
6495	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6496	"Hst: %08x %08x %08x %08x\n",
6497	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6498	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6499	pCurLeaf++;
6500	}
6501	}
6502
6503	return pCurLeaf;
6504	}
6505
6506
6507	/**
6508	* Display the guest CpuId leaves.
6509	*
6510	* @param pVM The cross context VM structure.
6511	* @param pHlp The info helper functions.
6512	* @param pszArgs "terse", "default" or "verbose".
6513	*/
6514	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6515	{
6516	/*
6517	* Parse the argument.
6518	*/
6519	unsigned iVerbosity = 1;
6520	if (pszArgs)
6521	{
6522	pszArgs = RTStrStripL(pszArgs);
6523	if (!strcmp(pszArgs, "terse"))
6524	iVerbosity--;
6525	else if (!strcmp(pszArgs, "verbose"))
6526	iVerbosity++;
6527	}
6528
6529	uint32_t uLeaf;
6530	CPUMCPUID Host;
6531	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6532	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6533	PCCPUMCPUIDLEAF pCurLeaf;
6534	PCCPUMCPUIDLEAF pNextLeaf;
6535	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6536	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6537	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6538
6539	/*
6540	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6541	*/
6542	uint32_t cHstMax = ASMCpuId_EAX(0);
6543	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6544	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6545	pHlp->pfnPrintf(pHlp,
6546	" Raw Standard CPUID Leaves\n"
6547	" Leaf/sub-leaf eax ebx ecx edx\n");
6548	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6549	{
6550	uint32_t cMaxSubLeaves = 1;
6551	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6552	cMaxSubLeaves = 16;
6553	else if (uLeaf == 0xd)
6554	cMaxSubLeaves = 128;
6555
6556	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6557	{
6558	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6559	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6560	&& pCurLeaf->uLeaf == uLeaf
6561	&& pCurLeaf->uSubLeaf == uSubLeaf)
6562	{
6563	pHlp->pfnPrintf(pHlp,
6564	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6565	"Hst: %08x %08x %08x %08x\n",
6566	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6567	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6568	pCurLeaf++;
6569	}
6570	else if ( uLeaf != 0xd
6571	\|\| uSubLeaf <= 1
6572	\|\| Host.uEbx != 0 )
6573	pHlp->pfnPrintf(pHlp,
6574	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6575	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6576
6577	/* Done? */
6578	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6579	\|\| pCurLeaf->uLeaf != uLeaf)
6580	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6581	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6582	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6583	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6584	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6585	)
6586	)
6587	break;
6588	}
6589	}
6590	pNextLeaf = pCurLeaf;
6591
6592	/*
6593	* If verbose, decode it.
6594	*/
6595	if (iVerbosity && paLeaves[0].uLeaf == 0)
6596	pHlp->pfnPrintf(pHlp,
6597	"%36s %.04s%.04s%.04s\n"
6598	"%36s 0x00000000-%#010x\n"
6599	,
6600	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6601	"Supports:", paLeaves[0].uEax);
6602
6603	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6604	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6605
6606	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6607	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6608
6609	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6610	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6611
6612	pCurLeaf = pNextLeaf;
6613
6614	/*
6615	* Hypervisor leaves.
6616	*
6617	* Unlike most of the other leaves reported, the guest hypervisor leaves
6618	* aren't a subset of the host CPUID bits.
6619	*/
6620	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6621
6622	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6623	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6624	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6625	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6626	cMax = RT_MAX(cHstMax, cGstMax);
6627	if (cMax >= UINT32_C(0x40000000))
6628	{
6629	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6630
6631	/** @todo dump these in more detail. */
6632
6633	pCurLeaf = pNextLeaf;
6634	}
6635
6636
6637	/*
6638	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6639	* Implemented after AMD specs.
6640	*/
6641	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6642
6643	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6644	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6645	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6646	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6647	cMax = RT_MAX(cHstMax, cGstMax);
6648	if (cMax >= UINT32_C(0x80000000))
6649	{
6650
6651	pHlp->pfnPrintf(pHlp,
6652	" Raw Extended CPUID Leaves\n"
6653	" Leaf/sub-leaf eax ebx ecx edx\n");
6654	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6655	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6656	{
6657	uint32_t cMaxSubLeaves = 1;
6658	if (uLeaf == UINT32_C(0x8000001d))
6659	cMaxSubLeaves = 16;
6660
6661	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6662	{
6663	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6664	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6665	&& pCurLeaf->uLeaf == uLeaf
6666	&& pCurLeaf->uSubLeaf == uSubLeaf)
6667	{
6668	pHlp->pfnPrintf(pHlp,
6669	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6670	"Hst: %08x %08x %08x %08x\n",
6671	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6672	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6673	pCurLeaf++;
6674	}
6675	else if ( uLeaf != 0xd
6676	\|\| uSubLeaf <= 1
6677	\|\| Host.uEbx != 0 )
6678	pHlp->pfnPrintf(pHlp,
6679	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6680	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6681
6682	/* Done? */
6683	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6684	\|\| pCurLeaf->uLeaf != uLeaf)
6685	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6686	break;
6687	}
6688	}
6689	pNextLeaf = pCurLeaf;
6690
6691	/*
6692	* Understandable output
6693	*/
6694	if (iVerbosity)
6695	pHlp->pfnPrintf(pHlp,
6696	"Ext Name: %.4s%.4s%.4s\n"
6697	"Ext Supports: 0x80000000-%#010x\n",
6698	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6699
6700	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6701	if (iVerbosity && pCurLeaf)
6702	{
6703	uint32_t uEAX = pCurLeaf->uEax;
6704	pHlp->pfnPrintf(pHlp,
6705	"Family: %d \tExtended: %d \tEffective: %d\n"
6706	"Model: %d \tExtended: %d \tEffective: %d\n"
6707	"Stepping: %d\n"
6708	"Brand ID: %#05x\n",
6709	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6710	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6711	ASMGetCpuStepping(uEAX),
6712	pCurLeaf->uEbx & 0xfff);
6713
6714	if (iVerbosity == 1)
6715	{
6716	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6717	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6718	}
6719	else
6720	{
6721	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6722	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6723	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6724	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6725	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6726	}
6727	}
6728
6729	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6730	{
6731	char szString[443+1] = {0};
6732	uint32_t pu32 = (uint32_t )szString;
6733	*pu32++ = pCurLeaf->uEax;
6734	*pu32++ = pCurLeaf->uEbx;
6735	*pu32++ = pCurLeaf->uEcx;
6736	*pu32++ = pCurLeaf->uEdx;
6737	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6738	if (pCurLeaf)
6739	{
6740	*pu32++ = pCurLeaf->uEax;
6741	*pu32++ = pCurLeaf->uEbx;
6742	*pu32++ = pCurLeaf->uEcx;
6743	*pu32++ = pCurLeaf->uEdx;
6744	}
6745	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6746	if (pCurLeaf)
6747	{
6748	*pu32++ = pCurLeaf->uEax;
6749	*pu32++ = pCurLeaf->uEbx;
6750	*pu32++ = pCurLeaf->uEcx;
6751	*pu32++ = pCurLeaf->uEdx;
6752	}
6753	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6754	}
6755
6756	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6757	{
6758	uint32_t uEAX = pCurLeaf->uEax;
6759	uint32_t uEBX = pCurLeaf->uEbx;
6760	uint32_t uECX = pCurLeaf->uEcx;
6761	uint32_t uEDX = pCurLeaf->uEdx;
6762	char sz1[32];
6763	char sz2[32];
6764
6765	pHlp->pfnPrintf(pHlp,
6766	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6767	"TLB 2/4M Data: %s %3d entries\n",
6768	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6769	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6770	pHlp->pfnPrintf(pHlp,
6771	"TLB 4K Instr/Uni: %s %3d entries\n"
6772	"TLB 4K Data: %s %3d entries\n",
6773	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6774	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6775	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6776	"L1 Instr Cache Lines Per Tag: %d\n"
6777	"L1 Instr Cache Associativity: %s\n"
6778	"L1 Instr Cache Size: %d KB\n",
6779	(uEDX >> 0) & 0xff,
6780	(uEDX >> 8) & 0xff,
6781	getCacheAss((uEDX >> 16) & 0xff, sz1),
6782	(uEDX >> 24) & 0xff);
6783	pHlp->pfnPrintf(pHlp,
6784	"L1 Data Cache Line Size: %d bytes\n"
6785	"L1 Data Cache Lines Per Tag: %d\n"
6786	"L1 Data Cache Associativity: %s\n"
6787	"L1 Data Cache Size: %d KB\n",
6788	(uECX >> 0) & 0xff,
6789	(uECX >> 8) & 0xff,
6790	getCacheAss((uECX >> 16) & 0xff, sz1),
6791	(uECX >> 24) & 0xff);
6792	}
6793
6794	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6795	{
6796	uint32_t uEAX = pCurLeaf->uEax;
6797	uint32_t uEBX = pCurLeaf->uEbx;
6798	uint32_t uEDX = pCurLeaf->uEdx;
6799
6800	pHlp->pfnPrintf(pHlp,
6801	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6802	"L2 TLB 2/4M Data: %s %4d entries\n",
6803	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6804	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6805	pHlp->pfnPrintf(pHlp,
6806	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6807	"L2 TLB 4K Data: %s %4d entries\n",
6808	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6809	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6810	pHlp->pfnPrintf(pHlp,
6811	"L2 Cache Line Size: %d bytes\n"
6812	"L2 Cache Lines Per Tag: %d\n"
6813	"L2 Cache Associativity: %s\n"
6814	"L2 Cache Size: %d KB\n",
6815	(uEDX >> 0) & 0xff,
6816	(uEDX >> 8) & 0xf,
6817	getL2CacheAss((uEDX >> 12) & 0xf),
6818	(uEDX >> 16) & 0xffff);
6819	}
6820
6821	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
6822	{
6823	uint32_t uEDX = pCurLeaf->uEdx;
6824
6825	pHlp->pfnPrintf(pHlp, "APM Features: ");
6826	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
6827	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
6828	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
6829	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
6830	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
6831	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
6832	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " MC");
6833	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " HWPSTATE");
6834	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TscInvariant");
6835	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " CPB");
6836	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " EffFreqRO");
6837	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PFI");
6838	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PA");
6839	for (unsigned iBit = 13; iBit < 32; iBit++)
6840	if (uEDX & RT_BIT(iBit))
6841	pHlp->pfnPrintf(pHlp, " %d", iBit);
6842	pHlp->pfnPrintf(pHlp, "\n");
6843
6844	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6845	pHlp->pfnPrintf(pHlp, "Host Invariant-TSC support: %RTbool\n",
6846	cHstMax >= UINT32_C(0x80000007) && (Host.uEdx & RT_BIT(8)));
6847
6848	}
6849
6850	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
6851	if (pCurLeaf != NULL)
6852	{
6853	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
6854	{
6855	if (iVerbosity < 1)
6856	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
6857	else
6858	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
6859	}
6860
6861	if (iVerbosity)
6862	{
6863	uint32_t uEAX = pCurLeaf->uEax;
6864	uint32_t uECX = pCurLeaf->uEcx;
6865
6866	pHlp->pfnPrintf(pHlp,
6867	"Physical Address Width: %d bits\n"
6868	"Virtual Address Width: %d bits\n"
6869	"Guest Physical Address Width: %d bits\n",
6870	(uEAX >> 0) & 0xff,
6871	(uEAX >> 8) & 0xff,
6872	(uEAX >> 16) & 0xff);
6873	pHlp->pfnPrintf(pHlp,
6874	"Physical Core Count: %d\n",
6875	((uECX >> 0) & 0xff) + 1);
6876	}
6877	}
6878
6879	pCurLeaf = pNextLeaf;
6880	}
6881
6882
6883
6884	/*
6885	* Centaur.
6886	*/
6887	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
6888
6889	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6890	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
6891	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
6892	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
6893	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
6894	cMax = RT_MAX(cHstMax, cGstMax);
6895	if (cMax >= UINT32_C(0xc0000000))
6896	{
6897	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
6898
6899	/*
6900	* Understandable output
6901	*/
6902	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
6903	pHlp->pfnPrintf(pHlp,
6904	"Centaur Supports: 0xc0000000-%#010x\n",
6905	pCurLeaf->uEax);
6906
6907	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
6908	{
6909	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6910	uint32_t uEdxGst = pCurLeaf->uEdx;
6911	uint32_t uEdxHst = Host.uEdx;
6912
6913	if (iVerbosity == 1)
6914	{
6915	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
6916	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
6917	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
6918	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
6919	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
6920	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
6921	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
6922	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
6923	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
6924	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6925	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
6926	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
6927	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
6928	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
6929	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
6930	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
6931	for (unsigned iBit = 14; iBit < 32; iBit++)
6932	if (uEdxGst & RT_BIT(iBit))
6933	pHlp->pfnPrintf(pHlp, " %d", iBit);
6934	pHlp->pfnPrintf(pHlp, "\n");
6935	}
6936	else
6937	{
6938	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
6939	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
6940	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
6941	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
6942	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
6943	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
6944	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
6945	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
6946	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
6947	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6948	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
6949	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
6950	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
6951	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
6952	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
6953	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
6954	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
6955	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
6956	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
6957	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
6958	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
6959	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
6960	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
6961	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
6962	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
6963	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
6964	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
6965	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
6966	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
6967	for (unsigned iBit = 27; iBit < 32; iBit++)
6968	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
6969	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
6970	pHlp->pfnPrintf(pHlp, "\n");
6971	}
6972	}
6973
6974	pCurLeaf = pNextLeaf;
6975	}
6976
6977	/*
6978	* The remainder.
6979	*/
6980	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
6981	}
6982
6983
6984
6985
6986
6987	/*
6988	*
6989	*
6990	* PATM interfaces.
6991	* PATM interfaces.
6992	* PATM interfaces.
6993	*
6994	*
6995	*/
6996
6997
6998	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
6999	/** @name Patchmanager CPUID legacy table APIs
7000	* @{
7001	*/
7002
7003	/**
7004	* Gets a pointer to the default CPUID leaf.
7005	*
7006	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
7007	* @param pVM The cross context VM structure.
7008	* @remark Intended for PATM only.
7009	*/
7010	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
7011	{
7012	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
7013	}
7014
7015
7016	/**
7017	* Gets a number of standard CPUID leaves (PATM only).
7018	*
7019	* @returns Number of leaves.
7020	* @param pVM The cross context VM structure.
7021	* @remark Intended for PATM - legacy, don't use in new code.
7022	*/
7023	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
7024	{
7025	RT_NOREF_PV(pVM);
7026	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
7027	}
7028
7029
7030	/**
7031	* Gets a number of extended CPUID leaves (PATM only).
7032	*
7033	* @returns Number of leaves.
7034	* @param pVM The cross context VM structure.
7035	* @remark Intended for PATM - legacy, don't use in new code.
7036	*/
7037	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
7038	{
7039	RT_NOREF_PV(pVM);
7040	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
7041	}
7042
7043
7044	/**
7045	* Gets a number of centaur CPUID leaves.
7046	*
7047	* @returns Number of leaves.
7048	* @param pVM The cross context VM structure.
7049	* @remark Intended for PATM - legacy, don't use in new code.
7050	*/
7051	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
7052	{
7053	RT_NOREF_PV(pVM);
7054	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
7055	}
7056
7057
7058	/**
7059	* Gets a pointer to the array of standard CPUID leaves.
7060	*
7061	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
7062	*
7063	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
7064	* @param pVM The cross context VM structure.
7065	* @remark Intended for PATM - legacy, don't use in new code.
7066	*/
7067	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
7068	{
7069	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
7070	}
7071
7072
7073	/**
7074	* Gets a pointer to the array of extended CPUID leaves.
7075	*
7076	* CPUMGetGuestCpuIdExtMax() give the size of the array.
7077	*
7078	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
7079	* @param pVM The cross context VM structure.
7080	* @remark Intended for PATM - legacy, don't use in new code.
7081	*/
7082	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
7083	{
7084	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
7085	}
7086
7087
7088	/**
7089	* Gets a pointer to the array of centaur CPUID leaves.
7090	*
7091	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
7092	*
7093	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
7094	* @param pVM The cross context VM structure.
7095	* @remark Intended for PATM - legacy, don't use in new code.
7096	*/
7097	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
7098	{
7099	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
7100	}
7101
7102	/** @} */
7103	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
7104
7105	#endif /* VBOX_IN_VMM */
7106

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 70720

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