CPUMR3CpuId.cpp@ 71289

Last change on this file since 71289 was 71166, checked in by vboxsync, 7 years ago
VMM/CPUM: Nested Hw.virt: Try expose SVM flush-by-ASID to the guest.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 334.7 KB

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1	/* $Id: CPUMR3CpuId.cpp 71166 2018-03-02 05:48:44Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/ssm.h>
27	#include "CPUMInternal.h"
28	#include <VBox/vmm/vm.h>
29	#include <VBox/vmm/mm.h>
30	#include <VBox/sup.h>
31
32	#include <VBox/err.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/ctype.h>
35	#include <iprt/mem.h>
36	#include <iprt/string.h>
37
38
39	/*********************************************************************************************************************************
40	* Defined Constants And Macros *
41	*********************************************************************************************************************************/
42	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
43	#define CPUM_CPUID_MAX_LEAVES 2048
44	/* Max size we accept for the XSAVE area. */
45	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
46	/* Min size we accept for the XSAVE area. */
47	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
48
49
50	/*********************************************************************************************************************************
51	* Global Variables *
52	*********************************************************************************************************************************/
53	/**
54	* The intel pentium family.
55	*/
56	static const CPUMMICROARCH g_aenmIntelFamily06[] =
57	{
58	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
59	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
60	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
61	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
62	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
63	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
64	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
65	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
66	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
67	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
68	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
69	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
70	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
71	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
72	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
73	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
74	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
80	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
81	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
82	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
83	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
85	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
86	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
87	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
88	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
89	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
90	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
91	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
96	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
97	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
98	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
99	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
101	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
102	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
103	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
104	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
105	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
106	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
107	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
112	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
113	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
114	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
115	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
117	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
118	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
119	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
120	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
121	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
122	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
123	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
128	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
130	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
131	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
133	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
134	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
135	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
136	/* [78(0x4e)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed */
137	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / unconfirmed, Broadwell-E */
138	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
139	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu */
144	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
145	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
146	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
147	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
149	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
150	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
151	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
152	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
153	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
154	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
155	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
158	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
159	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
160	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
161	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
162	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
163	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
164	/[106(0x6a)] = / kCpumMicroarch_Intel_Unknown,
165	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
166	/[108(0x6c)] = / kCpumMicroarch_Intel_Unknown,
167	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
168	/[110(0x6e)] = / kCpumMicroarch_Intel_Unknown,
169	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
170	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
171	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
172	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
173	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
174	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
175	/[117(0x75)] = / kCpumMicroarch_Intel_Unknown,
176	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
177	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
178	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
179	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
180	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
181	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
182	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
183	/[125(0x7d)] = / kCpumMicroarch_Intel_Unknown,
184	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
185	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
186	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
187	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
188	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
189	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
190	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
191	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
192	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
193	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
194	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
195	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
196	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
197	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
198	/[140(0x8c)] = / kCpumMicroarch_Intel_Unknown,
199	/[141(0x8d)] = / kCpumMicroarch_Intel_Unknown,
200	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
201	/[143(0x8f)] = / kCpumMicroarch_Intel_Unknown,
202	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
203	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
204	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
205	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
206	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
207	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
208	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
209	/[151(0x97)] = / kCpumMicroarch_Intel_Unknown,
210	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
211	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
212	/[154(0x9a)] = / kCpumMicroarch_Intel_Unknown,
213	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
214	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
215	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
216	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
217	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
218	};
219	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0x9f+1);
220
221
222	/**
223	* Figures out the (sub-)micro architecture given a bit of CPUID info.
224	*
225	* @returns Micro architecture.
226	* @param enmVendor The CPU vendor .
227	* @param bFamily The CPU family.
228	* @param bModel The CPU model.
229	* @param bStepping The CPU stepping.
230	*/
231	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
232	uint8_t bModel, uint8_t bStepping)
233	{
234	if (enmVendor == CPUMCPUVENDOR_AMD)
235	{
236	switch (bFamily)
237	{
238	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
239	case 0x03: return kCpumMicroarch_AMD_Am386;
240	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
241	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
242	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
243	case 0x06:
244	switch (bModel)
245	{
246	case 0: return kCpumMicroarch_AMD_K7_Palomino;
247	case 1: return kCpumMicroarch_AMD_K7_Palomino;
248	case 2: return kCpumMicroarch_AMD_K7_Palomino;
249	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
250	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
251	case 6: return kCpumMicroarch_AMD_K7_Palomino;
252	case 7: return kCpumMicroarch_AMD_K7_Morgan;
253	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
254	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
255	}
256	return kCpumMicroarch_AMD_K7_Unknown;
257	case 0x0f:
258	/*
259	* This family is a friggin mess. Trying my best to make some
260	* sense out of it. Too much happened in the 0x0f family to
261	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
262	*
263	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
264	* cpu-world.com, and other places:
265	* - 130nm:
266	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
267	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
268	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
269	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
270	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
271	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
272	* - 90nm:
273	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
274	* - Oakville: 10FC0/DH-D0.
275	* - Georgetown: 10FC0/DH-D0.
276	* - Sonora: 10FC0/DH-D0.
277	* - Venus: 20F71/SH-E4
278	* - Troy: 20F51/SH-E4
279	* - Athens: 20F51/SH-E4
280	* - San Diego: 20F71/SH-E4.
281	* - Lancaster: 20F42/SH-E5
282	* - Newark: 20F42/SH-E5.
283	* - Albany: 20FC2/DH-E6.
284	* - Roma: 20FC2/DH-E6.
285	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
286	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
287	* - 90nm introducing Dual core:
288	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
289	* - Italy: 20F10/JH-E1, 20F12/JH-E6
290	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
291	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
292	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
293	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
294	* - Santa Ana: 40F32/JH-F2, /-F3
295	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
296	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
297	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
298	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
299	* - Keene: 40FC2/DH-F2.
300	* - Richmond: 40FC2/DH-F2
301	* - Taylor: 40F82/BH-F2
302	* - Trinidad: 40F82/BH-F2
303	*
304	* - 65nm:
305	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
306	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
307	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
308	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
309	* - Sherman: /-G1, 70FC2/DH-G2.
310	* - Huron: 70FF2/DH-G2.
311	*/
312	if (bModel < 0x10)
313	return kCpumMicroarch_AMD_K8_130nm;
314	if (bModel >= 0x60 && bModel < 0x80)
315	return kCpumMicroarch_AMD_K8_65nm;
316	if (bModel >= 0x40)
317	return kCpumMicroarch_AMD_K8_90nm_AMDV;
318	switch (bModel)
319	{
320	case 0x21:
321	case 0x23:
322	case 0x2b:
323	case 0x2f:
324	case 0x37:
325	case 0x3f:
326	return kCpumMicroarch_AMD_K8_90nm_DualCore;
327	}
328	return kCpumMicroarch_AMD_K8_90nm;
329	case 0x10:
330	return kCpumMicroarch_AMD_K10;
331	case 0x11:
332	return kCpumMicroarch_AMD_K10_Lion;
333	case 0x12:
334	return kCpumMicroarch_AMD_K10_Llano;
335	case 0x14:
336	return kCpumMicroarch_AMD_Bobcat;
337	case 0x15:
338	switch (bModel)
339	{
340	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
341	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
342	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
343	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
344	case 0x11: /* ?? */
345	case 0x12: /* ?? */
346	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
347	}
348	return kCpumMicroarch_AMD_15h_Unknown;
349	case 0x16:
350	return kCpumMicroarch_AMD_Jaguar;
351	case 0x17:
352	return kCpumMicroarch_AMD_Zen_Ryzen;
353	}
354	return kCpumMicroarch_AMD_Unknown;
355	}
356
357	if (enmVendor == CPUMCPUVENDOR_INTEL)
358	{
359	switch (bFamily)
360	{
361	case 3:
362	return kCpumMicroarch_Intel_80386;
363	case 4:
364	return kCpumMicroarch_Intel_80486;
365	case 5:
366	return kCpumMicroarch_Intel_P5;
367	case 6:
368	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
369	{
370	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
371	if ( enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake
372	&& bStepping >= 0xa)
373	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
374	return enmMicroArch;
375	}
376	return kCpumMicroarch_Intel_Atom_Unknown;
377	case 15:
378	switch (bModel)
379	{
380	case 0: return kCpumMicroarch_Intel_NB_Willamette;
381	case 1: return kCpumMicroarch_Intel_NB_Willamette;
382	case 2: return kCpumMicroarch_Intel_NB_Northwood;
383	case 3: return kCpumMicroarch_Intel_NB_Prescott;
384	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
385	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
386	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
387	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
388	default: return kCpumMicroarch_Intel_NB_Unknown;
389	}
390	break;
391	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
392	case 0:
393	return kCpumMicroarch_Intel_8086;
394	case 1:
395	return kCpumMicroarch_Intel_80186;
396	case 2:
397	return kCpumMicroarch_Intel_80286;
398	}
399	return kCpumMicroarch_Intel_Unknown;
400	}
401
402	if (enmVendor == CPUMCPUVENDOR_VIA)
403	{
404	switch (bFamily)
405	{
406	case 5:
407	switch (bModel)
408	{
409	case 1: return kCpumMicroarch_Centaur_C6;
410	case 4: return kCpumMicroarch_Centaur_C6;
411	case 8: return kCpumMicroarch_Centaur_C2;
412	case 9: return kCpumMicroarch_Centaur_C3;
413	}
414	break;
415
416	case 6:
417	switch (bModel)
418	{
419	case 5: return kCpumMicroarch_VIA_C3_M2;
420	case 6: return kCpumMicroarch_VIA_C3_C5A;
421	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
422	case 8: return kCpumMicroarch_VIA_C3_C5N;
423	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
424	case 10: return kCpumMicroarch_VIA_C7_C5J;
425	case 15: return kCpumMicroarch_VIA_Isaiah;
426	}
427	break;
428	}
429	return kCpumMicroarch_VIA_Unknown;
430	}
431
432	if (enmVendor == CPUMCPUVENDOR_CYRIX)
433	{
434	switch (bFamily)
435	{
436	case 4:
437	switch (bModel)
438	{
439	case 9: return kCpumMicroarch_Cyrix_5x86;
440	}
441	break;
442
443	case 5:
444	switch (bModel)
445	{
446	case 2: return kCpumMicroarch_Cyrix_M1;
447	case 4: return kCpumMicroarch_Cyrix_MediaGX;
448	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
449	}
450	break;
451
452	case 6:
453	switch (bModel)
454	{
455	case 0: return kCpumMicroarch_Cyrix_M2;
456	}
457	break;
458
459	}
460	return kCpumMicroarch_Cyrix_Unknown;
461	}
462
463	return kCpumMicroarch_Unknown;
464	}
465
466
467	/**
468	* Translates a microarchitecture enum value to the corresponding string
469	* constant.
470	*
471	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
472	* NULL if the value is invalid.
473	*
474	* @param enmMicroarch The enum value to convert.
475	*/
476	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
477	{
478	switch (enmMicroarch)
479	{
480	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
481	CASE_RET_STR(kCpumMicroarch_Intel_8086);
482	CASE_RET_STR(kCpumMicroarch_Intel_80186);
483	CASE_RET_STR(kCpumMicroarch_Intel_80286);
484	CASE_RET_STR(kCpumMicroarch_Intel_80386);
485	CASE_RET_STR(kCpumMicroarch_Intel_80486);
486	CASE_RET_STR(kCpumMicroarch_Intel_P5);
487
488	CASE_RET_STR(kCpumMicroarch_Intel_P6);
489	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
490	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
491
492	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
493	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
494	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
495
496	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
497	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
498
499	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
500	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
501	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
502	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
503	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
504	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
505	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
506	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
507	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
508	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
509	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
510	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
511
512	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
513	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
514	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
515	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
516	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
517	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
518	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
519	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
520
521	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
522	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
523	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
524	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
525	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
526
527	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
528	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
529	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
530	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
531	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
532	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
533	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
534
535	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
536
537	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
538	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
539	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
540	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
541	CASE_RET_STR(kCpumMicroarch_AMD_K5);
542	CASE_RET_STR(kCpumMicroarch_AMD_K6);
543
544	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
545	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
546	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
547	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
548	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
549	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
550	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
551
552	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
553	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
554	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
555	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
556	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
557
558	CASE_RET_STR(kCpumMicroarch_AMD_K10);
559	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
560	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
561	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
562	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
563
564	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
565	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
566	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
567	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
568	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
569
570	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
571
572	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
573
574	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
575
576	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
577	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
578	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
579	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
580	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
581	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
582	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
583	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
584	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
585	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
586	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
587	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
588	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
589
590	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
591	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
592	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
593	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
594	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
595	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
596
597	CASE_RET_STR(kCpumMicroarch_NEC_V20);
598	CASE_RET_STR(kCpumMicroarch_NEC_V30);
599
600	CASE_RET_STR(kCpumMicroarch_Unknown);
601
602	#undef CASE_RET_STR
603	case kCpumMicroarch_Invalid:
604	case kCpumMicroarch_Intel_End:
605	case kCpumMicroarch_Intel_Core2_End:
606	case kCpumMicroarch_Intel_Core7_End:
607	case kCpumMicroarch_Intel_Atom_End:
608	case kCpumMicroarch_Intel_P6_Core_Atom_End:
609	case kCpumMicroarch_Intel_Phi_End:
610	case kCpumMicroarch_Intel_NB_End:
611	case kCpumMicroarch_AMD_K7_End:
612	case kCpumMicroarch_AMD_K8_End:
613	case kCpumMicroarch_AMD_15h_End:
614	case kCpumMicroarch_AMD_16h_End:
615	case kCpumMicroarch_AMD_Zen_End:
616	case kCpumMicroarch_AMD_End:
617	case kCpumMicroarch_VIA_End:
618	case kCpumMicroarch_Cyrix_End:
619	case kCpumMicroarch_NEC_End:
620	case kCpumMicroarch_32BitHack:
621	break;
622	/* no default! */
623	}
624
625	return NULL;
626	}
627
628
629	/**
630	* Determins the host CPU MXCSR mask.
631	*
632	* @returns MXCSR mask.
633	*/
634	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
635	{
636	if ( ASMHasCpuId()
637	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
638	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
639	{
640	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
641	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
642	RT_ZERO(*pState);
643	ASMFxSave(pState);
644	if (pState->MXCSR_MASK == 0)
645	return 0xffbf;
646	return pState->MXCSR_MASK;
647	}
648	return 0;
649	}
650
651
652	/**
653	* Gets a matching leaf in the CPUID leaf array.
654	*
655	* @returns Pointer to the matching leaf, or NULL if not found.
656	* @param paLeaves The CPUID leaves to search. This is sorted.
657	* @param cLeaves The number of leaves in the array.
658	* @param uLeaf The leaf to locate.
659	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
660	*/
661	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
662	{
663	/* Lazy bird does linear lookup here since this is only used for the
664	occational CPUID overrides. */
665	for (uint32_t i = 0; i < cLeaves; i++)
666	if ( paLeaves[i].uLeaf == uLeaf
667	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
668	return &paLeaves[i];
669	return NULL;
670	}
671
672
673	#ifndef IN_VBOX_CPU_REPORT
674	/**
675	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
676	*
677	* @returns true if found, false it not.
678	* @param paLeaves The CPUID leaves to search. This is sorted.
679	* @param cLeaves The number of leaves in the array.
680	* @param uLeaf The leaf to locate.
681	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
682	* @param pLegacy The legacy output leaf.
683	*/
684	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
685	PCPUMCPUID pLegacy)
686	{
687	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
688	if (pLeaf)
689	{
690	pLegacy->uEax = pLeaf->uEax;
691	pLegacy->uEbx = pLeaf->uEbx;
692	pLegacy->uEcx = pLeaf->uEcx;
693	pLegacy->uEdx = pLeaf->uEdx;
694	return true;
695	}
696	return false;
697	}
698	#endif /* IN_VBOX_CPU_REPORT */
699
700
701	/**
702	* Ensures that the CPUID leaf array can hold one more leaf.
703	*
704	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
705	* failure.
706	* @param pVM The cross context VM structure. If NULL, use
707	* the process heap, otherwise the VM's hyper heap.
708	* @param ppaLeaves Pointer to the variable holding the array pointer
709	* (input/output).
710	* @param cLeaves The current array size.
711	*
712	* @remarks This function will automatically update the R0 and RC pointers when
713	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
714	* be the corresponding VM's CPUID arrays (which is asserted).
715	*/
716	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
717	{
718	/*
719	* If pVM is not specified, we're on the regular heap and can waste a
720	* little space to speed things up.
721	*/
722	uint32_t cAllocated;
723	if (!pVM)
724	{
725	cAllocated = RT_ALIGN(cLeaves, 16);
726	if (cLeaves + 1 > cAllocated)
727	{
728	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
729	if (pvNew)
730	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
731	else
732	{
733	RTMemFree(*ppaLeaves);
734	*ppaLeaves = NULL;
735	}
736	}
737	}
738	/*
739	* Otherwise, we're on the hyper heap and are probably just inserting
740	* one or two leaves and should conserve space.
741	*/
742	else
743	{
744	#ifdef IN_VBOX_CPU_REPORT
745	AssertReleaseFailed();
746	#else
747	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
748	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
749
750	size_t cb = cLeaves * sizeof(**ppaLeaves);
751	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
752	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
753	if (RT_SUCCESS(rc))
754	{
755	/* Update the R0 and RC pointers. */
756	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
757	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
758	}
759	else
760	{
761	*ppaLeaves = NULL;
762	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
763	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
764	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
765	}
766	#endif
767	}
768	return *ppaLeaves;
769	}
770
771
772	/**
773	* Append a CPUID leaf or sub-leaf.
774	*
775	* ASSUMES linear insertion order, so we'll won't need to do any searching or
776	* replace anything. Use cpumR3CpuIdInsert() for those cases.
777	*
778	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
779	* the caller need do no more work.
780	* @param ppaLeaves Pointer to the pointer to the array of sorted
781	* CPUID leaves and sub-leaves.
782	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
783	* @param uLeaf The leaf we're adding.
784	* @param uSubLeaf The sub-leaf number.
785	* @param fSubLeafMask The sub-leaf mask.
786	* @param uEax The EAX value.
787	* @param uEbx The EBX value.
788	* @param uEcx The ECX value.
789	* @param uEdx The EDX value.
790	* @param fFlags The flags.
791	*/
792	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
793	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
794	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
795	{
796	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
797	return VERR_NO_MEMORY;
798
799	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
800	Assert( *pcLeaves == 0
801	\|\| pNew[-1].uLeaf < uLeaf
802	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
803
804	pNew->uLeaf = uLeaf;
805	pNew->uSubLeaf = uSubLeaf;
806	pNew->fSubLeafMask = fSubLeafMask;
807	pNew->uEax = uEax;
808	pNew->uEbx = uEbx;
809	pNew->uEcx = uEcx;
810	pNew->uEdx = uEdx;
811	pNew->fFlags = fFlags;
812
813	*pcLeaves += 1;
814	return VINF_SUCCESS;
815	}
816
817
818	/**
819	* Checks that we've updated the CPUID leaves array correctly.
820	*
821	* This is a no-op in non-strict builds.
822	*
823	* @param paLeaves The leaves array.
824	* @param cLeaves The number of leaves.
825	*/
826	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
827	{
828	#ifdef VBOX_STRICT
829	for (uint32_t i = 1; i < cLeaves; i++)
830	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
831	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
832	else
833	{
834	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
835	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
836	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
837	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
838	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
839	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
840	}
841	#else
842	NOREF(paLeaves);
843	NOREF(cLeaves);
844	#endif
845	}
846
847
848	/**
849	* Inserts a CPU ID leaf, replacing any existing ones.
850	*
851	* When inserting a simple leaf where we already got a series of sub-leaves with
852	* the same leaf number (eax), the simple leaf will replace the whole series.
853	*
854	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
855	* host-context heap and has only been allocated/reallocated by the
856	* cpumR3CpuIdEnsureSpace function.
857	*
858	* @returns VBox status code.
859	* @param pVM The cross context VM structure. If NULL, use
860	* the process heap, otherwise the VM's hyper heap.
861	* @param ppaLeaves Pointer to the pointer to the array of sorted
862	* CPUID leaves and sub-leaves. Must be NULL if using
863	* the hyper heap.
864	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
865	* be NULL if using the hyper heap.
866	* @param pNewLeaf Pointer to the data of the new leaf we're about to
867	* insert.
868	*/
869	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
870	{
871	/*
872	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
873	*/
874	if (pVM)
875	{
876	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
877	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
878
879	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
880	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
881	}
882
883	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
884	uint32_t cLeaves = *pcLeaves;
885
886	/*
887	* Validate the new leaf a little.
888	*/
889	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
890	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
891	VERR_INVALID_FLAGS);
892	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
893	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
894	VERR_INVALID_PARAMETER);
895	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
896	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
897	VERR_INVALID_PARAMETER);
898	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
899	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
900	VERR_INVALID_PARAMETER);
901
902	/*
903	* Find insertion point. The lazy bird uses the same excuse as in
904	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
905	*/
906	uint32_t i;
907	if ( cLeaves > 0
908	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
909	{
910	/* Add at end. */
911	i = cLeaves;
912	}
913	else if ( cLeaves > 0
914	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
915	{
916	/* Either replacing the last leaf or dealing with sub-leaves. Spool
917	back to the first sub-leaf to pretend we did the linear search. */
918	i = cLeaves - 1;
919	while ( i > 0
920	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
921	i--;
922	}
923	else
924	{
925	/* Linear search from the start. */
926	i = 0;
927	while ( i < cLeaves
928	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
929	i++;
930	}
931	if ( i < cLeaves
932	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
933	{
934	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
935	{
936	/*
937	* The sub-leaf mask differs, replace all existing leaves with the
938	* same leaf number.
939	*/
940	uint32_t c = 1;
941	while ( i + c < cLeaves
942	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
943	c++;
944	if (c > 1 && i + c < cLeaves)
945	{
946	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
947	*pcLeaves = cLeaves -= c - 1;
948	}
949
950	paLeaves[i] = *pNewLeaf;
951	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
952	return VINF_SUCCESS;
953	}
954
955	/* Find sub-leaf insertion point. */
956	while ( i < cLeaves
957	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
958	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
959	i++;
960
961	/*
962	* If we've got an exactly matching leaf, replace it.
963	*/
964	if ( i < cLeaves
965	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
966	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
967	{
968	paLeaves[i] = *pNewLeaf;
969	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
970	return VINF_SUCCESS;
971	}
972	}
973
974	/*
975	* Adding a new leaf at 'i'.
976	*/
977	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
978	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
979	if (!paLeaves)
980	return VERR_NO_MEMORY;
981
982	if (i < cLeaves)
983	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
984	*pcLeaves += 1;
985	paLeaves[i] = *pNewLeaf;
986
987	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
988	return VINF_SUCCESS;
989	}
990
991
992	#ifndef IN_VBOX_CPU_REPORT
993	/**
994	* Removes a range of CPUID leaves.
995	*
996	* This will not reallocate the array.
997	*
998	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
999	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1000	* @param uFirst The first leaf.
1001	* @param uLast The last leaf.
1002	*/
1003	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1004	{
1005	uint32_t cLeaves = *pcLeaves;
1006
1007	Assert(uFirst <= uLast);
1008
1009	/*
1010	* Find the first one.
1011	*/
1012	uint32_t iFirst = 0;
1013	while ( iFirst < cLeaves
1014	&& paLeaves[iFirst].uLeaf < uFirst)
1015	iFirst++;
1016
1017	/*
1018	* Find the end (last + 1).
1019	*/
1020	uint32_t iEnd = iFirst;
1021	while ( iEnd < cLeaves
1022	&& paLeaves[iEnd].uLeaf <= uLast)
1023	iEnd++;
1024
1025	/*
1026	* Adjust the array if anything needs removing.
1027	*/
1028	if (iFirst < iEnd)
1029	{
1030	if (iEnd < cLeaves)
1031	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1032	*pcLeaves = cLeaves -= (iEnd - iFirst);
1033	}
1034
1035	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1036	}
1037	#endif /* IN_VBOX_CPU_REPORT */
1038
1039
1040	/**
1041	* Checks if ECX make a difference when reading a given CPUID leaf.
1042	*
1043	* @returns @c true if it does, @c false if it doesn't.
1044	* @param uLeaf The leaf we're reading.
1045	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1046	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1047	* final sub-leaf (for leaf 0xb only).
1048	*/
1049	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1050	{
1051	*pfFinalEcxUnchanged = false;
1052
1053	uint32_t auCur[4];
1054	uint32_t auPrev[4];
1055	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1056
1057	/* Look for sub-leaves. */
1058	uint32_t uSubLeaf = 1;
1059	for (;;)
1060	{
1061	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1062	if (memcmp(auCur, auPrev, sizeof(auCur)))
1063	break;
1064
1065	/* Advance / give up. */
1066	uSubLeaf++;
1067	if (uSubLeaf >= 64)
1068	{
1069	*pcSubLeaves = 1;
1070	return false;
1071	}
1072	}
1073
1074	/* Count sub-leaves. */
1075	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1076	uint32_t cRepeats = 0;
1077	uSubLeaf = 0;
1078	for (;;)
1079	{
1080	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1081
1082	/* Figuring out when to stop isn't entirely straight forward as we need
1083	to cover undocumented behavior up to a point and implementation shortcuts. */
1084
1085	/* 1. Look for more than 4 repeating value sets. */
1086	if ( auCur[0] == auPrev[0]
1087	&& auCur[1] == auPrev[1]
1088	&& ( auCur[2] == auPrev[2]
1089	\|\| ( auCur[2] == uSubLeaf
1090	&& auPrev[2] == uSubLeaf - 1) )
1091	&& auCur[3] == auPrev[3])
1092	{
1093	if ( uLeaf != 0xd
1094	\|\| uSubLeaf >= 64
1095	\|\| ( auCur[0] == 0
1096	&& auCur[1] == 0
1097	&& auCur[2] == 0
1098	&& auCur[3] == 0
1099	&& auPrev[2] == 0) )
1100	cRepeats++;
1101	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1102	break;
1103	}
1104	else
1105	cRepeats = 0;
1106
1107	/* 2. Look for zero values. */
1108	if ( auCur[0] == 0
1109	&& auCur[1] == 0
1110	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1111	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1112	&& uSubLeaf >= cMinLeaves)
1113	{
1114	cRepeats = 0;
1115	break;
1116	}
1117
1118	/* 3. Leaf 0xb level type 0 check. */
1119	if ( uLeaf == 0xb
1120	&& (auCur[2] & 0xff00) == 0
1121	&& (auPrev[2] & 0xff00) == 0)
1122	{
1123	cRepeats = 0;
1124	break;
1125	}
1126
1127	/* 99. Give up. */
1128	if (uSubLeaf >= 128)
1129	{
1130	#ifndef IN_VBOX_CPU_REPORT
1131	/* Ok, limit it according to the documentation if possible just to
1132	avoid annoying users with these detection issues. */
1133	uint32_t cDocLimit = UINT32_MAX;
1134	if (uLeaf == 0x4)
1135	cDocLimit = 4;
1136	else if (uLeaf == 0x7)
1137	cDocLimit = 1;
1138	else if (uLeaf == 0xd)
1139	cDocLimit = 63;
1140	else if (uLeaf == 0xf)
1141	cDocLimit = 2;
1142	if (cDocLimit != UINT32_MAX)
1143	{
1144	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1145	*pcSubLeaves = cDocLimit + 3;
1146	return true;
1147	}
1148	#endif
1149	*pcSubLeaves = UINT32_MAX;
1150	return true;
1151	}
1152
1153	/* Advance. */
1154	uSubLeaf++;
1155	memcpy(auPrev, auCur, sizeof(auCur));
1156	}
1157
1158	/* Standard exit. */
1159	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1160	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1161	if (*pcSubLeaves == 0)
1162	*pcSubLeaves = 1;
1163	return true;
1164	}
1165
1166
1167	/**
1168	* Gets a CPU ID leaf.
1169	*
1170	* @returns VBox status code.
1171	* @param pVM The cross context VM structure.
1172	* @param pLeaf Where to store the found leaf.
1173	* @param uLeaf The leaf to locate.
1174	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1175	*/
1176	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1177	{
1178	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1179	uLeaf, uSubLeaf);
1180	if (pcLeaf)
1181	{
1182	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1183	return VINF_SUCCESS;
1184	}
1185
1186	return VERR_NOT_FOUND;
1187	}
1188
1189
1190	/**
1191	* Inserts a CPU ID leaf, replacing any existing ones.
1192	*
1193	* @returns VBox status code.
1194	* @param pVM The cross context VM structure.
1195	* @param pNewLeaf Pointer to the leaf being inserted.
1196	*/
1197	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1198	{
1199	/*
1200	* Validate parameters.
1201	*/
1202	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1203	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1204
1205	/*
1206	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1207	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1208	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1209	*/
1210	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1211	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1212	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1213	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1214	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1215	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1216	{
1217	return VERR_NOT_SUPPORTED;
1218	}
1219
1220	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1221	}
1222
1223	/**
1224	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1225	*
1226	* @returns VBox status code.
1227	* @param ppaLeaves Where to return the array pointer on success.
1228	* Use RTMemFree to release.
1229	* @param pcLeaves Where to return the size of the array on
1230	* success.
1231	*/
1232	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1233	{
1234	*ppaLeaves = NULL;
1235	*pcLeaves = 0;
1236
1237	/*
1238	* Try out various candidates. This must be sorted!
1239	*/
1240	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1241	{
1242	{ UINT32_C(0x00000000), false },
1243	{ UINT32_C(0x10000000), false },
1244	{ UINT32_C(0x20000000), false },
1245	{ UINT32_C(0x30000000), false },
1246	{ UINT32_C(0x40000000), false },
1247	{ UINT32_C(0x50000000), false },
1248	{ UINT32_C(0x60000000), false },
1249	{ UINT32_C(0x70000000), false },
1250	{ UINT32_C(0x80000000), false },
1251	{ UINT32_C(0x80860000), false },
1252	{ UINT32_C(0x8ffffffe), true },
1253	{ UINT32_C(0x8fffffff), true },
1254	{ UINT32_C(0x90000000), false },
1255	{ UINT32_C(0xa0000000), false },
1256	{ UINT32_C(0xb0000000), false },
1257	{ UINT32_C(0xc0000000), false },
1258	{ UINT32_C(0xd0000000), false },
1259	{ UINT32_C(0xe0000000), false },
1260	{ UINT32_C(0xf0000000), false },
1261	};
1262
1263	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1264	{
1265	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1266	uint32_t uEax, uEbx, uEcx, uEdx;
1267	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1268
1269	/*
1270	* Does EAX look like a typical leaf count value?
1271	*/
1272	if ( uEax > uLeaf
1273	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1274	{
1275	/* Yes, dump them. */
1276	uint32_t cLeaves = uEax - uLeaf + 1;
1277	while (cLeaves-- > 0)
1278	{
1279	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1280
1281	uint32_t fFlags = 0;
1282
1283	/* There are currently three known leaves containing an APIC ID
1284	that needs EMT specific attention */
1285	if (uLeaf == 1)
1286	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1287	else if (uLeaf == 0xb && uEcx != 0)
1288	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1289	else if ( uLeaf == UINT32_C(0x8000001e)
1290	&& ( uEax
1291	\|\| uEbx
1292	\|\| uEdx
1293	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1294	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1295
1296	/* The APIC bit is per-VCpu and needs flagging. */
1297	if (uLeaf == 1)
1298	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1299	else if ( uLeaf == UINT32_C(0x80000001)
1300	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1301	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1302	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1303
1304	/* Check three times here to reduce the chance of CPU migration
1305	resulting in false positives with things like the APIC ID. */
1306	uint32_t cSubLeaves;
1307	bool fFinalEcxUnchanged;
1308	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1309	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1310	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1311	{
1312	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1313	{
1314	/* This shouldn't happen. But in case it does, file all
1315	relevant details in the release log. */
1316	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1317	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1318	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1319	{
1320	uint32_t auTmp[4];
1321	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1322	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1323	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1324	}
1325	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1326	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1327	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1328	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1329	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1330	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1331	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1332	}
1333
1334	if (fFinalEcxUnchanged)
1335	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1336
1337	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1338	{
1339	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1340	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1341	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1342	if (RT_FAILURE(rc))
1343	return rc;
1344	}
1345	}
1346	else
1347	{
1348	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1349	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1350	if (RT_FAILURE(rc))
1351	return rc;
1352	}
1353
1354	/* next */
1355	uLeaf++;
1356	}
1357	}
1358	/*
1359	* Special CPUIDs needs special handling as they don't follow the
1360	* leaf count principle used above.
1361	*/
1362	else if (s_aCandidates[iOuter].fSpecial)
1363	{
1364	bool fKeep = false;
1365	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1366	fKeep = true;
1367	else if ( uLeaf == 0x8fffffff
1368	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1369	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1370	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1371	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1372	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1373	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1374	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1375	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1376	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1377	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1378	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1379	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1380	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1381	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1382	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1383	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1384	fKeep = true;
1385	if (fKeep)
1386	{
1387	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1388	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1389	if (RT_FAILURE(rc))
1390	return rc;
1391	}
1392	}
1393	}
1394
1395	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1396	return VINF_SUCCESS;
1397	}
1398
1399
1400	/**
1401	* Determines the method the CPU uses to handle unknown CPUID leaves.
1402	*
1403	* @returns VBox status code.
1404	* @param penmUnknownMethod Where to return the method.
1405	* @param pDefUnknown Where to return default unknown values. This
1406	* will be set, even if the resulting method
1407	* doesn't actually needs it.
1408	*/
1409	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1410	{
1411	uint32_t uLastStd = ASMCpuId_EAX(0);
1412	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1413	if (!ASMIsValidExtRange(uLastExt))
1414	uLastExt = 0x80000000;
1415
1416	uint32_t auChecks[] =
1417	{
1418	uLastStd + 1,
1419	uLastStd + 5,
1420	uLastStd + 8,
1421	uLastStd + 32,
1422	uLastStd + 251,
1423	uLastExt + 1,
1424	uLastExt + 8,
1425	uLastExt + 15,
1426	uLastExt + 63,
1427	uLastExt + 255,
1428	0x7fbbffcc,
1429	0x833f7872,
1430	0xefff2353,
1431	0x35779456,
1432	0x1ef6d33e,
1433	};
1434
1435	static const uint32_t s_auValues[] =
1436	{
1437	0xa95d2156,
1438	0x00000001,
1439	0x00000002,
1440	0x00000008,
1441	0x00000000,
1442	0x55773399,
1443	0x93401769,
1444	0x12039587,
1445	};
1446
1447	/*
1448	* Simple method, all zeros.
1449	*/
1450	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1451	pDefUnknown->uEax = 0;
1452	pDefUnknown->uEbx = 0;
1453	pDefUnknown->uEcx = 0;
1454	pDefUnknown->uEdx = 0;
1455
1456	/*
1457	* Intel has been observed returning the last standard leaf.
1458	*/
1459	uint32_t auLast[4];
1460	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1461
1462	uint32_t cChecks = RT_ELEMENTS(auChecks);
1463	while (cChecks > 0)
1464	{
1465	uint32_t auCur[4];
1466	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1467	if (memcmp(auCur, auLast, sizeof(auCur)))
1468	break;
1469	cChecks--;
1470	}
1471	if (cChecks == 0)
1472	{
1473	/* Now, what happens when the input changes? Esp. ECX. */
1474	uint32_t cTotal = 0;
1475	uint32_t cSame = 0;
1476	uint32_t cLastWithEcx = 0;
1477	uint32_t cNeither = 0;
1478	uint32_t cValues = RT_ELEMENTS(s_auValues);
1479	while (cValues > 0)
1480	{
1481	uint32_t uValue = s_auValues[cValues - 1];
1482	uint32_t auLastWithEcx[4];
1483	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1484	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1485
1486	cChecks = RT_ELEMENTS(auChecks);
1487	while (cChecks > 0)
1488	{
1489	uint32_t auCur[4];
1490	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1491	if (!memcmp(auCur, auLast, sizeof(auCur)))
1492	{
1493	cSame++;
1494	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1495	cLastWithEcx++;
1496	}
1497	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1498	cLastWithEcx++;
1499	else
1500	cNeither++;
1501	cTotal++;
1502	cChecks--;
1503	}
1504	cValues--;
1505	}
1506
1507	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1508	if (cSame == cTotal)
1509	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1510	else if (cLastWithEcx == cTotal)
1511	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1512	else
1513	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1514	pDefUnknown->uEax = auLast[0];
1515	pDefUnknown->uEbx = auLast[1];
1516	pDefUnknown->uEcx = auLast[2];
1517	pDefUnknown->uEdx = auLast[3];
1518	return VINF_SUCCESS;
1519	}
1520
1521	/*
1522	* Unchanged register values?
1523	*/
1524	cChecks = RT_ELEMENTS(auChecks);
1525	while (cChecks > 0)
1526	{
1527	uint32_t const uLeaf = auChecks[cChecks - 1];
1528	uint32_t cValues = RT_ELEMENTS(s_auValues);
1529	while (cValues > 0)
1530	{
1531	uint32_t uValue = s_auValues[cValues - 1];
1532	uint32_t auCur[4];
1533	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1534	if ( auCur[0] != uLeaf
1535	\|\| auCur[1] != uValue
1536	\|\| auCur[2] != uValue
1537	\|\| auCur[3] != uValue)
1538	break;
1539	cValues--;
1540	}
1541	if (cValues != 0)
1542	break;
1543	cChecks--;
1544	}
1545	if (cChecks == 0)
1546	{
1547	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1548	return VINF_SUCCESS;
1549	}
1550
1551	/*
1552	* Just go with the simple method.
1553	*/
1554	return VINF_SUCCESS;
1555	}
1556
1557
1558	/**
1559	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1560	*
1561	* @returns Read only name string.
1562	* @param enmUnknownMethod The method to translate.
1563	*/
1564	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1565	{
1566	switch (enmUnknownMethod)
1567	{
1568	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1569	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1570	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1571	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1572
1573	case CPUMUNKNOWNCPUID_INVALID:
1574	case CPUMUNKNOWNCPUID_END:
1575	case CPUMUNKNOWNCPUID_32BIT_HACK:
1576	break;
1577	}
1578	return "Invalid-unknown-CPUID-method";
1579	}
1580
1581
1582	/**
1583	* Detect the CPU vendor give n the
1584	*
1585	* @returns The vendor.
1586	* @param uEAX EAX from CPUID(0).
1587	* @param uEBX EBX from CPUID(0).
1588	* @param uECX ECX from CPUID(0).
1589	* @param uEDX EDX from CPUID(0).
1590	*/
1591	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1592	{
1593	if (ASMIsValidStdRange(uEAX))
1594	{
1595	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1596	return CPUMCPUVENDOR_AMD;
1597
1598	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1599	return CPUMCPUVENDOR_INTEL;
1600
1601	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1602	return CPUMCPUVENDOR_VIA;
1603
1604	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1605	&& uECX == UINT32_C(0x64616574)
1606	&& uEDX == UINT32_C(0x736E4978))
1607	return CPUMCPUVENDOR_CYRIX;
1608
1609	/* "Geode by NSC", example: family 5, model 9. */
1610
1611	/** @todo detect the other buggers... */
1612	}
1613
1614	return CPUMCPUVENDOR_UNKNOWN;
1615	}
1616
1617
1618	/**
1619	* Translates a CPU vendor enum value into the corresponding string constant.
1620	*
1621	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1622	* value name. This can be useful when generating code.
1623	*
1624	* @returns Read only name string.
1625	* @param enmVendor The CPU vendor value.
1626	*/
1627	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1628	{
1629	switch (enmVendor)
1630	{
1631	case CPUMCPUVENDOR_INTEL: return "INTEL";
1632	case CPUMCPUVENDOR_AMD: return "AMD";
1633	case CPUMCPUVENDOR_VIA: return "VIA";
1634	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1635	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1636
1637	case CPUMCPUVENDOR_INVALID:
1638	case CPUMCPUVENDOR_32BIT_HACK:
1639	break;
1640	}
1641	return "Invalid-cpu-vendor";
1642	}
1643
1644
1645	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1646	{
1647	/* Could do binary search, doing linear now because I'm lazy. */
1648	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1649	while (cLeaves-- > 0)
1650	{
1651	if (pLeaf->uLeaf == uLeaf)
1652	return pLeaf;
1653	pLeaf++;
1654	}
1655	return NULL;
1656	}
1657
1658
1659	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1660	{
1661	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1662	if ( !pLeaf
1663	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1664	return pLeaf;
1665
1666	/* Linear sub-leaf search. Lazy as usual. */
1667	cLeaves -= pLeaf - paLeaves;
1668	while ( cLeaves-- > 0
1669	&& pLeaf->uLeaf == uLeaf)
1670	{
1671	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1672	return pLeaf;
1673	pLeaf++;
1674	}
1675
1676	return NULL;
1677	}
1678
1679
1680	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1681	{
1682	RT_ZERO(*pFeatures);
1683	if (cLeaves >= 2)
1684	{
1685	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1686	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1687	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1688	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1689	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1690	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1691
1692	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1693	pStd0Leaf->uEbx,
1694	pStd0Leaf->uEcx,
1695	pStd0Leaf->uEdx);
1696	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1697	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1698	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1699	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1700	pFeatures->uFamily,
1701	pFeatures->uModel,
1702	pFeatures->uStepping);
1703
1704	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1705	if (pExtLeaf8)
1706	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1707	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1708	pFeatures->cMaxPhysAddrWidth = 36;
1709	else
1710	pFeatures->cMaxPhysAddrWidth = 32;
1711
1712	/* Standard features. */
1713	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1714	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1715	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1716	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1717	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1718	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1719	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1720	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1721	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1722	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1723	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1724	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1725	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1726	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1727	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1728	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1729	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1730	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1731	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1732	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1733	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1734	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1735	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1736	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1737	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1738
1739	/* Structured extended features. */
1740	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1741	if (pSxfLeaf0)
1742	{
1743	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1744	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1745	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1746	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1747	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1748
1749	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1750	pFeatures->fIbrs = pFeatures->fIbpb;
1751	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1752	#if 0 // Disabled until IA32_ARCH_CAPABILITIES support can be tested
1753	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1754	#endif
1755	}
1756
1757	/* MWAIT/MONITOR leaf. */
1758	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1759	if (pMWaitLeaf)
1760	{
1761	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1762	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1763	}
1764
1765	/* Extended features. */
1766	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1767	if (pExtLeaf)
1768	{
1769	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1770	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1771	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1772	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1773	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1774	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1775	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1776	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1777	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1778	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1779	}
1780
1781	if ( pExtLeaf
1782	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1783	{
1784	/* AMD features. */
1785	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1786	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1787	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1788	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1789	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1790	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1791	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1792	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1793	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1794	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1795	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1796	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1797	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1798	if (pFeatures->fSvm)
1799	{
1800	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1801	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1802	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1803	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1804	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1805	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1806	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1807	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1808	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1809	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1810	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1811	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1812	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1813	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1814	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1815	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1816	}
1817	}
1818
1819	/*
1820	* Quirks.
1821	*/
1822	pFeatures->fLeakyFxSR = pExtLeaf
1823	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1824	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1825	&& pFeatures->uFamily >= 6 /* K7 and up */;
1826
1827	/*
1828	* Max extended (/FPU) state.
1829	*/
1830	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1831	if (pFeatures->fXSaveRstor)
1832	{
1833	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1834	if (pXStateLeaf0)
1835	{
1836	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1837	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1838	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1839	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1840	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1841	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1842	{
1843	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1844
1845	/* (paranoia:) */
1846	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1847	if ( pXStateLeaf1
1848	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1849	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1850	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1851	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1852	}
1853	else
1854	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1855	pFeatures->fXSaveRstor = 0);
1856	}
1857	else
1858	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1859	pFeatures->fXSaveRstor = 0);
1860	}
1861	}
1862	else
1863	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1864	return VINF_SUCCESS;
1865	}
1866
1867
1868	/*
1869	*
1870	* Init related code.
1871	* Init related code.
1872	* Init related code.
1873	*
1874	*
1875	*/
1876	#ifdef VBOX_IN_VMM
1877
1878
1879	/**
1880	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1881	*
1882	* This ignores the fSubLeafMask.
1883	*
1884	* @returns Pointer to the matching leaf, or NULL if not found.
1885	* @param paLeaves The CPUID leaves to search. This is sorted.
1886	* @param cLeaves The number of leaves in the array.
1887	* @param uLeaf The leaf to locate.
1888	* @param uSubLeaf The subleaf to locate.
1889	*/
1890	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1891	{
1892	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1893	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1894	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1895	if (iEnd)
1896	{
1897	uint32_t iBegin = 0;
1898	for (;;)
1899	{
1900	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1901	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1902	if (uNeedle < uCur)
1903	{
1904	if (i > iBegin)
1905	iEnd = i;
1906	else
1907	break;
1908	}
1909	else if (uNeedle > uCur)
1910	{
1911	if (i + 1 < iEnd)
1912	iBegin = i + 1;
1913	else
1914	break;
1915	}
1916	else
1917	return &paLeaves[i];
1918	}
1919	}
1920	return NULL;
1921	}
1922
1923
1924	/**
1925	* Loads MSR range overrides.
1926	*
1927	* This must be called before the MSR ranges are moved from the normal heap to
1928	* the hyper heap!
1929	*
1930	* @returns VBox status code (VMSetError called).
1931	* @param pVM The cross context VM structure.
1932	* @param pMsrNode The CFGM node with the MSR overrides.
1933	*/
1934	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1935	{
1936	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1937	{
1938	/*
1939	* Assemble a valid MSR range.
1940	*/
1941	CPUMMSRRANGE MsrRange;
1942	MsrRange.offCpumCpu = 0;
1943	MsrRange.fReserved = 0;
1944
1945	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1946	if (RT_FAILURE(rc))
1947	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1948
1949	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1950	if (RT_FAILURE(rc))
1951	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1952	MsrRange.szName, rc);
1953
1954	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1955	if (RT_FAILURE(rc))
1956	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1957	MsrRange.szName, rc);
1958
1959	char szType[32];
1960	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1961	if (RT_FAILURE(rc))
1962	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1963	MsrRange.szName, rc);
1964	if (!RTStrICmp(szType, "FixedValue"))
1965	{
1966	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1967	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1968
1969	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1970	if (RT_FAILURE(rc))
1971	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1972	MsrRange.szName, rc);
1973
1974	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1975	if (RT_FAILURE(rc))
1976	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1977	MsrRange.szName, rc);
1978
1979	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1980	if (RT_FAILURE(rc))
1981	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1982	MsrRange.szName, rc);
1983	}
1984	else
1985	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1986	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1987
1988	/*
1989	* Insert the range into the table (replaces/splits/shrinks existing
1990	* MSR ranges).
1991	*/
1992	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1993	&MsrRange);
1994	if (RT_FAILURE(rc))
1995	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
1996	}
1997
1998	return VINF_SUCCESS;
1999	}
2000
2001
2002	/**
2003	* Loads CPUID leaf overrides.
2004	*
2005	* This must be called before the CPUID leaves are moved from the normal
2006	* heap to the hyper heap!
2007	*
2008	* @returns VBox status code (VMSetError called).
2009	* @param pVM The cross context VM structure.
2010	* @param pParentNode The CFGM node with the CPUID leaves.
2011	* @param pszLabel How to label the overrides we're loading.
2012	*/
2013	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2014	{
2015	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2016	{
2017	/*
2018	* Get the leaf and subleaf numbers.
2019	*/
2020	char szName[128];
2021	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2022	if (RT_FAILURE(rc))
2023	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2024
2025	/* The leaf number is either specified directly or thru the node name. */
2026	uint32_t uLeaf;
2027	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2028	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2029	{
2030	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2031	if (rc != VINF_SUCCESS)
2032	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2033	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2034	}
2035	else if (RT_FAILURE(rc))
2036	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2037	pszLabel, szName, rc);
2038
2039	uint32_t uSubLeaf;
2040	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2041	if (RT_FAILURE(rc))
2042	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2043	pszLabel, szName, rc);
2044
2045	uint32_t fSubLeafMask;
2046	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2047	if (RT_FAILURE(rc))
2048	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2049	pszLabel, szName, rc);
2050
2051	/*
2052	* Look up the specified leaf, since the output register values
2053	* defaults to any existing values. This allows overriding a single
2054	* register, without needing to know the other values.
2055	*/
2056	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2057	CPUMCPUIDLEAF Leaf;
2058	if (pLeaf)
2059	Leaf = *pLeaf;
2060	else
2061	RT_ZERO(Leaf);
2062	Leaf.uLeaf = uLeaf;
2063	Leaf.uSubLeaf = uSubLeaf;
2064	Leaf.fSubLeafMask = fSubLeafMask;
2065
2066	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2067	if (RT_FAILURE(rc))
2068	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2069	pszLabel, szName, rc);
2070	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2071	if (RT_FAILURE(rc))
2072	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2073	pszLabel, szName, rc);
2074	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2075	if (RT_FAILURE(rc))
2076	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2077	pszLabel, szName, rc);
2078	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2079	if (RT_FAILURE(rc))
2080	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2081	pszLabel, szName, rc);
2082
2083	/*
2084	* Insert the leaf into the table (replaces existing ones).
2085	*/
2086	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2087	&Leaf);
2088	if (RT_FAILURE(rc))
2089	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2090	}
2091
2092	return VINF_SUCCESS;
2093	}
2094
2095
2096
2097	/**
2098	* Fetches overrides for a CPUID leaf.
2099	*
2100	* @returns VBox status code.
2101	* @param pLeaf The leaf to load the overrides into.
2102	* @param pCfgNode The CFGM node containing the overrides
2103	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2104	* @param iLeaf The CPUID leaf number.
2105	*/
2106	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2107	{
2108	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2109	if (pLeafNode)
2110	{
2111	uint32_t u32;
2112	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2113	if (RT_SUCCESS(rc))
2114	pLeaf->uEax = u32;
2115	else
2116	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2117
2118	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2119	if (RT_SUCCESS(rc))
2120	pLeaf->uEbx = u32;
2121	else
2122	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2123
2124	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2125	if (RT_SUCCESS(rc))
2126	pLeaf->uEcx = u32;
2127	else
2128	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2129
2130	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2131	if (RT_SUCCESS(rc))
2132	pLeaf->uEdx = u32;
2133	else
2134	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2135
2136	}
2137	return VINF_SUCCESS;
2138	}
2139
2140
2141	/**
2142	* Load the overrides for a set of CPUID leaves.
2143	*
2144	* @returns VBox status code.
2145	* @param paLeaves The leaf array.
2146	* @param cLeaves The number of leaves.
2147	* @param uStart The start leaf number.
2148	* @param pCfgNode The CFGM node containing the overrides
2149	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2150	*/
2151	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2152	{
2153	for (uint32_t i = 0; i < cLeaves; i++)
2154	{
2155	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2156	if (RT_FAILURE(rc))
2157	return rc;
2158	}
2159
2160	return VINF_SUCCESS;
2161	}
2162
2163
2164	/**
2165	* Installs the CPUID leaves and explods the data into structures like
2166	* GuestFeatures and CPUMCTX::aoffXState.
2167	*
2168	* @returns VBox status code.
2169	* @param pVM The cross context VM structure.
2170	* @param pCpum The CPUM part of @a VM.
2171	* @param paLeaves The leaves. These will be copied (but not freed).
2172	* @param cLeaves The number of leaves.
2173	*/
2174	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
2175	{
2176	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2177
2178	/*
2179	* Install the CPUID information.
2180	*/
2181	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2182	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2183
2184	AssertLogRelRCReturn(rc, rc);
2185	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2186	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2187	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2188	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2189	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2190
2191	/*
2192	* Update the default CPUID leaf if necessary.
2193	*/
2194	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2195	{
2196	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2197	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2198	{
2199	/* We don't use CPUID(0).eax here because of the NT hack that only
2200	changes that value without actually removing any leaves. */
2201	uint32_t i = 0;
2202	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2203	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2204	{
2205	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2206	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2207	i++;
2208	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2209	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2210	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2211	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2212	}
2213	break;
2214	}
2215	default:
2216	break;
2217	}
2218
2219	/*
2220	* Explode the guest CPU features.
2221	*/
2222	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
2223	AssertLogRelRCReturn(rc, rc);
2224
2225	/*
2226	* Adjust the scalable bus frequency according to the CPUID information
2227	* we're now using.
2228	*/
2229	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2230	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2231	? UINT64_C(100000000) /* 100MHz */
2232	: UINT64_C(133333333); /* 133MHz */
2233
2234	/*
2235	* Populate the legacy arrays. Currently used for everything, later only
2236	* for patch manager.
2237	*/
2238	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2239	{
2240	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2241	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2242	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2243	};
2244	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2245	{
2246	uint32_t cLeft = aOldRanges[i].cCpuIds;
2247	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2248	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2249	while (cLeft-- > 0)
2250	{
2251	uLeaf--;
2252	pLegacyLeaf--;
2253
2254	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2255	if (pLeaf)
2256	{
2257	pLegacyLeaf->uEax = pLeaf->uEax;
2258	pLegacyLeaf->uEbx = pLeaf->uEbx;
2259	pLegacyLeaf->uEcx = pLeaf->uEcx;
2260	pLegacyLeaf->uEdx = pLeaf->uEdx;
2261	}
2262	else
2263	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2264	}
2265	}
2266
2267	/*
2268	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2269	*/
2270	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2271	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2272	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2273	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2274	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2275	{
2276	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2277	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2278	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2279	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2280	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2281	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2282	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2283	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2284	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2285	pCpum->GuestFeatures.cbMaxExtendedState),
2286	VERR_CPUM_IPE_1);
2287	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2288	}
2289	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2290
2291	/* Copy the CPU #0 data to the other CPUs. */
2292	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2293	{
2294	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2295	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2296	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2297	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2298	}
2299
2300	return VINF_SUCCESS;
2301	}
2302
2303
2304	/** @name Instruction Set Extension Options
2305	* @{ */
2306	/** Configuration option type (extended boolean, really). */
2307	typedef uint8_t CPUMISAEXTCFG;
2308	/** Always disable the extension. */
2309	#define CPUMISAEXTCFG_DISABLED false
2310	/** Enable the extension if it's supported by the host CPU. */
2311	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2312	/** Enable the extension if it's supported by the host CPU, but don't let
2313	* the portable CPUID feature disable it. */
2314	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2315	/** Always enable the extension. */
2316	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2317	/** @} */
2318
2319	/**
2320	* CPUID Configuration (from CFGM).
2321	*
2322	* @remarks The members aren't document since we would only be duplicating the
2323	* \@cfgm entries in cpumR3CpuIdReadConfig.
2324	*/
2325	typedef struct CPUMCPUIDCONFIG
2326	{
2327	bool fNt4LeafLimit;
2328	bool fInvariantTsc;
2329	bool fForceVme;
2330	bool fNestedHWVirt;
2331
2332	CPUMISAEXTCFG enmCmpXchg16b;
2333	CPUMISAEXTCFG enmMonitor;
2334	CPUMISAEXTCFG enmMWaitExtensions;
2335	CPUMISAEXTCFG enmSse41;
2336	CPUMISAEXTCFG enmSse42;
2337	CPUMISAEXTCFG enmAvx;
2338	CPUMISAEXTCFG enmAvx2;
2339	CPUMISAEXTCFG enmXSave;
2340	CPUMISAEXTCFG enmAesNi;
2341	CPUMISAEXTCFG enmPClMul;
2342	CPUMISAEXTCFG enmPopCnt;
2343	CPUMISAEXTCFG enmMovBe;
2344	CPUMISAEXTCFG enmRdRand;
2345	CPUMISAEXTCFG enmRdSeed;
2346	CPUMISAEXTCFG enmCLFlushOpt;
2347	CPUMISAEXTCFG enmFsGsBase;
2348	CPUMISAEXTCFG enmPcid;
2349	CPUMISAEXTCFG enmInvpcid;
2350
2351	CPUMISAEXTCFG enmAbm;
2352	CPUMISAEXTCFG enmSse4A;
2353	CPUMISAEXTCFG enmMisAlnSse;
2354	CPUMISAEXTCFG enm3dNowPrf;
2355	CPUMISAEXTCFG enmAmdExtMmx;
2356
2357	uint32_t uMaxStdLeaf;
2358	uint32_t uMaxExtLeaf;
2359	uint32_t uMaxCentaurLeaf;
2360	uint32_t uMaxIntelFamilyModelStep;
2361	char szCpuName[128];
2362	} CPUMCPUIDCONFIG;
2363	/** Pointer to CPUID config (from CFGM). */
2364	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2365
2366
2367	/**
2368	* Mini CPU selection support for making Mac OS X happy.
2369	*
2370	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2371	*
2372	* @param pCpum The CPUM instance data.
2373	* @param pConfig The CPUID configuration we've read from CFGM.
2374	*/
2375	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2376	{
2377	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2378	{
2379	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2380	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2381	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2382	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2383	0);
2384	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2385	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2386	{
2387	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2388	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2389	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2390	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2391	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2392	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2393	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2394	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2395	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2396	pStdFeatureLeaf->uEax = uNew;
2397	}
2398	}
2399	}
2400
2401
2402
2403	/**
2404	* Limit it the number of entries, zapping the remainder.
2405	*
2406	* The limits are masking off stuff about power saving and similar, this
2407	* is perhaps a bit crudely done as there is probably some relatively harmless
2408	* info too in these leaves (like words about having a constant TSC).
2409	*
2410	* @param pCpum The CPUM instance data.
2411	* @param pConfig The CPUID configuration we've read from CFGM.
2412	*/
2413	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2414	{
2415	/*
2416	* Standard leaves.
2417	*/
2418	uint32_t uSubLeaf = 0;
2419	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2420	if (pCurLeaf)
2421	{
2422	uint32_t uLimit = pCurLeaf->uEax;
2423	if (uLimit <= UINT32_C(0x000fffff))
2424	{
2425	if (uLimit > pConfig->uMaxStdLeaf)
2426	{
2427	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2428	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2429	uLimit + 1, UINT32_C(0x000fffff));
2430	}
2431
2432	/* NT4 hack, no zapping of extra leaves here. */
2433	if (pConfig->fNt4LeafLimit && uLimit > 3)
2434	pCurLeaf->uEax = uLimit = 3;
2435
2436	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2437	pCurLeaf->uEax = uLimit;
2438	}
2439	else
2440	{
2441	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2442	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2443	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2444	}
2445	}
2446
2447	/*
2448	* Extended leaves.
2449	*/
2450	uSubLeaf = 0;
2451	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2452	if (pCurLeaf)
2453	{
2454	uint32_t uLimit = pCurLeaf->uEax;
2455	if ( uLimit >= UINT32_C(0x80000000)
2456	&& uLimit <= UINT32_C(0x800fffff))
2457	{
2458	if (uLimit > pConfig->uMaxExtLeaf)
2459	{
2460	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2461	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2462	uLimit + 1, UINT32_C(0x800fffff));
2463	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2464	pCurLeaf->uEax = uLimit;
2465	}
2466	}
2467	else
2468	{
2469	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2470	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2471	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2472	}
2473	}
2474
2475	/*
2476	* Centaur leaves (VIA).
2477	*/
2478	uSubLeaf = 0;
2479	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2480	if (pCurLeaf)
2481	{
2482	uint32_t uLimit = pCurLeaf->uEax;
2483	if ( uLimit >= UINT32_C(0xc0000000)
2484	&& uLimit <= UINT32_C(0xc00fffff))
2485	{
2486	if (uLimit > pConfig->uMaxCentaurLeaf)
2487	{
2488	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2489	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2490	uLimit + 1, UINT32_C(0xcfffffff));
2491	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2492	pCurLeaf->uEax = uLimit;
2493	}
2494	}
2495	else
2496	{
2497	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2498	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2499	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2500	}
2501	}
2502	}
2503
2504
2505	/**
2506	* Clears a CPUID leaf and all sub-leaves (to zero).
2507	*
2508	* @param pCpum The CPUM instance data.
2509	* @param uLeaf The leaf to clear.
2510	*/
2511	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2512	{
2513	uint32_t uSubLeaf = 0;
2514	PCPUMCPUIDLEAF pCurLeaf;
2515	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2516	{
2517	pCurLeaf->uEax = 0;
2518	pCurLeaf->uEbx = 0;
2519	pCurLeaf->uEcx = 0;
2520	pCurLeaf->uEdx = 0;
2521	uSubLeaf++;
2522	}
2523	}
2524
2525
2526	/**
2527	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2528	* the given leaf.
2529	*
2530	* @returns pLeaf.
2531	* @param pCpum The CPUM instance data.
2532	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2533	*/
2534	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2535	{
2536	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2537	if (pLeaf->fSubLeafMask != 0)
2538	{
2539	/*
2540	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2541	* Log everything while we're at it.
2542	*/
2543	LogRel(("CPUM:\n"
2544	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2545	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2546	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2547	for (;;)
2548	{
2549	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2550	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2551	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2552	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2553	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2554	break;
2555	pSubLeaf++;
2556	}
2557	LogRel(("CPUM:\n"));
2558
2559	/*
2560	* Remove the offending sub-leaves.
2561	*/
2562	if (pSubLeaf != pLeaf)
2563	{
2564	if (pSubLeaf != pLast)
2565	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2566	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2567	}
2568
2569	/*
2570	* Convert the first sub-leaf into a single leaf.
2571	*/
2572	pLeaf->uSubLeaf = 0;
2573	pLeaf->fSubLeafMask = 0;
2574	}
2575	return pLeaf;
2576	}
2577
2578
2579	/**
2580	* Sanitizes and adjust the CPUID leaves.
2581	*
2582	* Drop features that aren't virtualized (or virtualizable). Adjust information
2583	* and capabilities to fit the virtualized hardware. Remove information the
2584	* guest shouldn't have (because it's wrong in the virtual world or because it
2585	* gives away host details) or that we don't have documentation for and no idea
2586	* what means.
2587	*
2588	* @returns VBox status code.
2589	* @param pVM The cross context VM structure (for cCpus).
2590	* @param pCpum The CPUM instance data.
2591	* @param pConfig The CPUID configuration we've read from CFGM.
2592	*/
2593	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2594	{
2595	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2596	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2597	{ \
2598	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2599	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2600	}
2601	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2602	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2603	{ \
2604	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2605	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2606	}
2607	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2608	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2609	&& ((a_pLeafReg) & (fBitMask)) \
2610	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2611	{ \
2612	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2613	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2614	}
2615	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2616
2617	/* Cpuid 1:
2618	* EAX: CPU model, family and stepping.
2619	*
2620	* ECX + EDX: Supported features. Only report features we can support.
2621	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2622	* options may require adjusting (i.e. stripping what was enabled).
2623	*
2624	* EBX: Branding, CLFLUSH line size, logical processors per package and
2625	* initial APIC ID.
2626	*/
2627	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2628	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2629	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2630
2631	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2632	\| X86_CPUID_FEATURE_EDX_VME
2633	\| X86_CPUID_FEATURE_EDX_DE
2634	\| X86_CPUID_FEATURE_EDX_PSE
2635	\| X86_CPUID_FEATURE_EDX_TSC
2636	\| X86_CPUID_FEATURE_EDX_MSR
2637	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2638	\| X86_CPUID_FEATURE_EDX_MCE
2639	\| X86_CPUID_FEATURE_EDX_CX8
2640	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2641	//\| RT_BIT_32(10) - not defined
2642	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2643	//\| X86_CPUID_FEATURE_EDX_SEP
2644	\| X86_CPUID_FEATURE_EDX_MTRR
2645	\| X86_CPUID_FEATURE_EDX_PGE
2646	\| X86_CPUID_FEATURE_EDX_MCA
2647	\| X86_CPUID_FEATURE_EDX_CMOV
2648	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2649	\| X86_CPUID_FEATURE_EDX_PSE36
2650	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2651	\| X86_CPUID_FEATURE_EDX_CLFSH
2652	//\| RT_BIT_32(20) - not defined
2653	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2654	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2655	\| X86_CPUID_FEATURE_EDX_MMX
2656	\| X86_CPUID_FEATURE_EDX_FXSR
2657	\| X86_CPUID_FEATURE_EDX_SSE
2658	\| X86_CPUID_FEATURE_EDX_SSE2
2659	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2660	\| X86_CPUID_FEATURE_EDX_HTT
2661	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2662	//\| RT_BIT_32(30) - not defined
2663	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2664	;
2665	pStdFeatureLeaf->uEcx &= 0
2666	\| X86_CPUID_FEATURE_ECX_SSE3
2667	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2668	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2669	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2670	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2671	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2672	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized yet.
2673	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2674	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2675	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2676	\| X86_CPUID_FEATURE_ECX_SSSE3
2677	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2678	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2679	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2680	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2681	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2682	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2683	\| (pConfig->enmPcid ? X86_CPUID_FEATURE_ECX_PCID : 0)
2684	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2685	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2686	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2687	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2688	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2689	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2690	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2691	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2692	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2693	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2694	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2695	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2696	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2697	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2698	;
2699
2700	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2701	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2702	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2703	{
2704	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2705	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2706	}
2707
2708	if (pCpum->u8PortableCpuIdLevel > 0)
2709	{
2710	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2711	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2712	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2713	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2714	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2715	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2716	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2717	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2718	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2719	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2720	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2721	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2722	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2723	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2724	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2725	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2726	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2727	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2728	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2729
2730	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2731	\| X86_CPUID_FEATURE_EDX_PSN
2732	\| X86_CPUID_FEATURE_EDX_DS
2733	\| X86_CPUID_FEATURE_EDX_ACPI
2734	\| X86_CPUID_FEATURE_EDX_SS
2735	\| X86_CPUID_FEATURE_EDX_TM
2736	\| X86_CPUID_FEATURE_EDX_PBE
2737	)));
2738	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2739	\| X86_CPUID_FEATURE_ECX_CPLDS
2740	\| X86_CPUID_FEATURE_ECX_VMX
2741	\| X86_CPUID_FEATURE_ECX_SMX
2742	\| X86_CPUID_FEATURE_ECX_EST
2743	\| X86_CPUID_FEATURE_ECX_TM2
2744	\| X86_CPUID_FEATURE_ECX_CNTXID
2745	\| X86_CPUID_FEATURE_ECX_FMA
2746	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2747	\| X86_CPUID_FEATURE_ECX_PDCM
2748	\| X86_CPUID_FEATURE_ECX_DCA
2749	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2750	)));
2751	}
2752
2753	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2754	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2755
2756	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2757	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2758	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2759	*/
2760	#ifdef VBOX_WITH_MULTI_CORE
2761	if (pVM->cCpus > 1)
2762	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2763	#endif
2764	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2765	{
2766	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2767	core times the number of CPU cores per processor */
2768	#ifdef VBOX_WITH_MULTI_CORE
2769	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2770	#else
2771	/* Single logical processor in a package. */
2772	pStdFeatureLeaf->uEbx \|= (1 << 16);
2773	#endif
2774	}
2775
2776	uint32_t uMicrocodeRev;
2777	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2778	if (RT_SUCCESS(rc))
2779	{
2780	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2781	}
2782	else
2783	{
2784	uMicrocodeRev = 0;
2785	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2786	}
2787
2788	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2789	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2790	*/
2791	if ( (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen)
2792	&& uMicrocodeRev < 0x8001126
2793	&& !pConfig->fForceVme)
2794	{
2795	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2796	LogRel(("CPUM: Zen VME workaround engaged\n"));
2797	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2798	}
2799
2800	/* Force standard feature bits. */
2801	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2802	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2803	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2804	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2805	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2806	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2807	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2808	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2809	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2810	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2811	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2812	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2813	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2814	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2815	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2816	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2817	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2818	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2819	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2820	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2821	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2822	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2823
2824	pStdFeatureLeaf = NULL; /* Must refetch! */
2825
2826	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2827	* AMD:
2828	* EAX: CPU model, family and stepping.
2829	*
2830	* ECX + EDX: Supported features. Only report features we can support.
2831	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2832	* options may require adjusting (i.e. stripping what was enabled).
2833	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2834	*
2835	* EBX: Branding ID and package type (or reserved).
2836	*
2837	* Intel and probably most others:
2838	* EAX: 0
2839	* EBX: 0
2840	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2841	*/
2842	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2843	if (pExtFeatureLeaf)
2844	{
2845	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2846
2847	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2848	\| X86_CPUID_AMD_FEATURE_EDX_VME
2849	\| X86_CPUID_AMD_FEATURE_EDX_DE
2850	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2851	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2852	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2853	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2854	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2855	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2856	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2857	//\| RT_BIT_32(10) - reserved
2858	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2859	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2860	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2861	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2862	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2863	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2864	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2865	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2866	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2867	//\| RT_BIT_32(18) - reserved
2868	//\| RT_BIT_32(19) - reserved
2869	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2870	//\| RT_BIT_32(21) - reserved
2871	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2872	\| X86_CPUID_AMD_FEATURE_EDX_MMX
2873	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
2874	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
2875	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2876	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2877	//\| RT_BIT_32(28) - reserved
2878	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2879	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2880	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
2881	;
2882	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2883	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2884	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
2885	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2886	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
2887	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2888	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2889	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2890	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2891	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2892	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2893	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
2894	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
2895	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2896	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
2897	//\| RT_BIT_32(14) - reserved
2898	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2899	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2900	//\| RT_BIT_32(17) - reserved
2901	//\| RT_BIT_32(18) - reserved
2902	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2903	//\| RT_BIT_32(20) - reserved
2904	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2905	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2906	//\| RT_BIT_32(23) - reserved
2907	//\| RT_BIT_32(24) - reserved
2908	//\| RT_BIT_32(25) - reserved
2909	//\| RT_BIT_32(26) - reserved
2910	//\| RT_BIT_32(27) - reserved
2911	//\| RT_BIT_32(28) - reserved
2912	//\| RT_BIT_32(29) - reserved
2913	//\| RT_BIT_32(30) - reserved
2914	//\| RT_BIT_32(31) - reserved
2915	;
2916	#ifdef VBOX_WITH_MULTI_CORE
2917	if ( pVM->cCpus > 1
2918	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2919	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2920	#endif
2921
2922	if (pCpum->u8PortableCpuIdLevel > 0)
2923	{
2924	CPUMISAEXTCFG enmSvm = pConfig->fNestedHWVirt ? CPUMISAEXTCFG_ENABLED_SUPPORTED : CPUMISAEXTCFG_DISABLED;
2925	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2926	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM, enmSvm);
2927	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2928	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2929	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2930	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2931	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2932	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2933	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2934	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2935	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2936	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2937	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2938	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2939	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2940	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2941
2942	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2943	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2944	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2945	\| X86_CPUID_AMD_FEATURE_ECX_IBS
2946	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2947	\| X86_CPUID_AMD_FEATURE_ECX_WDT
2948	\| X86_CPUID_AMD_FEATURE_ECX_LWP
2949	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
2950	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2951	\| UINT32_C(0xff964000)
2952	)));
2953	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2954	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2955	\| RT_BIT(18)
2956	\| RT_BIT(19)
2957	\| RT_BIT(21)
2958	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2959	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2960	\| RT_BIT(28)
2961	)));
2962	}
2963
2964	/* Force extended feature bits. */
2965	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2966	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
2967	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2968	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2969	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2970	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2971	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2972	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2973	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2974	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2975	}
2976	pExtFeatureLeaf = NULL; /* Must refetch! */
2977
2978
2979	/* Cpuid 2:
2980	* Intel: (Nondeterministic) Cache and TLB information
2981	* AMD: Reserved
2982	* VIA: Reserved
2983	* Safe to expose.
2984	*/
2985	uint32_t uSubLeaf = 0;
2986	PCPUMCPUIDLEAF pCurLeaf;
2987	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2988	{
2989	if ((pCurLeaf->uEax & 0xff) > 1)
2990	{
2991	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2992	pCurLeaf->uEax &= UINT32_C(0xffffff01);
2993	}
2994	uSubLeaf++;
2995	}
2996
2997	/* Cpuid 3:
2998	* Intel: EAX, EBX - reserved (transmeta uses these)
2999	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3000	* AMD: Reserved
3001	* VIA: Reserved
3002	* Safe to expose
3003	*/
3004	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3005	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3006	{
3007	uSubLeaf = 0;
3008	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3009	{
3010	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3011	if (pCpum->u8PortableCpuIdLevel > 0)
3012	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3013	uSubLeaf++;
3014	}
3015	}
3016
3017	/* Cpuid 4 + ECX:
3018	* Intel: Deterministic Cache Parameters Leaf.
3019	* AMD: Reserved
3020	* VIA: Reserved
3021	* Safe to expose, except for EAX:
3022	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3023	* Bits 31-26: Maximum number of processor cores in this physical package**
3024	* Note: These SMP values are constant regardless of ECX
3025	*/
3026	uSubLeaf = 0;
3027	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3028	{
3029	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3030	#ifdef VBOX_WITH_MULTI_CORE
3031	if ( pVM->cCpus > 1
3032	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3033	{
3034	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3035	/* One logical processor with possibly multiple cores. */
3036	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3037	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3038	}
3039	#endif
3040	uSubLeaf++;
3041	}
3042
3043	/* Cpuid 5: Monitor/mwait Leaf
3044	* Intel: ECX, EDX - reserved
3045	* EAX, EBX - Smallest and largest monitor line size
3046	* AMD: EDX - reserved
3047	* EAX, EBX - Smallest and largest monitor line size
3048	* ECX - extensions (ignored for now)
3049	* VIA: Reserved
3050	* Safe to expose
3051	*/
3052	uSubLeaf = 0;
3053	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3054	{
3055	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3056	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3057	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3058
3059	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3060	if (pConfig->enmMWaitExtensions)
3061	{
3062	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3063	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3064	it shall be part of our power management virtualization model */
3065	#if 0
3066	/* MWAIT sub C-states */
3067	pCurLeaf->uEdx =
3068	(0 << 0) /* 0 in C0 */ \|
3069	(2 << 4) /* 2 in C1 */ \|
3070	(2 << 8) /* 2 in C2 */ \|
3071	(2 << 12) /* 2 in C3 */ \|
3072	(0 << 16) /* 0 in C4 */
3073	;
3074	#endif
3075	}
3076	else
3077	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3078	uSubLeaf++;
3079	}
3080
3081	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3082	* Intel: Various stuff.
3083	* AMD: EAX, EBX, EDX - reserved.
3084	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3085	* present. Same as intel.
3086	* VIA: ??
3087	*
3088	* We clear everything here for now.
3089	*/
3090	cpumR3CpuIdZeroLeaf(pCpum, 6);
3091
3092	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3093	* EAX: Number of sub leaves.
3094	* EBX+ECX+EDX: Feature flags
3095	*
3096	* We only have documentation for one sub-leaf, so clear all other (no need
3097	* to remove them as such, just set them to zero).
3098	*
3099	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3100	* options may require adjusting (i.e. stripping what was enabled).
3101	*/
3102	uSubLeaf = 0;
3103	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3104	{
3105	switch (uSubLeaf)
3106	{
3107	case 0:
3108	{
3109	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3110	pCurLeaf->uEbx &= 0
3111	\| (pConfig->enmFsGsBase ? X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE : 0)
3112	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3113	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3114	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3115	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3116	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3117	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3118	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3119	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3120	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3121	\| (pConfig->enmInvpcid ? X86_CPUID_STEXT_FEATURE_EBX_INVPCID : 0)
3122	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3123	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3124	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3125	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3126	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3127	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3128	//\| RT_BIT(17) - reserved
3129	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3130	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3131	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3132	//\| RT_BIT(21) - reserved
3133	//\| RT_BIT(22) - reserved
3134	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3135	//\| RT_BIT(24) - reserved
3136	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3137	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3138	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3139	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3140	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3141	//\| RT_BIT(30) - reserved
3142	//\| RT_BIT(31) - reserved
3143	;
3144	pCurLeaf->uEcx &= 0
3145	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3146	;
3147	pCurLeaf->uEdx &= 0
3148	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3149	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3150	//\| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT(29)
3151	;
3152
3153	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3154	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3155	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3156	{
3157	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3158	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3159	}
3160
3161	if (pCpum->u8PortableCpuIdLevel > 0)
3162	{
3163	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3164	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3165	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3166	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3167	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3168	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3169	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3170	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3171	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3172	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3173	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3174	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3175	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3176	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3177	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3178	}
3179
3180	/* Force standard feature bits. */
3181	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3182	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3183	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3184	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3185	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3186	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3187	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3188	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3189	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3190	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3191	break;
3192	}
3193
3194	default:
3195	/* Invalid index, all values are zero. */
3196	pCurLeaf->uEax = 0;
3197	pCurLeaf->uEbx = 0;
3198	pCurLeaf->uEcx = 0;
3199	pCurLeaf->uEdx = 0;
3200	break;
3201	}
3202	uSubLeaf++;
3203	}
3204
3205	/* Cpuid 8: Marked as reserved by Intel and AMD.
3206	* We zero this since we don't know what it may have been used for.
3207	*/
3208	cpumR3CpuIdZeroLeaf(pCpum, 8);
3209
3210	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3211	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3212	* EBX, ECX, EDX - reserved.
3213	* AMD: Reserved
3214	* VIA: ??
3215	*
3216	* We zero this.
3217	*/
3218	cpumR3CpuIdZeroLeaf(pCpum, 9);
3219
3220	/* Cpuid 0xa: Architectural Performance Monitor Features
3221	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3222	* EBX, ECX, EDX - reserved.
3223	* AMD: Reserved
3224	* VIA: ??
3225	*
3226	* We zero this, for now at least.
3227	*/
3228	cpumR3CpuIdZeroLeaf(pCpum, 10);
3229
3230	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3231	* Intel: EAX - APCI ID shift right for next level.
3232	* EBX - Factory configured cores/threads at this level.
3233	* ECX - Level number (same as input) and level type (1,2,0).
3234	* EDX - Extended initial APIC ID.
3235	* AMD: Reserved
3236	* VIA: ??
3237	*/
3238	uSubLeaf = 0;
3239	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3240	{
3241	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3242	{
3243	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3244	if (bLevelType == 1)
3245	{
3246	/* Thread level - we don't do threads at the moment. */
3247	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3248	pCurLeaf->uEbx = 1;
3249	}
3250	else if (bLevelType == 2)
3251	{
3252	/* Core level. */
3253	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3254	#ifdef VBOX_WITH_MULTI_CORE
3255	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3256	pCurLeaf->uEax++;
3257	#endif
3258	pCurLeaf->uEbx = pVM->cCpus;
3259	}
3260	else
3261	{
3262	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3263	pCurLeaf->uEax = 0;
3264	pCurLeaf->uEbx = 0;
3265	pCurLeaf->uEcx = 0;
3266	}
3267	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3268	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3269	}
3270	else
3271	{
3272	pCurLeaf->uEax = 0;
3273	pCurLeaf->uEbx = 0;
3274	pCurLeaf->uEcx = 0;
3275	pCurLeaf->uEdx = 0;
3276	}
3277	uSubLeaf++;
3278	}
3279
3280	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3281	* We zero this since we don't know what it may have been used for.
3282	*/
3283	cpumR3CpuIdZeroLeaf(pCpum, 12);
3284
3285	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3286	* ECX=0: EAX - Valid bits in XCR0[31:0].
3287	* EBX - Maximum state size as per current XCR0 value.
3288	* ECX - Maximum state size for all supported features.
3289	* EDX - Valid bits in XCR0[63:32].
3290	* ECX=1: EAX - Various X-features.
3291	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3292	* ECX - Valid bits in IA32_XSS[31:0].
3293	* EDX - Valid bits in IA32_XSS[63:32].
3294	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3295	* if the bit invalid all four registers are set to zero.
3296	* EAX - The state size for this feature.
3297	* EBX - The state byte offset of this feature.
3298	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3299	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3300	*
3301	* Clear them all as we don't currently implement extended CPU state.
3302	*/
3303	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3304	uint64_t fGuestXcr0Mask = 0;
3305	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3306	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3307	{
3308	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3309	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3310	fGuestXcr0Mask \|= XSAVE_C_YMM;
3311	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3312	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3313	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3314	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3315
3316	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3317	}
3318	pStdFeatureLeaf = NULL;
3319	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3320
3321	/* Work the sub-leaves. */
3322	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3323	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3324	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3325	{
3326	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3327	if (pCurLeaf)
3328	{
3329	if (fGuestXcr0Mask)
3330	{
3331	switch (uSubLeaf)
3332	{
3333	case 0:
3334	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3335	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3336	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3337	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3338	VERR_CPUM_IPE_1);
3339	cbXSaveMaxActual = pCurLeaf->uEcx;
3340	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3341	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3342	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3343	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3344	VERR_CPUM_IPE_2);
3345	continue;
3346	case 1:
3347	pCurLeaf->uEax &= 0;
3348	pCurLeaf->uEcx &= 0;
3349	pCurLeaf->uEdx &= 0;
3350	/** @todo what about checking ebx? */
3351	continue;
3352	default:
3353	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3354	{
3355	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3356	&& pCurLeaf->uEax > 0
3357	&& pCurLeaf->uEbx < cbXSaveMaxActual
3358	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3359	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3360	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3361	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3362	VERR_CPUM_IPE_2);
3363	AssertLogRel(!(pCurLeaf->uEcx & 1));
3364	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3365	pCurLeaf->uEdx = 0; /* it's reserved... */
3366	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3367	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3368	continue;
3369	}
3370	break;
3371	}
3372	}
3373
3374	/* Clear the leaf. */
3375	pCurLeaf->uEax = 0;
3376	pCurLeaf->uEbx = 0;
3377	pCurLeaf->uEcx = 0;
3378	pCurLeaf->uEdx = 0;
3379	}
3380	}
3381
3382	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3383	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3384	{
3385	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3386	if (pCurLeaf)
3387	{
3388	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3389	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3390	pCurLeaf->uEbx = cbXSaveMaxReport;
3391	pCurLeaf->uEcx = cbXSaveMaxReport;
3392	}
3393	}
3394
3395	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3396	* We zero this since we don't know what it may have been used for.
3397	*/
3398	cpumR3CpuIdZeroLeaf(pCpum, 14);
3399
3400	/* Cpuid 0xf + ECX: Platform qualifity of service monitoring (PQM).
3401	* We zero this as we don't currently virtualize PQM.
3402	*/
3403	cpumR3CpuIdZeroLeaf(pCpum, 15);
3404
3405	/* Cpuid 0x10 + ECX: Platform qualifity of service enforcement (PQE).
3406	* We zero this as we don't currently virtualize PQE.
3407	*/
3408	cpumR3CpuIdZeroLeaf(pCpum, 16);
3409
3410	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3411	* We zero this since we don't know what it may have been used for.
3412	*/
3413	cpumR3CpuIdZeroLeaf(pCpum, 17);
3414
3415	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3416	* We zero this as we don't currently virtualize this.
3417	*/
3418	cpumR3CpuIdZeroLeaf(pCpum, 18);
3419
3420	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3421	* We zero this since we don't know what it may have been used for.
3422	*/
3423	cpumR3CpuIdZeroLeaf(pCpum, 19);
3424
3425	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3426	* We zero this as we don't currently virtualize this.
3427	*/
3428	cpumR3CpuIdZeroLeaf(pCpum, 20);
3429
3430	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3431	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3432	* EAX - denominator (unsigned).
3433	* EBX - numerator (unsigned).
3434	* ECX, EDX - reserved.
3435	* AMD: Reserved / undefined / not implemented.
3436	* VIA: Reserved / undefined / not implemented.
3437	* We zero this as we don't currently virtualize this.
3438	*/
3439	cpumR3CpuIdZeroLeaf(pCpum, 21);
3440
3441	/* Cpuid 0x16: Processor frequency info
3442	* Intel: EAX - Core base frequency in MHz.
3443	* EBX - Core maximum frequency in MHz.
3444	* ECX - Bus (reference) frequency in MHz.
3445	* EDX - Reserved.
3446	* AMD: Reserved / undefined / not implemented.
3447	* VIA: Reserved / undefined / not implemented.
3448	* We zero this as we don't currently virtualize this.
3449	*/
3450	cpumR3CpuIdZeroLeaf(pCpum, 22);
3451
3452	/* Cpuid 0x17..0x10000000: Unknown.
3453	* We don't know these and what they mean, so remove them. */
3454	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3455	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3456
3457
3458	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3459	* We remove all these as we're a hypervisor and must provide our own.
3460	*/
3461	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3462	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3463
3464
3465	/* Cpuid 0x80000000 is harmless. */
3466
3467	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3468
3469	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3470
3471	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3472	* Safe to pass on to the guest.
3473	*
3474	* AMD: 0x800000005 L1 cache information
3475	* 0x800000006 L2/L3 cache information
3476	* Intel: 0x800000005 reserved
3477	* 0x800000006 L2 cache information
3478	* VIA: 0x800000005 TLB and L1 cache information
3479	* 0x800000006 L2 cache information
3480	*/
3481
3482	/* Cpuid 0x800000007: Advanced Power Management Information.
3483	* AMD: EAX: Processor feedback capabilities.
3484	* EBX: RAS capabilites.
3485	* ECX: Advanced power monitoring interface.
3486	* EDX: Enhanced power management capabilities.
3487	* Intel: EAX, EBX, ECX - reserved.
3488	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3489	* VIA: Reserved
3490	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3491	*/
3492	uSubLeaf = 0;
3493	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3494	{
3495	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3496	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3497	{
3498	/*
3499	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3500	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3501	* bit is now configurable.
3502	*/
3503	pCurLeaf->uEdx &= 0
3504	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3505	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3506	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3507	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3508	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3509	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3510	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3511	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3512	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3513	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3514	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3515	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3516	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3517	\| 0;
3518	}
3519	else
3520	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3521	if (!pConfig->fInvariantTsc)
3522	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3523	uSubLeaf++;
3524	}
3525
3526	/* Cpuid 0x80000008:
3527	* AMD: EBX, EDX - reserved
3528	* EAX: Virtual/Physical/Guest address Size
3529	* ECX: Number of cores + APICIdCoreIdSize
3530	* Intel: EAX: Virtual/Physical address Size
3531	* EBX, ECX, EDX - reserved
3532	* VIA: EAX: Virtual/Physical address Size
3533	* EBX, ECX, EDX - reserved
3534	*
3535	* We only expose the virtual+pysical address size to the guest atm.
3536	* On AMD we set the core count, but not the apic id stuff as we're
3537	* currently not doing the apic id assignments in a complatible manner.
3538	*/
3539	uSubLeaf = 0;
3540	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3541	{
3542	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3543	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3544	pCurLeaf->uEdx = 0; /* reserved */
3545
3546	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3547	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3548	pCurLeaf->uEcx = 0;
3549	#ifdef VBOX_WITH_MULTI_CORE
3550	if ( pVM->cCpus > 1
3551	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3552	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3553	#endif
3554	uSubLeaf++;
3555	}
3556
3557	/* Cpuid 0x80000009: Reserved
3558	* We zero this since we don't know what it may have been used for.
3559	*/
3560	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3561
3562	/* Cpuid 0x8000000a: SVM Information
3563	* AMD: EAX - SVM revision.
3564	* EBX - Number of ASIDs.
3565	* ECX - Reserved.
3566	* EDX - SVM Feature identification.
3567	*/
3568	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3569	if (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
3570	{
3571	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3572	pSvmFeatureLeaf->uEax = 0x1;
3573	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3574	pSvmFeatureLeaf->uEcx = 0;
3575	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3576	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3577	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3578	}
3579	else
3580	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3581
3582	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3583	* We clear these as we don't know what purpose they might have. */
3584	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3585	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3586
3587	/* Cpuid 0x80000019: TLB configuration
3588	* Seems to be harmless, pass them thru as is. */
3589
3590	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3591	* Strip anything we don't know what is or addresses feature we don't implement. */
3592	uSubLeaf = 0;
3593	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3594	{
3595	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3596	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3597	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3598	;
3599	pCurLeaf->uEbx = 0; /* reserved */
3600	pCurLeaf->uEcx = 0; /* reserved */
3601	pCurLeaf->uEdx = 0; /* reserved */
3602	uSubLeaf++;
3603	}
3604
3605	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3606	* Clear this as we don't currently virtualize this feature. */
3607	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3608
3609	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3610	* Clear this as we don't currently virtualize this feature. */
3611	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3612
3613	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3614	* We need to sanitize the cores per cache (EAX[25:14]).
3615	*
3616	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3617	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3618	* slightly different meaning.
3619	*/
3620	uSubLeaf = 0;
3621	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3622	{
3623	#ifdef VBOX_WITH_MULTI_CORE
3624	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3625	if (cCores > pVM->cCpus)
3626	cCores = pVM->cCpus;
3627	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3628	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3629	#else
3630	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3631	#endif
3632	uSubLeaf++;
3633	}
3634
3635	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3636	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3637	* setup, we have one compute unit with all the cores in it. Single node.
3638	*/
3639	uSubLeaf = 0;
3640	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3641	{
3642	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3643	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3644	{
3645	#ifdef VBOX_WITH_MULTI_CORE
3646	pCurLeaf->uEbx = pVM->cCpus < 0x100
3647	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3648	#else
3649	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3650	#endif
3651	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3652	}
3653	else
3654	{
3655	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3656	pCurLeaf->uEbx = 0; /* Reserved. */
3657	pCurLeaf->uEcx = 0; /* Reserved. */
3658	}
3659	pCurLeaf->uEdx = 0; /* Reserved. */
3660	uSubLeaf++;
3661	}
3662
3663	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3664	* We don't know these and what they mean, so remove them. */
3665	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3666	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3667
3668	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3669	* Just pass it thru for now. */
3670
3671	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3672	* Just pass it thru for now. */
3673
3674	/* Cpuid 0xc0000000: Centaur stuff.
3675	* Harmless, pass it thru. */
3676
3677	/* Cpuid 0xc0000001: Centaur features.
3678	* VIA: EAX - Family, model, stepping.
3679	* EDX - Centaur extended feature flags. Nothing interesting, except may
3680	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3681	* EBX, ECX - reserved.
3682	* We keep EAX but strips the rest.
3683	*/
3684	uSubLeaf = 0;
3685	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3686	{
3687	pCurLeaf->uEbx = 0;
3688	pCurLeaf->uEcx = 0;
3689	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3690	uSubLeaf++;
3691	}
3692
3693	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3694	* We only have fixed stale values, but should be harmless. */
3695
3696	/* Cpuid 0xc0000003: Reserved.
3697	* We zero this since we don't know what it may have been used for.
3698	*/
3699	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3700
3701	/* Cpuid 0xc0000004: Centaur Performance Info.
3702	* We only have fixed stale values, but should be harmless. */
3703
3704
3705	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3706	* We don't know these and what they mean, so remove them. */
3707	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3708	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3709
3710	return VINF_SUCCESS;
3711	#undef PORTABLE_DISABLE_FEATURE_BIT
3712	#undef PORTABLE_CLEAR_BITS_WHEN
3713	}
3714
3715
3716	/**
3717	* Reads a value in /CPUM/IsaExts/ node.
3718	*
3719	* @returns VBox status code (error message raised).
3720	* @param pVM The cross context VM structure. (For errors.)
3721	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3722	* @param pszValueName The value / extension name.
3723	* @param penmValue Where to return the choice.
3724	* @param enmDefault The default choice.
3725	*/
3726	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3727	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3728	{
3729	/*
3730	* Try integer encoding first.
3731	*/
3732	uint64_t uValue;
3733	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3734	if (RT_SUCCESS(rc))
3735	switch (uValue)
3736	{
3737	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3738	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3739	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3740	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3741	default:
3742	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3743	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3744	pszValueName, uValue);
3745	}
3746	/*
3747	* If missing, use default.
3748	*/
3749	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3750	*penmValue = enmDefault;
3751	else
3752	{
3753	if (rc == VERR_CFGM_NOT_INTEGER)
3754	{
3755	/*
3756	* Not an integer, try read it as a string.
3757	*/
3758	char szValue[32];
3759	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3760	if (RT_SUCCESS(rc))
3761	{
3762	RTStrToLower(szValue);
3763	size_t cchValue = strlen(szValue);
3764	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3765	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3766	*penmValue = CPUMISAEXTCFG_DISABLED;
3767	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3768	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3769	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3770	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3771	else if (EQ("portable"))
3772	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3773	else if (EQ("default") \|\| EQ("def"))
3774	*penmValue = enmDefault;
3775	else
3776	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3777	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3778	pszValueName, uValue);
3779	#undef EQ
3780	}
3781	}
3782	if (RT_FAILURE(rc))
3783	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3784	}
3785	return VINF_SUCCESS;
3786	}
3787
3788
3789	/**
3790	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3791	*
3792	* @returns VBox status code (error message raised).
3793	* @param pVM The cross context VM structure. (For errors.)
3794	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3795	* @param pszValueName The value / extension name.
3796	* @param penmValue Where to return the choice.
3797	* @param enmDefault The default choice.
3798	* @param fAllowed Allowed choice. Applied both to the result and to
3799	* the default value.
3800	*/
3801	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3802	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3803	{
3804	int rc;
3805	if (fAllowed)
3806	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3807	else
3808	{
3809	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3810	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3811	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3812	*penmValue = CPUMISAEXTCFG_DISABLED;
3813	}
3814	return rc;
3815	}
3816
3817
3818	/**
3819	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3820	*
3821	* @returns VBox status code (error message raised).
3822	* @param pVM The cross context VM structure. (For errors.)
3823	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3824	* @param pCpumCfg The /CPUM node (can be NULL).
3825	* @param pszValueName The value / extension name.
3826	* @param penmValue Where to return the choice.
3827	* @param enmDefault The default choice.
3828	*/
3829	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3830	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3831	{
3832	if (CFGMR3Exists(pCpumCfg, pszValueName))
3833	{
3834	if (!CFGMR3Exists(pIsaExts, pszValueName))
3835	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3836	else
3837	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3838	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3839	pszValueName, pszValueName);
3840
3841	bool fLegacy;
3842	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3843	if (RT_SUCCESS(rc))
3844	{
3845	*penmValue = fLegacy;
3846	return VINF_SUCCESS;
3847	}
3848	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3849	}
3850
3851	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3852	}
3853
3854
3855	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3856	{
3857	int rc;
3858
3859	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3860	* When non-zero CPUID features that could cause portability issues will be
3861	* stripped. The higher the value the more features gets stripped. Higher
3862	* values should only be used when older CPUs are involved since it may
3863	* harm performance and maybe also cause problems with specific guests. */
3864	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
3865	AssertLogRelRCReturn(rc, rc);
3866
3867	/** @cfgm{/CPUM/GuestCpuName, string}
3868	* The name of the CPU we're to emulate. The default is the host CPU.
3869	* Note! CPUs other than "host" one is currently unsupported. */
3870	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3871	AssertLogRelRCReturn(rc, rc);
3872
3873	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3874	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3875	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3876	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3877	*/
3878	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3879	AssertLogRelRCReturn(rc, rc);
3880
3881	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
3882	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
3883	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
3884	* 64-bit linux guests which assume the presence of AMD performance counters
3885	* that we do not virtualize.
3886	*/
3887	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
3888	AssertLogRelRCReturn(rc, rc);
3889
3890	/** @cfgm{/CPUM/ForceVme, boolean, false}
3891	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
3892	* By default the flag is passed thru as is from the host CPU, except
3893	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
3894	* guests and DOS boxes in general.
3895	*/
3896	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
3897	AssertLogRelRCReturn(rc, rc);
3898
3899	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3900	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
3901	* probably going to be a temporary hack, so don't depend on this.
3902	* The 1st byte of the value is the stepping, the 2nd byte value is the model
3903	* number and the 3rd byte value is the family, and the 4th value must be zero.
3904	*/
3905	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3906	AssertLogRelRCReturn(rc, rc);
3907
3908	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3909	* The last standard leaf to keep. The actual last value that is stored in EAX
3910	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3911	* removed. (This works independently of and differently from NT4LeafLimit.)
3912	* The default is usually set to what we're able to reasonably sanitize.
3913	*/
3914	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3915	AssertLogRelRCReturn(rc, rc);
3916
3917	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3918	* The last extended leaf to keep. The actual last value that is stored in EAX
3919	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3920	* leaf are removed. The default is set to what we're able to sanitize.
3921	*/
3922	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3923	AssertLogRelRCReturn(rc, rc);
3924
3925	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3926	* The last extended leaf to keep. The actual last value that is stored in EAX
3927	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3928	* leaf are removed. The default is set to what we're able to sanitize.
3929	*/
3930	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3931	AssertLogRelRCReturn(rc, rc);
3932
3933	#ifdef VBOX_WITH_NESTED_HWVIRT
3934	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
3935	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
3936	* The default is false, and when enabled requires nested paging and AMD-V or
3937	* unrestricted guest mode.
3938	*/
3939	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
3940	AssertLogRelRCReturn(rc, rc);
3941	if ( pConfig->fNestedHWVirt
3942	&& !fNestedPagingAndFullGuestExec)
3943	{
3944	LogRel(("CPUM: Warning! Can't turn on nested VT-x/AMD-V without nested-paging and unrestricted guest execution!\n"));
3945	pConfig->fNestedHWVirt = false;
3946	}
3947	#endif
3948
3949	/*
3950	* Instruction Set Architecture (ISA) Extensions.
3951	*/
3952	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3953	if (pIsaExts)
3954	{
3955	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3956	"CMPXCHG16B"
3957	"\|MONITOR"
3958	"\|MWaitExtensions"
3959	"\|SSE4.1"
3960	"\|SSE4.2"
3961	"\|XSAVE"
3962	"\|AVX"
3963	"\|AVX2"
3964	"\|AESNI"
3965	"\|PCLMUL"
3966	"\|POPCNT"
3967	"\|MOVBE"
3968	"\|RDRAND"
3969	"\|RDSEED"
3970	"\|CLFLUSHOPT"
3971	"\|FSGSBASE"
3972	"\|PCID"
3973	"\|INVPCID"
3974	"\|ABM"
3975	"\|SSE4A"
3976	"\|MISALNSSE"
3977	"\|3DNOWPRF"
3978	"\|AXMMX"
3979	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
3980	if (RT_FAILURE(rc))
3981	return rc;
3982	}
3983
3984	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
3985	* Expose CMPXCHG16B to the guest if supported by the host. For the time
3986	* being the default is to only do this for VMs with nested paging and AMD-V or
3987	* unrestricted guest mode.
3988	*/
3989	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
3990	AssertLogRelRCReturn(rc, rc);
3991
3992	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
3993	* Expose MONITOR/MWAIT instructions to the guest.
3994	*/
3995	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
3996	AssertLogRelRCReturn(rc, rc);
3997
3998	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
3999	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4000	* break on interrupt feature (bit 1).
4001	*/
4002	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4003	AssertLogRelRCReturn(rc, rc);
4004
4005	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4006	* Expose SSE4.1 to the guest if available.
4007	*/
4008	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4009	AssertLogRelRCReturn(rc, rc);
4010
4011	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4012	* Expose SSE4.2 to the guest if available.
4013	*/
4014	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4015	AssertLogRelRCReturn(rc, rc);
4016
4017	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4018	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4019	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
4020	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
4021	&& !HMIsLongModeAllowed(pVM)
4022	#endif
4023	;
4024	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4025
4026	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4027	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4028	* default is to only expose this to VMs with nested paging and AMD-V or
4029	* unrestricted guest execution mode. Not possible to force this one without
4030	* host support at the moment.
4031	*/
4032	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4033	fMayHaveXSave /fAllowed/);
4034	AssertLogRelRCReturn(rc, rc);
4035
4036	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4037	* Expose the AVX instruction set extensions to the guest if available and
4038	* XSAVE is exposed too. For the time being the default is to only expose this
4039	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4040	*/
4041	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4042	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4043	AssertLogRelRCReturn(rc, rc);
4044
4045	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4046	* Expose the AVX2 instruction set extensions to the guest if available and
4047	* XSAVE is exposed too. For the time being the default is to only expose this
4048	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4049	*/
4050	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4051	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4052	AssertLogRelRCReturn(rc, rc);
4053
4054	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4055	* Whether to expose the AES instructions to the guest. For the time being the
4056	* default is to only do this for VMs with nested paging and AMD-V or
4057	* unrestricted guest mode.
4058	*/
4059	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4060	AssertLogRelRCReturn(rc, rc);
4061
4062	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4063	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4064	* being the default is to only do this for VMs with nested paging and AMD-V or
4065	* unrestricted guest mode.
4066	*/
4067	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4068	AssertLogRelRCReturn(rc, rc);
4069
4070	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4071	* Whether to expose the POPCNT instructions to the guest. For the time
4072	* being the default is to only do this for VMs with nested paging and AMD-V or
4073	* unrestricted guest mode.
4074	*/
4075	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4076	AssertLogRelRCReturn(rc, rc);
4077
4078	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4079	* Whether to expose the MOVBE instructions to the guest. For the time
4080	* being the default is to only do this for VMs with nested paging and AMD-V or
4081	* unrestricted guest mode.
4082	*/
4083	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4084	AssertLogRelRCReturn(rc, rc);
4085
4086	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4087	* Whether to expose the RDRAND instructions to the guest. For the time being
4088	* the default is to only do this for VMs with nested paging and AMD-V or
4089	* unrestricted guest mode.
4090	*/
4091	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4092	AssertLogRelRCReturn(rc, rc);
4093
4094	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4095	* Whether to expose the RDSEED instructions to the guest. For the time being
4096	* the default is to only do this for VMs with nested paging and AMD-V or
4097	* unrestricted guest mode.
4098	*/
4099	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4100	AssertLogRelRCReturn(rc, rc);
4101
4102	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4103	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4104	* being the default is to only do this for VMs with nested paging and AMD-V or
4105	* unrestricted guest mode.
4106	*/
4107	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4108	AssertLogRelRCReturn(rc, rc);
4109
4110	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4111	* Whether to expose the read/write FSGSBASE instructions to the guest.
4112	*/
4113	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4114	AssertLogRelRCReturn(rc, rc);
4115
4116	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4117	* Whether to expose the PCID feature to the guest.
4118	*/
4119	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4120	AssertLogRelRCReturn(rc, rc);
4121
4122	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4123	* Whether to expose the INVPCID instruction to the guest.
4124	*/
4125	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4126	AssertLogRelRCReturn(rc, rc);
4127
4128
4129	/* AMD: */
4130
4131	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4132	* Whether to expose the AMD ABM instructions to the guest. For the time
4133	* being the default is to only do this for VMs with nested paging and AMD-V or
4134	* unrestricted guest mode.
4135	*/
4136	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4137	AssertLogRelRCReturn(rc, rc);
4138
4139	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4140	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4141	* being the default is to only do this for VMs with nested paging and AMD-V or
4142	* unrestricted guest mode.
4143	*/
4144	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4145	AssertLogRelRCReturn(rc, rc);
4146
4147	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4148	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4149	* the time being the default is to only do this for VMs with nested paging and
4150	* AMD-V or unrestricted guest mode.
4151	*/
4152	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4153	AssertLogRelRCReturn(rc, rc);
4154
4155	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4156	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4157	* For the time being the default is to only do this for VMs with nested paging
4158	* and AMD-V or unrestricted guest mode.
4159	*/
4160	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4161	AssertLogRelRCReturn(rc, rc);
4162
4163	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4164	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4165	* the default is to only do this for VMs with nested paging and AMD-V or
4166	* unrestricted guest mode.
4167	*/
4168	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4169	AssertLogRelRCReturn(rc, rc);
4170
4171	return VINF_SUCCESS;
4172	}
4173
4174
4175	/**
4176	* Initializes the emulated CPU's CPUID & MSR information.
4177	*
4178	* @returns VBox status code.
4179	* @param pVM The cross context VM structure.
4180	*/
4181	int cpumR3InitCpuIdAndMsrs(PVM pVM)
4182	{
4183	PCPUM pCpum = &pVM->cpum.s;
4184	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4185
4186	/*
4187	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4188	* on construction and manage everything from here on.
4189	*/
4190	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
4191	pVM->aCpus[iCpu].cpum.s.fCpuIdApicFeatureVisible = true;
4192
4193	/*
4194	* Read the configuration.
4195	*/
4196	CPUMCPUIDCONFIG Config;
4197	RT_ZERO(Config);
4198
4199	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4200	AssertRCReturn(rc, rc);
4201
4202	/*
4203	* Get the guest CPU data from the database and/or the host.
4204	*
4205	* The CPUID and MSRs are currently living on the regular heap to avoid
4206	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4207	* API for the hyper heap). This means special cleanup considerations.
4208	*/
4209	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4210	if (RT_FAILURE(rc))
4211	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4212	? VMSetError(pVM, rc, RT_SRC_POS,
4213	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4214	: rc;
4215
4216	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4217	{
4218	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4219	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4220	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4221	}
4222	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4223
4224	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4225	* Overrides the guest MSRs.
4226	*/
4227	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4228
4229	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4230	* Overrides the CPUID leaf values (from the host CPU usually) used for
4231	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4232	* values when moving a VM to a different machine. Another use is restricting
4233	* (or extending) the feature set exposed to the guest. */
4234	if (RT_SUCCESS(rc))
4235	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4236
4237	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4238	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4239	"Found unsupported configuration node '/CPUM/CPUID/'. "
4240	"Please use IMachine::setCPUIDLeaf() instead.");
4241
4242	/*
4243	* Pre-explode the CPUID info.
4244	*/
4245	if (RT_SUCCESS(rc))
4246	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
4247
4248	/*
4249	* Sanitize the cpuid information passed on to the guest.
4250	*/
4251	if (RT_SUCCESS(rc))
4252	{
4253	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4254	if (RT_SUCCESS(rc))
4255	{
4256	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4257	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4258	}
4259	}
4260
4261	/*
4262	* MSR fudging.
4263	*/
4264	if (RT_SUCCESS(rc))
4265	{
4266	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4267	* Fudges some common MSRs if not present in the selected CPU database entry.
4268	* This is for trying to keep VMs running when moved between different hosts
4269	* and different CPU vendors. */
4270	bool fEnable;
4271	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4272	if (RT_SUCCESS(rc) && fEnable)
4273	{
4274	rc = cpumR3MsrApplyFudge(pVM);
4275	AssertLogRelRC(rc);
4276	}
4277	}
4278	if (RT_SUCCESS(rc))
4279	{
4280	/*
4281	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4282	* guest CPU features again.
4283	*/
4284	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4285	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4286	pCpum->GuestInfo.cCpuIdLeaves);
4287	RTMemFree(pvFree);
4288
4289	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4290	int rc2 = MMHyperDupMem(pVM, pvFree,
4291	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4292	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4293	RTMemFree(pvFree);
4294	AssertLogRelRCReturn(rc1, rc1);
4295	AssertLogRelRCReturn(rc2, rc2);
4296
4297	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4298	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4299
4300
4301	/*
4302	* Some more configuration that we're applying at the end of everything
4303	* via the CPUMSetGuestCpuIdFeature API.
4304	*/
4305
4306	/* Check if PAE was explicitely enabled by the user. */
4307	bool fEnable;
4308	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4309	AssertRCReturn(rc, rc);
4310	if (fEnable)
4311	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4312
4313	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4314	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4315	AssertRCReturn(rc, rc);
4316	if (fEnable)
4317	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4318
4319	/* Check if speculation control is enabled. */
4320	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4321	AssertRCReturn(rc, rc);
4322	if (fEnable)
4323	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4324
4325	return VINF_SUCCESS;
4326	}
4327
4328	/*
4329	* Failed before switching to hyper heap.
4330	*/
4331	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4332	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4333	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4334	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4335	return rc;
4336	}
4337
4338
4339	/**
4340	* Sets a CPUID feature bit during VM initialization.
4341	*
4342	* Since the CPUID feature bits are generally related to CPU features, other
4343	* CPUM configuration like MSRs can also be modified by calls to this API.
4344	*
4345	* @param pVM The cross context VM structure.
4346	* @param enmFeature The feature to set.
4347	*/
4348	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4349	{
4350	PCPUMCPUIDLEAF pLeaf;
4351	PCPUMMSRRANGE pMsrRange;
4352
4353	switch (enmFeature)
4354	{
4355	/*
4356	* Set the APIC bit in both feature masks.
4357	*/
4358	case CPUMCPUIDFEATURE_APIC:
4359	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4360	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4361	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4362
4363	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4364	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4365	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4366
4367	pVM->cpum.s.GuestFeatures.fApic = 1;
4368
4369	/* Make sure we've got the APICBASE MSR present. */
4370	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4371	if (!pMsrRange)
4372	{
4373	static CPUMMSRRANGE const s_ApicBase =
4374	{
4375	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4376	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4377	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4378	/.szName = / "IA32_APIC_BASE"
4379	};
4380	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4381	AssertLogRelRC(rc);
4382	}
4383
4384	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4385	break;
4386
4387	/*
4388	* Set the x2APIC bit in the standard feature mask.
4389	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4390	*/
4391	case CPUMCPUIDFEATURE_X2APIC:
4392	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4393	if (pLeaf)
4394	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4395	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4396
4397	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4398	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4399	if (pMsrRange)
4400	{
4401	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4402	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4403	}
4404
4405	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4406	break;
4407
4408	/*
4409	* Set the sysenter/sysexit bit in the standard feature mask.
4410	* Assumes the caller knows what it's doing! (host must support these)
4411	*/
4412	case CPUMCPUIDFEATURE_SEP:
4413	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4414	{
4415	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4416	return;
4417	}
4418
4419	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4420	if (pLeaf)
4421	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4422	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4423	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4424	break;
4425
4426	/*
4427	* Set the syscall/sysret bit in the extended feature mask.
4428	* Assumes the caller knows what it's doing! (host must support these)
4429	*/
4430	case CPUMCPUIDFEATURE_SYSCALL:
4431	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4432	if ( !pLeaf
4433	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4434	{
4435	#if HC_ARCH_BITS == 32
4436	/* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit
4437	mode by Intel, even when the cpu is capable of doing so in
4438	64-bit mode. Long mode requires syscall support. */
4439	if (!pVM->cpum.s.HostFeatures.fLongMode)
4440	#endif
4441	{
4442	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4443	return;
4444	}
4445	}
4446
4447	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4448	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4449	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4450	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4451	break;
4452
4453	/*
4454	* Set the PAE bit in both feature masks.
4455	* Assumes the caller knows what it's doing! (host must support these)
4456	*/
4457	case CPUMCPUIDFEATURE_PAE:
4458	if (!pVM->cpum.s.HostFeatures.fPae)
4459	{
4460	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4461	return;
4462	}
4463
4464	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4465	if (pLeaf)
4466	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4467
4468	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4469	if ( pLeaf
4470	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4471	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4472
4473	pVM->cpum.s.GuestFeatures.fPae = 1;
4474	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4475	break;
4476
4477	/*
4478	* Set the LONG MODE bit in the extended feature mask.
4479	* Assumes the caller knows what it's doing! (host must support these)
4480	*/
4481	case CPUMCPUIDFEATURE_LONG_MODE:
4482	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4483	if ( !pLeaf
4484	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4485	{
4486	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4487	return;
4488	}
4489
4490	/* Valid for both Intel and AMD. */
4491	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4492	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4493	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4494	break;
4495
4496	/*
4497	* Set the NX/XD bit in the extended feature mask.
4498	* Assumes the caller knows what it's doing! (host must support these)
4499	*/
4500	case CPUMCPUIDFEATURE_NX:
4501	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4502	if ( !pLeaf
4503	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4504	{
4505	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4506	return;
4507	}
4508
4509	/* Valid for both Intel and AMD. */
4510	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4511	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4512	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4513	break;
4514
4515
4516	/*
4517	* Set the LAHF/SAHF support in 64-bit mode.
4518	* Assumes the caller knows what it's doing! (host must support this)
4519	*/
4520	case CPUMCPUIDFEATURE_LAHF:
4521	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4522	if ( !pLeaf
4523	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4524	{
4525	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4526	return;
4527	}
4528
4529	/* Valid for both Intel and AMD. */
4530	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4531	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4532	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4533	break;
4534
4535	/*
4536	* Set the page attribute table bit. This is alternative page level
4537	* cache control that doesn't much matter when everything is
4538	* virtualized, though it may when passing thru device memory.
4539	*/
4540	case CPUMCPUIDFEATURE_PAT:
4541	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4542	if (pLeaf)
4543	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4544
4545	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4546	if ( pLeaf
4547	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4548	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4549
4550	pVM->cpum.s.GuestFeatures.fPat = 1;
4551	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4552	break;
4553
4554	/*
4555	* Set the RDTSCP support bit.
4556	* Assumes the caller knows what it's doing! (host must support this)
4557	*/
4558	case CPUMCPUIDFEATURE_RDTSCP:
4559	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4560	if ( !pLeaf
4561	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4562	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4563	{
4564	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4565	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4566	return;
4567	}
4568
4569	/* Valid for both Intel and AMD. */
4570	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4571	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4572	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4573	break;
4574
4575	/*
4576	* Set the Hypervisor Present bit in the standard feature mask.
4577	*/
4578	case CPUMCPUIDFEATURE_HVP:
4579	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4580	if (pLeaf)
4581	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4582	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4583	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4584	break;
4585
4586	/*
4587	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4588	* This currently includes the Present bit and MWAITBREAK bit as well.
4589	*/
4590	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4591	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4592	if ( !pLeaf
4593	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4594	{
4595	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4596	return;
4597	}
4598
4599	/* Valid for both Intel and AMD. */
4600	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4601	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4602	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4603	break;
4604
4605	/*
4606	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
4607	* on Intel CPUs, and different on AMDs.
4608	*/
4609	case CPUMCPUIDFEATURE_SPEC_CTRL:
4610	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4611	{
4612	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4613	if ( !pLeaf
4614	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
4615	{
4616	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4617	return;
4618	}
4619
4620	/* The feature can be enabled. Let's see what we can actually do. */
4621	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4622
4623	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4624	if (pVM->cpum.s.HostFeatures.fIbrs)
4625	{
4626	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4627	pVM->cpum.s.GuestFeatures.fIbrs = 1;
4628	if (pVM->cpum.s.HostFeatures.fStibp)
4629	{
4630	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4631	pVM->cpum.s.GuestFeatures.fStibp = 1;
4632	}
4633
4634	/* Make sure we have the speculation control MSR... */
4635	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4636	if (!pMsrRange)
4637	{
4638	static CPUMMSRRANGE const s_SpecCtrl =
4639	{
4640	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
4641	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
4642	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4643	/.szName = / "IA32_SPEC_CTRL"
4644	};
4645	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4646	AssertLogRelRC(rc);
4647	}
4648
4649	/* ... and the predictor command MSR. */
4650	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
4651	if (!pMsrRange)
4652	{
4653	static CPUMMSRRANGE const s_SpecCtrl =
4654	{
4655	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
4656	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
4657	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4658	/.szName = / "IA32_PRED_CMD"
4659	};
4660	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4661	AssertLogRelRC(rc);
4662	}
4663
4664	}
4665
4666	if (pVM->cpum.s.HostFeatures.fArchCap) {
4667	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
4668
4669	/* Install the architectural capabilities MSR. */
4670	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
4671	if (!pMsrRange)
4672	{
4673	static CPUMMSRRANGE const s_ArchCaps =
4674	{
4675	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
4676	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
4677	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
4678	/.szName = / "IA32_ARCH_CAPABILITIES"
4679	};
4680	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
4681	AssertLogRelRC(rc);
4682	}
4683	}
4684
4685	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
4686	}
4687	else if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4688	{
4689	/* The precise details of AMD's implementation are not yet clear. */
4690	}
4691	break;
4692
4693	default:
4694	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4695	break;
4696	}
4697
4698	/** @todo can probably kill this as this API is now init time only... */
4699	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4700	{
4701	PVMCPU pVCpu = &pVM->aCpus[i];
4702	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4703	}
4704	}
4705
4706
4707	/**
4708	* Queries a CPUID feature bit.
4709	*
4710	* @returns boolean for feature presence
4711	* @param pVM The cross context VM structure.
4712	* @param enmFeature The feature to query.
4713	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4714	*/
4715	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4716	{
4717	switch (enmFeature)
4718	{
4719	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4720	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4721	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4722	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4723	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4724	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4725	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4726	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4727	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4728	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4729	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4730	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4731	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
4732
4733	case CPUMCPUIDFEATURE_INVALID:
4734	case CPUMCPUIDFEATURE_32BIT_HACK:
4735	break;
4736	}
4737	AssertFailed();
4738	return false;
4739	}
4740
4741
4742	/**
4743	* Clears a CPUID feature bit.
4744	*
4745	* @param pVM The cross context VM structure.
4746	* @param enmFeature The feature to clear.
4747	*
4748	* @deprecated Probably better to default the feature to disabled and only allow
4749	* setting (enabling) it during construction.
4750	*/
4751	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4752	{
4753	PCPUMCPUIDLEAF pLeaf;
4754	switch (enmFeature)
4755	{
4756	case CPUMCPUIDFEATURE_APIC:
4757	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
4758	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4759	if (pLeaf)
4760	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
4761
4762	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4763	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4764	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4765
4766	pVM->cpum.s.GuestFeatures.fApic = 0;
4767	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4768	break;
4769
4770	case CPUMCPUIDFEATURE_X2APIC:
4771	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4772	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4773	if (pLeaf)
4774	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
4775	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
4776	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
4777	break;
4778
4779	case CPUMCPUIDFEATURE_PAE:
4780	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4781	if (pLeaf)
4782	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
4783
4784	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4785	if ( pLeaf
4786	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4787	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
4788
4789	pVM->cpum.s.GuestFeatures.fPae = 0;
4790	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
4791	break;
4792
4793	case CPUMCPUIDFEATURE_PAT:
4794	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4795	if (pLeaf)
4796	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
4797
4798	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4799	if ( pLeaf
4800	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4801	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
4802
4803	pVM->cpum.s.GuestFeatures.fPat = 0;
4804	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
4805	break;
4806
4807	case CPUMCPUIDFEATURE_LONG_MODE:
4808	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4809	if (pLeaf)
4810	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4811	pVM->cpum.s.GuestFeatures.fLongMode = 0;
4812	break;
4813
4814	case CPUMCPUIDFEATURE_LAHF:
4815	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4816	if (pLeaf)
4817	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4818	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
4819	break;
4820
4821	case CPUMCPUIDFEATURE_RDTSCP:
4822	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4823	if (pLeaf)
4824	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4825	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
4826	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
4827	break;
4828
4829	case CPUMCPUIDFEATURE_HVP:
4830	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4831	if (pLeaf)
4832	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
4833	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
4834	break;
4835
4836	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4837	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4838	if (pLeaf)
4839	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
4840	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
4841	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
4842	break;
4843
4844	case CPUMCPUIDFEATURE_SPEC_CTRL:
4845	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4846	if (pLeaf)
4847	/pVM->cpum.s.aGuestCpuIdPatmStd[7].uEdx =/ pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP \| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
4848	pVM->cpum.s.GuestFeatures.fSpeculationControl = 0;
4849	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
4850	break;
4851
4852	default:
4853	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4854	break;
4855	}
4856
4857	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4858	{
4859	PVMCPU pVCpu = &pVM->aCpus[i];
4860	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4861	}
4862	}
4863
4864
4865
4866	/*
4867	*
4868	*
4869	* Saved state related code.
4870	* Saved state related code.
4871	* Saved state related code.
4872	*
4873	*
4874	*/
4875
4876	/**
4877	* Called both in pass 0 and the final pass.
4878	*
4879	* @param pVM The cross context VM structure.
4880	* @param pSSM The saved state handle.
4881	*/
4882	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4883	{
4884	/*
4885	* Save all the CPU ID leaves.
4886	*/
4887	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4888	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4889	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4890	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4891
4892	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4893
4894	/*
4895	* Save a good portion of the raw CPU IDs as well as they may come in
4896	* handy when validating features for raw mode.
4897	*/
4898	CPUMCPUID aRawStd[16];
4899	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4900	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4901	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4902	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4903
4904	CPUMCPUID aRawExt[32];
4905	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4906	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4907	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4908	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4909	}
4910
4911
4912	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4913	{
4914	uint32_t cCpuIds;
4915	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4916	if (RT_SUCCESS(rc))
4917	{
4918	if (cCpuIds < 64)
4919	{
4920	for (uint32_t i = 0; i < cCpuIds; i++)
4921	{
4922	CPUMCPUID CpuId;
4923	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4924	if (RT_FAILURE(rc))
4925	break;
4926
4927	CPUMCPUIDLEAF NewLeaf;
4928	NewLeaf.uLeaf = uBase + i;
4929	NewLeaf.uSubLeaf = 0;
4930	NewLeaf.fSubLeafMask = 0;
4931	NewLeaf.uEax = CpuId.uEax;
4932	NewLeaf.uEbx = CpuId.uEbx;
4933	NewLeaf.uEcx = CpuId.uEcx;
4934	NewLeaf.uEdx = CpuId.uEdx;
4935	NewLeaf.fFlags = 0;
4936	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4937	}
4938	}
4939	else
4940	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4941	}
4942	if (RT_FAILURE(rc))
4943	{
4944	RTMemFree(*ppaLeaves);
4945	*ppaLeaves = NULL;
4946	*pcLeaves = 0;
4947	}
4948	return rc;
4949	}
4950
4951
4952	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4953	{
4954	*ppaLeaves = NULL;
4955	*pcLeaves = 0;
4956
4957	int rc;
4958	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4959	{
4960	/*
4961	* The new format. Starts by declaring the leave size and count.
4962	*/
4963	uint32_t cbLeaf;
4964	SSMR3GetU32(pSSM, &cbLeaf);
4965	uint32_t cLeaves;
4966	rc = SSMR3GetU32(pSSM, &cLeaves);
4967	if (RT_SUCCESS(rc))
4968	{
4969	if (cbLeaf == sizeof(**ppaLeaves))
4970	{
4971	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4972	{
4973	/*
4974	* Load the leaves one by one.
4975	*
4976	* The uPrev stuff is a kludge for working around a week worth of bad saved
4977	* states during the CPUID revamp in March 2015. We saved too many leaves
4978	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4979	* garbage entires at the end of the array when restoring. We also had
4980	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
4981	* this kludge doesn't deal correctly with that, but who cares...
4982	*/
4983	uint32_t uPrev = 0;
4984	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4985	{
4986	CPUMCPUIDLEAF Leaf;
4987	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
4988	if (RT_SUCCESS(rc))
4989	{
4990	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
4991	\|\| Leaf.uLeaf >= uPrev)
4992	{
4993	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4994	uPrev = Leaf.uLeaf;
4995	}
4996	else
4997	uPrev = UINT32_MAX;
4998	}
4999	}
5000	}
5001	else
5002	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5003	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5004	}
5005	else
5006	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5007	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5008	}
5009	}
5010	else
5011	{
5012	/*
5013	* The old format with its three inflexible arrays.
5014	*/
5015	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5016	if (RT_SUCCESS(rc))
5017	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5018	if (RT_SUCCESS(rc))
5019	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5020	if (RT_SUCCESS(rc))
5021	{
5022	/*
5023	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5024	*/
5025	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5026	if ( pLeaf
5027	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5028	{
5029	CPUMCPUIDLEAF Leaf;
5030	Leaf.uLeaf = 4;
5031	Leaf.fSubLeafMask = UINT32_MAX;
5032	Leaf.uSubLeaf = 0;
5033	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5034	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5035	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5036	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5037	\| UINT32_C(63); /* system coherency line size - 1 */
5038	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5039	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5040	\| (UINT32_C(1) << 5) /* cache level */
5041	\| UINT32_C(1); /* cache type (data) */
5042	Leaf.fFlags = 0;
5043	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5044	if (RT_SUCCESS(rc))
5045	{
5046	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5047	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5048	}
5049	if (RT_SUCCESS(rc))
5050	{
5051	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5052	Leaf.uEcx = 4095; /* sets - 1 */
5053	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5054	Leaf.uEbx \|= UINT32_C(23) << 22;
5055	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5056	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5057	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5058	Leaf.uEax \|= UINT32_C(2) << 5;
5059	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5060	}
5061	}
5062	}
5063	}
5064	return rc;
5065	}
5066
5067
5068	/**
5069	* Loads the CPU ID leaves saved by pass 0, inner worker.
5070	*
5071	* @returns VBox status code.
5072	* @param pVM The cross context VM structure.
5073	* @param pSSM The saved state handle.
5074	* @param uVersion The format version.
5075	* @param paLeaves Guest CPUID leaves loaded from the state.
5076	* @param cLeaves The number of leaves in @a paLeaves.
5077	*/
5078	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
5079	{
5080	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5081
5082	/*
5083	* Continue loading the state into stack buffers.
5084	*/
5085	CPUMCPUID GuestDefCpuId;
5086	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5087	AssertRCReturn(rc, rc);
5088
5089	CPUMCPUID aRawStd[16];
5090	uint32_t cRawStd;
5091	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5092	if (cRawStd > RT_ELEMENTS(aRawStd))
5093	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5094	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5095	AssertRCReturn(rc, rc);
5096	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5097	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5098
5099	CPUMCPUID aRawExt[32];
5100	uint32_t cRawExt;
5101	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5102	if (cRawExt > RT_ELEMENTS(aRawExt))
5103	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5104	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5105	AssertRCReturn(rc, rc);
5106	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5107	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5108
5109	/*
5110	* Get the raw CPU IDs for the current host.
5111	*/
5112	CPUMCPUID aHostRawStd[16];
5113	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5114	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5115
5116	CPUMCPUID aHostRawExt[32];
5117	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5118	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5119	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5120
5121	/*
5122	* Get the host and guest overrides so we don't reject the state because
5123	* some feature was enabled thru these interfaces.
5124	* Note! We currently only need the feature leaves, so skip rest.
5125	*/
5126	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5127	CPUMCPUID aHostOverrideStd[2];
5128	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5129	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5130
5131	CPUMCPUID aHostOverrideExt[2];
5132	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5133	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5134
5135	/*
5136	* This can be skipped.
5137	*/
5138	bool fStrictCpuIdChecks;
5139	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5140
5141	/*
5142	* Define a bunch of macros for simplifying the santizing/checking code below.
5143	*/
5144	/* Generic expression + failure message. */
5145	#define CPUID_CHECK_RET(expr, fmt) \
5146	do { \
5147	if (!(expr)) \
5148	{ \
5149	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5150	if (fStrictCpuIdChecks) \
5151	{ \
5152	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5153	RTStrFree(pszMsg); \
5154	return rcCpuid; \
5155	} \
5156	LogRel(("CPUM: %s\n", pszMsg)); \
5157	RTStrFree(pszMsg); \
5158	} \
5159	} while (0)
5160	#define CPUID_CHECK_WRN(expr, fmt) \
5161	do { \
5162	if (!(expr)) \
5163	LogRel(fmt); \
5164	} while (0)
5165
5166	/* For comparing two values and bitch if they differs. */
5167	#define CPUID_CHECK2_RET(what, host, saved) \
5168	do { \
5169	if ((host) != (saved)) \
5170	{ \
5171	if (fStrictCpuIdChecks) \
5172	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5173	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5174	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5175	} \
5176	} while (0)
5177	#define CPUID_CHECK2_WRN(what, host, saved) \
5178	do { \
5179	if ((host) != (saved)) \
5180	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5181	} while (0)
5182
5183	/* For checking raw cpu features (raw mode). */
5184	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5185	do { \
5186	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5187	{ \
5188	if (fStrictCpuIdChecks) \
5189	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5190	N_(#bit " mismatch: host=%d saved=%d"), \
5191	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5192	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5193	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5194	} \
5195	} while (0)
5196	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5197	do { \
5198	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5199	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5200	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5201	} while (0)
5202	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5203
5204	/* For checking guest features. */
5205	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5206	do { \
5207	if ( (aGuestCpuId##set [1].reg & bit) \
5208	&& !(aHostRaw##set [1].reg & bit) \
5209	&& !(aHostOverride##set [1].reg & bit) \
5210	) \
5211	{ \
5212	if (fStrictCpuIdChecks) \
5213	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5214	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5215	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5216	} \
5217	} while (0)
5218	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5219	do { \
5220	if ( (aGuestCpuId##set [1].reg & bit) \
5221	&& !(aHostRaw##set [1].reg & bit) \
5222	&& !(aHostOverride##set [1].reg & bit) \
5223	) \
5224	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5225	} while (0)
5226	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5227	do { \
5228	if ( (aGuestCpuId##set [1].reg & bit) \
5229	&& !(aHostRaw##set [1].reg & bit) \
5230	&& !(aHostOverride##set [1].reg & bit) \
5231	) \
5232	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5233	} while (0)
5234	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5235
5236	/* For checking guest features if AMD guest CPU. */
5237	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5238	do { \
5239	if ( (aGuestCpuId##set [1].reg & bit) \
5240	&& fGuestAmd \
5241	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5242	&& !(aHostOverride##set [1].reg & bit) \
5243	) \
5244	{ \
5245	if (fStrictCpuIdChecks) \
5246	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5247	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5248	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5249	} \
5250	} while (0)
5251	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5252	do { \
5253	if ( (aGuestCpuId##set [1].reg & bit) \
5254	&& fGuestAmd \
5255	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5256	&& !(aHostOverride##set [1].reg & bit) \
5257	) \
5258	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5259	} while (0)
5260	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5261	do { \
5262	if ( (aGuestCpuId##set [1].reg & bit) \
5263	&& fGuestAmd \
5264	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5265	&& !(aHostOverride##set [1].reg & bit) \
5266	) \
5267	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5268	} while (0)
5269	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5270
5271	/* For checking AMD features which have a corresponding bit in the standard
5272	range. (Intel defines very few bits in the extended feature sets.) */
5273	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5274	do { \
5275	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5276	&& !(fHostAmd \
5277	? aHostRawExt[1].reg & (ExtBit) \
5278	: aHostRawStd[1].reg & (StdBit)) \
5279	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5280	) \
5281	{ \
5282	if (fStrictCpuIdChecks) \
5283	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5284	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5285	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5286	} \
5287	} while (0)
5288	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5289	do { \
5290	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5291	&& !(fHostAmd \
5292	? aHostRawExt[1].reg & (ExtBit) \
5293	: aHostRawStd[1].reg & (StdBit)) \
5294	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5295	) \
5296	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5297	} while (0)
5298	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5299	do { \
5300	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5301	&& !(fHostAmd \
5302	? aHostRawExt[1].reg & (ExtBit) \
5303	: aHostRawStd[1].reg & (StdBit)) \
5304	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5305	) \
5306	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5307	} while (0)
5308	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5309
5310	/*
5311	* For raw-mode we'll require that the CPUs are very similar since we don't
5312	* intercept CPUID instructions for user mode applications.
5313	*/
5314	if (VM_IS_RAW_MODE_ENABLED(pVM))
5315	{
5316	/* CPUID(0) */
5317	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
5318	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
5319	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
5320	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5321	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
5322	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
5323	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
5324	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
5325	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5326
5327	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
5328
5329	/* CPUID(1).eax */
5330	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
5331	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
5332	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
5333
5334	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
5335	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
5336	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
5337
5338	/* CPUID(1).ecx */
5339	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
5340	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
5341	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
5342	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5343	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
5344	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
5345	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
5346	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
5347	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
5348	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
5349	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
5350	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
5351	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
5352	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
5353	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
5354	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
5355	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5356	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5357	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
5358	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
5359	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
5360	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5361	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
5362	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
5363	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5364	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
5365	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
5366	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5367	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
5368	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5369	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5370	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
5371
5372	/* CPUID(1).edx */
5373	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5374	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5375	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
5376	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5377	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
5378	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
5379	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5380	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5381	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
5382	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5383	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5384	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5385	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5386	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5387	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5388	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
5389	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5390	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5391	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5392	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
5393	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5394	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
5395	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
5396	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
5397	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
5398	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
5399	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
5400	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
5401	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
5402	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
5403	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
5404	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
5405
5406	/* CPUID(2) - config, mostly about caches. ignore. */
5407	/* CPUID(3) - processor serial number. ignore. */
5408	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
5409	/* CPUID(5) - mwait/monitor config. ignore. */
5410	/* CPUID(6) - power management. ignore. */
5411	/* CPUID(7) - ???. ignore. */
5412	/* CPUID(8) - ???. ignore. */
5413	/* CPUID(9) - DCA. ignore for now. */
5414	/* CPUID(a) - PeMo info. ignore for now. */
5415	/* CPUID(b) - topology info - takes ECX as input. ignore. */
5416
5417	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
5418	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
5419	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
5420	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
5421	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
5422	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
5423	{
5424	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
5425	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
5426	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
5427	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
5428	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
5429	}
5430
5431	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
5432	Note! Intel have/is marking many of the fields here as reserved. We
5433	will verify them as if it's an AMD CPU. */
5434	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
5435	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
5436	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
5437	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
5438	{
5439	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
5440	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
5441	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
5442	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5443	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
5444	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
5445	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
5446
5447	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
5448	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
5449	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
5450	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
5451	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
5452	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5453
5454	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
5455	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
5456	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
5457	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
5458
5459	/* CPUID(0x80000001).ecx */
5460	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
5461	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
5462	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
5463	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
5464	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
5465	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
5466	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
5467	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
5468	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
5469	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
5470	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
5471	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
5472	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
5473	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
5474	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5475	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5476	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5477	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5478	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5479	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5480	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5481	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5482	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5483	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5484	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5485	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5486	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5487	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5488	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5489	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5490	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5491	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5492
5493	/* CPUID(0x80000001).edx */
5494	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
5495	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
5496	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
5497	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
5498	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
5499	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
5500	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
5501	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
5502	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
5503	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
5504	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5505	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
5506	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
5507	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
5508	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
5509	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
5510	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
5511	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
5512	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5513	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5514	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5515	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
5516	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5517	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
5518	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
5519	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5520	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5521	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5522	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
5523	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5524	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5525	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5526
5527	/** @todo verify the rest as well. */
5528	}
5529	}
5530
5531
5532
5533	/*
5534	* Verify that we can support the features already exposed to the guest on
5535	* this host.
5536	*
5537	* Most of the features we're emulating requires intercepting instruction
5538	* and doing it the slow way, so there is no need to warn when they aren't
5539	* present in the host CPU. Thus we use IGN instead of EMU on these.
5540	*
5541	* Trailing comments:
5542	* "EMU" - Possible to emulate, could be lots of work and very slow.
5543	* "EMU?" - Can this be emulated?
5544	*/
5545	CPUMCPUID aGuestCpuIdStd[2];
5546	RT_ZERO(aGuestCpuIdStd);
5547	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5548
5549	/* CPUID(1).ecx */
5550	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5551	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5552	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5553	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5554	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5555	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5556	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5557	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5558	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5559	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5560	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5561	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5562	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5563	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5564	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5565	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5566	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5567	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5568	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5569	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5570	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5571	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5572	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5573	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5574	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5575	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5576	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5577	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5578	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5579	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5580	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5581	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5582
5583	/* CPUID(1).edx */
5584	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5585	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5586	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5587	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5588	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5589	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5590	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5591	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5592	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5593	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5594	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5595	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5596	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5597	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5598	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5599	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5600	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5601	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5602	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5603	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5604	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5605	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5606	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5607	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5608	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5609	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5610	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5611	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5612	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5613	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5614	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5615	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5616
5617	/* CPUID(0x80000000). */
5618	CPUMCPUID aGuestCpuIdExt[2];
5619	RT_ZERO(aGuestCpuIdExt);
5620	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5621	{
5622	/** @todo deal with no 0x80000001 on the host. */
5623	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5624	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5625
5626	/* CPUID(0x80000001).ecx */
5627	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5628	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5629	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5630	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5631	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5632	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5633	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5634	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5635	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5636	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5637	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5638	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5639	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5640	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5641	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5642	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5643	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5644	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5645	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5646	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5647	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5648	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5649	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5650	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5651	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5652	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5653	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5654	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5655	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5656	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5657	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5658	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5659
5660	/* CPUID(0x80000001).edx */
5661	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5662	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5663	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5664	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5665	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5666	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5667	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5668	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5669	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5670	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5671	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5672	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5673	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5674	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5675	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5676	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5677	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5678	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5679	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5680	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5681	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5682	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5683	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5684	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5685	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5686	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5687	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5688	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5689	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5690	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5691	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5692	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5693	}
5694
5695	/** @todo check leaf 7 */
5696
5697	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5698	* ECX=0: EAX - Valid bits in XCR0[31:0].
5699	* EBX - Maximum state size as per current XCR0 value.
5700	* ECX - Maximum state size for all supported features.
5701	* EDX - Valid bits in XCR0[63:32].
5702	* ECX=1: EAX - Various X-features.
5703	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5704	* ECX - Valid bits in IA32_XSS[31:0].
5705	* EDX - Valid bits in IA32_XSS[63:32].
5706	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5707	* if the bit invalid all four registers are set to zero.
5708	* EAX - The state size for this feature.
5709	* EBX - The state byte offset of this feature.
5710	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5711	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5712	*/
5713	uint64_t fGuestXcr0Mask = 0;
5714	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5715	if ( pCurLeaf
5716	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5717	&& ( pCurLeaf->uEax
5718	\|\| pCurLeaf->uEbx
5719	\|\| pCurLeaf->uEcx
5720	\|\| pCurLeaf->uEdx) )
5721	{
5722	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5723	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5724	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5725	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5726	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5727	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5728	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5729	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5730
5731	/* We don't support any additional features yet. */
5732	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5733	if (pCurLeaf && pCurLeaf->uEax)
5734	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5735	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5736	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5737	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5738	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5739	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5740
5741
5742	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5743	{
5744	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5745	if (pCurLeaf)
5746	{
5747	/* If advertised, the state component offset and size must match the one used by host. */
5748	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5749	{
5750	CPUMCPUID RawHost;
5751	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5752	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5753	if ( RawHost.uEbx != pCurLeaf->uEbx
5754	\|\| RawHost.uEax != pCurLeaf->uEax)
5755	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5756	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5757	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5758	}
5759	}
5760	}
5761	}
5762	/* Clear leaf 0xd just in case we're loading an old state... */
5763	else if (pCurLeaf)
5764	{
5765	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5766	{
5767	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5768	if (pCurLeaf)
5769	{
5770	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5771	\|\| ( pCurLeaf->uEax == 0
5772	&& pCurLeaf->uEbx == 0
5773	&& pCurLeaf->uEcx == 0
5774	&& pCurLeaf->uEdx == 0),
5775	("uVersion=%#x; %#x %#x %#x %#x\n",
5776	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5777	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5778	}
5779	}
5780	}
5781
5782	/* Update the fXStateGuestMask value for the VM. */
5783	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5784	{
5785	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5786	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5787	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5788	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5789	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5790	}
5791
5792	#undef CPUID_CHECK_RET
5793	#undef CPUID_CHECK_WRN
5794	#undef CPUID_CHECK2_RET
5795	#undef CPUID_CHECK2_WRN
5796	#undef CPUID_RAW_FEATURE_RET
5797	#undef CPUID_RAW_FEATURE_WRN
5798	#undef CPUID_RAW_FEATURE_IGN
5799	#undef CPUID_GST_FEATURE_RET
5800	#undef CPUID_GST_FEATURE_WRN
5801	#undef CPUID_GST_FEATURE_EMU
5802	#undef CPUID_GST_FEATURE_IGN
5803	#undef CPUID_GST_FEATURE2_RET
5804	#undef CPUID_GST_FEATURE2_WRN
5805	#undef CPUID_GST_FEATURE2_EMU
5806	#undef CPUID_GST_FEATURE2_IGN
5807	#undef CPUID_GST_AMD_FEATURE_RET
5808	#undef CPUID_GST_AMD_FEATURE_WRN
5809	#undef CPUID_GST_AMD_FEATURE_EMU
5810	#undef CPUID_GST_AMD_FEATURE_IGN
5811
5812	/*
5813	* We're good, commit the CPU ID leaves.
5814	*/
5815	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5816	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5817	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5818	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
5819	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5820	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
5821	AssertLogRelRCReturn(rc, rc);
5822
5823	return VINF_SUCCESS;
5824	}
5825
5826
5827	/**
5828	* Loads the CPU ID leaves saved by pass 0.
5829	*
5830	* @returns VBox status code.
5831	* @param pVM The cross context VM structure.
5832	* @param pSSM The saved state handle.
5833	* @param uVersion The format version.
5834	*/
5835	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5836	{
5837	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5838
5839	/*
5840	* Load the CPUID leaves array first and call worker to do the rest, just so
5841	* we can free the memory when we need to without ending up in column 1000.
5842	*/
5843	PCPUMCPUIDLEAF paLeaves;
5844	uint32_t cLeaves;
5845	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5846	AssertRC(rc);
5847	if (RT_SUCCESS(rc))
5848	{
5849	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
5850	RTMemFree(paLeaves);
5851	}
5852	return rc;
5853	}
5854
5855
5856
5857	/**
5858	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5859	*
5860	* @returns VBox status code.
5861	* @param pVM The cross context VM structure.
5862	* @param pSSM The saved state handle.
5863	* @param uVersion The format version.
5864	*/
5865	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5866	{
5867	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5868
5869	/*
5870	* Restore the CPUID leaves.
5871	*
5872	* Note that we support restoring less than the current amount of standard
5873	* leaves because we've been allowed more is newer version of VBox.
5874	*/
5875	uint32_t cElements;
5876	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5877	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5878	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5879	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5880
5881	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5882	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5883	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5884	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5885
5886	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5887	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5888	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5889	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5890
5891	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5892
5893	/*
5894	* Check that the basic cpuid id information is unchanged.
5895	*/
5896	/** @todo we should check the 64 bits capabilities too! */
5897	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5898	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5899	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5900	uint32_t au32CpuIdSaved[8];
5901	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5902	if (RT_SUCCESS(rc))
5903	{
5904	/* Ignore CPU stepping. */
5905	au32CpuId[4] &= 0xfffffff0;
5906	au32CpuIdSaved[4] &= 0xfffffff0;
5907
5908	/* Ignore APIC ID (AMD specs). */
5909	au32CpuId[5] &= ~0xff000000;
5910	au32CpuIdSaved[5] &= ~0xff000000;
5911
5912	/* Ignore the number of Logical CPUs (AMD specs). */
5913	au32CpuId[5] &= ~0x00ff0000;
5914	au32CpuIdSaved[5] &= ~0x00ff0000;
5915
5916	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5917	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5918	\| X86_CPUID_FEATURE_ECX_VMX
5919	\| X86_CPUID_FEATURE_ECX_SMX
5920	\| X86_CPUID_FEATURE_ECX_EST
5921	\| X86_CPUID_FEATURE_ECX_TM2
5922	\| X86_CPUID_FEATURE_ECX_CNTXID
5923	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5924	\| X86_CPUID_FEATURE_ECX_PDCM
5925	\| X86_CPUID_FEATURE_ECX_DCA
5926	\| X86_CPUID_FEATURE_ECX_X2APIC
5927	);
5928	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5929	\| X86_CPUID_FEATURE_ECX_VMX
5930	\| X86_CPUID_FEATURE_ECX_SMX
5931	\| X86_CPUID_FEATURE_ECX_EST
5932	\| X86_CPUID_FEATURE_ECX_TM2
5933	\| X86_CPUID_FEATURE_ECX_CNTXID
5934	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5935	\| X86_CPUID_FEATURE_ECX_PDCM
5936	\| X86_CPUID_FEATURE_ECX_DCA
5937	\| X86_CPUID_FEATURE_ECX_X2APIC
5938	);
5939
5940	/* Make sure we don't forget to update the masks when enabling
5941	* features in the future.
5942	*/
5943	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5944	( X86_CPUID_FEATURE_ECX_DTES64
5945	\| X86_CPUID_FEATURE_ECX_VMX
5946	\| X86_CPUID_FEATURE_ECX_SMX
5947	\| X86_CPUID_FEATURE_ECX_EST
5948	\| X86_CPUID_FEATURE_ECX_TM2
5949	\| X86_CPUID_FEATURE_ECX_CNTXID
5950	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5951	\| X86_CPUID_FEATURE_ECX_PDCM
5952	\| X86_CPUID_FEATURE_ECX_DCA
5953	\| X86_CPUID_FEATURE_ECX_X2APIC
5954	)));
5955	/* do the compare */
5956	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5957	{
5958	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5959	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5960	"Saved=%.*Rhxs\n"
5961	"Real =%.*Rhxs\n",
5962	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5963	sizeof(au32CpuId), au32CpuId));
5964	else
5965	{
5966	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5967	"Saved=%.*Rhxs\n"
5968	"Real =%.*Rhxs\n",
5969	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5970	sizeof(au32CpuId), au32CpuId));
5971	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5972	}
5973	}
5974	}
5975
5976	return rc;
5977	}
5978
5979
5980
5981	/*
5982	*
5983	*
5984	* CPUID Info Handler.
5985	* CPUID Info Handler.
5986	* CPUID Info Handler.
5987	*
5988	*
5989	*/
5990
5991
5992
5993	/**
5994	* Get L1 cache / TLS associativity.
5995	*/
5996	static const char getCacheAss(unsigned u, char pszBuf)
5997	{
5998	if (u == 0)
5999	return "res0 ";
6000	if (u == 1)
6001	return "direct";
6002	if (u == 255)
6003	return "fully";
6004	if (u >= 256)
6005	return "???";
6006
6007	RTStrPrintf(pszBuf, 16, "%d way", u);
6008	return pszBuf;
6009	}
6010
6011
6012	/**
6013	* Get L2 cache associativity.
6014	*/
6015	const char *getL2CacheAss(unsigned u)
6016	{
6017	switch (u)
6018	{
6019	case 0: return "off ";
6020	case 1: return "direct";
6021	case 2: return "2 way ";
6022	case 3: return "res3 ";
6023	case 4: return "4 way ";
6024	case 5: return "res5 ";
6025	case 6: return "8 way ";
6026	case 7: return "res7 ";
6027	case 8: return "16 way";
6028	case 9: return "res9 ";
6029	case 10: return "res10 ";
6030	case 11: return "res11 ";
6031	case 12: return "res12 ";
6032	case 13: return "res13 ";
6033	case 14: return "res14 ";
6034	case 15: return "fully ";
6035	default: return "????";
6036	}
6037	}
6038
6039
6040	/** CPUID(1).EDX field descriptions. */
6041	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6042	{
6043	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6044	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6045	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6046	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6047	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6048	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6049	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6050	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6051	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6052	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6053	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6054	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6055	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6056	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6057	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6058	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6059	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6060	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6061	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6062	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6063	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6064	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6065	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6066	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6067	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6068	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6069	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6070	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6071	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6072	DBGFREGSUBFIELD_TERMINATOR()
6073	};
6074
6075	/** CPUID(1).ECX field descriptions. */
6076	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6077	{
6078	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6079	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6080	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6081	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6082	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6083	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6084	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6085	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6086	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6087	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6088	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6089	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6090	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6091	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6092	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6093	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6094	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6095	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6096	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6097	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6098	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6099	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6100	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6101	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6102	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6103	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6104	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6105	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6106	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6107	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6108	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6109	DBGFREGSUBFIELD_TERMINATOR()
6110	};
6111
6112	/** CPUID(7,0).EBX field descriptions. */
6113	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6114	{
6115	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6116	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6117	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6118	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6119	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6120	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6121	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6122	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6123	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6124	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6125	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6126	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6127	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6128	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6129	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6130	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6131	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6132	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6133	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6134	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6135	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6136	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6137	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6138	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6139	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6140	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6141	DBGFREGSUBFIELD_TERMINATOR()
6142	};
6143
6144	/** CPUID(7,0).ECX field descriptions. */
6145	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6146	{
6147	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6148	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6149	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6150	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6151	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6152	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6153	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6154	DBGFREGSUBFIELD_TERMINATOR()
6155	};
6156
6157	/** CPUID(7,0).EDX field descriptions. */
6158	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6159	{
6160	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6161	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6162	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6163	DBGFREGSUBFIELD_TERMINATOR()
6164	};
6165
6166
6167	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6168	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6169	{
6170	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6171	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6172	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6173	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6174	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6175	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6176	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6177	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6178	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6179	DBGFREGSUBFIELD_TERMINATOR()
6180	};
6181
6182	/** CPUID(13,1).EAX field descriptions. */
6183	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6184	{
6185	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6186	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6187	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6188	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6189	DBGFREGSUBFIELD_TERMINATOR()
6190	};
6191
6192
6193	/** CPUID(0x80000001,0).EDX field descriptions. */
6194	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6195	{
6196	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6197	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6198	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6199	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6200	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6201	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6202	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6203	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6204	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6205	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6206	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6207	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6208	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6209	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6210	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6211	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6212	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6213	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6214	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6215	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6216	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6217	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6218	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6219	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6220	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6221	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6222	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6223	DBGFREGSUBFIELD_TERMINATOR()
6224	};
6225
6226	/** CPUID(0x80000001,0).ECX field descriptions. */
6227	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6228	{
6229	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6230	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6231	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6232	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6233	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6234	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6235	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6236	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6237	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6238	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6239	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6240	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6241	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6242	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6243	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6244	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6245	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6246	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6247	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6248	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6249	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6250	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6251	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6252	DBGFREGSUBFIELD_TERMINATOR()
6253	};
6254
6255	/** CPUID(0x80000007,0).EDX field descriptions. */
6256	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6257	{
6258	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6259	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6260	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6261	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6262	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6263	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6264	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6265	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6266	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6267	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6268	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6269	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6270	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6271	DBGFREGSUBFIELD_TERMINATOR()
6272	};
6273
6274	/** CPUID(0x80000008,0).EBX field descriptions. */
6275	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6276	{
6277	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6278	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6279	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6280	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6281	DBGFREGSUBFIELD_TERMINATOR()
6282	};
6283
6284
6285	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6286	const char *pszLeadIn, uint32_t cchWidth)
6287	{
6288	if (pszLeadIn)
6289	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6290
6291	for (uint32_t iBit = 0; iBit < 32; iBit++)
6292	if (RT_BIT_32(iBit) & uVal)
6293	{
6294	while ( pDesc->pszName != NULL
6295	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6296	pDesc++;
6297	if ( pDesc->pszName != NULL
6298	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6299	{
6300	if (pDesc->cBits == 1)
6301	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6302	else
6303	{
6304	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6305	if (pDesc->cBits < 32)
6306	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6307	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6308	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6309	}
6310	}
6311	else
6312	pHlp->pfnPrintf(pHlp, " %u", iBit);
6313	}
6314	if (pszLeadIn)
6315	pHlp->pfnPrintf(pHlp, "\n");
6316	}
6317
6318
6319	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6320	const char *pszLeadIn, uint32_t cchWidth)
6321	{
6322	if (pszLeadIn)
6323	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6324
6325	for (uint32_t iBit = 0; iBit < 64; iBit++)
6326	if (RT_BIT_64(iBit) & uVal)
6327	{
6328	while ( pDesc->pszName != NULL
6329	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6330	pDesc++;
6331	if ( pDesc->pszName != NULL
6332	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6333	{
6334	if (pDesc->cBits == 1)
6335	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6336	else
6337	{
6338	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6339	if (pDesc->cBits < 64)
6340	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6341	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6342	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6343	}
6344	}
6345	else
6346	pHlp->pfnPrintf(pHlp, " %u", iBit);
6347	}
6348	if (pszLeadIn)
6349	pHlp->pfnPrintf(pHlp, "\n");
6350	}
6351
6352
6353	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6354	const char *pszLeadIn, uint32_t cchWidth)
6355	{
6356	if (!uVal)
6357	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6358	else
6359	{
6360	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6361	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6362	pHlp->pfnPrintf(pHlp, " )\n");
6363	}
6364	}
6365
6366
6367	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6368	uint32_t cchWidth)
6369	{
6370	uint32_t uCombined = uVal1 \| uVal2;
6371	for (uint32_t iBit = 0; iBit < 32; iBit++)
6372	if ( (RT_BIT_32(iBit) & uCombined)
6373	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6374	{
6375	while ( pDesc->pszName != NULL
6376	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6377	pDesc++;
6378
6379	if ( pDesc->pszName != NULL
6380	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6381	{
6382	size_t cchMnemonic = strlen(pDesc->pszName);
6383	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6384	size_t cchDesc = strlen(pszDesc);
6385	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6386	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6387	if (pDesc->cBits < 32)
6388	{
6389	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6390	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6391	}
6392
6393	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6394	pDesc->pszName, pszDesc,
6395	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6396	uFieldValue1, uFieldValue2);
6397
6398	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6399	pDesc++;
6400	}
6401	else
6402	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6403	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6404	}
6405	}
6406
6407
6408	/**
6409	* Produces a detailed summary of standard leaf 0x00000001.
6410	*
6411	* @param pHlp The info helper functions.
6412	* @param pCurLeaf The 0x00000001 leaf.
6413	* @param fVerbose Whether to be very verbose or not.
6414	* @param fIntel Set if intel CPU.
6415	*/
6416	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6417	{
6418	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6419	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6420	uint32_t uEAX = pCurLeaf->uEax;
6421	uint32_t uEBX = pCurLeaf->uEbx;
6422
6423	pHlp->pfnPrintf(pHlp,
6424	"%36s %2d \tExtended: %d \tEffective: %d\n"
6425	"%36s %2d \tExtended: %d \tEffective: %d\n"
6426	"%36s %d\n"
6427	"%36s %d (%s)\n"
6428	"%36s %#04x\n"
6429	"%36s %d\n"
6430	"%36s %d\n"
6431	"%36s %#04x\n"
6432	,
6433	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6434	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6435	"Stepping:", ASMGetCpuStepping(uEAX),
6436	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6437	"APIC ID:", (uEBX >> 24) & 0xff,
6438	"Logical CPUs:",(uEBX >> 16) & 0xff,
6439	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6440	"Brand ID:", (uEBX >> 0) & 0xff);
6441	if (fVerbose)
6442	{
6443	CPUMCPUID Host;
6444	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6445	pHlp->pfnPrintf(pHlp, "Features\n");
6446	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6447	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6448	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6449	}
6450	else
6451	{
6452	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6453	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6454	}
6455	}
6456
6457
6458	/**
6459	* Produces a detailed summary of standard leaf 0x00000007.
6460	*
6461	* @param pHlp The info helper functions.
6462	* @param paLeaves The CPUID leaves array.
6463	* @param cLeaves The number of leaves in the array.
6464	* @param pCurLeaf The first 0x00000007 leaf.
6465	* @param fVerbose Whether to be very verbose or not.
6466	*/
6467	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6468	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6469	{
6470	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6471	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6472	for (;;)
6473	{
6474	CPUMCPUID Host;
6475	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6476
6477	switch (pCurLeaf->uSubLeaf)
6478	{
6479	case 0:
6480	if (fVerbose)
6481	{
6482	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6483	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6484	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6485	if (pCurLeaf->uEdx \|\| Host.uEdx)
6486	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6487	}
6488	else
6489	{
6490	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6491	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6492	if (pCurLeaf->uEdx)
6493	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6494	}
6495	break;
6496
6497	default:
6498	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6499	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6500	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6501	break;
6502
6503	}
6504
6505	/* advance. */
6506	pCurLeaf++;
6507	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6508	\|\| pCurLeaf->uLeaf != 0x7)
6509	break;
6510	}
6511	}
6512
6513
6514	/**
6515	* Produces a detailed summary of standard leaf 0x0000000d.
6516	*
6517	* @param pHlp The info helper functions.
6518	* @param paLeaves The CPUID leaves array.
6519	* @param cLeaves The number of leaves in the array.
6520	* @param pCurLeaf The first 0x00000007 leaf.
6521	* @param fVerbose Whether to be very verbose or not.
6522	*/
6523	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6524	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6525	{
6526	RT_NOREF_PV(fVerbose);
6527	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6528	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6529	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6530	{
6531	CPUMCPUID Host;
6532	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6533
6534	switch (uSubLeaf)
6535	{
6536	case 0:
6537	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6538	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6539	pCurLeaf->uEbx, pCurLeaf->uEcx);
6540	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6541
6542	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6543	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6544	"Valid XCR0 bits, guest:", 42);
6545	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6546	"Valid XCR0 bits, host:", 42);
6547	break;
6548
6549	case 1:
6550	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6551	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6552	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6553
6554	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6555	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6556	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6557
6558	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6559	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6560	" Valid IA32_XSS bits, guest:", 42);
6561	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6562	" Valid IA32_XSS bits, host:", 42);
6563	break;
6564
6565	default:
6566	if ( pCurLeaf
6567	&& pCurLeaf->uSubLeaf == uSubLeaf
6568	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6569	{
6570	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6571	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6572	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6573	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6574	if (pCurLeaf->uEdx)
6575	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6576	pHlp->pfnPrintf(pHlp, " --");
6577	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6578	pHlp->pfnPrintf(pHlp, "\n");
6579	}
6580	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6581	{
6582	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6583	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6584	if (Host.uEcx & ~RT_BIT_32(0))
6585	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6586	if (Host.uEdx)
6587	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6588	pHlp->pfnPrintf(pHlp, " --");
6589	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6590	pHlp->pfnPrintf(pHlp, "\n");
6591	}
6592	break;
6593
6594	}
6595
6596	/* advance. */
6597	if (pCurLeaf)
6598	{
6599	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6600	&& pCurLeaf->uSubLeaf <= uSubLeaf
6601	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6602	pCurLeaf++;
6603	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6604	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6605	pCurLeaf = NULL;
6606	}
6607	}
6608	}
6609
6610
6611	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6612	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6613	{
6614	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6615	&& pCurLeaf->uLeaf <= uUpToLeaf)
6616	{
6617	pHlp->pfnPrintf(pHlp,
6618	" %s\n"
6619	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6620	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6621	&& pCurLeaf->uLeaf <= uUpToLeaf)
6622	{
6623	CPUMCPUID Host;
6624	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6625	pHlp->pfnPrintf(pHlp,
6626	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6627	"Hst: %08x %08x %08x %08x\n",
6628	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6629	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6630	pCurLeaf++;
6631	}
6632	}
6633
6634	return pCurLeaf;
6635	}
6636
6637
6638	/**
6639	* Display the guest CpuId leaves.
6640	*
6641	* @param pVM The cross context VM structure.
6642	* @param pHlp The info helper functions.
6643	* @param pszArgs "terse", "default" or "verbose".
6644	*/
6645	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6646	{
6647	/*
6648	* Parse the argument.
6649	*/
6650	unsigned iVerbosity = 1;
6651	if (pszArgs)
6652	{
6653	pszArgs = RTStrStripL(pszArgs);
6654	if (!strcmp(pszArgs, "terse"))
6655	iVerbosity--;
6656	else if (!strcmp(pszArgs, "verbose"))
6657	iVerbosity++;
6658	}
6659
6660	uint32_t uLeaf;
6661	CPUMCPUID Host;
6662	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6663	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6664	PCCPUMCPUIDLEAF pCurLeaf;
6665	PCCPUMCPUIDLEAF pNextLeaf;
6666	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6667	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6668	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6669
6670	/*
6671	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6672	*/
6673	uint32_t cHstMax = ASMCpuId_EAX(0);
6674	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6675	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6676	pHlp->pfnPrintf(pHlp,
6677	" Raw Standard CPUID Leaves\n"
6678	" Leaf/sub-leaf eax ebx ecx edx\n");
6679	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6680	{
6681	uint32_t cMaxSubLeaves = 1;
6682	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6683	cMaxSubLeaves = 16;
6684	else if (uLeaf == 0xd)
6685	cMaxSubLeaves = 128;
6686
6687	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6688	{
6689	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6690	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6691	&& pCurLeaf->uLeaf == uLeaf
6692	&& pCurLeaf->uSubLeaf == uSubLeaf)
6693	{
6694	pHlp->pfnPrintf(pHlp,
6695	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6696	"Hst: %08x %08x %08x %08x\n",
6697	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6698	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6699	pCurLeaf++;
6700	}
6701	else if ( uLeaf != 0xd
6702	\|\| uSubLeaf <= 1
6703	\|\| Host.uEbx != 0 )
6704	pHlp->pfnPrintf(pHlp,
6705	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6706	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6707
6708	/* Done? */
6709	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6710	\|\| pCurLeaf->uLeaf != uLeaf)
6711	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6712	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6713	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6714	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6715	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6716	)
6717	)
6718	break;
6719	}
6720	}
6721	pNextLeaf = pCurLeaf;
6722
6723	/*
6724	* If verbose, decode it.
6725	*/
6726	if (iVerbosity && paLeaves[0].uLeaf == 0)
6727	pHlp->pfnPrintf(pHlp,
6728	"%36s %.04s%.04s%.04s\n"
6729	"%36s 0x00000000-%#010x\n"
6730	,
6731	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6732	"Supports:", paLeaves[0].uEax);
6733
6734	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6735	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6736
6737	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6738	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6739
6740	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6741	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6742
6743	pCurLeaf = pNextLeaf;
6744
6745	/*
6746	* Hypervisor leaves.
6747	*
6748	* Unlike most of the other leaves reported, the guest hypervisor leaves
6749	* aren't a subset of the host CPUID bits.
6750	*/
6751	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6752
6753	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6754	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6755	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6756	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6757	cMax = RT_MAX(cHstMax, cGstMax);
6758	if (cMax >= UINT32_C(0x40000000))
6759	{
6760	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6761
6762	/** @todo dump these in more detail. */
6763
6764	pCurLeaf = pNextLeaf;
6765	}
6766
6767
6768	/*
6769	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6770	* Implemented after AMD specs.
6771	*/
6772	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6773
6774	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6775	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6776	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6777	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6778	cMax = RT_MAX(cHstMax, cGstMax);
6779	if (cMax >= UINT32_C(0x80000000))
6780	{
6781
6782	pHlp->pfnPrintf(pHlp,
6783	" Raw Extended CPUID Leaves\n"
6784	" Leaf/sub-leaf eax ebx ecx edx\n");
6785	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6786	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6787	{
6788	uint32_t cMaxSubLeaves = 1;
6789	if (uLeaf == UINT32_C(0x8000001d))
6790	cMaxSubLeaves = 16;
6791
6792	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6793	{
6794	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6795	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6796	&& pCurLeaf->uLeaf == uLeaf
6797	&& pCurLeaf->uSubLeaf == uSubLeaf)
6798	{
6799	pHlp->pfnPrintf(pHlp,
6800	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6801	"Hst: %08x %08x %08x %08x\n",
6802	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6803	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6804	pCurLeaf++;
6805	}
6806	else if ( uLeaf != 0xd
6807	\|\| uSubLeaf <= 1
6808	\|\| Host.uEbx != 0 )
6809	pHlp->pfnPrintf(pHlp,
6810	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6811	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6812
6813	/* Done? */
6814	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6815	\|\| pCurLeaf->uLeaf != uLeaf)
6816	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6817	break;
6818	}
6819	}
6820	pNextLeaf = pCurLeaf;
6821
6822	/*
6823	* Understandable output
6824	*/
6825	if (iVerbosity)
6826	pHlp->pfnPrintf(pHlp,
6827	"Ext Name: %.4s%.4s%.4s\n"
6828	"Ext Supports: 0x80000000-%#010x\n",
6829	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6830
6831	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6832	if (iVerbosity && pCurLeaf)
6833	{
6834	uint32_t uEAX = pCurLeaf->uEax;
6835	pHlp->pfnPrintf(pHlp,
6836	"Family: %d \tExtended: %d \tEffective: %d\n"
6837	"Model: %d \tExtended: %d \tEffective: %d\n"
6838	"Stepping: %d\n"
6839	"Brand ID: %#05x\n",
6840	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6841	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6842	ASMGetCpuStepping(uEAX),
6843	pCurLeaf->uEbx & 0xfff);
6844
6845	if (iVerbosity == 1)
6846	{
6847	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6848	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6849	}
6850	else
6851	{
6852	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6853	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6854	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6855	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6856	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6857	}
6858	}
6859
6860	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6861	{
6862	char szString[443+1] = {0};
6863	uint32_t pu32 = (uint32_t )szString;
6864	*pu32++ = pCurLeaf->uEax;
6865	*pu32++ = pCurLeaf->uEbx;
6866	*pu32++ = pCurLeaf->uEcx;
6867	*pu32++ = pCurLeaf->uEdx;
6868	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6869	if (pCurLeaf)
6870	{
6871	*pu32++ = pCurLeaf->uEax;
6872	*pu32++ = pCurLeaf->uEbx;
6873	*pu32++ = pCurLeaf->uEcx;
6874	*pu32++ = pCurLeaf->uEdx;
6875	}
6876	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6877	if (pCurLeaf)
6878	{
6879	*pu32++ = pCurLeaf->uEax;
6880	*pu32++ = pCurLeaf->uEbx;
6881	*pu32++ = pCurLeaf->uEcx;
6882	*pu32++ = pCurLeaf->uEdx;
6883	}
6884	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6885	}
6886
6887	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6888	{
6889	uint32_t uEAX = pCurLeaf->uEax;
6890	uint32_t uEBX = pCurLeaf->uEbx;
6891	uint32_t uECX = pCurLeaf->uEcx;
6892	uint32_t uEDX = pCurLeaf->uEdx;
6893	char sz1[32];
6894	char sz2[32];
6895
6896	pHlp->pfnPrintf(pHlp,
6897	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6898	"TLB 2/4M Data: %s %3d entries\n",
6899	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6900	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6901	pHlp->pfnPrintf(pHlp,
6902	"TLB 4K Instr/Uni: %s %3d entries\n"
6903	"TLB 4K Data: %s %3d entries\n",
6904	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6905	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6906	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6907	"L1 Instr Cache Lines Per Tag: %d\n"
6908	"L1 Instr Cache Associativity: %s\n"
6909	"L1 Instr Cache Size: %d KB\n",
6910	(uEDX >> 0) & 0xff,
6911	(uEDX >> 8) & 0xff,
6912	getCacheAss((uEDX >> 16) & 0xff, sz1),
6913	(uEDX >> 24) & 0xff);
6914	pHlp->pfnPrintf(pHlp,
6915	"L1 Data Cache Line Size: %d bytes\n"
6916	"L1 Data Cache Lines Per Tag: %d\n"
6917	"L1 Data Cache Associativity: %s\n"
6918	"L1 Data Cache Size: %d KB\n",
6919	(uECX >> 0) & 0xff,
6920	(uECX >> 8) & 0xff,
6921	getCacheAss((uECX >> 16) & 0xff, sz1),
6922	(uECX >> 24) & 0xff);
6923	}
6924
6925	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6926	{
6927	uint32_t uEAX = pCurLeaf->uEax;
6928	uint32_t uEBX = pCurLeaf->uEbx;
6929	uint32_t uEDX = pCurLeaf->uEdx;
6930
6931	pHlp->pfnPrintf(pHlp,
6932	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6933	"L2 TLB 2/4M Data: %s %4d entries\n",
6934	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6935	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6936	pHlp->pfnPrintf(pHlp,
6937	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6938	"L2 TLB 4K Data: %s %4d entries\n",
6939	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6940	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6941	pHlp->pfnPrintf(pHlp,
6942	"L2 Cache Line Size: %d bytes\n"
6943	"L2 Cache Lines Per Tag: %d\n"
6944	"L2 Cache Associativity: %s\n"
6945	"L2 Cache Size: %d KB\n",
6946	(uEDX >> 0) & 0xff,
6947	(uEDX >> 8) & 0xf,
6948	getL2CacheAss((uEDX >> 12) & 0xf),
6949	(uEDX >> 16) & 0xffff);
6950	}
6951
6952	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
6953	{
6954	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6955	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
6956	{
6957	if (iVerbosity < 1)
6958	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
6959	else
6960	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
6961	}
6962	}
6963
6964	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
6965	if (pCurLeaf != NULL)
6966	{
6967	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6968	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
6969	{
6970	if (iVerbosity < 1)
6971	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
6972	else
6973	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
6974	}
6975
6976	if (iVerbosity)
6977	{
6978	uint32_t uEAX = pCurLeaf->uEax;
6979	uint32_t uECX = pCurLeaf->uEcx;
6980
6981	pHlp->pfnPrintf(pHlp,
6982	"Physical Address Width: %d bits\n"
6983	"Virtual Address Width: %d bits\n"
6984	"Guest Physical Address Width: %d bits\n",
6985	(uEAX >> 0) & 0xff,
6986	(uEAX >> 8) & 0xff,
6987	(uEAX >> 16) & 0xff);
6988	pHlp->pfnPrintf(pHlp,
6989	"Physical Core Count: %d\n",
6990	((uECX >> 0) & 0xff) + 1);
6991	}
6992	}
6993
6994	pCurLeaf = pNextLeaf;
6995	}
6996
6997
6998
6999	/*
7000	* Centaur.
7001	*/
7002	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7003
7004	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7005	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7006	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7007	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7008	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7009	cMax = RT_MAX(cHstMax, cGstMax);
7010	if (cMax >= UINT32_C(0xc0000000))
7011	{
7012	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7013
7014	/*
7015	* Understandable output
7016	*/
7017	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7018	pHlp->pfnPrintf(pHlp,
7019	"Centaur Supports: 0xc0000000-%#010x\n",
7020	pCurLeaf->uEax);
7021
7022	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7023	{
7024	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7025	uint32_t uEdxGst = pCurLeaf->uEdx;
7026	uint32_t uEdxHst = Host.uEdx;
7027
7028	if (iVerbosity == 1)
7029	{
7030	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7031	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7032	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7033	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7034	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7035	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7036	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7037	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7038	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7039	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7040	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7041	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7042	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7043	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7044	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7045	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7046	for (unsigned iBit = 14; iBit < 32; iBit++)
7047	if (uEdxGst & RT_BIT(iBit))
7048	pHlp->pfnPrintf(pHlp, " %d", iBit);
7049	pHlp->pfnPrintf(pHlp, "\n");
7050	}
7051	else
7052	{
7053	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7054	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7055	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7056	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7057	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7058	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7059	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7060	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7061	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7062	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7063	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7064	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7065	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7066	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7067	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7068	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7069	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7070	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7071	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7072	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7073	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7074	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7075	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7076	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7077	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7078	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7079	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7080	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7081	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7082	for (unsigned iBit = 27; iBit < 32; iBit++)
7083	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7084	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7085	pHlp->pfnPrintf(pHlp, "\n");
7086	}
7087	}
7088
7089	pCurLeaf = pNextLeaf;
7090	}
7091
7092	/*
7093	* The remainder.
7094	*/
7095	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7096	}
7097
7098
7099
7100
7101
7102	/*
7103	*
7104	*
7105	* PATM interfaces.
7106	* PATM interfaces.
7107	* PATM interfaces.
7108	*
7109	*
7110	*/
7111
7112
7113	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
7114	/** @name Patchmanager CPUID legacy table APIs
7115	* @{
7116	*/
7117
7118	/**
7119	* Gets a pointer to the default CPUID leaf.
7120	*
7121	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
7122	* @param pVM The cross context VM structure.
7123	* @remark Intended for PATM only.
7124	*/
7125	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
7126	{
7127	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
7128	}
7129
7130
7131	/**
7132	* Gets a number of standard CPUID leaves (PATM only).
7133	*
7134	* @returns Number of leaves.
7135	* @param pVM The cross context VM structure.
7136	* @remark Intended for PATM - legacy, don't use in new code.
7137	*/
7138	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
7139	{
7140	RT_NOREF_PV(pVM);
7141	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
7142	}
7143
7144
7145	/**
7146	* Gets a number of extended CPUID leaves (PATM only).
7147	*
7148	* @returns Number of leaves.
7149	* @param pVM The cross context VM structure.
7150	* @remark Intended for PATM - legacy, don't use in new code.
7151	*/
7152	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
7153	{
7154	RT_NOREF_PV(pVM);
7155	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
7156	}
7157
7158
7159	/**
7160	* Gets a number of centaur CPUID leaves.
7161	*
7162	* @returns Number of leaves.
7163	* @param pVM The cross context VM structure.
7164	* @remark Intended for PATM - legacy, don't use in new code.
7165	*/
7166	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
7167	{
7168	RT_NOREF_PV(pVM);
7169	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
7170	}
7171
7172
7173	/**
7174	* Gets a pointer to the array of standard CPUID leaves.
7175	*
7176	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
7177	*
7178	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
7179	* @param pVM The cross context VM structure.
7180	* @remark Intended for PATM - legacy, don't use in new code.
7181	*/
7182	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
7183	{
7184	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
7185	}
7186
7187
7188	/**
7189	* Gets a pointer to the array of extended CPUID leaves.
7190	*
7191	* CPUMGetGuestCpuIdExtMax() give the size of the array.
7192	*
7193	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
7194	* @param pVM The cross context VM structure.
7195	* @remark Intended for PATM - legacy, don't use in new code.
7196	*/
7197	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
7198	{
7199	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
7200	}
7201
7202
7203	/**
7204	* Gets a pointer to the array of centaur CPUID leaves.
7205	*
7206	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
7207	*
7208	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
7209	* @param pVM The cross context VM structure.
7210	* @remark Intended for PATM - legacy, don't use in new code.
7211	*/
7212	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
7213	{
7214	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
7215	}
7216
7217	/** @} */
7218	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
7219
7220	#endif /* VBOX_IN_VMM */
7221

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 71289

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