CPUMR3CpuId.cpp@ 72489

Last change on this file since 72489 was 72456, checked in by vboxsync, 7 years ago
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1	/* $Id: CPUMR3CpuId.cpp 72456 2018-06-06 03:53:15Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/mm.h>
31	#include <VBox/sup.h>
32
33	#include <VBox/err.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/ctype.h>
36	#include <iprt/mem.h>
37	#include <iprt/string.h>
38
39
40	/*********************************************************************************************************************************
41	* Defined Constants And Macros *
42	*********************************************************************************************************************************/
43	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
44	#define CPUM_CPUID_MAX_LEAVES 2048
45	/* Max size we accept for the XSAVE area. */
46	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
47	/* Min size we accept for the XSAVE area. */
48	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
49
50
51	/*********************************************************************************************************************************
52	* Global Variables *
53	*********************************************************************************************************************************/
54	/**
55	* The intel pentium family.
56	*/
57	static const CPUMMICROARCH g_aenmIntelFamily06[] =
58	{
59	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
60	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
61	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
63	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
64	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
65	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
66	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
67	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
68	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
69	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
70	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
71	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
72	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
73	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
74	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
75	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
81	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
82	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
83	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
86	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
88	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
89	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
90	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
91	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
97	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
98	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
99	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
102	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
104	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
105	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
106	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
107	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
113	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
114	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
115	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
118	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
121	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
122	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
130	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
131	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
136	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [78(0x4e)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed */
138	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / unconfirmed, Broadwell-E */
139	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu */
145	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
146	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
147	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
150	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
152	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
153	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
154	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
155	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
159	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
160	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
161	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
162	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
163	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
164	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
165	/[106(0x6a)] = / kCpumMicroarch_Intel_Unknown,
166	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
167	/[108(0x6c)] = / kCpumMicroarch_Intel_Unknown,
168	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
169	/[110(0x6e)] = / kCpumMicroarch_Intel_Unknown,
170	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
171	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
172	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
173	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
174	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
175	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
176	/[117(0x75)] = / kCpumMicroarch_Intel_Unknown,
177	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
178	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
179	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
180	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
181	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
182	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
183	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
184	/[125(0x7d)] = / kCpumMicroarch_Intel_Unknown,
185	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
186	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
187	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
188	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
189	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
190	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
191	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
192	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
193	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
194	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
195	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
196	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
197	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
198	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
199	/[140(0x8c)] = / kCpumMicroarch_Intel_Unknown,
200	/[141(0x8d)] = / kCpumMicroarch_Intel_Unknown,
201	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
202	/[143(0x8f)] = / kCpumMicroarch_Intel_Unknown,
203	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
204	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
205	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
206	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
207	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
208	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
209	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
210	/[151(0x97)] = / kCpumMicroarch_Intel_Unknown,
211	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
212	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
213	/[154(0x9a)] = / kCpumMicroarch_Intel_Unknown,
214	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
215	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
216	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
217	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
218	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
219	};
220	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0x9f+1);
221
222
223	/**
224	* Figures out the (sub-)micro architecture given a bit of CPUID info.
225	*
226	* @returns Micro architecture.
227	* @param enmVendor The CPU vendor .
228	* @param bFamily The CPU family.
229	* @param bModel The CPU model.
230	* @param bStepping The CPU stepping.
231	*/
232	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
233	uint8_t bModel, uint8_t bStepping)
234	{
235	if (enmVendor == CPUMCPUVENDOR_AMD)
236	{
237	switch (bFamily)
238	{
239	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
240	case 0x03: return kCpumMicroarch_AMD_Am386;
241	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
242	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
243	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
244	case 0x06:
245	switch (bModel)
246	{
247	case 0: return kCpumMicroarch_AMD_K7_Palomino;
248	case 1: return kCpumMicroarch_AMD_K7_Palomino;
249	case 2: return kCpumMicroarch_AMD_K7_Palomino;
250	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
251	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
252	case 6: return kCpumMicroarch_AMD_K7_Palomino;
253	case 7: return kCpumMicroarch_AMD_K7_Morgan;
254	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
255	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
256	}
257	return kCpumMicroarch_AMD_K7_Unknown;
258	case 0x0f:
259	/*
260	* This family is a friggin mess. Trying my best to make some
261	* sense out of it. Too much happened in the 0x0f family to
262	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
263	*
264	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
265	* cpu-world.com, and other places:
266	* - 130nm:
267	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
268	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
269	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
270	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
271	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
272	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
273	* - 90nm:
274	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
275	* - Oakville: 10FC0/DH-D0.
276	* - Georgetown: 10FC0/DH-D0.
277	* - Sonora: 10FC0/DH-D0.
278	* - Venus: 20F71/SH-E4
279	* - Troy: 20F51/SH-E4
280	* - Athens: 20F51/SH-E4
281	* - San Diego: 20F71/SH-E4.
282	* - Lancaster: 20F42/SH-E5
283	* - Newark: 20F42/SH-E5.
284	* - Albany: 20FC2/DH-E6.
285	* - Roma: 20FC2/DH-E6.
286	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
287	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
288	* - 90nm introducing Dual core:
289	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
290	* - Italy: 20F10/JH-E1, 20F12/JH-E6
291	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
292	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
293	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
294	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
295	* - Santa Ana: 40F32/JH-F2, /-F3
296	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
297	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
298	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
299	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
300	* - Keene: 40FC2/DH-F2.
301	* - Richmond: 40FC2/DH-F2
302	* - Taylor: 40F82/BH-F2
303	* - Trinidad: 40F82/BH-F2
304	*
305	* - 65nm:
306	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
307	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
308	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
309	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
310	* - Sherman: /-G1, 70FC2/DH-G2.
311	* - Huron: 70FF2/DH-G2.
312	*/
313	if (bModel < 0x10)
314	return kCpumMicroarch_AMD_K8_130nm;
315	if (bModel >= 0x60 && bModel < 0x80)
316	return kCpumMicroarch_AMD_K8_65nm;
317	if (bModel >= 0x40)
318	return kCpumMicroarch_AMD_K8_90nm_AMDV;
319	switch (bModel)
320	{
321	case 0x21:
322	case 0x23:
323	case 0x2b:
324	case 0x2f:
325	case 0x37:
326	case 0x3f:
327	return kCpumMicroarch_AMD_K8_90nm_DualCore;
328	}
329	return kCpumMicroarch_AMD_K8_90nm;
330	case 0x10:
331	return kCpumMicroarch_AMD_K10;
332	case 0x11:
333	return kCpumMicroarch_AMD_K10_Lion;
334	case 0x12:
335	return kCpumMicroarch_AMD_K10_Llano;
336	case 0x14:
337	return kCpumMicroarch_AMD_Bobcat;
338	case 0x15:
339	switch (bModel)
340	{
341	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
342	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
343	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
344	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
345	case 0x11: /* ?? */
346	case 0x12: /* ?? */
347	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
348	}
349	return kCpumMicroarch_AMD_15h_Unknown;
350	case 0x16:
351	return kCpumMicroarch_AMD_Jaguar;
352	case 0x17:
353	return kCpumMicroarch_AMD_Zen_Ryzen;
354	}
355	return kCpumMicroarch_AMD_Unknown;
356	}
357
358	if (enmVendor == CPUMCPUVENDOR_INTEL)
359	{
360	switch (bFamily)
361	{
362	case 3:
363	return kCpumMicroarch_Intel_80386;
364	case 4:
365	return kCpumMicroarch_Intel_80486;
366	case 5:
367	return kCpumMicroarch_Intel_P5;
368	case 6:
369	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
370	{
371	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
372	if ( enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake
373	&& bStepping >= 0xa)
374	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
375	return enmMicroArch;
376	}
377	return kCpumMicroarch_Intel_Atom_Unknown;
378	case 15:
379	switch (bModel)
380	{
381	case 0: return kCpumMicroarch_Intel_NB_Willamette;
382	case 1: return kCpumMicroarch_Intel_NB_Willamette;
383	case 2: return kCpumMicroarch_Intel_NB_Northwood;
384	case 3: return kCpumMicroarch_Intel_NB_Prescott;
385	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
386	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
387	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
388	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
389	default: return kCpumMicroarch_Intel_NB_Unknown;
390	}
391	break;
392	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
393	case 0:
394	return kCpumMicroarch_Intel_8086;
395	case 1:
396	return kCpumMicroarch_Intel_80186;
397	case 2:
398	return kCpumMicroarch_Intel_80286;
399	}
400	return kCpumMicroarch_Intel_Unknown;
401	}
402
403	if (enmVendor == CPUMCPUVENDOR_VIA)
404	{
405	switch (bFamily)
406	{
407	case 5:
408	switch (bModel)
409	{
410	case 1: return kCpumMicroarch_Centaur_C6;
411	case 4: return kCpumMicroarch_Centaur_C6;
412	case 8: return kCpumMicroarch_Centaur_C2;
413	case 9: return kCpumMicroarch_Centaur_C3;
414	}
415	break;
416
417	case 6:
418	switch (bModel)
419	{
420	case 5: return kCpumMicroarch_VIA_C3_M2;
421	case 6: return kCpumMicroarch_VIA_C3_C5A;
422	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
423	case 8: return kCpumMicroarch_VIA_C3_C5N;
424	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
425	case 10: return kCpumMicroarch_VIA_C7_C5J;
426	case 15: return kCpumMicroarch_VIA_Isaiah;
427	}
428	break;
429	}
430	return kCpumMicroarch_VIA_Unknown;
431	}
432
433	if (enmVendor == CPUMCPUVENDOR_CYRIX)
434	{
435	switch (bFamily)
436	{
437	case 4:
438	switch (bModel)
439	{
440	case 9: return kCpumMicroarch_Cyrix_5x86;
441	}
442	break;
443
444	case 5:
445	switch (bModel)
446	{
447	case 2: return kCpumMicroarch_Cyrix_M1;
448	case 4: return kCpumMicroarch_Cyrix_MediaGX;
449	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
450	}
451	break;
452
453	case 6:
454	switch (bModel)
455	{
456	case 0: return kCpumMicroarch_Cyrix_M2;
457	}
458	break;
459
460	}
461	return kCpumMicroarch_Cyrix_Unknown;
462	}
463
464	return kCpumMicroarch_Unknown;
465	}
466
467
468	/**
469	* Translates a microarchitecture enum value to the corresponding string
470	* constant.
471	*
472	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
473	* NULL if the value is invalid.
474	*
475	* @param enmMicroarch The enum value to convert.
476	*/
477	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
478	{
479	switch (enmMicroarch)
480	{
481	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
482	CASE_RET_STR(kCpumMicroarch_Intel_8086);
483	CASE_RET_STR(kCpumMicroarch_Intel_80186);
484	CASE_RET_STR(kCpumMicroarch_Intel_80286);
485	CASE_RET_STR(kCpumMicroarch_Intel_80386);
486	CASE_RET_STR(kCpumMicroarch_Intel_80486);
487	CASE_RET_STR(kCpumMicroarch_Intel_P5);
488
489	CASE_RET_STR(kCpumMicroarch_Intel_P6);
490	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
491	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
492
493	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
494	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
495	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
496
497	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
498	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
499
500	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
501	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
502	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
503	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
504	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
505	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
506	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
507	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
508	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
509	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
510	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
511	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
512
513	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
514	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
515	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
516	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
517	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
518	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
519	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
520	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
521
522	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
523	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
524	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
525	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
526	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
527
528	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
529	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
530	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
531	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
532	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
533	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
534	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
535
536	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
537
538	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
539	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
540	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
541	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
542	CASE_RET_STR(kCpumMicroarch_AMD_K5);
543	CASE_RET_STR(kCpumMicroarch_AMD_K6);
544
545	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
546	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
547	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
548	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
549	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
550	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
551	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
552
553	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
554	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
555	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
556	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
557	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
558
559	CASE_RET_STR(kCpumMicroarch_AMD_K10);
560	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
561	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
562	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
563	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
564
565	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
566	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
567	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
568	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
569	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
570
571	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
572
573	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
574
575	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
576
577	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
578	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
579	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
580	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
581	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
582	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
583	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
584	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
585	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
586	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
587	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
588	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
589	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
590
591	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
592	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
593	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
594	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
595	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
596	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
597
598	CASE_RET_STR(kCpumMicroarch_NEC_V20);
599	CASE_RET_STR(kCpumMicroarch_NEC_V30);
600
601	CASE_RET_STR(kCpumMicroarch_Unknown);
602
603	#undef CASE_RET_STR
604	case kCpumMicroarch_Invalid:
605	case kCpumMicroarch_Intel_End:
606	case kCpumMicroarch_Intel_Core2_End:
607	case kCpumMicroarch_Intel_Core7_End:
608	case kCpumMicroarch_Intel_Atom_End:
609	case kCpumMicroarch_Intel_P6_Core_Atom_End:
610	case kCpumMicroarch_Intel_Phi_End:
611	case kCpumMicroarch_Intel_NB_End:
612	case kCpumMicroarch_AMD_K7_End:
613	case kCpumMicroarch_AMD_K8_End:
614	case kCpumMicroarch_AMD_15h_End:
615	case kCpumMicroarch_AMD_16h_End:
616	case kCpumMicroarch_AMD_Zen_End:
617	case kCpumMicroarch_AMD_End:
618	case kCpumMicroarch_VIA_End:
619	case kCpumMicroarch_Cyrix_End:
620	case kCpumMicroarch_NEC_End:
621	case kCpumMicroarch_32BitHack:
622	break;
623	/* no default! */
624	}
625
626	return NULL;
627	}
628
629
630	/**
631	* Determins the host CPU MXCSR mask.
632	*
633	* @returns MXCSR mask.
634	*/
635	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
636	{
637	if ( ASMHasCpuId()
638	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
639	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
640	{
641	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
642	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
643	RT_ZERO(*pState);
644	ASMFxSave(pState);
645	if (pState->MXCSR_MASK == 0)
646	return 0xffbf;
647	return pState->MXCSR_MASK;
648	}
649	return 0;
650	}
651
652
653	/**
654	* Gets a matching leaf in the CPUID leaf array.
655	*
656	* @returns Pointer to the matching leaf, or NULL if not found.
657	* @param paLeaves The CPUID leaves to search. This is sorted.
658	* @param cLeaves The number of leaves in the array.
659	* @param uLeaf The leaf to locate.
660	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
661	*/
662	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
663	{
664	/* Lazy bird does linear lookup here since this is only used for the
665	occational CPUID overrides. */
666	for (uint32_t i = 0; i < cLeaves; i++)
667	if ( paLeaves[i].uLeaf == uLeaf
668	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
669	return &paLeaves[i];
670	return NULL;
671	}
672
673
674	#ifndef IN_VBOX_CPU_REPORT
675	/**
676	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
677	*
678	* @returns true if found, false it not.
679	* @param paLeaves The CPUID leaves to search. This is sorted.
680	* @param cLeaves The number of leaves in the array.
681	* @param uLeaf The leaf to locate.
682	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
683	* @param pLegacy The legacy output leaf.
684	*/
685	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
686	PCPUMCPUID pLegacy)
687	{
688	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
689	if (pLeaf)
690	{
691	pLegacy->uEax = pLeaf->uEax;
692	pLegacy->uEbx = pLeaf->uEbx;
693	pLegacy->uEcx = pLeaf->uEcx;
694	pLegacy->uEdx = pLeaf->uEdx;
695	return true;
696	}
697	return false;
698	}
699	#endif /* IN_VBOX_CPU_REPORT */
700
701
702	/**
703	* Ensures that the CPUID leaf array can hold one more leaf.
704	*
705	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
706	* failure.
707	* @param pVM The cross context VM structure. If NULL, use
708	* the process heap, otherwise the VM's hyper heap.
709	* @param ppaLeaves Pointer to the variable holding the array pointer
710	* (input/output).
711	* @param cLeaves The current array size.
712	*
713	* @remarks This function will automatically update the R0 and RC pointers when
714	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
715	* be the corresponding VM's CPUID arrays (which is asserted).
716	*/
717	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
718	{
719	/*
720	* If pVM is not specified, we're on the regular heap and can waste a
721	* little space to speed things up.
722	*/
723	uint32_t cAllocated;
724	if (!pVM)
725	{
726	cAllocated = RT_ALIGN(cLeaves, 16);
727	if (cLeaves + 1 > cAllocated)
728	{
729	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
730	if (pvNew)
731	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
732	else
733	{
734	RTMemFree(*ppaLeaves);
735	*ppaLeaves = NULL;
736	}
737	}
738	}
739	/*
740	* Otherwise, we're on the hyper heap and are probably just inserting
741	* one or two leaves and should conserve space.
742	*/
743	else
744	{
745	#ifdef IN_VBOX_CPU_REPORT
746	AssertReleaseFailed();
747	#else
748	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
749	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
750
751	size_t cb = cLeaves * sizeof(**ppaLeaves);
752	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
753	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
754	if (RT_SUCCESS(rc))
755	{
756	/* Update the R0 and RC pointers. */
757	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
758	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
759	}
760	else
761	{
762	*ppaLeaves = NULL;
763	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
764	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
765	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
766	}
767	#endif
768	}
769	return *ppaLeaves;
770	}
771
772
773	/**
774	* Append a CPUID leaf or sub-leaf.
775	*
776	* ASSUMES linear insertion order, so we'll won't need to do any searching or
777	* replace anything. Use cpumR3CpuIdInsert() for those cases.
778	*
779	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
780	* the caller need do no more work.
781	* @param ppaLeaves Pointer to the pointer to the array of sorted
782	* CPUID leaves and sub-leaves.
783	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
784	* @param uLeaf The leaf we're adding.
785	* @param uSubLeaf The sub-leaf number.
786	* @param fSubLeafMask The sub-leaf mask.
787	* @param uEax The EAX value.
788	* @param uEbx The EBX value.
789	* @param uEcx The ECX value.
790	* @param uEdx The EDX value.
791	* @param fFlags The flags.
792	*/
793	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
794	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
795	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
796	{
797	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
798	return VERR_NO_MEMORY;
799
800	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
801	Assert( *pcLeaves == 0
802	\|\| pNew[-1].uLeaf < uLeaf
803	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
804
805	pNew->uLeaf = uLeaf;
806	pNew->uSubLeaf = uSubLeaf;
807	pNew->fSubLeafMask = fSubLeafMask;
808	pNew->uEax = uEax;
809	pNew->uEbx = uEbx;
810	pNew->uEcx = uEcx;
811	pNew->uEdx = uEdx;
812	pNew->fFlags = fFlags;
813
814	*pcLeaves += 1;
815	return VINF_SUCCESS;
816	}
817
818
819	/**
820	* Checks that we've updated the CPUID leaves array correctly.
821	*
822	* This is a no-op in non-strict builds.
823	*
824	* @param paLeaves The leaves array.
825	* @param cLeaves The number of leaves.
826	*/
827	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
828	{
829	#ifdef VBOX_STRICT
830	for (uint32_t i = 1; i < cLeaves; i++)
831	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
832	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
833	else
834	{
835	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
836	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
837	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
838	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
839	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
840	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
841	}
842	#else
843	NOREF(paLeaves);
844	NOREF(cLeaves);
845	#endif
846	}
847
848
849	/**
850	* Inserts a CPU ID leaf, replacing any existing ones.
851	*
852	* When inserting a simple leaf where we already got a series of sub-leaves with
853	* the same leaf number (eax), the simple leaf will replace the whole series.
854	*
855	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
856	* host-context heap and has only been allocated/reallocated by the
857	* cpumR3CpuIdEnsureSpace function.
858	*
859	* @returns VBox status code.
860	* @param pVM The cross context VM structure. If NULL, use
861	* the process heap, otherwise the VM's hyper heap.
862	* @param ppaLeaves Pointer to the pointer to the array of sorted
863	* CPUID leaves and sub-leaves. Must be NULL if using
864	* the hyper heap.
865	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
866	* be NULL if using the hyper heap.
867	* @param pNewLeaf Pointer to the data of the new leaf we're about to
868	* insert.
869	*/
870	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
871	{
872	/*
873	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
874	*/
875	if (pVM)
876	{
877	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
878	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
879
880	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
881	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
882	}
883
884	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
885	uint32_t cLeaves = *pcLeaves;
886
887	/*
888	* Validate the new leaf a little.
889	*/
890	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
891	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
892	VERR_INVALID_FLAGS);
893	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
894	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
895	VERR_INVALID_PARAMETER);
896	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
897	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
898	VERR_INVALID_PARAMETER);
899	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
900	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
901	VERR_INVALID_PARAMETER);
902
903	/*
904	* Find insertion point. The lazy bird uses the same excuse as in
905	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
906	*/
907	uint32_t i;
908	if ( cLeaves > 0
909	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
910	{
911	/* Add at end. */
912	i = cLeaves;
913	}
914	else if ( cLeaves > 0
915	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
916	{
917	/* Either replacing the last leaf or dealing with sub-leaves. Spool
918	back to the first sub-leaf to pretend we did the linear search. */
919	i = cLeaves - 1;
920	while ( i > 0
921	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
922	i--;
923	}
924	else
925	{
926	/* Linear search from the start. */
927	i = 0;
928	while ( i < cLeaves
929	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
930	i++;
931	}
932	if ( i < cLeaves
933	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
934	{
935	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
936	{
937	/*
938	* The sub-leaf mask differs, replace all existing leaves with the
939	* same leaf number.
940	*/
941	uint32_t c = 1;
942	while ( i + c < cLeaves
943	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
944	c++;
945	if (c > 1 && i + c < cLeaves)
946	{
947	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
948	*pcLeaves = cLeaves -= c - 1;
949	}
950
951	paLeaves[i] = *pNewLeaf;
952	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
953	return VINF_SUCCESS;
954	}
955
956	/* Find sub-leaf insertion point. */
957	while ( i < cLeaves
958	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
959	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
960	i++;
961
962	/*
963	* If we've got an exactly matching leaf, replace it.
964	*/
965	if ( i < cLeaves
966	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
967	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
968	{
969	paLeaves[i] = *pNewLeaf;
970	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
971	return VINF_SUCCESS;
972	}
973	}
974
975	/*
976	* Adding a new leaf at 'i'.
977	*/
978	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
979	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
980	if (!paLeaves)
981	return VERR_NO_MEMORY;
982
983	if (i < cLeaves)
984	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
985	*pcLeaves += 1;
986	paLeaves[i] = *pNewLeaf;
987
988	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
989	return VINF_SUCCESS;
990	}
991
992
993	#ifndef IN_VBOX_CPU_REPORT
994	/**
995	* Removes a range of CPUID leaves.
996	*
997	* This will not reallocate the array.
998	*
999	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1000	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1001	* @param uFirst The first leaf.
1002	* @param uLast The last leaf.
1003	*/
1004	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1005	{
1006	uint32_t cLeaves = *pcLeaves;
1007
1008	Assert(uFirst <= uLast);
1009
1010	/*
1011	* Find the first one.
1012	*/
1013	uint32_t iFirst = 0;
1014	while ( iFirst < cLeaves
1015	&& paLeaves[iFirst].uLeaf < uFirst)
1016	iFirst++;
1017
1018	/*
1019	* Find the end (last + 1).
1020	*/
1021	uint32_t iEnd = iFirst;
1022	while ( iEnd < cLeaves
1023	&& paLeaves[iEnd].uLeaf <= uLast)
1024	iEnd++;
1025
1026	/*
1027	* Adjust the array if anything needs removing.
1028	*/
1029	if (iFirst < iEnd)
1030	{
1031	if (iEnd < cLeaves)
1032	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1033	*pcLeaves = cLeaves -= (iEnd - iFirst);
1034	}
1035
1036	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1037	}
1038	#endif /* IN_VBOX_CPU_REPORT */
1039
1040
1041	/**
1042	* Checks if ECX make a difference when reading a given CPUID leaf.
1043	*
1044	* @returns @c true if it does, @c false if it doesn't.
1045	* @param uLeaf The leaf we're reading.
1046	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1047	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1048	* final sub-leaf (for leaf 0xb only).
1049	*/
1050	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1051	{
1052	*pfFinalEcxUnchanged = false;
1053
1054	uint32_t auCur[4];
1055	uint32_t auPrev[4];
1056	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1057
1058	/* Look for sub-leaves. */
1059	uint32_t uSubLeaf = 1;
1060	for (;;)
1061	{
1062	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1063	if (memcmp(auCur, auPrev, sizeof(auCur)))
1064	break;
1065
1066	/* Advance / give up. */
1067	uSubLeaf++;
1068	if (uSubLeaf >= 64)
1069	{
1070	*pcSubLeaves = 1;
1071	return false;
1072	}
1073	}
1074
1075	/* Count sub-leaves. */
1076	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1077	uint32_t cRepeats = 0;
1078	uSubLeaf = 0;
1079	for (;;)
1080	{
1081	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1082
1083	/* Figuring out when to stop isn't entirely straight forward as we need
1084	to cover undocumented behavior up to a point and implementation shortcuts. */
1085
1086	/* 1. Look for more than 4 repeating value sets. */
1087	if ( auCur[0] == auPrev[0]
1088	&& auCur[1] == auPrev[1]
1089	&& ( auCur[2] == auPrev[2]
1090	\|\| ( auCur[2] == uSubLeaf
1091	&& auPrev[2] == uSubLeaf - 1) )
1092	&& auCur[3] == auPrev[3])
1093	{
1094	if ( uLeaf != 0xd
1095	\|\| uSubLeaf >= 64
1096	\|\| ( auCur[0] == 0
1097	&& auCur[1] == 0
1098	&& auCur[2] == 0
1099	&& auCur[3] == 0
1100	&& auPrev[2] == 0) )
1101	cRepeats++;
1102	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1103	break;
1104	}
1105	else
1106	cRepeats = 0;
1107
1108	/* 2. Look for zero values. */
1109	if ( auCur[0] == 0
1110	&& auCur[1] == 0
1111	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1112	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1113	&& uSubLeaf >= cMinLeaves)
1114	{
1115	cRepeats = 0;
1116	break;
1117	}
1118
1119	/* 3. Leaf 0xb level type 0 check. */
1120	if ( uLeaf == 0xb
1121	&& (auCur[2] & 0xff00) == 0
1122	&& (auPrev[2] & 0xff00) == 0)
1123	{
1124	cRepeats = 0;
1125	break;
1126	}
1127
1128	/* 99. Give up. */
1129	if (uSubLeaf >= 128)
1130	{
1131	#ifndef IN_VBOX_CPU_REPORT
1132	/* Ok, limit it according to the documentation if possible just to
1133	avoid annoying users with these detection issues. */
1134	uint32_t cDocLimit = UINT32_MAX;
1135	if (uLeaf == 0x4)
1136	cDocLimit = 4;
1137	else if (uLeaf == 0x7)
1138	cDocLimit = 1;
1139	else if (uLeaf == 0xd)
1140	cDocLimit = 63;
1141	else if (uLeaf == 0xf)
1142	cDocLimit = 2;
1143	if (cDocLimit != UINT32_MAX)
1144	{
1145	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1146	*pcSubLeaves = cDocLimit + 3;
1147	return true;
1148	}
1149	#endif
1150	*pcSubLeaves = UINT32_MAX;
1151	return true;
1152	}
1153
1154	/* Advance. */
1155	uSubLeaf++;
1156	memcpy(auPrev, auCur, sizeof(auCur));
1157	}
1158
1159	/* Standard exit. */
1160	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1161	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1162	if (*pcSubLeaves == 0)
1163	*pcSubLeaves = 1;
1164	return true;
1165	}
1166
1167
1168	/**
1169	* Gets a CPU ID leaf.
1170	*
1171	* @returns VBox status code.
1172	* @param pVM The cross context VM structure.
1173	* @param pLeaf Where to store the found leaf.
1174	* @param uLeaf The leaf to locate.
1175	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1176	*/
1177	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1178	{
1179	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1180	uLeaf, uSubLeaf);
1181	if (pcLeaf)
1182	{
1183	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1184	return VINF_SUCCESS;
1185	}
1186
1187	return VERR_NOT_FOUND;
1188	}
1189
1190
1191	/**
1192	* Inserts a CPU ID leaf, replacing any existing ones.
1193	*
1194	* @returns VBox status code.
1195	* @param pVM The cross context VM structure.
1196	* @param pNewLeaf Pointer to the leaf being inserted.
1197	*/
1198	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1199	{
1200	/*
1201	* Validate parameters.
1202	*/
1203	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1204	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1205
1206	/*
1207	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1208	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1209	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1210	*/
1211	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1212	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1213	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1214	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1215	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1216	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1217	{
1218	return VERR_NOT_SUPPORTED;
1219	}
1220
1221	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1222	}
1223
1224	/**
1225	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1226	*
1227	* @returns VBox status code.
1228	* @param ppaLeaves Where to return the array pointer on success.
1229	* Use RTMemFree to release.
1230	* @param pcLeaves Where to return the size of the array on
1231	* success.
1232	*/
1233	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1234	{
1235	*ppaLeaves = NULL;
1236	*pcLeaves = 0;
1237
1238	/*
1239	* Try out various candidates. This must be sorted!
1240	*/
1241	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1242	{
1243	{ UINT32_C(0x00000000), false },
1244	{ UINT32_C(0x10000000), false },
1245	{ UINT32_C(0x20000000), false },
1246	{ UINT32_C(0x30000000), false },
1247	{ UINT32_C(0x40000000), false },
1248	{ UINT32_C(0x50000000), false },
1249	{ UINT32_C(0x60000000), false },
1250	{ UINT32_C(0x70000000), false },
1251	{ UINT32_C(0x80000000), false },
1252	{ UINT32_C(0x80860000), false },
1253	{ UINT32_C(0x8ffffffe), true },
1254	{ UINT32_C(0x8fffffff), true },
1255	{ UINT32_C(0x90000000), false },
1256	{ UINT32_C(0xa0000000), false },
1257	{ UINT32_C(0xb0000000), false },
1258	{ UINT32_C(0xc0000000), false },
1259	{ UINT32_C(0xd0000000), false },
1260	{ UINT32_C(0xe0000000), false },
1261	{ UINT32_C(0xf0000000), false },
1262	};
1263
1264	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1265	{
1266	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1267	uint32_t uEax, uEbx, uEcx, uEdx;
1268	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1269
1270	/*
1271	* Does EAX look like a typical leaf count value?
1272	*/
1273	if ( uEax > uLeaf
1274	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1275	{
1276	/* Yes, dump them. */
1277	uint32_t cLeaves = uEax - uLeaf + 1;
1278	while (cLeaves-- > 0)
1279	{
1280	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1281
1282	uint32_t fFlags = 0;
1283
1284	/* There are currently three known leaves containing an APIC ID
1285	that needs EMT specific attention */
1286	if (uLeaf == 1)
1287	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1288	else if (uLeaf == 0xb && uEcx != 0)
1289	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1290	else if ( uLeaf == UINT32_C(0x8000001e)
1291	&& ( uEax
1292	\|\| uEbx
1293	\|\| uEdx
1294	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1295	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1296
1297	/* The APIC bit is per-VCpu and needs flagging. */
1298	if (uLeaf == 1)
1299	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1300	else if ( uLeaf == UINT32_C(0x80000001)
1301	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1302	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1303	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1304
1305	/* Check three times here to reduce the chance of CPU migration
1306	resulting in false positives with things like the APIC ID. */
1307	uint32_t cSubLeaves;
1308	bool fFinalEcxUnchanged;
1309	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1310	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1311	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1312	{
1313	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1314	{
1315	/* This shouldn't happen. But in case it does, file all
1316	relevant details in the release log. */
1317	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1318	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1319	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1320	{
1321	uint32_t auTmp[4];
1322	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1323	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1324	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1325	}
1326	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1327	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1328	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1329	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1330	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1331	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1332	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1333	}
1334
1335	if (fFinalEcxUnchanged)
1336	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1337
1338	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1339	{
1340	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1341	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1342	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1343	if (RT_FAILURE(rc))
1344	return rc;
1345	}
1346	}
1347	else
1348	{
1349	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1350	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1351	if (RT_FAILURE(rc))
1352	return rc;
1353	}
1354
1355	/* next */
1356	uLeaf++;
1357	}
1358	}
1359	/*
1360	* Special CPUIDs needs special handling as they don't follow the
1361	* leaf count principle used above.
1362	*/
1363	else if (s_aCandidates[iOuter].fSpecial)
1364	{
1365	bool fKeep = false;
1366	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1367	fKeep = true;
1368	else if ( uLeaf == 0x8fffffff
1369	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1370	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1371	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1372	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1373	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1374	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1375	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1376	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1377	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1378	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1379	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1380	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1381	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1382	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1383	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1384	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1385	fKeep = true;
1386	if (fKeep)
1387	{
1388	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1389	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1390	if (RT_FAILURE(rc))
1391	return rc;
1392	}
1393	}
1394	}
1395
1396	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1397	return VINF_SUCCESS;
1398	}
1399
1400
1401	/**
1402	* Determines the method the CPU uses to handle unknown CPUID leaves.
1403	*
1404	* @returns VBox status code.
1405	* @param penmUnknownMethod Where to return the method.
1406	* @param pDefUnknown Where to return default unknown values. This
1407	* will be set, even if the resulting method
1408	* doesn't actually needs it.
1409	*/
1410	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1411	{
1412	uint32_t uLastStd = ASMCpuId_EAX(0);
1413	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1414	if (!ASMIsValidExtRange(uLastExt))
1415	uLastExt = 0x80000000;
1416
1417	uint32_t auChecks[] =
1418	{
1419	uLastStd + 1,
1420	uLastStd + 5,
1421	uLastStd + 8,
1422	uLastStd + 32,
1423	uLastStd + 251,
1424	uLastExt + 1,
1425	uLastExt + 8,
1426	uLastExt + 15,
1427	uLastExt + 63,
1428	uLastExt + 255,
1429	0x7fbbffcc,
1430	0x833f7872,
1431	0xefff2353,
1432	0x35779456,
1433	0x1ef6d33e,
1434	};
1435
1436	static const uint32_t s_auValues[] =
1437	{
1438	0xa95d2156,
1439	0x00000001,
1440	0x00000002,
1441	0x00000008,
1442	0x00000000,
1443	0x55773399,
1444	0x93401769,
1445	0x12039587,
1446	};
1447
1448	/*
1449	* Simple method, all zeros.
1450	*/
1451	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1452	pDefUnknown->uEax = 0;
1453	pDefUnknown->uEbx = 0;
1454	pDefUnknown->uEcx = 0;
1455	pDefUnknown->uEdx = 0;
1456
1457	/*
1458	* Intel has been observed returning the last standard leaf.
1459	*/
1460	uint32_t auLast[4];
1461	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1462
1463	uint32_t cChecks = RT_ELEMENTS(auChecks);
1464	while (cChecks > 0)
1465	{
1466	uint32_t auCur[4];
1467	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1468	if (memcmp(auCur, auLast, sizeof(auCur)))
1469	break;
1470	cChecks--;
1471	}
1472	if (cChecks == 0)
1473	{
1474	/* Now, what happens when the input changes? Esp. ECX. */
1475	uint32_t cTotal = 0;
1476	uint32_t cSame = 0;
1477	uint32_t cLastWithEcx = 0;
1478	uint32_t cNeither = 0;
1479	uint32_t cValues = RT_ELEMENTS(s_auValues);
1480	while (cValues > 0)
1481	{
1482	uint32_t uValue = s_auValues[cValues - 1];
1483	uint32_t auLastWithEcx[4];
1484	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1485	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1486
1487	cChecks = RT_ELEMENTS(auChecks);
1488	while (cChecks > 0)
1489	{
1490	uint32_t auCur[4];
1491	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1492	if (!memcmp(auCur, auLast, sizeof(auCur)))
1493	{
1494	cSame++;
1495	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1496	cLastWithEcx++;
1497	}
1498	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1499	cLastWithEcx++;
1500	else
1501	cNeither++;
1502	cTotal++;
1503	cChecks--;
1504	}
1505	cValues--;
1506	}
1507
1508	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1509	if (cSame == cTotal)
1510	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1511	else if (cLastWithEcx == cTotal)
1512	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1513	else
1514	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1515	pDefUnknown->uEax = auLast[0];
1516	pDefUnknown->uEbx = auLast[1];
1517	pDefUnknown->uEcx = auLast[2];
1518	pDefUnknown->uEdx = auLast[3];
1519	return VINF_SUCCESS;
1520	}
1521
1522	/*
1523	* Unchanged register values?
1524	*/
1525	cChecks = RT_ELEMENTS(auChecks);
1526	while (cChecks > 0)
1527	{
1528	uint32_t const uLeaf = auChecks[cChecks - 1];
1529	uint32_t cValues = RT_ELEMENTS(s_auValues);
1530	while (cValues > 0)
1531	{
1532	uint32_t uValue = s_auValues[cValues - 1];
1533	uint32_t auCur[4];
1534	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1535	if ( auCur[0] != uLeaf
1536	\|\| auCur[1] != uValue
1537	\|\| auCur[2] != uValue
1538	\|\| auCur[3] != uValue)
1539	break;
1540	cValues--;
1541	}
1542	if (cValues != 0)
1543	break;
1544	cChecks--;
1545	}
1546	if (cChecks == 0)
1547	{
1548	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1549	return VINF_SUCCESS;
1550	}
1551
1552	/*
1553	* Just go with the simple method.
1554	*/
1555	return VINF_SUCCESS;
1556	}
1557
1558
1559	/**
1560	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1561	*
1562	* @returns Read only name string.
1563	* @param enmUnknownMethod The method to translate.
1564	*/
1565	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1566	{
1567	switch (enmUnknownMethod)
1568	{
1569	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1570	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1571	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1572	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1573
1574	case CPUMUNKNOWNCPUID_INVALID:
1575	case CPUMUNKNOWNCPUID_END:
1576	case CPUMUNKNOWNCPUID_32BIT_HACK:
1577	break;
1578	}
1579	return "Invalid-unknown-CPUID-method";
1580	}
1581
1582
1583	/**
1584	* Detect the CPU vendor give n the
1585	*
1586	* @returns The vendor.
1587	* @param uEAX EAX from CPUID(0).
1588	* @param uEBX EBX from CPUID(0).
1589	* @param uECX ECX from CPUID(0).
1590	* @param uEDX EDX from CPUID(0).
1591	*/
1592	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1593	{
1594	if (ASMIsValidStdRange(uEAX))
1595	{
1596	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1597	return CPUMCPUVENDOR_AMD;
1598
1599	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1600	return CPUMCPUVENDOR_INTEL;
1601
1602	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1603	return CPUMCPUVENDOR_VIA;
1604
1605	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1606	&& uECX == UINT32_C(0x64616574)
1607	&& uEDX == UINT32_C(0x736E4978))
1608	return CPUMCPUVENDOR_CYRIX;
1609
1610	/* "Geode by NSC", example: family 5, model 9. */
1611
1612	/** @todo detect the other buggers... */
1613	}
1614
1615	return CPUMCPUVENDOR_UNKNOWN;
1616	}
1617
1618
1619	/**
1620	* Translates a CPU vendor enum value into the corresponding string constant.
1621	*
1622	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1623	* value name. This can be useful when generating code.
1624	*
1625	* @returns Read only name string.
1626	* @param enmVendor The CPU vendor value.
1627	*/
1628	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1629	{
1630	switch (enmVendor)
1631	{
1632	case CPUMCPUVENDOR_INTEL: return "INTEL";
1633	case CPUMCPUVENDOR_AMD: return "AMD";
1634	case CPUMCPUVENDOR_VIA: return "VIA";
1635	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1636	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1637
1638	case CPUMCPUVENDOR_INVALID:
1639	case CPUMCPUVENDOR_32BIT_HACK:
1640	break;
1641	}
1642	return "Invalid-cpu-vendor";
1643	}
1644
1645
1646	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1647	{
1648	/* Could do binary search, doing linear now because I'm lazy. */
1649	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1650	while (cLeaves-- > 0)
1651	{
1652	if (pLeaf->uLeaf == uLeaf)
1653	return pLeaf;
1654	pLeaf++;
1655	}
1656	return NULL;
1657	}
1658
1659
1660	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1661	{
1662	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1663	if ( !pLeaf
1664	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1665	return pLeaf;
1666
1667	/* Linear sub-leaf search. Lazy as usual. */
1668	cLeaves -= pLeaf - paLeaves;
1669	while ( cLeaves-- > 0
1670	&& pLeaf->uLeaf == uLeaf)
1671	{
1672	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1673	return pLeaf;
1674	pLeaf++;
1675	}
1676
1677	return NULL;
1678	}
1679
1680
1681	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1682	{
1683	RT_ZERO(*pFeatures);
1684	if (cLeaves >= 2)
1685	{
1686	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1687	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1688	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1689	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1690	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1691	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1692
1693	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1694	pStd0Leaf->uEbx,
1695	pStd0Leaf->uEcx,
1696	pStd0Leaf->uEdx);
1697	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1698	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1699	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1700	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1701	pFeatures->uFamily,
1702	pFeatures->uModel,
1703	pFeatures->uStepping);
1704
1705	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1706	if (pExtLeaf8)
1707	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1708	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1709	pFeatures->cMaxPhysAddrWidth = 36;
1710	else
1711	pFeatures->cMaxPhysAddrWidth = 32;
1712
1713	/* Standard features. */
1714	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1715	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1716	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1717	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1718	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1719	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1720	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1721	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1722	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1723	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1724	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1725	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1726	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1727	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1728	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1729	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1730	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1731	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1732	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1733	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1734	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1735	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1736	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1737	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1738	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1739
1740	/* Structured extended features. */
1741	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1742	if (pSxfLeaf0)
1743	{
1744	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1745	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1746	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1747	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1748	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1749
1750	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1751	pFeatures->fIbrs = pFeatures->fIbpb;
1752	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1753	#if 0 // Disabled until IA32_ARCH_CAPABILITIES support can be tested
1754	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1755	#endif
1756	}
1757
1758	/* MWAIT/MONITOR leaf. */
1759	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1760	if (pMWaitLeaf)
1761	{
1762	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1763	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1764	}
1765
1766	/* Extended features. */
1767	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1768	if (pExtLeaf)
1769	{
1770	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1771	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1772	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1773	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1774	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1775	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1776	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1777	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1778	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1779	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1780	}
1781
1782	if ( pExtLeaf
1783	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1784	{
1785	/* AMD features. */
1786	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1787	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1788	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1789	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1790	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1791	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1792	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1793	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1794	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1795	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1796	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1797	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1798	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1799	if (pFeatures->fSvm)
1800	{
1801	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1802	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1803	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1804	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1805	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1806	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1807	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1808	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1809	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1810	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1811	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1812	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1813	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1814	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1815	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1816	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1817	}
1818	}
1819
1820	/*
1821	* Quirks.
1822	*/
1823	pFeatures->fLeakyFxSR = pExtLeaf
1824	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1825	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1826	&& pFeatures->uFamily >= 6 /* K7 and up */;
1827
1828	/*
1829	* Max extended (/FPU) state.
1830	*/
1831	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1832	if (pFeatures->fXSaveRstor)
1833	{
1834	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1835	if (pXStateLeaf0)
1836	{
1837	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1838	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1839	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1840	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1841	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1842	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1843	{
1844	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1845
1846	/* (paranoia:) */
1847	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1848	if ( pXStateLeaf1
1849	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1850	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1851	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1852	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1853	}
1854	else
1855	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1856	pFeatures->fXSaveRstor = 0);
1857	}
1858	else
1859	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1860	pFeatures->fXSaveRstor = 0);
1861	}
1862	}
1863	else
1864	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1865	return VINF_SUCCESS;
1866	}
1867
1868
1869	/*
1870	*
1871	* Init related code.
1872	* Init related code.
1873	* Init related code.
1874	*
1875	*
1876	*/
1877	#ifdef VBOX_IN_VMM
1878
1879
1880	/**
1881	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1882	*
1883	* This ignores the fSubLeafMask.
1884	*
1885	* @returns Pointer to the matching leaf, or NULL if not found.
1886	* @param paLeaves The CPUID leaves to search. This is sorted.
1887	* @param cLeaves The number of leaves in the array.
1888	* @param uLeaf The leaf to locate.
1889	* @param uSubLeaf The subleaf to locate.
1890	*/
1891	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1892	{
1893	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1894	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1895	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1896	if (iEnd)
1897	{
1898	uint32_t iBegin = 0;
1899	for (;;)
1900	{
1901	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1902	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1903	if (uNeedle < uCur)
1904	{
1905	if (i > iBegin)
1906	iEnd = i;
1907	else
1908	break;
1909	}
1910	else if (uNeedle > uCur)
1911	{
1912	if (i + 1 < iEnd)
1913	iBegin = i + 1;
1914	else
1915	break;
1916	}
1917	else
1918	return &paLeaves[i];
1919	}
1920	}
1921	return NULL;
1922	}
1923
1924
1925	/**
1926	* Loads MSR range overrides.
1927	*
1928	* This must be called before the MSR ranges are moved from the normal heap to
1929	* the hyper heap!
1930	*
1931	* @returns VBox status code (VMSetError called).
1932	* @param pVM The cross context VM structure.
1933	* @param pMsrNode The CFGM node with the MSR overrides.
1934	*/
1935	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1936	{
1937	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1938	{
1939	/*
1940	* Assemble a valid MSR range.
1941	*/
1942	CPUMMSRRANGE MsrRange;
1943	MsrRange.offCpumCpu = 0;
1944	MsrRange.fReserved = 0;
1945
1946	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1947	if (RT_FAILURE(rc))
1948	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1949
1950	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1951	if (RT_FAILURE(rc))
1952	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1953	MsrRange.szName, rc);
1954
1955	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1956	if (RT_FAILURE(rc))
1957	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1958	MsrRange.szName, rc);
1959
1960	char szType[32];
1961	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1962	if (RT_FAILURE(rc))
1963	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1964	MsrRange.szName, rc);
1965	if (!RTStrICmp(szType, "FixedValue"))
1966	{
1967	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1968	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1969
1970	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1971	if (RT_FAILURE(rc))
1972	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1973	MsrRange.szName, rc);
1974
1975	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1976	if (RT_FAILURE(rc))
1977	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1978	MsrRange.szName, rc);
1979
1980	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1981	if (RT_FAILURE(rc))
1982	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1983	MsrRange.szName, rc);
1984	}
1985	else
1986	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1987	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1988
1989	/*
1990	* Insert the range into the table (replaces/splits/shrinks existing
1991	* MSR ranges).
1992	*/
1993	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1994	&MsrRange);
1995	if (RT_FAILURE(rc))
1996	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
1997	}
1998
1999	return VINF_SUCCESS;
2000	}
2001
2002
2003	/**
2004	* Loads CPUID leaf overrides.
2005	*
2006	* This must be called before the CPUID leaves are moved from the normal
2007	* heap to the hyper heap!
2008	*
2009	* @returns VBox status code (VMSetError called).
2010	* @param pVM The cross context VM structure.
2011	* @param pParentNode The CFGM node with the CPUID leaves.
2012	* @param pszLabel How to label the overrides we're loading.
2013	*/
2014	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2015	{
2016	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2017	{
2018	/*
2019	* Get the leaf and subleaf numbers.
2020	*/
2021	char szName[128];
2022	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2023	if (RT_FAILURE(rc))
2024	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2025
2026	/* The leaf number is either specified directly or thru the node name. */
2027	uint32_t uLeaf;
2028	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2029	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2030	{
2031	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2032	if (rc != VINF_SUCCESS)
2033	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2034	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2035	}
2036	else if (RT_FAILURE(rc))
2037	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2038	pszLabel, szName, rc);
2039
2040	uint32_t uSubLeaf;
2041	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2042	if (RT_FAILURE(rc))
2043	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2044	pszLabel, szName, rc);
2045
2046	uint32_t fSubLeafMask;
2047	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2048	if (RT_FAILURE(rc))
2049	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2050	pszLabel, szName, rc);
2051
2052	/*
2053	* Look up the specified leaf, since the output register values
2054	* defaults to any existing values. This allows overriding a single
2055	* register, without needing to know the other values.
2056	*/
2057	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2058	CPUMCPUIDLEAF Leaf;
2059	if (pLeaf)
2060	Leaf = *pLeaf;
2061	else
2062	RT_ZERO(Leaf);
2063	Leaf.uLeaf = uLeaf;
2064	Leaf.uSubLeaf = uSubLeaf;
2065	Leaf.fSubLeafMask = fSubLeafMask;
2066
2067	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2068	if (RT_FAILURE(rc))
2069	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2070	pszLabel, szName, rc);
2071	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2072	if (RT_FAILURE(rc))
2073	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2074	pszLabel, szName, rc);
2075	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2076	if (RT_FAILURE(rc))
2077	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2078	pszLabel, szName, rc);
2079	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2080	if (RT_FAILURE(rc))
2081	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2082	pszLabel, szName, rc);
2083
2084	/*
2085	* Insert the leaf into the table (replaces existing ones).
2086	*/
2087	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2088	&Leaf);
2089	if (RT_FAILURE(rc))
2090	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2091	}
2092
2093	return VINF_SUCCESS;
2094	}
2095
2096
2097
2098	/**
2099	* Fetches overrides for a CPUID leaf.
2100	*
2101	* @returns VBox status code.
2102	* @param pLeaf The leaf to load the overrides into.
2103	* @param pCfgNode The CFGM node containing the overrides
2104	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2105	* @param iLeaf The CPUID leaf number.
2106	*/
2107	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2108	{
2109	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2110	if (pLeafNode)
2111	{
2112	uint32_t u32;
2113	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2114	if (RT_SUCCESS(rc))
2115	pLeaf->uEax = u32;
2116	else
2117	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2118
2119	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2120	if (RT_SUCCESS(rc))
2121	pLeaf->uEbx = u32;
2122	else
2123	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2124
2125	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2126	if (RT_SUCCESS(rc))
2127	pLeaf->uEcx = u32;
2128	else
2129	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2130
2131	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2132	if (RT_SUCCESS(rc))
2133	pLeaf->uEdx = u32;
2134	else
2135	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2136
2137	}
2138	return VINF_SUCCESS;
2139	}
2140
2141
2142	/**
2143	* Load the overrides for a set of CPUID leaves.
2144	*
2145	* @returns VBox status code.
2146	* @param paLeaves The leaf array.
2147	* @param cLeaves The number of leaves.
2148	* @param uStart The start leaf number.
2149	* @param pCfgNode The CFGM node containing the overrides
2150	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2151	*/
2152	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2153	{
2154	for (uint32_t i = 0; i < cLeaves; i++)
2155	{
2156	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2157	if (RT_FAILURE(rc))
2158	return rc;
2159	}
2160
2161	return VINF_SUCCESS;
2162	}
2163
2164
2165	/**
2166	* Installs the CPUID leaves and explods the data into structures like
2167	* GuestFeatures and CPUMCTX::aoffXState.
2168	*
2169	* @returns VBox status code.
2170	* @param pVM The cross context VM structure.
2171	* @param pCpum The CPUM part of @a VM.
2172	* @param paLeaves The leaves. These will be copied (but not freed).
2173	* @param cLeaves The number of leaves.
2174	*/
2175	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
2176	{
2177	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2178
2179	/*
2180	* Install the CPUID information.
2181	*/
2182	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2183	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2184
2185	AssertLogRelRCReturn(rc, rc);
2186	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2187	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2188	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2189	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2190	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2191
2192	/*
2193	* Update the default CPUID leaf if necessary.
2194	*/
2195	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2196	{
2197	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2198	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2199	{
2200	/* We don't use CPUID(0).eax here because of the NT hack that only
2201	changes that value without actually removing any leaves. */
2202	uint32_t i = 0;
2203	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2204	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2205	{
2206	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2207	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2208	i++;
2209	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2210	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2211	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2212	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2213	}
2214	break;
2215	}
2216	default:
2217	break;
2218	}
2219
2220	/*
2221	* Explode the guest CPU features.
2222	*/
2223	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
2224	AssertLogRelRCReturn(rc, rc);
2225
2226	/*
2227	* Adjust the scalable bus frequency according to the CPUID information
2228	* we're now using.
2229	*/
2230	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2231	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2232	? UINT64_C(100000000) /* 100MHz */
2233	: UINT64_C(133333333); /* 133MHz */
2234
2235	/*
2236	* Populate the legacy arrays. Currently used for everything, later only
2237	* for patch manager.
2238	*/
2239	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2240	{
2241	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2242	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2243	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2244	};
2245	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2246	{
2247	uint32_t cLeft = aOldRanges[i].cCpuIds;
2248	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2249	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2250	while (cLeft-- > 0)
2251	{
2252	uLeaf--;
2253	pLegacyLeaf--;
2254
2255	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2256	if (pLeaf)
2257	{
2258	pLegacyLeaf->uEax = pLeaf->uEax;
2259	pLegacyLeaf->uEbx = pLeaf->uEbx;
2260	pLegacyLeaf->uEcx = pLeaf->uEcx;
2261	pLegacyLeaf->uEdx = pLeaf->uEdx;
2262	}
2263	else
2264	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2265	}
2266	}
2267
2268	/*
2269	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2270	*/
2271	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2272	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2273	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2274	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2275	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2276	{
2277	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2278	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2279	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2280	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2281	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2282	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2283	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2284	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2285	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2286	pCpum->GuestFeatures.cbMaxExtendedState),
2287	VERR_CPUM_IPE_1);
2288	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2289	}
2290	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2291
2292	/* Copy the CPU #0 data to the other CPUs. */
2293	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2294	{
2295	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2296	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2297	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2298	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2299	}
2300
2301	return VINF_SUCCESS;
2302	}
2303
2304
2305	/** @name Instruction Set Extension Options
2306	* @{ */
2307	/** Configuration option type (extended boolean, really). */
2308	typedef uint8_t CPUMISAEXTCFG;
2309	/** Always disable the extension. */
2310	#define CPUMISAEXTCFG_DISABLED false
2311	/** Enable the extension if it's supported by the host CPU. */
2312	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2313	/** Enable the extension if it's supported by the host CPU, but don't let
2314	* the portable CPUID feature disable it. */
2315	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2316	/** Always enable the extension. */
2317	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2318	/** @} */
2319
2320	/**
2321	* CPUID Configuration (from CFGM).
2322	*
2323	* @remarks The members aren't document since we would only be duplicating the
2324	* \@cfgm entries in cpumR3CpuIdReadConfig.
2325	*/
2326	typedef struct CPUMCPUIDCONFIG
2327	{
2328	bool fNt4LeafLimit;
2329	bool fInvariantTsc;
2330	bool fForceVme;
2331	bool fNestedHWVirt;
2332
2333	CPUMISAEXTCFG enmCmpXchg16b;
2334	CPUMISAEXTCFG enmMonitor;
2335	CPUMISAEXTCFG enmMWaitExtensions;
2336	CPUMISAEXTCFG enmSse41;
2337	CPUMISAEXTCFG enmSse42;
2338	CPUMISAEXTCFG enmAvx;
2339	CPUMISAEXTCFG enmAvx2;
2340	CPUMISAEXTCFG enmXSave;
2341	CPUMISAEXTCFG enmAesNi;
2342	CPUMISAEXTCFG enmPClMul;
2343	CPUMISAEXTCFG enmPopCnt;
2344	CPUMISAEXTCFG enmMovBe;
2345	CPUMISAEXTCFG enmRdRand;
2346	CPUMISAEXTCFG enmRdSeed;
2347	CPUMISAEXTCFG enmCLFlushOpt;
2348	CPUMISAEXTCFG enmFsGsBase;
2349	CPUMISAEXTCFG enmPcid;
2350	CPUMISAEXTCFG enmInvpcid;
2351
2352	CPUMISAEXTCFG enmAbm;
2353	CPUMISAEXTCFG enmSse4A;
2354	CPUMISAEXTCFG enmMisAlnSse;
2355	CPUMISAEXTCFG enm3dNowPrf;
2356	CPUMISAEXTCFG enmAmdExtMmx;
2357
2358	uint32_t uMaxStdLeaf;
2359	uint32_t uMaxExtLeaf;
2360	uint32_t uMaxCentaurLeaf;
2361	uint32_t uMaxIntelFamilyModelStep;
2362	char szCpuName[128];
2363	} CPUMCPUIDCONFIG;
2364	/** Pointer to CPUID config (from CFGM). */
2365	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2366
2367
2368	/**
2369	* Mini CPU selection support for making Mac OS X happy.
2370	*
2371	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2372	*
2373	* @param pCpum The CPUM instance data.
2374	* @param pConfig The CPUID configuration we've read from CFGM.
2375	*/
2376	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2377	{
2378	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2379	{
2380	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2381	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2382	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2383	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2384	0);
2385	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2386	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2387	{
2388	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2389	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2390	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2391	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2392	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2393	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2394	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2395	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2396	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2397	pStdFeatureLeaf->uEax = uNew;
2398	}
2399	}
2400	}
2401
2402
2403
2404	/**
2405	* Limit it the number of entries, zapping the remainder.
2406	*
2407	* The limits are masking off stuff about power saving and similar, this
2408	* is perhaps a bit crudely done as there is probably some relatively harmless
2409	* info too in these leaves (like words about having a constant TSC).
2410	*
2411	* @param pCpum The CPUM instance data.
2412	* @param pConfig The CPUID configuration we've read from CFGM.
2413	*/
2414	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2415	{
2416	/*
2417	* Standard leaves.
2418	*/
2419	uint32_t uSubLeaf = 0;
2420	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2421	if (pCurLeaf)
2422	{
2423	uint32_t uLimit = pCurLeaf->uEax;
2424	if (uLimit <= UINT32_C(0x000fffff))
2425	{
2426	if (uLimit > pConfig->uMaxStdLeaf)
2427	{
2428	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2429	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2430	uLimit + 1, UINT32_C(0x000fffff));
2431	}
2432
2433	/* NT4 hack, no zapping of extra leaves here. */
2434	if (pConfig->fNt4LeafLimit && uLimit > 3)
2435	pCurLeaf->uEax = uLimit = 3;
2436
2437	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2438	pCurLeaf->uEax = uLimit;
2439	}
2440	else
2441	{
2442	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2443	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2444	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2445	}
2446	}
2447
2448	/*
2449	* Extended leaves.
2450	*/
2451	uSubLeaf = 0;
2452	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2453	if (pCurLeaf)
2454	{
2455	uint32_t uLimit = pCurLeaf->uEax;
2456	if ( uLimit >= UINT32_C(0x80000000)
2457	&& uLimit <= UINT32_C(0x800fffff))
2458	{
2459	if (uLimit > pConfig->uMaxExtLeaf)
2460	{
2461	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2462	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2463	uLimit + 1, UINT32_C(0x800fffff));
2464	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2465	pCurLeaf->uEax = uLimit;
2466	}
2467	}
2468	else
2469	{
2470	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2471	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2472	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2473	}
2474	}
2475
2476	/*
2477	* Centaur leaves (VIA).
2478	*/
2479	uSubLeaf = 0;
2480	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2481	if (pCurLeaf)
2482	{
2483	uint32_t uLimit = pCurLeaf->uEax;
2484	if ( uLimit >= UINT32_C(0xc0000000)
2485	&& uLimit <= UINT32_C(0xc00fffff))
2486	{
2487	if (uLimit > pConfig->uMaxCentaurLeaf)
2488	{
2489	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2490	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2491	uLimit + 1, UINT32_C(0xcfffffff));
2492	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2493	pCurLeaf->uEax = uLimit;
2494	}
2495	}
2496	else
2497	{
2498	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2499	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2500	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2501	}
2502	}
2503	}
2504
2505
2506	/**
2507	* Clears a CPUID leaf and all sub-leaves (to zero).
2508	*
2509	* @param pCpum The CPUM instance data.
2510	* @param uLeaf The leaf to clear.
2511	*/
2512	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2513	{
2514	uint32_t uSubLeaf = 0;
2515	PCPUMCPUIDLEAF pCurLeaf;
2516	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2517	{
2518	pCurLeaf->uEax = 0;
2519	pCurLeaf->uEbx = 0;
2520	pCurLeaf->uEcx = 0;
2521	pCurLeaf->uEdx = 0;
2522	uSubLeaf++;
2523	}
2524	}
2525
2526
2527	/**
2528	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2529	* the given leaf.
2530	*
2531	* @returns pLeaf.
2532	* @param pCpum The CPUM instance data.
2533	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2534	*/
2535	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2536	{
2537	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2538	if (pLeaf->fSubLeafMask != 0)
2539	{
2540	/*
2541	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2542	* Log everything while we're at it.
2543	*/
2544	LogRel(("CPUM:\n"
2545	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2546	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2547	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2548	for (;;)
2549	{
2550	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2551	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2552	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2553	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2554	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2555	break;
2556	pSubLeaf++;
2557	}
2558	LogRel(("CPUM:\n"));
2559
2560	/*
2561	* Remove the offending sub-leaves.
2562	*/
2563	if (pSubLeaf != pLeaf)
2564	{
2565	if (pSubLeaf != pLast)
2566	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2567	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2568	}
2569
2570	/*
2571	* Convert the first sub-leaf into a single leaf.
2572	*/
2573	pLeaf->uSubLeaf = 0;
2574	pLeaf->fSubLeafMask = 0;
2575	}
2576	return pLeaf;
2577	}
2578
2579
2580	/**
2581	* Sanitizes and adjust the CPUID leaves.
2582	*
2583	* Drop features that aren't virtualized (or virtualizable). Adjust information
2584	* and capabilities to fit the virtualized hardware. Remove information the
2585	* guest shouldn't have (because it's wrong in the virtual world or because it
2586	* gives away host details) or that we don't have documentation for and no idea
2587	* what means.
2588	*
2589	* @returns VBox status code.
2590	* @param pVM The cross context VM structure (for cCpus).
2591	* @param pCpum The CPUM instance data.
2592	* @param pConfig The CPUID configuration we've read from CFGM.
2593	*/
2594	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2595	{
2596	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2597	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2598	{ \
2599	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2600	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2601	}
2602	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2603	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2604	{ \
2605	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2606	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2607	}
2608	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2609	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2610	&& ((a_pLeafReg) & (fBitMask)) \
2611	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2612	{ \
2613	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2614	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2615	}
2616	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2617
2618	/* Cpuid 1:
2619	* EAX: CPU model, family and stepping.
2620	*
2621	* ECX + EDX: Supported features. Only report features we can support.
2622	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2623	* options may require adjusting (i.e. stripping what was enabled).
2624	*
2625	* EBX: Branding, CLFLUSH line size, logical processors per package and
2626	* initial APIC ID.
2627	*/
2628	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2629	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2630	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2631
2632	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2633	\| X86_CPUID_FEATURE_EDX_VME
2634	\| X86_CPUID_FEATURE_EDX_DE
2635	\| X86_CPUID_FEATURE_EDX_PSE
2636	\| X86_CPUID_FEATURE_EDX_TSC
2637	\| X86_CPUID_FEATURE_EDX_MSR
2638	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2639	\| X86_CPUID_FEATURE_EDX_MCE
2640	\| X86_CPUID_FEATURE_EDX_CX8
2641	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2642	//\| RT_BIT_32(10) - not defined
2643	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2644	//\| X86_CPUID_FEATURE_EDX_SEP
2645	\| X86_CPUID_FEATURE_EDX_MTRR
2646	\| X86_CPUID_FEATURE_EDX_PGE
2647	\| X86_CPUID_FEATURE_EDX_MCA
2648	\| X86_CPUID_FEATURE_EDX_CMOV
2649	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2650	\| X86_CPUID_FEATURE_EDX_PSE36
2651	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2652	\| X86_CPUID_FEATURE_EDX_CLFSH
2653	//\| RT_BIT_32(20) - not defined
2654	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2655	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2656	\| X86_CPUID_FEATURE_EDX_MMX
2657	\| X86_CPUID_FEATURE_EDX_FXSR
2658	\| X86_CPUID_FEATURE_EDX_SSE
2659	\| X86_CPUID_FEATURE_EDX_SSE2
2660	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2661	\| X86_CPUID_FEATURE_EDX_HTT
2662	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2663	//\| RT_BIT_32(30) - not defined
2664	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2665	;
2666	pStdFeatureLeaf->uEcx &= 0
2667	\| X86_CPUID_FEATURE_ECX_SSE3
2668	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2669	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2670	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2671	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2672	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2673	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized yet.
2674	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2675	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2676	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2677	\| X86_CPUID_FEATURE_ECX_SSSE3
2678	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2679	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2680	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2681	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2682	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2683	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2684	\| (pConfig->enmPcid ? X86_CPUID_FEATURE_ECX_PCID : 0)
2685	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2686	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2687	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2688	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2689	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2690	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2691	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2692	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2693	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2694	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2695	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2696	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2697	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2698	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2699	;
2700
2701	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2702	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2703	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2704	{
2705	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2706	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2707	}
2708
2709	if (pCpum->u8PortableCpuIdLevel > 0)
2710	{
2711	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2712	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2713	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2714	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2715	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2716	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2717	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2718	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2719	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2720	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2721	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2722	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2723	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2724	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2725	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2726	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2727	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2728	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2729	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2730
2731	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2732	\| X86_CPUID_FEATURE_EDX_PSN
2733	\| X86_CPUID_FEATURE_EDX_DS
2734	\| X86_CPUID_FEATURE_EDX_ACPI
2735	\| X86_CPUID_FEATURE_EDX_SS
2736	\| X86_CPUID_FEATURE_EDX_TM
2737	\| X86_CPUID_FEATURE_EDX_PBE
2738	)));
2739	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2740	\| X86_CPUID_FEATURE_ECX_CPLDS
2741	\| X86_CPUID_FEATURE_ECX_VMX
2742	\| X86_CPUID_FEATURE_ECX_SMX
2743	\| X86_CPUID_FEATURE_ECX_EST
2744	\| X86_CPUID_FEATURE_ECX_TM2
2745	\| X86_CPUID_FEATURE_ECX_CNTXID
2746	\| X86_CPUID_FEATURE_ECX_FMA
2747	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2748	\| X86_CPUID_FEATURE_ECX_PDCM
2749	\| X86_CPUID_FEATURE_ECX_DCA
2750	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2751	)));
2752	}
2753
2754	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2755	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2756
2757	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2758	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2759	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2760	*/
2761	#ifdef VBOX_WITH_MULTI_CORE
2762	if (pVM->cCpus > 1)
2763	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2764	#endif
2765	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2766	{
2767	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2768	core times the number of CPU cores per processor */
2769	#ifdef VBOX_WITH_MULTI_CORE
2770	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2771	#else
2772	/* Single logical processor in a package. */
2773	pStdFeatureLeaf->uEbx \|= (1 << 16);
2774	#endif
2775	}
2776
2777	uint32_t uMicrocodeRev;
2778	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2779	if (RT_SUCCESS(rc))
2780	{
2781	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2782	}
2783	else
2784	{
2785	uMicrocodeRev = 0;
2786	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2787	}
2788
2789	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2790	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2791	*/
2792	if ( (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen)
2793	&& uMicrocodeRev < 0x8001126
2794	&& !pConfig->fForceVme)
2795	{
2796	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2797	LogRel(("CPUM: Zen VME workaround engaged\n"));
2798	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2799	}
2800
2801	/* Force standard feature bits. */
2802	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2803	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2804	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2805	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2806	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2807	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2808	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2809	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2810	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2811	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2812	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2813	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2814	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2815	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2816	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2817	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2818	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2819	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2820	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2821	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2822	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2823	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2824
2825	pStdFeatureLeaf = NULL; /* Must refetch! */
2826
2827	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2828	* AMD:
2829	* EAX: CPU model, family and stepping.
2830	*
2831	* ECX + EDX: Supported features. Only report features we can support.
2832	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2833	* options may require adjusting (i.e. stripping what was enabled).
2834	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2835	*
2836	* EBX: Branding ID and package type (or reserved).
2837	*
2838	* Intel and probably most others:
2839	* EAX: 0
2840	* EBX: 0
2841	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2842	*/
2843	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2844	if (pExtFeatureLeaf)
2845	{
2846	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2847
2848	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2849	\| X86_CPUID_AMD_FEATURE_EDX_VME
2850	\| X86_CPUID_AMD_FEATURE_EDX_DE
2851	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2852	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2853	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2854	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2855	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2856	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2857	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2858	//\| RT_BIT_32(10) - reserved
2859	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2860	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2861	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2862	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2863	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2864	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2865	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2866	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2867	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2868	//\| RT_BIT_32(18) - reserved
2869	//\| RT_BIT_32(19) - reserved
2870	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2871	//\| RT_BIT_32(21) - reserved
2872	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2873	\| X86_CPUID_AMD_FEATURE_EDX_MMX
2874	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
2875	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
2876	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2877	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2878	//\| RT_BIT_32(28) - reserved
2879	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2880	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2881	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
2882	;
2883	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2884	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2885	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
2886	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2887	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
2888	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2889	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2890	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2891	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2892	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2893	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2894	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
2895	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
2896	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2897	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
2898	//\| RT_BIT_32(14) - reserved
2899	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2900	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2901	//\| RT_BIT_32(17) - reserved
2902	//\| RT_BIT_32(18) - reserved
2903	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2904	//\| RT_BIT_32(20) - reserved
2905	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2906	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2907	//\| RT_BIT_32(23) - reserved
2908	//\| RT_BIT_32(24) - reserved
2909	//\| RT_BIT_32(25) - reserved
2910	//\| RT_BIT_32(26) - reserved
2911	//\| RT_BIT_32(27) - reserved
2912	//\| RT_BIT_32(28) - reserved
2913	//\| RT_BIT_32(29) - reserved
2914	//\| RT_BIT_32(30) - reserved
2915	//\| RT_BIT_32(31) - reserved
2916	;
2917	#ifdef VBOX_WITH_MULTI_CORE
2918	if ( pVM->cCpus > 1
2919	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2920	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2921	#endif
2922
2923	if (pCpum->u8PortableCpuIdLevel > 0)
2924	{
2925	CPUMISAEXTCFG enmSvm = pConfig->fNestedHWVirt ? CPUMISAEXTCFG_ENABLED_SUPPORTED : CPUMISAEXTCFG_DISABLED;
2926	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2927	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM, enmSvm);
2928	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2929	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2930	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2931	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2932	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2933	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2934	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2935	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2936	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2937	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2938	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2939	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2940	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2941	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2942
2943	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2944	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2945	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2946	\| X86_CPUID_AMD_FEATURE_ECX_IBS
2947	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2948	\| X86_CPUID_AMD_FEATURE_ECX_WDT
2949	\| X86_CPUID_AMD_FEATURE_ECX_LWP
2950	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
2951	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2952	\| UINT32_C(0xff964000)
2953	)));
2954	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2955	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2956	\| RT_BIT(18)
2957	\| RT_BIT(19)
2958	\| RT_BIT(21)
2959	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2960	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2961	\| RT_BIT(28)
2962	)));
2963	}
2964
2965	/* Force extended feature bits. */
2966	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2967	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
2968	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2969	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2970	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2971	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2972	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2973	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2974	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2975	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2976	}
2977	pExtFeatureLeaf = NULL; /* Must refetch! */
2978
2979
2980	/* Cpuid 2:
2981	* Intel: (Nondeterministic) Cache and TLB information
2982	* AMD: Reserved
2983	* VIA: Reserved
2984	* Safe to expose.
2985	*/
2986	uint32_t uSubLeaf = 0;
2987	PCPUMCPUIDLEAF pCurLeaf;
2988	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2989	{
2990	if ((pCurLeaf->uEax & 0xff) > 1)
2991	{
2992	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2993	pCurLeaf->uEax &= UINT32_C(0xffffff01);
2994	}
2995	uSubLeaf++;
2996	}
2997
2998	/* Cpuid 3:
2999	* Intel: EAX, EBX - reserved (transmeta uses these)
3000	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3001	* AMD: Reserved
3002	* VIA: Reserved
3003	* Safe to expose
3004	*/
3005	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3006	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3007	{
3008	uSubLeaf = 0;
3009	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3010	{
3011	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3012	if (pCpum->u8PortableCpuIdLevel > 0)
3013	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3014	uSubLeaf++;
3015	}
3016	}
3017
3018	/* Cpuid 4 + ECX:
3019	* Intel: Deterministic Cache Parameters Leaf.
3020	* AMD: Reserved
3021	* VIA: Reserved
3022	* Safe to expose, except for EAX:
3023	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3024	* Bits 31-26: Maximum number of processor cores in this physical package**
3025	* Note: These SMP values are constant regardless of ECX
3026	*/
3027	uSubLeaf = 0;
3028	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3029	{
3030	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3031	#ifdef VBOX_WITH_MULTI_CORE
3032	if ( pVM->cCpus > 1
3033	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3034	{
3035	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3036	/* One logical processor with possibly multiple cores. */
3037	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3038	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3039	}
3040	#endif
3041	uSubLeaf++;
3042	}
3043
3044	/* Cpuid 5: Monitor/mwait Leaf
3045	* Intel: ECX, EDX - reserved
3046	* EAX, EBX - Smallest and largest monitor line size
3047	* AMD: EDX - reserved
3048	* EAX, EBX - Smallest and largest monitor line size
3049	* ECX - extensions (ignored for now)
3050	* VIA: Reserved
3051	* Safe to expose
3052	*/
3053	uSubLeaf = 0;
3054	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3055	{
3056	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3057	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3058	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3059
3060	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3061	if (pConfig->enmMWaitExtensions)
3062	{
3063	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3064	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3065	it shall be part of our power management virtualization model */
3066	#if 0
3067	/* MWAIT sub C-states */
3068	pCurLeaf->uEdx =
3069	(0 << 0) /* 0 in C0 */ \|
3070	(2 << 4) /* 2 in C1 */ \|
3071	(2 << 8) /* 2 in C2 */ \|
3072	(2 << 12) /* 2 in C3 */ \|
3073	(0 << 16) /* 0 in C4 */
3074	;
3075	#endif
3076	}
3077	else
3078	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3079	uSubLeaf++;
3080	}
3081
3082	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3083	* Intel: Various stuff.
3084	* AMD: EAX, EBX, EDX - reserved.
3085	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3086	* present. Same as intel.
3087	* VIA: ??
3088	*
3089	* We clear everything here for now.
3090	*/
3091	cpumR3CpuIdZeroLeaf(pCpum, 6);
3092
3093	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3094	* EAX: Number of sub leaves.
3095	* EBX+ECX+EDX: Feature flags
3096	*
3097	* We only have documentation for one sub-leaf, so clear all other (no need
3098	* to remove them as such, just set them to zero).
3099	*
3100	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3101	* options may require adjusting (i.e. stripping what was enabled).
3102	*/
3103	uSubLeaf = 0;
3104	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3105	{
3106	switch (uSubLeaf)
3107	{
3108	case 0:
3109	{
3110	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3111	pCurLeaf->uEbx &= 0
3112	\| (pConfig->enmFsGsBase ? X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE : 0)
3113	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3114	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3115	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3116	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3117	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3118	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3119	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3120	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3121	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3122	\| (pConfig->enmInvpcid ? X86_CPUID_STEXT_FEATURE_EBX_INVPCID : 0)
3123	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3124	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3125	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3126	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3127	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3128	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3129	//\| RT_BIT(17) - reserved
3130	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3131	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3132	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3133	//\| RT_BIT(21) - reserved
3134	//\| RT_BIT(22) - reserved
3135	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3136	//\| RT_BIT(24) - reserved
3137	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3138	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3139	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3140	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3141	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3142	//\| RT_BIT(30) - reserved
3143	//\| RT_BIT(31) - reserved
3144	;
3145	pCurLeaf->uEcx &= 0
3146	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3147	;
3148	pCurLeaf->uEdx &= 0
3149	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3150	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3151	//\| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT(29)
3152	;
3153
3154	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3155	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3156	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3157	{
3158	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3159	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3160	}
3161
3162	if (pCpum->u8PortableCpuIdLevel > 0)
3163	{
3164	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3165	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3166	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3167	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3168	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3169	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3170	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3171	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3172	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3173	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3174	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3175	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3176	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3177	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3178	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3179	}
3180
3181	/* Force standard feature bits. */
3182	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3183	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3184	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3185	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3186	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3187	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3188	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3189	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3190	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3191	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3192	break;
3193	}
3194
3195	default:
3196	/* Invalid index, all values are zero. */
3197	pCurLeaf->uEax = 0;
3198	pCurLeaf->uEbx = 0;
3199	pCurLeaf->uEcx = 0;
3200	pCurLeaf->uEdx = 0;
3201	break;
3202	}
3203	uSubLeaf++;
3204	}
3205
3206	/* Cpuid 8: Marked as reserved by Intel and AMD.
3207	* We zero this since we don't know what it may have been used for.
3208	*/
3209	cpumR3CpuIdZeroLeaf(pCpum, 8);
3210
3211	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3212	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3213	* EBX, ECX, EDX - reserved.
3214	* AMD: Reserved
3215	* VIA: ??
3216	*
3217	* We zero this.
3218	*/
3219	cpumR3CpuIdZeroLeaf(pCpum, 9);
3220
3221	/* Cpuid 0xa: Architectural Performance Monitor Features
3222	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3223	* EBX, ECX, EDX - reserved.
3224	* AMD: Reserved
3225	* VIA: ??
3226	*
3227	* We zero this, for now at least.
3228	*/
3229	cpumR3CpuIdZeroLeaf(pCpum, 10);
3230
3231	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3232	* Intel: EAX - APCI ID shift right for next level.
3233	* EBX - Factory configured cores/threads at this level.
3234	* ECX - Level number (same as input) and level type (1,2,0).
3235	* EDX - Extended initial APIC ID.
3236	* AMD: Reserved
3237	* VIA: ??
3238	*/
3239	uSubLeaf = 0;
3240	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3241	{
3242	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3243	{
3244	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3245	if (bLevelType == 1)
3246	{
3247	/* Thread level - we don't do threads at the moment. */
3248	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3249	pCurLeaf->uEbx = 1;
3250	}
3251	else if (bLevelType == 2)
3252	{
3253	/* Core level. */
3254	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3255	#ifdef VBOX_WITH_MULTI_CORE
3256	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3257	pCurLeaf->uEax++;
3258	#endif
3259	pCurLeaf->uEbx = pVM->cCpus;
3260	}
3261	else
3262	{
3263	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3264	pCurLeaf->uEax = 0;
3265	pCurLeaf->uEbx = 0;
3266	pCurLeaf->uEcx = 0;
3267	}
3268	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3269	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3270	}
3271	else
3272	{
3273	pCurLeaf->uEax = 0;
3274	pCurLeaf->uEbx = 0;
3275	pCurLeaf->uEcx = 0;
3276	pCurLeaf->uEdx = 0;
3277	}
3278	uSubLeaf++;
3279	}
3280
3281	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3282	* We zero this since we don't know what it may have been used for.
3283	*/
3284	cpumR3CpuIdZeroLeaf(pCpum, 12);
3285
3286	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3287	* ECX=0: EAX - Valid bits in XCR0[31:0].
3288	* EBX - Maximum state size as per current XCR0 value.
3289	* ECX - Maximum state size for all supported features.
3290	* EDX - Valid bits in XCR0[63:32].
3291	* ECX=1: EAX - Various X-features.
3292	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3293	* ECX - Valid bits in IA32_XSS[31:0].
3294	* EDX - Valid bits in IA32_XSS[63:32].
3295	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3296	* if the bit invalid all four registers are set to zero.
3297	* EAX - The state size for this feature.
3298	* EBX - The state byte offset of this feature.
3299	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3300	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3301	*
3302	* Clear them all as we don't currently implement extended CPU state.
3303	*/
3304	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3305	uint64_t fGuestXcr0Mask = 0;
3306	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3307	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3308	{
3309	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3310	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3311	fGuestXcr0Mask \|= XSAVE_C_YMM;
3312	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3313	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3314	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3315	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3316
3317	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3318	}
3319	pStdFeatureLeaf = NULL;
3320	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3321
3322	/* Work the sub-leaves. */
3323	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3324	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3325	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3326	{
3327	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3328	if (pCurLeaf)
3329	{
3330	if (fGuestXcr0Mask)
3331	{
3332	switch (uSubLeaf)
3333	{
3334	case 0:
3335	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3336	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3337	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3338	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3339	VERR_CPUM_IPE_1);
3340	cbXSaveMaxActual = pCurLeaf->uEcx;
3341	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3342	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3343	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3344	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3345	VERR_CPUM_IPE_2);
3346	continue;
3347	case 1:
3348	pCurLeaf->uEax &= 0;
3349	pCurLeaf->uEcx &= 0;
3350	pCurLeaf->uEdx &= 0;
3351	/** @todo what about checking ebx? */
3352	continue;
3353	default:
3354	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3355	{
3356	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3357	&& pCurLeaf->uEax > 0
3358	&& pCurLeaf->uEbx < cbXSaveMaxActual
3359	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3360	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3361	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3362	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3363	VERR_CPUM_IPE_2);
3364	AssertLogRel(!(pCurLeaf->uEcx & 1));
3365	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3366	pCurLeaf->uEdx = 0; /* it's reserved... */
3367	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3368	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3369	continue;
3370	}
3371	break;
3372	}
3373	}
3374
3375	/* Clear the leaf. */
3376	pCurLeaf->uEax = 0;
3377	pCurLeaf->uEbx = 0;
3378	pCurLeaf->uEcx = 0;
3379	pCurLeaf->uEdx = 0;
3380	}
3381	}
3382
3383	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3384	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3385	{
3386	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3387	if (pCurLeaf)
3388	{
3389	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3390	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3391	pCurLeaf->uEbx = cbXSaveMaxReport;
3392	pCurLeaf->uEcx = cbXSaveMaxReport;
3393	}
3394	}
3395
3396	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3397	* We zero this since we don't know what it may have been used for.
3398	*/
3399	cpumR3CpuIdZeroLeaf(pCpum, 14);
3400
3401	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3402	* also known as Intel Resource Director Technology (RDT) Monitoring
3403	* We zero this as we don't currently virtualize PQM.
3404	*/
3405	cpumR3CpuIdZeroLeaf(pCpum, 15);
3406
3407	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3408	* also known as Intel Resource Director Technology (RDT) Allocation
3409	* We zero this as we don't currently virtualize PQE.
3410	*/
3411	cpumR3CpuIdZeroLeaf(pCpum, 16);
3412
3413	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3414	* We zero this since we don't know what it may have been used for.
3415	*/
3416	cpumR3CpuIdZeroLeaf(pCpum, 17);
3417
3418	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3419	* We zero this as we don't currently virtualize this.
3420	*/
3421	cpumR3CpuIdZeroLeaf(pCpum, 18);
3422
3423	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3424	* We zero this since we don't know what it may have been used for.
3425	*/
3426	cpumR3CpuIdZeroLeaf(pCpum, 19);
3427
3428	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3429	* We zero this as we don't currently virtualize this.
3430	*/
3431	cpumR3CpuIdZeroLeaf(pCpum, 20);
3432
3433	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3434	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3435	* EAX - denominator (unsigned).
3436	* EBX - numerator (unsigned).
3437	* ECX, EDX - reserved.
3438	* AMD: Reserved / undefined / not implemented.
3439	* VIA: Reserved / undefined / not implemented.
3440	* We zero this as we don't currently virtualize this.
3441	*/
3442	cpumR3CpuIdZeroLeaf(pCpum, 21);
3443
3444	/* Cpuid 0x16: Processor frequency info
3445	* Intel: EAX - Core base frequency in MHz.
3446	* EBX - Core maximum frequency in MHz.
3447	* ECX - Bus (reference) frequency in MHz.
3448	* EDX - Reserved.
3449	* AMD: Reserved / undefined / not implemented.
3450	* VIA: Reserved / undefined / not implemented.
3451	* We zero this as we don't currently virtualize this.
3452	*/
3453	cpumR3CpuIdZeroLeaf(pCpum, 22);
3454
3455	/* Cpuid 0x17..0x10000000: Unknown.
3456	* We don't know these and what they mean, so remove them. */
3457	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3458	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3459
3460
3461	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3462	* We remove all these as we're a hypervisor and must provide our own.
3463	*/
3464	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3465	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3466
3467
3468	/* Cpuid 0x80000000 is harmless. */
3469
3470	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3471
3472	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3473
3474	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3475	* Safe to pass on to the guest.
3476	*
3477	* AMD: 0x800000005 L1 cache information
3478	* 0x800000006 L2/L3 cache information
3479	* Intel: 0x800000005 reserved
3480	* 0x800000006 L2 cache information
3481	* VIA: 0x800000005 TLB and L1 cache information
3482	* 0x800000006 L2 cache information
3483	*/
3484
3485	/* Cpuid 0x800000007: Advanced Power Management Information.
3486	* AMD: EAX: Processor feedback capabilities.
3487	* EBX: RAS capabilites.
3488	* ECX: Advanced power monitoring interface.
3489	* EDX: Enhanced power management capabilities.
3490	* Intel: EAX, EBX, ECX - reserved.
3491	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3492	* VIA: Reserved
3493	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3494	*/
3495	uSubLeaf = 0;
3496	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3497	{
3498	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3499	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3500	{
3501	/*
3502	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3503	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3504	* bit is now configurable.
3505	*/
3506	pCurLeaf->uEdx &= 0
3507	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3508	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3509	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3510	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3511	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3512	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3513	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3514	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3515	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3516	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3517	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3518	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3519	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3520	\| 0;
3521	}
3522	else
3523	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3524	if (!pConfig->fInvariantTsc)
3525	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3526	uSubLeaf++;
3527	}
3528
3529	/* Cpuid 0x80000008:
3530	* AMD: EBX, EDX - reserved
3531	* EAX: Virtual/Physical/Guest address Size
3532	* ECX: Number of cores + APICIdCoreIdSize
3533	* Intel: EAX: Virtual/Physical address Size
3534	* EBX, ECX, EDX - reserved
3535	* VIA: EAX: Virtual/Physical address Size
3536	* EBX, ECX, EDX - reserved
3537	*
3538	* We only expose the virtual+pysical address size to the guest atm.
3539	* On AMD we set the core count, but not the apic id stuff as we're
3540	* currently not doing the apic id assignments in a complatible manner.
3541	*/
3542	uSubLeaf = 0;
3543	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3544	{
3545	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3546	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3547	pCurLeaf->uEdx = 0; /* reserved */
3548
3549	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3550	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3551	pCurLeaf->uEcx = 0;
3552	#ifdef VBOX_WITH_MULTI_CORE
3553	if ( pVM->cCpus > 1
3554	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3555	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3556	#endif
3557	uSubLeaf++;
3558	}
3559
3560	/* Cpuid 0x80000009: Reserved
3561	* We zero this since we don't know what it may have been used for.
3562	*/
3563	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3564
3565	/* Cpuid 0x8000000a: SVM Information
3566	* AMD: EAX - SVM revision.
3567	* EBX - Number of ASIDs.
3568	* ECX - Reserved.
3569	* EDX - SVM Feature identification.
3570	*/
3571	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3572	if (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
3573	{
3574	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3575	pSvmFeatureLeaf->uEax = 0x1;
3576	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3577	pSvmFeatureLeaf->uEcx = 0;
3578	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3579	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3580	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3581	}
3582	else
3583	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3584
3585	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3586	* We clear these as we don't know what purpose they might have. */
3587	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3588	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3589
3590	/* Cpuid 0x80000019: TLB configuration
3591	* Seems to be harmless, pass them thru as is. */
3592
3593	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3594	* Strip anything we don't know what is or addresses feature we don't implement. */
3595	uSubLeaf = 0;
3596	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3597	{
3598	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3599	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3600	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3601	;
3602	pCurLeaf->uEbx = 0; /* reserved */
3603	pCurLeaf->uEcx = 0; /* reserved */
3604	pCurLeaf->uEdx = 0; /* reserved */
3605	uSubLeaf++;
3606	}
3607
3608	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3609	* Clear this as we don't currently virtualize this feature. */
3610	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3611
3612	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3613	* Clear this as we don't currently virtualize this feature. */
3614	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3615
3616	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3617	* We need to sanitize the cores per cache (EAX[25:14]).
3618	*
3619	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3620	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3621	* slightly different meaning.
3622	*/
3623	uSubLeaf = 0;
3624	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3625	{
3626	#ifdef VBOX_WITH_MULTI_CORE
3627	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3628	if (cCores > pVM->cCpus)
3629	cCores = pVM->cCpus;
3630	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3631	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3632	#else
3633	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3634	#endif
3635	uSubLeaf++;
3636	}
3637
3638	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3639	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3640	* setup, we have one compute unit with all the cores in it. Single node.
3641	*/
3642	uSubLeaf = 0;
3643	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3644	{
3645	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3646	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3647	{
3648	#ifdef VBOX_WITH_MULTI_CORE
3649	pCurLeaf->uEbx = pVM->cCpus < 0x100
3650	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3651	#else
3652	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3653	#endif
3654	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3655	}
3656	else
3657	{
3658	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3659	pCurLeaf->uEbx = 0; /* Reserved. */
3660	pCurLeaf->uEcx = 0; /* Reserved. */
3661	}
3662	pCurLeaf->uEdx = 0; /* Reserved. */
3663	uSubLeaf++;
3664	}
3665
3666	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3667	* We don't know these and what they mean, so remove them. */
3668	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3669	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3670
3671	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3672	* Just pass it thru for now. */
3673
3674	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3675	* Just pass it thru for now. */
3676
3677	/* Cpuid 0xc0000000: Centaur stuff.
3678	* Harmless, pass it thru. */
3679
3680	/* Cpuid 0xc0000001: Centaur features.
3681	* VIA: EAX - Family, model, stepping.
3682	* EDX - Centaur extended feature flags. Nothing interesting, except may
3683	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3684	* EBX, ECX - reserved.
3685	* We keep EAX but strips the rest.
3686	*/
3687	uSubLeaf = 0;
3688	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3689	{
3690	pCurLeaf->uEbx = 0;
3691	pCurLeaf->uEcx = 0;
3692	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3693	uSubLeaf++;
3694	}
3695
3696	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3697	* We only have fixed stale values, but should be harmless. */
3698
3699	/* Cpuid 0xc0000003: Reserved.
3700	* We zero this since we don't know what it may have been used for.
3701	*/
3702	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3703
3704	/* Cpuid 0xc0000004: Centaur Performance Info.
3705	* We only have fixed stale values, but should be harmless. */
3706
3707
3708	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3709	* We don't know these and what they mean, so remove them. */
3710	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3711	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3712
3713	return VINF_SUCCESS;
3714	#undef PORTABLE_DISABLE_FEATURE_BIT
3715	#undef PORTABLE_CLEAR_BITS_WHEN
3716	}
3717
3718
3719	/**
3720	* Reads a value in /CPUM/IsaExts/ node.
3721	*
3722	* @returns VBox status code (error message raised).
3723	* @param pVM The cross context VM structure. (For errors.)
3724	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3725	* @param pszValueName The value / extension name.
3726	* @param penmValue Where to return the choice.
3727	* @param enmDefault The default choice.
3728	*/
3729	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3730	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3731	{
3732	/*
3733	* Try integer encoding first.
3734	*/
3735	uint64_t uValue;
3736	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3737	if (RT_SUCCESS(rc))
3738	switch (uValue)
3739	{
3740	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3741	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3742	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3743	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3744	default:
3745	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3746	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3747	pszValueName, uValue);
3748	}
3749	/*
3750	* If missing, use default.
3751	*/
3752	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3753	*penmValue = enmDefault;
3754	else
3755	{
3756	if (rc == VERR_CFGM_NOT_INTEGER)
3757	{
3758	/*
3759	* Not an integer, try read it as a string.
3760	*/
3761	char szValue[32];
3762	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3763	if (RT_SUCCESS(rc))
3764	{
3765	RTStrToLower(szValue);
3766	size_t cchValue = strlen(szValue);
3767	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3768	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3769	*penmValue = CPUMISAEXTCFG_DISABLED;
3770	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3771	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3772	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3773	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3774	else if (EQ("portable"))
3775	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3776	else if (EQ("default") \|\| EQ("def"))
3777	*penmValue = enmDefault;
3778	else
3779	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3780	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3781	pszValueName, uValue);
3782	#undef EQ
3783	}
3784	}
3785	if (RT_FAILURE(rc))
3786	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3787	}
3788	return VINF_SUCCESS;
3789	}
3790
3791
3792	/**
3793	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3794	*
3795	* @returns VBox status code (error message raised).
3796	* @param pVM The cross context VM structure. (For errors.)
3797	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3798	* @param pszValueName The value / extension name.
3799	* @param penmValue Where to return the choice.
3800	* @param enmDefault The default choice.
3801	* @param fAllowed Allowed choice. Applied both to the result and to
3802	* the default value.
3803	*/
3804	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3805	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3806	{
3807	int rc;
3808	if (fAllowed)
3809	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3810	else
3811	{
3812	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3813	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3814	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3815	*penmValue = CPUMISAEXTCFG_DISABLED;
3816	}
3817	return rc;
3818	}
3819
3820
3821	/**
3822	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3823	*
3824	* @returns VBox status code (error message raised).
3825	* @param pVM The cross context VM structure. (For errors.)
3826	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3827	* @param pCpumCfg The /CPUM node (can be NULL).
3828	* @param pszValueName The value / extension name.
3829	* @param penmValue Where to return the choice.
3830	* @param enmDefault The default choice.
3831	*/
3832	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3833	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3834	{
3835	if (CFGMR3Exists(pCpumCfg, pszValueName))
3836	{
3837	if (!CFGMR3Exists(pIsaExts, pszValueName))
3838	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3839	else
3840	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3841	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3842	pszValueName, pszValueName);
3843
3844	bool fLegacy;
3845	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3846	if (RT_SUCCESS(rc))
3847	{
3848	*penmValue = fLegacy;
3849	return VINF_SUCCESS;
3850	}
3851	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3852	}
3853
3854	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3855	}
3856
3857
3858	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3859	{
3860	int rc;
3861
3862	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3863	* When non-zero CPUID features that could cause portability issues will be
3864	* stripped. The higher the value the more features gets stripped. Higher
3865	* values should only be used when older CPUs are involved since it may
3866	* harm performance and maybe also cause problems with specific guests. */
3867	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
3868	AssertLogRelRCReturn(rc, rc);
3869
3870	/** @cfgm{/CPUM/GuestCpuName, string}
3871	* The name of the CPU we're to emulate. The default is the host CPU.
3872	* Note! CPUs other than "host" one is currently unsupported. */
3873	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3874	AssertLogRelRCReturn(rc, rc);
3875
3876	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3877	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3878	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3879	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3880	*/
3881	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3882	AssertLogRelRCReturn(rc, rc);
3883
3884	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
3885	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
3886	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
3887	* 64-bit linux guests which assume the presence of AMD performance counters
3888	* that we do not virtualize.
3889	*/
3890	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
3891	AssertLogRelRCReturn(rc, rc);
3892
3893	/** @cfgm{/CPUM/ForceVme, boolean, false}
3894	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
3895	* By default the flag is passed thru as is from the host CPU, except
3896	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
3897	* guests and DOS boxes in general.
3898	*/
3899	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
3900	AssertLogRelRCReturn(rc, rc);
3901
3902	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3903	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
3904	* probably going to be a temporary hack, so don't depend on this.
3905	* The 1st byte of the value is the stepping, the 2nd byte value is the model
3906	* number and the 3rd byte value is the family, and the 4th value must be zero.
3907	*/
3908	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3909	AssertLogRelRCReturn(rc, rc);
3910
3911	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3912	* The last standard leaf to keep. The actual last value that is stored in EAX
3913	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3914	* removed. (This works independently of and differently from NT4LeafLimit.)
3915	* The default is usually set to what we're able to reasonably sanitize.
3916	*/
3917	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3918	AssertLogRelRCReturn(rc, rc);
3919
3920	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3921	* The last extended leaf to keep. The actual last value that is stored in EAX
3922	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3923	* leaf are removed. The default is set to what we're able to sanitize.
3924	*/
3925	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3926	AssertLogRelRCReturn(rc, rc);
3927
3928	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3929	* The last extended leaf to keep. The actual last value that is stored in EAX
3930	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3931	* leaf are removed. The default is set to what we're able to sanitize.
3932	*/
3933	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3934	AssertLogRelRCReturn(rc, rc);
3935
3936	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3937	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
3938	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
3939	* The default is false, and when enabled requires nested paging and AMD-V or
3940	* unrestricted guest mode.
3941	*/
3942	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
3943	AssertLogRelRCReturn(rc, rc);
3944	if ( pConfig->fNestedHWVirt
3945	&& !fNestedPagingAndFullGuestExec)
3946	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
3947	"Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
3948	#endif
3949
3950	/*
3951	* Instruction Set Architecture (ISA) Extensions.
3952	*/
3953	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3954	if (pIsaExts)
3955	{
3956	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3957	"CMPXCHG16B"
3958	"\|MONITOR"
3959	"\|MWaitExtensions"
3960	"\|SSE4.1"
3961	"\|SSE4.2"
3962	"\|XSAVE"
3963	"\|AVX"
3964	"\|AVX2"
3965	"\|AESNI"
3966	"\|PCLMUL"
3967	"\|POPCNT"
3968	"\|MOVBE"
3969	"\|RDRAND"
3970	"\|RDSEED"
3971	"\|CLFLUSHOPT"
3972	"\|FSGSBASE"
3973	"\|PCID"
3974	"\|INVPCID"
3975	"\|ABM"
3976	"\|SSE4A"
3977	"\|MISALNSSE"
3978	"\|3DNOWPRF"
3979	"\|AXMMX"
3980	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
3981	if (RT_FAILURE(rc))
3982	return rc;
3983	}
3984
3985	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
3986	* Expose CMPXCHG16B to the guest if supported by the host. For the time
3987	* being the default is to only do this for VMs with nested paging and AMD-V or
3988	* unrestricted guest mode.
3989	*/
3990	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
3991	AssertLogRelRCReturn(rc, rc);
3992
3993	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
3994	* Expose MONITOR/MWAIT instructions to the guest.
3995	*/
3996	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
3997	AssertLogRelRCReturn(rc, rc);
3998
3999	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4000	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4001	* break on interrupt feature (bit 1).
4002	*/
4003	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4004	AssertLogRelRCReturn(rc, rc);
4005
4006	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4007	* Expose SSE4.1 to the guest if available.
4008	*/
4009	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4010	AssertLogRelRCReturn(rc, rc);
4011
4012	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4013	* Expose SSE4.2 to the guest if available.
4014	*/
4015	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4016	AssertLogRelRCReturn(rc, rc);
4017
4018	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4019	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4020	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
4021	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
4022	&& ( !HMIsLongModeAllowed(pVM)
4023	\|\| NEMHCIsLongModeAllowed(pVM))
4024	#endif
4025	;
4026	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4027
4028	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4029	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4030	* default is to only expose this to VMs with nested paging and AMD-V or
4031	* unrestricted guest execution mode. Not possible to force this one without
4032	* host support at the moment.
4033	*/
4034	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4035	fMayHaveXSave /fAllowed/);
4036	AssertLogRelRCReturn(rc, rc);
4037
4038	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4039	* Expose the AVX instruction set extensions to the guest if available and
4040	* XSAVE is exposed too. For the time being the default is to only expose this
4041	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4042	*/
4043	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4044	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4045	AssertLogRelRCReturn(rc, rc);
4046
4047	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4048	* Expose the AVX2 instruction set extensions to the guest if available and
4049	* XSAVE is exposed too. For the time being the default is to only expose this
4050	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4051	*/
4052	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4053	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4054	AssertLogRelRCReturn(rc, rc);
4055
4056	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4057	* Whether to expose the AES instructions to the guest. For the time being the
4058	* default is to only do this for VMs with nested paging and AMD-V or
4059	* unrestricted guest mode.
4060	*/
4061	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4062	AssertLogRelRCReturn(rc, rc);
4063
4064	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4065	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4066	* being the default is to only do this for VMs with nested paging and AMD-V or
4067	* unrestricted guest mode.
4068	*/
4069	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4070	AssertLogRelRCReturn(rc, rc);
4071
4072	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4073	* Whether to expose the POPCNT instructions to the guest. For the time
4074	* being the default is to only do this for VMs with nested paging and AMD-V or
4075	* unrestricted guest mode.
4076	*/
4077	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4078	AssertLogRelRCReturn(rc, rc);
4079
4080	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4081	* Whether to expose the MOVBE instructions to the guest. For the time
4082	* being the default is to only do this for VMs with nested paging and AMD-V or
4083	* unrestricted guest mode.
4084	*/
4085	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4086	AssertLogRelRCReturn(rc, rc);
4087
4088	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4089	* Whether to expose the RDRAND instructions to the guest. For the time being
4090	* the default is to only do this for VMs with nested paging and AMD-V or
4091	* unrestricted guest mode.
4092	*/
4093	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4094	AssertLogRelRCReturn(rc, rc);
4095
4096	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4097	* Whether to expose the RDSEED instructions to the guest. For the time being
4098	* the default is to only do this for VMs with nested paging and AMD-V or
4099	* unrestricted guest mode.
4100	*/
4101	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4102	AssertLogRelRCReturn(rc, rc);
4103
4104	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4105	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4106	* being the default is to only do this for VMs with nested paging and AMD-V or
4107	* unrestricted guest mode.
4108	*/
4109	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4110	AssertLogRelRCReturn(rc, rc);
4111
4112	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4113	* Whether to expose the read/write FSGSBASE instructions to the guest.
4114	*/
4115	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4116	AssertLogRelRCReturn(rc, rc);
4117
4118	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4119	* Whether to expose the PCID feature to the guest.
4120	*/
4121	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4122	AssertLogRelRCReturn(rc, rc);
4123
4124	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4125	* Whether to expose the INVPCID instruction to the guest.
4126	*/
4127	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4128	AssertLogRelRCReturn(rc, rc);
4129
4130
4131	/* AMD: */
4132
4133	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4134	* Whether to expose the AMD ABM instructions to the guest. For the time
4135	* being the default is to only do this for VMs with nested paging and AMD-V or
4136	* unrestricted guest mode.
4137	*/
4138	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4139	AssertLogRelRCReturn(rc, rc);
4140
4141	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4142	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4143	* being the default is to only do this for VMs with nested paging and AMD-V or
4144	* unrestricted guest mode.
4145	*/
4146	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4147	AssertLogRelRCReturn(rc, rc);
4148
4149	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4150	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4151	* the time being the default is to only do this for VMs with nested paging and
4152	* AMD-V or unrestricted guest mode.
4153	*/
4154	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4155	AssertLogRelRCReturn(rc, rc);
4156
4157	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4158	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4159	* For the time being the default is to only do this for VMs with nested paging
4160	* and AMD-V or unrestricted guest mode.
4161	*/
4162	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4163	AssertLogRelRCReturn(rc, rc);
4164
4165	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4166	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4167	* the default is to only do this for VMs with nested paging and AMD-V or
4168	* unrestricted guest mode.
4169	*/
4170	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4171	AssertLogRelRCReturn(rc, rc);
4172
4173	return VINF_SUCCESS;
4174	}
4175
4176
4177	/**
4178	* Initializes the emulated CPU's CPUID & MSR information.
4179	*
4180	* @returns VBox status code.
4181	* @param pVM The cross context VM structure.
4182	*/
4183	int cpumR3InitCpuIdAndMsrs(PVM pVM)
4184	{
4185	PCPUM pCpum = &pVM->cpum.s;
4186	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4187
4188	/*
4189	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4190	* on construction and manage everything from here on.
4191	*/
4192	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
4193	pVM->aCpus[iCpu].cpum.s.fCpuIdApicFeatureVisible = true;
4194
4195	/*
4196	* Read the configuration.
4197	*/
4198	CPUMCPUIDCONFIG Config;
4199	RT_ZERO(Config);
4200
4201	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4202	AssertRCReturn(rc, rc);
4203
4204	/*
4205	* Get the guest CPU data from the database and/or the host.
4206	*
4207	* The CPUID and MSRs are currently living on the regular heap to avoid
4208	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4209	* API for the hyper heap). This means special cleanup considerations.
4210	*/
4211	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4212	if (RT_FAILURE(rc))
4213	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4214	? VMSetError(pVM, rc, RT_SRC_POS,
4215	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4216	: rc;
4217
4218	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4219	{
4220	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4221	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4222	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4223	}
4224	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4225
4226	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4227	* Overrides the guest MSRs.
4228	*/
4229	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4230
4231	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4232	* Overrides the CPUID leaf values (from the host CPU usually) used for
4233	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4234	* values when moving a VM to a different machine. Another use is restricting
4235	* (or extending) the feature set exposed to the guest. */
4236	if (RT_SUCCESS(rc))
4237	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4238
4239	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4240	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4241	"Found unsupported configuration node '/CPUM/CPUID/'. "
4242	"Please use IMachine::setCPUIDLeaf() instead.");
4243
4244	/*
4245	* Pre-explode the CPUID info.
4246	*/
4247	if (RT_SUCCESS(rc))
4248	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
4249
4250	/*
4251	* Sanitize the cpuid information passed on to the guest.
4252	*/
4253	if (RT_SUCCESS(rc))
4254	{
4255	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4256	if (RT_SUCCESS(rc))
4257	{
4258	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4259	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4260	}
4261	}
4262
4263	/*
4264	* MSR fudging.
4265	*/
4266	if (RT_SUCCESS(rc))
4267	{
4268	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4269	* Fudges some common MSRs if not present in the selected CPU database entry.
4270	* This is for trying to keep VMs running when moved between different hosts
4271	* and different CPU vendors. */
4272	bool fEnable;
4273	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4274	if (RT_SUCCESS(rc) && fEnable)
4275	{
4276	rc = cpumR3MsrApplyFudge(pVM);
4277	AssertLogRelRC(rc);
4278	}
4279	}
4280	if (RT_SUCCESS(rc))
4281	{
4282	/*
4283	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4284	* guest CPU features again.
4285	*/
4286	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4287	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4288	pCpum->GuestInfo.cCpuIdLeaves);
4289	RTMemFree(pvFree);
4290
4291	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4292	int rc2 = MMHyperDupMem(pVM, pvFree,
4293	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4294	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4295	RTMemFree(pvFree);
4296	AssertLogRelRCReturn(rc1, rc1);
4297	AssertLogRelRCReturn(rc2, rc2);
4298
4299	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4300	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4301
4302
4303	/*
4304	* Some more configuration that we're applying at the end of everything
4305	* via the CPUMSetGuestCpuIdFeature API.
4306	*/
4307
4308	/* Check if PAE was explicitely enabled by the user. */
4309	bool fEnable;
4310	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4311	AssertRCReturn(rc, rc);
4312	if (fEnable)
4313	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4314
4315	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4316	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4317	AssertRCReturn(rc, rc);
4318	if (fEnable)
4319	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4320
4321	/* Check if speculation control is enabled. */
4322	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4323	AssertRCReturn(rc, rc);
4324	if (fEnable)
4325	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4326
4327	return VINF_SUCCESS;
4328	}
4329
4330	/*
4331	* Failed before switching to hyper heap.
4332	*/
4333	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4334	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4335	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4336	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4337	return rc;
4338	}
4339
4340
4341	/**
4342	* Sets a CPUID feature bit during VM initialization.
4343	*
4344	* Since the CPUID feature bits are generally related to CPU features, other
4345	* CPUM configuration like MSRs can also be modified by calls to this API.
4346	*
4347	* @param pVM The cross context VM structure.
4348	* @param enmFeature The feature to set.
4349	*/
4350	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4351	{
4352	PCPUMCPUIDLEAF pLeaf;
4353	PCPUMMSRRANGE pMsrRange;
4354
4355	switch (enmFeature)
4356	{
4357	/*
4358	* Set the APIC bit in both feature masks.
4359	*/
4360	case CPUMCPUIDFEATURE_APIC:
4361	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4362	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4363	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4364
4365	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4366	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4367	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4368
4369	pVM->cpum.s.GuestFeatures.fApic = 1;
4370
4371	/* Make sure we've got the APICBASE MSR present. */
4372	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4373	if (!pMsrRange)
4374	{
4375	static CPUMMSRRANGE const s_ApicBase =
4376	{
4377	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4378	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4379	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4380	/.szName = / "IA32_APIC_BASE"
4381	};
4382	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4383	AssertLogRelRC(rc);
4384	}
4385
4386	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4387	break;
4388
4389	/*
4390	* Set the x2APIC bit in the standard feature mask.
4391	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4392	*/
4393	case CPUMCPUIDFEATURE_X2APIC:
4394	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4395	if (pLeaf)
4396	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4397	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4398
4399	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4400	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4401	if (pMsrRange)
4402	{
4403	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4404	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4405	}
4406
4407	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4408	break;
4409
4410	/*
4411	* Set the sysenter/sysexit bit in the standard feature mask.
4412	* Assumes the caller knows what it's doing! (host must support these)
4413	*/
4414	case CPUMCPUIDFEATURE_SEP:
4415	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4416	{
4417	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4418	return;
4419	}
4420
4421	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4422	if (pLeaf)
4423	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4424	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4425	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4426	break;
4427
4428	/*
4429	* Set the syscall/sysret bit in the extended feature mask.
4430	* Assumes the caller knows what it's doing! (host must support these)
4431	*/
4432	case CPUMCPUIDFEATURE_SYSCALL:
4433	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4434	if ( !pLeaf
4435	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4436	{
4437	#if HC_ARCH_BITS == 32
4438	/* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit
4439	mode by Intel, even when the cpu is capable of doing so in
4440	64-bit mode. Long mode requires syscall support. */
4441	if (!pVM->cpum.s.HostFeatures.fLongMode)
4442	#endif
4443	{
4444	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4445	return;
4446	}
4447	}
4448
4449	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4450	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4451	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4452	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4453	break;
4454
4455	/*
4456	* Set the PAE bit in both feature masks.
4457	* Assumes the caller knows what it's doing! (host must support these)
4458	*/
4459	case CPUMCPUIDFEATURE_PAE:
4460	if (!pVM->cpum.s.HostFeatures.fPae)
4461	{
4462	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4463	return;
4464	}
4465
4466	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4467	if (pLeaf)
4468	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4469
4470	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4471	if ( pLeaf
4472	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4473	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4474
4475	pVM->cpum.s.GuestFeatures.fPae = 1;
4476	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4477	break;
4478
4479	/*
4480	* Set the LONG MODE bit in the extended feature mask.
4481	* Assumes the caller knows what it's doing! (host must support these)
4482	*/
4483	case CPUMCPUIDFEATURE_LONG_MODE:
4484	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4485	if ( !pLeaf
4486	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4487	{
4488	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4489	return;
4490	}
4491
4492	/* Valid for both Intel and AMD. */
4493	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4494	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4495	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4496	break;
4497
4498	/*
4499	* Set the NX/XD bit in the extended feature mask.
4500	* Assumes the caller knows what it's doing! (host must support these)
4501	*/
4502	case CPUMCPUIDFEATURE_NX:
4503	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4504	if ( !pLeaf
4505	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4506	{
4507	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4508	return;
4509	}
4510
4511	/* Valid for both Intel and AMD. */
4512	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4513	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4514	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4515	break;
4516
4517
4518	/*
4519	* Set the LAHF/SAHF support in 64-bit mode.
4520	* Assumes the caller knows what it's doing! (host must support this)
4521	*/
4522	case CPUMCPUIDFEATURE_LAHF:
4523	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4524	if ( !pLeaf
4525	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4526	{
4527	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4528	return;
4529	}
4530
4531	/* Valid for both Intel and AMD. */
4532	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4533	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4534	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4535	break;
4536
4537	/*
4538	* Set the page attribute table bit. This is alternative page level
4539	* cache control that doesn't much matter when everything is
4540	* virtualized, though it may when passing thru device memory.
4541	*/
4542	case CPUMCPUIDFEATURE_PAT:
4543	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4544	if (pLeaf)
4545	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4546
4547	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4548	if ( pLeaf
4549	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4550	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4551
4552	pVM->cpum.s.GuestFeatures.fPat = 1;
4553	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4554	break;
4555
4556	/*
4557	* Set the RDTSCP support bit.
4558	* Assumes the caller knows what it's doing! (host must support this)
4559	*/
4560	case CPUMCPUIDFEATURE_RDTSCP:
4561	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4562	if ( !pLeaf
4563	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4564	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4565	{
4566	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4567	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4568	return;
4569	}
4570
4571	/* Valid for both Intel and AMD. */
4572	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4573	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4574	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4575	break;
4576
4577	/*
4578	* Set the Hypervisor Present bit in the standard feature mask.
4579	*/
4580	case CPUMCPUIDFEATURE_HVP:
4581	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4582	if (pLeaf)
4583	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4584	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4585	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4586	break;
4587
4588	/*
4589	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4590	* This currently includes the Present bit and MWAITBREAK bit as well.
4591	*/
4592	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4593	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4594	if ( !pLeaf
4595	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4596	{
4597	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4598	return;
4599	}
4600
4601	/* Valid for both Intel and AMD. */
4602	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4603	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4604	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4605	break;
4606
4607	/*
4608	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
4609	* on Intel CPUs, and different on AMDs.
4610	*/
4611	case CPUMCPUIDFEATURE_SPEC_CTRL:
4612	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4613	{
4614	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4615	if ( !pLeaf
4616	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
4617	{
4618	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4619	return;
4620	}
4621
4622	/* The feature can be enabled. Let's see what we can actually do. */
4623	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4624
4625	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4626	if (pVM->cpum.s.HostFeatures.fIbrs)
4627	{
4628	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4629	pVM->cpum.s.GuestFeatures.fIbrs = 1;
4630	if (pVM->cpum.s.HostFeatures.fStibp)
4631	{
4632	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4633	pVM->cpum.s.GuestFeatures.fStibp = 1;
4634	}
4635
4636	/* Make sure we have the speculation control MSR... */
4637	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4638	if (!pMsrRange)
4639	{
4640	static CPUMMSRRANGE const s_SpecCtrl =
4641	{
4642	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
4643	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
4644	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4645	/.szName = / "IA32_SPEC_CTRL"
4646	};
4647	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4648	AssertLogRelRC(rc);
4649	}
4650
4651	/* ... and the predictor command MSR. */
4652	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
4653	if (!pMsrRange)
4654	{
4655	static CPUMMSRRANGE const s_SpecCtrl =
4656	{
4657	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
4658	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
4659	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4660	/.szName = / "IA32_PRED_CMD"
4661	};
4662	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4663	AssertLogRelRC(rc);
4664	}
4665
4666	}
4667
4668	if (pVM->cpum.s.HostFeatures.fArchCap) {
4669	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
4670
4671	/* Install the architectural capabilities MSR. */
4672	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
4673	if (!pMsrRange)
4674	{
4675	static CPUMMSRRANGE const s_ArchCaps =
4676	{
4677	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
4678	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
4679	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
4680	/.szName = / "IA32_ARCH_CAPABILITIES"
4681	};
4682	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
4683	AssertLogRelRC(rc);
4684	}
4685	}
4686
4687	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
4688	}
4689	else if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4690	{
4691	/* The precise details of AMD's implementation are not yet clear. */
4692	}
4693	break;
4694
4695	default:
4696	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4697	break;
4698	}
4699
4700	/** @todo can probably kill this as this API is now init time only... */
4701	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4702	{
4703	PVMCPU pVCpu = &pVM->aCpus[i];
4704	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4705	}
4706	}
4707
4708
4709	/**
4710	* Queries a CPUID feature bit.
4711	*
4712	* @returns boolean for feature presence
4713	* @param pVM The cross context VM structure.
4714	* @param enmFeature The feature to query.
4715	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4716	*/
4717	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4718	{
4719	switch (enmFeature)
4720	{
4721	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4722	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4723	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4724	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4725	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4726	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4727	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4728	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4729	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4730	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4731	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4732	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4733	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
4734
4735	case CPUMCPUIDFEATURE_INVALID:
4736	case CPUMCPUIDFEATURE_32BIT_HACK:
4737	break;
4738	}
4739	AssertFailed();
4740	return false;
4741	}
4742
4743
4744	/**
4745	* Clears a CPUID feature bit.
4746	*
4747	* @param pVM The cross context VM structure.
4748	* @param enmFeature The feature to clear.
4749	*
4750	* @deprecated Probably better to default the feature to disabled and only allow
4751	* setting (enabling) it during construction.
4752	*/
4753	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4754	{
4755	PCPUMCPUIDLEAF pLeaf;
4756	switch (enmFeature)
4757	{
4758	case CPUMCPUIDFEATURE_APIC:
4759	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
4760	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4761	if (pLeaf)
4762	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
4763
4764	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4765	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4766	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4767
4768	pVM->cpum.s.GuestFeatures.fApic = 0;
4769	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4770	break;
4771
4772	case CPUMCPUIDFEATURE_X2APIC:
4773	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4774	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4775	if (pLeaf)
4776	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
4777	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
4778	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
4779	break;
4780
4781	case CPUMCPUIDFEATURE_PAE:
4782	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4783	if (pLeaf)
4784	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
4785
4786	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4787	if ( pLeaf
4788	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4789	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
4790
4791	pVM->cpum.s.GuestFeatures.fPae = 0;
4792	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
4793	break;
4794
4795	case CPUMCPUIDFEATURE_PAT:
4796	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4797	if (pLeaf)
4798	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
4799
4800	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4801	if ( pLeaf
4802	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4803	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
4804
4805	pVM->cpum.s.GuestFeatures.fPat = 0;
4806	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
4807	break;
4808
4809	case CPUMCPUIDFEATURE_LONG_MODE:
4810	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4811	if (pLeaf)
4812	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4813	pVM->cpum.s.GuestFeatures.fLongMode = 0;
4814	break;
4815
4816	case CPUMCPUIDFEATURE_LAHF:
4817	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4818	if (pLeaf)
4819	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4820	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
4821	break;
4822
4823	case CPUMCPUIDFEATURE_RDTSCP:
4824	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4825	if (pLeaf)
4826	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4827	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
4828	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
4829	break;
4830
4831	case CPUMCPUIDFEATURE_HVP:
4832	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4833	if (pLeaf)
4834	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
4835	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
4836	break;
4837
4838	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4839	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4840	if (pLeaf)
4841	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
4842	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
4843	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
4844	break;
4845
4846	case CPUMCPUIDFEATURE_SPEC_CTRL:
4847	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4848	if (pLeaf)
4849	/pVM->cpum.s.aGuestCpuIdPatmStd[7].uEdx =/ pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP \| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
4850	pVM->cpum.s.GuestFeatures.fSpeculationControl = 0;
4851	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
4852	break;
4853
4854	default:
4855	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4856	break;
4857	}
4858
4859	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4860	{
4861	PVMCPU pVCpu = &pVM->aCpus[i];
4862	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4863	}
4864	}
4865
4866
4867
4868	/*
4869	*
4870	*
4871	* Saved state related code.
4872	* Saved state related code.
4873	* Saved state related code.
4874	*
4875	*
4876	*/
4877
4878	/**
4879	* Called both in pass 0 and the final pass.
4880	*
4881	* @param pVM The cross context VM structure.
4882	* @param pSSM The saved state handle.
4883	*/
4884	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4885	{
4886	/*
4887	* Save all the CPU ID leaves.
4888	*/
4889	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4890	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4891	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4892	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4893
4894	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4895
4896	/*
4897	* Save a good portion of the raw CPU IDs as well as they may come in
4898	* handy when validating features for raw mode.
4899	*/
4900	CPUMCPUID aRawStd[16];
4901	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4902	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4903	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4904	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4905
4906	CPUMCPUID aRawExt[32];
4907	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4908	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4909	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4910	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4911	}
4912
4913
4914	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4915	{
4916	uint32_t cCpuIds;
4917	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4918	if (RT_SUCCESS(rc))
4919	{
4920	if (cCpuIds < 64)
4921	{
4922	for (uint32_t i = 0; i < cCpuIds; i++)
4923	{
4924	CPUMCPUID CpuId;
4925	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4926	if (RT_FAILURE(rc))
4927	break;
4928
4929	CPUMCPUIDLEAF NewLeaf;
4930	NewLeaf.uLeaf = uBase + i;
4931	NewLeaf.uSubLeaf = 0;
4932	NewLeaf.fSubLeafMask = 0;
4933	NewLeaf.uEax = CpuId.uEax;
4934	NewLeaf.uEbx = CpuId.uEbx;
4935	NewLeaf.uEcx = CpuId.uEcx;
4936	NewLeaf.uEdx = CpuId.uEdx;
4937	NewLeaf.fFlags = 0;
4938	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4939	}
4940	}
4941	else
4942	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4943	}
4944	if (RT_FAILURE(rc))
4945	{
4946	RTMemFree(*ppaLeaves);
4947	*ppaLeaves = NULL;
4948	*pcLeaves = 0;
4949	}
4950	return rc;
4951	}
4952
4953
4954	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4955	{
4956	*ppaLeaves = NULL;
4957	*pcLeaves = 0;
4958
4959	int rc;
4960	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4961	{
4962	/*
4963	* The new format. Starts by declaring the leave size and count.
4964	*/
4965	uint32_t cbLeaf;
4966	SSMR3GetU32(pSSM, &cbLeaf);
4967	uint32_t cLeaves;
4968	rc = SSMR3GetU32(pSSM, &cLeaves);
4969	if (RT_SUCCESS(rc))
4970	{
4971	if (cbLeaf == sizeof(**ppaLeaves))
4972	{
4973	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4974	{
4975	/*
4976	* Load the leaves one by one.
4977	*
4978	* The uPrev stuff is a kludge for working around a week worth of bad saved
4979	* states during the CPUID revamp in March 2015. We saved too many leaves
4980	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4981	* garbage entires at the end of the array when restoring. We also had
4982	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
4983	* this kludge doesn't deal correctly with that, but who cares...
4984	*/
4985	uint32_t uPrev = 0;
4986	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4987	{
4988	CPUMCPUIDLEAF Leaf;
4989	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
4990	if (RT_SUCCESS(rc))
4991	{
4992	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
4993	\|\| Leaf.uLeaf >= uPrev)
4994	{
4995	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4996	uPrev = Leaf.uLeaf;
4997	}
4998	else
4999	uPrev = UINT32_MAX;
5000	}
5001	}
5002	}
5003	else
5004	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5005	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5006	}
5007	else
5008	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5009	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5010	}
5011	}
5012	else
5013	{
5014	/*
5015	* The old format with its three inflexible arrays.
5016	*/
5017	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5018	if (RT_SUCCESS(rc))
5019	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5020	if (RT_SUCCESS(rc))
5021	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5022	if (RT_SUCCESS(rc))
5023	{
5024	/*
5025	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5026	*/
5027	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5028	if ( pLeaf
5029	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5030	{
5031	CPUMCPUIDLEAF Leaf;
5032	Leaf.uLeaf = 4;
5033	Leaf.fSubLeafMask = UINT32_MAX;
5034	Leaf.uSubLeaf = 0;
5035	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5036	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5037	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5038	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5039	\| UINT32_C(63); /* system coherency line size - 1 */
5040	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5041	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5042	\| (UINT32_C(1) << 5) /* cache level */
5043	\| UINT32_C(1); /* cache type (data) */
5044	Leaf.fFlags = 0;
5045	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5046	if (RT_SUCCESS(rc))
5047	{
5048	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5049	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5050	}
5051	if (RT_SUCCESS(rc))
5052	{
5053	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5054	Leaf.uEcx = 4095; /* sets - 1 */
5055	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5056	Leaf.uEbx \|= UINT32_C(23) << 22;
5057	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5058	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5059	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5060	Leaf.uEax \|= UINT32_C(2) << 5;
5061	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5062	}
5063	}
5064	}
5065	}
5066	return rc;
5067	}
5068
5069
5070	/**
5071	* Loads the CPU ID leaves saved by pass 0, inner worker.
5072	*
5073	* @returns VBox status code.
5074	* @param pVM The cross context VM structure.
5075	* @param pSSM The saved state handle.
5076	* @param uVersion The format version.
5077	* @param paLeaves Guest CPUID leaves loaded from the state.
5078	* @param cLeaves The number of leaves in @a paLeaves.
5079	*/
5080	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
5081	{
5082	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5083
5084	/*
5085	* Continue loading the state into stack buffers.
5086	*/
5087	CPUMCPUID GuestDefCpuId;
5088	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5089	AssertRCReturn(rc, rc);
5090
5091	CPUMCPUID aRawStd[16];
5092	uint32_t cRawStd;
5093	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5094	if (cRawStd > RT_ELEMENTS(aRawStd))
5095	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5096	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5097	AssertRCReturn(rc, rc);
5098	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5099	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5100
5101	CPUMCPUID aRawExt[32];
5102	uint32_t cRawExt;
5103	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5104	if (cRawExt > RT_ELEMENTS(aRawExt))
5105	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5106	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5107	AssertRCReturn(rc, rc);
5108	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5109	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5110
5111	/*
5112	* Get the raw CPU IDs for the current host.
5113	*/
5114	CPUMCPUID aHostRawStd[16];
5115	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5116	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5117
5118	CPUMCPUID aHostRawExt[32];
5119	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5120	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5121	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5122
5123	/*
5124	* Get the host and guest overrides so we don't reject the state because
5125	* some feature was enabled thru these interfaces.
5126	* Note! We currently only need the feature leaves, so skip rest.
5127	*/
5128	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5129	CPUMCPUID aHostOverrideStd[2];
5130	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5131	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5132
5133	CPUMCPUID aHostOverrideExt[2];
5134	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5135	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5136
5137	/*
5138	* This can be skipped.
5139	*/
5140	bool fStrictCpuIdChecks;
5141	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5142
5143	/*
5144	* Define a bunch of macros for simplifying the santizing/checking code below.
5145	*/
5146	/* Generic expression + failure message. */
5147	#define CPUID_CHECK_RET(expr, fmt) \
5148	do { \
5149	if (!(expr)) \
5150	{ \
5151	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5152	if (fStrictCpuIdChecks) \
5153	{ \
5154	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5155	RTStrFree(pszMsg); \
5156	return rcCpuid; \
5157	} \
5158	LogRel(("CPUM: %s\n", pszMsg)); \
5159	RTStrFree(pszMsg); \
5160	} \
5161	} while (0)
5162	#define CPUID_CHECK_WRN(expr, fmt) \
5163	do { \
5164	if (!(expr)) \
5165	LogRel(fmt); \
5166	} while (0)
5167
5168	/* For comparing two values and bitch if they differs. */
5169	#define CPUID_CHECK2_RET(what, host, saved) \
5170	do { \
5171	if ((host) != (saved)) \
5172	{ \
5173	if (fStrictCpuIdChecks) \
5174	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5175	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5176	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5177	} \
5178	} while (0)
5179	#define CPUID_CHECK2_WRN(what, host, saved) \
5180	do { \
5181	if ((host) != (saved)) \
5182	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5183	} while (0)
5184
5185	/* For checking raw cpu features (raw mode). */
5186	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5187	do { \
5188	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5189	{ \
5190	if (fStrictCpuIdChecks) \
5191	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5192	N_(#bit " mismatch: host=%d saved=%d"), \
5193	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5194	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5195	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5196	} \
5197	} while (0)
5198	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5199	do { \
5200	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5201	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5202	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5203	} while (0)
5204	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5205
5206	/* For checking guest features. */
5207	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5208	do { \
5209	if ( (aGuestCpuId##set [1].reg & bit) \
5210	&& !(aHostRaw##set [1].reg & bit) \
5211	&& !(aHostOverride##set [1].reg & bit) \
5212	) \
5213	{ \
5214	if (fStrictCpuIdChecks) \
5215	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5216	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5217	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5218	} \
5219	} while (0)
5220	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5221	do { \
5222	if ( (aGuestCpuId##set [1].reg & bit) \
5223	&& !(aHostRaw##set [1].reg & bit) \
5224	&& !(aHostOverride##set [1].reg & bit) \
5225	) \
5226	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5227	} while (0)
5228	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5229	do { \
5230	if ( (aGuestCpuId##set [1].reg & bit) \
5231	&& !(aHostRaw##set [1].reg & bit) \
5232	&& !(aHostOverride##set [1].reg & bit) \
5233	) \
5234	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5235	} while (0)
5236	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5237
5238	/* For checking guest features if AMD guest CPU. */
5239	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5240	do { \
5241	if ( (aGuestCpuId##set [1].reg & bit) \
5242	&& fGuestAmd \
5243	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5244	&& !(aHostOverride##set [1].reg & bit) \
5245	) \
5246	{ \
5247	if (fStrictCpuIdChecks) \
5248	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5249	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5250	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5251	} \
5252	} while (0)
5253	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5254	do { \
5255	if ( (aGuestCpuId##set [1].reg & bit) \
5256	&& fGuestAmd \
5257	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5258	&& !(aHostOverride##set [1].reg & bit) \
5259	) \
5260	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5261	} while (0)
5262	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5263	do { \
5264	if ( (aGuestCpuId##set [1].reg & bit) \
5265	&& fGuestAmd \
5266	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5267	&& !(aHostOverride##set [1].reg & bit) \
5268	) \
5269	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5270	} while (0)
5271	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5272
5273	/* For checking AMD features which have a corresponding bit in the standard
5274	range. (Intel defines very few bits in the extended feature sets.) */
5275	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5276	do { \
5277	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5278	&& !(fHostAmd \
5279	? aHostRawExt[1].reg & (ExtBit) \
5280	: aHostRawStd[1].reg & (StdBit)) \
5281	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5282	) \
5283	{ \
5284	if (fStrictCpuIdChecks) \
5285	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5286	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5287	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5288	} \
5289	} while (0)
5290	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5291	do { \
5292	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5293	&& !(fHostAmd \
5294	? aHostRawExt[1].reg & (ExtBit) \
5295	: aHostRawStd[1].reg & (StdBit)) \
5296	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5297	) \
5298	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5299	} while (0)
5300	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5301	do { \
5302	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5303	&& !(fHostAmd \
5304	? aHostRawExt[1].reg & (ExtBit) \
5305	: aHostRawStd[1].reg & (StdBit)) \
5306	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5307	) \
5308	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5309	} while (0)
5310	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5311
5312	/*
5313	* For raw-mode we'll require that the CPUs are very similar since we don't
5314	* intercept CPUID instructions for user mode applications.
5315	*/
5316	if (VM_IS_RAW_MODE_ENABLED(pVM))
5317	{
5318	/* CPUID(0) */
5319	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
5320	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
5321	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
5322	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5323	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
5324	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
5325	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
5326	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
5327	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5328
5329	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
5330
5331	/* CPUID(1).eax */
5332	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
5333	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
5334	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
5335
5336	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
5337	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
5338	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
5339
5340	/* CPUID(1).ecx */
5341	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
5342	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
5343	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
5344	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5345	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
5346	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
5347	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
5348	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
5349	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
5350	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
5351	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
5352	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
5353	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
5354	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
5355	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
5356	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
5357	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5358	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5359	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
5360	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
5361	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
5362	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5363	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
5364	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
5365	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5366	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
5367	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
5368	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5369	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
5370	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5371	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5372	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
5373
5374	/* CPUID(1).edx */
5375	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5376	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5377	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
5378	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5379	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
5380	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
5381	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5382	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5383	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
5384	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5385	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5386	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5387	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5388	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5389	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5390	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
5391	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5392	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5393	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5394	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
5395	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5396	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
5397	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
5398	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
5399	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
5400	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
5401	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
5402	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
5403	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
5404	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
5405	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
5406	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
5407
5408	/* CPUID(2) - config, mostly about caches. ignore. */
5409	/* CPUID(3) - processor serial number. ignore. */
5410	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
5411	/* CPUID(5) - mwait/monitor config. ignore. */
5412	/* CPUID(6) - power management. ignore. */
5413	/* CPUID(7) - ???. ignore. */
5414	/* CPUID(8) - ???. ignore. */
5415	/* CPUID(9) - DCA. ignore for now. */
5416	/* CPUID(a) - PeMo info. ignore for now. */
5417	/* CPUID(b) - topology info - takes ECX as input. ignore. */
5418
5419	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
5420	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
5421	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
5422	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
5423	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
5424	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
5425	{
5426	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
5427	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
5428	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
5429	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
5430	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
5431	}
5432
5433	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
5434	Note! Intel have/is marking many of the fields here as reserved. We
5435	will verify them as if it's an AMD CPU. */
5436	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
5437	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
5438	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
5439	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
5440	{
5441	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
5442	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
5443	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
5444	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5445	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
5446	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
5447	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
5448
5449	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
5450	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
5451	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
5452	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
5453	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
5454	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5455
5456	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
5457	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
5458	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
5459	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
5460
5461	/* CPUID(0x80000001).ecx */
5462	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
5463	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
5464	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
5465	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
5466	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
5467	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
5468	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
5469	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
5470	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
5471	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
5472	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
5473	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
5474	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
5475	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
5476	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5477	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5478	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5479	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5480	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5481	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5482	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5483	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5484	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5485	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5486	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5487	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5488	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5489	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5490	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5491	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5492	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5493	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5494
5495	/* CPUID(0x80000001).edx */
5496	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
5497	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
5498	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
5499	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
5500	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
5501	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
5502	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
5503	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
5504	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
5505	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
5506	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5507	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
5508	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
5509	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
5510	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
5511	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
5512	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
5513	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
5514	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5515	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5516	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5517	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
5518	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5519	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
5520	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
5521	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5522	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5523	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5524	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
5525	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5526	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5527	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5528
5529	/** @todo verify the rest as well. */
5530	}
5531	}
5532
5533
5534
5535	/*
5536	* Verify that we can support the features already exposed to the guest on
5537	* this host.
5538	*
5539	* Most of the features we're emulating requires intercepting instruction
5540	* and doing it the slow way, so there is no need to warn when they aren't
5541	* present in the host CPU. Thus we use IGN instead of EMU on these.
5542	*
5543	* Trailing comments:
5544	* "EMU" - Possible to emulate, could be lots of work and very slow.
5545	* "EMU?" - Can this be emulated?
5546	*/
5547	CPUMCPUID aGuestCpuIdStd[2];
5548	RT_ZERO(aGuestCpuIdStd);
5549	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5550
5551	/* CPUID(1).ecx */
5552	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5553	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5554	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5555	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5556	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5557	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5558	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5559	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5560	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5561	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5562	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5563	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5564	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5565	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5566	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5567	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5568	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5569	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5570	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5571	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5572	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5573	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5574	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5575	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5576	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5577	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5578	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5579	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5580	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5581	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5582	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5583	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5584
5585	/* CPUID(1).edx */
5586	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5587	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5588	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5589	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5590	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5591	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5592	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5593	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5594	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5595	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5596	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5597	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5598	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5599	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5600	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5601	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5602	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5603	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5604	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5605	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5606	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5607	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5608	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5609	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5610	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5611	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5612	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5613	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5614	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5615	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5616	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5617	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5618
5619	/* CPUID(0x80000000). */
5620	CPUMCPUID aGuestCpuIdExt[2];
5621	RT_ZERO(aGuestCpuIdExt);
5622	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5623	{
5624	/** @todo deal with no 0x80000001 on the host. */
5625	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5626	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5627
5628	/* CPUID(0x80000001).ecx */
5629	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5630	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5631	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5632	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5633	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5634	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5635	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5636	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5637	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5638	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5639	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5640	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5641	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5642	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5643	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5644	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5645	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5646	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5647	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5648	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5649	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5650	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5651	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5652	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5653	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5654	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5655	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5656	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5657	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5658	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5659	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5660	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5661
5662	/* CPUID(0x80000001).edx */
5663	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5664	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5665	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5666	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5667	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5668	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5669	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5670	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5671	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5672	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5673	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5674	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5675	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5676	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5677	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5678	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5679	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5680	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5681	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5682	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5683	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5684	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5685	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5686	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5687	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5688	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5689	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5690	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5691	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5692	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5693	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5694	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5695	}
5696
5697	/** @todo check leaf 7 */
5698
5699	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5700	* ECX=0: EAX - Valid bits in XCR0[31:0].
5701	* EBX - Maximum state size as per current XCR0 value.
5702	* ECX - Maximum state size for all supported features.
5703	* EDX - Valid bits in XCR0[63:32].
5704	* ECX=1: EAX - Various X-features.
5705	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5706	* ECX - Valid bits in IA32_XSS[31:0].
5707	* EDX - Valid bits in IA32_XSS[63:32].
5708	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5709	* if the bit invalid all four registers are set to zero.
5710	* EAX - The state size for this feature.
5711	* EBX - The state byte offset of this feature.
5712	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5713	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5714	*/
5715	uint64_t fGuestXcr0Mask = 0;
5716	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5717	if ( pCurLeaf
5718	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5719	&& ( pCurLeaf->uEax
5720	\|\| pCurLeaf->uEbx
5721	\|\| pCurLeaf->uEcx
5722	\|\| pCurLeaf->uEdx) )
5723	{
5724	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5725	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5726	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5727	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5728	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5729	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5730	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5731	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5732
5733	/* We don't support any additional features yet. */
5734	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5735	if (pCurLeaf && pCurLeaf->uEax)
5736	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5737	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5738	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5739	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5740	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5741	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5742
5743
5744	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5745	{
5746	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5747	if (pCurLeaf)
5748	{
5749	/* If advertised, the state component offset and size must match the one used by host. */
5750	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5751	{
5752	CPUMCPUID RawHost;
5753	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5754	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5755	if ( RawHost.uEbx != pCurLeaf->uEbx
5756	\|\| RawHost.uEax != pCurLeaf->uEax)
5757	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5758	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5759	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5760	}
5761	}
5762	}
5763	}
5764	/* Clear leaf 0xd just in case we're loading an old state... */
5765	else if (pCurLeaf)
5766	{
5767	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5768	{
5769	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5770	if (pCurLeaf)
5771	{
5772	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5773	\|\| ( pCurLeaf->uEax == 0
5774	&& pCurLeaf->uEbx == 0
5775	&& pCurLeaf->uEcx == 0
5776	&& pCurLeaf->uEdx == 0),
5777	("uVersion=%#x; %#x %#x %#x %#x\n",
5778	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5779	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5780	}
5781	}
5782	}
5783
5784	/* Update the fXStateGuestMask value for the VM. */
5785	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5786	{
5787	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5788	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5789	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5790	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5791	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5792	}
5793
5794	#undef CPUID_CHECK_RET
5795	#undef CPUID_CHECK_WRN
5796	#undef CPUID_CHECK2_RET
5797	#undef CPUID_CHECK2_WRN
5798	#undef CPUID_RAW_FEATURE_RET
5799	#undef CPUID_RAW_FEATURE_WRN
5800	#undef CPUID_RAW_FEATURE_IGN
5801	#undef CPUID_GST_FEATURE_RET
5802	#undef CPUID_GST_FEATURE_WRN
5803	#undef CPUID_GST_FEATURE_EMU
5804	#undef CPUID_GST_FEATURE_IGN
5805	#undef CPUID_GST_FEATURE2_RET
5806	#undef CPUID_GST_FEATURE2_WRN
5807	#undef CPUID_GST_FEATURE2_EMU
5808	#undef CPUID_GST_FEATURE2_IGN
5809	#undef CPUID_GST_AMD_FEATURE_RET
5810	#undef CPUID_GST_AMD_FEATURE_WRN
5811	#undef CPUID_GST_AMD_FEATURE_EMU
5812	#undef CPUID_GST_AMD_FEATURE_IGN
5813
5814	/*
5815	* We're good, commit the CPU ID leaves.
5816	*/
5817	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5818	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5819	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5820	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
5821	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5822	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
5823	AssertLogRelRCReturn(rc, rc);
5824
5825	return VINF_SUCCESS;
5826	}
5827
5828
5829	/**
5830	* Loads the CPU ID leaves saved by pass 0.
5831	*
5832	* @returns VBox status code.
5833	* @param pVM The cross context VM structure.
5834	* @param pSSM The saved state handle.
5835	* @param uVersion The format version.
5836	*/
5837	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5838	{
5839	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5840
5841	/*
5842	* Load the CPUID leaves array first and call worker to do the rest, just so
5843	* we can free the memory when we need to without ending up in column 1000.
5844	*/
5845	PCPUMCPUIDLEAF paLeaves;
5846	uint32_t cLeaves;
5847	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5848	AssertRC(rc);
5849	if (RT_SUCCESS(rc))
5850	{
5851	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
5852	RTMemFree(paLeaves);
5853	}
5854	return rc;
5855	}
5856
5857
5858
5859	/**
5860	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5861	*
5862	* @returns VBox status code.
5863	* @param pVM The cross context VM structure.
5864	* @param pSSM The saved state handle.
5865	* @param uVersion The format version.
5866	*/
5867	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5868	{
5869	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5870
5871	/*
5872	* Restore the CPUID leaves.
5873	*
5874	* Note that we support restoring less than the current amount of standard
5875	* leaves because we've been allowed more is newer version of VBox.
5876	*/
5877	uint32_t cElements;
5878	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5879	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5880	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5881	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5882
5883	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5884	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5885	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5886	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5887
5888	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5889	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5890	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5891	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5892
5893	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5894
5895	/*
5896	* Check that the basic cpuid id information is unchanged.
5897	*/
5898	/** @todo we should check the 64 bits capabilities too! */
5899	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5900	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5901	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5902	uint32_t au32CpuIdSaved[8];
5903	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5904	if (RT_SUCCESS(rc))
5905	{
5906	/* Ignore CPU stepping. */
5907	au32CpuId[4] &= 0xfffffff0;
5908	au32CpuIdSaved[4] &= 0xfffffff0;
5909
5910	/* Ignore APIC ID (AMD specs). */
5911	au32CpuId[5] &= ~0xff000000;
5912	au32CpuIdSaved[5] &= ~0xff000000;
5913
5914	/* Ignore the number of Logical CPUs (AMD specs). */
5915	au32CpuId[5] &= ~0x00ff0000;
5916	au32CpuIdSaved[5] &= ~0x00ff0000;
5917
5918	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5919	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5920	\| X86_CPUID_FEATURE_ECX_VMX
5921	\| X86_CPUID_FEATURE_ECX_SMX
5922	\| X86_CPUID_FEATURE_ECX_EST
5923	\| X86_CPUID_FEATURE_ECX_TM2
5924	\| X86_CPUID_FEATURE_ECX_CNTXID
5925	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5926	\| X86_CPUID_FEATURE_ECX_PDCM
5927	\| X86_CPUID_FEATURE_ECX_DCA
5928	\| X86_CPUID_FEATURE_ECX_X2APIC
5929	);
5930	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5931	\| X86_CPUID_FEATURE_ECX_VMX
5932	\| X86_CPUID_FEATURE_ECX_SMX
5933	\| X86_CPUID_FEATURE_ECX_EST
5934	\| X86_CPUID_FEATURE_ECX_TM2
5935	\| X86_CPUID_FEATURE_ECX_CNTXID
5936	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5937	\| X86_CPUID_FEATURE_ECX_PDCM
5938	\| X86_CPUID_FEATURE_ECX_DCA
5939	\| X86_CPUID_FEATURE_ECX_X2APIC
5940	);
5941
5942	/* Make sure we don't forget to update the masks when enabling
5943	* features in the future.
5944	*/
5945	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5946	( X86_CPUID_FEATURE_ECX_DTES64
5947	\| X86_CPUID_FEATURE_ECX_VMX
5948	\| X86_CPUID_FEATURE_ECX_SMX
5949	\| X86_CPUID_FEATURE_ECX_EST
5950	\| X86_CPUID_FEATURE_ECX_TM2
5951	\| X86_CPUID_FEATURE_ECX_CNTXID
5952	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5953	\| X86_CPUID_FEATURE_ECX_PDCM
5954	\| X86_CPUID_FEATURE_ECX_DCA
5955	\| X86_CPUID_FEATURE_ECX_X2APIC
5956	)));
5957	/* do the compare */
5958	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5959	{
5960	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5961	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5962	"Saved=%.*Rhxs\n"
5963	"Real =%.*Rhxs\n",
5964	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5965	sizeof(au32CpuId), au32CpuId));
5966	else
5967	{
5968	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5969	"Saved=%.*Rhxs\n"
5970	"Real =%.*Rhxs\n",
5971	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5972	sizeof(au32CpuId), au32CpuId));
5973	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5974	}
5975	}
5976	}
5977
5978	return rc;
5979	}
5980
5981
5982
5983	/*
5984	*
5985	*
5986	* CPUID Info Handler.
5987	* CPUID Info Handler.
5988	* CPUID Info Handler.
5989	*
5990	*
5991	*/
5992
5993
5994
5995	/**
5996	* Get L1 cache / TLS associativity.
5997	*/
5998	static const char getCacheAss(unsigned u, char pszBuf)
5999	{
6000	if (u == 0)
6001	return "res0 ";
6002	if (u == 1)
6003	return "direct";
6004	if (u == 255)
6005	return "fully";
6006	if (u >= 256)
6007	return "???";
6008
6009	RTStrPrintf(pszBuf, 16, "%d way", u);
6010	return pszBuf;
6011	}
6012
6013
6014	/**
6015	* Get L2 cache associativity.
6016	*/
6017	const char *getL2CacheAss(unsigned u)
6018	{
6019	switch (u)
6020	{
6021	case 0: return "off ";
6022	case 1: return "direct";
6023	case 2: return "2 way ";
6024	case 3: return "res3 ";
6025	case 4: return "4 way ";
6026	case 5: return "res5 ";
6027	case 6: return "8 way ";
6028	case 7: return "res7 ";
6029	case 8: return "16 way";
6030	case 9: return "res9 ";
6031	case 10: return "res10 ";
6032	case 11: return "res11 ";
6033	case 12: return "res12 ";
6034	case 13: return "res13 ";
6035	case 14: return "res14 ";
6036	case 15: return "fully ";
6037	default: return "????";
6038	}
6039	}
6040
6041
6042	/** CPUID(1).EDX field descriptions. */
6043	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6044	{
6045	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6046	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6047	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6048	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6049	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6050	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6051	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6052	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6053	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6054	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6055	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6056	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6057	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6058	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6059	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6060	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6061	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6062	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6063	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6064	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6065	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6066	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6067	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6068	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6069	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6070	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6071	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6072	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6073	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6074	DBGFREGSUBFIELD_TERMINATOR()
6075	};
6076
6077	/** CPUID(1).ECX field descriptions. */
6078	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6079	{
6080	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6081	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6082	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6083	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6084	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6085	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6086	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6087	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6088	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6089	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6090	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6091	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6092	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6093	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6094	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6095	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6096	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6097	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6098	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6099	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6100	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6101	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6102	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6103	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6104	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6105	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6106	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6107	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6108	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6109	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6110	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6111	DBGFREGSUBFIELD_TERMINATOR()
6112	};
6113
6114	/** CPUID(7,0).EBX field descriptions. */
6115	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6116	{
6117	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6118	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6119	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6120	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6121	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6122	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6123	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6124	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6125	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6126	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6127	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6128	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6129	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6130	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6131	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6132	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6133	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6134	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6135	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6136	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6137	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6138	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6139	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6140	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6141	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6142	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6143	DBGFREGSUBFIELD_TERMINATOR()
6144	};
6145
6146	/** CPUID(7,0).ECX field descriptions. */
6147	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6148	{
6149	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6150	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6151	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6152	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6153	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6154	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6155	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6156	DBGFREGSUBFIELD_TERMINATOR()
6157	};
6158
6159	/** CPUID(7,0).EDX field descriptions. */
6160	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6161	{
6162	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6163	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6164	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6165	DBGFREGSUBFIELD_TERMINATOR()
6166	};
6167
6168
6169	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6170	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6171	{
6172	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6173	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6174	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6175	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6176	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6177	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6178	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6179	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6180	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6181	DBGFREGSUBFIELD_TERMINATOR()
6182	};
6183
6184	/** CPUID(13,1).EAX field descriptions. */
6185	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6186	{
6187	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6188	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6189	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6190	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6191	DBGFREGSUBFIELD_TERMINATOR()
6192	};
6193
6194
6195	/** CPUID(0x80000001,0).EDX field descriptions. */
6196	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6197	{
6198	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6199	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6200	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6201	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6202	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6203	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6204	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6205	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6206	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6207	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6208	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6209	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6210	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6211	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6212	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6213	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6214	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6215	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6216	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6217	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6218	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6219	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6220	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6221	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6222	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6223	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6224	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6225	DBGFREGSUBFIELD_TERMINATOR()
6226	};
6227
6228	/** CPUID(0x80000001,0).ECX field descriptions. */
6229	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6230	{
6231	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6232	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6233	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6234	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6235	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6236	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6237	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6238	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6239	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6240	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6241	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6242	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6243	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6244	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6245	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6246	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6247	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6248	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6249	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6250	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6251	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6252	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6253	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6254	DBGFREGSUBFIELD_TERMINATOR()
6255	};
6256
6257	/** CPUID(0x80000007,0).EDX field descriptions. */
6258	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6259	{
6260	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6261	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6262	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6263	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6264	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6265	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6266	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6267	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6268	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6269	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6270	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6271	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6272	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6273	DBGFREGSUBFIELD_TERMINATOR()
6274	};
6275
6276	/** CPUID(0x80000008,0).EBX field descriptions. */
6277	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6278	{
6279	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6280	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6281	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6282	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6283	DBGFREGSUBFIELD_TERMINATOR()
6284	};
6285
6286
6287	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6288	const char *pszLeadIn, uint32_t cchWidth)
6289	{
6290	if (pszLeadIn)
6291	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6292
6293	for (uint32_t iBit = 0; iBit < 32; iBit++)
6294	if (RT_BIT_32(iBit) & uVal)
6295	{
6296	while ( pDesc->pszName != NULL
6297	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6298	pDesc++;
6299	if ( pDesc->pszName != NULL
6300	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6301	{
6302	if (pDesc->cBits == 1)
6303	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6304	else
6305	{
6306	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6307	if (pDesc->cBits < 32)
6308	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6309	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6310	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6311	}
6312	}
6313	else
6314	pHlp->pfnPrintf(pHlp, " %u", iBit);
6315	}
6316	if (pszLeadIn)
6317	pHlp->pfnPrintf(pHlp, "\n");
6318	}
6319
6320
6321	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6322	const char *pszLeadIn, uint32_t cchWidth)
6323	{
6324	if (pszLeadIn)
6325	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6326
6327	for (uint32_t iBit = 0; iBit < 64; iBit++)
6328	if (RT_BIT_64(iBit) & uVal)
6329	{
6330	while ( pDesc->pszName != NULL
6331	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6332	pDesc++;
6333	if ( pDesc->pszName != NULL
6334	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6335	{
6336	if (pDesc->cBits == 1)
6337	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6338	else
6339	{
6340	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6341	if (pDesc->cBits < 64)
6342	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6343	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6344	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6345	}
6346	}
6347	else
6348	pHlp->pfnPrintf(pHlp, " %u", iBit);
6349	}
6350	if (pszLeadIn)
6351	pHlp->pfnPrintf(pHlp, "\n");
6352	}
6353
6354
6355	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6356	const char *pszLeadIn, uint32_t cchWidth)
6357	{
6358	if (!uVal)
6359	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6360	else
6361	{
6362	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6363	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6364	pHlp->pfnPrintf(pHlp, " )\n");
6365	}
6366	}
6367
6368
6369	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6370	uint32_t cchWidth)
6371	{
6372	uint32_t uCombined = uVal1 \| uVal2;
6373	for (uint32_t iBit = 0; iBit < 32; iBit++)
6374	if ( (RT_BIT_32(iBit) & uCombined)
6375	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6376	{
6377	while ( pDesc->pszName != NULL
6378	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6379	pDesc++;
6380
6381	if ( pDesc->pszName != NULL
6382	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6383	{
6384	size_t cchMnemonic = strlen(pDesc->pszName);
6385	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6386	size_t cchDesc = strlen(pszDesc);
6387	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6388	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6389	if (pDesc->cBits < 32)
6390	{
6391	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6392	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6393	}
6394
6395	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6396	pDesc->pszName, pszDesc,
6397	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6398	uFieldValue1, uFieldValue2);
6399
6400	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6401	pDesc++;
6402	}
6403	else
6404	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6405	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6406	}
6407	}
6408
6409
6410	/**
6411	* Produces a detailed summary of standard leaf 0x00000001.
6412	*
6413	* @param pHlp The info helper functions.
6414	* @param pCurLeaf The 0x00000001 leaf.
6415	* @param fVerbose Whether to be very verbose or not.
6416	* @param fIntel Set if intel CPU.
6417	*/
6418	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6419	{
6420	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6421	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6422	uint32_t uEAX = pCurLeaf->uEax;
6423	uint32_t uEBX = pCurLeaf->uEbx;
6424
6425	pHlp->pfnPrintf(pHlp,
6426	"%36s %2d \tExtended: %d \tEffective: %d\n"
6427	"%36s %2d \tExtended: %d \tEffective: %d\n"
6428	"%36s %d\n"
6429	"%36s %d (%s)\n"
6430	"%36s %#04x\n"
6431	"%36s %d\n"
6432	"%36s %d\n"
6433	"%36s %#04x\n"
6434	,
6435	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6436	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6437	"Stepping:", ASMGetCpuStepping(uEAX),
6438	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6439	"APIC ID:", (uEBX >> 24) & 0xff,
6440	"Logical CPUs:",(uEBX >> 16) & 0xff,
6441	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6442	"Brand ID:", (uEBX >> 0) & 0xff);
6443	if (fVerbose)
6444	{
6445	CPUMCPUID Host;
6446	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6447	pHlp->pfnPrintf(pHlp, "Features\n");
6448	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6449	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6450	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6451	}
6452	else
6453	{
6454	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6455	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6456	}
6457	}
6458
6459
6460	/**
6461	* Produces a detailed summary of standard leaf 0x00000007.
6462	*
6463	* @param pHlp The info helper functions.
6464	* @param paLeaves The CPUID leaves array.
6465	* @param cLeaves The number of leaves in the array.
6466	* @param pCurLeaf The first 0x00000007 leaf.
6467	* @param fVerbose Whether to be very verbose or not.
6468	*/
6469	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6470	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6471	{
6472	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6473	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6474	for (;;)
6475	{
6476	CPUMCPUID Host;
6477	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6478
6479	switch (pCurLeaf->uSubLeaf)
6480	{
6481	case 0:
6482	if (fVerbose)
6483	{
6484	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6485	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6486	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6487	if (pCurLeaf->uEdx \|\| Host.uEdx)
6488	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6489	}
6490	else
6491	{
6492	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6493	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6494	if (pCurLeaf->uEdx)
6495	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6496	}
6497	break;
6498
6499	default:
6500	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6501	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6502	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6503	break;
6504
6505	}
6506
6507	/* advance. */
6508	pCurLeaf++;
6509	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6510	\|\| pCurLeaf->uLeaf != 0x7)
6511	break;
6512	}
6513	}
6514
6515
6516	/**
6517	* Produces a detailed summary of standard leaf 0x0000000d.
6518	*
6519	* @param pHlp The info helper functions.
6520	* @param paLeaves The CPUID leaves array.
6521	* @param cLeaves The number of leaves in the array.
6522	* @param pCurLeaf The first 0x00000007 leaf.
6523	* @param fVerbose Whether to be very verbose or not.
6524	*/
6525	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6526	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6527	{
6528	RT_NOREF_PV(fVerbose);
6529	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6530	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6531	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6532	{
6533	CPUMCPUID Host;
6534	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6535
6536	switch (uSubLeaf)
6537	{
6538	case 0:
6539	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6540	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6541	pCurLeaf->uEbx, pCurLeaf->uEcx);
6542	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6543
6544	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6545	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6546	"Valid XCR0 bits, guest:", 42);
6547	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6548	"Valid XCR0 bits, host:", 42);
6549	break;
6550
6551	case 1:
6552	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6553	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6554	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6555
6556	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6557	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6558	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6559
6560	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6561	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6562	" Valid IA32_XSS bits, guest:", 42);
6563	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6564	" Valid IA32_XSS bits, host:", 42);
6565	break;
6566
6567	default:
6568	if ( pCurLeaf
6569	&& pCurLeaf->uSubLeaf == uSubLeaf
6570	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6571	{
6572	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6573	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6574	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6575	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6576	if (pCurLeaf->uEdx)
6577	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6578	pHlp->pfnPrintf(pHlp, " --");
6579	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6580	pHlp->pfnPrintf(pHlp, "\n");
6581	}
6582	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6583	{
6584	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6585	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6586	if (Host.uEcx & ~RT_BIT_32(0))
6587	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6588	if (Host.uEdx)
6589	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6590	pHlp->pfnPrintf(pHlp, " --");
6591	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6592	pHlp->pfnPrintf(pHlp, "\n");
6593	}
6594	break;
6595
6596	}
6597
6598	/* advance. */
6599	if (pCurLeaf)
6600	{
6601	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6602	&& pCurLeaf->uSubLeaf <= uSubLeaf
6603	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6604	pCurLeaf++;
6605	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6606	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6607	pCurLeaf = NULL;
6608	}
6609	}
6610	}
6611
6612
6613	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6614	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6615	{
6616	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6617	&& pCurLeaf->uLeaf <= uUpToLeaf)
6618	{
6619	pHlp->pfnPrintf(pHlp,
6620	" %s\n"
6621	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6622	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6623	&& pCurLeaf->uLeaf <= uUpToLeaf)
6624	{
6625	CPUMCPUID Host;
6626	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6627	pHlp->pfnPrintf(pHlp,
6628	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6629	"Hst: %08x %08x %08x %08x\n",
6630	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6631	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6632	pCurLeaf++;
6633	}
6634	}
6635
6636	return pCurLeaf;
6637	}
6638
6639
6640	/**
6641	* Display the guest CpuId leaves.
6642	*
6643	* @param pVM The cross context VM structure.
6644	* @param pHlp The info helper functions.
6645	* @param pszArgs "terse", "default" or "verbose".
6646	*/
6647	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6648	{
6649	/*
6650	* Parse the argument.
6651	*/
6652	unsigned iVerbosity = 1;
6653	if (pszArgs)
6654	{
6655	pszArgs = RTStrStripL(pszArgs);
6656	if (!strcmp(pszArgs, "terse"))
6657	iVerbosity--;
6658	else if (!strcmp(pszArgs, "verbose"))
6659	iVerbosity++;
6660	}
6661
6662	uint32_t uLeaf;
6663	CPUMCPUID Host;
6664	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6665	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6666	PCCPUMCPUIDLEAF pCurLeaf;
6667	PCCPUMCPUIDLEAF pNextLeaf;
6668	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6669	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6670	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6671
6672	/*
6673	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6674	*/
6675	uint32_t cHstMax = ASMCpuId_EAX(0);
6676	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6677	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6678	pHlp->pfnPrintf(pHlp,
6679	" Raw Standard CPUID Leaves\n"
6680	" Leaf/sub-leaf eax ebx ecx edx\n");
6681	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6682	{
6683	uint32_t cMaxSubLeaves = 1;
6684	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6685	cMaxSubLeaves = 16;
6686	else if (uLeaf == 0xd)
6687	cMaxSubLeaves = 128;
6688
6689	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6690	{
6691	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6692	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6693	&& pCurLeaf->uLeaf == uLeaf
6694	&& pCurLeaf->uSubLeaf == uSubLeaf)
6695	{
6696	pHlp->pfnPrintf(pHlp,
6697	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6698	"Hst: %08x %08x %08x %08x\n",
6699	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6700	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6701	pCurLeaf++;
6702	}
6703	else if ( uLeaf != 0xd
6704	\|\| uSubLeaf <= 1
6705	\|\| Host.uEbx != 0 )
6706	pHlp->pfnPrintf(pHlp,
6707	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6708	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6709
6710	/* Done? */
6711	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6712	\|\| pCurLeaf->uLeaf != uLeaf)
6713	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6714	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6715	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6716	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6717	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6718	)
6719	)
6720	break;
6721	}
6722	}
6723	pNextLeaf = pCurLeaf;
6724
6725	/*
6726	* If verbose, decode it.
6727	*/
6728	if (iVerbosity && paLeaves[0].uLeaf == 0)
6729	pHlp->pfnPrintf(pHlp,
6730	"%36s %.04s%.04s%.04s\n"
6731	"%36s 0x00000000-%#010x\n"
6732	,
6733	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6734	"Supports:", paLeaves[0].uEax);
6735
6736	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6737	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6738
6739	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6740	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6741
6742	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6743	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6744
6745	pCurLeaf = pNextLeaf;
6746
6747	/*
6748	* Hypervisor leaves.
6749	*
6750	* Unlike most of the other leaves reported, the guest hypervisor leaves
6751	* aren't a subset of the host CPUID bits.
6752	*/
6753	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6754
6755	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6756	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6757	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6758	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6759	cMax = RT_MAX(cHstMax, cGstMax);
6760	if (cMax >= UINT32_C(0x40000000))
6761	{
6762	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6763
6764	/** @todo dump these in more detail. */
6765
6766	pCurLeaf = pNextLeaf;
6767	}
6768
6769
6770	/*
6771	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6772	* Implemented after AMD specs.
6773	*/
6774	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6775
6776	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6777	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6778	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6779	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6780	cMax = RT_MAX(cHstMax, cGstMax);
6781	if (cMax >= UINT32_C(0x80000000))
6782	{
6783
6784	pHlp->pfnPrintf(pHlp,
6785	" Raw Extended CPUID Leaves\n"
6786	" Leaf/sub-leaf eax ebx ecx edx\n");
6787	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6788	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6789	{
6790	uint32_t cMaxSubLeaves = 1;
6791	if (uLeaf == UINT32_C(0x8000001d))
6792	cMaxSubLeaves = 16;
6793
6794	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6795	{
6796	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6797	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6798	&& pCurLeaf->uLeaf == uLeaf
6799	&& pCurLeaf->uSubLeaf == uSubLeaf)
6800	{
6801	pHlp->pfnPrintf(pHlp,
6802	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6803	"Hst: %08x %08x %08x %08x\n",
6804	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6805	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6806	pCurLeaf++;
6807	}
6808	else if ( uLeaf != 0xd
6809	\|\| uSubLeaf <= 1
6810	\|\| Host.uEbx != 0 )
6811	pHlp->pfnPrintf(pHlp,
6812	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6813	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6814
6815	/* Done? */
6816	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6817	\|\| pCurLeaf->uLeaf != uLeaf)
6818	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6819	break;
6820	}
6821	}
6822	pNextLeaf = pCurLeaf;
6823
6824	/*
6825	* Understandable output
6826	*/
6827	if (iVerbosity)
6828	pHlp->pfnPrintf(pHlp,
6829	"Ext Name: %.4s%.4s%.4s\n"
6830	"Ext Supports: 0x80000000-%#010x\n",
6831	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6832
6833	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6834	if (iVerbosity && pCurLeaf)
6835	{
6836	uint32_t uEAX = pCurLeaf->uEax;
6837	pHlp->pfnPrintf(pHlp,
6838	"Family: %d \tExtended: %d \tEffective: %d\n"
6839	"Model: %d \tExtended: %d \tEffective: %d\n"
6840	"Stepping: %d\n"
6841	"Brand ID: %#05x\n",
6842	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6843	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6844	ASMGetCpuStepping(uEAX),
6845	pCurLeaf->uEbx & 0xfff);
6846
6847	if (iVerbosity == 1)
6848	{
6849	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6850	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6851	}
6852	else
6853	{
6854	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6855	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6856	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6857	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6858	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6859	}
6860	}
6861
6862	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6863	{
6864	char szString[443+1] = {0};
6865	uint32_t pu32 = (uint32_t )szString;
6866	*pu32++ = pCurLeaf->uEax;
6867	*pu32++ = pCurLeaf->uEbx;
6868	*pu32++ = pCurLeaf->uEcx;
6869	*pu32++ = pCurLeaf->uEdx;
6870	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6871	if (pCurLeaf)
6872	{
6873	*pu32++ = pCurLeaf->uEax;
6874	*pu32++ = pCurLeaf->uEbx;
6875	*pu32++ = pCurLeaf->uEcx;
6876	*pu32++ = pCurLeaf->uEdx;
6877	}
6878	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6879	if (pCurLeaf)
6880	{
6881	*pu32++ = pCurLeaf->uEax;
6882	*pu32++ = pCurLeaf->uEbx;
6883	*pu32++ = pCurLeaf->uEcx;
6884	*pu32++ = pCurLeaf->uEdx;
6885	}
6886	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6887	}
6888
6889	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6890	{
6891	uint32_t uEAX = pCurLeaf->uEax;
6892	uint32_t uEBX = pCurLeaf->uEbx;
6893	uint32_t uECX = pCurLeaf->uEcx;
6894	uint32_t uEDX = pCurLeaf->uEdx;
6895	char sz1[32];
6896	char sz2[32];
6897
6898	pHlp->pfnPrintf(pHlp,
6899	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6900	"TLB 2/4M Data: %s %3d entries\n",
6901	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6902	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6903	pHlp->pfnPrintf(pHlp,
6904	"TLB 4K Instr/Uni: %s %3d entries\n"
6905	"TLB 4K Data: %s %3d entries\n",
6906	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6907	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6908	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6909	"L1 Instr Cache Lines Per Tag: %d\n"
6910	"L1 Instr Cache Associativity: %s\n"
6911	"L1 Instr Cache Size: %d KB\n",
6912	(uEDX >> 0) & 0xff,
6913	(uEDX >> 8) & 0xff,
6914	getCacheAss((uEDX >> 16) & 0xff, sz1),
6915	(uEDX >> 24) & 0xff);
6916	pHlp->pfnPrintf(pHlp,
6917	"L1 Data Cache Line Size: %d bytes\n"
6918	"L1 Data Cache Lines Per Tag: %d\n"
6919	"L1 Data Cache Associativity: %s\n"
6920	"L1 Data Cache Size: %d KB\n",
6921	(uECX >> 0) & 0xff,
6922	(uECX >> 8) & 0xff,
6923	getCacheAss((uECX >> 16) & 0xff, sz1),
6924	(uECX >> 24) & 0xff);
6925	}
6926
6927	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6928	{
6929	uint32_t uEAX = pCurLeaf->uEax;
6930	uint32_t uEBX = pCurLeaf->uEbx;
6931	uint32_t uEDX = pCurLeaf->uEdx;
6932
6933	pHlp->pfnPrintf(pHlp,
6934	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6935	"L2 TLB 2/4M Data: %s %4d entries\n",
6936	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6937	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6938	pHlp->pfnPrintf(pHlp,
6939	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6940	"L2 TLB 4K Data: %s %4d entries\n",
6941	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6942	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6943	pHlp->pfnPrintf(pHlp,
6944	"L2 Cache Line Size: %d bytes\n"
6945	"L2 Cache Lines Per Tag: %d\n"
6946	"L2 Cache Associativity: %s\n"
6947	"L2 Cache Size: %d KB\n",
6948	(uEDX >> 0) & 0xff,
6949	(uEDX >> 8) & 0xf,
6950	getL2CacheAss((uEDX >> 12) & 0xf),
6951	(uEDX >> 16) & 0xffff);
6952	}
6953
6954	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
6955	{
6956	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6957	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
6958	{
6959	if (iVerbosity < 1)
6960	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
6961	else
6962	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
6963	}
6964	}
6965
6966	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
6967	if (pCurLeaf != NULL)
6968	{
6969	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6970	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
6971	{
6972	if (iVerbosity < 1)
6973	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
6974	else
6975	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
6976	}
6977
6978	if (iVerbosity)
6979	{
6980	uint32_t uEAX = pCurLeaf->uEax;
6981	uint32_t uECX = pCurLeaf->uEcx;
6982
6983	pHlp->pfnPrintf(pHlp,
6984	"Physical Address Width: %d bits\n"
6985	"Virtual Address Width: %d bits\n"
6986	"Guest Physical Address Width: %d bits\n",
6987	(uEAX >> 0) & 0xff,
6988	(uEAX >> 8) & 0xff,
6989	(uEAX >> 16) & 0xff);
6990	pHlp->pfnPrintf(pHlp,
6991	"Physical Core Count: %d\n",
6992	((uECX >> 0) & 0xff) + 1);
6993	}
6994	}
6995
6996	pCurLeaf = pNextLeaf;
6997	}
6998
6999
7000
7001	/*
7002	* Centaur.
7003	*/
7004	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7005
7006	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7007	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7008	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7009	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7010	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7011	cMax = RT_MAX(cHstMax, cGstMax);
7012	if (cMax >= UINT32_C(0xc0000000))
7013	{
7014	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7015
7016	/*
7017	* Understandable output
7018	*/
7019	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7020	pHlp->pfnPrintf(pHlp,
7021	"Centaur Supports: 0xc0000000-%#010x\n",
7022	pCurLeaf->uEax);
7023
7024	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7025	{
7026	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7027	uint32_t uEdxGst = pCurLeaf->uEdx;
7028	uint32_t uEdxHst = Host.uEdx;
7029
7030	if (iVerbosity == 1)
7031	{
7032	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7033	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7034	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7035	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7036	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7037	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7038	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7039	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7040	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7041	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7042	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7043	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7044	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7045	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7046	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7047	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7048	for (unsigned iBit = 14; iBit < 32; iBit++)
7049	if (uEdxGst & RT_BIT(iBit))
7050	pHlp->pfnPrintf(pHlp, " %d", iBit);
7051	pHlp->pfnPrintf(pHlp, "\n");
7052	}
7053	else
7054	{
7055	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7056	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7057	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7058	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7059	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7060	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7061	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7062	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7063	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7064	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7065	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7066	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7067	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7068	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7069	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7070	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7071	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7072	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7073	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7074	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7075	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7076	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7077	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7078	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7079	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7080	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7081	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7082	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7083	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7084	for (unsigned iBit = 27; iBit < 32; iBit++)
7085	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7086	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7087	pHlp->pfnPrintf(pHlp, "\n");
7088	}
7089	}
7090
7091	pCurLeaf = pNextLeaf;
7092	}
7093
7094	/*
7095	* The remainder.
7096	*/
7097	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7098	}
7099
7100
7101
7102
7103
7104	/*
7105	*
7106	*
7107	* PATM interfaces.
7108	* PATM interfaces.
7109	* PATM interfaces.
7110	*
7111	*
7112	*/
7113
7114
7115	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
7116	/** @name Patchmanager CPUID legacy table APIs
7117	* @{
7118	*/
7119
7120	/**
7121	* Gets a pointer to the default CPUID leaf.
7122	*
7123	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
7124	* @param pVM The cross context VM structure.
7125	* @remark Intended for PATM only.
7126	*/
7127	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
7128	{
7129	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
7130	}
7131
7132
7133	/**
7134	* Gets a number of standard CPUID leaves (PATM only).
7135	*
7136	* @returns Number of leaves.
7137	* @param pVM The cross context VM structure.
7138	* @remark Intended for PATM - legacy, don't use in new code.
7139	*/
7140	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
7141	{
7142	RT_NOREF_PV(pVM);
7143	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
7144	}
7145
7146
7147	/**
7148	* Gets a number of extended CPUID leaves (PATM only).
7149	*
7150	* @returns Number of leaves.
7151	* @param pVM The cross context VM structure.
7152	* @remark Intended for PATM - legacy, don't use in new code.
7153	*/
7154	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
7155	{
7156	RT_NOREF_PV(pVM);
7157	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
7158	}
7159
7160
7161	/**
7162	* Gets a number of centaur CPUID leaves.
7163	*
7164	* @returns Number of leaves.
7165	* @param pVM The cross context VM structure.
7166	* @remark Intended for PATM - legacy, don't use in new code.
7167	*/
7168	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
7169	{
7170	RT_NOREF_PV(pVM);
7171	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
7172	}
7173
7174
7175	/**
7176	* Gets a pointer to the array of standard CPUID leaves.
7177	*
7178	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
7179	*
7180	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
7181	* @param pVM The cross context VM structure.
7182	* @remark Intended for PATM - legacy, don't use in new code.
7183	*/
7184	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
7185	{
7186	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
7187	}
7188
7189
7190	/**
7191	* Gets a pointer to the array of extended CPUID leaves.
7192	*
7193	* CPUMGetGuestCpuIdExtMax() give the size of the array.
7194	*
7195	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
7196	* @param pVM The cross context VM structure.
7197	* @remark Intended for PATM - legacy, don't use in new code.
7198	*/
7199	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
7200	{
7201	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
7202	}
7203
7204
7205	/**
7206	* Gets a pointer to the array of centaur CPUID leaves.
7207	*
7208	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
7209	*
7210	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
7211	* @param pVM The cross context VM structure.
7212	* @remark Intended for PATM - legacy, don't use in new code.
7213	*/
7214	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
7215	{
7216	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
7217	}
7218
7219	/** @} */
7220	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
7221
7222	#endif /* VBOX_IN_VMM */
7223

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 72489

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