CPUMR3CpuId.cpp@ 73269

Last change on this file since 73269 was 73235, checked in by vboxsync, 6 years ago
VMM/CPUM: Nested VMX: bugref:9180 Disable nested hw.virt for NEM.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 337.3 KB

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1	/* $Id: CPUMR3CpuId.cpp 73235 2018-07-19 10:52:25Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/mm.h>
31	#include <VBox/sup.h>
32
33	#include <VBox/err.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/ctype.h>
36	#include <iprt/mem.h>
37	#include <iprt/string.h>
38
39
40	/*********************************************************************************************************************************
41	* Defined Constants And Macros *
42	*********************************************************************************************************************************/
43	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
44	#define CPUM_CPUID_MAX_LEAVES 2048
45	/* Max size we accept for the XSAVE area. */
46	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
47	/* Min size we accept for the XSAVE area. */
48	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
49
50
51	/*********************************************************************************************************************************
52	* Global Variables *
53	*********************************************************************************************************************************/
54	/**
55	* The intel pentium family.
56	*/
57	static const CPUMMICROARCH g_aenmIntelFamily06[] =
58	{
59	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
60	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
61	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
63	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
64	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
65	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
66	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
67	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
68	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
69	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
70	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
71	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
72	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
73	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
74	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
75	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
81	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
82	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
83	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
86	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
88	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
89	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
90	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
91	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
97	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
98	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
99	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
102	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
104	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
105	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
106	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
107	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
113	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
114	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
115	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
118	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
121	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
122	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
130	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
131	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
136	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [78(0x4e)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed */
138	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / unconfirmed, Broadwell-E */
139	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu */
145	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
146	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
147	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
150	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
152	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
153	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
154	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
155	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
159	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
160	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
161	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
162	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
163	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
164	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
165	/[106(0x6a)] = / kCpumMicroarch_Intel_Unknown,
166	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
167	/[108(0x6c)] = / kCpumMicroarch_Intel_Unknown,
168	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
169	/[110(0x6e)] = / kCpumMicroarch_Intel_Unknown,
170	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
171	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
172	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
173	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
174	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
175	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
176	/[117(0x75)] = / kCpumMicroarch_Intel_Unknown,
177	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
178	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
179	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
180	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
181	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
182	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
183	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
184	/[125(0x7d)] = / kCpumMicroarch_Intel_Unknown,
185	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
186	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
187	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
188	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
189	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
190	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
191	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
192	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
193	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
194	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
195	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
196	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
197	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
198	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
199	/[140(0x8c)] = / kCpumMicroarch_Intel_Unknown,
200	/[141(0x8d)] = / kCpumMicroarch_Intel_Unknown,
201	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
202	/[143(0x8f)] = / kCpumMicroarch_Intel_Unknown,
203	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
204	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
205	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
206	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
207	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
208	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
209	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
210	/[151(0x97)] = / kCpumMicroarch_Intel_Unknown,
211	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
212	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
213	/[154(0x9a)] = / kCpumMicroarch_Intel_Unknown,
214	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
215	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
216	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
217	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
218	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
219	};
220	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0x9f+1);
221
222
223	/**
224	* Figures out the (sub-)micro architecture given a bit of CPUID info.
225	*
226	* @returns Micro architecture.
227	* @param enmVendor The CPU vendor .
228	* @param bFamily The CPU family.
229	* @param bModel The CPU model.
230	* @param bStepping The CPU stepping.
231	*/
232	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
233	uint8_t bModel, uint8_t bStepping)
234	{
235	if (enmVendor == CPUMCPUVENDOR_AMD)
236	{
237	switch (bFamily)
238	{
239	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
240	case 0x03: return kCpumMicroarch_AMD_Am386;
241	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
242	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
243	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
244	case 0x06:
245	switch (bModel)
246	{
247	case 0: return kCpumMicroarch_AMD_K7_Palomino;
248	case 1: return kCpumMicroarch_AMD_K7_Palomino;
249	case 2: return kCpumMicroarch_AMD_K7_Palomino;
250	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
251	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
252	case 6: return kCpumMicroarch_AMD_K7_Palomino;
253	case 7: return kCpumMicroarch_AMD_K7_Morgan;
254	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
255	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
256	}
257	return kCpumMicroarch_AMD_K7_Unknown;
258	case 0x0f:
259	/*
260	* This family is a friggin mess. Trying my best to make some
261	* sense out of it. Too much happened in the 0x0f family to
262	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
263	*
264	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
265	* cpu-world.com, and other places:
266	* - 130nm:
267	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
268	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
269	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
270	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
271	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
272	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
273	* - 90nm:
274	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
275	* - Oakville: 10FC0/DH-D0.
276	* - Georgetown: 10FC0/DH-D0.
277	* - Sonora: 10FC0/DH-D0.
278	* - Venus: 20F71/SH-E4
279	* - Troy: 20F51/SH-E4
280	* - Athens: 20F51/SH-E4
281	* - San Diego: 20F71/SH-E4.
282	* - Lancaster: 20F42/SH-E5
283	* - Newark: 20F42/SH-E5.
284	* - Albany: 20FC2/DH-E6.
285	* - Roma: 20FC2/DH-E6.
286	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
287	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
288	* - 90nm introducing Dual core:
289	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
290	* - Italy: 20F10/JH-E1, 20F12/JH-E6
291	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
292	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
293	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
294	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
295	* - Santa Ana: 40F32/JH-F2, /-F3
296	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
297	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
298	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
299	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
300	* - Keene: 40FC2/DH-F2.
301	* - Richmond: 40FC2/DH-F2
302	* - Taylor: 40F82/BH-F2
303	* - Trinidad: 40F82/BH-F2
304	*
305	* - 65nm:
306	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
307	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
308	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
309	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
310	* - Sherman: /-G1, 70FC2/DH-G2.
311	* - Huron: 70FF2/DH-G2.
312	*/
313	if (bModel < 0x10)
314	return kCpumMicroarch_AMD_K8_130nm;
315	if (bModel >= 0x60 && bModel < 0x80)
316	return kCpumMicroarch_AMD_K8_65nm;
317	if (bModel >= 0x40)
318	return kCpumMicroarch_AMD_K8_90nm_AMDV;
319	switch (bModel)
320	{
321	case 0x21:
322	case 0x23:
323	case 0x2b:
324	case 0x2f:
325	case 0x37:
326	case 0x3f:
327	return kCpumMicroarch_AMD_K8_90nm_DualCore;
328	}
329	return kCpumMicroarch_AMD_K8_90nm;
330	case 0x10:
331	return kCpumMicroarch_AMD_K10;
332	case 0x11:
333	return kCpumMicroarch_AMD_K10_Lion;
334	case 0x12:
335	return kCpumMicroarch_AMD_K10_Llano;
336	case 0x14:
337	return kCpumMicroarch_AMD_Bobcat;
338	case 0x15:
339	switch (bModel)
340	{
341	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
342	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
343	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
344	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
345	case 0x11: /* ?? */
346	case 0x12: /* ?? */
347	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
348	}
349	return kCpumMicroarch_AMD_15h_Unknown;
350	case 0x16:
351	return kCpumMicroarch_AMD_Jaguar;
352	case 0x17:
353	return kCpumMicroarch_AMD_Zen_Ryzen;
354	}
355	return kCpumMicroarch_AMD_Unknown;
356	}
357
358	if (enmVendor == CPUMCPUVENDOR_INTEL)
359	{
360	switch (bFamily)
361	{
362	case 3:
363	return kCpumMicroarch_Intel_80386;
364	case 4:
365	return kCpumMicroarch_Intel_80486;
366	case 5:
367	return kCpumMicroarch_Intel_P5;
368	case 6:
369	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
370	{
371	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
372	if ( enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake
373	&& bStepping >= 0xa)
374	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
375	return enmMicroArch;
376	}
377	return kCpumMicroarch_Intel_Atom_Unknown;
378	case 15:
379	switch (bModel)
380	{
381	case 0: return kCpumMicroarch_Intel_NB_Willamette;
382	case 1: return kCpumMicroarch_Intel_NB_Willamette;
383	case 2: return kCpumMicroarch_Intel_NB_Northwood;
384	case 3: return kCpumMicroarch_Intel_NB_Prescott;
385	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
386	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
387	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
388	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
389	default: return kCpumMicroarch_Intel_NB_Unknown;
390	}
391	break;
392	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
393	case 0:
394	return kCpumMicroarch_Intel_8086;
395	case 1:
396	return kCpumMicroarch_Intel_80186;
397	case 2:
398	return kCpumMicroarch_Intel_80286;
399	}
400	return kCpumMicroarch_Intel_Unknown;
401	}
402
403	if (enmVendor == CPUMCPUVENDOR_VIA)
404	{
405	switch (bFamily)
406	{
407	case 5:
408	switch (bModel)
409	{
410	case 1: return kCpumMicroarch_Centaur_C6;
411	case 4: return kCpumMicroarch_Centaur_C6;
412	case 8: return kCpumMicroarch_Centaur_C2;
413	case 9: return kCpumMicroarch_Centaur_C3;
414	}
415	break;
416
417	case 6:
418	switch (bModel)
419	{
420	case 5: return kCpumMicroarch_VIA_C3_M2;
421	case 6: return kCpumMicroarch_VIA_C3_C5A;
422	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
423	case 8: return kCpumMicroarch_VIA_C3_C5N;
424	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
425	case 10: return kCpumMicroarch_VIA_C7_C5J;
426	case 15: return kCpumMicroarch_VIA_Isaiah;
427	}
428	break;
429	}
430	return kCpumMicroarch_VIA_Unknown;
431	}
432
433	if (enmVendor == CPUMCPUVENDOR_CYRIX)
434	{
435	switch (bFamily)
436	{
437	case 4:
438	switch (bModel)
439	{
440	case 9: return kCpumMicroarch_Cyrix_5x86;
441	}
442	break;
443
444	case 5:
445	switch (bModel)
446	{
447	case 2: return kCpumMicroarch_Cyrix_M1;
448	case 4: return kCpumMicroarch_Cyrix_MediaGX;
449	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
450	}
451	break;
452
453	case 6:
454	switch (bModel)
455	{
456	case 0: return kCpumMicroarch_Cyrix_M2;
457	}
458	break;
459
460	}
461	return kCpumMicroarch_Cyrix_Unknown;
462	}
463
464	return kCpumMicroarch_Unknown;
465	}
466
467
468	/**
469	* Translates a microarchitecture enum value to the corresponding string
470	* constant.
471	*
472	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
473	* NULL if the value is invalid.
474	*
475	* @param enmMicroarch The enum value to convert.
476	*/
477	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
478	{
479	switch (enmMicroarch)
480	{
481	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
482	CASE_RET_STR(kCpumMicroarch_Intel_8086);
483	CASE_RET_STR(kCpumMicroarch_Intel_80186);
484	CASE_RET_STR(kCpumMicroarch_Intel_80286);
485	CASE_RET_STR(kCpumMicroarch_Intel_80386);
486	CASE_RET_STR(kCpumMicroarch_Intel_80486);
487	CASE_RET_STR(kCpumMicroarch_Intel_P5);
488
489	CASE_RET_STR(kCpumMicroarch_Intel_P6);
490	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
491	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
492
493	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
494	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
495	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
496
497	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
498	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
499
500	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
501	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
502	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
503	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
504	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
505	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
506	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
507	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
508	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
509	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
510	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
511	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
512
513	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
514	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
515	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
516	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
517	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
518	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
519	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
520	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
521
522	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
523	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
524	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
525	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
526	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
527
528	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
529	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
530	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
531	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
532	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
533	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
534	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
535
536	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
537
538	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
539	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
540	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
541	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
542	CASE_RET_STR(kCpumMicroarch_AMD_K5);
543	CASE_RET_STR(kCpumMicroarch_AMD_K6);
544
545	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
546	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
547	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
548	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
549	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
550	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
551	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
552
553	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
554	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
555	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
556	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
557	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
558
559	CASE_RET_STR(kCpumMicroarch_AMD_K10);
560	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
561	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
562	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
563	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
564
565	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
566	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
567	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
568	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
569	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
570
571	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
572
573	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
574
575	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
576
577	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
578	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
579	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
580	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
581	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
582	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
583	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
584	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
585	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
586	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
587	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
588	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
589	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
590
591	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
592	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
593	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
594	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
595	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
596	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
597
598	CASE_RET_STR(kCpumMicroarch_NEC_V20);
599	CASE_RET_STR(kCpumMicroarch_NEC_V30);
600
601	CASE_RET_STR(kCpumMicroarch_Unknown);
602
603	#undef CASE_RET_STR
604	case kCpumMicroarch_Invalid:
605	case kCpumMicroarch_Intel_End:
606	case kCpumMicroarch_Intel_Core2_End:
607	case kCpumMicroarch_Intel_Core7_End:
608	case kCpumMicroarch_Intel_Atom_End:
609	case kCpumMicroarch_Intel_P6_Core_Atom_End:
610	case kCpumMicroarch_Intel_Phi_End:
611	case kCpumMicroarch_Intel_NB_End:
612	case kCpumMicroarch_AMD_K7_End:
613	case kCpumMicroarch_AMD_K8_End:
614	case kCpumMicroarch_AMD_15h_End:
615	case kCpumMicroarch_AMD_16h_End:
616	case kCpumMicroarch_AMD_Zen_End:
617	case kCpumMicroarch_AMD_End:
618	case kCpumMicroarch_VIA_End:
619	case kCpumMicroarch_Cyrix_End:
620	case kCpumMicroarch_NEC_End:
621	case kCpumMicroarch_32BitHack:
622	break;
623	/* no default! */
624	}
625
626	return NULL;
627	}
628
629
630	/**
631	* Determins the host CPU MXCSR mask.
632	*
633	* @returns MXCSR mask.
634	*/
635	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
636	{
637	if ( ASMHasCpuId()
638	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
639	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
640	{
641	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
642	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
643	RT_ZERO(*pState);
644	ASMFxSave(pState);
645	if (pState->MXCSR_MASK == 0)
646	return 0xffbf;
647	return pState->MXCSR_MASK;
648	}
649	return 0;
650	}
651
652
653	/**
654	* Gets a matching leaf in the CPUID leaf array.
655	*
656	* @returns Pointer to the matching leaf, or NULL if not found.
657	* @param paLeaves The CPUID leaves to search. This is sorted.
658	* @param cLeaves The number of leaves in the array.
659	* @param uLeaf The leaf to locate.
660	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
661	*/
662	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
663	{
664	/* Lazy bird does linear lookup here since this is only used for the
665	occational CPUID overrides. */
666	for (uint32_t i = 0; i < cLeaves; i++)
667	if ( paLeaves[i].uLeaf == uLeaf
668	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
669	return &paLeaves[i];
670	return NULL;
671	}
672
673
674	#ifndef IN_VBOX_CPU_REPORT
675	/**
676	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
677	*
678	* @returns true if found, false it not.
679	* @param paLeaves The CPUID leaves to search. This is sorted.
680	* @param cLeaves The number of leaves in the array.
681	* @param uLeaf The leaf to locate.
682	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
683	* @param pLegacy The legacy output leaf.
684	*/
685	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
686	PCPUMCPUID pLegacy)
687	{
688	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
689	if (pLeaf)
690	{
691	pLegacy->uEax = pLeaf->uEax;
692	pLegacy->uEbx = pLeaf->uEbx;
693	pLegacy->uEcx = pLeaf->uEcx;
694	pLegacy->uEdx = pLeaf->uEdx;
695	return true;
696	}
697	return false;
698	}
699	#endif /* IN_VBOX_CPU_REPORT */
700
701
702	/**
703	* Ensures that the CPUID leaf array can hold one more leaf.
704	*
705	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
706	* failure.
707	* @param pVM The cross context VM structure. If NULL, use
708	* the process heap, otherwise the VM's hyper heap.
709	* @param ppaLeaves Pointer to the variable holding the array pointer
710	* (input/output).
711	* @param cLeaves The current array size.
712	*
713	* @remarks This function will automatically update the R0 and RC pointers when
714	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
715	* be the corresponding VM's CPUID arrays (which is asserted).
716	*/
717	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
718	{
719	/*
720	* If pVM is not specified, we're on the regular heap and can waste a
721	* little space to speed things up.
722	*/
723	uint32_t cAllocated;
724	if (!pVM)
725	{
726	cAllocated = RT_ALIGN(cLeaves, 16);
727	if (cLeaves + 1 > cAllocated)
728	{
729	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
730	if (pvNew)
731	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
732	else
733	{
734	RTMemFree(*ppaLeaves);
735	*ppaLeaves = NULL;
736	}
737	}
738	}
739	/*
740	* Otherwise, we're on the hyper heap and are probably just inserting
741	* one or two leaves and should conserve space.
742	*/
743	else
744	{
745	#ifdef IN_VBOX_CPU_REPORT
746	AssertReleaseFailed();
747	#else
748	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
749	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
750
751	size_t cb = cLeaves * sizeof(**ppaLeaves);
752	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
753	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
754	if (RT_SUCCESS(rc))
755	{
756	/* Update the R0 and RC pointers. */
757	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
758	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
759	}
760	else
761	{
762	*ppaLeaves = NULL;
763	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
764	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
765	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
766	}
767	#endif
768	}
769	return *ppaLeaves;
770	}
771
772
773	/**
774	* Append a CPUID leaf or sub-leaf.
775	*
776	* ASSUMES linear insertion order, so we'll won't need to do any searching or
777	* replace anything. Use cpumR3CpuIdInsert() for those cases.
778	*
779	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
780	* the caller need do no more work.
781	* @param ppaLeaves Pointer to the pointer to the array of sorted
782	* CPUID leaves and sub-leaves.
783	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
784	* @param uLeaf The leaf we're adding.
785	* @param uSubLeaf The sub-leaf number.
786	* @param fSubLeafMask The sub-leaf mask.
787	* @param uEax The EAX value.
788	* @param uEbx The EBX value.
789	* @param uEcx The ECX value.
790	* @param uEdx The EDX value.
791	* @param fFlags The flags.
792	*/
793	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
794	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
795	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
796	{
797	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
798	return VERR_NO_MEMORY;
799
800	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
801	Assert( *pcLeaves == 0
802	\|\| pNew[-1].uLeaf < uLeaf
803	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
804
805	pNew->uLeaf = uLeaf;
806	pNew->uSubLeaf = uSubLeaf;
807	pNew->fSubLeafMask = fSubLeafMask;
808	pNew->uEax = uEax;
809	pNew->uEbx = uEbx;
810	pNew->uEcx = uEcx;
811	pNew->uEdx = uEdx;
812	pNew->fFlags = fFlags;
813
814	*pcLeaves += 1;
815	return VINF_SUCCESS;
816	}
817
818
819	/**
820	* Checks that we've updated the CPUID leaves array correctly.
821	*
822	* This is a no-op in non-strict builds.
823	*
824	* @param paLeaves The leaves array.
825	* @param cLeaves The number of leaves.
826	*/
827	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
828	{
829	#ifdef VBOX_STRICT
830	for (uint32_t i = 1; i < cLeaves; i++)
831	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
832	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
833	else
834	{
835	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
836	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
837	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
838	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
839	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
840	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
841	}
842	#else
843	NOREF(paLeaves);
844	NOREF(cLeaves);
845	#endif
846	}
847
848
849	/**
850	* Inserts a CPU ID leaf, replacing any existing ones.
851	*
852	* When inserting a simple leaf where we already got a series of sub-leaves with
853	* the same leaf number (eax), the simple leaf will replace the whole series.
854	*
855	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
856	* host-context heap and has only been allocated/reallocated by the
857	* cpumR3CpuIdEnsureSpace function.
858	*
859	* @returns VBox status code.
860	* @param pVM The cross context VM structure. If NULL, use
861	* the process heap, otherwise the VM's hyper heap.
862	* @param ppaLeaves Pointer to the pointer to the array of sorted
863	* CPUID leaves and sub-leaves. Must be NULL if using
864	* the hyper heap.
865	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
866	* be NULL if using the hyper heap.
867	* @param pNewLeaf Pointer to the data of the new leaf we're about to
868	* insert.
869	*/
870	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
871	{
872	/*
873	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
874	*/
875	if (pVM)
876	{
877	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
878	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
879
880	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
881	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
882	}
883
884	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
885	uint32_t cLeaves = *pcLeaves;
886
887	/*
888	* Validate the new leaf a little.
889	*/
890	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
891	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
892	VERR_INVALID_FLAGS);
893	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
894	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
895	VERR_INVALID_PARAMETER);
896	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
897	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
898	VERR_INVALID_PARAMETER);
899	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
900	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
901	VERR_INVALID_PARAMETER);
902
903	/*
904	* Find insertion point. The lazy bird uses the same excuse as in
905	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
906	*/
907	uint32_t i;
908	if ( cLeaves > 0
909	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
910	{
911	/* Add at end. */
912	i = cLeaves;
913	}
914	else if ( cLeaves > 0
915	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
916	{
917	/* Either replacing the last leaf or dealing with sub-leaves. Spool
918	back to the first sub-leaf to pretend we did the linear search. */
919	i = cLeaves - 1;
920	while ( i > 0
921	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
922	i--;
923	}
924	else
925	{
926	/* Linear search from the start. */
927	i = 0;
928	while ( i < cLeaves
929	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
930	i++;
931	}
932	if ( i < cLeaves
933	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
934	{
935	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
936	{
937	/*
938	* The sub-leaf mask differs, replace all existing leaves with the
939	* same leaf number.
940	*/
941	uint32_t c = 1;
942	while ( i + c < cLeaves
943	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
944	c++;
945	if (c > 1 && i + c < cLeaves)
946	{
947	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
948	*pcLeaves = cLeaves -= c - 1;
949	}
950
951	paLeaves[i] = *pNewLeaf;
952	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
953	return VINF_SUCCESS;
954	}
955
956	/* Find sub-leaf insertion point. */
957	while ( i < cLeaves
958	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
959	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
960	i++;
961
962	/*
963	* If we've got an exactly matching leaf, replace it.
964	*/
965	if ( i < cLeaves
966	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
967	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
968	{
969	paLeaves[i] = *pNewLeaf;
970	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
971	return VINF_SUCCESS;
972	}
973	}
974
975	/*
976	* Adding a new leaf at 'i'.
977	*/
978	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
979	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
980	if (!paLeaves)
981	return VERR_NO_MEMORY;
982
983	if (i < cLeaves)
984	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
985	*pcLeaves += 1;
986	paLeaves[i] = *pNewLeaf;
987
988	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
989	return VINF_SUCCESS;
990	}
991
992
993	#ifndef IN_VBOX_CPU_REPORT
994	/**
995	* Removes a range of CPUID leaves.
996	*
997	* This will not reallocate the array.
998	*
999	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1000	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1001	* @param uFirst The first leaf.
1002	* @param uLast The last leaf.
1003	*/
1004	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1005	{
1006	uint32_t cLeaves = *pcLeaves;
1007
1008	Assert(uFirst <= uLast);
1009
1010	/*
1011	* Find the first one.
1012	*/
1013	uint32_t iFirst = 0;
1014	while ( iFirst < cLeaves
1015	&& paLeaves[iFirst].uLeaf < uFirst)
1016	iFirst++;
1017
1018	/*
1019	* Find the end (last + 1).
1020	*/
1021	uint32_t iEnd = iFirst;
1022	while ( iEnd < cLeaves
1023	&& paLeaves[iEnd].uLeaf <= uLast)
1024	iEnd++;
1025
1026	/*
1027	* Adjust the array if anything needs removing.
1028	*/
1029	if (iFirst < iEnd)
1030	{
1031	if (iEnd < cLeaves)
1032	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1033	*pcLeaves = cLeaves -= (iEnd - iFirst);
1034	}
1035
1036	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1037	}
1038	#endif /* IN_VBOX_CPU_REPORT */
1039
1040
1041	/**
1042	* Checks if ECX make a difference when reading a given CPUID leaf.
1043	*
1044	* @returns @c true if it does, @c false if it doesn't.
1045	* @param uLeaf The leaf we're reading.
1046	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1047	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1048	* final sub-leaf (for leaf 0xb only).
1049	*/
1050	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1051	{
1052	*pfFinalEcxUnchanged = false;
1053
1054	uint32_t auCur[4];
1055	uint32_t auPrev[4];
1056	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1057
1058	/* Look for sub-leaves. */
1059	uint32_t uSubLeaf = 1;
1060	for (;;)
1061	{
1062	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1063	if (memcmp(auCur, auPrev, sizeof(auCur)))
1064	break;
1065
1066	/* Advance / give up. */
1067	uSubLeaf++;
1068	if (uSubLeaf >= 64)
1069	{
1070	*pcSubLeaves = 1;
1071	return false;
1072	}
1073	}
1074
1075	/* Count sub-leaves. */
1076	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1077	uint32_t cRepeats = 0;
1078	uSubLeaf = 0;
1079	for (;;)
1080	{
1081	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1082
1083	/* Figuring out when to stop isn't entirely straight forward as we need
1084	to cover undocumented behavior up to a point and implementation shortcuts. */
1085
1086	/* 1. Look for more than 4 repeating value sets. */
1087	if ( auCur[0] == auPrev[0]
1088	&& auCur[1] == auPrev[1]
1089	&& ( auCur[2] == auPrev[2]
1090	\|\| ( auCur[2] == uSubLeaf
1091	&& auPrev[2] == uSubLeaf - 1) )
1092	&& auCur[3] == auPrev[3])
1093	{
1094	if ( uLeaf != 0xd
1095	\|\| uSubLeaf >= 64
1096	\|\| ( auCur[0] == 0
1097	&& auCur[1] == 0
1098	&& auCur[2] == 0
1099	&& auCur[3] == 0
1100	&& auPrev[2] == 0) )
1101	cRepeats++;
1102	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1103	break;
1104	}
1105	else
1106	cRepeats = 0;
1107
1108	/* 2. Look for zero values. */
1109	if ( auCur[0] == 0
1110	&& auCur[1] == 0
1111	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1112	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1113	&& uSubLeaf >= cMinLeaves)
1114	{
1115	cRepeats = 0;
1116	break;
1117	}
1118
1119	/* 3. Leaf 0xb level type 0 check. */
1120	if ( uLeaf == 0xb
1121	&& (auCur[2] & 0xff00) == 0
1122	&& (auPrev[2] & 0xff00) == 0)
1123	{
1124	cRepeats = 0;
1125	break;
1126	}
1127
1128	/* 99. Give up. */
1129	if (uSubLeaf >= 128)
1130	{
1131	#ifndef IN_VBOX_CPU_REPORT
1132	/* Ok, limit it according to the documentation if possible just to
1133	avoid annoying users with these detection issues. */
1134	uint32_t cDocLimit = UINT32_MAX;
1135	if (uLeaf == 0x4)
1136	cDocLimit = 4;
1137	else if (uLeaf == 0x7)
1138	cDocLimit = 1;
1139	else if (uLeaf == 0xd)
1140	cDocLimit = 63;
1141	else if (uLeaf == 0xf)
1142	cDocLimit = 2;
1143	if (cDocLimit != UINT32_MAX)
1144	{
1145	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1146	*pcSubLeaves = cDocLimit + 3;
1147	return true;
1148	}
1149	#endif
1150	*pcSubLeaves = UINT32_MAX;
1151	return true;
1152	}
1153
1154	/* Advance. */
1155	uSubLeaf++;
1156	memcpy(auPrev, auCur, sizeof(auCur));
1157	}
1158
1159	/* Standard exit. */
1160	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1161	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1162	if (*pcSubLeaves == 0)
1163	*pcSubLeaves = 1;
1164	return true;
1165	}
1166
1167
1168	/**
1169	* Gets a CPU ID leaf.
1170	*
1171	* @returns VBox status code.
1172	* @param pVM The cross context VM structure.
1173	* @param pLeaf Where to store the found leaf.
1174	* @param uLeaf The leaf to locate.
1175	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1176	*/
1177	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1178	{
1179	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1180	uLeaf, uSubLeaf);
1181	if (pcLeaf)
1182	{
1183	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1184	return VINF_SUCCESS;
1185	}
1186
1187	return VERR_NOT_FOUND;
1188	}
1189
1190
1191	/**
1192	* Inserts a CPU ID leaf, replacing any existing ones.
1193	*
1194	* @returns VBox status code.
1195	* @param pVM The cross context VM structure.
1196	* @param pNewLeaf Pointer to the leaf being inserted.
1197	*/
1198	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1199	{
1200	/*
1201	* Validate parameters.
1202	*/
1203	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1204	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1205
1206	/*
1207	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1208	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1209	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1210	*/
1211	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1212	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1213	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1214	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1215	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1216	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1217	{
1218	return VERR_NOT_SUPPORTED;
1219	}
1220
1221	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1222	}
1223
1224	/**
1225	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1226	*
1227	* @returns VBox status code.
1228	* @param ppaLeaves Where to return the array pointer on success.
1229	* Use RTMemFree to release.
1230	* @param pcLeaves Where to return the size of the array on
1231	* success.
1232	*/
1233	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1234	{
1235	*ppaLeaves = NULL;
1236	*pcLeaves = 0;
1237
1238	/*
1239	* Try out various candidates. This must be sorted!
1240	*/
1241	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1242	{
1243	{ UINT32_C(0x00000000), false },
1244	{ UINT32_C(0x10000000), false },
1245	{ UINT32_C(0x20000000), false },
1246	{ UINT32_C(0x30000000), false },
1247	{ UINT32_C(0x40000000), false },
1248	{ UINT32_C(0x50000000), false },
1249	{ UINT32_C(0x60000000), false },
1250	{ UINT32_C(0x70000000), false },
1251	{ UINT32_C(0x80000000), false },
1252	{ UINT32_C(0x80860000), false },
1253	{ UINT32_C(0x8ffffffe), true },
1254	{ UINT32_C(0x8fffffff), true },
1255	{ UINT32_C(0x90000000), false },
1256	{ UINT32_C(0xa0000000), false },
1257	{ UINT32_C(0xb0000000), false },
1258	{ UINT32_C(0xc0000000), false },
1259	{ UINT32_C(0xd0000000), false },
1260	{ UINT32_C(0xe0000000), false },
1261	{ UINT32_C(0xf0000000), false },
1262	};
1263
1264	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1265	{
1266	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1267	uint32_t uEax, uEbx, uEcx, uEdx;
1268	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1269
1270	/*
1271	* Does EAX look like a typical leaf count value?
1272	*/
1273	if ( uEax > uLeaf
1274	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1275	{
1276	/* Yes, dump them. */
1277	uint32_t cLeaves = uEax - uLeaf + 1;
1278	while (cLeaves-- > 0)
1279	{
1280	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1281
1282	uint32_t fFlags = 0;
1283
1284	/* There are currently three known leaves containing an APIC ID
1285	that needs EMT specific attention */
1286	if (uLeaf == 1)
1287	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1288	else if (uLeaf == 0xb && uEcx != 0)
1289	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1290	else if ( uLeaf == UINT32_C(0x8000001e)
1291	&& ( uEax
1292	\|\| uEbx
1293	\|\| uEdx
1294	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1295	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1296
1297	/* The APIC bit is per-VCpu and needs flagging. */
1298	if (uLeaf == 1)
1299	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1300	else if ( uLeaf == UINT32_C(0x80000001)
1301	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1302	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1303	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1304
1305	/* Check three times here to reduce the chance of CPU migration
1306	resulting in false positives with things like the APIC ID. */
1307	uint32_t cSubLeaves;
1308	bool fFinalEcxUnchanged;
1309	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1310	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1311	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1312	{
1313	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1314	{
1315	/* This shouldn't happen. But in case it does, file all
1316	relevant details in the release log. */
1317	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1318	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1319	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1320	{
1321	uint32_t auTmp[4];
1322	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1323	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1324	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1325	}
1326	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1327	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1328	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1329	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1330	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1331	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1332	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1333	}
1334
1335	if (fFinalEcxUnchanged)
1336	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1337
1338	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1339	{
1340	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1341	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1342	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1343	if (RT_FAILURE(rc))
1344	return rc;
1345	}
1346	}
1347	else
1348	{
1349	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1350	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1351	if (RT_FAILURE(rc))
1352	return rc;
1353	}
1354
1355	/* next */
1356	uLeaf++;
1357	}
1358	}
1359	/*
1360	* Special CPUIDs needs special handling as they don't follow the
1361	* leaf count principle used above.
1362	*/
1363	else if (s_aCandidates[iOuter].fSpecial)
1364	{
1365	bool fKeep = false;
1366	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1367	fKeep = true;
1368	else if ( uLeaf == 0x8fffffff
1369	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1370	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1371	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1372	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1373	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1374	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1375	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1376	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1377	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1378	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1379	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1380	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1381	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1382	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1383	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1384	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1385	fKeep = true;
1386	if (fKeep)
1387	{
1388	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1389	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1390	if (RT_FAILURE(rc))
1391	return rc;
1392	}
1393	}
1394	}
1395
1396	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1397	return VINF_SUCCESS;
1398	}
1399
1400
1401	/**
1402	* Determines the method the CPU uses to handle unknown CPUID leaves.
1403	*
1404	* @returns VBox status code.
1405	* @param penmUnknownMethod Where to return the method.
1406	* @param pDefUnknown Where to return default unknown values. This
1407	* will be set, even if the resulting method
1408	* doesn't actually needs it.
1409	*/
1410	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1411	{
1412	uint32_t uLastStd = ASMCpuId_EAX(0);
1413	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1414	if (!ASMIsValidExtRange(uLastExt))
1415	uLastExt = 0x80000000;
1416
1417	uint32_t auChecks[] =
1418	{
1419	uLastStd + 1,
1420	uLastStd + 5,
1421	uLastStd + 8,
1422	uLastStd + 32,
1423	uLastStd + 251,
1424	uLastExt + 1,
1425	uLastExt + 8,
1426	uLastExt + 15,
1427	uLastExt + 63,
1428	uLastExt + 255,
1429	0x7fbbffcc,
1430	0x833f7872,
1431	0xefff2353,
1432	0x35779456,
1433	0x1ef6d33e,
1434	};
1435
1436	static const uint32_t s_auValues[] =
1437	{
1438	0xa95d2156,
1439	0x00000001,
1440	0x00000002,
1441	0x00000008,
1442	0x00000000,
1443	0x55773399,
1444	0x93401769,
1445	0x12039587,
1446	};
1447
1448	/*
1449	* Simple method, all zeros.
1450	*/
1451	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1452	pDefUnknown->uEax = 0;
1453	pDefUnknown->uEbx = 0;
1454	pDefUnknown->uEcx = 0;
1455	pDefUnknown->uEdx = 0;
1456
1457	/*
1458	* Intel has been observed returning the last standard leaf.
1459	*/
1460	uint32_t auLast[4];
1461	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1462
1463	uint32_t cChecks = RT_ELEMENTS(auChecks);
1464	while (cChecks > 0)
1465	{
1466	uint32_t auCur[4];
1467	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1468	if (memcmp(auCur, auLast, sizeof(auCur)))
1469	break;
1470	cChecks--;
1471	}
1472	if (cChecks == 0)
1473	{
1474	/* Now, what happens when the input changes? Esp. ECX. */
1475	uint32_t cTotal = 0;
1476	uint32_t cSame = 0;
1477	uint32_t cLastWithEcx = 0;
1478	uint32_t cNeither = 0;
1479	uint32_t cValues = RT_ELEMENTS(s_auValues);
1480	while (cValues > 0)
1481	{
1482	uint32_t uValue = s_auValues[cValues - 1];
1483	uint32_t auLastWithEcx[4];
1484	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1485	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1486
1487	cChecks = RT_ELEMENTS(auChecks);
1488	while (cChecks > 0)
1489	{
1490	uint32_t auCur[4];
1491	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1492	if (!memcmp(auCur, auLast, sizeof(auCur)))
1493	{
1494	cSame++;
1495	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1496	cLastWithEcx++;
1497	}
1498	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1499	cLastWithEcx++;
1500	else
1501	cNeither++;
1502	cTotal++;
1503	cChecks--;
1504	}
1505	cValues--;
1506	}
1507
1508	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1509	if (cSame == cTotal)
1510	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1511	else if (cLastWithEcx == cTotal)
1512	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1513	else
1514	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1515	pDefUnknown->uEax = auLast[0];
1516	pDefUnknown->uEbx = auLast[1];
1517	pDefUnknown->uEcx = auLast[2];
1518	pDefUnknown->uEdx = auLast[3];
1519	return VINF_SUCCESS;
1520	}
1521
1522	/*
1523	* Unchanged register values?
1524	*/
1525	cChecks = RT_ELEMENTS(auChecks);
1526	while (cChecks > 0)
1527	{
1528	uint32_t const uLeaf = auChecks[cChecks - 1];
1529	uint32_t cValues = RT_ELEMENTS(s_auValues);
1530	while (cValues > 0)
1531	{
1532	uint32_t uValue = s_auValues[cValues - 1];
1533	uint32_t auCur[4];
1534	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1535	if ( auCur[0] != uLeaf
1536	\|\| auCur[1] != uValue
1537	\|\| auCur[2] != uValue
1538	\|\| auCur[3] != uValue)
1539	break;
1540	cValues--;
1541	}
1542	if (cValues != 0)
1543	break;
1544	cChecks--;
1545	}
1546	if (cChecks == 0)
1547	{
1548	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1549	return VINF_SUCCESS;
1550	}
1551
1552	/*
1553	* Just go with the simple method.
1554	*/
1555	return VINF_SUCCESS;
1556	}
1557
1558
1559	/**
1560	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1561	*
1562	* @returns Read only name string.
1563	* @param enmUnknownMethod The method to translate.
1564	*/
1565	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1566	{
1567	switch (enmUnknownMethod)
1568	{
1569	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1570	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1571	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1572	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1573
1574	case CPUMUNKNOWNCPUID_INVALID:
1575	case CPUMUNKNOWNCPUID_END:
1576	case CPUMUNKNOWNCPUID_32BIT_HACK:
1577	break;
1578	}
1579	return "Invalid-unknown-CPUID-method";
1580	}
1581
1582
1583	/**
1584	* Detect the CPU vendor give n the
1585	*
1586	* @returns The vendor.
1587	* @param uEAX EAX from CPUID(0).
1588	* @param uEBX EBX from CPUID(0).
1589	* @param uECX ECX from CPUID(0).
1590	* @param uEDX EDX from CPUID(0).
1591	*/
1592	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1593	{
1594	if (ASMIsValidStdRange(uEAX))
1595	{
1596	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1597	return CPUMCPUVENDOR_AMD;
1598
1599	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1600	return CPUMCPUVENDOR_INTEL;
1601
1602	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1603	return CPUMCPUVENDOR_VIA;
1604
1605	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1606	&& uECX == UINT32_C(0x64616574)
1607	&& uEDX == UINT32_C(0x736E4978))
1608	return CPUMCPUVENDOR_CYRIX;
1609
1610	/* "Geode by NSC", example: family 5, model 9. */
1611
1612	/** @todo detect the other buggers... */
1613	}
1614
1615	return CPUMCPUVENDOR_UNKNOWN;
1616	}
1617
1618
1619	/**
1620	* Translates a CPU vendor enum value into the corresponding string constant.
1621	*
1622	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1623	* value name. This can be useful when generating code.
1624	*
1625	* @returns Read only name string.
1626	* @param enmVendor The CPU vendor value.
1627	*/
1628	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1629	{
1630	switch (enmVendor)
1631	{
1632	case CPUMCPUVENDOR_INTEL: return "INTEL";
1633	case CPUMCPUVENDOR_AMD: return "AMD";
1634	case CPUMCPUVENDOR_VIA: return "VIA";
1635	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1636	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1637
1638	case CPUMCPUVENDOR_INVALID:
1639	case CPUMCPUVENDOR_32BIT_HACK:
1640	break;
1641	}
1642	return "Invalid-cpu-vendor";
1643	}
1644
1645
1646	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1647	{
1648	/* Could do binary search, doing linear now because I'm lazy. */
1649	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1650	while (cLeaves-- > 0)
1651	{
1652	if (pLeaf->uLeaf == uLeaf)
1653	return pLeaf;
1654	pLeaf++;
1655	}
1656	return NULL;
1657	}
1658
1659
1660	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1661	{
1662	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1663	if ( !pLeaf
1664	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1665	return pLeaf;
1666
1667	/* Linear sub-leaf search. Lazy as usual. */
1668	cLeaves -= pLeaf - paLeaves;
1669	while ( cLeaves-- > 0
1670	&& pLeaf->uLeaf == uLeaf)
1671	{
1672	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1673	return pLeaf;
1674	pLeaf++;
1675	}
1676
1677	return NULL;
1678	}
1679
1680
1681	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1682	{
1683	RT_ZERO(*pFeatures);
1684	if (cLeaves >= 2)
1685	{
1686	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1687	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1688	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1689	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1690	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1691	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1692
1693	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1694	pStd0Leaf->uEbx,
1695	pStd0Leaf->uEcx,
1696	pStd0Leaf->uEdx);
1697	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1698	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1699	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1700	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1701	pFeatures->uFamily,
1702	pFeatures->uModel,
1703	pFeatures->uStepping);
1704
1705	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1706	if (pExtLeaf8)
1707	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1708	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1709	pFeatures->cMaxPhysAddrWidth = 36;
1710	else
1711	pFeatures->cMaxPhysAddrWidth = 32;
1712
1713	/* Standard features. */
1714	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1715	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1716	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1717	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1718	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1719	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1720	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1721	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1722	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1723	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1724	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1725	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1726	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1727	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1728	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1729	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1730	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1731	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1732	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1733	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1734	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1735	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1736	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1737	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1738	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1739	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1740
1741	/* Structured extended features. */
1742	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1743	if (pSxfLeaf0)
1744	{
1745	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1746	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1747	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1748	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1749	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1750
1751	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1752	pFeatures->fIbrs = pFeatures->fIbpb;
1753	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1754	#if 0 // Disabled until IA32_ARCH_CAPABILITIES support can be tested
1755	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1756	#endif
1757	}
1758
1759	/* MWAIT/MONITOR leaf. */
1760	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1761	if (pMWaitLeaf)
1762	{
1763	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1764	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1765	}
1766
1767	/* Extended features. */
1768	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1769	if (pExtLeaf)
1770	{
1771	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1772	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1773	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1774	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1775	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1776	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1777	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1778	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1779	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1780	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1781	}
1782
1783	if ( pExtLeaf
1784	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1785	{
1786	/* AMD features. */
1787	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1788	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1789	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1790	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1791	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1792	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1793	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1794	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1795	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1796	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1797	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1798	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1799	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1800	if (pFeatures->fSvm)
1801	{
1802	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1803	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1804	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1805	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1806	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1807	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1808	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1809	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1810	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1811	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1812	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1813	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1814	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1815	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1816	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1817	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1818	}
1819	}
1820
1821	/*
1822	* Quirks.
1823	*/
1824	pFeatures->fLeakyFxSR = pExtLeaf
1825	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1826	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1827	&& pFeatures->uFamily >= 6 /* K7 and up */;
1828
1829	/*
1830	* Max extended (/FPU) state.
1831	*/
1832	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1833	if (pFeatures->fXSaveRstor)
1834	{
1835	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1836	if (pXStateLeaf0)
1837	{
1838	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1839	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1840	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1841	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1842	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1843	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1844	{
1845	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1846
1847	/* (paranoia:) */
1848	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1849	if ( pXStateLeaf1
1850	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1851	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1852	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1853	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1854	}
1855	else
1856	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1857	pFeatures->fXSaveRstor = 0);
1858	}
1859	else
1860	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1861	pFeatures->fXSaveRstor = 0);
1862	}
1863	}
1864	else
1865	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1866	return VINF_SUCCESS;
1867	}
1868
1869
1870	/*
1871	*
1872	* Init related code.
1873	* Init related code.
1874	* Init related code.
1875	*
1876	*
1877	*/
1878	#ifdef VBOX_IN_VMM
1879
1880
1881	/**
1882	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1883	*
1884	* This ignores the fSubLeafMask.
1885	*
1886	* @returns Pointer to the matching leaf, or NULL if not found.
1887	* @param paLeaves The CPUID leaves to search. This is sorted.
1888	* @param cLeaves The number of leaves in the array.
1889	* @param uLeaf The leaf to locate.
1890	* @param uSubLeaf The subleaf to locate.
1891	*/
1892	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1893	{
1894	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1895	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1896	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1897	if (iEnd)
1898	{
1899	uint32_t iBegin = 0;
1900	for (;;)
1901	{
1902	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1903	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1904	if (uNeedle < uCur)
1905	{
1906	if (i > iBegin)
1907	iEnd = i;
1908	else
1909	break;
1910	}
1911	else if (uNeedle > uCur)
1912	{
1913	if (i + 1 < iEnd)
1914	iBegin = i + 1;
1915	else
1916	break;
1917	}
1918	else
1919	return &paLeaves[i];
1920	}
1921	}
1922	return NULL;
1923	}
1924
1925
1926	/**
1927	* Loads MSR range overrides.
1928	*
1929	* This must be called before the MSR ranges are moved from the normal heap to
1930	* the hyper heap!
1931	*
1932	* @returns VBox status code (VMSetError called).
1933	* @param pVM The cross context VM structure.
1934	* @param pMsrNode The CFGM node with the MSR overrides.
1935	*/
1936	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1937	{
1938	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1939	{
1940	/*
1941	* Assemble a valid MSR range.
1942	*/
1943	CPUMMSRRANGE MsrRange;
1944	MsrRange.offCpumCpu = 0;
1945	MsrRange.fReserved = 0;
1946
1947	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1948	if (RT_FAILURE(rc))
1949	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1950
1951	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1952	if (RT_FAILURE(rc))
1953	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1954	MsrRange.szName, rc);
1955
1956	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1957	if (RT_FAILURE(rc))
1958	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1959	MsrRange.szName, rc);
1960
1961	char szType[32];
1962	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1963	if (RT_FAILURE(rc))
1964	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1965	MsrRange.szName, rc);
1966	if (!RTStrICmp(szType, "FixedValue"))
1967	{
1968	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1969	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1970
1971	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1972	if (RT_FAILURE(rc))
1973	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1974	MsrRange.szName, rc);
1975
1976	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1977	if (RT_FAILURE(rc))
1978	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1979	MsrRange.szName, rc);
1980
1981	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1982	if (RT_FAILURE(rc))
1983	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1984	MsrRange.szName, rc);
1985	}
1986	else
1987	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1988	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1989
1990	/*
1991	* Insert the range into the table (replaces/splits/shrinks existing
1992	* MSR ranges).
1993	*/
1994	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1995	&MsrRange);
1996	if (RT_FAILURE(rc))
1997	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
1998	}
1999
2000	return VINF_SUCCESS;
2001	}
2002
2003
2004	/**
2005	* Loads CPUID leaf overrides.
2006	*
2007	* This must be called before the CPUID leaves are moved from the normal
2008	* heap to the hyper heap!
2009	*
2010	* @returns VBox status code (VMSetError called).
2011	* @param pVM The cross context VM structure.
2012	* @param pParentNode The CFGM node with the CPUID leaves.
2013	* @param pszLabel How to label the overrides we're loading.
2014	*/
2015	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2016	{
2017	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2018	{
2019	/*
2020	* Get the leaf and subleaf numbers.
2021	*/
2022	char szName[128];
2023	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2024	if (RT_FAILURE(rc))
2025	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2026
2027	/* The leaf number is either specified directly or thru the node name. */
2028	uint32_t uLeaf;
2029	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2030	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2031	{
2032	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2033	if (rc != VINF_SUCCESS)
2034	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2035	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2036	}
2037	else if (RT_FAILURE(rc))
2038	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2039	pszLabel, szName, rc);
2040
2041	uint32_t uSubLeaf;
2042	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2043	if (RT_FAILURE(rc))
2044	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2045	pszLabel, szName, rc);
2046
2047	uint32_t fSubLeafMask;
2048	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2049	if (RT_FAILURE(rc))
2050	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2051	pszLabel, szName, rc);
2052
2053	/*
2054	* Look up the specified leaf, since the output register values
2055	* defaults to any existing values. This allows overriding a single
2056	* register, without needing to know the other values.
2057	*/
2058	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2059	CPUMCPUIDLEAF Leaf;
2060	if (pLeaf)
2061	Leaf = *pLeaf;
2062	else
2063	RT_ZERO(Leaf);
2064	Leaf.uLeaf = uLeaf;
2065	Leaf.uSubLeaf = uSubLeaf;
2066	Leaf.fSubLeafMask = fSubLeafMask;
2067
2068	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2069	if (RT_FAILURE(rc))
2070	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2071	pszLabel, szName, rc);
2072	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2073	if (RT_FAILURE(rc))
2074	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2075	pszLabel, szName, rc);
2076	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2077	if (RT_FAILURE(rc))
2078	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2079	pszLabel, szName, rc);
2080	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2081	if (RT_FAILURE(rc))
2082	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2083	pszLabel, szName, rc);
2084
2085	/*
2086	* Insert the leaf into the table (replaces existing ones).
2087	*/
2088	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2089	&Leaf);
2090	if (RT_FAILURE(rc))
2091	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2092	}
2093
2094	return VINF_SUCCESS;
2095	}
2096
2097
2098
2099	/**
2100	* Fetches overrides for a CPUID leaf.
2101	*
2102	* @returns VBox status code.
2103	* @param pLeaf The leaf to load the overrides into.
2104	* @param pCfgNode The CFGM node containing the overrides
2105	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2106	* @param iLeaf The CPUID leaf number.
2107	*/
2108	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2109	{
2110	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2111	if (pLeafNode)
2112	{
2113	uint32_t u32;
2114	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2115	if (RT_SUCCESS(rc))
2116	pLeaf->uEax = u32;
2117	else
2118	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2119
2120	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2121	if (RT_SUCCESS(rc))
2122	pLeaf->uEbx = u32;
2123	else
2124	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2125
2126	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2127	if (RT_SUCCESS(rc))
2128	pLeaf->uEcx = u32;
2129	else
2130	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2131
2132	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2133	if (RT_SUCCESS(rc))
2134	pLeaf->uEdx = u32;
2135	else
2136	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2137
2138	}
2139	return VINF_SUCCESS;
2140	}
2141
2142
2143	/**
2144	* Load the overrides for a set of CPUID leaves.
2145	*
2146	* @returns VBox status code.
2147	* @param paLeaves The leaf array.
2148	* @param cLeaves The number of leaves.
2149	* @param uStart The start leaf number.
2150	* @param pCfgNode The CFGM node containing the overrides
2151	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2152	*/
2153	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2154	{
2155	for (uint32_t i = 0; i < cLeaves; i++)
2156	{
2157	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2158	if (RT_FAILURE(rc))
2159	return rc;
2160	}
2161
2162	return VINF_SUCCESS;
2163	}
2164
2165
2166	/**
2167	* Installs the CPUID leaves and explods the data into structures like
2168	* GuestFeatures and CPUMCTX::aoffXState.
2169	*
2170	* @returns VBox status code.
2171	* @param pVM The cross context VM structure.
2172	* @param pCpum The CPUM part of @a VM.
2173	* @param paLeaves The leaves. These will be copied (but not freed).
2174	* @param cLeaves The number of leaves.
2175	*/
2176	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
2177	{
2178	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2179
2180	/*
2181	* Install the CPUID information.
2182	*/
2183	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2184	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2185
2186	AssertLogRelRCReturn(rc, rc);
2187	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2188	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2189	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2190	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2191	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2192
2193	/*
2194	* Update the default CPUID leaf if necessary.
2195	*/
2196	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2197	{
2198	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2199	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2200	{
2201	/* We don't use CPUID(0).eax here because of the NT hack that only
2202	changes that value without actually removing any leaves. */
2203	uint32_t i = 0;
2204	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2205	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2206	{
2207	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2208	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2209	i++;
2210	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2211	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2212	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2213	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2214	}
2215	break;
2216	}
2217	default:
2218	break;
2219	}
2220
2221	/*
2222	* Explode the guest CPU features.
2223	*/
2224	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
2225	AssertLogRelRCReturn(rc, rc);
2226
2227	/*
2228	* Adjust the scalable bus frequency according to the CPUID information
2229	* we're now using.
2230	*/
2231	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2232	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2233	? UINT64_C(100000000) /* 100MHz */
2234	: UINT64_C(133333333); /* 133MHz */
2235
2236	/*
2237	* Populate the legacy arrays. Currently used for everything, later only
2238	* for patch manager.
2239	*/
2240	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2241	{
2242	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2243	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2244	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2245	};
2246	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2247	{
2248	uint32_t cLeft = aOldRanges[i].cCpuIds;
2249	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2250	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2251	while (cLeft-- > 0)
2252	{
2253	uLeaf--;
2254	pLegacyLeaf--;
2255
2256	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2257	if (pLeaf)
2258	{
2259	pLegacyLeaf->uEax = pLeaf->uEax;
2260	pLegacyLeaf->uEbx = pLeaf->uEbx;
2261	pLegacyLeaf->uEcx = pLeaf->uEcx;
2262	pLegacyLeaf->uEdx = pLeaf->uEdx;
2263	}
2264	else
2265	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2266	}
2267	}
2268
2269	/*
2270	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2271	*/
2272	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2273	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2274	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2275	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2276	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2277	{
2278	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2279	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2280	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2281	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2282	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2283	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2284	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2285	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2286	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2287	pCpum->GuestFeatures.cbMaxExtendedState),
2288	VERR_CPUM_IPE_1);
2289	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2290	}
2291	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2292
2293	/* Copy the CPU #0 data to the other CPUs. */
2294	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2295	{
2296	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2297	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2298	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2299	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2300	}
2301
2302	return VINF_SUCCESS;
2303	}
2304
2305
2306	/** @name Instruction Set Extension Options
2307	* @{ */
2308	/** Configuration option type (extended boolean, really). */
2309	typedef uint8_t CPUMISAEXTCFG;
2310	/** Always disable the extension. */
2311	#define CPUMISAEXTCFG_DISABLED false
2312	/** Enable the extension if it's supported by the host CPU. */
2313	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2314	/** Enable the extension if it's supported by the host CPU, but don't let
2315	* the portable CPUID feature disable it. */
2316	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2317	/** Always enable the extension. */
2318	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2319	/** @} */
2320
2321	/**
2322	* CPUID Configuration (from CFGM).
2323	*
2324	* @remarks The members aren't document since we would only be duplicating the
2325	* \@cfgm entries in cpumR3CpuIdReadConfig.
2326	*/
2327	typedef struct CPUMCPUIDCONFIG
2328	{
2329	bool fNt4LeafLimit;
2330	bool fInvariantTsc;
2331	bool fForceVme;
2332	bool fNestedHWVirt;
2333
2334	CPUMISAEXTCFG enmCmpXchg16b;
2335	CPUMISAEXTCFG enmMonitor;
2336	CPUMISAEXTCFG enmMWaitExtensions;
2337	CPUMISAEXTCFG enmSse41;
2338	CPUMISAEXTCFG enmSse42;
2339	CPUMISAEXTCFG enmAvx;
2340	CPUMISAEXTCFG enmAvx2;
2341	CPUMISAEXTCFG enmXSave;
2342	CPUMISAEXTCFG enmAesNi;
2343	CPUMISAEXTCFG enmPClMul;
2344	CPUMISAEXTCFG enmPopCnt;
2345	CPUMISAEXTCFG enmMovBe;
2346	CPUMISAEXTCFG enmRdRand;
2347	CPUMISAEXTCFG enmRdSeed;
2348	CPUMISAEXTCFG enmCLFlushOpt;
2349	CPUMISAEXTCFG enmFsGsBase;
2350	CPUMISAEXTCFG enmPcid;
2351	CPUMISAEXTCFG enmInvpcid;
2352
2353	CPUMISAEXTCFG enmAbm;
2354	CPUMISAEXTCFG enmSse4A;
2355	CPUMISAEXTCFG enmMisAlnSse;
2356	CPUMISAEXTCFG enm3dNowPrf;
2357	CPUMISAEXTCFG enmAmdExtMmx;
2358
2359	uint32_t uMaxStdLeaf;
2360	uint32_t uMaxExtLeaf;
2361	uint32_t uMaxCentaurLeaf;
2362	uint32_t uMaxIntelFamilyModelStep;
2363	char szCpuName[128];
2364	} CPUMCPUIDCONFIG;
2365	/** Pointer to CPUID config (from CFGM). */
2366	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2367
2368
2369	/**
2370	* Mini CPU selection support for making Mac OS X happy.
2371	*
2372	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2373	*
2374	* @param pCpum The CPUM instance data.
2375	* @param pConfig The CPUID configuration we've read from CFGM.
2376	*/
2377	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2378	{
2379	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2380	{
2381	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2382	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2383	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2384	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2385	0);
2386	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2387	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2388	{
2389	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2390	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2391	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2392	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2393	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2394	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2395	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2396	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2397	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2398	pStdFeatureLeaf->uEax = uNew;
2399	}
2400	}
2401	}
2402
2403
2404
2405	/**
2406	* Limit it the number of entries, zapping the remainder.
2407	*
2408	* The limits are masking off stuff about power saving and similar, this
2409	* is perhaps a bit crudely done as there is probably some relatively harmless
2410	* info too in these leaves (like words about having a constant TSC).
2411	*
2412	* @param pCpum The CPUM instance data.
2413	* @param pConfig The CPUID configuration we've read from CFGM.
2414	*/
2415	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2416	{
2417	/*
2418	* Standard leaves.
2419	*/
2420	uint32_t uSubLeaf = 0;
2421	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2422	if (pCurLeaf)
2423	{
2424	uint32_t uLimit = pCurLeaf->uEax;
2425	if (uLimit <= UINT32_C(0x000fffff))
2426	{
2427	if (uLimit > pConfig->uMaxStdLeaf)
2428	{
2429	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2430	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2431	uLimit + 1, UINT32_C(0x000fffff));
2432	}
2433
2434	/* NT4 hack, no zapping of extra leaves here. */
2435	if (pConfig->fNt4LeafLimit && uLimit > 3)
2436	pCurLeaf->uEax = uLimit = 3;
2437
2438	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2439	pCurLeaf->uEax = uLimit;
2440	}
2441	else
2442	{
2443	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2444	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2445	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2446	}
2447	}
2448
2449	/*
2450	* Extended leaves.
2451	*/
2452	uSubLeaf = 0;
2453	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2454	if (pCurLeaf)
2455	{
2456	uint32_t uLimit = pCurLeaf->uEax;
2457	if ( uLimit >= UINT32_C(0x80000000)
2458	&& uLimit <= UINT32_C(0x800fffff))
2459	{
2460	if (uLimit > pConfig->uMaxExtLeaf)
2461	{
2462	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2463	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2464	uLimit + 1, UINT32_C(0x800fffff));
2465	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2466	pCurLeaf->uEax = uLimit;
2467	}
2468	}
2469	else
2470	{
2471	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2472	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2473	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2474	}
2475	}
2476
2477	/*
2478	* Centaur leaves (VIA).
2479	*/
2480	uSubLeaf = 0;
2481	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2482	if (pCurLeaf)
2483	{
2484	uint32_t uLimit = pCurLeaf->uEax;
2485	if ( uLimit >= UINT32_C(0xc0000000)
2486	&& uLimit <= UINT32_C(0xc00fffff))
2487	{
2488	if (uLimit > pConfig->uMaxCentaurLeaf)
2489	{
2490	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2491	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2492	uLimit + 1, UINT32_C(0xcfffffff));
2493	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2494	pCurLeaf->uEax = uLimit;
2495	}
2496	}
2497	else
2498	{
2499	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2500	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2501	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2502	}
2503	}
2504	}
2505
2506
2507	/**
2508	* Clears a CPUID leaf and all sub-leaves (to zero).
2509	*
2510	* @param pCpum The CPUM instance data.
2511	* @param uLeaf The leaf to clear.
2512	*/
2513	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2514	{
2515	uint32_t uSubLeaf = 0;
2516	PCPUMCPUIDLEAF pCurLeaf;
2517	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2518	{
2519	pCurLeaf->uEax = 0;
2520	pCurLeaf->uEbx = 0;
2521	pCurLeaf->uEcx = 0;
2522	pCurLeaf->uEdx = 0;
2523	uSubLeaf++;
2524	}
2525	}
2526
2527
2528	/**
2529	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2530	* the given leaf.
2531	*
2532	* @returns pLeaf.
2533	* @param pCpum The CPUM instance data.
2534	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2535	*/
2536	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2537	{
2538	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2539	if (pLeaf->fSubLeafMask != 0)
2540	{
2541	/*
2542	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2543	* Log everything while we're at it.
2544	*/
2545	LogRel(("CPUM:\n"
2546	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2547	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2548	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2549	for (;;)
2550	{
2551	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2552	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2553	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2554	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2555	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2556	break;
2557	pSubLeaf++;
2558	}
2559	LogRel(("CPUM:\n"));
2560
2561	/*
2562	* Remove the offending sub-leaves.
2563	*/
2564	if (pSubLeaf != pLeaf)
2565	{
2566	if (pSubLeaf != pLast)
2567	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2568	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2569	}
2570
2571	/*
2572	* Convert the first sub-leaf into a single leaf.
2573	*/
2574	pLeaf->uSubLeaf = 0;
2575	pLeaf->fSubLeafMask = 0;
2576	}
2577	return pLeaf;
2578	}
2579
2580
2581	/**
2582	* Sanitizes and adjust the CPUID leaves.
2583	*
2584	* Drop features that aren't virtualized (or virtualizable). Adjust information
2585	* and capabilities to fit the virtualized hardware. Remove information the
2586	* guest shouldn't have (because it's wrong in the virtual world or because it
2587	* gives away host details) or that we don't have documentation for and no idea
2588	* what means.
2589	*
2590	* @returns VBox status code.
2591	* @param pVM The cross context VM structure (for cCpus).
2592	* @param pCpum The CPUM instance data.
2593	* @param pConfig The CPUID configuration we've read from CFGM.
2594	*/
2595	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2596	{
2597	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2598	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2599	{ \
2600	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2601	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2602	}
2603	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2604	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2605	{ \
2606	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2607	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2608	}
2609	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2610	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2611	&& ((a_pLeafReg) & (fBitMask)) \
2612	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2613	{ \
2614	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2615	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2616	}
2617	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2618
2619	/* Cpuid 1:
2620	* EAX: CPU model, family and stepping.
2621	*
2622	* ECX + EDX: Supported features. Only report features we can support.
2623	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2624	* options may require adjusting (i.e. stripping what was enabled).
2625	*
2626	* EBX: Branding, CLFLUSH line size, logical processors per package and
2627	* initial APIC ID.
2628	*/
2629	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2630	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2631	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2632
2633	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2634	\| X86_CPUID_FEATURE_EDX_VME
2635	\| X86_CPUID_FEATURE_EDX_DE
2636	\| X86_CPUID_FEATURE_EDX_PSE
2637	\| X86_CPUID_FEATURE_EDX_TSC
2638	\| X86_CPUID_FEATURE_EDX_MSR
2639	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2640	\| X86_CPUID_FEATURE_EDX_MCE
2641	\| X86_CPUID_FEATURE_EDX_CX8
2642	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2643	//\| RT_BIT_32(10) - not defined
2644	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2645	//\| X86_CPUID_FEATURE_EDX_SEP
2646	\| X86_CPUID_FEATURE_EDX_MTRR
2647	\| X86_CPUID_FEATURE_EDX_PGE
2648	\| X86_CPUID_FEATURE_EDX_MCA
2649	\| X86_CPUID_FEATURE_EDX_CMOV
2650	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2651	\| X86_CPUID_FEATURE_EDX_PSE36
2652	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2653	\| X86_CPUID_FEATURE_EDX_CLFSH
2654	//\| RT_BIT_32(20) - not defined
2655	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2656	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2657	\| X86_CPUID_FEATURE_EDX_MMX
2658	\| X86_CPUID_FEATURE_EDX_FXSR
2659	\| X86_CPUID_FEATURE_EDX_SSE
2660	\| X86_CPUID_FEATURE_EDX_SSE2
2661	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2662	\| X86_CPUID_FEATURE_EDX_HTT
2663	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2664	//\| RT_BIT_32(30) - not defined
2665	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2666	;
2667	pStdFeatureLeaf->uEcx &= 0
2668	\| X86_CPUID_FEATURE_ECX_SSE3
2669	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2670	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2671	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2672	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2673	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2674	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2675	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2676	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2677	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2678	\| X86_CPUID_FEATURE_ECX_SSSE3
2679	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2680	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2681	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2682	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2683	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2684	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2685	\| (pConfig->enmPcid ? X86_CPUID_FEATURE_ECX_PCID : 0)
2686	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2687	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2688	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2689	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2690	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2691	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2692	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2693	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2694	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2695	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2696	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2697	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2698	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2699	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2700	;
2701
2702	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2703	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2704	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2705	{
2706	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2707	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2708	}
2709
2710	if (pCpum->u8PortableCpuIdLevel > 0)
2711	{
2712	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2713	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2714	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2715	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2716	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2717	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2718	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2719	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2720	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2721	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2722	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2723	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2724	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2725	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2726	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2727	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2728	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2729	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2730	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2731	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2732
2733	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2734	\| X86_CPUID_FEATURE_EDX_PSN
2735	\| X86_CPUID_FEATURE_EDX_DS
2736	\| X86_CPUID_FEATURE_EDX_ACPI
2737	\| X86_CPUID_FEATURE_EDX_SS
2738	\| X86_CPUID_FEATURE_EDX_TM
2739	\| X86_CPUID_FEATURE_EDX_PBE
2740	)));
2741	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2742	\| X86_CPUID_FEATURE_ECX_CPLDS
2743	\| X86_CPUID_FEATURE_ECX_AES
2744	\| X86_CPUID_FEATURE_ECX_VMX
2745	\| X86_CPUID_FEATURE_ECX_SMX
2746	\| X86_CPUID_FEATURE_ECX_EST
2747	\| X86_CPUID_FEATURE_ECX_TM2
2748	\| X86_CPUID_FEATURE_ECX_CNTXID
2749	\| X86_CPUID_FEATURE_ECX_FMA
2750	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2751	\| X86_CPUID_FEATURE_ECX_PDCM
2752	\| X86_CPUID_FEATURE_ECX_DCA
2753	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2754	)));
2755	}
2756
2757	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2758	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2759
2760	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2761	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2762	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2763	*/
2764	#ifdef VBOX_WITH_MULTI_CORE
2765	if (pVM->cCpus > 1)
2766	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2767	#endif
2768	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2769	{
2770	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2771	core times the number of CPU cores per processor */
2772	#ifdef VBOX_WITH_MULTI_CORE
2773	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2774	#else
2775	/* Single logical processor in a package. */
2776	pStdFeatureLeaf->uEbx \|= (1 << 16);
2777	#endif
2778	}
2779
2780	uint32_t uMicrocodeRev;
2781	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2782	if (RT_SUCCESS(rc))
2783	{
2784	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2785	}
2786	else
2787	{
2788	uMicrocodeRev = 0;
2789	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2790	}
2791
2792	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2793	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2794	*/
2795	if ( (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen)
2796	&& uMicrocodeRev < 0x8001126
2797	&& !pConfig->fForceVme)
2798	{
2799	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2800	LogRel(("CPUM: Zen VME workaround engaged\n"));
2801	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2802	}
2803
2804	/* Force standard feature bits. */
2805	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2806	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2807	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2808	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2809	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2810	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2811	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2812	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2813	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2814	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2815	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2816	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2817	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2818	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2819	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2820	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2821	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2822	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2823	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2824	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2825	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2826	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2827
2828	pStdFeatureLeaf = NULL; /* Must refetch! */
2829
2830	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2831	* AMD:
2832	* EAX: CPU model, family and stepping.
2833	*
2834	* ECX + EDX: Supported features. Only report features we can support.
2835	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2836	* options may require adjusting (i.e. stripping what was enabled).
2837	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2838	*
2839	* EBX: Branding ID and package type (or reserved).
2840	*
2841	* Intel and probably most others:
2842	* EAX: 0
2843	* EBX: 0
2844	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2845	*/
2846	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2847	if (pExtFeatureLeaf)
2848	{
2849	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2850
2851	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2852	\| X86_CPUID_AMD_FEATURE_EDX_VME
2853	\| X86_CPUID_AMD_FEATURE_EDX_DE
2854	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2855	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2856	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2857	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2858	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2859	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2860	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2861	//\| RT_BIT_32(10) - reserved
2862	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2863	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2864	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2865	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2866	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2867	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2868	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2869	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2870	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2871	//\| RT_BIT_32(18) - reserved
2872	//\| RT_BIT_32(19) - reserved
2873	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2874	//\| RT_BIT_32(21) - reserved
2875	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2876	\| X86_CPUID_AMD_FEATURE_EDX_MMX
2877	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
2878	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
2879	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2880	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2881	//\| RT_BIT_32(28) - reserved
2882	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2883	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2884	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
2885	;
2886	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2887	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2888	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
2889	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2890	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
2891	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2892	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2893	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2894	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2895	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2896	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2897	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
2898	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
2899	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2900	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
2901	//\| RT_BIT_32(14) - reserved
2902	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2903	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2904	//\| RT_BIT_32(17) - reserved
2905	//\| RT_BIT_32(18) - reserved
2906	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2907	//\| RT_BIT_32(20) - reserved
2908	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2909	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2910	//\| RT_BIT_32(23) - reserved
2911	//\| RT_BIT_32(24) - reserved
2912	//\| RT_BIT_32(25) - reserved
2913	//\| RT_BIT_32(26) - reserved
2914	//\| RT_BIT_32(27) - reserved
2915	//\| RT_BIT_32(28) - reserved
2916	//\| RT_BIT_32(29) - reserved
2917	//\| RT_BIT_32(30) - reserved
2918	//\| RT_BIT_32(31) - reserved
2919	;
2920	#ifdef VBOX_WITH_MULTI_CORE
2921	if ( pVM->cCpus > 1
2922	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2923	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2924	#endif
2925
2926	if (pCpum->u8PortableCpuIdLevel > 0)
2927	{
2928	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2929	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
2930	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2931	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2932	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2933	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2934	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2935	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2936	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2937	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2938	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2939	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2940	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2941	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2942	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2943	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2944
2945	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2946	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2947	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2948	\| X86_CPUID_AMD_FEATURE_ECX_IBS
2949	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2950	\| X86_CPUID_AMD_FEATURE_ECX_WDT
2951	\| X86_CPUID_AMD_FEATURE_ECX_LWP
2952	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
2953	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2954	\| UINT32_C(0xff964000)
2955	)));
2956	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2957	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2958	\| RT_BIT(18)
2959	\| RT_BIT(19)
2960	\| RT_BIT(21)
2961	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2962	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2963	\| RT_BIT(28)
2964	)));
2965	}
2966
2967	/* Force extended feature bits. */
2968	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2969	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
2970	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2971	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2972	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2973	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2974	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2975	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2976	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2977	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2978	}
2979	pExtFeatureLeaf = NULL; /* Must refetch! */
2980
2981
2982	/* Cpuid 2:
2983	* Intel: (Nondeterministic) Cache and TLB information
2984	* AMD: Reserved
2985	* VIA: Reserved
2986	* Safe to expose.
2987	*/
2988	uint32_t uSubLeaf = 0;
2989	PCPUMCPUIDLEAF pCurLeaf;
2990	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2991	{
2992	if ((pCurLeaf->uEax & 0xff) > 1)
2993	{
2994	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2995	pCurLeaf->uEax &= UINT32_C(0xffffff01);
2996	}
2997	uSubLeaf++;
2998	}
2999
3000	/* Cpuid 3:
3001	* Intel: EAX, EBX - reserved (transmeta uses these)
3002	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3003	* AMD: Reserved
3004	* VIA: Reserved
3005	* Safe to expose
3006	*/
3007	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3008	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3009	{
3010	uSubLeaf = 0;
3011	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3012	{
3013	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3014	if (pCpum->u8PortableCpuIdLevel > 0)
3015	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3016	uSubLeaf++;
3017	}
3018	}
3019
3020	/* Cpuid 4 + ECX:
3021	* Intel: Deterministic Cache Parameters Leaf.
3022	* AMD: Reserved
3023	* VIA: Reserved
3024	* Safe to expose, except for EAX:
3025	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3026	* Bits 31-26: Maximum number of processor cores in this physical package**
3027	* Note: These SMP values are constant regardless of ECX
3028	*/
3029	uSubLeaf = 0;
3030	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3031	{
3032	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3033	#ifdef VBOX_WITH_MULTI_CORE
3034	if ( pVM->cCpus > 1
3035	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3036	{
3037	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3038	/* One logical processor with possibly multiple cores. */
3039	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3040	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3041	}
3042	#endif
3043	uSubLeaf++;
3044	}
3045
3046	/* Cpuid 5: Monitor/mwait Leaf
3047	* Intel: ECX, EDX - reserved
3048	* EAX, EBX - Smallest and largest monitor line size
3049	* AMD: EDX - reserved
3050	* EAX, EBX - Smallest and largest monitor line size
3051	* ECX - extensions (ignored for now)
3052	* VIA: Reserved
3053	* Safe to expose
3054	*/
3055	uSubLeaf = 0;
3056	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3057	{
3058	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3059	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3060	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3061
3062	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3063	if (pConfig->enmMWaitExtensions)
3064	{
3065	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3066	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3067	it shall be part of our power management virtualization model */
3068	#if 0
3069	/* MWAIT sub C-states */
3070	pCurLeaf->uEdx =
3071	(0 << 0) /* 0 in C0 */ \|
3072	(2 << 4) /* 2 in C1 */ \|
3073	(2 << 8) /* 2 in C2 */ \|
3074	(2 << 12) /* 2 in C3 */ \|
3075	(0 << 16) /* 0 in C4 */
3076	;
3077	#endif
3078	}
3079	else
3080	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3081	uSubLeaf++;
3082	}
3083
3084	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3085	* Intel: Various stuff.
3086	* AMD: EAX, EBX, EDX - reserved.
3087	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3088	* present. Same as intel.
3089	* VIA: ??
3090	*
3091	* We clear everything here for now.
3092	*/
3093	cpumR3CpuIdZeroLeaf(pCpum, 6);
3094
3095	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3096	* EAX: Number of sub leaves.
3097	* EBX+ECX+EDX: Feature flags
3098	*
3099	* We only have documentation for one sub-leaf, so clear all other (no need
3100	* to remove them as such, just set them to zero).
3101	*
3102	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3103	* options may require adjusting (i.e. stripping what was enabled).
3104	*/
3105	uSubLeaf = 0;
3106	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3107	{
3108	switch (uSubLeaf)
3109	{
3110	case 0:
3111	{
3112	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3113	pCurLeaf->uEbx &= 0
3114	\| (pConfig->enmFsGsBase ? X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE : 0)
3115	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3116	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3117	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3118	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3119	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3120	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3121	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3122	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3123	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3124	\| (pConfig->enmInvpcid ? X86_CPUID_STEXT_FEATURE_EBX_INVPCID : 0)
3125	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3126	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3127	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3128	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3129	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3130	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3131	//\| RT_BIT(17) - reserved
3132	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3133	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3134	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3135	//\| RT_BIT(21) - reserved
3136	//\| RT_BIT(22) - reserved
3137	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3138	//\| RT_BIT(24) - reserved
3139	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3140	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3141	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3142	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3143	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3144	//\| RT_BIT(30) - reserved
3145	//\| RT_BIT(31) - reserved
3146	;
3147	pCurLeaf->uEcx &= 0
3148	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3149	;
3150	pCurLeaf->uEdx &= 0
3151	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3152	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3153	//\| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT(29)
3154	;
3155
3156	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3157	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3158	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3159	{
3160	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3161	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3162	}
3163
3164	if (pCpum->u8PortableCpuIdLevel > 0)
3165	{
3166	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3167	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3168	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3169	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3170	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3171	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3172	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3173	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3174	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3175	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3176	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3177	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3178	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3179	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3180	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3181	}
3182
3183	/* Force standard feature bits. */
3184	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3185	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3186	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3187	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3188	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3189	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3190	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3191	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3192	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3193	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3194	break;
3195	}
3196
3197	default:
3198	/* Invalid index, all values are zero. */
3199	pCurLeaf->uEax = 0;
3200	pCurLeaf->uEbx = 0;
3201	pCurLeaf->uEcx = 0;
3202	pCurLeaf->uEdx = 0;
3203	break;
3204	}
3205	uSubLeaf++;
3206	}
3207
3208	/* Cpuid 8: Marked as reserved by Intel and AMD.
3209	* We zero this since we don't know what it may have been used for.
3210	*/
3211	cpumR3CpuIdZeroLeaf(pCpum, 8);
3212
3213	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3214	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3215	* EBX, ECX, EDX - reserved.
3216	* AMD: Reserved
3217	* VIA: ??
3218	*
3219	* We zero this.
3220	*/
3221	cpumR3CpuIdZeroLeaf(pCpum, 9);
3222
3223	/* Cpuid 0xa: Architectural Performance Monitor Features
3224	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3225	* EBX, ECX, EDX - reserved.
3226	* AMD: Reserved
3227	* VIA: ??
3228	*
3229	* We zero this, for now at least.
3230	*/
3231	cpumR3CpuIdZeroLeaf(pCpum, 10);
3232
3233	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3234	* Intel: EAX - APCI ID shift right for next level.
3235	* EBX - Factory configured cores/threads at this level.
3236	* ECX - Level number (same as input) and level type (1,2,0).
3237	* EDX - Extended initial APIC ID.
3238	* AMD: Reserved
3239	* VIA: ??
3240	*/
3241	uSubLeaf = 0;
3242	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3243	{
3244	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3245	{
3246	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3247	if (bLevelType == 1)
3248	{
3249	/* Thread level - we don't do threads at the moment. */
3250	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3251	pCurLeaf->uEbx = 1;
3252	}
3253	else if (bLevelType == 2)
3254	{
3255	/* Core level. */
3256	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3257	#ifdef VBOX_WITH_MULTI_CORE
3258	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3259	pCurLeaf->uEax++;
3260	#endif
3261	pCurLeaf->uEbx = pVM->cCpus;
3262	}
3263	else
3264	{
3265	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3266	pCurLeaf->uEax = 0;
3267	pCurLeaf->uEbx = 0;
3268	pCurLeaf->uEcx = 0;
3269	}
3270	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3271	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3272	}
3273	else
3274	{
3275	pCurLeaf->uEax = 0;
3276	pCurLeaf->uEbx = 0;
3277	pCurLeaf->uEcx = 0;
3278	pCurLeaf->uEdx = 0;
3279	}
3280	uSubLeaf++;
3281	}
3282
3283	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3284	* We zero this since we don't know what it may have been used for.
3285	*/
3286	cpumR3CpuIdZeroLeaf(pCpum, 12);
3287
3288	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3289	* ECX=0: EAX - Valid bits in XCR0[31:0].
3290	* EBX - Maximum state size as per current XCR0 value.
3291	* ECX - Maximum state size for all supported features.
3292	* EDX - Valid bits in XCR0[63:32].
3293	* ECX=1: EAX - Various X-features.
3294	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3295	* ECX - Valid bits in IA32_XSS[31:0].
3296	* EDX - Valid bits in IA32_XSS[63:32].
3297	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3298	* if the bit invalid all four registers are set to zero.
3299	* EAX - The state size for this feature.
3300	* EBX - The state byte offset of this feature.
3301	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3302	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3303	*
3304	* Clear them all as we don't currently implement extended CPU state.
3305	*/
3306	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3307	uint64_t fGuestXcr0Mask = 0;
3308	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3309	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3310	{
3311	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3312	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3313	fGuestXcr0Mask \|= XSAVE_C_YMM;
3314	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3315	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3316	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3317	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3318
3319	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3320	}
3321	pStdFeatureLeaf = NULL;
3322	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3323
3324	/* Work the sub-leaves. */
3325	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3326	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3327	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3328	{
3329	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3330	if (pCurLeaf)
3331	{
3332	if (fGuestXcr0Mask)
3333	{
3334	switch (uSubLeaf)
3335	{
3336	case 0:
3337	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3338	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3339	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3340	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3341	VERR_CPUM_IPE_1);
3342	cbXSaveMaxActual = pCurLeaf->uEcx;
3343	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3344	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3345	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3346	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3347	VERR_CPUM_IPE_2);
3348	continue;
3349	case 1:
3350	pCurLeaf->uEax &= 0;
3351	pCurLeaf->uEcx &= 0;
3352	pCurLeaf->uEdx &= 0;
3353	/** @todo what about checking ebx? */
3354	continue;
3355	default:
3356	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3357	{
3358	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3359	&& pCurLeaf->uEax > 0
3360	&& pCurLeaf->uEbx < cbXSaveMaxActual
3361	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3362	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3363	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3364	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3365	VERR_CPUM_IPE_2);
3366	AssertLogRel(!(pCurLeaf->uEcx & 1));
3367	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3368	pCurLeaf->uEdx = 0; /* it's reserved... */
3369	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3370	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3371	continue;
3372	}
3373	break;
3374	}
3375	}
3376
3377	/* Clear the leaf. */
3378	pCurLeaf->uEax = 0;
3379	pCurLeaf->uEbx = 0;
3380	pCurLeaf->uEcx = 0;
3381	pCurLeaf->uEdx = 0;
3382	}
3383	}
3384
3385	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3386	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3387	{
3388	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3389	if (pCurLeaf)
3390	{
3391	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3392	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3393	pCurLeaf->uEbx = cbXSaveMaxReport;
3394	pCurLeaf->uEcx = cbXSaveMaxReport;
3395	}
3396	}
3397
3398	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3399	* We zero this since we don't know what it may have been used for.
3400	*/
3401	cpumR3CpuIdZeroLeaf(pCpum, 14);
3402
3403	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3404	* also known as Intel Resource Director Technology (RDT) Monitoring
3405	* We zero this as we don't currently virtualize PQM.
3406	*/
3407	cpumR3CpuIdZeroLeaf(pCpum, 15);
3408
3409	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3410	* also known as Intel Resource Director Technology (RDT) Allocation
3411	* We zero this as we don't currently virtualize PQE.
3412	*/
3413	cpumR3CpuIdZeroLeaf(pCpum, 16);
3414
3415	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3416	* We zero this since we don't know what it may have been used for.
3417	*/
3418	cpumR3CpuIdZeroLeaf(pCpum, 17);
3419
3420	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3421	* We zero this as we don't currently virtualize this.
3422	*/
3423	cpumR3CpuIdZeroLeaf(pCpum, 18);
3424
3425	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3426	* We zero this since we don't know what it may have been used for.
3427	*/
3428	cpumR3CpuIdZeroLeaf(pCpum, 19);
3429
3430	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3431	* We zero this as we don't currently virtualize this.
3432	*/
3433	cpumR3CpuIdZeroLeaf(pCpum, 20);
3434
3435	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3436	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3437	* EAX - denominator (unsigned).
3438	* EBX - numerator (unsigned).
3439	* ECX, EDX - reserved.
3440	* AMD: Reserved / undefined / not implemented.
3441	* VIA: Reserved / undefined / not implemented.
3442	* We zero this as we don't currently virtualize this.
3443	*/
3444	cpumR3CpuIdZeroLeaf(pCpum, 21);
3445
3446	/* Cpuid 0x16: Processor frequency info
3447	* Intel: EAX - Core base frequency in MHz.
3448	* EBX - Core maximum frequency in MHz.
3449	* ECX - Bus (reference) frequency in MHz.
3450	* EDX - Reserved.
3451	* AMD: Reserved / undefined / not implemented.
3452	* VIA: Reserved / undefined / not implemented.
3453	* We zero this as we don't currently virtualize this.
3454	*/
3455	cpumR3CpuIdZeroLeaf(pCpum, 22);
3456
3457	/* Cpuid 0x17..0x10000000: Unknown.
3458	* We don't know these and what they mean, so remove them. */
3459	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3460	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3461
3462
3463	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3464	* We remove all these as we're a hypervisor and must provide our own.
3465	*/
3466	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3467	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3468
3469
3470	/* Cpuid 0x80000000 is harmless. */
3471
3472	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3473
3474	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3475
3476	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3477	* Safe to pass on to the guest.
3478	*
3479	* AMD: 0x800000005 L1 cache information
3480	* 0x800000006 L2/L3 cache information
3481	* Intel: 0x800000005 reserved
3482	* 0x800000006 L2 cache information
3483	* VIA: 0x800000005 TLB and L1 cache information
3484	* 0x800000006 L2 cache information
3485	*/
3486
3487	/* Cpuid 0x800000007: Advanced Power Management Information.
3488	* AMD: EAX: Processor feedback capabilities.
3489	* EBX: RAS capabilites.
3490	* ECX: Advanced power monitoring interface.
3491	* EDX: Enhanced power management capabilities.
3492	* Intel: EAX, EBX, ECX - reserved.
3493	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3494	* VIA: Reserved
3495	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3496	*/
3497	uSubLeaf = 0;
3498	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3499	{
3500	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3501	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3502	{
3503	/*
3504	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3505	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3506	* bit is now configurable.
3507	*/
3508	pCurLeaf->uEdx &= 0
3509	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3510	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3511	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3512	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3513	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3514	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3515	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3516	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3517	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3518	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3519	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3520	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3521	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3522	\| 0;
3523	}
3524	else
3525	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3526	if (!pConfig->fInvariantTsc)
3527	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3528	uSubLeaf++;
3529	}
3530
3531	/* Cpuid 0x80000008:
3532	* AMD: EBX, EDX - reserved
3533	* EAX: Virtual/Physical/Guest address Size
3534	* ECX: Number of cores + APICIdCoreIdSize
3535	* Intel: EAX: Virtual/Physical address Size
3536	* EBX, ECX, EDX - reserved
3537	* VIA: EAX: Virtual/Physical address Size
3538	* EBX, ECX, EDX - reserved
3539	*
3540	* We only expose the virtual+pysical address size to the guest atm.
3541	* On AMD we set the core count, but not the apic id stuff as we're
3542	* currently not doing the apic id assignments in a complatible manner.
3543	*/
3544	uSubLeaf = 0;
3545	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3546	{
3547	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3548	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3549	pCurLeaf->uEdx = 0; /* reserved */
3550
3551	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3552	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3553	pCurLeaf->uEcx = 0;
3554	#ifdef VBOX_WITH_MULTI_CORE
3555	if ( pVM->cCpus > 1
3556	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3557	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3558	#endif
3559	uSubLeaf++;
3560	}
3561
3562	/* Cpuid 0x80000009: Reserved
3563	* We zero this since we don't know what it may have been used for.
3564	*/
3565	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3566
3567	/* Cpuid 0x8000000a: SVM Information
3568	* AMD: EAX - SVM revision.
3569	* EBX - Number of ASIDs.
3570	* ECX - Reserved.
3571	* EDX - SVM Feature identification.
3572	*/
3573	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3574	if (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
3575	{
3576	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3577	pSvmFeatureLeaf->uEax = 0x1;
3578	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3579	pSvmFeatureLeaf->uEcx = 0;
3580	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3581	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3582	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3583	}
3584	else
3585	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3586
3587	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3588	* We clear these as we don't know what purpose they might have. */
3589	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3590	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3591
3592	/* Cpuid 0x80000019: TLB configuration
3593	* Seems to be harmless, pass them thru as is. */
3594
3595	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3596	* Strip anything we don't know what is or addresses feature we don't implement. */
3597	uSubLeaf = 0;
3598	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3599	{
3600	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3601	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3602	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3603	;
3604	pCurLeaf->uEbx = 0; /* reserved */
3605	pCurLeaf->uEcx = 0; /* reserved */
3606	pCurLeaf->uEdx = 0; /* reserved */
3607	uSubLeaf++;
3608	}
3609
3610	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3611	* Clear this as we don't currently virtualize this feature. */
3612	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3613
3614	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3615	* Clear this as we don't currently virtualize this feature. */
3616	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3617
3618	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3619	* We need to sanitize the cores per cache (EAX[25:14]).
3620	*
3621	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3622	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3623	* slightly different meaning.
3624	*/
3625	uSubLeaf = 0;
3626	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3627	{
3628	#ifdef VBOX_WITH_MULTI_CORE
3629	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3630	if (cCores > pVM->cCpus)
3631	cCores = pVM->cCpus;
3632	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3633	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3634	#else
3635	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3636	#endif
3637	uSubLeaf++;
3638	}
3639
3640	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3641	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3642	* setup, we have one compute unit with all the cores in it. Single node.
3643	*/
3644	uSubLeaf = 0;
3645	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3646	{
3647	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3648	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3649	{
3650	#ifdef VBOX_WITH_MULTI_CORE
3651	pCurLeaf->uEbx = pVM->cCpus < 0x100
3652	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3653	#else
3654	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3655	#endif
3656	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3657	}
3658	else
3659	{
3660	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3661	pCurLeaf->uEbx = 0; /* Reserved. */
3662	pCurLeaf->uEcx = 0; /* Reserved. */
3663	}
3664	pCurLeaf->uEdx = 0; /* Reserved. */
3665	uSubLeaf++;
3666	}
3667
3668	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3669	* We don't know these and what they mean, so remove them. */
3670	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3671	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3672
3673	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3674	* Just pass it thru for now. */
3675
3676	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3677	* Just pass it thru for now. */
3678
3679	/* Cpuid 0xc0000000: Centaur stuff.
3680	* Harmless, pass it thru. */
3681
3682	/* Cpuid 0xc0000001: Centaur features.
3683	* VIA: EAX - Family, model, stepping.
3684	* EDX - Centaur extended feature flags. Nothing interesting, except may
3685	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3686	* EBX, ECX - reserved.
3687	* We keep EAX but strips the rest.
3688	*/
3689	uSubLeaf = 0;
3690	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3691	{
3692	pCurLeaf->uEbx = 0;
3693	pCurLeaf->uEcx = 0;
3694	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3695	uSubLeaf++;
3696	}
3697
3698	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3699	* We only have fixed stale values, but should be harmless. */
3700
3701	/* Cpuid 0xc0000003: Reserved.
3702	* We zero this since we don't know what it may have been used for.
3703	*/
3704	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3705
3706	/* Cpuid 0xc0000004: Centaur Performance Info.
3707	* We only have fixed stale values, but should be harmless. */
3708
3709
3710	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3711	* We don't know these and what they mean, so remove them. */
3712	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3713	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3714
3715	return VINF_SUCCESS;
3716	#undef PORTABLE_DISABLE_FEATURE_BIT
3717	#undef PORTABLE_CLEAR_BITS_WHEN
3718	}
3719
3720
3721	/**
3722	* Reads a value in /CPUM/IsaExts/ node.
3723	*
3724	* @returns VBox status code (error message raised).
3725	* @param pVM The cross context VM structure. (For errors.)
3726	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3727	* @param pszValueName The value / extension name.
3728	* @param penmValue Where to return the choice.
3729	* @param enmDefault The default choice.
3730	*/
3731	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3732	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3733	{
3734	/*
3735	* Try integer encoding first.
3736	*/
3737	uint64_t uValue;
3738	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3739	if (RT_SUCCESS(rc))
3740	switch (uValue)
3741	{
3742	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3743	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3744	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3745	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3746	default:
3747	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3748	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3749	pszValueName, uValue);
3750	}
3751	/*
3752	* If missing, use default.
3753	*/
3754	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3755	*penmValue = enmDefault;
3756	else
3757	{
3758	if (rc == VERR_CFGM_NOT_INTEGER)
3759	{
3760	/*
3761	* Not an integer, try read it as a string.
3762	*/
3763	char szValue[32];
3764	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3765	if (RT_SUCCESS(rc))
3766	{
3767	RTStrToLower(szValue);
3768	size_t cchValue = strlen(szValue);
3769	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3770	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3771	*penmValue = CPUMISAEXTCFG_DISABLED;
3772	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3773	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3774	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3775	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3776	else if (EQ("portable"))
3777	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3778	else if (EQ("default") \|\| EQ("def"))
3779	*penmValue = enmDefault;
3780	else
3781	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3782	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3783	pszValueName, uValue);
3784	#undef EQ
3785	}
3786	}
3787	if (RT_FAILURE(rc))
3788	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3789	}
3790	return VINF_SUCCESS;
3791	}
3792
3793
3794	/**
3795	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3796	*
3797	* @returns VBox status code (error message raised).
3798	* @param pVM The cross context VM structure. (For errors.)
3799	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3800	* @param pszValueName The value / extension name.
3801	* @param penmValue Where to return the choice.
3802	* @param enmDefault The default choice.
3803	* @param fAllowed Allowed choice. Applied both to the result and to
3804	* the default value.
3805	*/
3806	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3807	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3808	{
3809	int rc;
3810	if (fAllowed)
3811	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3812	else
3813	{
3814	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3815	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3816	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3817	*penmValue = CPUMISAEXTCFG_DISABLED;
3818	}
3819	return rc;
3820	}
3821
3822
3823	/**
3824	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3825	*
3826	* @returns VBox status code (error message raised).
3827	* @param pVM The cross context VM structure. (For errors.)
3828	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3829	* @param pCpumCfg The /CPUM node (can be NULL).
3830	* @param pszValueName The value / extension name.
3831	* @param penmValue Where to return the choice.
3832	* @param enmDefault The default choice.
3833	*/
3834	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3835	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3836	{
3837	if (CFGMR3Exists(pCpumCfg, pszValueName))
3838	{
3839	if (!CFGMR3Exists(pIsaExts, pszValueName))
3840	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3841	else
3842	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3843	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3844	pszValueName, pszValueName);
3845
3846	bool fLegacy;
3847	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3848	if (RT_SUCCESS(rc))
3849	{
3850	*penmValue = fLegacy;
3851	return VINF_SUCCESS;
3852	}
3853	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3854	}
3855
3856	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3857	}
3858
3859
3860	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3861	{
3862	int rc;
3863
3864	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3865	* When non-zero CPUID features that could cause portability issues will be
3866	* stripped. The higher the value the more features gets stripped. Higher
3867	* values should only be used when older CPUs are involved since it may
3868	* harm performance and maybe also cause problems with specific guests. */
3869	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
3870	AssertLogRelRCReturn(rc, rc);
3871
3872	/** @cfgm{/CPUM/GuestCpuName, string}
3873	* The name of the CPU we're to emulate. The default is the host CPU.
3874	* Note! CPUs other than "host" one is currently unsupported. */
3875	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3876	AssertLogRelRCReturn(rc, rc);
3877
3878	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3879	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3880	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3881	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3882	*/
3883	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3884	AssertLogRelRCReturn(rc, rc);
3885
3886	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
3887	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
3888	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
3889	* 64-bit linux guests which assume the presence of AMD performance counters
3890	* that we do not virtualize.
3891	*/
3892	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
3893	AssertLogRelRCReturn(rc, rc);
3894
3895	/** @cfgm{/CPUM/ForceVme, boolean, false}
3896	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
3897	* By default the flag is passed thru as is from the host CPU, except
3898	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
3899	* guests and DOS boxes in general.
3900	*/
3901	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
3902	AssertLogRelRCReturn(rc, rc);
3903
3904	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3905	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
3906	* probably going to be a temporary hack, so don't depend on this.
3907	* The 1st byte of the value is the stepping, the 2nd byte value is the model
3908	* number and the 3rd byte value is the family, and the 4th value must be zero.
3909	*/
3910	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3911	AssertLogRelRCReturn(rc, rc);
3912
3913	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3914	* The last standard leaf to keep. The actual last value that is stored in EAX
3915	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3916	* removed. (This works independently of and differently from NT4LeafLimit.)
3917	* The default is usually set to what we're able to reasonably sanitize.
3918	*/
3919	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3920	AssertLogRelRCReturn(rc, rc);
3921
3922	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3923	* The last extended leaf to keep. The actual last value that is stored in EAX
3924	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3925	* leaf are removed. The default is set to what we're able to sanitize.
3926	*/
3927	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3928	AssertLogRelRCReturn(rc, rc);
3929
3930	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3931	* The last extended leaf to keep. The actual last value that is stored in EAX
3932	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3933	* leaf are removed. The default is set to what we're able to sanitize.
3934	*/
3935	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3936	AssertLogRelRCReturn(rc, rc);
3937
3938	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
3939	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
3940	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
3941	* The default is false, and when enabled requires nested paging and AMD-V or
3942	* unrestricted guest mode.
3943	*/
3944	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
3945	AssertLogRelRCReturn(rc, rc);
3946	if ( pConfig->fNestedHWVirt
3947	&& !fNestedPagingAndFullGuestExec)
3948	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
3949	"Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
3950
3951	/** @todo Think about enabling this later with NEM/KVM. */
3952	if ( pConfig->fNestedHWVirt
3953	&& VM_IS_NEM_ENABLED(pVM))
3954	{
3955	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
3956	pConfig->fNestedHWVirt = false;
3957	}
3958	#endif
3959
3960	/*
3961	* Instruction Set Architecture (ISA) Extensions.
3962	*/
3963	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3964	if (pIsaExts)
3965	{
3966	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3967	"CMPXCHG16B"
3968	"\|MONITOR"
3969	"\|MWaitExtensions"
3970	"\|SSE4.1"
3971	"\|SSE4.2"
3972	"\|XSAVE"
3973	"\|AVX"
3974	"\|AVX2"
3975	"\|AESNI"
3976	"\|PCLMUL"
3977	"\|POPCNT"
3978	"\|MOVBE"
3979	"\|RDRAND"
3980	"\|RDSEED"
3981	"\|CLFLUSHOPT"
3982	"\|FSGSBASE"
3983	"\|PCID"
3984	"\|INVPCID"
3985	"\|ABM"
3986	"\|SSE4A"
3987	"\|MISALNSSE"
3988	"\|3DNOWPRF"
3989	"\|AXMMX"
3990	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
3991	if (RT_FAILURE(rc))
3992	return rc;
3993	}
3994
3995	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
3996	* Expose CMPXCHG16B to the guest if supported by the host. For the time
3997	* being the default is to only do this for VMs with nested paging and AMD-V or
3998	* unrestricted guest mode.
3999	*/
4000	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
4001	AssertLogRelRCReturn(rc, rc);
4002
4003	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4004	* Expose MONITOR/MWAIT instructions to the guest.
4005	*/
4006	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4007	AssertLogRelRCReturn(rc, rc);
4008
4009	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4010	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4011	* break on interrupt feature (bit 1).
4012	*/
4013	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4014	AssertLogRelRCReturn(rc, rc);
4015
4016	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4017	* Expose SSE4.1 to the guest if available.
4018	*/
4019	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4020	AssertLogRelRCReturn(rc, rc);
4021
4022	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4023	* Expose SSE4.2 to the guest if available.
4024	*/
4025	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4026	AssertLogRelRCReturn(rc, rc);
4027
4028	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4029	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4030	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
4031	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
4032	&& ( !HMIsLongModeAllowed(pVM)
4033	\|\| NEMHCIsLongModeAllowed(pVM))
4034	#endif
4035	;
4036	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4037
4038	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4039	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4040	* default is to only expose this to VMs with nested paging and AMD-V or
4041	* unrestricted guest execution mode. Not possible to force this one without
4042	* host support at the moment.
4043	*/
4044	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4045	fMayHaveXSave /fAllowed/);
4046	AssertLogRelRCReturn(rc, rc);
4047
4048	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4049	* Expose the AVX instruction set extensions to the guest if available and
4050	* XSAVE is exposed too. For the time being the default is to only expose this
4051	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4052	*/
4053	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4054	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4055	AssertLogRelRCReturn(rc, rc);
4056
4057	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4058	* Expose the AVX2 instruction set extensions to the guest if available and
4059	* XSAVE is exposed too. For the time being the default is to only expose this
4060	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4061	*/
4062	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4063	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4064	AssertLogRelRCReturn(rc, rc);
4065
4066	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4067	* Whether to expose the AES instructions to the guest. For the time being the
4068	* default is to only do this for VMs with nested paging and AMD-V or
4069	* unrestricted guest mode.
4070	*/
4071	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4072	AssertLogRelRCReturn(rc, rc);
4073
4074	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4075	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4076	* being the default is to only do this for VMs with nested paging and AMD-V or
4077	* unrestricted guest mode.
4078	*/
4079	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4080	AssertLogRelRCReturn(rc, rc);
4081
4082	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4083	* Whether to expose the POPCNT instructions to the guest. For the time
4084	* being the default is to only do this for VMs with nested paging and AMD-V or
4085	* unrestricted guest mode.
4086	*/
4087	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4088	AssertLogRelRCReturn(rc, rc);
4089
4090	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4091	* Whether to expose the MOVBE instructions to the guest. For the time
4092	* being the default is to only do this for VMs with nested paging and AMD-V or
4093	* unrestricted guest mode.
4094	*/
4095	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4096	AssertLogRelRCReturn(rc, rc);
4097
4098	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4099	* Whether to expose the RDRAND instructions to the guest. For the time being
4100	* the default is to only do this for VMs with nested paging and AMD-V or
4101	* unrestricted guest mode.
4102	*/
4103	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4104	AssertLogRelRCReturn(rc, rc);
4105
4106	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4107	* Whether to expose the RDSEED instructions to the guest. For the time being
4108	* the default is to only do this for VMs with nested paging and AMD-V or
4109	* unrestricted guest mode.
4110	*/
4111	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4112	AssertLogRelRCReturn(rc, rc);
4113
4114	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4115	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4116	* being the default is to only do this for VMs with nested paging and AMD-V or
4117	* unrestricted guest mode.
4118	*/
4119	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4120	AssertLogRelRCReturn(rc, rc);
4121
4122	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4123	* Whether to expose the read/write FSGSBASE instructions to the guest.
4124	*/
4125	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4126	AssertLogRelRCReturn(rc, rc);
4127
4128	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4129	* Whether to expose the PCID feature to the guest.
4130	*/
4131	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4132	AssertLogRelRCReturn(rc, rc);
4133
4134	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4135	* Whether to expose the INVPCID instruction to the guest.
4136	*/
4137	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4138	AssertLogRelRCReturn(rc, rc);
4139
4140
4141	/* AMD: */
4142
4143	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4144	* Whether to expose the AMD ABM instructions to the guest. For the time
4145	* being the default is to only do this for VMs with nested paging and AMD-V or
4146	* unrestricted guest mode.
4147	*/
4148	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4149	AssertLogRelRCReturn(rc, rc);
4150
4151	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4152	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4153	* being the default is to only do this for VMs with nested paging and AMD-V or
4154	* unrestricted guest mode.
4155	*/
4156	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4157	AssertLogRelRCReturn(rc, rc);
4158
4159	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4160	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4161	* the time being the default is to only do this for VMs with nested paging and
4162	* AMD-V or unrestricted guest mode.
4163	*/
4164	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4165	AssertLogRelRCReturn(rc, rc);
4166
4167	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4168	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4169	* For the time being the default is to only do this for VMs with nested paging
4170	* and AMD-V or unrestricted guest mode.
4171	*/
4172	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4173	AssertLogRelRCReturn(rc, rc);
4174
4175	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4176	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4177	* the default is to only do this for VMs with nested paging and AMD-V or
4178	* unrestricted guest mode.
4179	*/
4180	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4181	AssertLogRelRCReturn(rc, rc);
4182
4183	return VINF_SUCCESS;
4184	}
4185
4186
4187	/**
4188	* Initializes the emulated CPU's CPUID & MSR information.
4189	*
4190	* @returns VBox status code.
4191	* @param pVM The cross context VM structure.
4192	*/
4193	int cpumR3InitCpuIdAndMsrs(PVM pVM)
4194	{
4195	PCPUM pCpum = &pVM->cpum.s;
4196	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4197
4198	/*
4199	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4200	* on construction and manage everything from here on.
4201	*/
4202	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
4203	pVM->aCpus[iCpu].cpum.s.fCpuIdApicFeatureVisible = true;
4204
4205	/*
4206	* Read the configuration.
4207	*/
4208	CPUMCPUIDCONFIG Config;
4209	RT_ZERO(Config);
4210
4211	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4212	AssertRCReturn(rc, rc);
4213
4214	/*
4215	* Get the guest CPU data from the database and/or the host.
4216	*
4217	* The CPUID and MSRs are currently living on the regular heap to avoid
4218	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4219	* API for the hyper heap). This means special cleanup considerations.
4220	*/
4221	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4222	if (RT_FAILURE(rc))
4223	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4224	? VMSetError(pVM, rc, RT_SRC_POS,
4225	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4226	: rc;
4227
4228	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4229	{
4230	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4231	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4232	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4233	}
4234	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4235
4236	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4237	* Overrides the guest MSRs.
4238	*/
4239	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4240
4241	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4242	* Overrides the CPUID leaf values (from the host CPU usually) used for
4243	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4244	* values when moving a VM to a different machine. Another use is restricting
4245	* (or extending) the feature set exposed to the guest. */
4246	if (RT_SUCCESS(rc))
4247	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4248
4249	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4250	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4251	"Found unsupported configuration node '/CPUM/CPUID/'. "
4252	"Please use IMachine::setCPUIDLeaf() instead.");
4253
4254	/*
4255	* Pre-explode the CPUID info.
4256	*/
4257	if (RT_SUCCESS(rc))
4258	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
4259
4260	/*
4261	* Sanitize the cpuid information passed on to the guest.
4262	*/
4263	if (RT_SUCCESS(rc))
4264	{
4265	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4266	if (RT_SUCCESS(rc))
4267	{
4268	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4269	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4270	}
4271	}
4272
4273	/*
4274	* MSR fudging.
4275	*/
4276	if (RT_SUCCESS(rc))
4277	{
4278	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4279	* Fudges some common MSRs if not present in the selected CPU database entry.
4280	* This is for trying to keep VMs running when moved between different hosts
4281	* and different CPU vendors. */
4282	bool fEnable;
4283	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4284	if (RT_SUCCESS(rc) && fEnable)
4285	{
4286	rc = cpumR3MsrApplyFudge(pVM);
4287	AssertLogRelRC(rc);
4288	}
4289	}
4290	if (RT_SUCCESS(rc))
4291	{
4292	/*
4293	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4294	* guest CPU features again.
4295	*/
4296	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4297	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4298	pCpum->GuestInfo.cCpuIdLeaves);
4299	RTMemFree(pvFree);
4300
4301	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4302	int rc2 = MMHyperDupMem(pVM, pvFree,
4303	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4304	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4305	RTMemFree(pvFree);
4306	AssertLogRelRCReturn(rc1, rc1);
4307	AssertLogRelRCReturn(rc2, rc2);
4308
4309	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4310	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4311
4312
4313	/*
4314	* Some more configuration that we're applying at the end of everything
4315	* via the CPUMSetGuestCpuIdFeature API.
4316	*/
4317
4318	/* Check if PAE was explicitely enabled by the user. */
4319	bool fEnable;
4320	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4321	AssertRCReturn(rc, rc);
4322	if (fEnable)
4323	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4324
4325	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4326	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4327	AssertRCReturn(rc, rc);
4328	if (fEnable)
4329	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4330
4331	/* Check if speculation control is enabled. */
4332	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4333	AssertRCReturn(rc, rc);
4334	if (fEnable)
4335	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4336
4337	return VINF_SUCCESS;
4338	}
4339
4340	/*
4341	* Failed before switching to hyper heap.
4342	*/
4343	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4344	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4345	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4346	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4347	return rc;
4348	}
4349
4350
4351	/**
4352	* Sets a CPUID feature bit during VM initialization.
4353	*
4354	* Since the CPUID feature bits are generally related to CPU features, other
4355	* CPUM configuration like MSRs can also be modified by calls to this API.
4356	*
4357	* @param pVM The cross context VM structure.
4358	* @param enmFeature The feature to set.
4359	*/
4360	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4361	{
4362	PCPUMCPUIDLEAF pLeaf;
4363	PCPUMMSRRANGE pMsrRange;
4364
4365	switch (enmFeature)
4366	{
4367	/*
4368	* Set the APIC bit in both feature masks.
4369	*/
4370	case CPUMCPUIDFEATURE_APIC:
4371	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4372	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4373	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4374
4375	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4376	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4377	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4378
4379	pVM->cpum.s.GuestFeatures.fApic = 1;
4380
4381	/* Make sure we've got the APICBASE MSR present. */
4382	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4383	if (!pMsrRange)
4384	{
4385	static CPUMMSRRANGE const s_ApicBase =
4386	{
4387	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4388	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4389	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4390	/.szName = / "IA32_APIC_BASE"
4391	};
4392	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4393	AssertLogRelRC(rc);
4394	}
4395
4396	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4397	break;
4398
4399	/*
4400	* Set the x2APIC bit in the standard feature mask.
4401	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4402	*/
4403	case CPUMCPUIDFEATURE_X2APIC:
4404	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4405	if (pLeaf)
4406	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4407	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4408
4409	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4410	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4411	if (pMsrRange)
4412	{
4413	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4414	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4415	}
4416
4417	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4418	break;
4419
4420	/*
4421	* Set the sysenter/sysexit bit in the standard feature mask.
4422	* Assumes the caller knows what it's doing! (host must support these)
4423	*/
4424	case CPUMCPUIDFEATURE_SEP:
4425	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4426	{
4427	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4428	return;
4429	}
4430
4431	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4432	if (pLeaf)
4433	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4434	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4435	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4436	break;
4437
4438	/*
4439	* Set the syscall/sysret bit in the extended feature mask.
4440	* Assumes the caller knows what it's doing! (host must support these)
4441	*/
4442	case CPUMCPUIDFEATURE_SYSCALL:
4443	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4444	if ( !pLeaf
4445	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4446	{
4447	#if HC_ARCH_BITS == 32
4448	/* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit
4449	mode by Intel, even when the cpu is capable of doing so in
4450	64-bit mode. Long mode requires syscall support. */
4451	if (!pVM->cpum.s.HostFeatures.fLongMode)
4452	#endif
4453	{
4454	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4455	return;
4456	}
4457	}
4458
4459	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4460	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4461	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4462	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4463	break;
4464
4465	/*
4466	* Set the PAE bit in both feature masks.
4467	* Assumes the caller knows what it's doing! (host must support these)
4468	*/
4469	case CPUMCPUIDFEATURE_PAE:
4470	if (!pVM->cpum.s.HostFeatures.fPae)
4471	{
4472	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4473	return;
4474	}
4475
4476	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4477	if (pLeaf)
4478	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4479
4480	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4481	if ( pLeaf
4482	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4483	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4484
4485	pVM->cpum.s.GuestFeatures.fPae = 1;
4486	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4487	break;
4488
4489	/*
4490	* Set the LONG MODE bit in the extended feature mask.
4491	* Assumes the caller knows what it's doing! (host must support these)
4492	*/
4493	case CPUMCPUIDFEATURE_LONG_MODE:
4494	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4495	if ( !pLeaf
4496	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4497	{
4498	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4499	return;
4500	}
4501
4502	/* Valid for both Intel and AMD. */
4503	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4504	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4505	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4506	break;
4507
4508	/*
4509	* Set the NX/XD bit in the extended feature mask.
4510	* Assumes the caller knows what it's doing! (host must support these)
4511	*/
4512	case CPUMCPUIDFEATURE_NX:
4513	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4514	if ( !pLeaf
4515	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4516	{
4517	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4518	return;
4519	}
4520
4521	/* Valid for both Intel and AMD. */
4522	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4523	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4524	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4525	break;
4526
4527
4528	/*
4529	* Set the LAHF/SAHF support in 64-bit mode.
4530	* Assumes the caller knows what it's doing! (host must support this)
4531	*/
4532	case CPUMCPUIDFEATURE_LAHF:
4533	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4534	if ( !pLeaf
4535	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4536	{
4537	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4538	return;
4539	}
4540
4541	/* Valid for both Intel and AMD. */
4542	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4543	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4544	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4545	break;
4546
4547	/*
4548	* Set the page attribute table bit. This is alternative page level
4549	* cache control that doesn't much matter when everything is
4550	* virtualized, though it may when passing thru device memory.
4551	*/
4552	case CPUMCPUIDFEATURE_PAT:
4553	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4554	if (pLeaf)
4555	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4556
4557	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4558	if ( pLeaf
4559	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4560	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4561
4562	pVM->cpum.s.GuestFeatures.fPat = 1;
4563	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4564	break;
4565
4566	/*
4567	* Set the RDTSCP support bit.
4568	* Assumes the caller knows what it's doing! (host must support this)
4569	*/
4570	case CPUMCPUIDFEATURE_RDTSCP:
4571	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4572	if ( !pLeaf
4573	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4574	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4575	{
4576	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4577	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4578	return;
4579	}
4580
4581	/* Valid for both Intel and AMD. */
4582	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4583	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4584	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4585	break;
4586
4587	/*
4588	* Set the Hypervisor Present bit in the standard feature mask.
4589	*/
4590	case CPUMCPUIDFEATURE_HVP:
4591	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4592	if (pLeaf)
4593	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4594	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4595	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4596	break;
4597
4598	/*
4599	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4600	* This currently includes the Present bit and MWAITBREAK bit as well.
4601	*/
4602	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4603	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4604	if ( !pLeaf
4605	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4606	{
4607	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4608	return;
4609	}
4610
4611	/* Valid for both Intel and AMD. */
4612	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4613	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4614	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4615	break;
4616
4617	/*
4618	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
4619	* on Intel CPUs, and different on AMDs.
4620	*/
4621	case CPUMCPUIDFEATURE_SPEC_CTRL:
4622	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4623	{
4624	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4625	if ( !pLeaf
4626	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
4627	{
4628	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4629	return;
4630	}
4631
4632	/* The feature can be enabled. Let's see what we can actually do. */
4633	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4634
4635	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4636	if (pVM->cpum.s.HostFeatures.fIbrs)
4637	{
4638	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4639	pVM->cpum.s.GuestFeatures.fIbrs = 1;
4640	if (pVM->cpum.s.HostFeatures.fStibp)
4641	{
4642	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4643	pVM->cpum.s.GuestFeatures.fStibp = 1;
4644	}
4645
4646	/* Make sure we have the speculation control MSR... */
4647	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4648	if (!pMsrRange)
4649	{
4650	static CPUMMSRRANGE const s_SpecCtrl =
4651	{
4652	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
4653	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
4654	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4655	/.szName = / "IA32_SPEC_CTRL"
4656	};
4657	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4658	AssertLogRelRC(rc);
4659	}
4660
4661	/* ... and the predictor command MSR. */
4662	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
4663	if (!pMsrRange)
4664	{
4665	static CPUMMSRRANGE const s_SpecCtrl =
4666	{
4667	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
4668	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
4669	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4670	/.szName = / "IA32_PRED_CMD"
4671	};
4672	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4673	AssertLogRelRC(rc);
4674	}
4675
4676	}
4677
4678	if (pVM->cpum.s.HostFeatures.fArchCap) {
4679	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
4680
4681	/* Install the architectural capabilities MSR. */
4682	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
4683	if (!pMsrRange)
4684	{
4685	static CPUMMSRRANGE const s_ArchCaps =
4686	{
4687	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
4688	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
4689	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
4690	/.szName = / "IA32_ARCH_CAPABILITIES"
4691	};
4692	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
4693	AssertLogRelRC(rc);
4694	}
4695	}
4696
4697	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
4698	}
4699	else if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4700	{
4701	/* The precise details of AMD's implementation are not yet clear. */
4702	}
4703	break;
4704
4705	default:
4706	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4707	break;
4708	}
4709
4710	/** @todo can probably kill this as this API is now init time only... */
4711	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4712	{
4713	PVMCPU pVCpu = &pVM->aCpus[i];
4714	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4715	}
4716	}
4717
4718
4719	/**
4720	* Queries a CPUID feature bit.
4721	*
4722	* @returns boolean for feature presence
4723	* @param pVM The cross context VM structure.
4724	* @param enmFeature The feature to query.
4725	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4726	*/
4727	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4728	{
4729	switch (enmFeature)
4730	{
4731	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4732	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4733	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4734	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4735	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4736	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4737	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4738	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4739	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4740	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4741	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4742	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4743	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
4744
4745	case CPUMCPUIDFEATURE_INVALID:
4746	case CPUMCPUIDFEATURE_32BIT_HACK:
4747	break;
4748	}
4749	AssertFailed();
4750	return false;
4751	}
4752
4753
4754	/**
4755	* Clears a CPUID feature bit.
4756	*
4757	* @param pVM The cross context VM structure.
4758	* @param enmFeature The feature to clear.
4759	*
4760	* @deprecated Probably better to default the feature to disabled and only allow
4761	* setting (enabling) it during construction.
4762	*/
4763	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4764	{
4765	PCPUMCPUIDLEAF pLeaf;
4766	switch (enmFeature)
4767	{
4768	case CPUMCPUIDFEATURE_APIC:
4769	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
4770	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4771	if (pLeaf)
4772	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
4773
4774	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4775	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4776	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4777
4778	pVM->cpum.s.GuestFeatures.fApic = 0;
4779	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4780	break;
4781
4782	case CPUMCPUIDFEATURE_X2APIC:
4783	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4784	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4785	if (pLeaf)
4786	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
4787	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
4788	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
4789	break;
4790
4791	case CPUMCPUIDFEATURE_PAE:
4792	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4793	if (pLeaf)
4794	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
4795
4796	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4797	if ( pLeaf
4798	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4799	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
4800
4801	pVM->cpum.s.GuestFeatures.fPae = 0;
4802	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
4803	break;
4804
4805	case CPUMCPUIDFEATURE_PAT:
4806	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4807	if (pLeaf)
4808	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
4809
4810	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4811	if ( pLeaf
4812	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4813	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
4814
4815	pVM->cpum.s.GuestFeatures.fPat = 0;
4816	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
4817	break;
4818
4819	case CPUMCPUIDFEATURE_LONG_MODE:
4820	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4821	if (pLeaf)
4822	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4823	pVM->cpum.s.GuestFeatures.fLongMode = 0;
4824	break;
4825
4826	case CPUMCPUIDFEATURE_LAHF:
4827	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4828	if (pLeaf)
4829	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4830	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
4831	break;
4832
4833	case CPUMCPUIDFEATURE_RDTSCP:
4834	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4835	if (pLeaf)
4836	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4837	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
4838	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
4839	break;
4840
4841	case CPUMCPUIDFEATURE_HVP:
4842	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4843	if (pLeaf)
4844	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
4845	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
4846	break;
4847
4848	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4849	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4850	if (pLeaf)
4851	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
4852	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
4853	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
4854	break;
4855
4856	case CPUMCPUIDFEATURE_SPEC_CTRL:
4857	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4858	if (pLeaf)
4859	/pVM->cpum.s.aGuestCpuIdPatmStd[7].uEdx =/ pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP \| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
4860	pVM->cpum.s.GuestFeatures.fSpeculationControl = 0;
4861	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
4862	break;
4863
4864	default:
4865	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4866	break;
4867	}
4868
4869	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4870	{
4871	PVMCPU pVCpu = &pVM->aCpus[i];
4872	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4873	}
4874	}
4875
4876
4877
4878	/*
4879	*
4880	*
4881	* Saved state related code.
4882	* Saved state related code.
4883	* Saved state related code.
4884	*
4885	*
4886	*/
4887
4888	/**
4889	* Called both in pass 0 and the final pass.
4890	*
4891	* @param pVM The cross context VM structure.
4892	* @param pSSM The saved state handle.
4893	*/
4894	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4895	{
4896	/*
4897	* Save all the CPU ID leaves.
4898	*/
4899	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4900	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4901	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4902	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4903
4904	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4905
4906	/*
4907	* Save a good portion of the raw CPU IDs as well as they may come in
4908	* handy when validating features for raw mode.
4909	*/
4910	CPUMCPUID aRawStd[16];
4911	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4912	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4913	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4914	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4915
4916	CPUMCPUID aRawExt[32];
4917	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4918	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4919	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4920	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4921	}
4922
4923
4924	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4925	{
4926	uint32_t cCpuIds;
4927	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4928	if (RT_SUCCESS(rc))
4929	{
4930	if (cCpuIds < 64)
4931	{
4932	for (uint32_t i = 0; i < cCpuIds; i++)
4933	{
4934	CPUMCPUID CpuId;
4935	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4936	if (RT_FAILURE(rc))
4937	break;
4938
4939	CPUMCPUIDLEAF NewLeaf;
4940	NewLeaf.uLeaf = uBase + i;
4941	NewLeaf.uSubLeaf = 0;
4942	NewLeaf.fSubLeafMask = 0;
4943	NewLeaf.uEax = CpuId.uEax;
4944	NewLeaf.uEbx = CpuId.uEbx;
4945	NewLeaf.uEcx = CpuId.uEcx;
4946	NewLeaf.uEdx = CpuId.uEdx;
4947	NewLeaf.fFlags = 0;
4948	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4949	}
4950	}
4951	else
4952	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4953	}
4954	if (RT_FAILURE(rc))
4955	{
4956	RTMemFree(*ppaLeaves);
4957	*ppaLeaves = NULL;
4958	*pcLeaves = 0;
4959	}
4960	return rc;
4961	}
4962
4963
4964	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4965	{
4966	*ppaLeaves = NULL;
4967	*pcLeaves = 0;
4968
4969	int rc;
4970	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4971	{
4972	/*
4973	* The new format. Starts by declaring the leave size and count.
4974	*/
4975	uint32_t cbLeaf;
4976	SSMR3GetU32(pSSM, &cbLeaf);
4977	uint32_t cLeaves;
4978	rc = SSMR3GetU32(pSSM, &cLeaves);
4979	if (RT_SUCCESS(rc))
4980	{
4981	if (cbLeaf == sizeof(**ppaLeaves))
4982	{
4983	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4984	{
4985	/*
4986	* Load the leaves one by one.
4987	*
4988	* The uPrev stuff is a kludge for working around a week worth of bad saved
4989	* states during the CPUID revamp in March 2015. We saved too many leaves
4990	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4991	* garbage entires at the end of the array when restoring. We also had
4992	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
4993	* this kludge doesn't deal correctly with that, but who cares...
4994	*/
4995	uint32_t uPrev = 0;
4996	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4997	{
4998	CPUMCPUIDLEAF Leaf;
4999	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5000	if (RT_SUCCESS(rc))
5001	{
5002	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5003	\|\| Leaf.uLeaf >= uPrev)
5004	{
5005	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5006	uPrev = Leaf.uLeaf;
5007	}
5008	else
5009	uPrev = UINT32_MAX;
5010	}
5011	}
5012	}
5013	else
5014	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5015	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5016	}
5017	else
5018	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5019	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5020	}
5021	}
5022	else
5023	{
5024	/*
5025	* The old format with its three inflexible arrays.
5026	*/
5027	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5028	if (RT_SUCCESS(rc))
5029	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5030	if (RT_SUCCESS(rc))
5031	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5032	if (RT_SUCCESS(rc))
5033	{
5034	/*
5035	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5036	*/
5037	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5038	if ( pLeaf
5039	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5040	{
5041	CPUMCPUIDLEAF Leaf;
5042	Leaf.uLeaf = 4;
5043	Leaf.fSubLeafMask = UINT32_MAX;
5044	Leaf.uSubLeaf = 0;
5045	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5046	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5047	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5048	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5049	\| UINT32_C(63); /* system coherency line size - 1 */
5050	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5051	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5052	\| (UINT32_C(1) << 5) /* cache level */
5053	\| UINT32_C(1); /* cache type (data) */
5054	Leaf.fFlags = 0;
5055	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5056	if (RT_SUCCESS(rc))
5057	{
5058	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5059	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5060	}
5061	if (RT_SUCCESS(rc))
5062	{
5063	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5064	Leaf.uEcx = 4095; /* sets - 1 */
5065	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5066	Leaf.uEbx \|= UINT32_C(23) << 22;
5067	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5068	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5069	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5070	Leaf.uEax \|= UINT32_C(2) << 5;
5071	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5072	}
5073	}
5074	}
5075	}
5076	return rc;
5077	}
5078
5079
5080	/**
5081	* Loads the CPU ID leaves saved by pass 0, inner worker.
5082	*
5083	* @returns VBox status code.
5084	* @param pVM The cross context VM structure.
5085	* @param pSSM The saved state handle.
5086	* @param uVersion The format version.
5087	* @param paLeaves Guest CPUID leaves loaded from the state.
5088	* @param cLeaves The number of leaves in @a paLeaves.
5089	*/
5090	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
5091	{
5092	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5093
5094	/*
5095	* Continue loading the state into stack buffers.
5096	*/
5097	CPUMCPUID GuestDefCpuId;
5098	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5099	AssertRCReturn(rc, rc);
5100
5101	CPUMCPUID aRawStd[16];
5102	uint32_t cRawStd;
5103	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5104	if (cRawStd > RT_ELEMENTS(aRawStd))
5105	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5106	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5107	AssertRCReturn(rc, rc);
5108	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5109	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5110
5111	CPUMCPUID aRawExt[32];
5112	uint32_t cRawExt;
5113	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5114	if (cRawExt > RT_ELEMENTS(aRawExt))
5115	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5116	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5117	AssertRCReturn(rc, rc);
5118	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5119	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5120
5121	/*
5122	* Get the raw CPU IDs for the current host.
5123	*/
5124	CPUMCPUID aHostRawStd[16];
5125	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5126	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5127
5128	CPUMCPUID aHostRawExt[32];
5129	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5130	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5131	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5132
5133	/*
5134	* Get the host and guest overrides so we don't reject the state because
5135	* some feature was enabled thru these interfaces.
5136	* Note! We currently only need the feature leaves, so skip rest.
5137	*/
5138	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5139	CPUMCPUID aHostOverrideStd[2];
5140	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5141	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5142
5143	CPUMCPUID aHostOverrideExt[2];
5144	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5145	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5146
5147	/*
5148	* This can be skipped.
5149	*/
5150	bool fStrictCpuIdChecks;
5151	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5152
5153	/*
5154	* Define a bunch of macros for simplifying the santizing/checking code below.
5155	*/
5156	/* Generic expression + failure message. */
5157	#define CPUID_CHECK_RET(expr, fmt) \
5158	do { \
5159	if (!(expr)) \
5160	{ \
5161	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5162	if (fStrictCpuIdChecks) \
5163	{ \
5164	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5165	RTStrFree(pszMsg); \
5166	return rcCpuid; \
5167	} \
5168	LogRel(("CPUM: %s\n", pszMsg)); \
5169	RTStrFree(pszMsg); \
5170	} \
5171	} while (0)
5172	#define CPUID_CHECK_WRN(expr, fmt) \
5173	do { \
5174	if (!(expr)) \
5175	LogRel(fmt); \
5176	} while (0)
5177
5178	/* For comparing two values and bitch if they differs. */
5179	#define CPUID_CHECK2_RET(what, host, saved) \
5180	do { \
5181	if ((host) != (saved)) \
5182	{ \
5183	if (fStrictCpuIdChecks) \
5184	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5185	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5186	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5187	} \
5188	} while (0)
5189	#define CPUID_CHECK2_WRN(what, host, saved) \
5190	do { \
5191	if ((host) != (saved)) \
5192	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5193	} while (0)
5194
5195	/* For checking raw cpu features (raw mode). */
5196	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5197	do { \
5198	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5199	{ \
5200	if (fStrictCpuIdChecks) \
5201	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5202	N_(#bit " mismatch: host=%d saved=%d"), \
5203	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5204	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5205	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5206	} \
5207	} while (0)
5208	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5209	do { \
5210	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5211	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5212	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5213	} while (0)
5214	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5215
5216	/* For checking guest features. */
5217	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5218	do { \
5219	if ( (aGuestCpuId##set [1].reg & bit) \
5220	&& !(aHostRaw##set [1].reg & bit) \
5221	&& !(aHostOverride##set [1].reg & bit) \
5222	) \
5223	{ \
5224	if (fStrictCpuIdChecks) \
5225	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5226	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5227	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5228	} \
5229	} while (0)
5230	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5231	do { \
5232	if ( (aGuestCpuId##set [1].reg & bit) \
5233	&& !(aHostRaw##set [1].reg & bit) \
5234	&& !(aHostOverride##set [1].reg & bit) \
5235	) \
5236	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5237	} while (0)
5238	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5239	do { \
5240	if ( (aGuestCpuId##set [1].reg & bit) \
5241	&& !(aHostRaw##set [1].reg & bit) \
5242	&& !(aHostOverride##set [1].reg & bit) \
5243	) \
5244	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5245	} while (0)
5246	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5247
5248	/* For checking guest features if AMD guest CPU. */
5249	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5250	do { \
5251	if ( (aGuestCpuId##set [1].reg & bit) \
5252	&& fGuestAmd \
5253	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5254	&& !(aHostOverride##set [1].reg & bit) \
5255	) \
5256	{ \
5257	if (fStrictCpuIdChecks) \
5258	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5259	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5260	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5261	} \
5262	} while (0)
5263	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5264	do { \
5265	if ( (aGuestCpuId##set [1].reg & bit) \
5266	&& fGuestAmd \
5267	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5268	&& !(aHostOverride##set [1].reg & bit) \
5269	) \
5270	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5271	} while (0)
5272	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5273	do { \
5274	if ( (aGuestCpuId##set [1].reg & bit) \
5275	&& fGuestAmd \
5276	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5277	&& !(aHostOverride##set [1].reg & bit) \
5278	) \
5279	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5280	} while (0)
5281	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5282
5283	/* For checking AMD features which have a corresponding bit in the standard
5284	range. (Intel defines very few bits in the extended feature sets.) */
5285	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5286	do { \
5287	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5288	&& !(fHostAmd \
5289	? aHostRawExt[1].reg & (ExtBit) \
5290	: aHostRawStd[1].reg & (StdBit)) \
5291	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5292	) \
5293	{ \
5294	if (fStrictCpuIdChecks) \
5295	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5296	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5297	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5298	} \
5299	} while (0)
5300	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5301	do { \
5302	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5303	&& !(fHostAmd \
5304	? aHostRawExt[1].reg & (ExtBit) \
5305	: aHostRawStd[1].reg & (StdBit)) \
5306	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5307	) \
5308	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5309	} while (0)
5310	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5311	do { \
5312	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5313	&& !(fHostAmd \
5314	? aHostRawExt[1].reg & (ExtBit) \
5315	: aHostRawStd[1].reg & (StdBit)) \
5316	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5317	) \
5318	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5319	} while (0)
5320	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5321
5322	/*
5323	* For raw-mode we'll require that the CPUs are very similar since we don't
5324	* intercept CPUID instructions for user mode applications.
5325	*/
5326	if (VM_IS_RAW_MODE_ENABLED(pVM))
5327	{
5328	/* CPUID(0) */
5329	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
5330	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
5331	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
5332	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5333	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
5334	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
5335	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
5336	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
5337	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5338
5339	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
5340
5341	/* CPUID(1).eax */
5342	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
5343	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
5344	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
5345
5346	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
5347	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
5348	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
5349
5350	/* CPUID(1).ecx */
5351	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
5352	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
5353	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
5354	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5355	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
5356	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
5357	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
5358	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
5359	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
5360	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
5361	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
5362	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
5363	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
5364	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
5365	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
5366	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
5367	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5368	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5369	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
5370	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
5371	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
5372	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5373	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
5374	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
5375	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5376	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
5377	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
5378	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5379	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
5380	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5381	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5382	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
5383
5384	/* CPUID(1).edx */
5385	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5386	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5387	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
5388	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5389	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
5390	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
5391	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5392	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5393	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
5394	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5395	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5396	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5397	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5398	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5399	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5400	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
5401	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5402	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5403	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5404	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
5405	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5406	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
5407	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
5408	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
5409	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
5410	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
5411	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
5412	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
5413	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
5414	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
5415	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
5416	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
5417
5418	/* CPUID(2) - config, mostly about caches. ignore. */
5419	/* CPUID(3) - processor serial number. ignore. */
5420	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
5421	/* CPUID(5) - mwait/monitor config. ignore. */
5422	/* CPUID(6) - power management. ignore. */
5423	/* CPUID(7) - ???. ignore. */
5424	/* CPUID(8) - ???. ignore. */
5425	/* CPUID(9) - DCA. ignore for now. */
5426	/* CPUID(a) - PeMo info. ignore for now. */
5427	/* CPUID(b) - topology info - takes ECX as input. ignore. */
5428
5429	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
5430	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
5431	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
5432	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
5433	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
5434	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
5435	{
5436	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
5437	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
5438	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
5439	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
5440	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
5441	}
5442
5443	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
5444	Note! Intel have/is marking many of the fields here as reserved. We
5445	will verify them as if it's an AMD CPU. */
5446	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
5447	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
5448	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
5449	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
5450	{
5451	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
5452	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
5453	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
5454	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5455	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
5456	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
5457	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
5458
5459	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
5460	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
5461	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
5462	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
5463	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
5464	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5465
5466	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
5467	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
5468	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
5469	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
5470
5471	/* CPUID(0x80000001).ecx */
5472	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
5473	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
5474	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
5475	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
5476	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
5477	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
5478	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
5479	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
5480	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
5481	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
5482	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
5483	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
5484	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
5485	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
5486	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5487	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5488	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5489	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5490	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5491	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5492	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5493	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5494	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5495	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5496	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5497	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5498	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5499	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5500	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5501	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5502	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5503	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5504
5505	/* CPUID(0x80000001).edx */
5506	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
5507	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
5508	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
5509	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
5510	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
5511	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
5512	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
5513	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
5514	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
5515	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
5516	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5517	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
5518	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
5519	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
5520	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
5521	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
5522	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
5523	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
5524	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5525	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5526	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5527	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
5528	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5529	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
5530	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
5531	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5532	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5533	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5534	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
5535	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5536	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5537	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5538
5539	/** @todo verify the rest as well. */
5540	}
5541	}
5542
5543
5544
5545	/*
5546	* Verify that we can support the features already exposed to the guest on
5547	* this host.
5548	*
5549	* Most of the features we're emulating requires intercepting instruction
5550	* and doing it the slow way, so there is no need to warn when they aren't
5551	* present in the host CPU. Thus we use IGN instead of EMU on these.
5552	*
5553	* Trailing comments:
5554	* "EMU" - Possible to emulate, could be lots of work and very slow.
5555	* "EMU?" - Can this be emulated?
5556	*/
5557	CPUMCPUID aGuestCpuIdStd[2];
5558	RT_ZERO(aGuestCpuIdStd);
5559	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5560
5561	/* CPUID(1).ecx */
5562	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5563	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5564	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5565	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5566	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5567	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5568	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5569	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5570	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5571	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5572	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5573	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5574	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5575	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5576	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5577	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5578	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5579	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5580	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5581	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5582	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5583	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5584	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5585	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5586	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5587	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5588	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5589	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5590	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5591	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5592	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5593	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5594
5595	/* CPUID(1).edx */
5596	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5597	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5598	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5599	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5600	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5601	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5602	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5603	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5604	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5605	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5606	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5607	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5608	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5609	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5610	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5611	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5612	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5613	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5614	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5615	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5616	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5617	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5618	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5619	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5620	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5621	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5622	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5623	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5624	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5625	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5626	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5627	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5628
5629	/* CPUID(0x80000000). */
5630	CPUMCPUID aGuestCpuIdExt[2];
5631	RT_ZERO(aGuestCpuIdExt);
5632	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5633	{
5634	/** @todo deal with no 0x80000001 on the host. */
5635	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5636	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5637
5638	/* CPUID(0x80000001).ecx */
5639	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5640	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5641	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5642	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5643	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5644	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5645	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5646	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5647	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5648	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5649	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5650	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5651	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5652	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5653	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5654	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5655	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5656	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5657	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5658	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5659	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5660	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5661	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5662	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5663	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5664	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5665	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5666	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5667	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5668	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5669	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5670	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5671
5672	/* CPUID(0x80000001).edx */
5673	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5674	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5675	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5676	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5677	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5678	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5679	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5680	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5681	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5682	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5683	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5684	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5685	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5686	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5687	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5688	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5689	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5690	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5691	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5692	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5693	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5694	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5695	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5696	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5697	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5698	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5699	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5700	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5701	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5702	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5703	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5704	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5705	}
5706
5707	/** @todo check leaf 7 */
5708
5709	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5710	* ECX=0: EAX - Valid bits in XCR0[31:0].
5711	* EBX - Maximum state size as per current XCR0 value.
5712	* ECX - Maximum state size for all supported features.
5713	* EDX - Valid bits in XCR0[63:32].
5714	* ECX=1: EAX - Various X-features.
5715	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5716	* ECX - Valid bits in IA32_XSS[31:0].
5717	* EDX - Valid bits in IA32_XSS[63:32].
5718	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5719	* if the bit invalid all four registers are set to zero.
5720	* EAX - The state size for this feature.
5721	* EBX - The state byte offset of this feature.
5722	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5723	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5724	*/
5725	uint64_t fGuestXcr0Mask = 0;
5726	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5727	if ( pCurLeaf
5728	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5729	&& ( pCurLeaf->uEax
5730	\|\| pCurLeaf->uEbx
5731	\|\| pCurLeaf->uEcx
5732	\|\| pCurLeaf->uEdx) )
5733	{
5734	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5735	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5736	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5737	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5738	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5739	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5740	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5741	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5742
5743	/* We don't support any additional features yet. */
5744	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5745	if (pCurLeaf && pCurLeaf->uEax)
5746	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5747	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5748	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5749	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5750	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5751	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5752
5753
5754	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5755	{
5756	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5757	if (pCurLeaf)
5758	{
5759	/* If advertised, the state component offset and size must match the one used by host. */
5760	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5761	{
5762	CPUMCPUID RawHost;
5763	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5764	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5765	if ( RawHost.uEbx != pCurLeaf->uEbx
5766	\|\| RawHost.uEax != pCurLeaf->uEax)
5767	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5768	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5769	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5770	}
5771	}
5772	}
5773	}
5774	/* Clear leaf 0xd just in case we're loading an old state... */
5775	else if (pCurLeaf)
5776	{
5777	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5778	{
5779	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5780	if (pCurLeaf)
5781	{
5782	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5783	\|\| ( pCurLeaf->uEax == 0
5784	&& pCurLeaf->uEbx == 0
5785	&& pCurLeaf->uEcx == 0
5786	&& pCurLeaf->uEdx == 0),
5787	("uVersion=%#x; %#x %#x %#x %#x\n",
5788	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5789	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5790	}
5791	}
5792	}
5793
5794	/* Update the fXStateGuestMask value for the VM. */
5795	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5796	{
5797	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5798	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5799	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5800	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5801	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5802	}
5803
5804	#undef CPUID_CHECK_RET
5805	#undef CPUID_CHECK_WRN
5806	#undef CPUID_CHECK2_RET
5807	#undef CPUID_CHECK2_WRN
5808	#undef CPUID_RAW_FEATURE_RET
5809	#undef CPUID_RAW_FEATURE_WRN
5810	#undef CPUID_RAW_FEATURE_IGN
5811	#undef CPUID_GST_FEATURE_RET
5812	#undef CPUID_GST_FEATURE_WRN
5813	#undef CPUID_GST_FEATURE_EMU
5814	#undef CPUID_GST_FEATURE_IGN
5815	#undef CPUID_GST_FEATURE2_RET
5816	#undef CPUID_GST_FEATURE2_WRN
5817	#undef CPUID_GST_FEATURE2_EMU
5818	#undef CPUID_GST_FEATURE2_IGN
5819	#undef CPUID_GST_AMD_FEATURE_RET
5820	#undef CPUID_GST_AMD_FEATURE_WRN
5821	#undef CPUID_GST_AMD_FEATURE_EMU
5822	#undef CPUID_GST_AMD_FEATURE_IGN
5823
5824	/*
5825	* We're good, commit the CPU ID leaves.
5826	*/
5827	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5828	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5829	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5830	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
5831	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5832	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
5833	AssertLogRelRCReturn(rc, rc);
5834
5835	return VINF_SUCCESS;
5836	}
5837
5838
5839	/**
5840	* Loads the CPU ID leaves saved by pass 0.
5841	*
5842	* @returns VBox status code.
5843	* @param pVM The cross context VM structure.
5844	* @param pSSM The saved state handle.
5845	* @param uVersion The format version.
5846	*/
5847	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5848	{
5849	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5850
5851	/*
5852	* Load the CPUID leaves array first and call worker to do the rest, just so
5853	* we can free the memory when we need to without ending up in column 1000.
5854	*/
5855	PCPUMCPUIDLEAF paLeaves;
5856	uint32_t cLeaves;
5857	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5858	AssertRC(rc);
5859	if (RT_SUCCESS(rc))
5860	{
5861	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
5862	RTMemFree(paLeaves);
5863	}
5864	return rc;
5865	}
5866
5867
5868
5869	/**
5870	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5871	*
5872	* @returns VBox status code.
5873	* @param pVM The cross context VM structure.
5874	* @param pSSM The saved state handle.
5875	* @param uVersion The format version.
5876	*/
5877	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5878	{
5879	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5880
5881	/*
5882	* Restore the CPUID leaves.
5883	*
5884	* Note that we support restoring less than the current amount of standard
5885	* leaves because we've been allowed more is newer version of VBox.
5886	*/
5887	uint32_t cElements;
5888	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5889	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5890	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5891	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5892
5893	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5894	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5895	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5896	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5897
5898	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5899	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5900	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5901	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5902
5903	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5904
5905	/*
5906	* Check that the basic cpuid id information is unchanged.
5907	*/
5908	/** @todo we should check the 64 bits capabilities too! */
5909	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5910	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5911	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5912	uint32_t au32CpuIdSaved[8];
5913	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5914	if (RT_SUCCESS(rc))
5915	{
5916	/* Ignore CPU stepping. */
5917	au32CpuId[4] &= 0xfffffff0;
5918	au32CpuIdSaved[4] &= 0xfffffff0;
5919
5920	/* Ignore APIC ID (AMD specs). */
5921	au32CpuId[5] &= ~0xff000000;
5922	au32CpuIdSaved[5] &= ~0xff000000;
5923
5924	/* Ignore the number of Logical CPUs (AMD specs). */
5925	au32CpuId[5] &= ~0x00ff0000;
5926	au32CpuIdSaved[5] &= ~0x00ff0000;
5927
5928	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5929	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5930	\| X86_CPUID_FEATURE_ECX_VMX
5931	\| X86_CPUID_FEATURE_ECX_SMX
5932	\| X86_CPUID_FEATURE_ECX_EST
5933	\| X86_CPUID_FEATURE_ECX_TM2
5934	\| X86_CPUID_FEATURE_ECX_CNTXID
5935	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5936	\| X86_CPUID_FEATURE_ECX_PDCM
5937	\| X86_CPUID_FEATURE_ECX_DCA
5938	\| X86_CPUID_FEATURE_ECX_X2APIC
5939	);
5940	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5941	\| X86_CPUID_FEATURE_ECX_VMX
5942	\| X86_CPUID_FEATURE_ECX_SMX
5943	\| X86_CPUID_FEATURE_ECX_EST
5944	\| X86_CPUID_FEATURE_ECX_TM2
5945	\| X86_CPUID_FEATURE_ECX_CNTXID
5946	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5947	\| X86_CPUID_FEATURE_ECX_PDCM
5948	\| X86_CPUID_FEATURE_ECX_DCA
5949	\| X86_CPUID_FEATURE_ECX_X2APIC
5950	);
5951
5952	/* Make sure we don't forget to update the masks when enabling
5953	* features in the future.
5954	*/
5955	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5956	( X86_CPUID_FEATURE_ECX_DTES64
5957	\| X86_CPUID_FEATURE_ECX_VMX
5958	\| X86_CPUID_FEATURE_ECX_SMX
5959	\| X86_CPUID_FEATURE_ECX_EST
5960	\| X86_CPUID_FEATURE_ECX_TM2
5961	\| X86_CPUID_FEATURE_ECX_CNTXID
5962	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5963	\| X86_CPUID_FEATURE_ECX_PDCM
5964	\| X86_CPUID_FEATURE_ECX_DCA
5965	\| X86_CPUID_FEATURE_ECX_X2APIC
5966	)));
5967	/* do the compare */
5968	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5969	{
5970	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5971	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5972	"Saved=%.*Rhxs\n"
5973	"Real =%.*Rhxs\n",
5974	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5975	sizeof(au32CpuId), au32CpuId));
5976	else
5977	{
5978	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5979	"Saved=%.*Rhxs\n"
5980	"Real =%.*Rhxs\n",
5981	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5982	sizeof(au32CpuId), au32CpuId));
5983	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5984	}
5985	}
5986	}
5987
5988	return rc;
5989	}
5990
5991
5992
5993	/*
5994	*
5995	*
5996	* CPUID Info Handler.
5997	* CPUID Info Handler.
5998	* CPUID Info Handler.
5999	*
6000	*
6001	*/
6002
6003
6004
6005	/**
6006	* Get L1 cache / TLS associativity.
6007	*/
6008	static const char getCacheAss(unsigned u, char pszBuf)
6009	{
6010	if (u == 0)
6011	return "res0 ";
6012	if (u == 1)
6013	return "direct";
6014	if (u == 255)
6015	return "fully";
6016	if (u >= 256)
6017	return "???";
6018
6019	RTStrPrintf(pszBuf, 16, "%d way", u);
6020	return pszBuf;
6021	}
6022
6023
6024	/**
6025	* Get L2 cache associativity.
6026	*/
6027	const char *getL2CacheAss(unsigned u)
6028	{
6029	switch (u)
6030	{
6031	case 0: return "off ";
6032	case 1: return "direct";
6033	case 2: return "2 way ";
6034	case 3: return "res3 ";
6035	case 4: return "4 way ";
6036	case 5: return "res5 ";
6037	case 6: return "8 way ";
6038	case 7: return "res7 ";
6039	case 8: return "16 way";
6040	case 9: return "res9 ";
6041	case 10: return "res10 ";
6042	case 11: return "res11 ";
6043	case 12: return "res12 ";
6044	case 13: return "res13 ";
6045	case 14: return "res14 ";
6046	case 15: return "fully ";
6047	default: return "????";
6048	}
6049	}
6050
6051
6052	/** CPUID(1).EDX field descriptions. */
6053	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6054	{
6055	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6056	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6057	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6058	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6059	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6060	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6061	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6062	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6063	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6064	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6065	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6066	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6067	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6068	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6069	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6070	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6071	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6072	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6073	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6074	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6075	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6076	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6077	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6078	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6079	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6080	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6081	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6082	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6083	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6084	DBGFREGSUBFIELD_TERMINATOR()
6085	};
6086
6087	/** CPUID(1).ECX field descriptions. */
6088	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6089	{
6090	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6091	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6092	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6093	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6094	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6095	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6096	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6097	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6098	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6099	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6100	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6101	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6102	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6103	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6104	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6105	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6106	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6107	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6108	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6109	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6110	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6111	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6112	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6113	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6114	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6115	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6116	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6117	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6118	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6119	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6120	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6121	DBGFREGSUBFIELD_TERMINATOR()
6122	};
6123
6124	/** CPUID(7,0).EBX field descriptions. */
6125	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6126	{
6127	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6128	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6129	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6130	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6131	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6132	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6133	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6134	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6135	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6136	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6137	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6138	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6139	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6140	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6141	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6142	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6143	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6144	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6145	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6146	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6147	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6148	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6149	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6150	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6151	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6152	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6153	DBGFREGSUBFIELD_TERMINATOR()
6154	};
6155
6156	/** CPUID(7,0).ECX field descriptions. */
6157	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6158	{
6159	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6160	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6161	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6162	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6163	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6164	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6165	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6166	DBGFREGSUBFIELD_TERMINATOR()
6167	};
6168
6169	/** CPUID(7,0).EDX field descriptions. */
6170	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6171	{
6172	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6173	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6174	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6175	DBGFREGSUBFIELD_TERMINATOR()
6176	};
6177
6178
6179	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6180	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6181	{
6182	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6183	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6184	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6185	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6186	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6187	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6188	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6189	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6190	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6191	DBGFREGSUBFIELD_TERMINATOR()
6192	};
6193
6194	/** CPUID(13,1).EAX field descriptions. */
6195	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6196	{
6197	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6198	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6199	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6200	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6201	DBGFREGSUBFIELD_TERMINATOR()
6202	};
6203
6204
6205	/** CPUID(0x80000001,0).EDX field descriptions. */
6206	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6207	{
6208	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6209	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6210	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6211	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6212	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6213	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6214	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6215	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6216	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6217	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6218	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6219	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6220	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6221	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6222	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6223	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6224	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6225	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6226	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6227	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6228	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6229	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6230	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6231	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6232	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6233	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6234	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6235	DBGFREGSUBFIELD_TERMINATOR()
6236	};
6237
6238	/** CPUID(0x80000001,0).ECX field descriptions. */
6239	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6240	{
6241	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6242	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6243	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6244	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6245	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6246	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6247	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6248	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6249	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6250	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6251	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6252	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6253	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6254	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6255	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6256	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6257	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6258	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6259	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6260	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6261	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6262	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6263	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6264	DBGFREGSUBFIELD_TERMINATOR()
6265	};
6266
6267	/** CPUID(0x8000000a,0).EDX field descriptions. */
6268	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6269	{
6270	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6271	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6272	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6273	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6274	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6275	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6276	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6277	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6278	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6279	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6280	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6281	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6282	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6283	DBGFREGSUBFIELD_TERMINATOR()
6284	};
6285
6286
6287	/** CPUID(0x80000007,0).EDX field descriptions. */
6288	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6289	{
6290	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6291	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6292	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6293	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6294	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6295	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6296	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6297	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6298	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6299	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6300	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6301	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6302	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6303	DBGFREGSUBFIELD_TERMINATOR()
6304	};
6305
6306	/** CPUID(0x80000008,0).EBX field descriptions. */
6307	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6308	{
6309	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6310	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6311	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6312	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6313	DBGFREGSUBFIELD_TERMINATOR()
6314	};
6315
6316
6317	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6318	const char *pszLeadIn, uint32_t cchWidth)
6319	{
6320	if (pszLeadIn)
6321	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6322
6323	for (uint32_t iBit = 0; iBit < 32; iBit++)
6324	if (RT_BIT_32(iBit) & uVal)
6325	{
6326	while ( pDesc->pszName != NULL
6327	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6328	pDesc++;
6329	if ( pDesc->pszName != NULL
6330	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6331	{
6332	if (pDesc->cBits == 1)
6333	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6334	else
6335	{
6336	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6337	if (pDesc->cBits < 32)
6338	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6339	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6340	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6341	}
6342	}
6343	else
6344	pHlp->pfnPrintf(pHlp, " %u", iBit);
6345	}
6346	if (pszLeadIn)
6347	pHlp->pfnPrintf(pHlp, "\n");
6348	}
6349
6350
6351	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6352	const char *pszLeadIn, uint32_t cchWidth)
6353	{
6354	if (pszLeadIn)
6355	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6356
6357	for (uint32_t iBit = 0; iBit < 64; iBit++)
6358	if (RT_BIT_64(iBit) & uVal)
6359	{
6360	while ( pDesc->pszName != NULL
6361	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6362	pDesc++;
6363	if ( pDesc->pszName != NULL
6364	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6365	{
6366	if (pDesc->cBits == 1)
6367	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6368	else
6369	{
6370	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6371	if (pDesc->cBits < 64)
6372	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6373	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6374	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6375	}
6376	}
6377	else
6378	pHlp->pfnPrintf(pHlp, " %u", iBit);
6379	}
6380	if (pszLeadIn)
6381	pHlp->pfnPrintf(pHlp, "\n");
6382	}
6383
6384
6385	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6386	const char *pszLeadIn, uint32_t cchWidth)
6387	{
6388	if (!uVal)
6389	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6390	else
6391	{
6392	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6393	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6394	pHlp->pfnPrintf(pHlp, " )\n");
6395	}
6396	}
6397
6398
6399	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6400	uint32_t cchWidth)
6401	{
6402	uint32_t uCombined = uVal1 \| uVal2;
6403	for (uint32_t iBit = 0; iBit < 32; iBit++)
6404	if ( (RT_BIT_32(iBit) & uCombined)
6405	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6406	{
6407	while ( pDesc->pszName != NULL
6408	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6409	pDesc++;
6410
6411	if ( pDesc->pszName != NULL
6412	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6413	{
6414	size_t cchMnemonic = strlen(pDesc->pszName);
6415	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6416	size_t cchDesc = strlen(pszDesc);
6417	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6418	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6419	if (pDesc->cBits < 32)
6420	{
6421	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6422	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6423	}
6424
6425	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6426	pDesc->pszName, pszDesc,
6427	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6428	uFieldValue1, uFieldValue2);
6429
6430	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6431	pDesc++;
6432	}
6433	else
6434	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6435	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6436	}
6437	}
6438
6439
6440	/**
6441	* Produces a detailed summary of standard leaf 0x00000001.
6442	*
6443	* @param pHlp The info helper functions.
6444	* @param pCurLeaf The 0x00000001 leaf.
6445	* @param fVerbose Whether to be very verbose or not.
6446	* @param fIntel Set if intel CPU.
6447	*/
6448	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6449	{
6450	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6451	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6452	uint32_t uEAX = pCurLeaf->uEax;
6453	uint32_t uEBX = pCurLeaf->uEbx;
6454
6455	pHlp->pfnPrintf(pHlp,
6456	"%36s %2d \tExtended: %d \tEffective: %d\n"
6457	"%36s %2d \tExtended: %d \tEffective: %d\n"
6458	"%36s %d\n"
6459	"%36s %d (%s)\n"
6460	"%36s %#04x\n"
6461	"%36s %d\n"
6462	"%36s %d\n"
6463	"%36s %#04x\n"
6464	,
6465	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6466	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6467	"Stepping:", ASMGetCpuStepping(uEAX),
6468	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6469	"APIC ID:", (uEBX >> 24) & 0xff,
6470	"Logical CPUs:",(uEBX >> 16) & 0xff,
6471	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6472	"Brand ID:", (uEBX >> 0) & 0xff);
6473	if (fVerbose)
6474	{
6475	CPUMCPUID Host;
6476	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6477	pHlp->pfnPrintf(pHlp, "Features\n");
6478	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6479	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6480	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6481	}
6482	else
6483	{
6484	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6485	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6486	}
6487	}
6488
6489
6490	/**
6491	* Produces a detailed summary of standard leaf 0x00000007.
6492	*
6493	* @param pHlp The info helper functions.
6494	* @param paLeaves The CPUID leaves array.
6495	* @param cLeaves The number of leaves in the array.
6496	* @param pCurLeaf The first 0x00000007 leaf.
6497	* @param fVerbose Whether to be very verbose or not.
6498	*/
6499	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6500	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6501	{
6502	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6503	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6504	for (;;)
6505	{
6506	CPUMCPUID Host;
6507	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6508
6509	switch (pCurLeaf->uSubLeaf)
6510	{
6511	case 0:
6512	if (fVerbose)
6513	{
6514	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6515	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6516	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6517	if (pCurLeaf->uEdx \|\| Host.uEdx)
6518	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6519	}
6520	else
6521	{
6522	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6523	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6524	if (pCurLeaf->uEdx)
6525	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6526	}
6527	break;
6528
6529	default:
6530	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6531	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6532	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6533	break;
6534
6535	}
6536
6537	/* advance. */
6538	pCurLeaf++;
6539	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6540	\|\| pCurLeaf->uLeaf != 0x7)
6541	break;
6542	}
6543	}
6544
6545
6546	/**
6547	* Produces a detailed summary of standard leaf 0x0000000d.
6548	*
6549	* @param pHlp The info helper functions.
6550	* @param paLeaves The CPUID leaves array.
6551	* @param cLeaves The number of leaves in the array.
6552	* @param pCurLeaf The first 0x00000007 leaf.
6553	* @param fVerbose Whether to be very verbose or not.
6554	*/
6555	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6556	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6557	{
6558	RT_NOREF_PV(fVerbose);
6559	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6560	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6561	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6562	{
6563	CPUMCPUID Host;
6564	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6565
6566	switch (uSubLeaf)
6567	{
6568	case 0:
6569	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6570	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6571	pCurLeaf->uEbx, pCurLeaf->uEcx);
6572	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6573
6574	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6575	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6576	"Valid XCR0 bits, guest:", 42);
6577	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6578	"Valid XCR0 bits, host:", 42);
6579	break;
6580
6581	case 1:
6582	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6583	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6584	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6585
6586	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6587	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6588	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6589
6590	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6591	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6592	" Valid IA32_XSS bits, guest:", 42);
6593	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6594	" Valid IA32_XSS bits, host:", 42);
6595	break;
6596
6597	default:
6598	if ( pCurLeaf
6599	&& pCurLeaf->uSubLeaf == uSubLeaf
6600	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6601	{
6602	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6603	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6604	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6605	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6606	if (pCurLeaf->uEdx)
6607	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6608	pHlp->pfnPrintf(pHlp, " --");
6609	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6610	pHlp->pfnPrintf(pHlp, "\n");
6611	}
6612	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6613	{
6614	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6615	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6616	if (Host.uEcx & ~RT_BIT_32(0))
6617	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6618	if (Host.uEdx)
6619	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6620	pHlp->pfnPrintf(pHlp, " --");
6621	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6622	pHlp->pfnPrintf(pHlp, "\n");
6623	}
6624	break;
6625
6626	}
6627
6628	/* advance. */
6629	if (pCurLeaf)
6630	{
6631	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6632	&& pCurLeaf->uSubLeaf <= uSubLeaf
6633	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6634	pCurLeaf++;
6635	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6636	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6637	pCurLeaf = NULL;
6638	}
6639	}
6640	}
6641
6642
6643	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6644	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6645	{
6646	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6647	&& pCurLeaf->uLeaf <= uUpToLeaf)
6648	{
6649	pHlp->pfnPrintf(pHlp,
6650	" %s\n"
6651	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6652	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6653	&& pCurLeaf->uLeaf <= uUpToLeaf)
6654	{
6655	CPUMCPUID Host;
6656	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6657	pHlp->pfnPrintf(pHlp,
6658	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6659	"Hst: %08x %08x %08x %08x\n",
6660	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6661	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6662	pCurLeaf++;
6663	}
6664	}
6665
6666	return pCurLeaf;
6667	}
6668
6669
6670	/**
6671	* Display the guest CpuId leaves.
6672	*
6673	* @param pVM The cross context VM structure.
6674	* @param pHlp The info helper functions.
6675	* @param pszArgs "terse", "default" or "verbose".
6676	*/
6677	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6678	{
6679	/*
6680	* Parse the argument.
6681	*/
6682	unsigned iVerbosity = 1;
6683	if (pszArgs)
6684	{
6685	pszArgs = RTStrStripL(pszArgs);
6686	if (!strcmp(pszArgs, "terse"))
6687	iVerbosity--;
6688	else if (!strcmp(pszArgs, "verbose"))
6689	iVerbosity++;
6690	}
6691
6692	uint32_t uLeaf;
6693	CPUMCPUID Host;
6694	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6695	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6696	PCCPUMCPUIDLEAF pCurLeaf;
6697	PCCPUMCPUIDLEAF pNextLeaf;
6698	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6699	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6700	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6701
6702	/*
6703	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6704	*/
6705	uint32_t cHstMax = ASMCpuId_EAX(0);
6706	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6707	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6708	pHlp->pfnPrintf(pHlp,
6709	" Raw Standard CPUID Leaves\n"
6710	" Leaf/sub-leaf eax ebx ecx edx\n");
6711	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6712	{
6713	uint32_t cMaxSubLeaves = 1;
6714	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6715	cMaxSubLeaves = 16;
6716	else if (uLeaf == 0xd)
6717	cMaxSubLeaves = 128;
6718
6719	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6720	{
6721	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6722	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6723	&& pCurLeaf->uLeaf == uLeaf
6724	&& pCurLeaf->uSubLeaf == uSubLeaf)
6725	{
6726	pHlp->pfnPrintf(pHlp,
6727	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6728	"Hst: %08x %08x %08x %08x\n",
6729	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6730	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6731	pCurLeaf++;
6732	}
6733	else if ( uLeaf != 0xd
6734	\|\| uSubLeaf <= 1
6735	\|\| Host.uEbx != 0 )
6736	pHlp->pfnPrintf(pHlp,
6737	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6738	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6739
6740	/* Done? */
6741	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6742	\|\| pCurLeaf->uLeaf != uLeaf)
6743	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6744	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6745	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6746	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6747	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6748	)
6749	)
6750	break;
6751	}
6752	}
6753	pNextLeaf = pCurLeaf;
6754
6755	/*
6756	* If verbose, decode it.
6757	*/
6758	if (iVerbosity && paLeaves[0].uLeaf == 0)
6759	pHlp->pfnPrintf(pHlp,
6760	"%36s %.04s%.04s%.04s\n"
6761	"%36s 0x00000000-%#010x\n"
6762	,
6763	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6764	"Supports:", paLeaves[0].uEax);
6765
6766	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6767	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6768
6769	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6770	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6771
6772	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6773	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6774
6775	pCurLeaf = pNextLeaf;
6776
6777	/*
6778	* Hypervisor leaves.
6779	*
6780	* Unlike most of the other leaves reported, the guest hypervisor leaves
6781	* aren't a subset of the host CPUID bits.
6782	*/
6783	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6784
6785	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6786	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6787	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6788	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6789	cMax = RT_MAX(cHstMax, cGstMax);
6790	if (cMax >= UINT32_C(0x40000000))
6791	{
6792	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6793
6794	/** @todo dump these in more detail. */
6795
6796	pCurLeaf = pNextLeaf;
6797	}
6798
6799
6800	/*
6801	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6802	* Implemented after AMD specs.
6803	*/
6804	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6805
6806	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6807	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6808	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6809	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6810	cMax = RT_MAX(cHstMax, cGstMax);
6811	if (cMax >= UINT32_C(0x80000000))
6812	{
6813
6814	pHlp->pfnPrintf(pHlp,
6815	" Raw Extended CPUID Leaves\n"
6816	" Leaf/sub-leaf eax ebx ecx edx\n");
6817	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6818	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6819	{
6820	uint32_t cMaxSubLeaves = 1;
6821	if (uLeaf == UINT32_C(0x8000001d))
6822	cMaxSubLeaves = 16;
6823
6824	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6825	{
6826	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6827	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6828	&& pCurLeaf->uLeaf == uLeaf
6829	&& pCurLeaf->uSubLeaf == uSubLeaf)
6830	{
6831	pHlp->pfnPrintf(pHlp,
6832	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6833	"Hst: %08x %08x %08x %08x\n",
6834	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6835	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6836	pCurLeaf++;
6837	}
6838	else if ( uLeaf != 0xd
6839	\|\| uSubLeaf <= 1
6840	\|\| Host.uEbx != 0 )
6841	pHlp->pfnPrintf(pHlp,
6842	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6843	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6844
6845	/* Done? */
6846	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6847	\|\| pCurLeaf->uLeaf != uLeaf)
6848	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6849	break;
6850	}
6851	}
6852	pNextLeaf = pCurLeaf;
6853
6854	/*
6855	* Understandable output
6856	*/
6857	if (iVerbosity)
6858	pHlp->pfnPrintf(pHlp,
6859	"Ext Name: %.4s%.4s%.4s\n"
6860	"Ext Supports: 0x80000000-%#010x\n",
6861	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6862
6863	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6864	if (iVerbosity && pCurLeaf)
6865	{
6866	uint32_t uEAX = pCurLeaf->uEax;
6867	pHlp->pfnPrintf(pHlp,
6868	"Family: %d \tExtended: %d \tEffective: %d\n"
6869	"Model: %d \tExtended: %d \tEffective: %d\n"
6870	"Stepping: %d\n"
6871	"Brand ID: %#05x\n",
6872	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6873	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6874	ASMGetCpuStepping(uEAX),
6875	pCurLeaf->uEbx & 0xfff);
6876
6877	if (iVerbosity == 1)
6878	{
6879	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6880	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6881	}
6882	else
6883	{
6884	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6885	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6886	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6887	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6888	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6889	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
6890	{
6891	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
6892	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6893	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
6894	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
6895	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
6896	}
6897	}
6898	}
6899
6900	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6901	{
6902	char szString[443+1] = {0};
6903	uint32_t pu32 = (uint32_t )szString;
6904	*pu32++ = pCurLeaf->uEax;
6905	*pu32++ = pCurLeaf->uEbx;
6906	*pu32++ = pCurLeaf->uEcx;
6907	*pu32++ = pCurLeaf->uEdx;
6908	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6909	if (pCurLeaf)
6910	{
6911	*pu32++ = pCurLeaf->uEax;
6912	*pu32++ = pCurLeaf->uEbx;
6913	*pu32++ = pCurLeaf->uEcx;
6914	*pu32++ = pCurLeaf->uEdx;
6915	}
6916	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6917	if (pCurLeaf)
6918	{
6919	*pu32++ = pCurLeaf->uEax;
6920	*pu32++ = pCurLeaf->uEbx;
6921	*pu32++ = pCurLeaf->uEcx;
6922	*pu32++ = pCurLeaf->uEdx;
6923	}
6924	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6925	}
6926
6927	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6928	{
6929	uint32_t uEAX = pCurLeaf->uEax;
6930	uint32_t uEBX = pCurLeaf->uEbx;
6931	uint32_t uECX = pCurLeaf->uEcx;
6932	uint32_t uEDX = pCurLeaf->uEdx;
6933	char sz1[32];
6934	char sz2[32];
6935
6936	pHlp->pfnPrintf(pHlp,
6937	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6938	"TLB 2/4M Data: %s %3d entries\n",
6939	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6940	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6941	pHlp->pfnPrintf(pHlp,
6942	"TLB 4K Instr/Uni: %s %3d entries\n"
6943	"TLB 4K Data: %s %3d entries\n",
6944	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6945	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6946	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6947	"L1 Instr Cache Lines Per Tag: %d\n"
6948	"L1 Instr Cache Associativity: %s\n"
6949	"L1 Instr Cache Size: %d KB\n",
6950	(uEDX >> 0) & 0xff,
6951	(uEDX >> 8) & 0xff,
6952	getCacheAss((uEDX >> 16) & 0xff, sz1),
6953	(uEDX >> 24) & 0xff);
6954	pHlp->pfnPrintf(pHlp,
6955	"L1 Data Cache Line Size: %d bytes\n"
6956	"L1 Data Cache Lines Per Tag: %d\n"
6957	"L1 Data Cache Associativity: %s\n"
6958	"L1 Data Cache Size: %d KB\n",
6959	(uECX >> 0) & 0xff,
6960	(uECX >> 8) & 0xff,
6961	getCacheAss((uECX >> 16) & 0xff, sz1),
6962	(uECX >> 24) & 0xff);
6963	}
6964
6965	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6966	{
6967	uint32_t uEAX = pCurLeaf->uEax;
6968	uint32_t uEBX = pCurLeaf->uEbx;
6969	uint32_t uEDX = pCurLeaf->uEdx;
6970
6971	pHlp->pfnPrintf(pHlp,
6972	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6973	"L2 TLB 2/4M Data: %s %4d entries\n",
6974	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6975	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6976	pHlp->pfnPrintf(pHlp,
6977	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6978	"L2 TLB 4K Data: %s %4d entries\n",
6979	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6980	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6981	pHlp->pfnPrintf(pHlp,
6982	"L2 Cache Line Size: %d bytes\n"
6983	"L2 Cache Lines Per Tag: %d\n"
6984	"L2 Cache Associativity: %s\n"
6985	"L2 Cache Size: %d KB\n",
6986	(uEDX >> 0) & 0xff,
6987	(uEDX >> 8) & 0xf,
6988	getL2CacheAss((uEDX >> 12) & 0xf),
6989	(uEDX >> 16) & 0xffff);
6990	}
6991
6992	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
6993	{
6994	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6995	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
6996	{
6997	if (iVerbosity < 1)
6998	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
6999	else
7000	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7001	}
7002	}
7003
7004	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7005	if (pCurLeaf != NULL)
7006	{
7007	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7008	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7009	{
7010	if (iVerbosity < 1)
7011	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7012	else
7013	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7014	}
7015
7016	if (iVerbosity)
7017	{
7018	uint32_t uEAX = pCurLeaf->uEax;
7019	uint32_t uECX = pCurLeaf->uEcx;
7020
7021	pHlp->pfnPrintf(pHlp,
7022	"Physical Address Width: %d bits\n"
7023	"Virtual Address Width: %d bits\n"
7024	"Guest Physical Address Width: %d bits\n",
7025	(uEAX >> 0) & 0xff,
7026	(uEAX >> 8) & 0xff,
7027	(uEAX >> 16) & 0xff);
7028	pHlp->pfnPrintf(pHlp,
7029	"Physical Core Count: %d\n",
7030	((uECX >> 0) & 0xff) + 1);
7031	}
7032	}
7033
7034	pCurLeaf = pNextLeaf;
7035	}
7036
7037
7038
7039	/*
7040	* Centaur.
7041	*/
7042	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7043
7044	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7045	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7046	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7047	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7048	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7049	cMax = RT_MAX(cHstMax, cGstMax);
7050	if (cMax >= UINT32_C(0xc0000000))
7051	{
7052	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7053
7054	/*
7055	* Understandable output
7056	*/
7057	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7058	pHlp->pfnPrintf(pHlp,
7059	"Centaur Supports: 0xc0000000-%#010x\n",
7060	pCurLeaf->uEax);
7061
7062	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7063	{
7064	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7065	uint32_t uEdxGst = pCurLeaf->uEdx;
7066	uint32_t uEdxHst = Host.uEdx;
7067
7068	if (iVerbosity == 1)
7069	{
7070	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7071	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7072	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7073	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7074	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7075	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7076	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7077	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7078	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7079	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7080	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7081	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7082	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7083	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7084	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7085	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7086	for (unsigned iBit = 14; iBit < 32; iBit++)
7087	if (uEdxGst & RT_BIT(iBit))
7088	pHlp->pfnPrintf(pHlp, " %d", iBit);
7089	pHlp->pfnPrintf(pHlp, "\n");
7090	}
7091	else
7092	{
7093	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7094	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7095	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7096	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7097	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7098	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7099	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7100	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7101	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7102	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7103	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7104	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7105	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7106	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7107	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7108	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7109	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7110	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7111	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7112	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7113	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7114	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7115	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7116	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7117	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7118	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7119	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7120	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7121	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7122	for (unsigned iBit = 27; iBit < 32; iBit++)
7123	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7124	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7125	pHlp->pfnPrintf(pHlp, "\n");
7126	}
7127	}
7128
7129	pCurLeaf = pNextLeaf;
7130	}
7131
7132	/*
7133	* The remainder.
7134	*/
7135	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7136	}
7137
7138
7139
7140
7141
7142	/*
7143	*
7144	*
7145	* PATM interfaces.
7146	* PATM interfaces.
7147	* PATM interfaces.
7148	*
7149	*
7150	*/
7151
7152
7153	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
7154	/** @name Patchmanager CPUID legacy table APIs
7155	* @{
7156	*/
7157
7158	/**
7159	* Gets a pointer to the default CPUID leaf.
7160	*
7161	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
7162	* @param pVM The cross context VM structure.
7163	* @remark Intended for PATM only.
7164	*/
7165	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
7166	{
7167	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
7168	}
7169
7170
7171	/**
7172	* Gets a number of standard CPUID leaves (PATM only).
7173	*
7174	* @returns Number of leaves.
7175	* @param pVM The cross context VM structure.
7176	* @remark Intended for PATM - legacy, don't use in new code.
7177	*/
7178	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
7179	{
7180	RT_NOREF_PV(pVM);
7181	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
7182	}
7183
7184
7185	/**
7186	* Gets a number of extended CPUID leaves (PATM only).
7187	*
7188	* @returns Number of leaves.
7189	* @param pVM The cross context VM structure.
7190	* @remark Intended for PATM - legacy, don't use in new code.
7191	*/
7192	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
7193	{
7194	RT_NOREF_PV(pVM);
7195	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
7196	}
7197
7198
7199	/**
7200	* Gets a number of centaur CPUID leaves.
7201	*
7202	* @returns Number of leaves.
7203	* @param pVM The cross context VM structure.
7204	* @remark Intended for PATM - legacy, don't use in new code.
7205	*/
7206	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
7207	{
7208	RT_NOREF_PV(pVM);
7209	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
7210	}
7211
7212
7213	/**
7214	* Gets a pointer to the array of standard CPUID leaves.
7215	*
7216	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
7217	*
7218	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
7219	* @param pVM The cross context VM structure.
7220	* @remark Intended for PATM - legacy, don't use in new code.
7221	*/
7222	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
7223	{
7224	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
7225	}
7226
7227
7228	/**
7229	* Gets a pointer to the array of extended CPUID leaves.
7230	*
7231	* CPUMGetGuestCpuIdExtMax() give the size of the array.
7232	*
7233	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
7234	* @param pVM The cross context VM structure.
7235	* @remark Intended for PATM - legacy, don't use in new code.
7236	*/
7237	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
7238	{
7239	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
7240	}
7241
7242
7243	/**
7244	* Gets a pointer to the array of centaur CPUID leaves.
7245	*
7246	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
7247	*
7248	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
7249	* @param pVM The cross context VM structure.
7250	* @remark Intended for PATM - legacy, don't use in new code.
7251	*/
7252	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
7253	{
7254	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
7255	}
7256
7257	/** @} */
7258	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
7259
7260	#endif /* VBOX_IN_VMM */
7261

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 73269

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