CPUMR3CpuId.cpp@ 73711

Last change on this file since 73711 was 73606, checked in by vboxsync, 6 years ago

VMM: Nested VMX: bugref:9180 Various bits:

IEM: Started VMXON, VMXOFF implementation, use IEM_OPCODE_GET_NEXT_RM.
IEM: Fixed INVPCID C impl, removed unused IEMExecDecodedInvpcid.
IEM: Updated iemCImpl_load_CrX to check for CR0/CR4 fixed bits in VMX.
IEM: Update offModRm to reset/re-initialize where needed.
CPUM: Added VMX root, non-root mode and other bits and updated a few places where they're used.
HM: Started adding fine-grained VMX instruction failure diagnostics.
HM: Made VM instruction error an enum.
HM: Added HMVMXAll.cpp for all context VMX code.
Ensure building with VBOX_WITH_NESTED_HWVIRT_[SVM|VMX] does the right thing based on host CPU.
CPUM: Added dumping of nested-VMX CPUMCTX state.
HMVMXR0: Added memory operand decoding.
HMVMXR0: VMX instr. privilege checks (CR0/CR4 read shadows are not consulted, so we need to do them)
HM: Added some more bit-field representaions.
Recompiler: Refuse to run when in nested-VMX guest code.

Property svn:eol-style set to native
Property svn:keywords set to Author Date Id Revision

File size: 337.9 KB

Line
1	/* $Id: CPUMR3CpuId.cpp 73606 2018-08-10 07:38:56Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/mm.h>
31	#include <VBox/sup.h>
32
33	#include <VBox/err.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/ctype.h>
36	#include <iprt/mem.h>
37	#include <iprt/string.h>
38
39
40	/*********************************************************************************************************************************
41	* Defined Constants And Macros *
42	*********************************************************************************************************************************/
43	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
44	#define CPUM_CPUID_MAX_LEAVES 2048
45	/* Max size we accept for the XSAVE area. */
46	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
47	/* Min size we accept for the XSAVE area. */
48	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
49
50
51	/*********************************************************************************************************************************
52	* Global Variables *
53	*********************************************************************************************************************************/
54	/**
55	* The intel pentium family.
56	*/
57	static const CPUMMICROARCH g_aenmIntelFamily06[] =
58	{
59	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
60	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
61	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
63	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
64	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
65	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
66	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
67	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
68	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
69	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
70	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
71	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
72	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
73	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
74	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
75	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
81	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
82	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
83	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
86	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
88	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
89	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
90	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
91	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
97	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
98	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
99	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
102	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
104	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
105	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
106	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
107	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
113	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
114	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
115	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
118	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
121	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
122	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
130	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
131	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
136	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [78(0x4e)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed */
138	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / unconfirmed, Broadwell-E */
139	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu */
145	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
146	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
147	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
150	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
152	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
153	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
154	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
155	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
159	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
160	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
161	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
162	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
163	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
164	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
165	/[106(0x6a)] = / kCpumMicroarch_Intel_Unknown,
166	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
167	/[108(0x6c)] = / kCpumMicroarch_Intel_Unknown,
168	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
169	/[110(0x6e)] = / kCpumMicroarch_Intel_Unknown,
170	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
171	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
172	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
173	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
174	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
175	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
176	/[117(0x75)] = / kCpumMicroarch_Intel_Unknown,
177	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
178	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
179	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
180	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
181	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
182	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
183	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
184	/[125(0x7d)] = / kCpumMicroarch_Intel_Unknown,
185	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
186	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
187	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
188	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
189	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
190	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
191	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
192	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
193	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
194	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
195	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
196	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
197	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
198	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
199	/[140(0x8c)] = / kCpumMicroarch_Intel_Unknown,
200	/[141(0x8d)] = / kCpumMicroarch_Intel_Unknown,
201	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
202	/[143(0x8f)] = / kCpumMicroarch_Intel_Unknown,
203	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
204	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
205	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
206	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
207	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
208	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
209	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
210	/[151(0x97)] = / kCpumMicroarch_Intel_Unknown,
211	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
212	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
213	/[154(0x9a)] = / kCpumMicroarch_Intel_Unknown,
214	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
215	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
216	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
217	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
218	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
219	};
220	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0x9f+1);
221
222
223	/**
224	* Figures out the (sub-)micro architecture given a bit of CPUID info.
225	*
226	* @returns Micro architecture.
227	* @param enmVendor The CPU vendor .
228	* @param bFamily The CPU family.
229	* @param bModel The CPU model.
230	* @param bStepping The CPU stepping.
231	*/
232	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
233	uint8_t bModel, uint8_t bStepping)
234	{
235	if (enmVendor == CPUMCPUVENDOR_AMD)
236	{
237	switch (bFamily)
238	{
239	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
240	case 0x03: return kCpumMicroarch_AMD_Am386;
241	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
242	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
243	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
244	case 0x06:
245	switch (bModel)
246	{
247	case 0: return kCpumMicroarch_AMD_K7_Palomino;
248	case 1: return kCpumMicroarch_AMD_K7_Palomino;
249	case 2: return kCpumMicroarch_AMD_K7_Palomino;
250	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
251	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
252	case 6: return kCpumMicroarch_AMD_K7_Palomino;
253	case 7: return kCpumMicroarch_AMD_K7_Morgan;
254	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
255	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
256	}
257	return kCpumMicroarch_AMD_K7_Unknown;
258	case 0x0f:
259	/*
260	* This family is a friggin mess. Trying my best to make some
261	* sense out of it. Too much happened in the 0x0f family to
262	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
263	*
264	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
265	* cpu-world.com, and other places:
266	* - 130nm:
267	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
268	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
269	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
270	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
271	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
272	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
273	* - 90nm:
274	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
275	* - Oakville: 10FC0/DH-D0.
276	* - Georgetown: 10FC0/DH-D0.
277	* - Sonora: 10FC0/DH-D0.
278	* - Venus: 20F71/SH-E4
279	* - Troy: 20F51/SH-E4
280	* - Athens: 20F51/SH-E4
281	* - San Diego: 20F71/SH-E4.
282	* - Lancaster: 20F42/SH-E5
283	* - Newark: 20F42/SH-E5.
284	* - Albany: 20FC2/DH-E6.
285	* - Roma: 20FC2/DH-E6.
286	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
287	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
288	* - 90nm introducing Dual core:
289	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
290	* - Italy: 20F10/JH-E1, 20F12/JH-E6
291	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
292	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
293	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
294	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
295	* - Santa Ana: 40F32/JH-F2, /-F3
296	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
297	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
298	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
299	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
300	* - Keene: 40FC2/DH-F2.
301	* - Richmond: 40FC2/DH-F2
302	* - Taylor: 40F82/BH-F2
303	* - Trinidad: 40F82/BH-F2
304	*
305	* - 65nm:
306	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
307	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
308	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
309	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
310	* - Sherman: /-G1, 70FC2/DH-G2.
311	* - Huron: 70FF2/DH-G2.
312	*/
313	if (bModel < 0x10)
314	return kCpumMicroarch_AMD_K8_130nm;
315	if (bModel >= 0x60 && bModel < 0x80)
316	return kCpumMicroarch_AMD_K8_65nm;
317	if (bModel >= 0x40)
318	return kCpumMicroarch_AMD_K8_90nm_AMDV;
319	switch (bModel)
320	{
321	case 0x21:
322	case 0x23:
323	case 0x2b:
324	case 0x2f:
325	case 0x37:
326	case 0x3f:
327	return kCpumMicroarch_AMD_K8_90nm_DualCore;
328	}
329	return kCpumMicroarch_AMD_K8_90nm;
330	case 0x10:
331	return kCpumMicroarch_AMD_K10;
332	case 0x11:
333	return kCpumMicroarch_AMD_K10_Lion;
334	case 0x12:
335	return kCpumMicroarch_AMD_K10_Llano;
336	case 0x14:
337	return kCpumMicroarch_AMD_Bobcat;
338	case 0x15:
339	switch (bModel)
340	{
341	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
342	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
343	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
344	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
345	case 0x11: /* ?? */
346	case 0x12: /* ?? */
347	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
348	}
349	return kCpumMicroarch_AMD_15h_Unknown;
350	case 0x16:
351	return kCpumMicroarch_AMD_Jaguar;
352	case 0x17:
353	return kCpumMicroarch_AMD_Zen_Ryzen;
354	}
355	return kCpumMicroarch_AMD_Unknown;
356	}
357
358	if (enmVendor == CPUMCPUVENDOR_INTEL)
359	{
360	switch (bFamily)
361	{
362	case 3:
363	return kCpumMicroarch_Intel_80386;
364	case 4:
365	return kCpumMicroarch_Intel_80486;
366	case 5:
367	return kCpumMicroarch_Intel_P5;
368	case 6:
369	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
370	{
371	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
372	if ( enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake
373	&& bStepping >= 0xa)
374	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
375	return enmMicroArch;
376	}
377	return kCpumMicroarch_Intel_Atom_Unknown;
378	case 15:
379	switch (bModel)
380	{
381	case 0: return kCpumMicroarch_Intel_NB_Willamette;
382	case 1: return kCpumMicroarch_Intel_NB_Willamette;
383	case 2: return kCpumMicroarch_Intel_NB_Northwood;
384	case 3: return kCpumMicroarch_Intel_NB_Prescott;
385	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
386	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
387	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
388	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
389	default: return kCpumMicroarch_Intel_NB_Unknown;
390	}
391	break;
392	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
393	case 0:
394	return kCpumMicroarch_Intel_8086;
395	case 1:
396	return kCpumMicroarch_Intel_80186;
397	case 2:
398	return kCpumMicroarch_Intel_80286;
399	}
400	return kCpumMicroarch_Intel_Unknown;
401	}
402
403	if (enmVendor == CPUMCPUVENDOR_VIA)
404	{
405	switch (bFamily)
406	{
407	case 5:
408	switch (bModel)
409	{
410	case 1: return kCpumMicroarch_Centaur_C6;
411	case 4: return kCpumMicroarch_Centaur_C6;
412	case 8: return kCpumMicroarch_Centaur_C2;
413	case 9: return kCpumMicroarch_Centaur_C3;
414	}
415	break;
416
417	case 6:
418	switch (bModel)
419	{
420	case 5: return kCpumMicroarch_VIA_C3_M2;
421	case 6: return kCpumMicroarch_VIA_C3_C5A;
422	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
423	case 8: return kCpumMicroarch_VIA_C3_C5N;
424	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
425	case 10: return kCpumMicroarch_VIA_C7_C5J;
426	case 15: return kCpumMicroarch_VIA_Isaiah;
427	}
428	break;
429	}
430	return kCpumMicroarch_VIA_Unknown;
431	}
432
433	if (enmVendor == CPUMCPUVENDOR_CYRIX)
434	{
435	switch (bFamily)
436	{
437	case 4:
438	switch (bModel)
439	{
440	case 9: return kCpumMicroarch_Cyrix_5x86;
441	}
442	break;
443
444	case 5:
445	switch (bModel)
446	{
447	case 2: return kCpumMicroarch_Cyrix_M1;
448	case 4: return kCpumMicroarch_Cyrix_MediaGX;
449	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
450	}
451	break;
452
453	case 6:
454	switch (bModel)
455	{
456	case 0: return kCpumMicroarch_Cyrix_M2;
457	}
458	break;
459
460	}
461	return kCpumMicroarch_Cyrix_Unknown;
462	}
463
464	return kCpumMicroarch_Unknown;
465	}
466
467
468	/**
469	* Translates a microarchitecture enum value to the corresponding string
470	* constant.
471	*
472	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
473	* NULL if the value is invalid.
474	*
475	* @param enmMicroarch The enum value to convert.
476	*/
477	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
478	{
479	switch (enmMicroarch)
480	{
481	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
482	CASE_RET_STR(kCpumMicroarch_Intel_8086);
483	CASE_RET_STR(kCpumMicroarch_Intel_80186);
484	CASE_RET_STR(kCpumMicroarch_Intel_80286);
485	CASE_RET_STR(kCpumMicroarch_Intel_80386);
486	CASE_RET_STR(kCpumMicroarch_Intel_80486);
487	CASE_RET_STR(kCpumMicroarch_Intel_P5);
488
489	CASE_RET_STR(kCpumMicroarch_Intel_P6);
490	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
491	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
492
493	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
494	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
495	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
496
497	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
498	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
499
500	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
501	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
502	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
503	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
504	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
505	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
506	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
507	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
508	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
509	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
510	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
511	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
512
513	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
514	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
515	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
516	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
517	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
518	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
519	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
520	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
521
522	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
523	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
524	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
525	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
526	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
527
528	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
529	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
530	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
531	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
532	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
533	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
534	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
535
536	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
537
538	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
539	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
540	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
541	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
542	CASE_RET_STR(kCpumMicroarch_AMD_K5);
543	CASE_RET_STR(kCpumMicroarch_AMD_K6);
544
545	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
546	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
547	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
548	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
549	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
550	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
551	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
552
553	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
554	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
555	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
556	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
557	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
558
559	CASE_RET_STR(kCpumMicroarch_AMD_K10);
560	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
561	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
562	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
563	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
564
565	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
566	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
567	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
568	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
569	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
570
571	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
572
573	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
574
575	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
576
577	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
578	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
579	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
580	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
581	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
582	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
583	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
584	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
585	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
586	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
587	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
588	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
589	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
590
591	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
592	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
593	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
594	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
595	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
596	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
597
598	CASE_RET_STR(kCpumMicroarch_NEC_V20);
599	CASE_RET_STR(kCpumMicroarch_NEC_V30);
600
601	CASE_RET_STR(kCpumMicroarch_Unknown);
602
603	#undef CASE_RET_STR
604	case kCpumMicroarch_Invalid:
605	case kCpumMicroarch_Intel_End:
606	case kCpumMicroarch_Intel_Core2_End:
607	case kCpumMicroarch_Intel_Core7_End:
608	case kCpumMicroarch_Intel_Atom_End:
609	case kCpumMicroarch_Intel_P6_Core_Atom_End:
610	case kCpumMicroarch_Intel_Phi_End:
611	case kCpumMicroarch_Intel_NB_End:
612	case kCpumMicroarch_AMD_K7_End:
613	case kCpumMicroarch_AMD_K8_End:
614	case kCpumMicroarch_AMD_15h_End:
615	case kCpumMicroarch_AMD_16h_End:
616	case kCpumMicroarch_AMD_Zen_End:
617	case kCpumMicroarch_AMD_End:
618	case kCpumMicroarch_VIA_End:
619	case kCpumMicroarch_Cyrix_End:
620	case kCpumMicroarch_NEC_End:
621	case kCpumMicroarch_32BitHack:
622	break;
623	/* no default! */
624	}
625
626	return NULL;
627	}
628
629
630	/**
631	* Determins the host CPU MXCSR mask.
632	*
633	* @returns MXCSR mask.
634	*/
635	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
636	{
637	if ( ASMHasCpuId()
638	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
639	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
640	{
641	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
642	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
643	RT_ZERO(*pState);
644	ASMFxSave(pState);
645	if (pState->MXCSR_MASK == 0)
646	return 0xffbf;
647	return pState->MXCSR_MASK;
648	}
649	return 0;
650	}
651
652
653	/**
654	* Gets a matching leaf in the CPUID leaf array.
655	*
656	* @returns Pointer to the matching leaf, or NULL if not found.
657	* @param paLeaves The CPUID leaves to search. This is sorted.
658	* @param cLeaves The number of leaves in the array.
659	* @param uLeaf The leaf to locate.
660	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
661	*/
662	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
663	{
664	/* Lazy bird does linear lookup here since this is only used for the
665	occational CPUID overrides. */
666	for (uint32_t i = 0; i < cLeaves; i++)
667	if ( paLeaves[i].uLeaf == uLeaf
668	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
669	return &paLeaves[i];
670	return NULL;
671	}
672
673
674	#ifndef IN_VBOX_CPU_REPORT
675	/**
676	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
677	*
678	* @returns true if found, false it not.
679	* @param paLeaves The CPUID leaves to search. This is sorted.
680	* @param cLeaves The number of leaves in the array.
681	* @param uLeaf The leaf to locate.
682	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
683	* @param pLegacy The legacy output leaf.
684	*/
685	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
686	PCPUMCPUID pLegacy)
687	{
688	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
689	if (pLeaf)
690	{
691	pLegacy->uEax = pLeaf->uEax;
692	pLegacy->uEbx = pLeaf->uEbx;
693	pLegacy->uEcx = pLeaf->uEcx;
694	pLegacy->uEdx = pLeaf->uEdx;
695	return true;
696	}
697	return false;
698	}
699	#endif /* IN_VBOX_CPU_REPORT */
700
701
702	/**
703	* Ensures that the CPUID leaf array can hold one more leaf.
704	*
705	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
706	* failure.
707	* @param pVM The cross context VM structure. If NULL, use
708	* the process heap, otherwise the VM's hyper heap.
709	* @param ppaLeaves Pointer to the variable holding the array pointer
710	* (input/output).
711	* @param cLeaves The current array size.
712	*
713	* @remarks This function will automatically update the R0 and RC pointers when
714	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
715	* be the corresponding VM's CPUID arrays (which is asserted).
716	*/
717	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
718	{
719	/*
720	* If pVM is not specified, we're on the regular heap and can waste a
721	* little space to speed things up.
722	*/
723	uint32_t cAllocated;
724	if (!pVM)
725	{
726	cAllocated = RT_ALIGN(cLeaves, 16);
727	if (cLeaves + 1 > cAllocated)
728	{
729	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
730	if (pvNew)
731	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
732	else
733	{
734	RTMemFree(*ppaLeaves);
735	*ppaLeaves = NULL;
736	}
737	}
738	}
739	/*
740	* Otherwise, we're on the hyper heap and are probably just inserting
741	* one or two leaves and should conserve space.
742	*/
743	else
744	{
745	#ifdef IN_VBOX_CPU_REPORT
746	AssertReleaseFailed();
747	#else
748	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
749	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
750
751	size_t cb = cLeaves * sizeof(**ppaLeaves);
752	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
753	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
754	if (RT_SUCCESS(rc))
755	{
756	/* Update the R0 and RC pointers. */
757	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
758	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
759	}
760	else
761	{
762	*ppaLeaves = NULL;
763	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
764	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
765	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
766	}
767	#endif
768	}
769	return *ppaLeaves;
770	}
771
772
773	/**
774	* Append a CPUID leaf or sub-leaf.
775	*
776	* ASSUMES linear insertion order, so we'll won't need to do any searching or
777	* replace anything. Use cpumR3CpuIdInsert() for those cases.
778	*
779	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
780	* the caller need do no more work.
781	* @param ppaLeaves Pointer to the pointer to the array of sorted
782	* CPUID leaves and sub-leaves.
783	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
784	* @param uLeaf The leaf we're adding.
785	* @param uSubLeaf The sub-leaf number.
786	* @param fSubLeafMask The sub-leaf mask.
787	* @param uEax The EAX value.
788	* @param uEbx The EBX value.
789	* @param uEcx The ECX value.
790	* @param uEdx The EDX value.
791	* @param fFlags The flags.
792	*/
793	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
794	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
795	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
796	{
797	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
798	return VERR_NO_MEMORY;
799
800	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
801	Assert( *pcLeaves == 0
802	\|\| pNew[-1].uLeaf < uLeaf
803	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
804
805	pNew->uLeaf = uLeaf;
806	pNew->uSubLeaf = uSubLeaf;
807	pNew->fSubLeafMask = fSubLeafMask;
808	pNew->uEax = uEax;
809	pNew->uEbx = uEbx;
810	pNew->uEcx = uEcx;
811	pNew->uEdx = uEdx;
812	pNew->fFlags = fFlags;
813
814	*pcLeaves += 1;
815	return VINF_SUCCESS;
816	}
817
818
819	/**
820	* Checks that we've updated the CPUID leaves array correctly.
821	*
822	* This is a no-op in non-strict builds.
823	*
824	* @param paLeaves The leaves array.
825	* @param cLeaves The number of leaves.
826	*/
827	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
828	{
829	#ifdef VBOX_STRICT
830	for (uint32_t i = 1; i < cLeaves; i++)
831	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
832	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
833	else
834	{
835	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
836	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
837	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
838	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
839	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
840	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
841	}
842	#else
843	NOREF(paLeaves);
844	NOREF(cLeaves);
845	#endif
846	}
847
848
849	/**
850	* Inserts a CPU ID leaf, replacing any existing ones.
851	*
852	* When inserting a simple leaf where we already got a series of sub-leaves with
853	* the same leaf number (eax), the simple leaf will replace the whole series.
854	*
855	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
856	* host-context heap and has only been allocated/reallocated by the
857	* cpumR3CpuIdEnsureSpace function.
858	*
859	* @returns VBox status code.
860	* @param pVM The cross context VM structure. If NULL, use
861	* the process heap, otherwise the VM's hyper heap.
862	* @param ppaLeaves Pointer to the pointer to the array of sorted
863	* CPUID leaves and sub-leaves. Must be NULL if using
864	* the hyper heap.
865	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
866	* be NULL if using the hyper heap.
867	* @param pNewLeaf Pointer to the data of the new leaf we're about to
868	* insert.
869	*/
870	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
871	{
872	/*
873	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
874	*/
875	if (pVM)
876	{
877	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
878	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
879
880	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
881	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
882	}
883
884	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
885	uint32_t cLeaves = *pcLeaves;
886
887	/*
888	* Validate the new leaf a little.
889	*/
890	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
891	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
892	VERR_INVALID_FLAGS);
893	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
894	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
895	VERR_INVALID_PARAMETER);
896	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
897	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
898	VERR_INVALID_PARAMETER);
899	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
900	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
901	VERR_INVALID_PARAMETER);
902
903	/*
904	* Find insertion point. The lazy bird uses the same excuse as in
905	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
906	*/
907	uint32_t i;
908	if ( cLeaves > 0
909	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
910	{
911	/* Add at end. */
912	i = cLeaves;
913	}
914	else if ( cLeaves > 0
915	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
916	{
917	/* Either replacing the last leaf or dealing with sub-leaves. Spool
918	back to the first sub-leaf to pretend we did the linear search. */
919	i = cLeaves - 1;
920	while ( i > 0
921	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
922	i--;
923	}
924	else
925	{
926	/* Linear search from the start. */
927	i = 0;
928	while ( i < cLeaves
929	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
930	i++;
931	}
932	if ( i < cLeaves
933	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
934	{
935	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
936	{
937	/*
938	* The sub-leaf mask differs, replace all existing leaves with the
939	* same leaf number.
940	*/
941	uint32_t c = 1;
942	while ( i + c < cLeaves
943	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
944	c++;
945	if (c > 1 && i + c < cLeaves)
946	{
947	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
948	*pcLeaves = cLeaves -= c - 1;
949	}
950
951	paLeaves[i] = *pNewLeaf;
952	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
953	return VINF_SUCCESS;
954	}
955
956	/* Find sub-leaf insertion point. */
957	while ( i < cLeaves
958	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
959	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
960	i++;
961
962	/*
963	* If we've got an exactly matching leaf, replace it.
964	*/
965	if ( i < cLeaves
966	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
967	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
968	{
969	paLeaves[i] = *pNewLeaf;
970	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
971	return VINF_SUCCESS;
972	}
973	}
974
975	/*
976	* Adding a new leaf at 'i'.
977	*/
978	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
979	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
980	if (!paLeaves)
981	return VERR_NO_MEMORY;
982
983	if (i < cLeaves)
984	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
985	*pcLeaves += 1;
986	paLeaves[i] = *pNewLeaf;
987
988	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
989	return VINF_SUCCESS;
990	}
991
992
993	#ifndef IN_VBOX_CPU_REPORT
994	/**
995	* Removes a range of CPUID leaves.
996	*
997	* This will not reallocate the array.
998	*
999	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1000	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1001	* @param uFirst The first leaf.
1002	* @param uLast The last leaf.
1003	*/
1004	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1005	{
1006	uint32_t cLeaves = *pcLeaves;
1007
1008	Assert(uFirst <= uLast);
1009
1010	/*
1011	* Find the first one.
1012	*/
1013	uint32_t iFirst = 0;
1014	while ( iFirst < cLeaves
1015	&& paLeaves[iFirst].uLeaf < uFirst)
1016	iFirst++;
1017
1018	/*
1019	* Find the end (last + 1).
1020	*/
1021	uint32_t iEnd = iFirst;
1022	while ( iEnd < cLeaves
1023	&& paLeaves[iEnd].uLeaf <= uLast)
1024	iEnd++;
1025
1026	/*
1027	* Adjust the array if anything needs removing.
1028	*/
1029	if (iFirst < iEnd)
1030	{
1031	if (iEnd < cLeaves)
1032	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1033	*pcLeaves = cLeaves -= (iEnd - iFirst);
1034	}
1035
1036	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1037	}
1038	#endif /* IN_VBOX_CPU_REPORT */
1039
1040
1041	/**
1042	* Checks if ECX make a difference when reading a given CPUID leaf.
1043	*
1044	* @returns @c true if it does, @c false if it doesn't.
1045	* @param uLeaf The leaf we're reading.
1046	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1047	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1048	* final sub-leaf (for leaf 0xb only).
1049	*/
1050	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1051	{
1052	*pfFinalEcxUnchanged = false;
1053
1054	uint32_t auCur[4];
1055	uint32_t auPrev[4];
1056	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1057
1058	/* Look for sub-leaves. */
1059	uint32_t uSubLeaf = 1;
1060	for (;;)
1061	{
1062	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1063	if (memcmp(auCur, auPrev, sizeof(auCur)))
1064	break;
1065
1066	/* Advance / give up. */
1067	uSubLeaf++;
1068	if (uSubLeaf >= 64)
1069	{
1070	*pcSubLeaves = 1;
1071	return false;
1072	}
1073	}
1074
1075	/* Count sub-leaves. */
1076	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1077	uint32_t cRepeats = 0;
1078	uSubLeaf = 0;
1079	for (;;)
1080	{
1081	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1082
1083	/* Figuring out when to stop isn't entirely straight forward as we need
1084	to cover undocumented behavior up to a point and implementation shortcuts. */
1085
1086	/* 1. Look for more than 4 repeating value sets. */
1087	if ( auCur[0] == auPrev[0]
1088	&& auCur[1] == auPrev[1]
1089	&& ( auCur[2] == auPrev[2]
1090	\|\| ( auCur[2] == uSubLeaf
1091	&& auPrev[2] == uSubLeaf - 1) )
1092	&& auCur[3] == auPrev[3])
1093	{
1094	if ( uLeaf != 0xd
1095	\|\| uSubLeaf >= 64
1096	\|\| ( auCur[0] == 0
1097	&& auCur[1] == 0
1098	&& auCur[2] == 0
1099	&& auCur[3] == 0
1100	&& auPrev[2] == 0) )
1101	cRepeats++;
1102	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1103	break;
1104	}
1105	else
1106	cRepeats = 0;
1107
1108	/* 2. Look for zero values. */
1109	if ( auCur[0] == 0
1110	&& auCur[1] == 0
1111	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1112	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1113	&& uSubLeaf >= cMinLeaves)
1114	{
1115	cRepeats = 0;
1116	break;
1117	}
1118
1119	/* 3. Leaf 0xb level type 0 check. */
1120	if ( uLeaf == 0xb
1121	&& (auCur[2] & 0xff00) == 0
1122	&& (auPrev[2] & 0xff00) == 0)
1123	{
1124	cRepeats = 0;
1125	break;
1126	}
1127
1128	/* 99. Give up. */
1129	if (uSubLeaf >= 128)
1130	{
1131	#ifndef IN_VBOX_CPU_REPORT
1132	/* Ok, limit it according to the documentation if possible just to
1133	avoid annoying users with these detection issues. */
1134	uint32_t cDocLimit = UINT32_MAX;
1135	if (uLeaf == 0x4)
1136	cDocLimit = 4;
1137	else if (uLeaf == 0x7)
1138	cDocLimit = 1;
1139	else if (uLeaf == 0xd)
1140	cDocLimit = 63;
1141	else if (uLeaf == 0xf)
1142	cDocLimit = 2;
1143	if (cDocLimit != UINT32_MAX)
1144	{
1145	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1146	*pcSubLeaves = cDocLimit + 3;
1147	return true;
1148	}
1149	#endif
1150	*pcSubLeaves = UINT32_MAX;
1151	return true;
1152	}
1153
1154	/* Advance. */
1155	uSubLeaf++;
1156	memcpy(auPrev, auCur, sizeof(auCur));
1157	}
1158
1159	/* Standard exit. */
1160	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1161	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1162	if (*pcSubLeaves == 0)
1163	*pcSubLeaves = 1;
1164	return true;
1165	}
1166
1167
1168	/**
1169	* Gets a CPU ID leaf.
1170	*
1171	* @returns VBox status code.
1172	* @param pVM The cross context VM structure.
1173	* @param pLeaf Where to store the found leaf.
1174	* @param uLeaf The leaf to locate.
1175	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1176	*/
1177	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1178	{
1179	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1180	uLeaf, uSubLeaf);
1181	if (pcLeaf)
1182	{
1183	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1184	return VINF_SUCCESS;
1185	}
1186
1187	return VERR_NOT_FOUND;
1188	}
1189
1190
1191	/**
1192	* Inserts a CPU ID leaf, replacing any existing ones.
1193	*
1194	* @returns VBox status code.
1195	* @param pVM The cross context VM structure.
1196	* @param pNewLeaf Pointer to the leaf being inserted.
1197	*/
1198	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1199	{
1200	/*
1201	* Validate parameters.
1202	*/
1203	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1204	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1205
1206	/*
1207	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1208	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1209	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1210	*/
1211	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1212	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1213	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1214	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1215	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1216	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1217	{
1218	return VERR_NOT_SUPPORTED;
1219	}
1220
1221	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1222	}
1223
1224	/**
1225	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1226	*
1227	* @returns VBox status code.
1228	* @param ppaLeaves Where to return the array pointer on success.
1229	* Use RTMemFree to release.
1230	* @param pcLeaves Where to return the size of the array on
1231	* success.
1232	*/
1233	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1234	{
1235	*ppaLeaves = NULL;
1236	*pcLeaves = 0;
1237
1238	/*
1239	* Try out various candidates. This must be sorted!
1240	*/
1241	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1242	{
1243	{ UINT32_C(0x00000000), false },
1244	{ UINT32_C(0x10000000), false },
1245	{ UINT32_C(0x20000000), false },
1246	{ UINT32_C(0x30000000), false },
1247	{ UINT32_C(0x40000000), false },
1248	{ UINT32_C(0x50000000), false },
1249	{ UINT32_C(0x60000000), false },
1250	{ UINT32_C(0x70000000), false },
1251	{ UINT32_C(0x80000000), false },
1252	{ UINT32_C(0x80860000), false },
1253	{ UINT32_C(0x8ffffffe), true },
1254	{ UINT32_C(0x8fffffff), true },
1255	{ UINT32_C(0x90000000), false },
1256	{ UINT32_C(0xa0000000), false },
1257	{ UINT32_C(0xb0000000), false },
1258	{ UINT32_C(0xc0000000), false },
1259	{ UINT32_C(0xd0000000), false },
1260	{ UINT32_C(0xe0000000), false },
1261	{ UINT32_C(0xf0000000), false },
1262	};
1263
1264	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1265	{
1266	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1267	uint32_t uEax, uEbx, uEcx, uEdx;
1268	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1269
1270	/*
1271	* Does EAX look like a typical leaf count value?
1272	*/
1273	if ( uEax > uLeaf
1274	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1275	{
1276	/* Yes, dump them. */
1277	uint32_t cLeaves = uEax - uLeaf + 1;
1278	while (cLeaves-- > 0)
1279	{
1280	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1281
1282	uint32_t fFlags = 0;
1283
1284	/* There are currently three known leaves containing an APIC ID
1285	that needs EMT specific attention */
1286	if (uLeaf == 1)
1287	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1288	else if (uLeaf == 0xb && uEcx != 0)
1289	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1290	else if ( uLeaf == UINT32_C(0x8000001e)
1291	&& ( uEax
1292	\|\| uEbx
1293	\|\| uEdx
1294	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1295	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1296
1297	/* The APIC bit is per-VCpu and needs flagging. */
1298	if (uLeaf == 1)
1299	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1300	else if ( uLeaf == UINT32_C(0x80000001)
1301	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1302	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1303	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1304
1305	/* Check three times here to reduce the chance of CPU migration
1306	resulting in false positives with things like the APIC ID. */
1307	uint32_t cSubLeaves;
1308	bool fFinalEcxUnchanged;
1309	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1310	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1311	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1312	{
1313	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1314	{
1315	/* This shouldn't happen. But in case it does, file all
1316	relevant details in the release log. */
1317	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1318	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1319	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1320	{
1321	uint32_t auTmp[4];
1322	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1323	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1324	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1325	}
1326	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1327	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1328	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1329	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1330	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1331	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1332	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1333	}
1334
1335	if (fFinalEcxUnchanged)
1336	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1337
1338	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1339	{
1340	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1341	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1342	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1343	if (RT_FAILURE(rc))
1344	return rc;
1345	}
1346	}
1347	else
1348	{
1349	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1350	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1351	if (RT_FAILURE(rc))
1352	return rc;
1353	}
1354
1355	/* next */
1356	uLeaf++;
1357	}
1358	}
1359	/*
1360	* Special CPUIDs needs special handling as they don't follow the
1361	* leaf count principle used above.
1362	*/
1363	else if (s_aCandidates[iOuter].fSpecial)
1364	{
1365	bool fKeep = false;
1366	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1367	fKeep = true;
1368	else if ( uLeaf == 0x8fffffff
1369	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1370	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1371	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1372	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1373	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1374	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1375	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1376	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1377	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1378	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1379	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1380	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1381	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1382	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1383	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1384	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1385	fKeep = true;
1386	if (fKeep)
1387	{
1388	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1389	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1390	if (RT_FAILURE(rc))
1391	return rc;
1392	}
1393	}
1394	}
1395
1396	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1397	return VINF_SUCCESS;
1398	}
1399
1400
1401	/**
1402	* Determines the method the CPU uses to handle unknown CPUID leaves.
1403	*
1404	* @returns VBox status code.
1405	* @param penmUnknownMethod Where to return the method.
1406	* @param pDefUnknown Where to return default unknown values. This
1407	* will be set, even if the resulting method
1408	* doesn't actually needs it.
1409	*/
1410	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1411	{
1412	uint32_t uLastStd = ASMCpuId_EAX(0);
1413	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1414	if (!ASMIsValidExtRange(uLastExt))
1415	uLastExt = 0x80000000;
1416
1417	uint32_t auChecks[] =
1418	{
1419	uLastStd + 1,
1420	uLastStd + 5,
1421	uLastStd + 8,
1422	uLastStd + 32,
1423	uLastStd + 251,
1424	uLastExt + 1,
1425	uLastExt + 8,
1426	uLastExt + 15,
1427	uLastExt + 63,
1428	uLastExt + 255,
1429	0x7fbbffcc,
1430	0x833f7872,
1431	0xefff2353,
1432	0x35779456,
1433	0x1ef6d33e,
1434	};
1435
1436	static const uint32_t s_auValues[] =
1437	{
1438	0xa95d2156,
1439	0x00000001,
1440	0x00000002,
1441	0x00000008,
1442	0x00000000,
1443	0x55773399,
1444	0x93401769,
1445	0x12039587,
1446	};
1447
1448	/*
1449	* Simple method, all zeros.
1450	*/
1451	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1452	pDefUnknown->uEax = 0;
1453	pDefUnknown->uEbx = 0;
1454	pDefUnknown->uEcx = 0;
1455	pDefUnknown->uEdx = 0;
1456
1457	/*
1458	* Intel has been observed returning the last standard leaf.
1459	*/
1460	uint32_t auLast[4];
1461	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1462
1463	uint32_t cChecks = RT_ELEMENTS(auChecks);
1464	while (cChecks > 0)
1465	{
1466	uint32_t auCur[4];
1467	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1468	if (memcmp(auCur, auLast, sizeof(auCur)))
1469	break;
1470	cChecks--;
1471	}
1472	if (cChecks == 0)
1473	{
1474	/* Now, what happens when the input changes? Esp. ECX. */
1475	uint32_t cTotal = 0;
1476	uint32_t cSame = 0;
1477	uint32_t cLastWithEcx = 0;
1478	uint32_t cNeither = 0;
1479	uint32_t cValues = RT_ELEMENTS(s_auValues);
1480	while (cValues > 0)
1481	{
1482	uint32_t uValue = s_auValues[cValues - 1];
1483	uint32_t auLastWithEcx[4];
1484	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1485	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1486
1487	cChecks = RT_ELEMENTS(auChecks);
1488	while (cChecks > 0)
1489	{
1490	uint32_t auCur[4];
1491	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1492	if (!memcmp(auCur, auLast, sizeof(auCur)))
1493	{
1494	cSame++;
1495	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1496	cLastWithEcx++;
1497	}
1498	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1499	cLastWithEcx++;
1500	else
1501	cNeither++;
1502	cTotal++;
1503	cChecks--;
1504	}
1505	cValues--;
1506	}
1507
1508	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1509	if (cSame == cTotal)
1510	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1511	else if (cLastWithEcx == cTotal)
1512	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1513	else
1514	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1515	pDefUnknown->uEax = auLast[0];
1516	pDefUnknown->uEbx = auLast[1];
1517	pDefUnknown->uEcx = auLast[2];
1518	pDefUnknown->uEdx = auLast[3];
1519	return VINF_SUCCESS;
1520	}
1521
1522	/*
1523	* Unchanged register values?
1524	*/
1525	cChecks = RT_ELEMENTS(auChecks);
1526	while (cChecks > 0)
1527	{
1528	uint32_t const uLeaf = auChecks[cChecks - 1];
1529	uint32_t cValues = RT_ELEMENTS(s_auValues);
1530	while (cValues > 0)
1531	{
1532	uint32_t uValue = s_auValues[cValues - 1];
1533	uint32_t auCur[4];
1534	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1535	if ( auCur[0] != uLeaf
1536	\|\| auCur[1] != uValue
1537	\|\| auCur[2] != uValue
1538	\|\| auCur[3] != uValue)
1539	break;
1540	cValues--;
1541	}
1542	if (cValues != 0)
1543	break;
1544	cChecks--;
1545	}
1546	if (cChecks == 0)
1547	{
1548	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1549	return VINF_SUCCESS;
1550	}
1551
1552	/*
1553	* Just go with the simple method.
1554	*/
1555	return VINF_SUCCESS;
1556	}
1557
1558
1559	/**
1560	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1561	*
1562	* @returns Read only name string.
1563	* @param enmUnknownMethod The method to translate.
1564	*/
1565	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1566	{
1567	switch (enmUnknownMethod)
1568	{
1569	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1570	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1571	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1572	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1573
1574	case CPUMUNKNOWNCPUID_INVALID:
1575	case CPUMUNKNOWNCPUID_END:
1576	case CPUMUNKNOWNCPUID_32BIT_HACK:
1577	break;
1578	}
1579	return "Invalid-unknown-CPUID-method";
1580	}
1581
1582
1583	/**
1584	* Detect the CPU vendor give n the
1585	*
1586	* @returns The vendor.
1587	* @param uEAX EAX from CPUID(0).
1588	* @param uEBX EBX from CPUID(0).
1589	* @param uECX ECX from CPUID(0).
1590	* @param uEDX EDX from CPUID(0).
1591	*/
1592	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1593	{
1594	if (ASMIsValidStdRange(uEAX))
1595	{
1596	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1597	return CPUMCPUVENDOR_AMD;
1598
1599	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1600	return CPUMCPUVENDOR_INTEL;
1601
1602	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1603	return CPUMCPUVENDOR_VIA;
1604
1605	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1606	&& uECX == UINT32_C(0x64616574)
1607	&& uEDX == UINT32_C(0x736E4978))
1608	return CPUMCPUVENDOR_CYRIX;
1609
1610	/* "Geode by NSC", example: family 5, model 9. */
1611
1612	/** @todo detect the other buggers... */
1613	}
1614
1615	return CPUMCPUVENDOR_UNKNOWN;
1616	}
1617
1618
1619	/**
1620	* Translates a CPU vendor enum value into the corresponding string constant.
1621	*
1622	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1623	* value name. This can be useful when generating code.
1624	*
1625	* @returns Read only name string.
1626	* @param enmVendor The CPU vendor value.
1627	*/
1628	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1629	{
1630	switch (enmVendor)
1631	{
1632	case CPUMCPUVENDOR_INTEL: return "INTEL";
1633	case CPUMCPUVENDOR_AMD: return "AMD";
1634	case CPUMCPUVENDOR_VIA: return "VIA";
1635	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1636	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1637
1638	case CPUMCPUVENDOR_INVALID:
1639	case CPUMCPUVENDOR_32BIT_HACK:
1640	break;
1641	}
1642	return "Invalid-cpu-vendor";
1643	}
1644
1645
1646	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1647	{
1648	/* Could do binary search, doing linear now because I'm lazy. */
1649	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1650	while (cLeaves-- > 0)
1651	{
1652	if (pLeaf->uLeaf == uLeaf)
1653	return pLeaf;
1654	pLeaf++;
1655	}
1656	return NULL;
1657	}
1658
1659
1660	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1661	{
1662	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1663	if ( !pLeaf
1664	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1665	return pLeaf;
1666
1667	/* Linear sub-leaf search. Lazy as usual. */
1668	cLeaves -= pLeaf - paLeaves;
1669	while ( cLeaves-- > 0
1670	&& pLeaf->uLeaf == uLeaf)
1671	{
1672	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1673	return pLeaf;
1674	pLeaf++;
1675	}
1676
1677	return NULL;
1678	}
1679
1680
1681	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1682	{
1683	RT_ZERO(*pFeatures);
1684	if (cLeaves >= 2)
1685	{
1686	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1687	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1688	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1689	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1690	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1691	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1692
1693	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1694	pStd0Leaf->uEbx,
1695	pStd0Leaf->uEcx,
1696	pStd0Leaf->uEdx);
1697	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1698	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1699	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1700	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1701	pFeatures->uFamily,
1702	pFeatures->uModel,
1703	pFeatures->uStepping);
1704
1705	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1706	if (pExtLeaf8)
1707	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1708	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1709	pFeatures->cMaxPhysAddrWidth = 36;
1710	else
1711	pFeatures->cMaxPhysAddrWidth = 32;
1712
1713	/* Standard features. */
1714	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1715	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1716	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1717	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1718	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1719	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1720	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1721	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1722	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1723	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1724	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1725	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1726	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1727	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1728	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1729	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1730	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1731	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1732	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1733	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1734	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1735	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1736	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1737	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1738	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1739	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1740	/* VMX sub-features will be initialized in cpumR3InitVmxCpuFeatures(). */
1741
1742	/* Structured extended features. */
1743	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1744	if (pSxfLeaf0)
1745	{
1746	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1747	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1748	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1749	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1750	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1751
1752	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1753	pFeatures->fIbrs = pFeatures->fIbpb;
1754	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1755	#if 0 // Disabled until IA32_ARCH_CAPABILITIES support can be tested
1756	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1757	#endif
1758	}
1759
1760	/* MWAIT/MONITOR leaf. */
1761	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1762	if (pMWaitLeaf)
1763	{
1764	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1765	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1766	}
1767
1768	/* Extended features. */
1769	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1770	if (pExtLeaf)
1771	{
1772	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1773	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1774	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1775	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1776	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1777	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1778	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1779	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1780	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1781	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1782	}
1783
1784	if ( pExtLeaf
1785	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1786	{
1787	/* AMD features. */
1788	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1789	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1790	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1791	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1792	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1793	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1794	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1795	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1796	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1797	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1798	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1799	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1800	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1801	if (pFeatures->fSvm)
1802	{
1803	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1804	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1805	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1806	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1807	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1808	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1809	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1810	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1811	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1812	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1813	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1814	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1815	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1816	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1817	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1818	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1819	}
1820	}
1821
1822	/*
1823	* Quirks.
1824	*/
1825	pFeatures->fLeakyFxSR = pExtLeaf
1826	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1827	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1828	&& pFeatures->uFamily >= 6 /* K7 and up */;
1829
1830	/*
1831	* Max extended (/FPU) state.
1832	*/
1833	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1834	if (pFeatures->fXSaveRstor)
1835	{
1836	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1837	if (pXStateLeaf0)
1838	{
1839	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1840	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1841	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1842	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1843	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1844	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1845	{
1846	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1847
1848	/* (paranoia:) */
1849	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1850	if ( pXStateLeaf1
1851	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1852	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1853	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1854	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1855	}
1856	else
1857	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1858	pFeatures->fXSaveRstor = 0);
1859	}
1860	else
1861	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1862	pFeatures->fXSaveRstor = 0);
1863	}
1864	}
1865	else
1866	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1867	return VINF_SUCCESS;
1868	}
1869
1870
1871	/*
1872	*
1873	* Init related code.
1874	* Init related code.
1875	* Init related code.
1876	*
1877	*
1878	*/
1879	#ifdef VBOX_IN_VMM
1880
1881
1882	/**
1883	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1884	*
1885	* This ignores the fSubLeafMask.
1886	*
1887	* @returns Pointer to the matching leaf, or NULL if not found.
1888	* @param paLeaves The CPUID leaves to search. This is sorted.
1889	* @param cLeaves The number of leaves in the array.
1890	* @param uLeaf The leaf to locate.
1891	* @param uSubLeaf The subleaf to locate.
1892	*/
1893	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1894	{
1895	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1896	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1897	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1898	if (iEnd)
1899	{
1900	uint32_t iBegin = 0;
1901	for (;;)
1902	{
1903	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1904	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1905	if (uNeedle < uCur)
1906	{
1907	if (i > iBegin)
1908	iEnd = i;
1909	else
1910	break;
1911	}
1912	else if (uNeedle > uCur)
1913	{
1914	if (i + 1 < iEnd)
1915	iBegin = i + 1;
1916	else
1917	break;
1918	}
1919	else
1920	return &paLeaves[i];
1921	}
1922	}
1923	return NULL;
1924	}
1925
1926
1927	/**
1928	* Loads MSR range overrides.
1929	*
1930	* This must be called before the MSR ranges are moved from the normal heap to
1931	* the hyper heap!
1932	*
1933	* @returns VBox status code (VMSetError called).
1934	* @param pVM The cross context VM structure.
1935	* @param pMsrNode The CFGM node with the MSR overrides.
1936	*/
1937	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1938	{
1939	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1940	{
1941	/*
1942	* Assemble a valid MSR range.
1943	*/
1944	CPUMMSRRANGE MsrRange;
1945	MsrRange.offCpumCpu = 0;
1946	MsrRange.fReserved = 0;
1947
1948	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1949	if (RT_FAILURE(rc))
1950	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1951
1952	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1953	if (RT_FAILURE(rc))
1954	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1955	MsrRange.szName, rc);
1956
1957	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1958	if (RT_FAILURE(rc))
1959	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1960	MsrRange.szName, rc);
1961
1962	char szType[32];
1963	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1964	if (RT_FAILURE(rc))
1965	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1966	MsrRange.szName, rc);
1967	if (!RTStrICmp(szType, "FixedValue"))
1968	{
1969	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1970	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1971
1972	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1973	if (RT_FAILURE(rc))
1974	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1975	MsrRange.szName, rc);
1976
1977	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1978	if (RT_FAILURE(rc))
1979	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1980	MsrRange.szName, rc);
1981
1982	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1983	if (RT_FAILURE(rc))
1984	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1985	MsrRange.szName, rc);
1986	}
1987	else
1988	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1989	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1990
1991	/*
1992	* Insert the range into the table (replaces/splits/shrinks existing
1993	* MSR ranges).
1994	*/
1995	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1996	&MsrRange);
1997	if (RT_FAILURE(rc))
1998	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
1999	}
2000
2001	return VINF_SUCCESS;
2002	}
2003
2004
2005	/**
2006	* Loads CPUID leaf overrides.
2007	*
2008	* This must be called before the CPUID leaves are moved from the normal
2009	* heap to the hyper heap!
2010	*
2011	* @returns VBox status code (VMSetError called).
2012	* @param pVM The cross context VM structure.
2013	* @param pParentNode The CFGM node with the CPUID leaves.
2014	* @param pszLabel How to label the overrides we're loading.
2015	*/
2016	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2017	{
2018	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2019	{
2020	/*
2021	* Get the leaf and subleaf numbers.
2022	*/
2023	char szName[128];
2024	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2025	if (RT_FAILURE(rc))
2026	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2027
2028	/* The leaf number is either specified directly or thru the node name. */
2029	uint32_t uLeaf;
2030	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2031	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2032	{
2033	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2034	if (rc != VINF_SUCCESS)
2035	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2036	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2037	}
2038	else if (RT_FAILURE(rc))
2039	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2040	pszLabel, szName, rc);
2041
2042	uint32_t uSubLeaf;
2043	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2044	if (RT_FAILURE(rc))
2045	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2046	pszLabel, szName, rc);
2047
2048	uint32_t fSubLeafMask;
2049	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2050	if (RT_FAILURE(rc))
2051	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2052	pszLabel, szName, rc);
2053
2054	/*
2055	* Look up the specified leaf, since the output register values
2056	* defaults to any existing values. This allows overriding a single
2057	* register, without needing to know the other values.
2058	*/
2059	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2060	CPUMCPUIDLEAF Leaf;
2061	if (pLeaf)
2062	Leaf = *pLeaf;
2063	else
2064	RT_ZERO(Leaf);
2065	Leaf.uLeaf = uLeaf;
2066	Leaf.uSubLeaf = uSubLeaf;
2067	Leaf.fSubLeafMask = fSubLeafMask;
2068
2069	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2070	if (RT_FAILURE(rc))
2071	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2072	pszLabel, szName, rc);
2073	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2074	if (RT_FAILURE(rc))
2075	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2076	pszLabel, szName, rc);
2077	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2078	if (RT_FAILURE(rc))
2079	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2080	pszLabel, szName, rc);
2081	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2082	if (RT_FAILURE(rc))
2083	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2084	pszLabel, szName, rc);
2085
2086	/*
2087	* Insert the leaf into the table (replaces existing ones).
2088	*/
2089	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2090	&Leaf);
2091	if (RT_FAILURE(rc))
2092	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2093	}
2094
2095	return VINF_SUCCESS;
2096	}
2097
2098
2099
2100	/**
2101	* Fetches overrides for a CPUID leaf.
2102	*
2103	* @returns VBox status code.
2104	* @param pLeaf The leaf to load the overrides into.
2105	* @param pCfgNode The CFGM node containing the overrides
2106	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2107	* @param iLeaf The CPUID leaf number.
2108	*/
2109	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2110	{
2111	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2112	if (pLeafNode)
2113	{
2114	uint32_t u32;
2115	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2116	if (RT_SUCCESS(rc))
2117	pLeaf->uEax = u32;
2118	else
2119	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2120
2121	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2122	if (RT_SUCCESS(rc))
2123	pLeaf->uEbx = u32;
2124	else
2125	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2126
2127	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2128	if (RT_SUCCESS(rc))
2129	pLeaf->uEcx = u32;
2130	else
2131	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2132
2133	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2134	if (RT_SUCCESS(rc))
2135	pLeaf->uEdx = u32;
2136	else
2137	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2138
2139	}
2140	return VINF_SUCCESS;
2141	}
2142
2143
2144	/**
2145	* Load the overrides for a set of CPUID leaves.
2146	*
2147	* @returns VBox status code.
2148	* @param paLeaves The leaf array.
2149	* @param cLeaves The number of leaves.
2150	* @param uStart The start leaf number.
2151	* @param pCfgNode The CFGM node containing the overrides
2152	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2153	*/
2154	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2155	{
2156	for (uint32_t i = 0; i < cLeaves; i++)
2157	{
2158	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2159	if (RT_FAILURE(rc))
2160	return rc;
2161	}
2162
2163	return VINF_SUCCESS;
2164	}
2165
2166
2167	/**
2168	* Installs the CPUID leaves and explods the data into structures like
2169	* GuestFeatures and CPUMCTX::aoffXState.
2170	*
2171	* @returns VBox status code.
2172	* @param pVM The cross context VM structure.
2173	* @param pCpum The CPUM part of @a VM.
2174	* @param paLeaves The leaves. These will be copied (but not freed).
2175	* @param cLeaves The number of leaves.
2176	*/
2177	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
2178	{
2179	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2180
2181	/*
2182	* Install the CPUID information.
2183	*/
2184	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2185	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2186
2187	AssertLogRelRCReturn(rc, rc);
2188	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2189	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2190	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2191	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2192	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2193
2194	/*
2195	* Update the default CPUID leaf if necessary.
2196	*/
2197	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2198	{
2199	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2200	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2201	{
2202	/* We don't use CPUID(0).eax here because of the NT hack that only
2203	changes that value without actually removing any leaves. */
2204	uint32_t i = 0;
2205	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2206	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2207	{
2208	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2209	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2210	i++;
2211	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2212	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2213	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2214	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2215	}
2216	break;
2217	}
2218	default:
2219	break;
2220	}
2221
2222	/*
2223	* Explode the guest CPU features.
2224	*/
2225	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
2226	AssertLogRelRCReturn(rc, rc);
2227
2228	/*
2229	* Adjust the scalable bus frequency according to the CPUID information
2230	* we're now using.
2231	*/
2232	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2233	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2234	? UINT64_C(100000000) /* 100MHz */
2235	: UINT64_C(133333333); /* 133MHz */
2236
2237	/*
2238	* Populate the legacy arrays. Currently used for everything, later only
2239	* for patch manager.
2240	*/
2241	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2242	{
2243	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2244	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2245	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2246	};
2247	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2248	{
2249	uint32_t cLeft = aOldRanges[i].cCpuIds;
2250	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2251	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2252	while (cLeft-- > 0)
2253	{
2254	uLeaf--;
2255	pLegacyLeaf--;
2256
2257	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2258	if (pLeaf)
2259	{
2260	pLegacyLeaf->uEax = pLeaf->uEax;
2261	pLegacyLeaf->uEbx = pLeaf->uEbx;
2262	pLegacyLeaf->uEcx = pLeaf->uEcx;
2263	pLegacyLeaf->uEdx = pLeaf->uEdx;
2264	}
2265	else
2266	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2267	}
2268	}
2269
2270	/*
2271	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2272	*/
2273	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2274	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2275	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2276	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2277	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2278	{
2279	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2280	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2281	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2282	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2283	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2284	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2285	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2286	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2287	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2288	pCpum->GuestFeatures.cbMaxExtendedState),
2289	VERR_CPUM_IPE_1);
2290	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2291	}
2292	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2293
2294	/* Copy the CPU #0 data to the other CPUs. */
2295	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2296	{
2297	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2298	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2299	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2300	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2301	}
2302
2303	return VINF_SUCCESS;
2304	}
2305
2306
2307	/** @name Instruction Set Extension Options
2308	* @{ */
2309	/** Configuration option type (extended boolean, really). */
2310	typedef uint8_t CPUMISAEXTCFG;
2311	/** Always disable the extension. */
2312	#define CPUMISAEXTCFG_DISABLED false
2313	/** Enable the extension if it's supported by the host CPU. */
2314	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2315	/** Enable the extension if it's supported by the host CPU, but don't let
2316	* the portable CPUID feature disable it. */
2317	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2318	/** Always enable the extension. */
2319	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2320	/** @} */
2321
2322	/**
2323	* CPUID Configuration (from CFGM).
2324	*
2325	* @remarks The members aren't document since we would only be duplicating the
2326	* \@cfgm entries in cpumR3CpuIdReadConfig.
2327	*/
2328	typedef struct CPUMCPUIDCONFIG
2329	{
2330	bool fNt4LeafLimit;
2331	bool fInvariantTsc;
2332	bool fForceVme;
2333	bool fNestedHWVirt;
2334
2335	CPUMISAEXTCFG enmCmpXchg16b;
2336	CPUMISAEXTCFG enmMonitor;
2337	CPUMISAEXTCFG enmMWaitExtensions;
2338	CPUMISAEXTCFG enmSse41;
2339	CPUMISAEXTCFG enmSse42;
2340	CPUMISAEXTCFG enmAvx;
2341	CPUMISAEXTCFG enmAvx2;
2342	CPUMISAEXTCFG enmXSave;
2343	CPUMISAEXTCFG enmAesNi;
2344	CPUMISAEXTCFG enmPClMul;
2345	CPUMISAEXTCFG enmPopCnt;
2346	CPUMISAEXTCFG enmMovBe;
2347	CPUMISAEXTCFG enmRdRand;
2348	CPUMISAEXTCFG enmRdSeed;
2349	CPUMISAEXTCFG enmCLFlushOpt;
2350	CPUMISAEXTCFG enmFsGsBase;
2351	CPUMISAEXTCFG enmPcid;
2352	CPUMISAEXTCFG enmInvpcid;
2353
2354	CPUMISAEXTCFG enmAbm;
2355	CPUMISAEXTCFG enmSse4A;
2356	CPUMISAEXTCFG enmMisAlnSse;
2357	CPUMISAEXTCFG enm3dNowPrf;
2358	CPUMISAEXTCFG enmAmdExtMmx;
2359
2360	uint32_t uMaxStdLeaf;
2361	uint32_t uMaxExtLeaf;
2362	uint32_t uMaxCentaurLeaf;
2363	uint32_t uMaxIntelFamilyModelStep;
2364	char szCpuName[128];
2365	} CPUMCPUIDCONFIG;
2366	/** Pointer to CPUID config (from CFGM). */
2367	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2368
2369
2370	/**
2371	* Mini CPU selection support for making Mac OS X happy.
2372	*
2373	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2374	*
2375	* @param pCpum The CPUM instance data.
2376	* @param pConfig The CPUID configuration we've read from CFGM.
2377	*/
2378	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2379	{
2380	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2381	{
2382	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2383	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2384	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2385	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2386	0);
2387	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2388	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2389	{
2390	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2391	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2392	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2393	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2394	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2395	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2396	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2397	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2398	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2399	pStdFeatureLeaf->uEax = uNew;
2400	}
2401	}
2402	}
2403
2404
2405
2406	/**
2407	* Limit it the number of entries, zapping the remainder.
2408	*
2409	* The limits are masking off stuff about power saving and similar, this
2410	* is perhaps a bit crudely done as there is probably some relatively harmless
2411	* info too in these leaves (like words about having a constant TSC).
2412	*
2413	* @param pCpum The CPUM instance data.
2414	* @param pConfig The CPUID configuration we've read from CFGM.
2415	*/
2416	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2417	{
2418	/*
2419	* Standard leaves.
2420	*/
2421	uint32_t uSubLeaf = 0;
2422	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2423	if (pCurLeaf)
2424	{
2425	uint32_t uLimit = pCurLeaf->uEax;
2426	if (uLimit <= UINT32_C(0x000fffff))
2427	{
2428	if (uLimit > pConfig->uMaxStdLeaf)
2429	{
2430	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2431	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2432	uLimit + 1, UINT32_C(0x000fffff));
2433	}
2434
2435	/* NT4 hack, no zapping of extra leaves here. */
2436	if (pConfig->fNt4LeafLimit && uLimit > 3)
2437	pCurLeaf->uEax = uLimit = 3;
2438
2439	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2440	pCurLeaf->uEax = uLimit;
2441	}
2442	else
2443	{
2444	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2445	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2446	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2447	}
2448	}
2449
2450	/*
2451	* Extended leaves.
2452	*/
2453	uSubLeaf = 0;
2454	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2455	if (pCurLeaf)
2456	{
2457	uint32_t uLimit = pCurLeaf->uEax;
2458	if ( uLimit >= UINT32_C(0x80000000)
2459	&& uLimit <= UINT32_C(0x800fffff))
2460	{
2461	if (uLimit > pConfig->uMaxExtLeaf)
2462	{
2463	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2464	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2465	uLimit + 1, UINT32_C(0x800fffff));
2466	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2467	pCurLeaf->uEax = uLimit;
2468	}
2469	}
2470	else
2471	{
2472	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2473	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2474	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2475	}
2476	}
2477
2478	/*
2479	* Centaur leaves (VIA).
2480	*/
2481	uSubLeaf = 0;
2482	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2483	if (pCurLeaf)
2484	{
2485	uint32_t uLimit = pCurLeaf->uEax;
2486	if ( uLimit >= UINT32_C(0xc0000000)
2487	&& uLimit <= UINT32_C(0xc00fffff))
2488	{
2489	if (uLimit > pConfig->uMaxCentaurLeaf)
2490	{
2491	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2492	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2493	uLimit + 1, UINT32_C(0xcfffffff));
2494	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2495	pCurLeaf->uEax = uLimit;
2496	}
2497	}
2498	else
2499	{
2500	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2501	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2502	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2503	}
2504	}
2505	}
2506
2507
2508	/**
2509	* Clears a CPUID leaf and all sub-leaves (to zero).
2510	*
2511	* @param pCpum The CPUM instance data.
2512	* @param uLeaf The leaf to clear.
2513	*/
2514	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2515	{
2516	uint32_t uSubLeaf = 0;
2517	PCPUMCPUIDLEAF pCurLeaf;
2518	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2519	{
2520	pCurLeaf->uEax = 0;
2521	pCurLeaf->uEbx = 0;
2522	pCurLeaf->uEcx = 0;
2523	pCurLeaf->uEdx = 0;
2524	uSubLeaf++;
2525	}
2526	}
2527
2528
2529	/**
2530	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2531	* the given leaf.
2532	*
2533	* @returns pLeaf.
2534	* @param pCpum The CPUM instance data.
2535	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2536	*/
2537	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2538	{
2539	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2540	if (pLeaf->fSubLeafMask != 0)
2541	{
2542	/*
2543	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2544	* Log everything while we're at it.
2545	*/
2546	LogRel(("CPUM:\n"
2547	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2548	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2549	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2550	for (;;)
2551	{
2552	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2553	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2554	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2555	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2556	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2557	break;
2558	pSubLeaf++;
2559	}
2560	LogRel(("CPUM:\n"));
2561
2562	/*
2563	* Remove the offending sub-leaves.
2564	*/
2565	if (pSubLeaf != pLeaf)
2566	{
2567	if (pSubLeaf != pLast)
2568	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2569	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2570	}
2571
2572	/*
2573	* Convert the first sub-leaf into a single leaf.
2574	*/
2575	pLeaf->uSubLeaf = 0;
2576	pLeaf->fSubLeafMask = 0;
2577	}
2578	return pLeaf;
2579	}
2580
2581
2582	/**
2583	* Sanitizes and adjust the CPUID leaves.
2584	*
2585	* Drop features that aren't virtualized (or virtualizable). Adjust information
2586	* and capabilities to fit the virtualized hardware. Remove information the
2587	* guest shouldn't have (because it's wrong in the virtual world or because it
2588	* gives away host details) or that we don't have documentation for and no idea
2589	* what means.
2590	*
2591	* @returns VBox status code.
2592	* @param pVM The cross context VM structure (for cCpus).
2593	* @param pCpum The CPUM instance data.
2594	* @param pConfig The CPUID configuration we've read from CFGM.
2595	*/
2596	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2597	{
2598	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2599	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2600	{ \
2601	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2602	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2603	}
2604	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2605	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2606	{ \
2607	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2608	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2609	}
2610	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2611	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2612	&& ((a_pLeafReg) & (fBitMask)) \
2613	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2614	{ \
2615	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2616	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2617	}
2618	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2619
2620	/* Cpuid 1:
2621	* EAX: CPU model, family and stepping.
2622	*
2623	* ECX + EDX: Supported features. Only report features we can support.
2624	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2625	* options may require adjusting (i.e. stripping what was enabled).
2626	*
2627	* EBX: Branding, CLFLUSH line size, logical processors per package and
2628	* initial APIC ID.
2629	*/
2630	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2631	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2632	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2633
2634	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2635	\| X86_CPUID_FEATURE_EDX_VME
2636	\| X86_CPUID_FEATURE_EDX_DE
2637	\| X86_CPUID_FEATURE_EDX_PSE
2638	\| X86_CPUID_FEATURE_EDX_TSC
2639	\| X86_CPUID_FEATURE_EDX_MSR
2640	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2641	\| X86_CPUID_FEATURE_EDX_MCE
2642	\| X86_CPUID_FEATURE_EDX_CX8
2643	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2644	//\| RT_BIT_32(10) - not defined
2645	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2646	//\| X86_CPUID_FEATURE_EDX_SEP
2647	\| X86_CPUID_FEATURE_EDX_MTRR
2648	\| X86_CPUID_FEATURE_EDX_PGE
2649	\| X86_CPUID_FEATURE_EDX_MCA
2650	\| X86_CPUID_FEATURE_EDX_CMOV
2651	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2652	\| X86_CPUID_FEATURE_EDX_PSE36
2653	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2654	\| X86_CPUID_FEATURE_EDX_CLFSH
2655	//\| RT_BIT_32(20) - not defined
2656	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2657	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2658	\| X86_CPUID_FEATURE_EDX_MMX
2659	\| X86_CPUID_FEATURE_EDX_FXSR
2660	\| X86_CPUID_FEATURE_EDX_SSE
2661	\| X86_CPUID_FEATURE_EDX_SSE2
2662	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2663	\| X86_CPUID_FEATURE_EDX_HTT
2664	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2665	//\| RT_BIT_32(30) - not defined
2666	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2667	;
2668	pStdFeatureLeaf->uEcx &= 0
2669	\| X86_CPUID_FEATURE_ECX_SSE3
2670	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2671	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2672	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2673	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2674	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2675	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2676	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2677	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2678	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2679	\| X86_CPUID_FEATURE_ECX_SSSE3
2680	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2681	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2682	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2683	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2684	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2685	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2686	\| (pConfig->enmPcid ? X86_CPUID_FEATURE_ECX_PCID : 0)
2687	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2688	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2689	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2690	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2691	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2692	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2693	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2694	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2695	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2696	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2697	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2698	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2699	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2700	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2701	;
2702
2703	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2704	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2705	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2706	{
2707	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2708	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2709	}
2710
2711	if (pCpum->u8PortableCpuIdLevel > 0)
2712	{
2713	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2714	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2715	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2716	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2717	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2718	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2719	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2720	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2721	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2722	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2723	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2724	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2725	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2726	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2727	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2728	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2729	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2730	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2731	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2732	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2733
2734	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2735	\| X86_CPUID_FEATURE_EDX_PSN
2736	\| X86_CPUID_FEATURE_EDX_DS
2737	\| X86_CPUID_FEATURE_EDX_ACPI
2738	\| X86_CPUID_FEATURE_EDX_SS
2739	\| X86_CPUID_FEATURE_EDX_TM
2740	\| X86_CPUID_FEATURE_EDX_PBE
2741	)));
2742	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2743	\| X86_CPUID_FEATURE_ECX_CPLDS
2744	\| X86_CPUID_FEATURE_ECX_AES
2745	\| X86_CPUID_FEATURE_ECX_VMX
2746	\| X86_CPUID_FEATURE_ECX_SMX
2747	\| X86_CPUID_FEATURE_ECX_EST
2748	\| X86_CPUID_FEATURE_ECX_TM2
2749	\| X86_CPUID_FEATURE_ECX_CNTXID
2750	\| X86_CPUID_FEATURE_ECX_FMA
2751	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2752	\| X86_CPUID_FEATURE_ECX_PDCM
2753	\| X86_CPUID_FEATURE_ECX_DCA
2754	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2755	)));
2756	}
2757
2758	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2759	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2760
2761	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2762	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2763	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2764	*/
2765	#ifdef VBOX_WITH_MULTI_CORE
2766	if (pVM->cCpus > 1)
2767	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2768	#endif
2769	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2770	{
2771	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2772	core times the number of CPU cores per processor */
2773	#ifdef VBOX_WITH_MULTI_CORE
2774	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2775	#else
2776	/* Single logical processor in a package. */
2777	pStdFeatureLeaf->uEbx \|= (1 << 16);
2778	#endif
2779	}
2780
2781	uint32_t uMicrocodeRev;
2782	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2783	if (RT_SUCCESS(rc))
2784	{
2785	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2786	}
2787	else
2788	{
2789	uMicrocodeRev = 0;
2790	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2791	}
2792
2793	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2794	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2795	*/
2796	if ( (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen)
2797	&& uMicrocodeRev < 0x8001126
2798	&& !pConfig->fForceVme)
2799	{
2800	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2801	LogRel(("CPUM: Zen VME workaround engaged\n"));
2802	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2803	}
2804
2805	/* Force standard feature bits. */
2806	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2807	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2808	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2809	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2810	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2811	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2812	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2813	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2814	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2815	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2816	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2817	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2818	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2819	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2820	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2821	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2822	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2823	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2824	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2825	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2826	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2827	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2828
2829	pStdFeatureLeaf = NULL; /* Must refetch! */
2830
2831	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2832	* AMD:
2833	* EAX: CPU model, family and stepping.
2834	*
2835	* ECX + EDX: Supported features. Only report features we can support.
2836	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2837	* options may require adjusting (i.e. stripping what was enabled).
2838	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2839	*
2840	* EBX: Branding ID and package type (or reserved).
2841	*
2842	* Intel and probably most others:
2843	* EAX: 0
2844	* EBX: 0
2845	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2846	*/
2847	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2848	if (pExtFeatureLeaf)
2849	{
2850	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2851
2852	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2853	\| X86_CPUID_AMD_FEATURE_EDX_VME
2854	\| X86_CPUID_AMD_FEATURE_EDX_DE
2855	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2856	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2857	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2858	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2859	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2860	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2861	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2862	//\| RT_BIT_32(10) - reserved
2863	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2864	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2865	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2866	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2867	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2868	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2869	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2870	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2871	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2872	//\| RT_BIT_32(18) - reserved
2873	//\| RT_BIT_32(19) - reserved
2874	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2875	//\| RT_BIT_32(21) - reserved
2876	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2877	\| X86_CPUID_AMD_FEATURE_EDX_MMX
2878	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
2879	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
2880	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2881	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2882	//\| RT_BIT_32(28) - reserved
2883	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2884	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2885	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
2886	;
2887	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2888	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2889	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
2890	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2891	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
2892	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2893	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2894	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2895	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2896	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2897	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2898	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
2899	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
2900	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2901	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
2902	//\| RT_BIT_32(14) - reserved
2903	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2904	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2905	//\| RT_BIT_32(17) - reserved
2906	//\| RT_BIT_32(18) - reserved
2907	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2908	//\| RT_BIT_32(20) - reserved
2909	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2910	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2911	//\| RT_BIT_32(23) - reserved
2912	//\| RT_BIT_32(24) - reserved
2913	//\| RT_BIT_32(25) - reserved
2914	//\| RT_BIT_32(26) - reserved
2915	//\| RT_BIT_32(27) - reserved
2916	//\| RT_BIT_32(28) - reserved
2917	//\| RT_BIT_32(29) - reserved
2918	//\| RT_BIT_32(30) - reserved
2919	//\| RT_BIT_32(31) - reserved
2920	;
2921	#ifdef VBOX_WITH_MULTI_CORE
2922	if ( pVM->cCpus > 1
2923	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2924	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2925	#endif
2926
2927	if (pCpum->u8PortableCpuIdLevel > 0)
2928	{
2929	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2930	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
2931	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2932	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2933	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2934	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2935	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2936	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2937	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2938	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2939	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2940	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2941	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2942	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2943	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2944	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2945
2946	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2947	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2948	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2949	\| X86_CPUID_AMD_FEATURE_ECX_IBS
2950	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2951	\| X86_CPUID_AMD_FEATURE_ECX_WDT
2952	\| X86_CPUID_AMD_FEATURE_ECX_LWP
2953	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
2954	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2955	\| UINT32_C(0xff964000)
2956	)));
2957	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2958	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2959	\| RT_BIT(18)
2960	\| RT_BIT(19)
2961	\| RT_BIT(21)
2962	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2963	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2964	\| RT_BIT(28)
2965	)));
2966	}
2967
2968	/* Force extended feature bits. */
2969	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2970	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
2971	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2972	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2973	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2974	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2975	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2976	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2977	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2978	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2979	}
2980	pExtFeatureLeaf = NULL; /* Must refetch! */
2981
2982
2983	/* Cpuid 2:
2984	* Intel: (Nondeterministic) Cache and TLB information
2985	* AMD: Reserved
2986	* VIA: Reserved
2987	* Safe to expose.
2988	*/
2989	uint32_t uSubLeaf = 0;
2990	PCPUMCPUIDLEAF pCurLeaf;
2991	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2992	{
2993	if ((pCurLeaf->uEax & 0xff) > 1)
2994	{
2995	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2996	pCurLeaf->uEax &= UINT32_C(0xffffff01);
2997	}
2998	uSubLeaf++;
2999	}
3000
3001	/* Cpuid 3:
3002	* Intel: EAX, EBX - reserved (transmeta uses these)
3003	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3004	* AMD: Reserved
3005	* VIA: Reserved
3006	* Safe to expose
3007	*/
3008	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3009	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3010	{
3011	uSubLeaf = 0;
3012	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3013	{
3014	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3015	if (pCpum->u8PortableCpuIdLevel > 0)
3016	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3017	uSubLeaf++;
3018	}
3019	}
3020
3021	/* Cpuid 4 + ECX:
3022	* Intel: Deterministic Cache Parameters Leaf.
3023	* AMD: Reserved
3024	* VIA: Reserved
3025	* Safe to expose, except for EAX:
3026	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3027	* Bits 31-26: Maximum number of processor cores in this physical package**
3028	* Note: These SMP values are constant regardless of ECX
3029	*/
3030	uSubLeaf = 0;
3031	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3032	{
3033	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3034	#ifdef VBOX_WITH_MULTI_CORE
3035	if ( pVM->cCpus > 1
3036	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3037	{
3038	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3039	/* One logical processor with possibly multiple cores. */
3040	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3041	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3042	}
3043	#endif
3044	uSubLeaf++;
3045	}
3046
3047	/* Cpuid 5: Monitor/mwait Leaf
3048	* Intel: ECX, EDX - reserved
3049	* EAX, EBX - Smallest and largest monitor line size
3050	* AMD: EDX - reserved
3051	* EAX, EBX - Smallest and largest monitor line size
3052	* ECX - extensions (ignored for now)
3053	* VIA: Reserved
3054	* Safe to expose
3055	*/
3056	uSubLeaf = 0;
3057	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3058	{
3059	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3060	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3061	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3062
3063	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3064	if (pConfig->enmMWaitExtensions)
3065	{
3066	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3067	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3068	it shall be part of our power management virtualization model */
3069	#if 0
3070	/* MWAIT sub C-states */
3071	pCurLeaf->uEdx =
3072	(0 << 0) /* 0 in C0 */ \|
3073	(2 << 4) /* 2 in C1 */ \|
3074	(2 << 8) /* 2 in C2 */ \|
3075	(2 << 12) /* 2 in C3 */ \|
3076	(0 << 16) /* 0 in C4 */
3077	;
3078	#endif
3079	}
3080	else
3081	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3082	uSubLeaf++;
3083	}
3084
3085	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3086	* Intel: Various stuff.
3087	* AMD: EAX, EBX, EDX - reserved.
3088	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3089	* present. Same as intel.
3090	* VIA: ??
3091	*
3092	* We clear everything here for now.
3093	*/
3094	cpumR3CpuIdZeroLeaf(pCpum, 6);
3095
3096	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3097	* EAX: Number of sub leaves.
3098	* EBX+ECX+EDX: Feature flags
3099	*
3100	* We only have documentation for one sub-leaf, so clear all other (no need
3101	* to remove them as such, just set them to zero).
3102	*
3103	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3104	* options may require adjusting (i.e. stripping what was enabled).
3105	*/
3106	uSubLeaf = 0;
3107	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3108	{
3109	switch (uSubLeaf)
3110	{
3111	case 0:
3112	{
3113	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3114	pCurLeaf->uEbx &= 0
3115	\| (pConfig->enmFsGsBase ? X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE : 0)
3116	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3117	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3118	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3119	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3120	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3121	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3122	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3123	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3124	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3125	\| (pConfig->enmInvpcid ? X86_CPUID_STEXT_FEATURE_EBX_INVPCID : 0)
3126	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3127	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3128	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3129	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3130	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3131	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3132	//\| RT_BIT(17) - reserved
3133	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3134	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3135	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3136	//\| RT_BIT(21) - reserved
3137	//\| RT_BIT(22) - reserved
3138	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3139	//\| RT_BIT(24) - reserved
3140	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3141	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3142	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3143	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3144	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3145	//\| RT_BIT(30) - reserved
3146	//\| RT_BIT(31) - reserved
3147	;
3148	pCurLeaf->uEcx &= 0
3149	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3150	;
3151	pCurLeaf->uEdx &= 0
3152	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3153	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3154	//\| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT(29)
3155	;
3156
3157	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3158	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3159	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3160	{
3161	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3162	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3163	}
3164
3165	if (pCpum->u8PortableCpuIdLevel > 0)
3166	{
3167	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3168	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3169	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3170	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3171	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3172	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3173	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3174	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3175	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3176	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3177	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3178	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3179	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3180	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3181	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3182	}
3183
3184	/* Force standard feature bits. */
3185	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3186	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3187	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3188	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3189	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3190	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3191	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3192	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3193	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3194	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3195	break;
3196	}
3197
3198	default:
3199	/* Invalid index, all values are zero. */
3200	pCurLeaf->uEax = 0;
3201	pCurLeaf->uEbx = 0;
3202	pCurLeaf->uEcx = 0;
3203	pCurLeaf->uEdx = 0;
3204	break;
3205	}
3206	uSubLeaf++;
3207	}
3208
3209	/* Cpuid 8: Marked as reserved by Intel and AMD.
3210	* We zero this since we don't know what it may have been used for.
3211	*/
3212	cpumR3CpuIdZeroLeaf(pCpum, 8);
3213
3214	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3215	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3216	* EBX, ECX, EDX - reserved.
3217	* AMD: Reserved
3218	* VIA: ??
3219	*
3220	* We zero this.
3221	*/
3222	cpumR3CpuIdZeroLeaf(pCpum, 9);
3223
3224	/* Cpuid 0xa: Architectural Performance Monitor Features
3225	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3226	* EBX, ECX, EDX - reserved.
3227	* AMD: Reserved
3228	* VIA: ??
3229	*
3230	* We zero this, for now at least.
3231	*/
3232	cpumR3CpuIdZeroLeaf(pCpum, 10);
3233
3234	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3235	* Intel: EAX - APCI ID shift right for next level.
3236	* EBX - Factory configured cores/threads at this level.
3237	* ECX - Level number (same as input) and level type (1,2,0).
3238	* EDX - Extended initial APIC ID.
3239	* AMD: Reserved
3240	* VIA: ??
3241	*/
3242	uSubLeaf = 0;
3243	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3244	{
3245	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3246	{
3247	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3248	if (bLevelType == 1)
3249	{
3250	/* Thread level - we don't do threads at the moment. */
3251	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3252	pCurLeaf->uEbx = 1;
3253	}
3254	else if (bLevelType == 2)
3255	{
3256	/* Core level. */
3257	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3258	#ifdef VBOX_WITH_MULTI_CORE
3259	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3260	pCurLeaf->uEax++;
3261	#endif
3262	pCurLeaf->uEbx = pVM->cCpus;
3263	}
3264	else
3265	{
3266	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3267	pCurLeaf->uEax = 0;
3268	pCurLeaf->uEbx = 0;
3269	pCurLeaf->uEcx = 0;
3270	}
3271	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3272	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3273	}
3274	else
3275	{
3276	pCurLeaf->uEax = 0;
3277	pCurLeaf->uEbx = 0;
3278	pCurLeaf->uEcx = 0;
3279	pCurLeaf->uEdx = 0;
3280	}
3281	uSubLeaf++;
3282	}
3283
3284	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3285	* We zero this since we don't know what it may have been used for.
3286	*/
3287	cpumR3CpuIdZeroLeaf(pCpum, 12);
3288
3289	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3290	* ECX=0: EAX - Valid bits in XCR0[31:0].
3291	* EBX - Maximum state size as per current XCR0 value.
3292	* ECX - Maximum state size for all supported features.
3293	* EDX - Valid bits in XCR0[63:32].
3294	* ECX=1: EAX - Various X-features.
3295	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3296	* ECX - Valid bits in IA32_XSS[31:0].
3297	* EDX - Valid bits in IA32_XSS[63:32].
3298	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3299	* if the bit invalid all four registers are set to zero.
3300	* EAX - The state size for this feature.
3301	* EBX - The state byte offset of this feature.
3302	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3303	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3304	*
3305	* Clear them all as we don't currently implement extended CPU state.
3306	*/
3307	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3308	uint64_t fGuestXcr0Mask = 0;
3309	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3310	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3311	{
3312	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3313	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3314	fGuestXcr0Mask \|= XSAVE_C_YMM;
3315	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3316	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3317	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3318	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3319
3320	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3321	}
3322	pStdFeatureLeaf = NULL;
3323	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3324
3325	/* Work the sub-leaves. */
3326	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3327	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3328	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3329	{
3330	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3331	if (pCurLeaf)
3332	{
3333	if (fGuestXcr0Mask)
3334	{
3335	switch (uSubLeaf)
3336	{
3337	case 0:
3338	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3339	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3340	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3341	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3342	VERR_CPUM_IPE_1);
3343	cbXSaveMaxActual = pCurLeaf->uEcx;
3344	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3345	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3346	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3347	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3348	VERR_CPUM_IPE_2);
3349	continue;
3350	case 1:
3351	pCurLeaf->uEax &= 0;
3352	pCurLeaf->uEcx &= 0;
3353	pCurLeaf->uEdx &= 0;
3354	/** @todo what about checking ebx? */
3355	continue;
3356	default:
3357	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3358	{
3359	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3360	&& pCurLeaf->uEax > 0
3361	&& pCurLeaf->uEbx < cbXSaveMaxActual
3362	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3363	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3364	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3365	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3366	VERR_CPUM_IPE_2);
3367	AssertLogRel(!(pCurLeaf->uEcx & 1));
3368	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3369	pCurLeaf->uEdx = 0; /* it's reserved... */
3370	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3371	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3372	continue;
3373	}
3374	break;
3375	}
3376	}
3377
3378	/* Clear the leaf. */
3379	pCurLeaf->uEax = 0;
3380	pCurLeaf->uEbx = 0;
3381	pCurLeaf->uEcx = 0;
3382	pCurLeaf->uEdx = 0;
3383	}
3384	}
3385
3386	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3387	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3388	{
3389	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3390	if (pCurLeaf)
3391	{
3392	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3393	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3394	pCurLeaf->uEbx = cbXSaveMaxReport;
3395	pCurLeaf->uEcx = cbXSaveMaxReport;
3396	}
3397	}
3398
3399	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3400	* We zero this since we don't know what it may have been used for.
3401	*/
3402	cpumR3CpuIdZeroLeaf(pCpum, 14);
3403
3404	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3405	* also known as Intel Resource Director Technology (RDT) Monitoring
3406	* We zero this as we don't currently virtualize PQM.
3407	*/
3408	cpumR3CpuIdZeroLeaf(pCpum, 15);
3409
3410	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3411	* also known as Intel Resource Director Technology (RDT) Allocation
3412	* We zero this as we don't currently virtualize PQE.
3413	*/
3414	cpumR3CpuIdZeroLeaf(pCpum, 16);
3415
3416	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3417	* We zero this since we don't know what it may have been used for.
3418	*/
3419	cpumR3CpuIdZeroLeaf(pCpum, 17);
3420
3421	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3422	* We zero this as we don't currently virtualize this.
3423	*/
3424	cpumR3CpuIdZeroLeaf(pCpum, 18);
3425
3426	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3427	* We zero this since we don't know what it may have been used for.
3428	*/
3429	cpumR3CpuIdZeroLeaf(pCpum, 19);
3430
3431	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3432	* We zero this as we don't currently virtualize this.
3433	*/
3434	cpumR3CpuIdZeroLeaf(pCpum, 20);
3435
3436	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3437	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3438	* EAX - denominator (unsigned).
3439	* EBX - numerator (unsigned).
3440	* ECX, EDX - reserved.
3441	* AMD: Reserved / undefined / not implemented.
3442	* VIA: Reserved / undefined / not implemented.
3443	* We zero this as we don't currently virtualize this.
3444	*/
3445	cpumR3CpuIdZeroLeaf(pCpum, 21);
3446
3447	/* Cpuid 0x16: Processor frequency info
3448	* Intel: EAX - Core base frequency in MHz.
3449	* EBX - Core maximum frequency in MHz.
3450	* ECX - Bus (reference) frequency in MHz.
3451	* EDX - Reserved.
3452	* AMD: Reserved / undefined / not implemented.
3453	* VIA: Reserved / undefined / not implemented.
3454	* We zero this as we don't currently virtualize this.
3455	*/
3456	cpumR3CpuIdZeroLeaf(pCpum, 22);
3457
3458	/* Cpuid 0x17..0x10000000: Unknown.
3459	* We don't know these and what they mean, so remove them. */
3460	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3461	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3462
3463
3464	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3465	* We remove all these as we're a hypervisor and must provide our own.
3466	*/
3467	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3468	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3469
3470
3471	/* Cpuid 0x80000000 is harmless. */
3472
3473	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3474
3475	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3476
3477	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3478	* Safe to pass on to the guest.
3479	*
3480	* AMD: 0x800000005 L1 cache information
3481	* 0x800000006 L2/L3 cache information
3482	* Intel: 0x800000005 reserved
3483	* 0x800000006 L2 cache information
3484	* VIA: 0x800000005 TLB and L1 cache information
3485	* 0x800000006 L2 cache information
3486	*/
3487
3488	/* Cpuid 0x800000007: Advanced Power Management Information.
3489	* AMD: EAX: Processor feedback capabilities.
3490	* EBX: RAS capabilites.
3491	* ECX: Advanced power monitoring interface.
3492	* EDX: Enhanced power management capabilities.
3493	* Intel: EAX, EBX, ECX - reserved.
3494	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3495	* VIA: Reserved
3496	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3497	*/
3498	uSubLeaf = 0;
3499	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3500	{
3501	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3502	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3503	{
3504	/*
3505	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3506	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3507	* bit is now configurable.
3508	*/
3509	pCurLeaf->uEdx &= 0
3510	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3511	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3512	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3513	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3514	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3515	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3516	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3517	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3518	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3519	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3520	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3521	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3522	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3523	\| 0;
3524	}
3525	else
3526	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3527	if (!pConfig->fInvariantTsc)
3528	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3529	uSubLeaf++;
3530	}
3531
3532	/* Cpuid 0x80000008:
3533	* AMD: EBX, EDX - reserved
3534	* EAX: Virtual/Physical/Guest address Size
3535	* ECX: Number of cores + APICIdCoreIdSize
3536	* Intel: EAX: Virtual/Physical address Size
3537	* EBX, ECX, EDX - reserved
3538	* VIA: EAX: Virtual/Physical address Size
3539	* EBX, ECX, EDX - reserved
3540	*
3541	* We only expose the virtual+pysical address size to the guest atm.
3542	* On AMD we set the core count, but not the apic id stuff as we're
3543	* currently not doing the apic id assignments in a complatible manner.
3544	*/
3545	uSubLeaf = 0;
3546	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3547	{
3548	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3549	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3550	pCurLeaf->uEdx = 0; /* reserved */
3551
3552	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3553	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3554	pCurLeaf->uEcx = 0;
3555	#ifdef VBOX_WITH_MULTI_CORE
3556	if ( pVM->cCpus > 1
3557	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3558	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3559	#endif
3560	uSubLeaf++;
3561	}
3562
3563	/* Cpuid 0x80000009: Reserved
3564	* We zero this since we don't know what it may have been used for.
3565	*/
3566	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3567
3568	/* Cpuid 0x8000000a: SVM Information
3569	* AMD: EAX - SVM revision.
3570	* EBX - Number of ASIDs.
3571	* ECX - Reserved.
3572	* EDX - SVM Feature identification.
3573	*/
3574	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3575	if (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
3576	{
3577	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3578	pSvmFeatureLeaf->uEax = 0x1;
3579	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3580	pSvmFeatureLeaf->uEcx = 0;
3581	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3582	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3583	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3584	}
3585	else
3586	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3587
3588	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3589	* We clear these as we don't know what purpose they might have. */
3590	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3591	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3592
3593	/* Cpuid 0x80000019: TLB configuration
3594	* Seems to be harmless, pass them thru as is. */
3595
3596	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3597	* Strip anything we don't know what is or addresses feature we don't implement. */
3598	uSubLeaf = 0;
3599	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3600	{
3601	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3602	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3603	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3604	;
3605	pCurLeaf->uEbx = 0; /* reserved */
3606	pCurLeaf->uEcx = 0; /* reserved */
3607	pCurLeaf->uEdx = 0; /* reserved */
3608	uSubLeaf++;
3609	}
3610
3611	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3612	* Clear this as we don't currently virtualize this feature. */
3613	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3614
3615	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3616	* Clear this as we don't currently virtualize this feature. */
3617	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3618
3619	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3620	* We need to sanitize the cores per cache (EAX[25:14]).
3621	*
3622	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3623	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3624	* slightly different meaning.
3625	*/
3626	uSubLeaf = 0;
3627	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3628	{
3629	#ifdef VBOX_WITH_MULTI_CORE
3630	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3631	if (cCores > pVM->cCpus)
3632	cCores = pVM->cCpus;
3633	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3634	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3635	#else
3636	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3637	#endif
3638	uSubLeaf++;
3639	}
3640
3641	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3642	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3643	* setup, we have one compute unit with all the cores in it. Single node.
3644	*/
3645	uSubLeaf = 0;
3646	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3647	{
3648	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3649	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3650	{
3651	#ifdef VBOX_WITH_MULTI_CORE
3652	pCurLeaf->uEbx = pVM->cCpus < 0x100
3653	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3654	#else
3655	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3656	#endif
3657	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3658	}
3659	else
3660	{
3661	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3662	pCurLeaf->uEbx = 0; /* Reserved. */
3663	pCurLeaf->uEcx = 0; /* Reserved. */
3664	}
3665	pCurLeaf->uEdx = 0; /* Reserved. */
3666	uSubLeaf++;
3667	}
3668
3669	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3670	* We don't know these and what they mean, so remove them. */
3671	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3672	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3673
3674	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3675	* Just pass it thru for now. */
3676
3677	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3678	* Just pass it thru for now. */
3679
3680	/* Cpuid 0xc0000000: Centaur stuff.
3681	* Harmless, pass it thru. */
3682
3683	/* Cpuid 0xc0000001: Centaur features.
3684	* VIA: EAX - Family, model, stepping.
3685	* EDX - Centaur extended feature flags. Nothing interesting, except may
3686	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3687	* EBX, ECX - reserved.
3688	* We keep EAX but strips the rest.
3689	*/
3690	uSubLeaf = 0;
3691	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3692	{
3693	pCurLeaf->uEbx = 0;
3694	pCurLeaf->uEcx = 0;
3695	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3696	uSubLeaf++;
3697	}
3698
3699	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3700	* We only have fixed stale values, but should be harmless. */
3701
3702	/* Cpuid 0xc0000003: Reserved.
3703	* We zero this since we don't know what it may have been used for.
3704	*/
3705	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3706
3707	/* Cpuid 0xc0000004: Centaur Performance Info.
3708	* We only have fixed stale values, but should be harmless. */
3709
3710
3711	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3712	* We don't know these and what they mean, so remove them. */
3713	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3714	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3715
3716	return VINF_SUCCESS;
3717	#undef PORTABLE_DISABLE_FEATURE_BIT
3718	#undef PORTABLE_CLEAR_BITS_WHEN
3719	}
3720
3721
3722	/**
3723	* Reads a value in /CPUM/IsaExts/ node.
3724	*
3725	* @returns VBox status code (error message raised).
3726	* @param pVM The cross context VM structure. (For errors.)
3727	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3728	* @param pszValueName The value / extension name.
3729	* @param penmValue Where to return the choice.
3730	* @param enmDefault The default choice.
3731	*/
3732	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3733	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3734	{
3735	/*
3736	* Try integer encoding first.
3737	*/
3738	uint64_t uValue;
3739	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3740	if (RT_SUCCESS(rc))
3741	switch (uValue)
3742	{
3743	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3744	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3745	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3746	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3747	default:
3748	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3749	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3750	pszValueName, uValue);
3751	}
3752	/*
3753	* If missing, use default.
3754	*/
3755	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3756	*penmValue = enmDefault;
3757	else
3758	{
3759	if (rc == VERR_CFGM_NOT_INTEGER)
3760	{
3761	/*
3762	* Not an integer, try read it as a string.
3763	*/
3764	char szValue[32];
3765	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3766	if (RT_SUCCESS(rc))
3767	{
3768	RTStrToLower(szValue);
3769	size_t cchValue = strlen(szValue);
3770	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3771	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3772	*penmValue = CPUMISAEXTCFG_DISABLED;
3773	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3774	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3775	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3776	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3777	else if (EQ("portable"))
3778	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3779	else if (EQ("default") \|\| EQ("def"))
3780	*penmValue = enmDefault;
3781	else
3782	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3783	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3784	pszValueName, uValue);
3785	#undef EQ
3786	}
3787	}
3788	if (RT_FAILURE(rc))
3789	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3790	}
3791	return VINF_SUCCESS;
3792	}
3793
3794
3795	/**
3796	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3797	*
3798	* @returns VBox status code (error message raised).
3799	* @param pVM The cross context VM structure. (For errors.)
3800	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3801	* @param pszValueName The value / extension name.
3802	* @param penmValue Where to return the choice.
3803	* @param enmDefault The default choice.
3804	* @param fAllowed Allowed choice. Applied both to the result and to
3805	* the default value.
3806	*/
3807	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3808	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3809	{
3810	int rc;
3811	if (fAllowed)
3812	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3813	else
3814	{
3815	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3816	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3817	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3818	*penmValue = CPUMISAEXTCFG_DISABLED;
3819	}
3820	return rc;
3821	}
3822
3823
3824	/**
3825	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3826	*
3827	* @returns VBox status code (error message raised).
3828	* @param pVM The cross context VM structure. (For errors.)
3829	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3830	* @param pCpumCfg The /CPUM node (can be NULL).
3831	* @param pszValueName The value / extension name.
3832	* @param penmValue Where to return the choice.
3833	* @param enmDefault The default choice.
3834	*/
3835	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3836	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3837	{
3838	if (CFGMR3Exists(pCpumCfg, pszValueName))
3839	{
3840	if (!CFGMR3Exists(pIsaExts, pszValueName))
3841	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3842	else
3843	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3844	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3845	pszValueName, pszValueName);
3846
3847	bool fLegacy;
3848	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3849	if (RT_SUCCESS(rc))
3850	{
3851	*penmValue = fLegacy;
3852	return VINF_SUCCESS;
3853	}
3854	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3855	}
3856
3857	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3858	}
3859
3860
3861	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3862	{
3863	int rc;
3864
3865	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3866	* When non-zero CPUID features that could cause portability issues will be
3867	* stripped. The higher the value the more features gets stripped. Higher
3868	* values should only be used when older CPUs are involved since it may
3869	* harm performance and maybe also cause problems with specific guests. */
3870	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
3871	AssertLogRelRCReturn(rc, rc);
3872
3873	/** @cfgm{/CPUM/GuestCpuName, string}
3874	* The name of the CPU we're to emulate. The default is the host CPU.
3875	* Note! CPUs other than "host" one is currently unsupported. */
3876	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3877	AssertLogRelRCReturn(rc, rc);
3878
3879	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3880	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3881	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3882	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3883	*/
3884	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3885	AssertLogRelRCReturn(rc, rc);
3886
3887	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
3888	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
3889	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
3890	* 64-bit linux guests which assume the presence of AMD performance counters
3891	* that we do not virtualize.
3892	*/
3893	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
3894	AssertLogRelRCReturn(rc, rc);
3895
3896	/** @cfgm{/CPUM/ForceVme, boolean, false}
3897	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
3898	* By default the flag is passed thru as is from the host CPU, except
3899	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
3900	* guests and DOS boxes in general.
3901	*/
3902	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
3903	AssertLogRelRCReturn(rc, rc);
3904
3905	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3906	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
3907	* probably going to be a temporary hack, so don't depend on this.
3908	* The 1st byte of the value is the stepping, the 2nd byte value is the model
3909	* number and the 3rd byte value is the family, and the 4th value must be zero.
3910	*/
3911	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3912	AssertLogRelRCReturn(rc, rc);
3913
3914	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3915	* The last standard leaf to keep. The actual last value that is stored in EAX
3916	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3917	* removed. (This works independently of and differently from NT4LeafLimit.)
3918	* The default is usually set to what we're able to reasonably sanitize.
3919	*/
3920	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3921	AssertLogRelRCReturn(rc, rc);
3922
3923	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3924	* The last extended leaf to keep. The actual last value that is stored in EAX
3925	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3926	* leaf are removed. The default is set to what we're able to sanitize.
3927	*/
3928	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3929	AssertLogRelRCReturn(rc, rc);
3930
3931	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3932	* The last extended leaf to keep. The actual last value that is stored in EAX
3933	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3934	* leaf are removed. The default is set to what we're able to sanitize.
3935	*/
3936	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3937	AssertLogRelRCReturn(rc, rc);
3938
3939	bool fQueryNestedHwvirt = false;
3940	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3941	fQueryNestedHwvirt \|= RT_BOOL(pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD);
3942	#endif
3943	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3944	fQueryNestedHwvirt \|= RT_BOOL( pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
3945	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA);
3946	#endif
3947	if (fQueryNestedHwvirt)
3948	{
3949	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
3950	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
3951	* The default is false, and when enabled requires nested paging and AMD-V or
3952	* unrestricted guest mode.
3953	*/
3954	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
3955	AssertLogRelRCReturn(rc, rc);
3956	if ( pConfig->fNestedHWVirt
3957	&& !fNestedPagingAndFullGuestExec)
3958	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
3959	"Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
3960
3961	/** @todo Think about enabling this later with NEM/KVM. */
3962	if ( pConfig->fNestedHWVirt
3963	&& VM_IS_NEM_ENABLED(pVM))
3964	{
3965	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
3966	pConfig->fNestedHWVirt = false;
3967	}
3968	}
3969
3970	/*
3971	* Instruction Set Architecture (ISA) Extensions.
3972	*/
3973	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3974	if (pIsaExts)
3975	{
3976	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3977	"CMPXCHG16B"
3978	"\|MONITOR"
3979	"\|MWaitExtensions"
3980	"\|SSE4.1"
3981	"\|SSE4.2"
3982	"\|XSAVE"
3983	"\|AVX"
3984	"\|AVX2"
3985	"\|AESNI"
3986	"\|PCLMUL"
3987	"\|POPCNT"
3988	"\|MOVBE"
3989	"\|RDRAND"
3990	"\|RDSEED"
3991	"\|CLFLUSHOPT"
3992	"\|FSGSBASE"
3993	"\|PCID"
3994	"\|INVPCID"
3995	"\|ABM"
3996	"\|SSE4A"
3997	"\|MISALNSSE"
3998	"\|3DNOWPRF"
3999	"\|AXMMX"
4000	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
4001	if (RT_FAILURE(rc))
4002	return rc;
4003	}
4004
4005	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
4006	* Expose CMPXCHG16B to the guest if supported by the host. For the time
4007	* being the default is to only do this for VMs with nested paging and AMD-V or
4008	* unrestricted guest mode.
4009	*/
4010	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
4011	AssertLogRelRCReturn(rc, rc);
4012
4013	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4014	* Expose MONITOR/MWAIT instructions to the guest.
4015	*/
4016	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4017	AssertLogRelRCReturn(rc, rc);
4018
4019	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4020	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4021	* break on interrupt feature (bit 1).
4022	*/
4023	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4024	AssertLogRelRCReturn(rc, rc);
4025
4026	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4027	* Expose SSE4.1 to the guest if available.
4028	*/
4029	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4030	AssertLogRelRCReturn(rc, rc);
4031
4032	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4033	* Expose SSE4.2 to the guest if available.
4034	*/
4035	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4036	AssertLogRelRCReturn(rc, rc);
4037
4038	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4039	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4040	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
4041	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
4042	&& ( !HMIsLongModeAllowed(pVM)
4043	\|\| NEMHCIsLongModeAllowed(pVM))
4044	#endif
4045	;
4046	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4047
4048	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4049	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4050	* default is to only expose this to VMs with nested paging and AMD-V or
4051	* unrestricted guest execution mode. Not possible to force this one without
4052	* host support at the moment.
4053	*/
4054	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4055	fMayHaveXSave /fAllowed/);
4056	AssertLogRelRCReturn(rc, rc);
4057
4058	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4059	* Expose the AVX instruction set extensions to the guest if available and
4060	* XSAVE is exposed too. For the time being the default is to only expose this
4061	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4062	*/
4063	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4064	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4065	AssertLogRelRCReturn(rc, rc);
4066
4067	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4068	* Expose the AVX2 instruction set extensions to the guest if available and
4069	* XSAVE is exposed too. For the time being the default is to only expose this
4070	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4071	*/
4072	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4073	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4074	AssertLogRelRCReturn(rc, rc);
4075
4076	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4077	* Whether to expose the AES instructions to the guest. For the time being the
4078	* default is to only do this for VMs with nested paging and AMD-V or
4079	* unrestricted guest mode.
4080	*/
4081	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4082	AssertLogRelRCReturn(rc, rc);
4083
4084	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4085	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4086	* being the default is to only do this for VMs with nested paging and AMD-V or
4087	* unrestricted guest mode.
4088	*/
4089	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4090	AssertLogRelRCReturn(rc, rc);
4091
4092	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4093	* Whether to expose the POPCNT instructions to the guest. For the time
4094	* being the default is to only do this for VMs with nested paging and AMD-V or
4095	* unrestricted guest mode.
4096	*/
4097	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4098	AssertLogRelRCReturn(rc, rc);
4099
4100	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4101	* Whether to expose the MOVBE instructions to the guest. For the time
4102	* being the default is to only do this for VMs with nested paging and AMD-V or
4103	* unrestricted guest mode.
4104	*/
4105	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4106	AssertLogRelRCReturn(rc, rc);
4107
4108	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4109	* Whether to expose the RDRAND instructions to the guest. For the time being
4110	* the default is to only do this for VMs with nested paging and AMD-V or
4111	* unrestricted guest mode.
4112	*/
4113	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4114	AssertLogRelRCReturn(rc, rc);
4115
4116	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4117	* Whether to expose the RDSEED instructions to the guest. For the time being
4118	* the default is to only do this for VMs with nested paging and AMD-V or
4119	* unrestricted guest mode.
4120	*/
4121	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4122	AssertLogRelRCReturn(rc, rc);
4123
4124	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4125	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4126	* being the default is to only do this for VMs with nested paging and AMD-V or
4127	* unrestricted guest mode.
4128	*/
4129	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4130	AssertLogRelRCReturn(rc, rc);
4131
4132	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4133	* Whether to expose the read/write FSGSBASE instructions to the guest.
4134	*/
4135	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4136	AssertLogRelRCReturn(rc, rc);
4137
4138	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4139	* Whether to expose the PCID feature to the guest.
4140	*/
4141	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4142	AssertLogRelRCReturn(rc, rc);
4143
4144	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4145	* Whether to expose the INVPCID instruction to the guest.
4146	*/
4147	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4148	AssertLogRelRCReturn(rc, rc);
4149
4150
4151	/* AMD: */
4152
4153	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4154	* Whether to expose the AMD ABM instructions to the guest. For the time
4155	* being the default is to only do this for VMs with nested paging and AMD-V or
4156	* unrestricted guest mode.
4157	*/
4158	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4159	AssertLogRelRCReturn(rc, rc);
4160
4161	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4162	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4163	* being the default is to only do this for VMs with nested paging and AMD-V or
4164	* unrestricted guest mode.
4165	*/
4166	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4167	AssertLogRelRCReturn(rc, rc);
4168
4169	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4170	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4171	* the time being the default is to only do this for VMs with nested paging and
4172	* AMD-V or unrestricted guest mode.
4173	*/
4174	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4175	AssertLogRelRCReturn(rc, rc);
4176
4177	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4178	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4179	* For the time being the default is to only do this for VMs with nested paging
4180	* and AMD-V or unrestricted guest mode.
4181	*/
4182	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4183	AssertLogRelRCReturn(rc, rc);
4184
4185	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4186	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4187	* the default is to only do this for VMs with nested paging and AMD-V or
4188	* unrestricted guest mode.
4189	*/
4190	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4191	AssertLogRelRCReturn(rc, rc);
4192
4193	return VINF_SUCCESS;
4194	}
4195
4196
4197	/**
4198	* Initializes the emulated CPU's CPUID & MSR information.
4199	*
4200	* @returns VBox status code.
4201	* @param pVM The cross context VM structure.
4202	*/
4203	int cpumR3InitCpuIdAndMsrs(PVM pVM)
4204	{
4205	PCPUM pCpum = &pVM->cpum.s;
4206	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4207
4208	/*
4209	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4210	* on construction and manage everything from here on.
4211	*/
4212	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
4213	pVM->aCpus[iCpu].cpum.s.fCpuIdApicFeatureVisible = true;
4214
4215	/*
4216	* Read the configuration.
4217	*/
4218	CPUMCPUIDCONFIG Config;
4219	RT_ZERO(Config);
4220
4221	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4222	AssertRCReturn(rc, rc);
4223
4224	/*
4225	* Get the guest CPU data from the database and/or the host.
4226	*
4227	* The CPUID and MSRs are currently living on the regular heap to avoid
4228	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4229	* API for the hyper heap). This means special cleanup considerations.
4230	*/
4231	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4232	if (RT_FAILURE(rc))
4233	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4234	? VMSetError(pVM, rc, RT_SRC_POS,
4235	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4236	: rc;
4237
4238	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4239	{
4240	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4241	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4242	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4243	}
4244	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4245
4246	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4247	* Overrides the guest MSRs.
4248	*/
4249	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4250
4251	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4252	* Overrides the CPUID leaf values (from the host CPU usually) used for
4253	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4254	* values when moving a VM to a different machine. Another use is restricting
4255	* (or extending) the feature set exposed to the guest. */
4256	if (RT_SUCCESS(rc))
4257	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4258
4259	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4260	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4261	"Found unsupported configuration node '/CPUM/CPUID/'. "
4262	"Please use IMachine::setCPUIDLeaf() instead.");
4263
4264	/*
4265	* Pre-explode the CPUID info.
4266	*/
4267	if (RT_SUCCESS(rc))
4268	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
4269
4270	/*
4271	* Sanitize the cpuid information passed on to the guest.
4272	*/
4273	if (RT_SUCCESS(rc))
4274	{
4275	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4276	if (RT_SUCCESS(rc))
4277	{
4278	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4279	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4280	}
4281	}
4282
4283	/*
4284	* MSR fudging.
4285	*/
4286	if (RT_SUCCESS(rc))
4287	{
4288	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4289	* Fudges some common MSRs if not present in the selected CPU database entry.
4290	* This is for trying to keep VMs running when moved between different hosts
4291	* and different CPU vendors. */
4292	bool fEnable;
4293	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4294	if (RT_SUCCESS(rc) && fEnable)
4295	{
4296	rc = cpumR3MsrApplyFudge(pVM);
4297	AssertLogRelRC(rc);
4298	}
4299	}
4300	if (RT_SUCCESS(rc))
4301	{
4302	/*
4303	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4304	* guest CPU features again.
4305	*/
4306	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4307	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4308	pCpum->GuestInfo.cCpuIdLeaves);
4309	RTMemFree(pvFree);
4310
4311	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4312	int rc2 = MMHyperDupMem(pVM, pvFree,
4313	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4314	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4315	RTMemFree(pvFree);
4316	AssertLogRelRCReturn(rc1, rc1);
4317	AssertLogRelRCReturn(rc2, rc2);
4318
4319	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4320	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4321
4322
4323	/*
4324	* Some more configuration that we're applying at the end of everything
4325	* via the CPUMSetGuestCpuIdFeature API.
4326	*/
4327
4328	/* Check if PAE was explicitely enabled by the user. */
4329	bool fEnable;
4330	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4331	AssertRCReturn(rc, rc);
4332	if (fEnable)
4333	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4334
4335	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4336	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4337	AssertRCReturn(rc, rc);
4338	if (fEnable)
4339	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4340
4341	/* Check if speculation control is enabled. */
4342	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4343	AssertRCReturn(rc, rc);
4344	if (fEnable)
4345	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4346
4347	return VINF_SUCCESS;
4348	}
4349
4350	/*
4351	* Failed before switching to hyper heap.
4352	*/
4353	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4354	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4355	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4356	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4357	return rc;
4358	}
4359
4360
4361	/**
4362	* Sets a CPUID feature bit during VM initialization.
4363	*
4364	* Since the CPUID feature bits are generally related to CPU features, other
4365	* CPUM configuration like MSRs can also be modified by calls to this API.
4366	*
4367	* @param pVM The cross context VM structure.
4368	* @param enmFeature The feature to set.
4369	*/
4370	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4371	{
4372	PCPUMCPUIDLEAF pLeaf;
4373	PCPUMMSRRANGE pMsrRange;
4374
4375	switch (enmFeature)
4376	{
4377	/*
4378	* Set the APIC bit in both feature masks.
4379	*/
4380	case CPUMCPUIDFEATURE_APIC:
4381	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4382	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4383	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4384
4385	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4386	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4387	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4388
4389	pVM->cpum.s.GuestFeatures.fApic = 1;
4390
4391	/* Make sure we've got the APICBASE MSR present. */
4392	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4393	if (!pMsrRange)
4394	{
4395	static CPUMMSRRANGE const s_ApicBase =
4396	{
4397	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4398	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4399	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4400	/.szName = / "IA32_APIC_BASE"
4401	};
4402	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4403	AssertLogRelRC(rc);
4404	}
4405
4406	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4407	break;
4408
4409	/*
4410	* Set the x2APIC bit in the standard feature mask.
4411	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4412	*/
4413	case CPUMCPUIDFEATURE_X2APIC:
4414	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4415	if (pLeaf)
4416	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4417	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4418
4419	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4420	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4421	if (pMsrRange)
4422	{
4423	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4424	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4425	}
4426
4427	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4428	break;
4429
4430	/*
4431	* Set the sysenter/sysexit bit in the standard feature mask.
4432	* Assumes the caller knows what it's doing! (host must support these)
4433	*/
4434	case CPUMCPUIDFEATURE_SEP:
4435	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4436	{
4437	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4438	return;
4439	}
4440
4441	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4442	if (pLeaf)
4443	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4444	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4445	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4446	break;
4447
4448	/*
4449	* Set the syscall/sysret bit in the extended feature mask.
4450	* Assumes the caller knows what it's doing! (host must support these)
4451	*/
4452	case CPUMCPUIDFEATURE_SYSCALL:
4453	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4454	if ( !pLeaf
4455	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4456	{
4457	#if HC_ARCH_BITS == 32
4458	/* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit
4459	mode by Intel, even when the cpu is capable of doing so in
4460	64-bit mode. Long mode requires syscall support. */
4461	if (!pVM->cpum.s.HostFeatures.fLongMode)
4462	#endif
4463	{
4464	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4465	return;
4466	}
4467	}
4468
4469	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4470	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4471	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4472	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4473	break;
4474
4475	/*
4476	* Set the PAE bit in both feature masks.
4477	* Assumes the caller knows what it's doing! (host must support these)
4478	*/
4479	case CPUMCPUIDFEATURE_PAE:
4480	if (!pVM->cpum.s.HostFeatures.fPae)
4481	{
4482	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4483	return;
4484	}
4485
4486	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4487	if (pLeaf)
4488	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4489
4490	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4491	if ( pLeaf
4492	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4493	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4494
4495	pVM->cpum.s.GuestFeatures.fPae = 1;
4496	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4497	break;
4498
4499	/*
4500	* Set the LONG MODE bit in the extended feature mask.
4501	* Assumes the caller knows what it's doing! (host must support these)
4502	*/
4503	case CPUMCPUIDFEATURE_LONG_MODE:
4504	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4505	if ( !pLeaf
4506	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4507	{
4508	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4509	return;
4510	}
4511
4512	/* Valid for both Intel and AMD. */
4513	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4514	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4515	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4516	break;
4517
4518	/*
4519	* Set the NX/XD bit in the extended feature mask.
4520	* Assumes the caller knows what it's doing! (host must support these)
4521	*/
4522	case CPUMCPUIDFEATURE_NX:
4523	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4524	if ( !pLeaf
4525	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4526	{
4527	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4528	return;
4529	}
4530
4531	/* Valid for both Intel and AMD. */
4532	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4533	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4534	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4535	break;
4536
4537
4538	/*
4539	* Set the LAHF/SAHF support in 64-bit mode.
4540	* Assumes the caller knows what it's doing! (host must support this)
4541	*/
4542	case CPUMCPUIDFEATURE_LAHF:
4543	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4544	if ( !pLeaf
4545	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4546	{
4547	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4548	return;
4549	}
4550
4551	/* Valid for both Intel and AMD. */
4552	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4553	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4554	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4555	break;
4556
4557	/*
4558	* Set the page attribute table bit. This is alternative page level
4559	* cache control that doesn't much matter when everything is
4560	* virtualized, though it may when passing thru device memory.
4561	*/
4562	case CPUMCPUIDFEATURE_PAT:
4563	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4564	if (pLeaf)
4565	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4566
4567	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4568	if ( pLeaf
4569	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4570	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4571
4572	pVM->cpum.s.GuestFeatures.fPat = 1;
4573	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4574	break;
4575
4576	/*
4577	* Set the RDTSCP support bit.
4578	* Assumes the caller knows what it's doing! (host must support this)
4579	*/
4580	case CPUMCPUIDFEATURE_RDTSCP:
4581	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4582	if ( !pLeaf
4583	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4584	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4585	{
4586	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4587	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4588	return;
4589	}
4590
4591	/* Valid for both Intel and AMD. */
4592	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4593	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4594	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4595	break;
4596
4597	/*
4598	* Set the Hypervisor Present bit in the standard feature mask.
4599	*/
4600	case CPUMCPUIDFEATURE_HVP:
4601	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4602	if (pLeaf)
4603	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4604	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4605	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4606	break;
4607
4608	/*
4609	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4610	* This currently includes the Present bit and MWAITBREAK bit as well.
4611	*/
4612	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4613	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4614	if ( !pLeaf
4615	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4616	{
4617	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4618	return;
4619	}
4620
4621	/* Valid for both Intel and AMD. */
4622	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4623	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4624	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4625	break;
4626
4627	/*
4628	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
4629	* on Intel CPUs, and different on AMDs.
4630	*/
4631	case CPUMCPUIDFEATURE_SPEC_CTRL:
4632	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4633	{
4634	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4635	if ( !pLeaf
4636	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
4637	{
4638	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4639	return;
4640	}
4641
4642	/* The feature can be enabled. Let's see what we can actually do. */
4643	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4644
4645	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4646	if (pVM->cpum.s.HostFeatures.fIbrs)
4647	{
4648	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4649	pVM->cpum.s.GuestFeatures.fIbrs = 1;
4650	if (pVM->cpum.s.HostFeatures.fStibp)
4651	{
4652	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4653	pVM->cpum.s.GuestFeatures.fStibp = 1;
4654	}
4655
4656	/* Make sure we have the speculation control MSR... */
4657	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4658	if (!pMsrRange)
4659	{
4660	static CPUMMSRRANGE const s_SpecCtrl =
4661	{
4662	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
4663	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
4664	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4665	/.szName = / "IA32_SPEC_CTRL"
4666	};
4667	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4668	AssertLogRelRC(rc);
4669	}
4670
4671	/* ... and the predictor command MSR. */
4672	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
4673	if (!pMsrRange)
4674	{
4675	static CPUMMSRRANGE const s_SpecCtrl =
4676	{
4677	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
4678	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
4679	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4680	/.szName = / "IA32_PRED_CMD"
4681	};
4682	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4683	AssertLogRelRC(rc);
4684	}
4685
4686	}
4687
4688	if (pVM->cpum.s.HostFeatures.fArchCap) {
4689	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
4690
4691	/* Install the architectural capabilities MSR. */
4692	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
4693	if (!pMsrRange)
4694	{
4695	static CPUMMSRRANGE const s_ArchCaps =
4696	{
4697	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
4698	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
4699	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
4700	/.szName = / "IA32_ARCH_CAPABILITIES"
4701	};
4702	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
4703	AssertLogRelRC(rc);
4704	}
4705	}
4706
4707	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
4708	}
4709	else if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4710	{
4711	/* The precise details of AMD's implementation are not yet clear. */
4712	}
4713	break;
4714
4715	default:
4716	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4717	break;
4718	}
4719
4720	/** @todo can probably kill this as this API is now init time only... */
4721	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4722	{
4723	PVMCPU pVCpu = &pVM->aCpus[i];
4724	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4725	}
4726	}
4727
4728
4729	/**
4730	* Queries a CPUID feature bit.
4731	*
4732	* @returns boolean for feature presence
4733	* @param pVM The cross context VM structure.
4734	* @param enmFeature The feature to query.
4735	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4736	*/
4737	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4738	{
4739	switch (enmFeature)
4740	{
4741	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4742	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4743	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4744	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4745	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4746	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4747	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4748	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4749	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4750	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4751	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4752	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4753	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
4754
4755	case CPUMCPUIDFEATURE_INVALID:
4756	case CPUMCPUIDFEATURE_32BIT_HACK:
4757	break;
4758	}
4759	AssertFailed();
4760	return false;
4761	}
4762
4763
4764	/**
4765	* Clears a CPUID feature bit.
4766	*
4767	* @param pVM The cross context VM structure.
4768	* @param enmFeature The feature to clear.
4769	*
4770	* @deprecated Probably better to default the feature to disabled and only allow
4771	* setting (enabling) it during construction.
4772	*/
4773	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4774	{
4775	PCPUMCPUIDLEAF pLeaf;
4776	switch (enmFeature)
4777	{
4778	case CPUMCPUIDFEATURE_APIC:
4779	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
4780	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4781	if (pLeaf)
4782	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
4783
4784	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4785	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4786	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4787
4788	pVM->cpum.s.GuestFeatures.fApic = 0;
4789	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4790	break;
4791
4792	case CPUMCPUIDFEATURE_X2APIC:
4793	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4794	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4795	if (pLeaf)
4796	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
4797	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
4798	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
4799	break;
4800
4801	case CPUMCPUIDFEATURE_PAE:
4802	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4803	if (pLeaf)
4804	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
4805
4806	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4807	if ( pLeaf
4808	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4809	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
4810
4811	pVM->cpum.s.GuestFeatures.fPae = 0;
4812	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
4813	break;
4814
4815	case CPUMCPUIDFEATURE_PAT:
4816	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4817	if (pLeaf)
4818	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
4819
4820	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4821	if ( pLeaf
4822	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4823	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
4824
4825	pVM->cpum.s.GuestFeatures.fPat = 0;
4826	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
4827	break;
4828
4829	case CPUMCPUIDFEATURE_LONG_MODE:
4830	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4831	if (pLeaf)
4832	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4833	pVM->cpum.s.GuestFeatures.fLongMode = 0;
4834	break;
4835
4836	case CPUMCPUIDFEATURE_LAHF:
4837	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4838	if (pLeaf)
4839	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4840	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
4841	break;
4842
4843	case CPUMCPUIDFEATURE_RDTSCP:
4844	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4845	if (pLeaf)
4846	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4847	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
4848	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
4849	break;
4850
4851	case CPUMCPUIDFEATURE_HVP:
4852	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4853	if (pLeaf)
4854	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
4855	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
4856	break;
4857
4858	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4859	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4860	if (pLeaf)
4861	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
4862	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
4863	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
4864	break;
4865
4866	case CPUMCPUIDFEATURE_SPEC_CTRL:
4867	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4868	if (pLeaf)
4869	/pVM->cpum.s.aGuestCpuIdPatmStd[7].uEdx =/ pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP \| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
4870	pVM->cpum.s.GuestFeatures.fSpeculationControl = 0;
4871	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
4872	break;
4873
4874	default:
4875	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4876	break;
4877	}
4878
4879	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4880	{
4881	PVMCPU pVCpu = &pVM->aCpus[i];
4882	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4883	}
4884	}
4885
4886
4887
4888	/*
4889	*
4890	*
4891	* Saved state related code.
4892	* Saved state related code.
4893	* Saved state related code.
4894	*
4895	*
4896	*/
4897
4898	/**
4899	* Called both in pass 0 and the final pass.
4900	*
4901	* @param pVM The cross context VM structure.
4902	* @param pSSM The saved state handle.
4903	*/
4904	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4905	{
4906	/*
4907	* Save all the CPU ID leaves.
4908	*/
4909	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4910	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4911	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4912	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4913
4914	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4915
4916	/*
4917	* Save a good portion of the raw CPU IDs as well as they may come in
4918	* handy when validating features for raw mode.
4919	*/
4920	CPUMCPUID aRawStd[16];
4921	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4922	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4923	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4924	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4925
4926	CPUMCPUID aRawExt[32];
4927	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4928	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4929	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4930	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4931	}
4932
4933
4934	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4935	{
4936	uint32_t cCpuIds;
4937	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4938	if (RT_SUCCESS(rc))
4939	{
4940	if (cCpuIds < 64)
4941	{
4942	for (uint32_t i = 0; i < cCpuIds; i++)
4943	{
4944	CPUMCPUID CpuId;
4945	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4946	if (RT_FAILURE(rc))
4947	break;
4948
4949	CPUMCPUIDLEAF NewLeaf;
4950	NewLeaf.uLeaf = uBase + i;
4951	NewLeaf.uSubLeaf = 0;
4952	NewLeaf.fSubLeafMask = 0;
4953	NewLeaf.uEax = CpuId.uEax;
4954	NewLeaf.uEbx = CpuId.uEbx;
4955	NewLeaf.uEcx = CpuId.uEcx;
4956	NewLeaf.uEdx = CpuId.uEdx;
4957	NewLeaf.fFlags = 0;
4958	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4959	}
4960	}
4961	else
4962	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4963	}
4964	if (RT_FAILURE(rc))
4965	{
4966	RTMemFree(*ppaLeaves);
4967	*ppaLeaves = NULL;
4968	*pcLeaves = 0;
4969	}
4970	return rc;
4971	}
4972
4973
4974	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4975	{
4976	*ppaLeaves = NULL;
4977	*pcLeaves = 0;
4978
4979	int rc;
4980	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4981	{
4982	/*
4983	* The new format. Starts by declaring the leave size and count.
4984	*/
4985	uint32_t cbLeaf;
4986	SSMR3GetU32(pSSM, &cbLeaf);
4987	uint32_t cLeaves;
4988	rc = SSMR3GetU32(pSSM, &cLeaves);
4989	if (RT_SUCCESS(rc))
4990	{
4991	if (cbLeaf == sizeof(**ppaLeaves))
4992	{
4993	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4994	{
4995	/*
4996	* Load the leaves one by one.
4997	*
4998	* The uPrev stuff is a kludge for working around a week worth of bad saved
4999	* states during the CPUID revamp in March 2015. We saved too many leaves
5000	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
5001	* garbage entires at the end of the array when restoring. We also had
5002	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
5003	* this kludge doesn't deal correctly with that, but who cares...
5004	*/
5005	uint32_t uPrev = 0;
5006	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
5007	{
5008	CPUMCPUIDLEAF Leaf;
5009	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5010	if (RT_SUCCESS(rc))
5011	{
5012	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5013	\|\| Leaf.uLeaf >= uPrev)
5014	{
5015	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5016	uPrev = Leaf.uLeaf;
5017	}
5018	else
5019	uPrev = UINT32_MAX;
5020	}
5021	}
5022	}
5023	else
5024	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5025	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5026	}
5027	else
5028	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5029	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5030	}
5031	}
5032	else
5033	{
5034	/*
5035	* The old format with its three inflexible arrays.
5036	*/
5037	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5038	if (RT_SUCCESS(rc))
5039	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5040	if (RT_SUCCESS(rc))
5041	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5042	if (RT_SUCCESS(rc))
5043	{
5044	/*
5045	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5046	*/
5047	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5048	if ( pLeaf
5049	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5050	{
5051	CPUMCPUIDLEAF Leaf;
5052	Leaf.uLeaf = 4;
5053	Leaf.fSubLeafMask = UINT32_MAX;
5054	Leaf.uSubLeaf = 0;
5055	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5056	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5057	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5058	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5059	\| UINT32_C(63); /* system coherency line size - 1 */
5060	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5061	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5062	\| (UINT32_C(1) << 5) /* cache level */
5063	\| UINT32_C(1); /* cache type (data) */
5064	Leaf.fFlags = 0;
5065	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5066	if (RT_SUCCESS(rc))
5067	{
5068	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5069	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5070	}
5071	if (RT_SUCCESS(rc))
5072	{
5073	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5074	Leaf.uEcx = 4095; /* sets - 1 */
5075	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5076	Leaf.uEbx \|= UINT32_C(23) << 22;
5077	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5078	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5079	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5080	Leaf.uEax \|= UINT32_C(2) << 5;
5081	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5082	}
5083	}
5084	}
5085	}
5086	return rc;
5087	}
5088
5089
5090	/**
5091	* Loads the CPU ID leaves saved by pass 0, inner worker.
5092	*
5093	* @returns VBox status code.
5094	* @param pVM The cross context VM structure.
5095	* @param pSSM The saved state handle.
5096	* @param uVersion The format version.
5097	* @param paLeaves Guest CPUID leaves loaded from the state.
5098	* @param cLeaves The number of leaves in @a paLeaves.
5099	*/
5100	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
5101	{
5102	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5103
5104	/*
5105	* Continue loading the state into stack buffers.
5106	*/
5107	CPUMCPUID GuestDefCpuId;
5108	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5109	AssertRCReturn(rc, rc);
5110
5111	CPUMCPUID aRawStd[16];
5112	uint32_t cRawStd;
5113	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5114	if (cRawStd > RT_ELEMENTS(aRawStd))
5115	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5116	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5117	AssertRCReturn(rc, rc);
5118	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5119	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5120
5121	CPUMCPUID aRawExt[32];
5122	uint32_t cRawExt;
5123	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5124	if (cRawExt > RT_ELEMENTS(aRawExt))
5125	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5126	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5127	AssertRCReturn(rc, rc);
5128	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5129	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5130
5131	/*
5132	* Get the raw CPU IDs for the current host.
5133	*/
5134	CPUMCPUID aHostRawStd[16];
5135	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5136	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5137
5138	CPUMCPUID aHostRawExt[32];
5139	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5140	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5141	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5142
5143	/*
5144	* Get the host and guest overrides so we don't reject the state because
5145	* some feature was enabled thru these interfaces.
5146	* Note! We currently only need the feature leaves, so skip rest.
5147	*/
5148	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5149	CPUMCPUID aHostOverrideStd[2];
5150	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5151	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5152
5153	CPUMCPUID aHostOverrideExt[2];
5154	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5155	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5156
5157	/*
5158	* This can be skipped.
5159	*/
5160	bool fStrictCpuIdChecks;
5161	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5162
5163	/*
5164	* Define a bunch of macros for simplifying the santizing/checking code below.
5165	*/
5166	/* Generic expression + failure message. */
5167	#define CPUID_CHECK_RET(expr, fmt) \
5168	do { \
5169	if (!(expr)) \
5170	{ \
5171	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5172	if (fStrictCpuIdChecks) \
5173	{ \
5174	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5175	RTStrFree(pszMsg); \
5176	return rcCpuid; \
5177	} \
5178	LogRel(("CPUM: %s\n", pszMsg)); \
5179	RTStrFree(pszMsg); \
5180	} \
5181	} while (0)
5182	#define CPUID_CHECK_WRN(expr, fmt) \
5183	do { \
5184	if (!(expr)) \
5185	LogRel(fmt); \
5186	} while (0)
5187
5188	/* For comparing two values and bitch if they differs. */
5189	#define CPUID_CHECK2_RET(what, host, saved) \
5190	do { \
5191	if ((host) != (saved)) \
5192	{ \
5193	if (fStrictCpuIdChecks) \
5194	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5195	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5196	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5197	} \
5198	} while (0)
5199	#define CPUID_CHECK2_WRN(what, host, saved) \
5200	do { \
5201	if ((host) != (saved)) \
5202	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5203	} while (0)
5204
5205	/* For checking raw cpu features (raw mode). */
5206	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5207	do { \
5208	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5209	{ \
5210	if (fStrictCpuIdChecks) \
5211	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5212	N_(#bit " mismatch: host=%d saved=%d"), \
5213	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5214	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5215	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5216	} \
5217	} while (0)
5218	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5219	do { \
5220	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5221	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5222	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5223	} while (0)
5224	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5225
5226	/* For checking guest features. */
5227	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5228	do { \
5229	if ( (aGuestCpuId##set [1].reg & bit) \
5230	&& !(aHostRaw##set [1].reg & bit) \
5231	&& !(aHostOverride##set [1].reg & bit) \
5232	) \
5233	{ \
5234	if (fStrictCpuIdChecks) \
5235	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5236	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5237	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5238	} \
5239	} while (0)
5240	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5241	do { \
5242	if ( (aGuestCpuId##set [1].reg & bit) \
5243	&& !(aHostRaw##set [1].reg & bit) \
5244	&& !(aHostOverride##set [1].reg & bit) \
5245	) \
5246	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5247	} while (0)
5248	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5249	do { \
5250	if ( (aGuestCpuId##set [1].reg & bit) \
5251	&& !(aHostRaw##set [1].reg & bit) \
5252	&& !(aHostOverride##set [1].reg & bit) \
5253	) \
5254	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5255	} while (0)
5256	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5257
5258	/* For checking guest features if AMD guest CPU. */
5259	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5260	do { \
5261	if ( (aGuestCpuId##set [1].reg & bit) \
5262	&& fGuestAmd \
5263	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5264	&& !(aHostOverride##set [1].reg & bit) \
5265	) \
5266	{ \
5267	if (fStrictCpuIdChecks) \
5268	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5269	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5270	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5271	} \
5272	} while (0)
5273	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5274	do { \
5275	if ( (aGuestCpuId##set [1].reg & bit) \
5276	&& fGuestAmd \
5277	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5278	&& !(aHostOverride##set [1].reg & bit) \
5279	) \
5280	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5281	} while (0)
5282	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5283	do { \
5284	if ( (aGuestCpuId##set [1].reg & bit) \
5285	&& fGuestAmd \
5286	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5287	&& !(aHostOverride##set [1].reg & bit) \
5288	) \
5289	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5290	} while (0)
5291	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5292
5293	/* For checking AMD features which have a corresponding bit in the standard
5294	range. (Intel defines very few bits in the extended feature sets.) */
5295	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5296	do { \
5297	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5298	&& !(fHostAmd \
5299	? aHostRawExt[1].reg & (ExtBit) \
5300	: aHostRawStd[1].reg & (StdBit)) \
5301	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5302	) \
5303	{ \
5304	if (fStrictCpuIdChecks) \
5305	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5306	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5307	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5308	} \
5309	} while (0)
5310	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5311	do { \
5312	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5313	&& !(fHostAmd \
5314	? aHostRawExt[1].reg & (ExtBit) \
5315	: aHostRawStd[1].reg & (StdBit)) \
5316	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5317	) \
5318	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5319	} while (0)
5320	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5321	do { \
5322	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5323	&& !(fHostAmd \
5324	? aHostRawExt[1].reg & (ExtBit) \
5325	: aHostRawStd[1].reg & (StdBit)) \
5326	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5327	) \
5328	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5329	} while (0)
5330	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5331
5332	/*
5333	* For raw-mode we'll require that the CPUs are very similar since we don't
5334	* intercept CPUID instructions for user mode applications.
5335	*/
5336	if (VM_IS_RAW_MODE_ENABLED(pVM))
5337	{
5338	/* CPUID(0) */
5339	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
5340	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
5341	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
5342	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5343	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
5344	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
5345	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
5346	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
5347	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5348
5349	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
5350
5351	/* CPUID(1).eax */
5352	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
5353	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
5354	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
5355
5356	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
5357	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
5358	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
5359
5360	/* CPUID(1).ecx */
5361	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
5362	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
5363	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
5364	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5365	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
5366	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
5367	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
5368	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
5369	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
5370	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
5371	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
5372	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
5373	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
5374	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
5375	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
5376	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
5377	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5378	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5379	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
5380	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
5381	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
5382	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5383	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
5384	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
5385	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5386	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
5387	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
5388	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5389	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
5390	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5391	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5392	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
5393
5394	/* CPUID(1).edx */
5395	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5396	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5397	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
5398	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5399	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
5400	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
5401	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5402	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5403	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
5404	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5405	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5406	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5407	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5408	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5409	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5410	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
5411	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5412	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5413	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5414	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
5415	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5416	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
5417	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
5418	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
5419	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
5420	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
5421	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
5422	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
5423	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
5424	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
5425	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
5426	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
5427
5428	/* CPUID(2) - config, mostly about caches. ignore. */
5429	/* CPUID(3) - processor serial number. ignore. */
5430	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
5431	/* CPUID(5) - mwait/monitor config. ignore. */
5432	/* CPUID(6) - power management. ignore. */
5433	/* CPUID(7) - ???. ignore. */
5434	/* CPUID(8) - ???. ignore. */
5435	/* CPUID(9) - DCA. ignore for now. */
5436	/* CPUID(a) - PeMo info. ignore for now. */
5437	/* CPUID(b) - topology info - takes ECX as input. ignore. */
5438
5439	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
5440	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
5441	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
5442	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
5443	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
5444	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
5445	{
5446	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
5447	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
5448	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
5449	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
5450	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
5451	}
5452
5453	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
5454	Note! Intel have/is marking many of the fields here as reserved. We
5455	will verify them as if it's an AMD CPU. */
5456	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
5457	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
5458	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
5459	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
5460	{
5461	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
5462	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
5463	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
5464	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5465	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
5466	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
5467	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
5468
5469	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
5470	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
5471	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
5472	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
5473	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
5474	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5475
5476	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
5477	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
5478	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
5479	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
5480
5481	/* CPUID(0x80000001).ecx */
5482	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
5483	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
5484	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
5485	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
5486	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
5487	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
5488	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
5489	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
5490	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
5491	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
5492	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
5493	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
5494	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
5495	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
5496	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5497	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5498	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5499	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5500	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5501	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5502	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5503	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5504	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5505	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5506	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5507	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5508	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5509	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5510	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5511	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5512	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5513	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5514
5515	/* CPUID(0x80000001).edx */
5516	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
5517	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
5518	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
5519	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
5520	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
5521	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
5522	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
5523	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
5524	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
5525	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
5526	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5527	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
5528	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
5529	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
5530	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
5531	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
5532	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
5533	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
5534	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5535	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5536	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5537	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
5538	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5539	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
5540	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
5541	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5542	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5543	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5544	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
5545	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5546	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5547	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5548
5549	/** @todo verify the rest as well. */
5550	}
5551	}
5552
5553
5554
5555	/*
5556	* Verify that we can support the features already exposed to the guest on
5557	* this host.
5558	*
5559	* Most of the features we're emulating requires intercepting instruction
5560	* and doing it the slow way, so there is no need to warn when they aren't
5561	* present in the host CPU. Thus we use IGN instead of EMU on these.
5562	*
5563	* Trailing comments:
5564	* "EMU" - Possible to emulate, could be lots of work and very slow.
5565	* "EMU?" - Can this be emulated?
5566	*/
5567	CPUMCPUID aGuestCpuIdStd[2];
5568	RT_ZERO(aGuestCpuIdStd);
5569	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5570
5571	/* CPUID(1).ecx */
5572	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5573	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5574	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5575	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5576	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5577	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5578	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5579	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5580	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5581	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5582	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5583	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5584	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5585	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5586	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5587	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5588	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5589	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5590	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5591	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5592	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5593	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5594	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5595	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5596	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5597	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5598	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5599	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5600	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5601	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5602	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5603	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5604
5605	/* CPUID(1).edx */
5606	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5607	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5608	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5609	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5610	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5611	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5612	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5613	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5614	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5615	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5616	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5617	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5618	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5619	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5620	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5621	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5622	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5623	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5624	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5625	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5626	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5627	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5628	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5629	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5630	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5631	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5632	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5633	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5634	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5635	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5636	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5637	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5638
5639	/* CPUID(0x80000000). */
5640	CPUMCPUID aGuestCpuIdExt[2];
5641	RT_ZERO(aGuestCpuIdExt);
5642	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5643	{
5644	/** @todo deal with no 0x80000001 on the host. */
5645	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5646	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5647
5648	/* CPUID(0x80000001).ecx */
5649	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5650	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5651	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5652	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5653	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5654	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5655	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5656	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5657	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5658	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5659	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5660	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5661	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5662	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5663	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5664	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5665	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5666	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5667	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5668	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5669	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5670	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5671	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5672	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5673	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5674	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5675	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5676	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5677	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5678	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5679	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5680	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5681
5682	/* CPUID(0x80000001).edx */
5683	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5684	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5685	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5686	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5687	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5688	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5689	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5690	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5691	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5692	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5693	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5694	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5695	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5696	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5697	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5698	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5699	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5700	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5701	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5702	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5703	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5704	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5705	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5706	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5707	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5708	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5709	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5710	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5711	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5712	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5713	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5714	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5715	}
5716
5717	/** @todo check leaf 7 */
5718
5719	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5720	* ECX=0: EAX - Valid bits in XCR0[31:0].
5721	* EBX - Maximum state size as per current XCR0 value.
5722	* ECX - Maximum state size for all supported features.
5723	* EDX - Valid bits in XCR0[63:32].
5724	* ECX=1: EAX - Various X-features.
5725	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5726	* ECX - Valid bits in IA32_XSS[31:0].
5727	* EDX - Valid bits in IA32_XSS[63:32].
5728	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5729	* if the bit invalid all four registers are set to zero.
5730	* EAX - The state size for this feature.
5731	* EBX - The state byte offset of this feature.
5732	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5733	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5734	*/
5735	uint64_t fGuestXcr0Mask = 0;
5736	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5737	if ( pCurLeaf
5738	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5739	&& ( pCurLeaf->uEax
5740	\|\| pCurLeaf->uEbx
5741	\|\| pCurLeaf->uEcx
5742	\|\| pCurLeaf->uEdx) )
5743	{
5744	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5745	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5746	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5747	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5748	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5749	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5750	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5751	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5752
5753	/* We don't support any additional features yet. */
5754	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5755	if (pCurLeaf && pCurLeaf->uEax)
5756	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5757	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5758	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5759	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5760	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5761	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5762
5763
5764	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5765	{
5766	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5767	if (pCurLeaf)
5768	{
5769	/* If advertised, the state component offset and size must match the one used by host. */
5770	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5771	{
5772	CPUMCPUID RawHost;
5773	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5774	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5775	if ( RawHost.uEbx != pCurLeaf->uEbx
5776	\|\| RawHost.uEax != pCurLeaf->uEax)
5777	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5778	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5779	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5780	}
5781	}
5782	}
5783	}
5784	/* Clear leaf 0xd just in case we're loading an old state... */
5785	else if (pCurLeaf)
5786	{
5787	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5788	{
5789	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5790	if (pCurLeaf)
5791	{
5792	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5793	\|\| ( pCurLeaf->uEax == 0
5794	&& pCurLeaf->uEbx == 0
5795	&& pCurLeaf->uEcx == 0
5796	&& pCurLeaf->uEdx == 0),
5797	("uVersion=%#x; %#x %#x %#x %#x\n",
5798	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5799	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5800	}
5801	}
5802	}
5803
5804	/* Update the fXStateGuestMask value for the VM. */
5805	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5806	{
5807	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5808	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5809	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5810	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5811	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5812	}
5813
5814	#undef CPUID_CHECK_RET
5815	#undef CPUID_CHECK_WRN
5816	#undef CPUID_CHECK2_RET
5817	#undef CPUID_CHECK2_WRN
5818	#undef CPUID_RAW_FEATURE_RET
5819	#undef CPUID_RAW_FEATURE_WRN
5820	#undef CPUID_RAW_FEATURE_IGN
5821	#undef CPUID_GST_FEATURE_RET
5822	#undef CPUID_GST_FEATURE_WRN
5823	#undef CPUID_GST_FEATURE_EMU
5824	#undef CPUID_GST_FEATURE_IGN
5825	#undef CPUID_GST_FEATURE2_RET
5826	#undef CPUID_GST_FEATURE2_WRN
5827	#undef CPUID_GST_FEATURE2_EMU
5828	#undef CPUID_GST_FEATURE2_IGN
5829	#undef CPUID_GST_AMD_FEATURE_RET
5830	#undef CPUID_GST_AMD_FEATURE_WRN
5831	#undef CPUID_GST_AMD_FEATURE_EMU
5832	#undef CPUID_GST_AMD_FEATURE_IGN
5833
5834	/*
5835	* We're good, commit the CPU ID leaves.
5836	*/
5837	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5838	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5839	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5840	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
5841	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5842	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
5843	AssertLogRelRCReturn(rc, rc);
5844
5845	return VINF_SUCCESS;
5846	}
5847
5848
5849	/**
5850	* Loads the CPU ID leaves saved by pass 0.
5851	*
5852	* @returns VBox status code.
5853	* @param pVM The cross context VM structure.
5854	* @param pSSM The saved state handle.
5855	* @param uVersion The format version.
5856	*/
5857	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5858	{
5859	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5860
5861	/*
5862	* Load the CPUID leaves array first and call worker to do the rest, just so
5863	* we can free the memory when we need to without ending up in column 1000.
5864	*/
5865	PCPUMCPUIDLEAF paLeaves;
5866	uint32_t cLeaves;
5867	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5868	AssertRC(rc);
5869	if (RT_SUCCESS(rc))
5870	{
5871	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
5872	RTMemFree(paLeaves);
5873	}
5874	return rc;
5875	}
5876
5877
5878
5879	/**
5880	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5881	*
5882	* @returns VBox status code.
5883	* @param pVM The cross context VM structure.
5884	* @param pSSM The saved state handle.
5885	* @param uVersion The format version.
5886	*/
5887	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5888	{
5889	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5890
5891	/*
5892	* Restore the CPUID leaves.
5893	*
5894	* Note that we support restoring less than the current amount of standard
5895	* leaves because we've been allowed more is newer version of VBox.
5896	*/
5897	uint32_t cElements;
5898	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5899	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5900	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5901	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5902
5903	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5904	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5905	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5906	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5907
5908	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5909	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5910	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5911	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5912
5913	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5914
5915	/*
5916	* Check that the basic cpuid id information is unchanged.
5917	*/
5918	/** @todo we should check the 64 bits capabilities too! */
5919	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5920	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5921	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5922	uint32_t au32CpuIdSaved[8];
5923	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5924	if (RT_SUCCESS(rc))
5925	{
5926	/* Ignore CPU stepping. */
5927	au32CpuId[4] &= 0xfffffff0;
5928	au32CpuIdSaved[4] &= 0xfffffff0;
5929
5930	/* Ignore APIC ID (AMD specs). */
5931	au32CpuId[5] &= ~0xff000000;
5932	au32CpuIdSaved[5] &= ~0xff000000;
5933
5934	/* Ignore the number of Logical CPUs (AMD specs). */
5935	au32CpuId[5] &= ~0x00ff0000;
5936	au32CpuIdSaved[5] &= ~0x00ff0000;
5937
5938	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5939	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5940	\| X86_CPUID_FEATURE_ECX_VMX
5941	\| X86_CPUID_FEATURE_ECX_SMX
5942	\| X86_CPUID_FEATURE_ECX_EST
5943	\| X86_CPUID_FEATURE_ECX_TM2
5944	\| X86_CPUID_FEATURE_ECX_CNTXID
5945	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5946	\| X86_CPUID_FEATURE_ECX_PDCM
5947	\| X86_CPUID_FEATURE_ECX_DCA
5948	\| X86_CPUID_FEATURE_ECX_X2APIC
5949	);
5950	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5951	\| X86_CPUID_FEATURE_ECX_VMX
5952	\| X86_CPUID_FEATURE_ECX_SMX
5953	\| X86_CPUID_FEATURE_ECX_EST
5954	\| X86_CPUID_FEATURE_ECX_TM2
5955	\| X86_CPUID_FEATURE_ECX_CNTXID
5956	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5957	\| X86_CPUID_FEATURE_ECX_PDCM
5958	\| X86_CPUID_FEATURE_ECX_DCA
5959	\| X86_CPUID_FEATURE_ECX_X2APIC
5960	);
5961
5962	/* Make sure we don't forget to update the masks when enabling
5963	* features in the future.
5964	*/
5965	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5966	( X86_CPUID_FEATURE_ECX_DTES64
5967	\| X86_CPUID_FEATURE_ECX_VMX
5968	\| X86_CPUID_FEATURE_ECX_SMX
5969	\| X86_CPUID_FEATURE_ECX_EST
5970	\| X86_CPUID_FEATURE_ECX_TM2
5971	\| X86_CPUID_FEATURE_ECX_CNTXID
5972	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5973	\| X86_CPUID_FEATURE_ECX_PDCM
5974	\| X86_CPUID_FEATURE_ECX_DCA
5975	\| X86_CPUID_FEATURE_ECX_X2APIC
5976	)));
5977	/* do the compare */
5978	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5979	{
5980	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5981	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5982	"Saved=%.*Rhxs\n"
5983	"Real =%.*Rhxs\n",
5984	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5985	sizeof(au32CpuId), au32CpuId));
5986	else
5987	{
5988	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5989	"Saved=%.*Rhxs\n"
5990	"Real =%.*Rhxs\n",
5991	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5992	sizeof(au32CpuId), au32CpuId));
5993	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5994	}
5995	}
5996	}
5997
5998	return rc;
5999	}
6000
6001
6002
6003	/*
6004	*
6005	*
6006	* CPUID Info Handler.
6007	* CPUID Info Handler.
6008	* CPUID Info Handler.
6009	*
6010	*
6011	*/
6012
6013
6014
6015	/**
6016	* Get L1 cache / TLS associativity.
6017	*/
6018	static const char getCacheAss(unsigned u, char pszBuf)
6019	{
6020	if (u == 0)
6021	return "res0 ";
6022	if (u == 1)
6023	return "direct";
6024	if (u == 255)
6025	return "fully";
6026	if (u >= 256)
6027	return "???";
6028
6029	RTStrPrintf(pszBuf, 16, "%d way", u);
6030	return pszBuf;
6031	}
6032
6033
6034	/**
6035	* Get L2 cache associativity.
6036	*/
6037	const char *getL2CacheAss(unsigned u)
6038	{
6039	switch (u)
6040	{
6041	case 0: return "off ";
6042	case 1: return "direct";
6043	case 2: return "2 way ";
6044	case 3: return "res3 ";
6045	case 4: return "4 way ";
6046	case 5: return "res5 ";
6047	case 6: return "8 way ";
6048	case 7: return "res7 ";
6049	case 8: return "16 way";
6050	case 9: return "res9 ";
6051	case 10: return "res10 ";
6052	case 11: return "res11 ";
6053	case 12: return "res12 ";
6054	case 13: return "res13 ";
6055	case 14: return "res14 ";
6056	case 15: return "fully ";
6057	default: return "????";
6058	}
6059	}
6060
6061
6062	/** CPUID(1).EDX field descriptions. */
6063	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6064	{
6065	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6066	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6067	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6068	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6069	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6070	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6071	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6072	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6073	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6074	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6075	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6076	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6077	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6078	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6079	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6080	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6081	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6082	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6083	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6084	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6085	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6086	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6087	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6088	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6089	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6090	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6091	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6092	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6093	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6094	DBGFREGSUBFIELD_TERMINATOR()
6095	};
6096
6097	/** CPUID(1).ECX field descriptions. */
6098	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6099	{
6100	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6101	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6102	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6103	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6104	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6105	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6106	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6107	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6108	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6109	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6110	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6111	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6112	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6113	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6114	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6115	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6116	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6117	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6118	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6119	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6120	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6121	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6122	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6123	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6124	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6125	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6126	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6127	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6128	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6129	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6130	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6131	DBGFREGSUBFIELD_TERMINATOR()
6132	};
6133
6134	/** CPUID(7,0).EBX field descriptions. */
6135	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6136	{
6137	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6138	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6139	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6140	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6141	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6142	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6143	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6144	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6145	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6146	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6147	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6148	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6149	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6150	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6151	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6152	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6153	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6154	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6155	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6156	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6157	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6158	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6159	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6160	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6161	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6162	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6163	DBGFREGSUBFIELD_TERMINATOR()
6164	};
6165
6166	/** CPUID(7,0).ECX field descriptions. */
6167	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6168	{
6169	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6170	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6171	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6172	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6173	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6174	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6175	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6176	DBGFREGSUBFIELD_TERMINATOR()
6177	};
6178
6179	/** CPUID(7,0).EDX field descriptions. */
6180	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6181	{
6182	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6183	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6184	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6185	DBGFREGSUBFIELD_TERMINATOR()
6186	};
6187
6188
6189	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6190	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6191	{
6192	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6193	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6194	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6195	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6196	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6197	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6198	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6199	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6200	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6201	DBGFREGSUBFIELD_TERMINATOR()
6202	};
6203
6204	/** CPUID(13,1).EAX field descriptions. */
6205	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6206	{
6207	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6208	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6209	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6210	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6211	DBGFREGSUBFIELD_TERMINATOR()
6212	};
6213
6214
6215	/** CPUID(0x80000001,0).EDX field descriptions. */
6216	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6217	{
6218	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6219	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6220	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6221	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6222	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6223	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6224	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6225	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6226	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6227	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6228	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6229	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6230	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6231	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6232	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6233	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6234	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6235	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6236	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6237	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6238	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6239	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6240	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6241	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6242	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6243	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6244	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6245	DBGFREGSUBFIELD_TERMINATOR()
6246	};
6247
6248	/** CPUID(0x80000001,0).ECX field descriptions. */
6249	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6250	{
6251	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6252	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6253	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6254	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6255	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6256	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6257	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6258	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6259	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6260	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6261	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6262	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6263	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6264	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6265	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6266	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6267	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6268	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6269	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6270	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6271	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6272	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6273	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6274	DBGFREGSUBFIELD_TERMINATOR()
6275	};
6276
6277	/** CPUID(0x8000000a,0).EDX field descriptions. */
6278	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6279	{
6280	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6281	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6282	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6283	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6284	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6285	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6286	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6287	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6288	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6289	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6290	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6291	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6292	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6293	DBGFREGSUBFIELD_TERMINATOR()
6294	};
6295
6296
6297	/** CPUID(0x80000007,0).EDX field descriptions. */
6298	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6299	{
6300	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6301	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6302	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6303	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6304	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6305	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6306	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6307	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6308	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6309	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6310	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6311	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6312	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6313	DBGFREGSUBFIELD_TERMINATOR()
6314	};
6315
6316	/** CPUID(0x80000008,0).EBX field descriptions. */
6317	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6318	{
6319	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6320	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6321	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6322	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6323	DBGFREGSUBFIELD_TERMINATOR()
6324	};
6325
6326
6327	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6328	const char *pszLeadIn, uint32_t cchWidth)
6329	{
6330	if (pszLeadIn)
6331	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6332
6333	for (uint32_t iBit = 0; iBit < 32; iBit++)
6334	if (RT_BIT_32(iBit) & uVal)
6335	{
6336	while ( pDesc->pszName != NULL
6337	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6338	pDesc++;
6339	if ( pDesc->pszName != NULL
6340	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6341	{
6342	if (pDesc->cBits == 1)
6343	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6344	else
6345	{
6346	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6347	if (pDesc->cBits < 32)
6348	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6349	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6350	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6351	}
6352	}
6353	else
6354	pHlp->pfnPrintf(pHlp, " %u", iBit);
6355	}
6356	if (pszLeadIn)
6357	pHlp->pfnPrintf(pHlp, "\n");
6358	}
6359
6360
6361	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6362	const char *pszLeadIn, uint32_t cchWidth)
6363	{
6364	if (pszLeadIn)
6365	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6366
6367	for (uint32_t iBit = 0; iBit < 64; iBit++)
6368	if (RT_BIT_64(iBit) & uVal)
6369	{
6370	while ( pDesc->pszName != NULL
6371	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6372	pDesc++;
6373	if ( pDesc->pszName != NULL
6374	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6375	{
6376	if (pDesc->cBits == 1)
6377	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6378	else
6379	{
6380	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6381	if (pDesc->cBits < 64)
6382	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6383	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6384	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6385	}
6386	}
6387	else
6388	pHlp->pfnPrintf(pHlp, " %u", iBit);
6389	}
6390	if (pszLeadIn)
6391	pHlp->pfnPrintf(pHlp, "\n");
6392	}
6393
6394
6395	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6396	const char *pszLeadIn, uint32_t cchWidth)
6397	{
6398	if (!uVal)
6399	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6400	else
6401	{
6402	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6403	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6404	pHlp->pfnPrintf(pHlp, " )\n");
6405	}
6406	}
6407
6408
6409	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6410	uint32_t cchWidth)
6411	{
6412	uint32_t uCombined = uVal1 \| uVal2;
6413	for (uint32_t iBit = 0; iBit < 32; iBit++)
6414	if ( (RT_BIT_32(iBit) & uCombined)
6415	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6416	{
6417	while ( pDesc->pszName != NULL
6418	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6419	pDesc++;
6420
6421	if ( pDesc->pszName != NULL
6422	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6423	{
6424	size_t cchMnemonic = strlen(pDesc->pszName);
6425	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6426	size_t cchDesc = strlen(pszDesc);
6427	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6428	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6429	if (pDesc->cBits < 32)
6430	{
6431	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6432	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6433	}
6434
6435	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6436	pDesc->pszName, pszDesc,
6437	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6438	uFieldValue1, uFieldValue2);
6439
6440	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6441	pDesc++;
6442	}
6443	else
6444	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6445	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6446	}
6447	}
6448
6449
6450	/**
6451	* Produces a detailed summary of standard leaf 0x00000001.
6452	*
6453	* @param pHlp The info helper functions.
6454	* @param pCurLeaf The 0x00000001 leaf.
6455	* @param fVerbose Whether to be very verbose or not.
6456	* @param fIntel Set if intel CPU.
6457	*/
6458	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6459	{
6460	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6461	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6462	uint32_t uEAX = pCurLeaf->uEax;
6463	uint32_t uEBX = pCurLeaf->uEbx;
6464
6465	pHlp->pfnPrintf(pHlp,
6466	"%36s %2d \tExtended: %d \tEffective: %d\n"
6467	"%36s %2d \tExtended: %d \tEffective: %d\n"
6468	"%36s %d\n"
6469	"%36s %d (%s)\n"
6470	"%36s %#04x\n"
6471	"%36s %d\n"
6472	"%36s %d\n"
6473	"%36s %#04x\n"
6474	,
6475	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6476	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6477	"Stepping:", ASMGetCpuStepping(uEAX),
6478	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6479	"APIC ID:", (uEBX >> 24) & 0xff,
6480	"Logical CPUs:",(uEBX >> 16) & 0xff,
6481	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6482	"Brand ID:", (uEBX >> 0) & 0xff);
6483	if (fVerbose)
6484	{
6485	CPUMCPUID Host;
6486	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6487	pHlp->pfnPrintf(pHlp, "Features\n");
6488	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6489	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6490	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6491	}
6492	else
6493	{
6494	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6495	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6496	}
6497	}
6498
6499
6500	/**
6501	* Produces a detailed summary of standard leaf 0x00000007.
6502	*
6503	* @param pHlp The info helper functions.
6504	* @param paLeaves The CPUID leaves array.
6505	* @param cLeaves The number of leaves in the array.
6506	* @param pCurLeaf The first 0x00000007 leaf.
6507	* @param fVerbose Whether to be very verbose or not.
6508	*/
6509	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6510	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6511	{
6512	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6513	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6514	for (;;)
6515	{
6516	CPUMCPUID Host;
6517	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6518
6519	switch (pCurLeaf->uSubLeaf)
6520	{
6521	case 0:
6522	if (fVerbose)
6523	{
6524	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6525	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6526	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6527	if (pCurLeaf->uEdx \|\| Host.uEdx)
6528	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6529	}
6530	else
6531	{
6532	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6533	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6534	if (pCurLeaf->uEdx)
6535	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6536	}
6537	break;
6538
6539	default:
6540	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6541	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6542	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6543	break;
6544
6545	}
6546
6547	/* advance. */
6548	pCurLeaf++;
6549	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6550	\|\| pCurLeaf->uLeaf != 0x7)
6551	break;
6552	}
6553	}
6554
6555
6556	/**
6557	* Produces a detailed summary of standard leaf 0x0000000d.
6558	*
6559	* @param pHlp The info helper functions.
6560	* @param paLeaves The CPUID leaves array.
6561	* @param cLeaves The number of leaves in the array.
6562	* @param pCurLeaf The first 0x00000007 leaf.
6563	* @param fVerbose Whether to be very verbose or not.
6564	*/
6565	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6566	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6567	{
6568	RT_NOREF_PV(fVerbose);
6569	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6570	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6571	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6572	{
6573	CPUMCPUID Host;
6574	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6575
6576	switch (uSubLeaf)
6577	{
6578	case 0:
6579	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6580	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6581	pCurLeaf->uEbx, pCurLeaf->uEcx);
6582	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6583
6584	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6585	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6586	"Valid XCR0 bits, guest:", 42);
6587	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6588	"Valid XCR0 bits, host:", 42);
6589	break;
6590
6591	case 1:
6592	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6593	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6594	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6595
6596	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6597	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6598	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6599
6600	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6601	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6602	" Valid IA32_XSS bits, guest:", 42);
6603	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6604	" Valid IA32_XSS bits, host:", 42);
6605	break;
6606
6607	default:
6608	if ( pCurLeaf
6609	&& pCurLeaf->uSubLeaf == uSubLeaf
6610	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6611	{
6612	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6613	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6614	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6615	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6616	if (pCurLeaf->uEdx)
6617	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6618	pHlp->pfnPrintf(pHlp, " --");
6619	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6620	pHlp->pfnPrintf(pHlp, "\n");
6621	}
6622	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6623	{
6624	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6625	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6626	if (Host.uEcx & ~RT_BIT_32(0))
6627	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6628	if (Host.uEdx)
6629	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6630	pHlp->pfnPrintf(pHlp, " --");
6631	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6632	pHlp->pfnPrintf(pHlp, "\n");
6633	}
6634	break;
6635
6636	}
6637
6638	/* advance. */
6639	if (pCurLeaf)
6640	{
6641	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6642	&& pCurLeaf->uSubLeaf <= uSubLeaf
6643	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6644	pCurLeaf++;
6645	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6646	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6647	pCurLeaf = NULL;
6648	}
6649	}
6650	}
6651
6652
6653	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6654	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6655	{
6656	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6657	&& pCurLeaf->uLeaf <= uUpToLeaf)
6658	{
6659	pHlp->pfnPrintf(pHlp,
6660	" %s\n"
6661	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6662	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6663	&& pCurLeaf->uLeaf <= uUpToLeaf)
6664	{
6665	CPUMCPUID Host;
6666	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6667	pHlp->pfnPrintf(pHlp,
6668	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6669	"Hst: %08x %08x %08x %08x\n",
6670	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6671	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6672	pCurLeaf++;
6673	}
6674	}
6675
6676	return pCurLeaf;
6677	}
6678
6679
6680	/**
6681	* Display the guest CpuId leaves.
6682	*
6683	* @param pVM The cross context VM structure.
6684	* @param pHlp The info helper functions.
6685	* @param pszArgs "terse", "default" or "verbose".
6686	*/
6687	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6688	{
6689	/*
6690	* Parse the argument.
6691	*/
6692	unsigned iVerbosity = 1;
6693	if (pszArgs)
6694	{
6695	pszArgs = RTStrStripL(pszArgs);
6696	if (!strcmp(pszArgs, "terse"))
6697	iVerbosity--;
6698	else if (!strcmp(pszArgs, "verbose"))
6699	iVerbosity++;
6700	}
6701
6702	uint32_t uLeaf;
6703	CPUMCPUID Host;
6704	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6705	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6706	PCCPUMCPUIDLEAF pCurLeaf;
6707	PCCPUMCPUIDLEAF pNextLeaf;
6708	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6709	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6710	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6711
6712	/*
6713	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6714	*/
6715	uint32_t cHstMax = ASMCpuId_EAX(0);
6716	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6717	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6718	pHlp->pfnPrintf(pHlp,
6719	" Raw Standard CPUID Leaves\n"
6720	" Leaf/sub-leaf eax ebx ecx edx\n");
6721	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6722	{
6723	uint32_t cMaxSubLeaves = 1;
6724	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6725	cMaxSubLeaves = 16;
6726	else if (uLeaf == 0xd)
6727	cMaxSubLeaves = 128;
6728
6729	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6730	{
6731	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6732	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6733	&& pCurLeaf->uLeaf == uLeaf
6734	&& pCurLeaf->uSubLeaf == uSubLeaf)
6735	{
6736	pHlp->pfnPrintf(pHlp,
6737	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6738	"Hst: %08x %08x %08x %08x\n",
6739	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6740	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6741	pCurLeaf++;
6742	}
6743	else if ( uLeaf != 0xd
6744	\|\| uSubLeaf <= 1
6745	\|\| Host.uEbx != 0 )
6746	pHlp->pfnPrintf(pHlp,
6747	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6748	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6749
6750	/* Done? */
6751	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6752	\|\| pCurLeaf->uLeaf != uLeaf)
6753	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6754	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6755	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6756	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6757	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6758	)
6759	)
6760	break;
6761	}
6762	}
6763	pNextLeaf = pCurLeaf;
6764
6765	/*
6766	* If verbose, decode it.
6767	*/
6768	if (iVerbosity && paLeaves[0].uLeaf == 0)
6769	pHlp->pfnPrintf(pHlp,
6770	"%36s %.04s%.04s%.04s\n"
6771	"%36s 0x00000000-%#010x\n"
6772	,
6773	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6774	"Supports:", paLeaves[0].uEax);
6775
6776	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6777	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6778
6779	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6780	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6781
6782	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6783	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6784
6785	pCurLeaf = pNextLeaf;
6786
6787	/*
6788	* Hypervisor leaves.
6789	*
6790	* Unlike most of the other leaves reported, the guest hypervisor leaves
6791	* aren't a subset of the host CPUID bits.
6792	*/
6793	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6794
6795	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6796	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6797	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6798	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6799	cMax = RT_MAX(cHstMax, cGstMax);
6800	if (cMax >= UINT32_C(0x40000000))
6801	{
6802	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6803
6804	/** @todo dump these in more detail. */
6805
6806	pCurLeaf = pNextLeaf;
6807	}
6808
6809
6810	/*
6811	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6812	* Implemented after AMD specs.
6813	*/
6814	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6815
6816	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6817	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6818	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6819	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6820	cMax = RT_MAX(cHstMax, cGstMax);
6821	if (cMax >= UINT32_C(0x80000000))
6822	{
6823
6824	pHlp->pfnPrintf(pHlp,
6825	" Raw Extended CPUID Leaves\n"
6826	" Leaf/sub-leaf eax ebx ecx edx\n");
6827	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6828	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6829	{
6830	uint32_t cMaxSubLeaves = 1;
6831	if (uLeaf == UINT32_C(0x8000001d))
6832	cMaxSubLeaves = 16;
6833
6834	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6835	{
6836	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6837	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6838	&& pCurLeaf->uLeaf == uLeaf
6839	&& pCurLeaf->uSubLeaf == uSubLeaf)
6840	{
6841	pHlp->pfnPrintf(pHlp,
6842	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6843	"Hst: %08x %08x %08x %08x\n",
6844	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6845	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6846	pCurLeaf++;
6847	}
6848	else if ( uLeaf != 0xd
6849	\|\| uSubLeaf <= 1
6850	\|\| Host.uEbx != 0 )
6851	pHlp->pfnPrintf(pHlp,
6852	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6853	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6854
6855	/* Done? */
6856	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6857	\|\| pCurLeaf->uLeaf != uLeaf)
6858	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6859	break;
6860	}
6861	}
6862	pNextLeaf = pCurLeaf;
6863
6864	/*
6865	* Understandable output
6866	*/
6867	if (iVerbosity)
6868	pHlp->pfnPrintf(pHlp,
6869	"Ext Name: %.4s%.4s%.4s\n"
6870	"Ext Supports: 0x80000000-%#010x\n",
6871	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6872
6873	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6874	if (iVerbosity && pCurLeaf)
6875	{
6876	uint32_t uEAX = pCurLeaf->uEax;
6877	pHlp->pfnPrintf(pHlp,
6878	"Family: %d \tExtended: %d \tEffective: %d\n"
6879	"Model: %d \tExtended: %d \tEffective: %d\n"
6880	"Stepping: %d\n"
6881	"Brand ID: %#05x\n",
6882	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6883	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6884	ASMGetCpuStepping(uEAX),
6885	pCurLeaf->uEbx & 0xfff);
6886
6887	if (iVerbosity == 1)
6888	{
6889	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6890	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6891	}
6892	else
6893	{
6894	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6895	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6896	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6897	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6898	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6899	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
6900	{
6901	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
6902	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6903	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
6904	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
6905	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
6906	}
6907	}
6908	}
6909
6910	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6911	{
6912	char szString[443+1] = {0};
6913	uint32_t pu32 = (uint32_t )szString;
6914	*pu32++ = pCurLeaf->uEax;
6915	*pu32++ = pCurLeaf->uEbx;
6916	*pu32++ = pCurLeaf->uEcx;
6917	*pu32++ = pCurLeaf->uEdx;
6918	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6919	if (pCurLeaf)
6920	{
6921	*pu32++ = pCurLeaf->uEax;
6922	*pu32++ = pCurLeaf->uEbx;
6923	*pu32++ = pCurLeaf->uEcx;
6924	*pu32++ = pCurLeaf->uEdx;
6925	}
6926	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6927	if (pCurLeaf)
6928	{
6929	*pu32++ = pCurLeaf->uEax;
6930	*pu32++ = pCurLeaf->uEbx;
6931	*pu32++ = pCurLeaf->uEcx;
6932	*pu32++ = pCurLeaf->uEdx;
6933	}
6934	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6935	}
6936
6937	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6938	{
6939	uint32_t uEAX = pCurLeaf->uEax;
6940	uint32_t uEBX = pCurLeaf->uEbx;
6941	uint32_t uECX = pCurLeaf->uEcx;
6942	uint32_t uEDX = pCurLeaf->uEdx;
6943	char sz1[32];
6944	char sz2[32];
6945
6946	pHlp->pfnPrintf(pHlp,
6947	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6948	"TLB 2/4M Data: %s %3d entries\n",
6949	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6950	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6951	pHlp->pfnPrintf(pHlp,
6952	"TLB 4K Instr/Uni: %s %3d entries\n"
6953	"TLB 4K Data: %s %3d entries\n",
6954	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6955	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6956	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6957	"L1 Instr Cache Lines Per Tag: %d\n"
6958	"L1 Instr Cache Associativity: %s\n"
6959	"L1 Instr Cache Size: %d KB\n",
6960	(uEDX >> 0) & 0xff,
6961	(uEDX >> 8) & 0xff,
6962	getCacheAss((uEDX >> 16) & 0xff, sz1),
6963	(uEDX >> 24) & 0xff);
6964	pHlp->pfnPrintf(pHlp,
6965	"L1 Data Cache Line Size: %d bytes\n"
6966	"L1 Data Cache Lines Per Tag: %d\n"
6967	"L1 Data Cache Associativity: %s\n"
6968	"L1 Data Cache Size: %d KB\n",
6969	(uECX >> 0) & 0xff,
6970	(uECX >> 8) & 0xff,
6971	getCacheAss((uECX >> 16) & 0xff, sz1),
6972	(uECX >> 24) & 0xff);
6973	}
6974
6975	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6976	{
6977	uint32_t uEAX = pCurLeaf->uEax;
6978	uint32_t uEBX = pCurLeaf->uEbx;
6979	uint32_t uEDX = pCurLeaf->uEdx;
6980
6981	pHlp->pfnPrintf(pHlp,
6982	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6983	"L2 TLB 2/4M Data: %s %4d entries\n",
6984	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6985	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6986	pHlp->pfnPrintf(pHlp,
6987	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6988	"L2 TLB 4K Data: %s %4d entries\n",
6989	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6990	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6991	pHlp->pfnPrintf(pHlp,
6992	"L2 Cache Line Size: %d bytes\n"
6993	"L2 Cache Lines Per Tag: %d\n"
6994	"L2 Cache Associativity: %s\n"
6995	"L2 Cache Size: %d KB\n",
6996	(uEDX >> 0) & 0xff,
6997	(uEDX >> 8) & 0xf,
6998	getL2CacheAss((uEDX >> 12) & 0xf),
6999	(uEDX >> 16) & 0xffff);
7000	}
7001
7002	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
7003	{
7004	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7005	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
7006	{
7007	if (iVerbosity < 1)
7008	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7009	else
7010	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7011	}
7012	}
7013
7014	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7015	if (pCurLeaf != NULL)
7016	{
7017	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7018	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7019	{
7020	if (iVerbosity < 1)
7021	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7022	else
7023	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7024	}
7025
7026	if (iVerbosity)
7027	{
7028	uint32_t uEAX = pCurLeaf->uEax;
7029	uint32_t uECX = pCurLeaf->uEcx;
7030
7031	pHlp->pfnPrintf(pHlp,
7032	"Physical Address Width: %d bits\n"
7033	"Virtual Address Width: %d bits\n"
7034	"Guest Physical Address Width: %d bits\n",
7035	(uEAX >> 0) & 0xff,
7036	(uEAX >> 8) & 0xff,
7037	(uEAX >> 16) & 0xff);
7038	pHlp->pfnPrintf(pHlp,
7039	"Physical Core Count: %d\n",
7040	((uECX >> 0) & 0xff) + 1);
7041	}
7042	}
7043
7044	pCurLeaf = pNextLeaf;
7045	}
7046
7047
7048
7049	/*
7050	* Centaur.
7051	*/
7052	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7053
7054	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7055	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7056	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7057	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7058	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7059	cMax = RT_MAX(cHstMax, cGstMax);
7060	if (cMax >= UINT32_C(0xc0000000))
7061	{
7062	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7063
7064	/*
7065	* Understandable output
7066	*/
7067	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7068	pHlp->pfnPrintf(pHlp,
7069	"Centaur Supports: 0xc0000000-%#010x\n",
7070	pCurLeaf->uEax);
7071
7072	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7073	{
7074	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7075	uint32_t uEdxGst = pCurLeaf->uEdx;
7076	uint32_t uEdxHst = Host.uEdx;
7077
7078	if (iVerbosity == 1)
7079	{
7080	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7081	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7082	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7083	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7084	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7085	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7086	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7087	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7088	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7089	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7090	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7091	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7092	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7093	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7094	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7095	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7096	for (unsigned iBit = 14; iBit < 32; iBit++)
7097	if (uEdxGst & RT_BIT(iBit))
7098	pHlp->pfnPrintf(pHlp, " %d", iBit);
7099	pHlp->pfnPrintf(pHlp, "\n");
7100	}
7101	else
7102	{
7103	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7104	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7105	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7106	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7107	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7108	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7109	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7110	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7111	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7112	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7113	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7114	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7115	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7116	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7117	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7118	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7119	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7120	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7121	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7122	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7123	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7124	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7125	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7126	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7127	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7128	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7129	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7130	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7131	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7132	for (unsigned iBit = 27; iBit < 32; iBit++)
7133	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7134	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7135	pHlp->pfnPrintf(pHlp, "\n");
7136	}
7137	}
7138
7139	pCurLeaf = pNextLeaf;
7140	}
7141
7142	/*
7143	* The remainder.
7144	*/
7145	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7146	}
7147
7148
7149
7150
7151
7152	/*
7153	*
7154	*
7155	* PATM interfaces.
7156	* PATM interfaces.
7157	* PATM interfaces.
7158	*
7159	*
7160	*/
7161
7162
7163	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
7164	/** @name Patchmanager CPUID legacy table APIs
7165	* @{
7166	*/
7167
7168	/**
7169	* Gets a pointer to the default CPUID leaf.
7170	*
7171	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
7172	* @param pVM The cross context VM structure.
7173	* @remark Intended for PATM only.
7174	*/
7175	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
7176	{
7177	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
7178	}
7179
7180
7181	/**
7182	* Gets a number of standard CPUID leaves (PATM only).
7183	*
7184	* @returns Number of leaves.
7185	* @param pVM The cross context VM structure.
7186	* @remark Intended for PATM - legacy, don't use in new code.
7187	*/
7188	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
7189	{
7190	RT_NOREF_PV(pVM);
7191	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
7192	}
7193
7194
7195	/**
7196	* Gets a number of extended CPUID leaves (PATM only).
7197	*
7198	* @returns Number of leaves.
7199	* @param pVM The cross context VM structure.
7200	* @remark Intended for PATM - legacy, don't use in new code.
7201	*/
7202	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
7203	{
7204	RT_NOREF_PV(pVM);
7205	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
7206	}
7207
7208
7209	/**
7210	* Gets a number of centaur CPUID leaves.
7211	*
7212	* @returns Number of leaves.
7213	* @param pVM The cross context VM structure.
7214	* @remark Intended for PATM - legacy, don't use in new code.
7215	*/
7216	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
7217	{
7218	RT_NOREF_PV(pVM);
7219	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
7220	}
7221
7222
7223	/**
7224	* Gets a pointer to the array of standard CPUID leaves.
7225	*
7226	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
7227	*
7228	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
7229	* @param pVM The cross context VM structure.
7230	* @remark Intended for PATM - legacy, don't use in new code.
7231	*/
7232	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
7233	{
7234	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
7235	}
7236
7237
7238	/**
7239	* Gets a pointer to the array of extended CPUID leaves.
7240	*
7241	* CPUMGetGuestCpuIdExtMax() give the size of the array.
7242	*
7243	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
7244	* @param pVM The cross context VM structure.
7245	* @remark Intended for PATM - legacy, don't use in new code.
7246	*/
7247	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
7248	{
7249	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
7250	}
7251
7252
7253	/**
7254	* Gets a pointer to the array of centaur CPUID leaves.
7255	*
7256	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
7257	*
7258	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
7259	* @param pVM The cross context VM structure.
7260	* @remark Intended for PATM - legacy, don't use in new code.
7261	*/
7262	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
7263	{
7264	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
7265	}
7266
7267	/** @} */
7268	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
7269
7270	#endif /* VBOX_IN_VMM */
7271

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 73711

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