CPUMR3CpuId.cpp@ 74113

Last change on this file since 74113 was 74113, checked in by vboxsync, 6 years ago
VMM/CPUM, IEM: Nested VMX: bugref:9180 Fixes for allowing 32-bit nested-guest support.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 338.4 KB

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1	/* $Id: CPUMR3CpuId.cpp 74113 2018-09-06 11:49:14Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/mm.h>
31	#include <VBox/sup.h>
32
33	#include <VBox/err.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/ctype.h>
36	#include <iprt/mem.h>
37	#include <iprt/string.h>
38
39
40	/*********************************************************************************************************************************
41	* Defined Constants And Macros *
42	*********************************************************************************************************************************/
43	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
44	#define CPUM_CPUID_MAX_LEAVES 2048
45	/* Max size we accept for the XSAVE area. */
46	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
47	/* Min size we accept for the XSAVE area. */
48	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
49
50
51	/*********************************************************************************************************************************
52	* Global Variables *
53	*********************************************************************************************************************************/
54	/**
55	* The intel pentium family.
56	*/
57	static const CPUMMICROARCH g_aenmIntelFamily06[] =
58	{
59	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
60	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
61	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
63	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
64	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
65	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
66	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
67	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
68	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
69	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
70	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
71	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
72	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
73	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
74	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
75	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
81	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
82	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
83	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
86	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
88	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
89	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
90	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
91	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
97	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
98	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
99	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
102	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
104	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
105	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
106	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
107	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
113	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
114	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
115	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
118	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
121	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
122	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
130	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
131	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
136	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [78(0x4e)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed */
138	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / unconfirmed, Broadwell-E */
139	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu */
145	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
146	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
147	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
150	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
152	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
153	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
154	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
155	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
159	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
160	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
161	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
162	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
163	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
164	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
165	/[106(0x6a)] = / kCpumMicroarch_Intel_Unknown,
166	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
167	/[108(0x6c)] = / kCpumMicroarch_Intel_Unknown,
168	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
169	/[110(0x6e)] = / kCpumMicroarch_Intel_Unknown,
170	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
171	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
172	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
173	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
174	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
175	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
176	/[117(0x75)] = / kCpumMicroarch_Intel_Unknown,
177	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
178	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
179	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
180	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
181	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
182	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
183	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
184	/[125(0x7d)] = / kCpumMicroarch_Intel_Unknown,
185	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
186	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
187	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
188	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
189	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
190	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
191	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
192	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
193	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
194	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
195	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
196	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
197	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
198	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
199	/[140(0x8c)] = / kCpumMicroarch_Intel_Unknown,
200	/[141(0x8d)] = / kCpumMicroarch_Intel_Unknown,
201	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
202	/[143(0x8f)] = / kCpumMicroarch_Intel_Unknown,
203	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
204	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
205	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
206	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
207	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
208	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
209	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
210	/[151(0x97)] = / kCpumMicroarch_Intel_Unknown,
211	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
212	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
213	/[154(0x9a)] = / kCpumMicroarch_Intel_Unknown,
214	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
215	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
216	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
217	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
218	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
219	};
220	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0x9f+1);
221
222
223	/**
224	* Figures out the (sub-)micro architecture given a bit of CPUID info.
225	*
226	* @returns Micro architecture.
227	* @param enmVendor The CPU vendor .
228	* @param bFamily The CPU family.
229	* @param bModel The CPU model.
230	* @param bStepping The CPU stepping.
231	*/
232	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
233	uint8_t bModel, uint8_t bStepping)
234	{
235	if (enmVendor == CPUMCPUVENDOR_AMD)
236	{
237	switch (bFamily)
238	{
239	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
240	case 0x03: return kCpumMicroarch_AMD_Am386;
241	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
242	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
243	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
244	case 0x06:
245	switch (bModel)
246	{
247	case 0: return kCpumMicroarch_AMD_K7_Palomino;
248	case 1: return kCpumMicroarch_AMD_K7_Palomino;
249	case 2: return kCpumMicroarch_AMD_K7_Palomino;
250	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
251	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
252	case 6: return kCpumMicroarch_AMD_K7_Palomino;
253	case 7: return kCpumMicroarch_AMD_K7_Morgan;
254	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
255	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
256	}
257	return kCpumMicroarch_AMD_K7_Unknown;
258	case 0x0f:
259	/*
260	* This family is a friggin mess. Trying my best to make some
261	* sense out of it. Too much happened in the 0x0f family to
262	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
263	*
264	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
265	* cpu-world.com, and other places:
266	* - 130nm:
267	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
268	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
269	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
270	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
271	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
272	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
273	* - 90nm:
274	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
275	* - Oakville: 10FC0/DH-D0.
276	* - Georgetown: 10FC0/DH-D0.
277	* - Sonora: 10FC0/DH-D0.
278	* - Venus: 20F71/SH-E4
279	* - Troy: 20F51/SH-E4
280	* - Athens: 20F51/SH-E4
281	* - San Diego: 20F71/SH-E4.
282	* - Lancaster: 20F42/SH-E5
283	* - Newark: 20F42/SH-E5.
284	* - Albany: 20FC2/DH-E6.
285	* - Roma: 20FC2/DH-E6.
286	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
287	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
288	* - 90nm introducing Dual core:
289	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
290	* - Italy: 20F10/JH-E1, 20F12/JH-E6
291	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
292	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
293	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
294	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
295	* - Santa Ana: 40F32/JH-F2, /-F3
296	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
297	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
298	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
299	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
300	* - Keene: 40FC2/DH-F2.
301	* - Richmond: 40FC2/DH-F2
302	* - Taylor: 40F82/BH-F2
303	* - Trinidad: 40F82/BH-F2
304	*
305	* - 65nm:
306	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
307	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
308	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
309	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
310	* - Sherman: /-G1, 70FC2/DH-G2.
311	* - Huron: 70FF2/DH-G2.
312	*/
313	if (bModel < 0x10)
314	return kCpumMicroarch_AMD_K8_130nm;
315	if (bModel >= 0x60 && bModel < 0x80)
316	return kCpumMicroarch_AMD_K8_65nm;
317	if (bModel >= 0x40)
318	return kCpumMicroarch_AMD_K8_90nm_AMDV;
319	switch (bModel)
320	{
321	case 0x21:
322	case 0x23:
323	case 0x2b:
324	case 0x2f:
325	case 0x37:
326	case 0x3f:
327	return kCpumMicroarch_AMD_K8_90nm_DualCore;
328	}
329	return kCpumMicroarch_AMD_K8_90nm;
330	case 0x10:
331	return kCpumMicroarch_AMD_K10;
332	case 0x11:
333	return kCpumMicroarch_AMD_K10_Lion;
334	case 0x12:
335	return kCpumMicroarch_AMD_K10_Llano;
336	case 0x14:
337	return kCpumMicroarch_AMD_Bobcat;
338	case 0x15:
339	switch (bModel)
340	{
341	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
342	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
343	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
344	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
345	case 0x11: /* ?? */
346	case 0x12: /* ?? */
347	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
348	}
349	return kCpumMicroarch_AMD_15h_Unknown;
350	case 0x16:
351	return kCpumMicroarch_AMD_Jaguar;
352	case 0x17:
353	return kCpumMicroarch_AMD_Zen_Ryzen;
354	}
355	return kCpumMicroarch_AMD_Unknown;
356	}
357
358	if (enmVendor == CPUMCPUVENDOR_INTEL)
359	{
360	switch (bFamily)
361	{
362	case 3:
363	return kCpumMicroarch_Intel_80386;
364	case 4:
365	return kCpumMicroarch_Intel_80486;
366	case 5:
367	return kCpumMicroarch_Intel_P5;
368	case 6:
369	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
370	{
371	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
372	if ( enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake
373	&& bStepping >= 0xa)
374	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
375	return enmMicroArch;
376	}
377	return kCpumMicroarch_Intel_Atom_Unknown;
378	case 15:
379	switch (bModel)
380	{
381	case 0: return kCpumMicroarch_Intel_NB_Willamette;
382	case 1: return kCpumMicroarch_Intel_NB_Willamette;
383	case 2: return kCpumMicroarch_Intel_NB_Northwood;
384	case 3: return kCpumMicroarch_Intel_NB_Prescott;
385	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
386	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
387	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
388	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
389	default: return kCpumMicroarch_Intel_NB_Unknown;
390	}
391	break;
392	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
393	case 0:
394	return kCpumMicroarch_Intel_8086;
395	case 1:
396	return kCpumMicroarch_Intel_80186;
397	case 2:
398	return kCpumMicroarch_Intel_80286;
399	}
400	return kCpumMicroarch_Intel_Unknown;
401	}
402
403	if (enmVendor == CPUMCPUVENDOR_VIA)
404	{
405	switch (bFamily)
406	{
407	case 5:
408	switch (bModel)
409	{
410	case 1: return kCpumMicroarch_Centaur_C6;
411	case 4: return kCpumMicroarch_Centaur_C6;
412	case 8: return kCpumMicroarch_Centaur_C2;
413	case 9: return kCpumMicroarch_Centaur_C3;
414	}
415	break;
416
417	case 6:
418	switch (bModel)
419	{
420	case 5: return kCpumMicroarch_VIA_C3_M2;
421	case 6: return kCpumMicroarch_VIA_C3_C5A;
422	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
423	case 8: return kCpumMicroarch_VIA_C3_C5N;
424	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
425	case 10: return kCpumMicroarch_VIA_C7_C5J;
426	case 15: return kCpumMicroarch_VIA_Isaiah;
427	}
428	break;
429	}
430	return kCpumMicroarch_VIA_Unknown;
431	}
432
433	if (enmVendor == CPUMCPUVENDOR_CYRIX)
434	{
435	switch (bFamily)
436	{
437	case 4:
438	switch (bModel)
439	{
440	case 9: return kCpumMicroarch_Cyrix_5x86;
441	}
442	break;
443
444	case 5:
445	switch (bModel)
446	{
447	case 2: return kCpumMicroarch_Cyrix_M1;
448	case 4: return kCpumMicroarch_Cyrix_MediaGX;
449	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
450	}
451	break;
452
453	case 6:
454	switch (bModel)
455	{
456	case 0: return kCpumMicroarch_Cyrix_M2;
457	}
458	break;
459
460	}
461	return kCpumMicroarch_Cyrix_Unknown;
462	}
463
464	return kCpumMicroarch_Unknown;
465	}
466
467
468	/**
469	* Translates a microarchitecture enum value to the corresponding string
470	* constant.
471	*
472	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
473	* NULL if the value is invalid.
474	*
475	* @param enmMicroarch The enum value to convert.
476	*/
477	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
478	{
479	switch (enmMicroarch)
480	{
481	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
482	CASE_RET_STR(kCpumMicroarch_Intel_8086);
483	CASE_RET_STR(kCpumMicroarch_Intel_80186);
484	CASE_RET_STR(kCpumMicroarch_Intel_80286);
485	CASE_RET_STR(kCpumMicroarch_Intel_80386);
486	CASE_RET_STR(kCpumMicroarch_Intel_80486);
487	CASE_RET_STR(kCpumMicroarch_Intel_P5);
488
489	CASE_RET_STR(kCpumMicroarch_Intel_P6);
490	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
491	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
492
493	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
494	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
495	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
496
497	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
498	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
499
500	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
501	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
502	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
503	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
504	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
505	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
506	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
507	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
508	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
509	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
510	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
511	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
512
513	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
514	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
515	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
516	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
517	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
518	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
519	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
520	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
521
522	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
523	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
524	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
525	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
526	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
527
528	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
529	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
530	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
531	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
532	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
533	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
534	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
535
536	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
537
538	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
539	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
540	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
541	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
542	CASE_RET_STR(kCpumMicroarch_AMD_K5);
543	CASE_RET_STR(kCpumMicroarch_AMD_K6);
544
545	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
546	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
547	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
548	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
549	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
550	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
551	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
552
553	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
554	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
555	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
556	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
557	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
558
559	CASE_RET_STR(kCpumMicroarch_AMD_K10);
560	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
561	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
562	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
563	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
564
565	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
566	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
567	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
568	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
569	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
570
571	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
572
573	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
574
575	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
576
577	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
578	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
579	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
580	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
581	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
582	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
583	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
584	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
585	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
586	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
587	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
588	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
589	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
590
591	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
592	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
593	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
594	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
595	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
596	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
597
598	CASE_RET_STR(kCpumMicroarch_NEC_V20);
599	CASE_RET_STR(kCpumMicroarch_NEC_V30);
600
601	CASE_RET_STR(kCpumMicroarch_Unknown);
602
603	#undef CASE_RET_STR
604	case kCpumMicroarch_Invalid:
605	case kCpumMicroarch_Intel_End:
606	case kCpumMicroarch_Intel_Core2_End:
607	case kCpumMicroarch_Intel_Core7_End:
608	case kCpumMicroarch_Intel_Atom_End:
609	case kCpumMicroarch_Intel_P6_Core_Atom_End:
610	case kCpumMicroarch_Intel_Phi_End:
611	case kCpumMicroarch_Intel_NB_End:
612	case kCpumMicroarch_AMD_K7_End:
613	case kCpumMicroarch_AMD_K8_End:
614	case kCpumMicroarch_AMD_15h_End:
615	case kCpumMicroarch_AMD_16h_End:
616	case kCpumMicroarch_AMD_Zen_End:
617	case kCpumMicroarch_AMD_End:
618	case kCpumMicroarch_VIA_End:
619	case kCpumMicroarch_Cyrix_End:
620	case kCpumMicroarch_NEC_End:
621	case kCpumMicroarch_32BitHack:
622	break;
623	/* no default! */
624	}
625
626	return NULL;
627	}
628
629
630	/**
631	* Determins the host CPU MXCSR mask.
632	*
633	* @returns MXCSR mask.
634	*/
635	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
636	{
637	if ( ASMHasCpuId()
638	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
639	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
640	{
641	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
642	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
643	RT_ZERO(*pState);
644	ASMFxSave(pState);
645	if (pState->MXCSR_MASK == 0)
646	return 0xffbf;
647	return pState->MXCSR_MASK;
648	}
649	return 0;
650	}
651
652
653	/**
654	* Gets a matching leaf in the CPUID leaf array.
655	*
656	* @returns Pointer to the matching leaf, or NULL if not found.
657	* @param paLeaves The CPUID leaves to search. This is sorted.
658	* @param cLeaves The number of leaves in the array.
659	* @param uLeaf The leaf to locate.
660	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
661	*/
662	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
663	{
664	/* Lazy bird does linear lookup here since this is only used for the
665	occational CPUID overrides. */
666	for (uint32_t i = 0; i < cLeaves; i++)
667	if ( paLeaves[i].uLeaf == uLeaf
668	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
669	return &paLeaves[i];
670	return NULL;
671	}
672
673
674	#ifndef IN_VBOX_CPU_REPORT
675	/**
676	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
677	*
678	* @returns true if found, false it not.
679	* @param paLeaves The CPUID leaves to search. This is sorted.
680	* @param cLeaves The number of leaves in the array.
681	* @param uLeaf The leaf to locate.
682	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
683	* @param pLegacy The legacy output leaf.
684	*/
685	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
686	PCPUMCPUID pLegacy)
687	{
688	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
689	if (pLeaf)
690	{
691	pLegacy->uEax = pLeaf->uEax;
692	pLegacy->uEbx = pLeaf->uEbx;
693	pLegacy->uEcx = pLeaf->uEcx;
694	pLegacy->uEdx = pLeaf->uEdx;
695	return true;
696	}
697	return false;
698	}
699	#endif /* IN_VBOX_CPU_REPORT */
700
701
702	/**
703	* Ensures that the CPUID leaf array can hold one more leaf.
704	*
705	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
706	* failure.
707	* @param pVM The cross context VM structure. If NULL, use
708	* the process heap, otherwise the VM's hyper heap.
709	* @param ppaLeaves Pointer to the variable holding the array pointer
710	* (input/output).
711	* @param cLeaves The current array size.
712	*
713	* @remarks This function will automatically update the R0 and RC pointers when
714	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
715	* be the corresponding VM's CPUID arrays (which is asserted).
716	*/
717	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
718	{
719	/*
720	* If pVM is not specified, we're on the regular heap and can waste a
721	* little space to speed things up.
722	*/
723	uint32_t cAllocated;
724	if (!pVM)
725	{
726	cAllocated = RT_ALIGN(cLeaves, 16);
727	if (cLeaves + 1 > cAllocated)
728	{
729	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
730	if (pvNew)
731	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
732	else
733	{
734	RTMemFree(*ppaLeaves);
735	*ppaLeaves = NULL;
736	}
737	}
738	}
739	/*
740	* Otherwise, we're on the hyper heap and are probably just inserting
741	* one or two leaves and should conserve space.
742	*/
743	else
744	{
745	#ifdef IN_VBOX_CPU_REPORT
746	AssertReleaseFailed();
747	#else
748	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
749	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
750
751	size_t cb = cLeaves * sizeof(**ppaLeaves);
752	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
753	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
754	if (RT_SUCCESS(rc))
755	{
756	/* Update the R0 and RC pointers. */
757	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
758	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
759	}
760	else
761	{
762	*ppaLeaves = NULL;
763	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
764	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
765	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
766	}
767	#endif
768	}
769	return *ppaLeaves;
770	}
771
772
773	/**
774	* Append a CPUID leaf or sub-leaf.
775	*
776	* ASSUMES linear insertion order, so we'll won't need to do any searching or
777	* replace anything. Use cpumR3CpuIdInsert() for those cases.
778	*
779	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
780	* the caller need do no more work.
781	* @param ppaLeaves Pointer to the pointer to the array of sorted
782	* CPUID leaves and sub-leaves.
783	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
784	* @param uLeaf The leaf we're adding.
785	* @param uSubLeaf The sub-leaf number.
786	* @param fSubLeafMask The sub-leaf mask.
787	* @param uEax The EAX value.
788	* @param uEbx The EBX value.
789	* @param uEcx The ECX value.
790	* @param uEdx The EDX value.
791	* @param fFlags The flags.
792	*/
793	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
794	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
795	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
796	{
797	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
798	return VERR_NO_MEMORY;
799
800	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
801	Assert( *pcLeaves == 0
802	\|\| pNew[-1].uLeaf < uLeaf
803	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
804
805	pNew->uLeaf = uLeaf;
806	pNew->uSubLeaf = uSubLeaf;
807	pNew->fSubLeafMask = fSubLeafMask;
808	pNew->uEax = uEax;
809	pNew->uEbx = uEbx;
810	pNew->uEcx = uEcx;
811	pNew->uEdx = uEdx;
812	pNew->fFlags = fFlags;
813
814	*pcLeaves += 1;
815	return VINF_SUCCESS;
816	}
817
818
819	/**
820	* Checks that we've updated the CPUID leaves array correctly.
821	*
822	* This is a no-op in non-strict builds.
823	*
824	* @param paLeaves The leaves array.
825	* @param cLeaves The number of leaves.
826	*/
827	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
828	{
829	#ifdef VBOX_STRICT
830	for (uint32_t i = 1; i < cLeaves; i++)
831	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
832	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
833	else
834	{
835	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
836	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
837	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
838	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
839	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
840	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
841	}
842	#else
843	NOREF(paLeaves);
844	NOREF(cLeaves);
845	#endif
846	}
847
848
849	/**
850	* Inserts a CPU ID leaf, replacing any existing ones.
851	*
852	* When inserting a simple leaf where we already got a series of sub-leaves with
853	* the same leaf number (eax), the simple leaf will replace the whole series.
854	*
855	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
856	* host-context heap and has only been allocated/reallocated by the
857	* cpumR3CpuIdEnsureSpace function.
858	*
859	* @returns VBox status code.
860	* @param pVM The cross context VM structure. If NULL, use
861	* the process heap, otherwise the VM's hyper heap.
862	* @param ppaLeaves Pointer to the pointer to the array of sorted
863	* CPUID leaves and sub-leaves. Must be NULL if using
864	* the hyper heap.
865	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
866	* be NULL if using the hyper heap.
867	* @param pNewLeaf Pointer to the data of the new leaf we're about to
868	* insert.
869	*/
870	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
871	{
872	/*
873	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
874	*/
875	if (pVM)
876	{
877	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
878	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
879
880	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
881	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
882	}
883
884	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
885	uint32_t cLeaves = *pcLeaves;
886
887	/*
888	* Validate the new leaf a little.
889	*/
890	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
891	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
892	VERR_INVALID_FLAGS);
893	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
894	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
895	VERR_INVALID_PARAMETER);
896	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
897	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
898	VERR_INVALID_PARAMETER);
899	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
900	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
901	VERR_INVALID_PARAMETER);
902
903	/*
904	* Find insertion point. The lazy bird uses the same excuse as in
905	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
906	*/
907	uint32_t i;
908	if ( cLeaves > 0
909	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
910	{
911	/* Add at end. */
912	i = cLeaves;
913	}
914	else if ( cLeaves > 0
915	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
916	{
917	/* Either replacing the last leaf or dealing with sub-leaves. Spool
918	back to the first sub-leaf to pretend we did the linear search. */
919	i = cLeaves - 1;
920	while ( i > 0
921	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
922	i--;
923	}
924	else
925	{
926	/* Linear search from the start. */
927	i = 0;
928	while ( i < cLeaves
929	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
930	i++;
931	}
932	if ( i < cLeaves
933	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
934	{
935	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
936	{
937	/*
938	* The sub-leaf mask differs, replace all existing leaves with the
939	* same leaf number.
940	*/
941	uint32_t c = 1;
942	while ( i + c < cLeaves
943	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
944	c++;
945	if (c > 1 && i + c < cLeaves)
946	{
947	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
948	*pcLeaves = cLeaves -= c - 1;
949	}
950
951	paLeaves[i] = *pNewLeaf;
952	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
953	return VINF_SUCCESS;
954	}
955
956	/* Find sub-leaf insertion point. */
957	while ( i < cLeaves
958	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
959	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
960	i++;
961
962	/*
963	* If we've got an exactly matching leaf, replace it.
964	*/
965	if ( i < cLeaves
966	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
967	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
968	{
969	paLeaves[i] = *pNewLeaf;
970	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
971	return VINF_SUCCESS;
972	}
973	}
974
975	/*
976	* Adding a new leaf at 'i'.
977	*/
978	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
979	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
980	if (!paLeaves)
981	return VERR_NO_MEMORY;
982
983	if (i < cLeaves)
984	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
985	*pcLeaves += 1;
986	paLeaves[i] = *pNewLeaf;
987
988	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
989	return VINF_SUCCESS;
990	}
991
992
993	#ifndef IN_VBOX_CPU_REPORT
994	/**
995	* Removes a range of CPUID leaves.
996	*
997	* This will not reallocate the array.
998	*
999	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1000	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1001	* @param uFirst The first leaf.
1002	* @param uLast The last leaf.
1003	*/
1004	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1005	{
1006	uint32_t cLeaves = *pcLeaves;
1007
1008	Assert(uFirst <= uLast);
1009
1010	/*
1011	* Find the first one.
1012	*/
1013	uint32_t iFirst = 0;
1014	while ( iFirst < cLeaves
1015	&& paLeaves[iFirst].uLeaf < uFirst)
1016	iFirst++;
1017
1018	/*
1019	* Find the end (last + 1).
1020	*/
1021	uint32_t iEnd = iFirst;
1022	while ( iEnd < cLeaves
1023	&& paLeaves[iEnd].uLeaf <= uLast)
1024	iEnd++;
1025
1026	/*
1027	* Adjust the array if anything needs removing.
1028	*/
1029	if (iFirst < iEnd)
1030	{
1031	if (iEnd < cLeaves)
1032	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1033	*pcLeaves = cLeaves -= (iEnd - iFirst);
1034	}
1035
1036	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1037	}
1038	#endif /* IN_VBOX_CPU_REPORT */
1039
1040
1041	/**
1042	* Checks if ECX make a difference when reading a given CPUID leaf.
1043	*
1044	* @returns @c true if it does, @c false if it doesn't.
1045	* @param uLeaf The leaf we're reading.
1046	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1047	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1048	* final sub-leaf (for leaf 0xb only).
1049	*/
1050	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1051	{
1052	*pfFinalEcxUnchanged = false;
1053
1054	uint32_t auCur[4];
1055	uint32_t auPrev[4];
1056	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1057
1058	/* Look for sub-leaves. */
1059	uint32_t uSubLeaf = 1;
1060	for (;;)
1061	{
1062	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1063	if (memcmp(auCur, auPrev, sizeof(auCur)))
1064	break;
1065
1066	/* Advance / give up. */
1067	uSubLeaf++;
1068	if (uSubLeaf >= 64)
1069	{
1070	*pcSubLeaves = 1;
1071	return false;
1072	}
1073	}
1074
1075	/* Count sub-leaves. */
1076	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1077	uint32_t cRepeats = 0;
1078	uSubLeaf = 0;
1079	for (;;)
1080	{
1081	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1082
1083	/* Figuring out when to stop isn't entirely straight forward as we need
1084	to cover undocumented behavior up to a point and implementation shortcuts. */
1085
1086	/* 1. Look for more than 4 repeating value sets. */
1087	if ( auCur[0] == auPrev[0]
1088	&& auCur[1] == auPrev[1]
1089	&& ( auCur[2] == auPrev[2]
1090	\|\| ( auCur[2] == uSubLeaf
1091	&& auPrev[2] == uSubLeaf - 1) )
1092	&& auCur[3] == auPrev[3])
1093	{
1094	if ( uLeaf != 0xd
1095	\|\| uSubLeaf >= 64
1096	\|\| ( auCur[0] == 0
1097	&& auCur[1] == 0
1098	&& auCur[2] == 0
1099	&& auCur[3] == 0
1100	&& auPrev[2] == 0) )
1101	cRepeats++;
1102	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1103	break;
1104	}
1105	else
1106	cRepeats = 0;
1107
1108	/* 2. Look for zero values. */
1109	if ( auCur[0] == 0
1110	&& auCur[1] == 0
1111	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1112	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1113	&& uSubLeaf >= cMinLeaves)
1114	{
1115	cRepeats = 0;
1116	break;
1117	}
1118
1119	/* 3. Leaf 0xb level type 0 check. */
1120	if ( uLeaf == 0xb
1121	&& (auCur[2] & 0xff00) == 0
1122	&& (auPrev[2] & 0xff00) == 0)
1123	{
1124	cRepeats = 0;
1125	break;
1126	}
1127
1128	/* 99. Give up. */
1129	if (uSubLeaf >= 128)
1130	{
1131	#ifndef IN_VBOX_CPU_REPORT
1132	/* Ok, limit it according to the documentation if possible just to
1133	avoid annoying users with these detection issues. */
1134	uint32_t cDocLimit = UINT32_MAX;
1135	if (uLeaf == 0x4)
1136	cDocLimit = 4;
1137	else if (uLeaf == 0x7)
1138	cDocLimit = 1;
1139	else if (uLeaf == 0xd)
1140	cDocLimit = 63;
1141	else if (uLeaf == 0xf)
1142	cDocLimit = 2;
1143	if (cDocLimit != UINT32_MAX)
1144	{
1145	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1146	*pcSubLeaves = cDocLimit + 3;
1147	return true;
1148	}
1149	#endif
1150	*pcSubLeaves = UINT32_MAX;
1151	return true;
1152	}
1153
1154	/* Advance. */
1155	uSubLeaf++;
1156	memcpy(auPrev, auCur, sizeof(auCur));
1157	}
1158
1159	/* Standard exit. */
1160	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1161	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1162	if (*pcSubLeaves == 0)
1163	*pcSubLeaves = 1;
1164	return true;
1165	}
1166
1167
1168	/**
1169	* Gets a CPU ID leaf.
1170	*
1171	* @returns VBox status code.
1172	* @param pVM The cross context VM structure.
1173	* @param pLeaf Where to store the found leaf.
1174	* @param uLeaf The leaf to locate.
1175	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1176	*/
1177	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1178	{
1179	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1180	uLeaf, uSubLeaf);
1181	if (pcLeaf)
1182	{
1183	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1184	return VINF_SUCCESS;
1185	}
1186
1187	return VERR_NOT_FOUND;
1188	}
1189
1190
1191	/**
1192	* Inserts a CPU ID leaf, replacing any existing ones.
1193	*
1194	* @returns VBox status code.
1195	* @param pVM The cross context VM structure.
1196	* @param pNewLeaf Pointer to the leaf being inserted.
1197	*/
1198	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1199	{
1200	/*
1201	* Validate parameters.
1202	*/
1203	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1204	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1205
1206	/*
1207	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1208	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1209	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1210	*/
1211	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1212	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1213	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1214	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1215	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1216	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1217	{
1218	return VERR_NOT_SUPPORTED;
1219	}
1220
1221	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1222	}
1223
1224	/**
1225	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1226	*
1227	* @returns VBox status code.
1228	* @param ppaLeaves Where to return the array pointer on success.
1229	* Use RTMemFree to release.
1230	* @param pcLeaves Where to return the size of the array on
1231	* success.
1232	*/
1233	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1234	{
1235	*ppaLeaves = NULL;
1236	*pcLeaves = 0;
1237
1238	/*
1239	* Try out various candidates. This must be sorted!
1240	*/
1241	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1242	{
1243	{ UINT32_C(0x00000000), false },
1244	{ UINT32_C(0x10000000), false },
1245	{ UINT32_C(0x20000000), false },
1246	{ UINT32_C(0x30000000), false },
1247	{ UINT32_C(0x40000000), false },
1248	{ UINT32_C(0x50000000), false },
1249	{ UINT32_C(0x60000000), false },
1250	{ UINT32_C(0x70000000), false },
1251	{ UINT32_C(0x80000000), false },
1252	{ UINT32_C(0x80860000), false },
1253	{ UINT32_C(0x8ffffffe), true },
1254	{ UINT32_C(0x8fffffff), true },
1255	{ UINT32_C(0x90000000), false },
1256	{ UINT32_C(0xa0000000), false },
1257	{ UINT32_C(0xb0000000), false },
1258	{ UINT32_C(0xc0000000), false },
1259	{ UINT32_C(0xd0000000), false },
1260	{ UINT32_C(0xe0000000), false },
1261	{ UINT32_C(0xf0000000), false },
1262	};
1263
1264	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1265	{
1266	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1267	uint32_t uEax, uEbx, uEcx, uEdx;
1268	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1269
1270	/*
1271	* Does EAX look like a typical leaf count value?
1272	*/
1273	if ( uEax > uLeaf
1274	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1275	{
1276	/* Yes, dump them. */
1277	uint32_t cLeaves = uEax - uLeaf + 1;
1278	while (cLeaves-- > 0)
1279	{
1280	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1281
1282	uint32_t fFlags = 0;
1283
1284	/* There are currently three known leaves containing an APIC ID
1285	that needs EMT specific attention */
1286	if (uLeaf == 1)
1287	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1288	else if (uLeaf == 0xb && uEcx != 0)
1289	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1290	else if ( uLeaf == UINT32_C(0x8000001e)
1291	&& ( uEax
1292	\|\| uEbx
1293	\|\| uEdx
1294	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1295	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1296
1297	/* The APIC bit is per-VCpu and needs flagging. */
1298	if (uLeaf == 1)
1299	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1300	else if ( uLeaf == UINT32_C(0x80000001)
1301	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1302	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1303	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1304
1305	/* Check three times here to reduce the chance of CPU migration
1306	resulting in false positives with things like the APIC ID. */
1307	uint32_t cSubLeaves;
1308	bool fFinalEcxUnchanged;
1309	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1310	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1311	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1312	{
1313	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1314	{
1315	/* This shouldn't happen. But in case it does, file all
1316	relevant details in the release log. */
1317	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1318	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1319	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1320	{
1321	uint32_t auTmp[4];
1322	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1323	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1324	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1325	}
1326	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1327	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1328	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1329	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1330	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1331	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1332	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1333	}
1334
1335	if (fFinalEcxUnchanged)
1336	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1337
1338	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1339	{
1340	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1341	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1342	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1343	if (RT_FAILURE(rc))
1344	return rc;
1345	}
1346	}
1347	else
1348	{
1349	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1350	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1351	if (RT_FAILURE(rc))
1352	return rc;
1353	}
1354
1355	/* next */
1356	uLeaf++;
1357	}
1358	}
1359	/*
1360	* Special CPUIDs needs special handling as they don't follow the
1361	* leaf count principle used above.
1362	*/
1363	else if (s_aCandidates[iOuter].fSpecial)
1364	{
1365	bool fKeep = false;
1366	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1367	fKeep = true;
1368	else if ( uLeaf == 0x8fffffff
1369	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1370	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1371	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1372	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1373	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1374	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1375	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1376	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1377	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1378	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1379	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1380	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1381	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1382	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1383	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1384	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1385	fKeep = true;
1386	if (fKeep)
1387	{
1388	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1389	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1390	if (RT_FAILURE(rc))
1391	return rc;
1392	}
1393	}
1394	}
1395
1396	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1397	return VINF_SUCCESS;
1398	}
1399
1400
1401	/**
1402	* Determines the method the CPU uses to handle unknown CPUID leaves.
1403	*
1404	* @returns VBox status code.
1405	* @param penmUnknownMethod Where to return the method.
1406	* @param pDefUnknown Where to return default unknown values. This
1407	* will be set, even if the resulting method
1408	* doesn't actually needs it.
1409	*/
1410	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1411	{
1412	uint32_t uLastStd = ASMCpuId_EAX(0);
1413	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1414	if (!ASMIsValidExtRange(uLastExt))
1415	uLastExt = 0x80000000;
1416
1417	uint32_t auChecks[] =
1418	{
1419	uLastStd + 1,
1420	uLastStd + 5,
1421	uLastStd + 8,
1422	uLastStd + 32,
1423	uLastStd + 251,
1424	uLastExt + 1,
1425	uLastExt + 8,
1426	uLastExt + 15,
1427	uLastExt + 63,
1428	uLastExt + 255,
1429	0x7fbbffcc,
1430	0x833f7872,
1431	0xefff2353,
1432	0x35779456,
1433	0x1ef6d33e,
1434	};
1435
1436	static const uint32_t s_auValues[] =
1437	{
1438	0xa95d2156,
1439	0x00000001,
1440	0x00000002,
1441	0x00000008,
1442	0x00000000,
1443	0x55773399,
1444	0x93401769,
1445	0x12039587,
1446	};
1447
1448	/*
1449	* Simple method, all zeros.
1450	*/
1451	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1452	pDefUnknown->uEax = 0;
1453	pDefUnknown->uEbx = 0;
1454	pDefUnknown->uEcx = 0;
1455	pDefUnknown->uEdx = 0;
1456
1457	/*
1458	* Intel has been observed returning the last standard leaf.
1459	*/
1460	uint32_t auLast[4];
1461	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1462
1463	uint32_t cChecks = RT_ELEMENTS(auChecks);
1464	while (cChecks > 0)
1465	{
1466	uint32_t auCur[4];
1467	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1468	if (memcmp(auCur, auLast, sizeof(auCur)))
1469	break;
1470	cChecks--;
1471	}
1472	if (cChecks == 0)
1473	{
1474	/* Now, what happens when the input changes? Esp. ECX. */
1475	uint32_t cTotal = 0;
1476	uint32_t cSame = 0;
1477	uint32_t cLastWithEcx = 0;
1478	uint32_t cNeither = 0;
1479	uint32_t cValues = RT_ELEMENTS(s_auValues);
1480	while (cValues > 0)
1481	{
1482	uint32_t uValue = s_auValues[cValues - 1];
1483	uint32_t auLastWithEcx[4];
1484	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1485	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1486
1487	cChecks = RT_ELEMENTS(auChecks);
1488	while (cChecks > 0)
1489	{
1490	uint32_t auCur[4];
1491	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1492	if (!memcmp(auCur, auLast, sizeof(auCur)))
1493	{
1494	cSame++;
1495	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1496	cLastWithEcx++;
1497	}
1498	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1499	cLastWithEcx++;
1500	else
1501	cNeither++;
1502	cTotal++;
1503	cChecks--;
1504	}
1505	cValues--;
1506	}
1507
1508	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1509	if (cSame == cTotal)
1510	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1511	else if (cLastWithEcx == cTotal)
1512	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1513	else
1514	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1515	pDefUnknown->uEax = auLast[0];
1516	pDefUnknown->uEbx = auLast[1];
1517	pDefUnknown->uEcx = auLast[2];
1518	pDefUnknown->uEdx = auLast[3];
1519	return VINF_SUCCESS;
1520	}
1521
1522	/*
1523	* Unchanged register values?
1524	*/
1525	cChecks = RT_ELEMENTS(auChecks);
1526	while (cChecks > 0)
1527	{
1528	uint32_t const uLeaf = auChecks[cChecks - 1];
1529	uint32_t cValues = RT_ELEMENTS(s_auValues);
1530	while (cValues > 0)
1531	{
1532	uint32_t uValue = s_auValues[cValues - 1];
1533	uint32_t auCur[4];
1534	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1535	if ( auCur[0] != uLeaf
1536	\|\| auCur[1] != uValue
1537	\|\| auCur[2] != uValue
1538	\|\| auCur[3] != uValue)
1539	break;
1540	cValues--;
1541	}
1542	if (cValues != 0)
1543	break;
1544	cChecks--;
1545	}
1546	if (cChecks == 0)
1547	{
1548	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1549	return VINF_SUCCESS;
1550	}
1551
1552	/*
1553	* Just go with the simple method.
1554	*/
1555	return VINF_SUCCESS;
1556	}
1557
1558
1559	/**
1560	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1561	*
1562	* @returns Read only name string.
1563	* @param enmUnknownMethod The method to translate.
1564	*/
1565	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1566	{
1567	switch (enmUnknownMethod)
1568	{
1569	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1570	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1571	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1572	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1573
1574	case CPUMUNKNOWNCPUID_INVALID:
1575	case CPUMUNKNOWNCPUID_END:
1576	case CPUMUNKNOWNCPUID_32BIT_HACK:
1577	break;
1578	}
1579	return "Invalid-unknown-CPUID-method";
1580	}
1581
1582
1583	/**
1584	* Detect the CPU vendor give n the
1585	*
1586	* @returns The vendor.
1587	* @param uEAX EAX from CPUID(0).
1588	* @param uEBX EBX from CPUID(0).
1589	* @param uECX ECX from CPUID(0).
1590	* @param uEDX EDX from CPUID(0).
1591	*/
1592	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1593	{
1594	if (ASMIsValidStdRange(uEAX))
1595	{
1596	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1597	return CPUMCPUVENDOR_AMD;
1598
1599	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1600	return CPUMCPUVENDOR_INTEL;
1601
1602	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1603	return CPUMCPUVENDOR_VIA;
1604
1605	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1606	&& uECX == UINT32_C(0x64616574)
1607	&& uEDX == UINT32_C(0x736E4978))
1608	return CPUMCPUVENDOR_CYRIX;
1609
1610	/* "Geode by NSC", example: family 5, model 9. */
1611
1612	/** @todo detect the other buggers... */
1613	}
1614
1615	return CPUMCPUVENDOR_UNKNOWN;
1616	}
1617
1618
1619	/**
1620	* Translates a CPU vendor enum value into the corresponding string constant.
1621	*
1622	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1623	* value name. This can be useful when generating code.
1624	*
1625	* @returns Read only name string.
1626	* @param enmVendor The CPU vendor value.
1627	*/
1628	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1629	{
1630	switch (enmVendor)
1631	{
1632	case CPUMCPUVENDOR_INTEL: return "INTEL";
1633	case CPUMCPUVENDOR_AMD: return "AMD";
1634	case CPUMCPUVENDOR_VIA: return "VIA";
1635	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1636	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1637
1638	case CPUMCPUVENDOR_INVALID:
1639	case CPUMCPUVENDOR_32BIT_HACK:
1640	break;
1641	}
1642	return "Invalid-cpu-vendor";
1643	}
1644
1645
1646	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1647	{
1648	/* Could do binary search, doing linear now because I'm lazy. */
1649	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1650	while (cLeaves-- > 0)
1651	{
1652	if (pLeaf->uLeaf == uLeaf)
1653	return pLeaf;
1654	pLeaf++;
1655	}
1656	return NULL;
1657	}
1658
1659
1660	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1661	{
1662	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1663	if ( !pLeaf
1664	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1665	return pLeaf;
1666
1667	/* Linear sub-leaf search. Lazy as usual. */
1668	cLeaves -= pLeaf - paLeaves;
1669	while ( cLeaves-- > 0
1670	&& pLeaf->uLeaf == uLeaf)
1671	{
1672	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1673	return pLeaf;
1674	pLeaf++;
1675	}
1676
1677	return NULL;
1678	}
1679
1680
1681	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1682	{
1683	RT_ZERO(*pFeatures);
1684	if (cLeaves >= 2)
1685	{
1686	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1687	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1688	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1689	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1690	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1691	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1692
1693	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1694	pStd0Leaf->uEbx,
1695	pStd0Leaf->uEcx,
1696	pStd0Leaf->uEdx);
1697	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1698	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1699	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1700	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1701	pFeatures->uFamily,
1702	pFeatures->uModel,
1703	pFeatures->uStepping);
1704
1705	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1706	if (pExtLeaf8)
1707	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1708	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1709	pFeatures->cMaxPhysAddrWidth = 36;
1710	else
1711	pFeatures->cMaxPhysAddrWidth = 32;
1712
1713	/* Standard features. */
1714	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1715	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1716	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1717	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1718	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1719	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1720	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1721	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1722	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1723	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1724	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1725	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1726	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1727	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1728	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1729	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1730	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1731	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1732	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1733	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1734	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1735	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1736	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1737	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1738	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1739	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1740	/* VMX sub-features will be initialized in cpumR3InitVmxCpuFeatures(). */
1741
1742	/* Structured extended features. */
1743	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1744	if (pSxfLeaf0)
1745	{
1746	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1747	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1748	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1749	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1750	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1751
1752	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1753	pFeatures->fIbrs = pFeatures->fIbpb;
1754	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1755	#if 0 // Disabled until IA32_ARCH_CAPABILITIES support can be tested
1756	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1757	#endif
1758	}
1759
1760	/* MWAIT/MONITOR leaf. */
1761	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1762	if (pMWaitLeaf)
1763	{
1764	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1765	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1766	}
1767
1768	/* Extended features. */
1769	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1770	if (pExtLeaf)
1771	{
1772	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1773	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1774	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1775	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1776	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1777	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1778	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1779	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1780	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1781	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1782	}
1783
1784	/* VMX (VMXON, VMCS region and related data structures') physical address width (depends on long-mode). */
1785	pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
1786
1787	if ( pExtLeaf
1788	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1789	{
1790	/* AMD features. */
1791	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1792	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1793	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1794	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1795	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1796	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1797	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1798	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1799	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1800	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1801	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1802	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1803	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1804	if (pFeatures->fSvm)
1805	{
1806	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1807	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1808	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1809	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1810	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1811	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1812	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1813	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1814	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1815	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1816	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1817	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1818	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1819	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1820	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1821	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1822	}
1823	}
1824
1825	/*
1826	* Quirks.
1827	*/
1828	pFeatures->fLeakyFxSR = pExtLeaf
1829	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1830	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1831	&& pFeatures->uFamily >= 6 /* K7 and up */;
1832
1833	/*
1834	* Max extended (/FPU) state.
1835	*/
1836	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1837	if (pFeatures->fXSaveRstor)
1838	{
1839	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1840	if (pXStateLeaf0)
1841	{
1842	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1843	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1844	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1845	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1846	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1847	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1848	{
1849	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1850
1851	/* (paranoia:) */
1852	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1853	if ( pXStateLeaf1
1854	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1855	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1856	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1857	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1858	}
1859	else
1860	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1861	pFeatures->fXSaveRstor = 0);
1862	}
1863	else
1864	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1865	pFeatures->fXSaveRstor = 0);
1866	}
1867	}
1868	else
1869	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1870	return VINF_SUCCESS;
1871	}
1872
1873
1874	/*
1875	*
1876	* Init related code.
1877	* Init related code.
1878	* Init related code.
1879	*
1880	*
1881	*/
1882	#ifdef VBOX_IN_VMM
1883
1884
1885	/**
1886	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1887	*
1888	* This ignores the fSubLeafMask.
1889	*
1890	* @returns Pointer to the matching leaf, or NULL if not found.
1891	* @param paLeaves The CPUID leaves to search. This is sorted.
1892	* @param cLeaves The number of leaves in the array.
1893	* @param uLeaf The leaf to locate.
1894	* @param uSubLeaf The subleaf to locate.
1895	*/
1896	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1897	{
1898	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1899	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1900	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1901	if (iEnd)
1902	{
1903	uint32_t iBegin = 0;
1904	for (;;)
1905	{
1906	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1907	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1908	if (uNeedle < uCur)
1909	{
1910	if (i > iBegin)
1911	iEnd = i;
1912	else
1913	break;
1914	}
1915	else if (uNeedle > uCur)
1916	{
1917	if (i + 1 < iEnd)
1918	iBegin = i + 1;
1919	else
1920	break;
1921	}
1922	else
1923	return &paLeaves[i];
1924	}
1925	}
1926	return NULL;
1927	}
1928
1929
1930	/**
1931	* Loads MSR range overrides.
1932	*
1933	* This must be called before the MSR ranges are moved from the normal heap to
1934	* the hyper heap!
1935	*
1936	* @returns VBox status code (VMSetError called).
1937	* @param pVM The cross context VM structure.
1938	* @param pMsrNode The CFGM node with the MSR overrides.
1939	*/
1940	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1941	{
1942	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1943	{
1944	/*
1945	* Assemble a valid MSR range.
1946	*/
1947	CPUMMSRRANGE MsrRange;
1948	MsrRange.offCpumCpu = 0;
1949	MsrRange.fReserved = 0;
1950
1951	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1952	if (RT_FAILURE(rc))
1953	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1954
1955	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1956	if (RT_FAILURE(rc))
1957	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1958	MsrRange.szName, rc);
1959
1960	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1961	if (RT_FAILURE(rc))
1962	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1963	MsrRange.szName, rc);
1964
1965	char szType[32];
1966	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1967	if (RT_FAILURE(rc))
1968	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1969	MsrRange.szName, rc);
1970	if (!RTStrICmp(szType, "FixedValue"))
1971	{
1972	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1973	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1974
1975	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1976	if (RT_FAILURE(rc))
1977	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1978	MsrRange.szName, rc);
1979
1980	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1981	if (RT_FAILURE(rc))
1982	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1983	MsrRange.szName, rc);
1984
1985	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1986	if (RT_FAILURE(rc))
1987	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1988	MsrRange.szName, rc);
1989	}
1990	else
1991	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1992	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1993
1994	/*
1995	* Insert the range into the table (replaces/splits/shrinks existing
1996	* MSR ranges).
1997	*/
1998	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1999	&MsrRange);
2000	if (RT_FAILURE(rc))
2001	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
2002	}
2003
2004	return VINF_SUCCESS;
2005	}
2006
2007
2008	/**
2009	* Loads CPUID leaf overrides.
2010	*
2011	* This must be called before the CPUID leaves are moved from the normal
2012	* heap to the hyper heap!
2013	*
2014	* @returns VBox status code (VMSetError called).
2015	* @param pVM The cross context VM structure.
2016	* @param pParentNode The CFGM node with the CPUID leaves.
2017	* @param pszLabel How to label the overrides we're loading.
2018	*/
2019	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2020	{
2021	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2022	{
2023	/*
2024	* Get the leaf and subleaf numbers.
2025	*/
2026	char szName[128];
2027	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2028	if (RT_FAILURE(rc))
2029	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2030
2031	/* The leaf number is either specified directly or thru the node name. */
2032	uint32_t uLeaf;
2033	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2034	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2035	{
2036	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2037	if (rc != VINF_SUCCESS)
2038	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2039	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2040	}
2041	else if (RT_FAILURE(rc))
2042	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2043	pszLabel, szName, rc);
2044
2045	uint32_t uSubLeaf;
2046	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2047	if (RT_FAILURE(rc))
2048	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2049	pszLabel, szName, rc);
2050
2051	uint32_t fSubLeafMask;
2052	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2053	if (RT_FAILURE(rc))
2054	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2055	pszLabel, szName, rc);
2056
2057	/*
2058	* Look up the specified leaf, since the output register values
2059	* defaults to any existing values. This allows overriding a single
2060	* register, without needing to know the other values.
2061	*/
2062	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2063	CPUMCPUIDLEAF Leaf;
2064	if (pLeaf)
2065	Leaf = *pLeaf;
2066	else
2067	RT_ZERO(Leaf);
2068	Leaf.uLeaf = uLeaf;
2069	Leaf.uSubLeaf = uSubLeaf;
2070	Leaf.fSubLeafMask = fSubLeafMask;
2071
2072	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2073	if (RT_FAILURE(rc))
2074	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2075	pszLabel, szName, rc);
2076	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2077	if (RT_FAILURE(rc))
2078	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2079	pszLabel, szName, rc);
2080	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2081	if (RT_FAILURE(rc))
2082	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2083	pszLabel, szName, rc);
2084	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2085	if (RT_FAILURE(rc))
2086	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2087	pszLabel, szName, rc);
2088
2089	/*
2090	* Insert the leaf into the table (replaces existing ones).
2091	*/
2092	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2093	&Leaf);
2094	if (RT_FAILURE(rc))
2095	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2096	}
2097
2098	return VINF_SUCCESS;
2099	}
2100
2101
2102
2103	/**
2104	* Fetches overrides for a CPUID leaf.
2105	*
2106	* @returns VBox status code.
2107	* @param pLeaf The leaf to load the overrides into.
2108	* @param pCfgNode The CFGM node containing the overrides
2109	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2110	* @param iLeaf The CPUID leaf number.
2111	*/
2112	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2113	{
2114	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2115	if (pLeafNode)
2116	{
2117	uint32_t u32;
2118	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2119	if (RT_SUCCESS(rc))
2120	pLeaf->uEax = u32;
2121	else
2122	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2123
2124	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2125	if (RT_SUCCESS(rc))
2126	pLeaf->uEbx = u32;
2127	else
2128	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2129
2130	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2131	if (RT_SUCCESS(rc))
2132	pLeaf->uEcx = u32;
2133	else
2134	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2135
2136	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2137	if (RT_SUCCESS(rc))
2138	pLeaf->uEdx = u32;
2139	else
2140	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2141
2142	}
2143	return VINF_SUCCESS;
2144	}
2145
2146
2147	/**
2148	* Load the overrides for a set of CPUID leaves.
2149	*
2150	* @returns VBox status code.
2151	* @param paLeaves The leaf array.
2152	* @param cLeaves The number of leaves.
2153	* @param uStart The start leaf number.
2154	* @param pCfgNode The CFGM node containing the overrides
2155	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2156	*/
2157	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2158	{
2159	for (uint32_t i = 0; i < cLeaves; i++)
2160	{
2161	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2162	if (RT_FAILURE(rc))
2163	return rc;
2164	}
2165
2166	return VINF_SUCCESS;
2167	}
2168
2169
2170	/**
2171	* Installs the CPUID leaves and explods the data into structures like
2172	* GuestFeatures and CPUMCTX::aoffXState.
2173	*
2174	* @returns VBox status code.
2175	* @param pVM The cross context VM structure.
2176	* @param pCpum The CPUM part of @a VM.
2177	* @param paLeaves The leaves. These will be copied (but not freed).
2178	* @param cLeaves The number of leaves.
2179	*/
2180	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
2181	{
2182	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2183
2184	/*
2185	* Install the CPUID information.
2186	*/
2187	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2188	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2189
2190	AssertLogRelRCReturn(rc, rc);
2191	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2192	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2193	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2194	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2195	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2196
2197	/*
2198	* Update the default CPUID leaf if necessary.
2199	*/
2200	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2201	{
2202	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2203	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2204	{
2205	/* We don't use CPUID(0).eax here because of the NT hack that only
2206	changes that value without actually removing any leaves. */
2207	uint32_t i = 0;
2208	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2209	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2210	{
2211	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2212	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2213	i++;
2214	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2215	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2216	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2217	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2218	}
2219	break;
2220	}
2221	default:
2222	break;
2223	}
2224
2225	/*
2226	* Explode the guest CPU features.
2227	*/
2228	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
2229	AssertLogRelRCReturn(rc, rc);
2230
2231	/*
2232	* Adjust the scalable bus frequency according to the CPUID information
2233	* we're now using.
2234	*/
2235	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2236	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2237	? UINT64_C(100000000) /* 100MHz */
2238	: UINT64_C(133333333); /* 133MHz */
2239
2240	/*
2241	* Populate the legacy arrays. Currently used for everything, later only
2242	* for patch manager.
2243	*/
2244	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2245	{
2246	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2247	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2248	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2249	};
2250	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2251	{
2252	uint32_t cLeft = aOldRanges[i].cCpuIds;
2253	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2254	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2255	while (cLeft-- > 0)
2256	{
2257	uLeaf--;
2258	pLegacyLeaf--;
2259
2260	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2261	if (pLeaf)
2262	{
2263	pLegacyLeaf->uEax = pLeaf->uEax;
2264	pLegacyLeaf->uEbx = pLeaf->uEbx;
2265	pLegacyLeaf->uEcx = pLeaf->uEcx;
2266	pLegacyLeaf->uEdx = pLeaf->uEdx;
2267	}
2268	else
2269	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2270	}
2271	}
2272
2273	/*
2274	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2275	*/
2276	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2277	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2278	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2279	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2280	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2281	{
2282	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2283	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2284	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2285	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2286	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2287	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2288	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2289	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2290	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2291	pCpum->GuestFeatures.cbMaxExtendedState),
2292	VERR_CPUM_IPE_1);
2293	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2294	}
2295	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2296
2297	/* Copy the CPU #0 data to the other CPUs. */
2298	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2299	{
2300	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2301	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2302	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2303	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2304	}
2305
2306	return VINF_SUCCESS;
2307	}
2308
2309
2310	/** @name Instruction Set Extension Options
2311	* @{ */
2312	/** Configuration option type (extended boolean, really). */
2313	typedef uint8_t CPUMISAEXTCFG;
2314	/** Always disable the extension. */
2315	#define CPUMISAEXTCFG_DISABLED false
2316	/** Enable the extension if it's supported by the host CPU. */
2317	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2318	/** Enable the extension if it's supported by the host CPU, but don't let
2319	* the portable CPUID feature disable it. */
2320	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2321	/** Always enable the extension. */
2322	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2323	/** @} */
2324
2325	/**
2326	* CPUID Configuration (from CFGM).
2327	*
2328	* @remarks The members aren't document since we would only be duplicating the
2329	* \@cfgm entries in cpumR3CpuIdReadConfig.
2330	*/
2331	typedef struct CPUMCPUIDCONFIG
2332	{
2333	bool fNt4LeafLimit;
2334	bool fInvariantTsc;
2335	bool fForceVme;
2336	bool fNestedHWVirt;
2337
2338	CPUMISAEXTCFG enmCmpXchg16b;
2339	CPUMISAEXTCFG enmMonitor;
2340	CPUMISAEXTCFG enmMWaitExtensions;
2341	CPUMISAEXTCFG enmSse41;
2342	CPUMISAEXTCFG enmSse42;
2343	CPUMISAEXTCFG enmAvx;
2344	CPUMISAEXTCFG enmAvx2;
2345	CPUMISAEXTCFG enmXSave;
2346	CPUMISAEXTCFG enmAesNi;
2347	CPUMISAEXTCFG enmPClMul;
2348	CPUMISAEXTCFG enmPopCnt;
2349	CPUMISAEXTCFG enmMovBe;
2350	CPUMISAEXTCFG enmRdRand;
2351	CPUMISAEXTCFG enmRdSeed;
2352	CPUMISAEXTCFG enmCLFlushOpt;
2353	CPUMISAEXTCFG enmFsGsBase;
2354	CPUMISAEXTCFG enmPcid;
2355	CPUMISAEXTCFG enmInvpcid;
2356
2357	CPUMISAEXTCFG enmAbm;
2358	CPUMISAEXTCFG enmSse4A;
2359	CPUMISAEXTCFG enmMisAlnSse;
2360	CPUMISAEXTCFG enm3dNowPrf;
2361	CPUMISAEXTCFG enmAmdExtMmx;
2362
2363	uint32_t uMaxStdLeaf;
2364	uint32_t uMaxExtLeaf;
2365	uint32_t uMaxCentaurLeaf;
2366	uint32_t uMaxIntelFamilyModelStep;
2367	char szCpuName[128];
2368	} CPUMCPUIDCONFIG;
2369	/** Pointer to CPUID config (from CFGM). */
2370	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2371
2372
2373	/**
2374	* Mini CPU selection support for making Mac OS X happy.
2375	*
2376	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2377	*
2378	* @param pCpum The CPUM instance data.
2379	* @param pConfig The CPUID configuration we've read from CFGM.
2380	*/
2381	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2382	{
2383	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2384	{
2385	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2386	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2387	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2388	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2389	0);
2390	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2391	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2392	{
2393	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2394	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2395	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2396	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2397	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2398	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2399	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2400	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2401	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2402	pStdFeatureLeaf->uEax = uNew;
2403	}
2404	}
2405	}
2406
2407
2408
2409	/**
2410	* Limit it the number of entries, zapping the remainder.
2411	*
2412	* The limits are masking off stuff about power saving and similar, this
2413	* is perhaps a bit crudely done as there is probably some relatively harmless
2414	* info too in these leaves (like words about having a constant TSC).
2415	*
2416	* @param pCpum The CPUM instance data.
2417	* @param pConfig The CPUID configuration we've read from CFGM.
2418	*/
2419	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2420	{
2421	/*
2422	* Standard leaves.
2423	*/
2424	uint32_t uSubLeaf = 0;
2425	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2426	if (pCurLeaf)
2427	{
2428	uint32_t uLimit = pCurLeaf->uEax;
2429	if (uLimit <= UINT32_C(0x000fffff))
2430	{
2431	if (uLimit > pConfig->uMaxStdLeaf)
2432	{
2433	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2434	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2435	uLimit + 1, UINT32_C(0x000fffff));
2436	}
2437
2438	/* NT4 hack, no zapping of extra leaves here. */
2439	if (pConfig->fNt4LeafLimit && uLimit > 3)
2440	pCurLeaf->uEax = uLimit = 3;
2441
2442	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2443	pCurLeaf->uEax = uLimit;
2444	}
2445	else
2446	{
2447	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2448	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2449	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2450	}
2451	}
2452
2453	/*
2454	* Extended leaves.
2455	*/
2456	uSubLeaf = 0;
2457	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2458	if (pCurLeaf)
2459	{
2460	uint32_t uLimit = pCurLeaf->uEax;
2461	if ( uLimit >= UINT32_C(0x80000000)
2462	&& uLimit <= UINT32_C(0x800fffff))
2463	{
2464	if (uLimit > pConfig->uMaxExtLeaf)
2465	{
2466	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2467	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2468	uLimit + 1, UINT32_C(0x800fffff));
2469	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2470	pCurLeaf->uEax = uLimit;
2471	}
2472	}
2473	else
2474	{
2475	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2476	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2477	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2478	}
2479	}
2480
2481	/*
2482	* Centaur leaves (VIA).
2483	*/
2484	uSubLeaf = 0;
2485	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2486	if (pCurLeaf)
2487	{
2488	uint32_t uLimit = pCurLeaf->uEax;
2489	if ( uLimit >= UINT32_C(0xc0000000)
2490	&& uLimit <= UINT32_C(0xc00fffff))
2491	{
2492	if (uLimit > pConfig->uMaxCentaurLeaf)
2493	{
2494	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2495	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2496	uLimit + 1, UINT32_C(0xcfffffff));
2497	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2498	pCurLeaf->uEax = uLimit;
2499	}
2500	}
2501	else
2502	{
2503	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2504	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2505	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2506	}
2507	}
2508	}
2509
2510
2511	/**
2512	* Clears a CPUID leaf and all sub-leaves (to zero).
2513	*
2514	* @param pCpum The CPUM instance data.
2515	* @param uLeaf The leaf to clear.
2516	*/
2517	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2518	{
2519	uint32_t uSubLeaf = 0;
2520	PCPUMCPUIDLEAF pCurLeaf;
2521	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2522	{
2523	pCurLeaf->uEax = 0;
2524	pCurLeaf->uEbx = 0;
2525	pCurLeaf->uEcx = 0;
2526	pCurLeaf->uEdx = 0;
2527	uSubLeaf++;
2528	}
2529	}
2530
2531
2532	/**
2533	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2534	* the given leaf.
2535	*
2536	* @returns pLeaf.
2537	* @param pCpum The CPUM instance data.
2538	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2539	*/
2540	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2541	{
2542	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2543	if (pLeaf->fSubLeafMask != 0)
2544	{
2545	/*
2546	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2547	* Log everything while we're at it.
2548	*/
2549	LogRel(("CPUM:\n"
2550	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2551	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2552	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2553	for (;;)
2554	{
2555	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2556	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2557	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2558	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2559	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2560	break;
2561	pSubLeaf++;
2562	}
2563	LogRel(("CPUM:\n"));
2564
2565	/*
2566	* Remove the offending sub-leaves.
2567	*/
2568	if (pSubLeaf != pLeaf)
2569	{
2570	if (pSubLeaf != pLast)
2571	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2572	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2573	}
2574
2575	/*
2576	* Convert the first sub-leaf into a single leaf.
2577	*/
2578	pLeaf->uSubLeaf = 0;
2579	pLeaf->fSubLeafMask = 0;
2580	}
2581	return pLeaf;
2582	}
2583
2584
2585	/**
2586	* Sanitizes and adjust the CPUID leaves.
2587	*
2588	* Drop features that aren't virtualized (or virtualizable). Adjust information
2589	* and capabilities to fit the virtualized hardware. Remove information the
2590	* guest shouldn't have (because it's wrong in the virtual world or because it
2591	* gives away host details) or that we don't have documentation for and no idea
2592	* what means.
2593	*
2594	* @returns VBox status code.
2595	* @param pVM The cross context VM structure (for cCpus).
2596	* @param pCpum The CPUM instance data.
2597	* @param pConfig The CPUID configuration we've read from CFGM.
2598	*/
2599	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2600	{
2601	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2602	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2603	{ \
2604	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2605	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2606	}
2607	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2608	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2609	{ \
2610	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2611	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2612	}
2613	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2614	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2615	&& ((a_pLeafReg) & (fBitMask)) \
2616	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2617	{ \
2618	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2619	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2620	}
2621	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2622
2623	/* Cpuid 1:
2624	* EAX: CPU model, family and stepping.
2625	*
2626	* ECX + EDX: Supported features. Only report features we can support.
2627	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2628	* options may require adjusting (i.e. stripping what was enabled).
2629	*
2630	* EBX: Branding, CLFLUSH line size, logical processors per package and
2631	* initial APIC ID.
2632	*/
2633	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2634	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2635	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2636
2637	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2638	\| X86_CPUID_FEATURE_EDX_VME
2639	\| X86_CPUID_FEATURE_EDX_DE
2640	\| X86_CPUID_FEATURE_EDX_PSE
2641	\| X86_CPUID_FEATURE_EDX_TSC
2642	\| X86_CPUID_FEATURE_EDX_MSR
2643	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2644	\| X86_CPUID_FEATURE_EDX_MCE
2645	\| X86_CPUID_FEATURE_EDX_CX8
2646	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2647	//\| RT_BIT_32(10) - not defined
2648	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2649	//\| X86_CPUID_FEATURE_EDX_SEP
2650	\| X86_CPUID_FEATURE_EDX_MTRR
2651	\| X86_CPUID_FEATURE_EDX_PGE
2652	\| X86_CPUID_FEATURE_EDX_MCA
2653	\| X86_CPUID_FEATURE_EDX_CMOV
2654	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2655	\| X86_CPUID_FEATURE_EDX_PSE36
2656	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2657	\| X86_CPUID_FEATURE_EDX_CLFSH
2658	//\| RT_BIT_32(20) - not defined
2659	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2660	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2661	\| X86_CPUID_FEATURE_EDX_MMX
2662	\| X86_CPUID_FEATURE_EDX_FXSR
2663	\| X86_CPUID_FEATURE_EDX_SSE
2664	\| X86_CPUID_FEATURE_EDX_SSE2
2665	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2666	\| X86_CPUID_FEATURE_EDX_HTT
2667	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2668	//\| RT_BIT_32(30) - not defined
2669	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2670	;
2671	pStdFeatureLeaf->uEcx &= 0
2672	\| X86_CPUID_FEATURE_ECX_SSE3
2673	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2674	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2675	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2676	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2677	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2678	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2679	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2680	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2681	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2682	\| X86_CPUID_FEATURE_ECX_SSSE3
2683	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2684	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2685	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2686	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2687	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2688	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2689	\| (pConfig->enmPcid ? X86_CPUID_FEATURE_ECX_PCID : 0)
2690	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2691	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2692	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2693	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2694	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2695	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2696	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2697	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2698	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2699	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2700	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2701	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2702	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2703	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2704	;
2705
2706	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2707	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2708	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2709	{
2710	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2711	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2712	}
2713
2714	if (pCpum->u8PortableCpuIdLevel > 0)
2715	{
2716	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2717	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2718	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2719	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2720	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2721	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2722	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2723	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2724	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2725	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2726	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2727	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2728	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2729	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2730	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2731	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2732	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2733	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2734	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2735	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2736
2737	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2738	\| X86_CPUID_FEATURE_EDX_PSN
2739	\| X86_CPUID_FEATURE_EDX_DS
2740	\| X86_CPUID_FEATURE_EDX_ACPI
2741	\| X86_CPUID_FEATURE_EDX_SS
2742	\| X86_CPUID_FEATURE_EDX_TM
2743	\| X86_CPUID_FEATURE_EDX_PBE
2744	)));
2745	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2746	\| X86_CPUID_FEATURE_ECX_CPLDS
2747	\| X86_CPUID_FEATURE_ECX_AES
2748	\| X86_CPUID_FEATURE_ECX_VMX
2749	\| X86_CPUID_FEATURE_ECX_SMX
2750	\| X86_CPUID_FEATURE_ECX_EST
2751	\| X86_CPUID_FEATURE_ECX_TM2
2752	\| X86_CPUID_FEATURE_ECX_CNTXID
2753	\| X86_CPUID_FEATURE_ECX_FMA
2754	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2755	\| X86_CPUID_FEATURE_ECX_PDCM
2756	\| X86_CPUID_FEATURE_ECX_DCA
2757	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2758	)));
2759	}
2760
2761	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2762	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2763
2764	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2765	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2766	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2767	*/
2768	#ifdef VBOX_WITH_MULTI_CORE
2769	if (pVM->cCpus > 1)
2770	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2771	#endif
2772	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2773	{
2774	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2775	core times the number of CPU cores per processor */
2776	#ifdef VBOX_WITH_MULTI_CORE
2777	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2778	#else
2779	/* Single logical processor in a package. */
2780	pStdFeatureLeaf->uEbx \|= (1 << 16);
2781	#endif
2782	}
2783
2784	uint32_t uMicrocodeRev;
2785	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2786	if (RT_SUCCESS(rc))
2787	{
2788	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2789	}
2790	else
2791	{
2792	uMicrocodeRev = 0;
2793	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2794	}
2795
2796	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2797	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2798	*/
2799	if ( (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen)
2800	&& uMicrocodeRev < 0x8001126
2801	&& !pConfig->fForceVme)
2802	{
2803	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2804	LogRel(("CPUM: Zen VME workaround engaged\n"));
2805	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2806	}
2807
2808	/* Force standard feature bits. */
2809	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2810	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2811	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2812	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2813	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2814	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2815	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2816	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2817	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2818	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2819	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2820	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2821	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2822	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2823	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2824	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2825	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2826	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2827	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2828	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2829	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2830	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2831
2832	pStdFeatureLeaf = NULL; /* Must refetch! */
2833
2834	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2835	* AMD:
2836	* EAX: CPU model, family and stepping.
2837	*
2838	* ECX + EDX: Supported features. Only report features we can support.
2839	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2840	* options may require adjusting (i.e. stripping what was enabled).
2841	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2842	*
2843	* EBX: Branding ID and package type (or reserved).
2844	*
2845	* Intel and probably most others:
2846	* EAX: 0
2847	* EBX: 0
2848	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2849	*/
2850	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2851	if (pExtFeatureLeaf)
2852	{
2853	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2854
2855	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2856	\| X86_CPUID_AMD_FEATURE_EDX_VME
2857	\| X86_CPUID_AMD_FEATURE_EDX_DE
2858	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2859	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2860	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2861	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2862	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2863	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2864	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2865	//\| RT_BIT_32(10) - reserved
2866	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2867	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2868	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2869	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2870	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2871	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2872	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2873	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2874	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2875	//\| RT_BIT_32(18) - reserved
2876	//\| RT_BIT_32(19) - reserved
2877	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2878	//\| RT_BIT_32(21) - reserved
2879	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2880	\| X86_CPUID_AMD_FEATURE_EDX_MMX
2881	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
2882	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
2883	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2884	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2885	//\| RT_BIT_32(28) - reserved
2886	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2887	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2888	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
2889	;
2890	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2891	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2892	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
2893	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2894	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
2895	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2896	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2897	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2898	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2899	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2900	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2901	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
2902	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
2903	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2904	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
2905	//\| RT_BIT_32(14) - reserved
2906	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2907	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2908	//\| RT_BIT_32(17) - reserved
2909	//\| RT_BIT_32(18) - reserved
2910	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2911	//\| RT_BIT_32(20) - reserved
2912	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2913	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2914	//\| RT_BIT_32(23) - reserved
2915	//\| RT_BIT_32(24) - reserved
2916	//\| RT_BIT_32(25) - reserved
2917	//\| RT_BIT_32(26) - reserved
2918	//\| RT_BIT_32(27) - reserved
2919	//\| RT_BIT_32(28) - reserved
2920	//\| RT_BIT_32(29) - reserved
2921	//\| RT_BIT_32(30) - reserved
2922	//\| RT_BIT_32(31) - reserved
2923	;
2924	#ifdef VBOX_WITH_MULTI_CORE
2925	if ( pVM->cCpus > 1
2926	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2927	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2928	#endif
2929
2930	if (pCpum->u8PortableCpuIdLevel > 0)
2931	{
2932	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2933	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
2934	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2935	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2936	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2937	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2938	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2939	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2940	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2941	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2942	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2943	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2944	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2945	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2946	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2947	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2948
2949	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2950	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2951	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2952	\| X86_CPUID_AMD_FEATURE_ECX_IBS
2953	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2954	\| X86_CPUID_AMD_FEATURE_ECX_WDT
2955	\| X86_CPUID_AMD_FEATURE_ECX_LWP
2956	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
2957	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2958	\| UINT32_C(0xff964000)
2959	)));
2960	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2961	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2962	\| RT_BIT(18)
2963	\| RT_BIT(19)
2964	\| RT_BIT(21)
2965	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2966	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2967	\| RT_BIT(28)
2968	)));
2969	}
2970
2971	/* Force extended feature bits. */
2972	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2973	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
2974	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2975	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2976	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2977	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2978	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2979	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2980	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2981	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2982	}
2983	pExtFeatureLeaf = NULL; /* Must refetch! */
2984
2985
2986	/* Cpuid 2:
2987	* Intel: (Nondeterministic) Cache and TLB information
2988	* AMD: Reserved
2989	* VIA: Reserved
2990	* Safe to expose.
2991	*/
2992	uint32_t uSubLeaf = 0;
2993	PCPUMCPUIDLEAF pCurLeaf;
2994	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2995	{
2996	if ((pCurLeaf->uEax & 0xff) > 1)
2997	{
2998	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2999	pCurLeaf->uEax &= UINT32_C(0xffffff01);
3000	}
3001	uSubLeaf++;
3002	}
3003
3004	/* Cpuid 3:
3005	* Intel: EAX, EBX - reserved (transmeta uses these)
3006	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3007	* AMD: Reserved
3008	* VIA: Reserved
3009	* Safe to expose
3010	*/
3011	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3012	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3013	{
3014	uSubLeaf = 0;
3015	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3016	{
3017	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3018	if (pCpum->u8PortableCpuIdLevel > 0)
3019	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3020	uSubLeaf++;
3021	}
3022	}
3023
3024	/* Cpuid 4 + ECX:
3025	* Intel: Deterministic Cache Parameters Leaf.
3026	* AMD: Reserved
3027	* VIA: Reserved
3028	* Safe to expose, except for EAX:
3029	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3030	* Bits 31-26: Maximum number of processor cores in this physical package**
3031	* Note: These SMP values are constant regardless of ECX
3032	*/
3033	uSubLeaf = 0;
3034	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3035	{
3036	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3037	#ifdef VBOX_WITH_MULTI_CORE
3038	if ( pVM->cCpus > 1
3039	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3040	{
3041	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3042	/* One logical processor with possibly multiple cores. */
3043	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3044	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3045	}
3046	#endif
3047	uSubLeaf++;
3048	}
3049
3050	/* Cpuid 5: Monitor/mwait Leaf
3051	* Intel: ECX, EDX - reserved
3052	* EAX, EBX - Smallest and largest monitor line size
3053	* AMD: EDX - reserved
3054	* EAX, EBX - Smallest and largest monitor line size
3055	* ECX - extensions (ignored for now)
3056	* VIA: Reserved
3057	* Safe to expose
3058	*/
3059	uSubLeaf = 0;
3060	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3061	{
3062	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3063	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3064	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3065
3066	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3067	if (pConfig->enmMWaitExtensions)
3068	{
3069	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3070	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3071	it shall be part of our power management virtualization model */
3072	#if 0
3073	/* MWAIT sub C-states */
3074	pCurLeaf->uEdx =
3075	(0 << 0) /* 0 in C0 */ \|
3076	(2 << 4) /* 2 in C1 */ \|
3077	(2 << 8) /* 2 in C2 */ \|
3078	(2 << 12) /* 2 in C3 */ \|
3079	(0 << 16) /* 0 in C4 */
3080	;
3081	#endif
3082	}
3083	else
3084	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3085	uSubLeaf++;
3086	}
3087
3088	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3089	* Intel: Various stuff.
3090	* AMD: EAX, EBX, EDX - reserved.
3091	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3092	* present. Same as intel.
3093	* VIA: ??
3094	*
3095	* We clear everything here for now.
3096	*/
3097	cpumR3CpuIdZeroLeaf(pCpum, 6);
3098
3099	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3100	* EAX: Number of sub leaves.
3101	* EBX+ECX+EDX: Feature flags
3102	*
3103	* We only have documentation for one sub-leaf, so clear all other (no need
3104	* to remove them as such, just set them to zero).
3105	*
3106	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3107	* options may require adjusting (i.e. stripping what was enabled).
3108	*/
3109	uSubLeaf = 0;
3110	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3111	{
3112	switch (uSubLeaf)
3113	{
3114	case 0:
3115	{
3116	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3117	pCurLeaf->uEbx &= 0
3118	\| (pConfig->enmFsGsBase ? X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE : 0)
3119	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3120	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3121	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3122	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3123	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3124	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3125	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3126	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3127	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3128	\| (pConfig->enmInvpcid ? X86_CPUID_STEXT_FEATURE_EBX_INVPCID : 0)
3129	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3130	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3131	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3132	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3133	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3134	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3135	//\| RT_BIT(17) - reserved
3136	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3137	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3138	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3139	//\| RT_BIT(21) - reserved
3140	//\| RT_BIT(22) - reserved
3141	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3142	//\| RT_BIT(24) - reserved
3143	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3144	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3145	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3146	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3147	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3148	//\| RT_BIT(30) - reserved
3149	//\| RT_BIT(31) - reserved
3150	;
3151	pCurLeaf->uEcx &= 0
3152	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3153	;
3154	pCurLeaf->uEdx &= 0
3155	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3156	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3157	//\| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT(29)
3158	;
3159
3160	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3161	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3162	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3163	{
3164	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3165	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3166	}
3167
3168	if (pCpum->u8PortableCpuIdLevel > 0)
3169	{
3170	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3171	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3172	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3173	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3174	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3175	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3176	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3177	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3178	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3179	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3180	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3181	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3182	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3183	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3184	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3185	}
3186
3187	/* Force standard feature bits. */
3188	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3189	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3190	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3191	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3192	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3193	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3194	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3195	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3196	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3197	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3198	break;
3199	}
3200
3201	default:
3202	/* Invalid index, all values are zero. */
3203	pCurLeaf->uEax = 0;
3204	pCurLeaf->uEbx = 0;
3205	pCurLeaf->uEcx = 0;
3206	pCurLeaf->uEdx = 0;
3207	break;
3208	}
3209	uSubLeaf++;
3210	}
3211
3212	/* Cpuid 8: Marked as reserved by Intel and AMD.
3213	* We zero this since we don't know what it may have been used for.
3214	*/
3215	cpumR3CpuIdZeroLeaf(pCpum, 8);
3216
3217	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3218	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3219	* EBX, ECX, EDX - reserved.
3220	* AMD: Reserved
3221	* VIA: ??
3222	*
3223	* We zero this.
3224	*/
3225	cpumR3CpuIdZeroLeaf(pCpum, 9);
3226
3227	/* Cpuid 0xa: Architectural Performance Monitor Features
3228	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3229	* EBX, ECX, EDX - reserved.
3230	* AMD: Reserved
3231	* VIA: ??
3232	*
3233	* We zero this, for now at least.
3234	*/
3235	cpumR3CpuIdZeroLeaf(pCpum, 10);
3236
3237	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3238	* Intel: EAX - APCI ID shift right for next level.
3239	* EBX - Factory configured cores/threads at this level.
3240	* ECX - Level number (same as input) and level type (1,2,0).
3241	* EDX - Extended initial APIC ID.
3242	* AMD: Reserved
3243	* VIA: ??
3244	*/
3245	uSubLeaf = 0;
3246	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3247	{
3248	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3249	{
3250	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3251	if (bLevelType == 1)
3252	{
3253	/* Thread level - we don't do threads at the moment. */
3254	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3255	pCurLeaf->uEbx = 1;
3256	}
3257	else if (bLevelType == 2)
3258	{
3259	/* Core level. */
3260	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3261	#ifdef VBOX_WITH_MULTI_CORE
3262	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3263	pCurLeaf->uEax++;
3264	#endif
3265	pCurLeaf->uEbx = pVM->cCpus;
3266	}
3267	else
3268	{
3269	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3270	pCurLeaf->uEax = 0;
3271	pCurLeaf->uEbx = 0;
3272	pCurLeaf->uEcx = 0;
3273	}
3274	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3275	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3276	}
3277	else
3278	{
3279	pCurLeaf->uEax = 0;
3280	pCurLeaf->uEbx = 0;
3281	pCurLeaf->uEcx = 0;
3282	pCurLeaf->uEdx = 0;
3283	}
3284	uSubLeaf++;
3285	}
3286
3287	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3288	* We zero this since we don't know what it may have been used for.
3289	*/
3290	cpumR3CpuIdZeroLeaf(pCpum, 12);
3291
3292	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3293	* ECX=0: EAX - Valid bits in XCR0[31:0].
3294	* EBX - Maximum state size as per current XCR0 value.
3295	* ECX - Maximum state size for all supported features.
3296	* EDX - Valid bits in XCR0[63:32].
3297	* ECX=1: EAX - Various X-features.
3298	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3299	* ECX - Valid bits in IA32_XSS[31:0].
3300	* EDX - Valid bits in IA32_XSS[63:32].
3301	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3302	* if the bit invalid all four registers are set to zero.
3303	* EAX - The state size for this feature.
3304	* EBX - The state byte offset of this feature.
3305	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3306	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3307	*
3308	* Clear them all as we don't currently implement extended CPU state.
3309	*/
3310	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3311	uint64_t fGuestXcr0Mask = 0;
3312	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3313	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3314	{
3315	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3316	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3317	fGuestXcr0Mask \|= XSAVE_C_YMM;
3318	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3319	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3320	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3321	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3322
3323	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3324	}
3325	pStdFeatureLeaf = NULL;
3326	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3327
3328	/* Work the sub-leaves. */
3329	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3330	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3331	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3332	{
3333	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3334	if (pCurLeaf)
3335	{
3336	if (fGuestXcr0Mask)
3337	{
3338	switch (uSubLeaf)
3339	{
3340	case 0:
3341	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3342	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3343	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3344	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3345	VERR_CPUM_IPE_1);
3346	cbXSaveMaxActual = pCurLeaf->uEcx;
3347	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3348	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3349	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3350	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3351	VERR_CPUM_IPE_2);
3352	continue;
3353	case 1:
3354	pCurLeaf->uEax &= 0;
3355	pCurLeaf->uEcx &= 0;
3356	pCurLeaf->uEdx &= 0;
3357	/** @todo what about checking ebx? */
3358	continue;
3359	default:
3360	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3361	{
3362	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3363	&& pCurLeaf->uEax > 0
3364	&& pCurLeaf->uEbx < cbXSaveMaxActual
3365	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3366	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3367	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3368	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3369	VERR_CPUM_IPE_2);
3370	AssertLogRel(!(pCurLeaf->uEcx & 1));
3371	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3372	pCurLeaf->uEdx = 0; /* it's reserved... */
3373	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3374	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3375	continue;
3376	}
3377	break;
3378	}
3379	}
3380
3381	/* Clear the leaf. */
3382	pCurLeaf->uEax = 0;
3383	pCurLeaf->uEbx = 0;
3384	pCurLeaf->uEcx = 0;
3385	pCurLeaf->uEdx = 0;
3386	}
3387	}
3388
3389	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3390	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3391	{
3392	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3393	if (pCurLeaf)
3394	{
3395	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3396	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3397	pCurLeaf->uEbx = cbXSaveMaxReport;
3398	pCurLeaf->uEcx = cbXSaveMaxReport;
3399	}
3400	}
3401
3402	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3403	* We zero this since we don't know what it may have been used for.
3404	*/
3405	cpumR3CpuIdZeroLeaf(pCpum, 14);
3406
3407	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3408	* also known as Intel Resource Director Technology (RDT) Monitoring
3409	* We zero this as we don't currently virtualize PQM.
3410	*/
3411	cpumR3CpuIdZeroLeaf(pCpum, 15);
3412
3413	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3414	* also known as Intel Resource Director Technology (RDT) Allocation
3415	* We zero this as we don't currently virtualize PQE.
3416	*/
3417	cpumR3CpuIdZeroLeaf(pCpum, 16);
3418
3419	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3420	* We zero this since we don't know what it may have been used for.
3421	*/
3422	cpumR3CpuIdZeroLeaf(pCpum, 17);
3423
3424	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3425	* We zero this as we don't currently virtualize this.
3426	*/
3427	cpumR3CpuIdZeroLeaf(pCpum, 18);
3428
3429	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3430	* We zero this since we don't know what it may have been used for.
3431	*/
3432	cpumR3CpuIdZeroLeaf(pCpum, 19);
3433
3434	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3435	* We zero this as we don't currently virtualize this.
3436	*/
3437	cpumR3CpuIdZeroLeaf(pCpum, 20);
3438
3439	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3440	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3441	* EAX - denominator (unsigned).
3442	* EBX - numerator (unsigned).
3443	* ECX, EDX - reserved.
3444	* AMD: Reserved / undefined / not implemented.
3445	* VIA: Reserved / undefined / not implemented.
3446	* We zero this as we don't currently virtualize this.
3447	*/
3448	cpumR3CpuIdZeroLeaf(pCpum, 21);
3449
3450	/* Cpuid 0x16: Processor frequency info
3451	* Intel: EAX - Core base frequency in MHz.
3452	* EBX - Core maximum frequency in MHz.
3453	* ECX - Bus (reference) frequency in MHz.
3454	* EDX - Reserved.
3455	* AMD: Reserved / undefined / not implemented.
3456	* VIA: Reserved / undefined / not implemented.
3457	* We zero this as we don't currently virtualize this.
3458	*/
3459	cpumR3CpuIdZeroLeaf(pCpum, 22);
3460
3461	/* Cpuid 0x17..0x10000000: Unknown.
3462	* We don't know these and what they mean, so remove them. */
3463	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3464	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3465
3466
3467	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3468	* We remove all these as we're a hypervisor and must provide our own.
3469	*/
3470	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3471	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3472
3473
3474	/* Cpuid 0x80000000 is harmless. */
3475
3476	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3477
3478	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3479
3480	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3481	* Safe to pass on to the guest.
3482	*
3483	* AMD: 0x800000005 L1 cache information
3484	* 0x800000006 L2/L3 cache information
3485	* Intel: 0x800000005 reserved
3486	* 0x800000006 L2 cache information
3487	* VIA: 0x800000005 TLB and L1 cache information
3488	* 0x800000006 L2 cache information
3489	*/
3490
3491	/* Cpuid 0x800000007: Advanced Power Management Information.
3492	* AMD: EAX: Processor feedback capabilities.
3493	* EBX: RAS capabilites.
3494	* ECX: Advanced power monitoring interface.
3495	* EDX: Enhanced power management capabilities.
3496	* Intel: EAX, EBX, ECX - reserved.
3497	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3498	* VIA: Reserved
3499	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3500	*/
3501	uSubLeaf = 0;
3502	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3503	{
3504	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3505	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3506	{
3507	/*
3508	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3509	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3510	* bit is now configurable.
3511	*/
3512	pCurLeaf->uEdx &= 0
3513	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3514	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3515	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3516	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3517	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3518	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3519	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3520	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3521	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3522	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3523	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3524	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3525	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3526	\| 0;
3527	}
3528	else
3529	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3530	if (!pConfig->fInvariantTsc)
3531	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3532	uSubLeaf++;
3533	}
3534
3535	/* Cpuid 0x80000008:
3536	* AMD: EBX, EDX - reserved
3537	* EAX: Virtual/Physical/Guest address Size
3538	* ECX: Number of cores + APICIdCoreIdSize
3539	* Intel: EAX: Virtual/Physical address Size
3540	* EBX, ECX, EDX - reserved
3541	* VIA: EAX: Virtual/Physical address Size
3542	* EBX, ECX, EDX - reserved
3543	*
3544	* We only expose the virtual+pysical address size to the guest atm.
3545	* On AMD we set the core count, but not the apic id stuff as we're
3546	* currently not doing the apic id assignments in a complatible manner.
3547	*/
3548	uSubLeaf = 0;
3549	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3550	{
3551	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3552	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3553	pCurLeaf->uEdx = 0; /* reserved */
3554
3555	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3556	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3557	pCurLeaf->uEcx = 0;
3558	#ifdef VBOX_WITH_MULTI_CORE
3559	if ( pVM->cCpus > 1
3560	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3561	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3562	#endif
3563	uSubLeaf++;
3564	}
3565
3566	/* Cpuid 0x80000009: Reserved
3567	* We zero this since we don't know what it may have been used for.
3568	*/
3569	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3570
3571	/* Cpuid 0x8000000a: SVM Information
3572	* AMD: EAX - SVM revision.
3573	* EBX - Number of ASIDs.
3574	* ECX - Reserved.
3575	* EDX - SVM Feature identification.
3576	*/
3577	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3578	if (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
3579	{
3580	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3581	pSvmFeatureLeaf->uEax = 0x1;
3582	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3583	pSvmFeatureLeaf->uEcx = 0;
3584	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3585	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3586	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3587	}
3588	else
3589	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3590
3591	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3592	* We clear these as we don't know what purpose they might have. */
3593	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3594	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3595
3596	/* Cpuid 0x80000019: TLB configuration
3597	* Seems to be harmless, pass them thru as is. */
3598
3599	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3600	* Strip anything we don't know what is or addresses feature we don't implement. */
3601	uSubLeaf = 0;
3602	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3603	{
3604	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3605	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3606	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3607	;
3608	pCurLeaf->uEbx = 0; /* reserved */
3609	pCurLeaf->uEcx = 0; /* reserved */
3610	pCurLeaf->uEdx = 0; /* reserved */
3611	uSubLeaf++;
3612	}
3613
3614	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3615	* Clear this as we don't currently virtualize this feature. */
3616	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3617
3618	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3619	* Clear this as we don't currently virtualize this feature. */
3620	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3621
3622	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3623	* We need to sanitize the cores per cache (EAX[25:14]).
3624	*
3625	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3626	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3627	* slightly different meaning.
3628	*/
3629	uSubLeaf = 0;
3630	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3631	{
3632	#ifdef VBOX_WITH_MULTI_CORE
3633	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3634	if (cCores > pVM->cCpus)
3635	cCores = pVM->cCpus;
3636	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3637	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3638	#else
3639	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3640	#endif
3641	uSubLeaf++;
3642	}
3643
3644	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3645	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3646	* setup, we have one compute unit with all the cores in it. Single node.
3647	*/
3648	uSubLeaf = 0;
3649	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3650	{
3651	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3652	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3653	{
3654	#ifdef VBOX_WITH_MULTI_CORE
3655	pCurLeaf->uEbx = pVM->cCpus < 0x100
3656	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3657	#else
3658	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3659	#endif
3660	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3661	}
3662	else
3663	{
3664	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3665	pCurLeaf->uEbx = 0; /* Reserved. */
3666	pCurLeaf->uEcx = 0; /* Reserved. */
3667	}
3668	pCurLeaf->uEdx = 0; /* Reserved. */
3669	uSubLeaf++;
3670	}
3671
3672	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3673	* We don't know these and what they mean, so remove them. */
3674	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3675	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3676
3677	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3678	* Just pass it thru for now. */
3679
3680	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3681	* Just pass it thru for now. */
3682
3683	/* Cpuid 0xc0000000: Centaur stuff.
3684	* Harmless, pass it thru. */
3685
3686	/* Cpuid 0xc0000001: Centaur features.
3687	* VIA: EAX - Family, model, stepping.
3688	* EDX - Centaur extended feature flags. Nothing interesting, except may
3689	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3690	* EBX, ECX - reserved.
3691	* We keep EAX but strips the rest.
3692	*/
3693	uSubLeaf = 0;
3694	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3695	{
3696	pCurLeaf->uEbx = 0;
3697	pCurLeaf->uEcx = 0;
3698	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3699	uSubLeaf++;
3700	}
3701
3702	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3703	* We only have fixed stale values, but should be harmless. */
3704
3705	/* Cpuid 0xc0000003: Reserved.
3706	* We zero this since we don't know what it may have been used for.
3707	*/
3708	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3709
3710	/* Cpuid 0xc0000004: Centaur Performance Info.
3711	* We only have fixed stale values, but should be harmless. */
3712
3713
3714	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3715	* We don't know these and what they mean, so remove them. */
3716	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3717	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3718
3719	return VINF_SUCCESS;
3720	#undef PORTABLE_DISABLE_FEATURE_BIT
3721	#undef PORTABLE_CLEAR_BITS_WHEN
3722	}
3723
3724
3725	/**
3726	* Reads a value in /CPUM/IsaExts/ node.
3727	*
3728	* @returns VBox status code (error message raised).
3729	* @param pVM The cross context VM structure. (For errors.)
3730	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3731	* @param pszValueName The value / extension name.
3732	* @param penmValue Where to return the choice.
3733	* @param enmDefault The default choice.
3734	*/
3735	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3736	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3737	{
3738	/*
3739	* Try integer encoding first.
3740	*/
3741	uint64_t uValue;
3742	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3743	if (RT_SUCCESS(rc))
3744	switch (uValue)
3745	{
3746	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3747	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3748	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3749	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3750	default:
3751	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3752	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3753	pszValueName, uValue);
3754	}
3755	/*
3756	* If missing, use default.
3757	*/
3758	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3759	*penmValue = enmDefault;
3760	else
3761	{
3762	if (rc == VERR_CFGM_NOT_INTEGER)
3763	{
3764	/*
3765	* Not an integer, try read it as a string.
3766	*/
3767	char szValue[32];
3768	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3769	if (RT_SUCCESS(rc))
3770	{
3771	RTStrToLower(szValue);
3772	size_t cchValue = strlen(szValue);
3773	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3774	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3775	*penmValue = CPUMISAEXTCFG_DISABLED;
3776	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3777	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3778	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3779	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3780	else if (EQ("portable"))
3781	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3782	else if (EQ("default") \|\| EQ("def"))
3783	*penmValue = enmDefault;
3784	else
3785	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3786	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3787	pszValueName, uValue);
3788	#undef EQ
3789	}
3790	}
3791	if (RT_FAILURE(rc))
3792	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3793	}
3794	return VINF_SUCCESS;
3795	}
3796
3797
3798	/**
3799	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3800	*
3801	* @returns VBox status code (error message raised).
3802	* @param pVM The cross context VM structure. (For errors.)
3803	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3804	* @param pszValueName The value / extension name.
3805	* @param penmValue Where to return the choice.
3806	* @param enmDefault The default choice.
3807	* @param fAllowed Allowed choice. Applied both to the result and to
3808	* the default value.
3809	*/
3810	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3811	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3812	{
3813	int rc;
3814	if (fAllowed)
3815	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3816	else
3817	{
3818	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3819	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3820	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3821	*penmValue = CPUMISAEXTCFG_DISABLED;
3822	}
3823	return rc;
3824	}
3825
3826
3827	/**
3828	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3829	*
3830	* @returns VBox status code (error message raised).
3831	* @param pVM The cross context VM structure. (For errors.)
3832	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3833	* @param pCpumCfg The /CPUM node (can be NULL).
3834	* @param pszValueName The value / extension name.
3835	* @param penmValue Where to return the choice.
3836	* @param enmDefault The default choice.
3837	*/
3838	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3839	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3840	{
3841	if (CFGMR3Exists(pCpumCfg, pszValueName))
3842	{
3843	if (!CFGMR3Exists(pIsaExts, pszValueName))
3844	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3845	else
3846	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3847	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3848	pszValueName, pszValueName);
3849
3850	bool fLegacy;
3851	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3852	if (RT_SUCCESS(rc))
3853	{
3854	*penmValue = fLegacy;
3855	return VINF_SUCCESS;
3856	}
3857	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3858	}
3859
3860	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3861	}
3862
3863
3864	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3865	{
3866	int rc;
3867
3868	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3869	* When non-zero CPUID features that could cause portability issues will be
3870	* stripped. The higher the value the more features gets stripped. Higher
3871	* values should only be used when older CPUs are involved since it may
3872	* harm performance and maybe also cause problems with specific guests. */
3873	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
3874	AssertLogRelRCReturn(rc, rc);
3875
3876	/** @cfgm{/CPUM/GuestCpuName, string}
3877	* The name of the CPU we're to emulate. The default is the host CPU.
3878	* Note! CPUs other than "host" one is currently unsupported. */
3879	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3880	AssertLogRelRCReturn(rc, rc);
3881
3882	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3883	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3884	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3885	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3886	*/
3887	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3888	AssertLogRelRCReturn(rc, rc);
3889
3890	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
3891	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
3892	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
3893	* 64-bit linux guests which assume the presence of AMD performance counters
3894	* that we do not virtualize.
3895	*/
3896	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
3897	AssertLogRelRCReturn(rc, rc);
3898
3899	/** @cfgm{/CPUM/ForceVme, boolean, false}
3900	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
3901	* By default the flag is passed thru as is from the host CPU, except
3902	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
3903	* guests and DOS boxes in general.
3904	*/
3905	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
3906	AssertLogRelRCReturn(rc, rc);
3907
3908	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3909	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
3910	* probably going to be a temporary hack, so don't depend on this.
3911	* The 1st byte of the value is the stepping, the 2nd byte value is the model
3912	* number and the 3rd byte value is the family, and the 4th value must be zero.
3913	*/
3914	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3915	AssertLogRelRCReturn(rc, rc);
3916
3917	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3918	* The last standard leaf to keep. The actual last value that is stored in EAX
3919	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3920	* removed. (This works independently of and differently from NT4LeafLimit.)
3921	* The default is usually set to what we're able to reasonably sanitize.
3922	*/
3923	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3924	AssertLogRelRCReturn(rc, rc);
3925
3926	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3927	* The last extended leaf to keep. The actual last value that is stored in EAX
3928	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3929	* leaf are removed. The default is set to what we're able to sanitize.
3930	*/
3931	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3932	AssertLogRelRCReturn(rc, rc);
3933
3934	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3935	* The last extended leaf to keep. The actual last value that is stored in EAX
3936	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3937	* leaf are removed. The default is set to what we're able to sanitize.
3938	*/
3939	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3940	AssertLogRelRCReturn(rc, rc);
3941
3942	bool fQueryNestedHwvirt = false;
3943	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3944	fQueryNestedHwvirt \|= RT_BOOL(pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD);
3945	#endif
3946	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3947	fQueryNestedHwvirt \|= RT_BOOL( pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
3948	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA);
3949	#endif
3950	if (fQueryNestedHwvirt)
3951	{
3952	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
3953	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
3954	* The default is false, and when enabled requires a 64-bit CPU with support for
3955	* nested-paging and AMD-V or unrestricted guest mode.
3956	*/
3957	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
3958	AssertLogRelRCReturn(rc, rc);
3959	if ( pConfig->fNestedHWVirt
3960	&& !fNestedPagingAndFullGuestExec)
3961	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
3962	"Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
3963
3964	/** @todo Think about enabling this later with NEM/KVM. */
3965	if ( pConfig->fNestedHWVirt
3966	&& VM_IS_NEM_ENABLED(pVM))
3967	{
3968	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
3969	pConfig->fNestedHWVirt = false;
3970	}
3971
3972	#if HC_ARCH_BITS == 32
3973	/* We don't support nested hardware virtualization on 32-bit hosts. */
3974	if (pConfig->fNestedHWVirt)
3975	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
3976	"Cannot enable nested VT-x/AMD-V on a 32-bit host\n");
3977	#endif
3978	}
3979
3980	/*
3981	* Instruction Set Architecture (ISA) Extensions.
3982	*/
3983	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3984	if (pIsaExts)
3985	{
3986	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3987	"CMPXCHG16B"
3988	"\|MONITOR"
3989	"\|MWaitExtensions"
3990	"\|SSE4.1"
3991	"\|SSE4.2"
3992	"\|XSAVE"
3993	"\|AVX"
3994	"\|AVX2"
3995	"\|AESNI"
3996	"\|PCLMUL"
3997	"\|POPCNT"
3998	"\|MOVBE"
3999	"\|RDRAND"
4000	"\|RDSEED"
4001	"\|CLFLUSHOPT"
4002	"\|FSGSBASE"
4003	"\|PCID"
4004	"\|INVPCID"
4005	"\|ABM"
4006	"\|SSE4A"
4007	"\|MISALNSSE"
4008	"\|3DNOWPRF"
4009	"\|AXMMX"
4010	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
4011	if (RT_FAILURE(rc))
4012	return rc;
4013	}
4014
4015	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
4016	* Expose CMPXCHG16B to the guest if supported by the host. For the time
4017	* being the default is to only do this for VMs with nested paging and AMD-V or
4018	* unrestricted guest mode.
4019	*/
4020	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
4021	AssertLogRelRCReturn(rc, rc);
4022
4023	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4024	* Expose MONITOR/MWAIT instructions to the guest.
4025	*/
4026	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4027	AssertLogRelRCReturn(rc, rc);
4028
4029	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4030	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4031	* break on interrupt feature (bit 1).
4032	*/
4033	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4034	AssertLogRelRCReturn(rc, rc);
4035
4036	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4037	* Expose SSE4.1 to the guest if available.
4038	*/
4039	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4040	AssertLogRelRCReturn(rc, rc);
4041
4042	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4043	* Expose SSE4.2 to the guest if available.
4044	*/
4045	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4046	AssertLogRelRCReturn(rc, rc);
4047
4048	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4049	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4050	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
4051	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
4052	&& ( !HMIsLongModeAllowed(pVM)
4053	\|\| NEMHCIsLongModeAllowed(pVM))
4054	#endif
4055	;
4056	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4057
4058	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4059	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4060	* default is to only expose this to VMs with nested paging and AMD-V or
4061	* unrestricted guest execution mode. Not possible to force this one without
4062	* host support at the moment.
4063	*/
4064	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4065	fMayHaveXSave /fAllowed/);
4066	AssertLogRelRCReturn(rc, rc);
4067
4068	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4069	* Expose the AVX instruction set extensions to the guest if available and
4070	* XSAVE is exposed too. For the time being the default is to only expose this
4071	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4072	*/
4073	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4074	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4075	AssertLogRelRCReturn(rc, rc);
4076
4077	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4078	* Expose the AVX2 instruction set extensions to the guest if available and
4079	* XSAVE is exposed too. For the time being the default is to only expose this
4080	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4081	*/
4082	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4083	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4084	AssertLogRelRCReturn(rc, rc);
4085
4086	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4087	* Whether to expose the AES instructions to the guest. For the time being the
4088	* default is to only do this for VMs with nested paging and AMD-V or
4089	* unrestricted guest mode.
4090	*/
4091	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4092	AssertLogRelRCReturn(rc, rc);
4093
4094	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4095	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4096	* being the default is to only do this for VMs with nested paging and AMD-V or
4097	* unrestricted guest mode.
4098	*/
4099	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4100	AssertLogRelRCReturn(rc, rc);
4101
4102	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4103	* Whether to expose the POPCNT instructions to the guest. For the time
4104	* being the default is to only do this for VMs with nested paging and AMD-V or
4105	* unrestricted guest mode.
4106	*/
4107	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4108	AssertLogRelRCReturn(rc, rc);
4109
4110	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4111	* Whether to expose the MOVBE instructions to the guest. For the time
4112	* being the default is to only do this for VMs with nested paging and AMD-V or
4113	* unrestricted guest mode.
4114	*/
4115	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4116	AssertLogRelRCReturn(rc, rc);
4117
4118	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4119	* Whether to expose the RDRAND instructions to the guest. For the time being
4120	* the default is to only do this for VMs with nested paging and AMD-V or
4121	* unrestricted guest mode.
4122	*/
4123	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4124	AssertLogRelRCReturn(rc, rc);
4125
4126	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4127	* Whether to expose the RDSEED instructions to the guest. For the time being
4128	* the default is to only do this for VMs with nested paging and AMD-V or
4129	* unrestricted guest mode.
4130	*/
4131	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4132	AssertLogRelRCReturn(rc, rc);
4133
4134	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4135	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4136	* being the default is to only do this for VMs with nested paging and AMD-V or
4137	* unrestricted guest mode.
4138	*/
4139	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4140	AssertLogRelRCReturn(rc, rc);
4141
4142	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4143	* Whether to expose the read/write FSGSBASE instructions to the guest.
4144	*/
4145	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4146	AssertLogRelRCReturn(rc, rc);
4147
4148	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4149	* Whether to expose the PCID feature to the guest.
4150	*/
4151	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4152	AssertLogRelRCReturn(rc, rc);
4153
4154	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4155	* Whether to expose the INVPCID instruction to the guest.
4156	*/
4157	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4158	AssertLogRelRCReturn(rc, rc);
4159
4160
4161	/* AMD: */
4162
4163	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4164	* Whether to expose the AMD ABM instructions to the guest. For the time
4165	* being the default is to only do this for VMs with nested paging and AMD-V or
4166	* unrestricted guest mode.
4167	*/
4168	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4169	AssertLogRelRCReturn(rc, rc);
4170
4171	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4172	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4173	* being the default is to only do this for VMs with nested paging and AMD-V or
4174	* unrestricted guest mode.
4175	*/
4176	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4177	AssertLogRelRCReturn(rc, rc);
4178
4179	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4180	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4181	* the time being the default is to only do this for VMs with nested paging and
4182	* AMD-V or unrestricted guest mode.
4183	*/
4184	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4185	AssertLogRelRCReturn(rc, rc);
4186
4187	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4188	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4189	* For the time being the default is to only do this for VMs with nested paging
4190	* and AMD-V or unrestricted guest mode.
4191	*/
4192	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4193	AssertLogRelRCReturn(rc, rc);
4194
4195	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4196	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4197	* the default is to only do this for VMs with nested paging and AMD-V or
4198	* unrestricted guest mode.
4199	*/
4200	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4201	AssertLogRelRCReturn(rc, rc);
4202
4203	return VINF_SUCCESS;
4204	}
4205
4206
4207	/**
4208	* Initializes the emulated CPU's CPUID & MSR information.
4209	*
4210	* @returns VBox status code.
4211	* @param pVM The cross context VM structure.
4212	*/
4213	int cpumR3InitCpuIdAndMsrs(PVM pVM)
4214	{
4215	PCPUM pCpum = &pVM->cpum.s;
4216	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4217
4218	/*
4219	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4220	* on construction and manage everything from here on.
4221	*/
4222	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
4223	pVM->aCpus[iCpu].cpum.s.fCpuIdApicFeatureVisible = true;
4224
4225	/*
4226	* Read the configuration.
4227	*/
4228	CPUMCPUIDCONFIG Config;
4229	RT_ZERO(Config);
4230
4231	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4232	AssertRCReturn(rc, rc);
4233
4234	/*
4235	* Get the guest CPU data from the database and/or the host.
4236	*
4237	* The CPUID and MSRs are currently living on the regular heap to avoid
4238	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4239	* API for the hyper heap). This means special cleanup considerations.
4240	*/
4241	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4242	if (RT_FAILURE(rc))
4243	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4244	? VMSetError(pVM, rc, RT_SRC_POS,
4245	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4246	: rc;
4247
4248	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4249	{
4250	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4251	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4252	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4253	}
4254	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4255
4256	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4257	* Overrides the guest MSRs.
4258	*/
4259	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4260
4261	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4262	* Overrides the CPUID leaf values (from the host CPU usually) used for
4263	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4264	* values when moving a VM to a different machine. Another use is restricting
4265	* (or extending) the feature set exposed to the guest. */
4266	if (RT_SUCCESS(rc))
4267	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4268
4269	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4270	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4271	"Found unsupported configuration node '/CPUM/CPUID/'. "
4272	"Please use IMachine::setCPUIDLeaf() instead.");
4273
4274	/*
4275	* Pre-explode the CPUID info.
4276	*/
4277	if (RT_SUCCESS(rc))
4278	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
4279
4280	/*
4281	* Sanitize the cpuid information passed on to the guest.
4282	*/
4283	if (RT_SUCCESS(rc))
4284	{
4285	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4286	if (RT_SUCCESS(rc))
4287	{
4288	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4289	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4290	}
4291	}
4292
4293	/*
4294	* MSR fudging.
4295	*/
4296	if (RT_SUCCESS(rc))
4297	{
4298	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4299	* Fudges some common MSRs if not present in the selected CPU database entry.
4300	* This is for trying to keep VMs running when moved between different hosts
4301	* and different CPU vendors. */
4302	bool fEnable;
4303	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4304	if (RT_SUCCESS(rc) && fEnable)
4305	{
4306	rc = cpumR3MsrApplyFudge(pVM);
4307	AssertLogRelRC(rc);
4308	}
4309	}
4310	if (RT_SUCCESS(rc))
4311	{
4312	/*
4313	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4314	* guest CPU features again.
4315	*/
4316	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4317	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4318	pCpum->GuestInfo.cCpuIdLeaves);
4319	RTMemFree(pvFree);
4320
4321	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4322	int rc2 = MMHyperDupMem(pVM, pvFree,
4323	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4324	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4325	RTMemFree(pvFree);
4326	AssertLogRelRCReturn(rc1, rc1);
4327	AssertLogRelRCReturn(rc2, rc2);
4328
4329	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4330	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4331
4332
4333	/*
4334	* Some more configuration that we're applying at the end of everything
4335	* via the CPUMSetGuestCpuIdFeature API.
4336	*/
4337
4338	/* Check if PAE was explicitely enabled by the user. */
4339	bool fEnable;
4340	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4341	AssertRCReturn(rc, rc);
4342	if (fEnable)
4343	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4344
4345	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4346	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4347	AssertRCReturn(rc, rc);
4348	if (fEnable)
4349	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4350
4351	/* Check if speculation control is enabled. */
4352	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4353	AssertRCReturn(rc, rc);
4354	if (fEnable)
4355	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4356
4357	return VINF_SUCCESS;
4358	}
4359
4360	/*
4361	* Failed before switching to hyper heap.
4362	*/
4363	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4364	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4365	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4366	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4367	return rc;
4368	}
4369
4370
4371	/**
4372	* Sets a CPUID feature bit during VM initialization.
4373	*
4374	* Since the CPUID feature bits are generally related to CPU features, other
4375	* CPUM configuration like MSRs can also be modified by calls to this API.
4376	*
4377	* @param pVM The cross context VM structure.
4378	* @param enmFeature The feature to set.
4379	*/
4380	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4381	{
4382	PCPUMCPUIDLEAF pLeaf;
4383	PCPUMMSRRANGE pMsrRange;
4384
4385	switch (enmFeature)
4386	{
4387	/*
4388	* Set the APIC bit in both feature masks.
4389	*/
4390	case CPUMCPUIDFEATURE_APIC:
4391	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4392	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4393	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4394
4395	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4396	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4397	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4398
4399	pVM->cpum.s.GuestFeatures.fApic = 1;
4400
4401	/* Make sure we've got the APICBASE MSR present. */
4402	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4403	if (!pMsrRange)
4404	{
4405	static CPUMMSRRANGE const s_ApicBase =
4406	{
4407	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4408	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4409	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4410	/.szName = / "IA32_APIC_BASE"
4411	};
4412	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4413	AssertLogRelRC(rc);
4414	}
4415
4416	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4417	break;
4418
4419	/*
4420	* Set the x2APIC bit in the standard feature mask.
4421	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4422	*/
4423	case CPUMCPUIDFEATURE_X2APIC:
4424	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4425	if (pLeaf)
4426	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4427	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4428
4429	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4430	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4431	if (pMsrRange)
4432	{
4433	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4434	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4435	}
4436
4437	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4438	break;
4439
4440	/*
4441	* Set the sysenter/sysexit bit in the standard feature mask.
4442	* Assumes the caller knows what it's doing! (host must support these)
4443	*/
4444	case CPUMCPUIDFEATURE_SEP:
4445	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4446	{
4447	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4448	return;
4449	}
4450
4451	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4452	if (pLeaf)
4453	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4454	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4455	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4456	break;
4457
4458	/*
4459	* Set the syscall/sysret bit in the extended feature mask.
4460	* Assumes the caller knows what it's doing! (host must support these)
4461	*/
4462	case CPUMCPUIDFEATURE_SYSCALL:
4463	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4464	if ( !pLeaf
4465	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4466	{
4467	#if HC_ARCH_BITS == 32
4468	/* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit
4469	mode by Intel, even when the cpu is capable of doing so in
4470	64-bit mode. Long mode requires syscall support. */
4471	if (!pVM->cpum.s.HostFeatures.fLongMode)
4472	#endif
4473	{
4474	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4475	return;
4476	}
4477	}
4478
4479	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4480	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4481	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4482	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4483	break;
4484
4485	/*
4486	* Set the PAE bit in both feature masks.
4487	* Assumes the caller knows what it's doing! (host must support these)
4488	*/
4489	case CPUMCPUIDFEATURE_PAE:
4490	if (!pVM->cpum.s.HostFeatures.fPae)
4491	{
4492	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4493	return;
4494	}
4495
4496	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4497	if (pLeaf)
4498	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4499
4500	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4501	if ( pLeaf
4502	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4503	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4504
4505	pVM->cpum.s.GuestFeatures.fPae = 1;
4506	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4507	break;
4508
4509	/*
4510	* Set the LONG MODE bit in the extended feature mask.
4511	* Assumes the caller knows what it's doing! (host must support these)
4512	*/
4513	case CPUMCPUIDFEATURE_LONG_MODE:
4514	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4515	if ( !pLeaf
4516	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4517	{
4518	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4519	return;
4520	}
4521
4522	/* Valid for both Intel and AMD. */
4523	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4524	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4525	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4526	break;
4527
4528	/*
4529	* Set the NX/XD bit in the extended feature mask.
4530	* Assumes the caller knows what it's doing! (host must support these)
4531	*/
4532	case CPUMCPUIDFEATURE_NX:
4533	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4534	if ( !pLeaf
4535	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4536	{
4537	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4538	return;
4539	}
4540
4541	/* Valid for both Intel and AMD. */
4542	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4543	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4544	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4545	break;
4546
4547
4548	/*
4549	* Set the LAHF/SAHF support in 64-bit mode.
4550	* Assumes the caller knows what it's doing! (host must support this)
4551	*/
4552	case CPUMCPUIDFEATURE_LAHF:
4553	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4554	if ( !pLeaf
4555	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4556	{
4557	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4558	return;
4559	}
4560
4561	/* Valid for both Intel and AMD. */
4562	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4563	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4564	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4565	break;
4566
4567	/*
4568	* Set the page attribute table bit. This is alternative page level
4569	* cache control that doesn't much matter when everything is
4570	* virtualized, though it may when passing thru device memory.
4571	*/
4572	case CPUMCPUIDFEATURE_PAT:
4573	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4574	if (pLeaf)
4575	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4576
4577	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4578	if ( pLeaf
4579	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4580	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4581
4582	pVM->cpum.s.GuestFeatures.fPat = 1;
4583	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4584	break;
4585
4586	/*
4587	* Set the RDTSCP support bit.
4588	* Assumes the caller knows what it's doing! (host must support this)
4589	*/
4590	case CPUMCPUIDFEATURE_RDTSCP:
4591	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4592	if ( !pLeaf
4593	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4594	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4595	{
4596	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4597	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4598	return;
4599	}
4600
4601	/* Valid for both Intel and AMD. */
4602	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4603	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4604	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4605	break;
4606
4607	/*
4608	* Set the Hypervisor Present bit in the standard feature mask.
4609	*/
4610	case CPUMCPUIDFEATURE_HVP:
4611	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4612	if (pLeaf)
4613	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4614	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4615	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4616	break;
4617
4618	/*
4619	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4620	* This currently includes the Present bit and MWAITBREAK bit as well.
4621	*/
4622	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4623	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4624	if ( !pLeaf
4625	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4626	{
4627	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4628	return;
4629	}
4630
4631	/* Valid for both Intel and AMD. */
4632	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4633	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4634	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4635	break;
4636
4637	/*
4638	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
4639	* on Intel CPUs, and different on AMDs.
4640	*/
4641	case CPUMCPUIDFEATURE_SPEC_CTRL:
4642	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4643	{
4644	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4645	if ( !pLeaf
4646	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
4647	{
4648	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4649	return;
4650	}
4651
4652	/* The feature can be enabled. Let's see what we can actually do. */
4653	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4654
4655	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4656	if (pVM->cpum.s.HostFeatures.fIbrs)
4657	{
4658	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4659	pVM->cpum.s.GuestFeatures.fIbrs = 1;
4660	if (pVM->cpum.s.HostFeatures.fStibp)
4661	{
4662	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4663	pVM->cpum.s.GuestFeatures.fStibp = 1;
4664	}
4665
4666	/* Make sure we have the speculation control MSR... */
4667	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4668	if (!pMsrRange)
4669	{
4670	static CPUMMSRRANGE const s_SpecCtrl =
4671	{
4672	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
4673	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
4674	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4675	/.szName = / "IA32_SPEC_CTRL"
4676	};
4677	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4678	AssertLogRelRC(rc);
4679	}
4680
4681	/* ... and the predictor command MSR. */
4682	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
4683	if (!pMsrRange)
4684	{
4685	static CPUMMSRRANGE const s_SpecCtrl =
4686	{
4687	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
4688	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
4689	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4690	/.szName = / "IA32_PRED_CMD"
4691	};
4692	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4693	AssertLogRelRC(rc);
4694	}
4695
4696	}
4697
4698	if (pVM->cpum.s.HostFeatures.fArchCap) {
4699	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
4700
4701	/* Install the architectural capabilities MSR. */
4702	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
4703	if (!pMsrRange)
4704	{
4705	static CPUMMSRRANGE const s_ArchCaps =
4706	{
4707	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
4708	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
4709	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
4710	/.szName = / "IA32_ARCH_CAPABILITIES"
4711	};
4712	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
4713	AssertLogRelRC(rc);
4714	}
4715	}
4716
4717	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
4718	}
4719	else if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4720	{
4721	/* The precise details of AMD's implementation are not yet clear. */
4722	}
4723	break;
4724
4725	default:
4726	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4727	break;
4728	}
4729
4730	/** @todo can probably kill this as this API is now init time only... */
4731	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4732	{
4733	PVMCPU pVCpu = &pVM->aCpus[i];
4734	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4735	}
4736	}
4737
4738
4739	/**
4740	* Queries a CPUID feature bit.
4741	*
4742	* @returns boolean for feature presence
4743	* @param pVM The cross context VM structure.
4744	* @param enmFeature The feature to query.
4745	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4746	*/
4747	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4748	{
4749	switch (enmFeature)
4750	{
4751	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4752	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4753	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4754	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4755	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4756	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4757	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4758	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4759	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4760	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4761	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4762	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4763	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
4764
4765	case CPUMCPUIDFEATURE_INVALID:
4766	case CPUMCPUIDFEATURE_32BIT_HACK:
4767	break;
4768	}
4769	AssertFailed();
4770	return false;
4771	}
4772
4773
4774	/**
4775	* Clears a CPUID feature bit.
4776	*
4777	* @param pVM The cross context VM structure.
4778	* @param enmFeature The feature to clear.
4779	*
4780	* @deprecated Probably better to default the feature to disabled and only allow
4781	* setting (enabling) it during construction.
4782	*/
4783	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4784	{
4785	PCPUMCPUIDLEAF pLeaf;
4786	switch (enmFeature)
4787	{
4788	case CPUMCPUIDFEATURE_APIC:
4789	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
4790	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4791	if (pLeaf)
4792	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
4793
4794	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4795	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4796	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4797
4798	pVM->cpum.s.GuestFeatures.fApic = 0;
4799	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4800	break;
4801
4802	case CPUMCPUIDFEATURE_X2APIC:
4803	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4804	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4805	if (pLeaf)
4806	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
4807	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
4808	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
4809	break;
4810
4811	case CPUMCPUIDFEATURE_PAE:
4812	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4813	if (pLeaf)
4814	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
4815
4816	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4817	if ( pLeaf
4818	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4819	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
4820
4821	pVM->cpum.s.GuestFeatures.fPae = 0;
4822	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
4823	break;
4824
4825	case CPUMCPUIDFEATURE_PAT:
4826	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4827	if (pLeaf)
4828	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
4829
4830	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4831	if ( pLeaf
4832	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4833	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
4834
4835	pVM->cpum.s.GuestFeatures.fPat = 0;
4836	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
4837	break;
4838
4839	case CPUMCPUIDFEATURE_LONG_MODE:
4840	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4841	if (pLeaf)
4842	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4843	pVM->cpum.s.GuestFeatures.fLongMode = 0;
4844	break;
4845
4846	case CPUMCPUIDFEATURE_LAHF:
4847	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4848	if (pLeaf)
4849	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4850	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
4851	break;
4852
4853	case CPUMCPUIDFEATURE_RDTSCP:
4854	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4855	if (pLeaf)
4856	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4857	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
4858	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
4859	break;
4860
4861	case CPUMCPUIDFEATURE_HVP:
4862	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4863	if (pLeaf)
4864	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
4865	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
4866	break;
4867
4868	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4869	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4870	if (pLeaf)
4871	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
4872	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
4873	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
4874	break;
4875
4876	case CPUMCPUIDFEATURE_SPEC_CTRL:
4877	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4878	if (pLeaf)
4879	/pVM->cpum.s.aGuestCpuIdPatmStd[7].uEdx =/ pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP \| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
4880	pVM->cpum.s.GuestFeatures.fSpeculationControl = 0;
4881	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
4882	break;
4883
4884	default:
4885	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4886	break;
4887	}
4888
4889	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4890	{
4891	PVMCPU pVCpu = &pVM->aCpus[i];
4892	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4893	}
4894	}
4895
4896
4897
4898	/*
4899	*
4900	*
4901	* Saved state related code.
4902	* Saved state related code.
4903	* Saved state related code.
4904	*
4905	*
4906	*/
4907
4908	/**
4909	* Called both in pass 0 and the final pass.
4910	*
4911	* @param pVM The cross context VM structure.
4912	* @param pSSM The saved state handle.
4913	*/
4914	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4915	{
4916	/*
4917	* Save all the CPU ID leaves.
4918	*/
4919	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4920	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4921	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4922	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4923
4924	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4925
4926	/*
4927	* Save a good portion of the raw CPU IDs as well as they may come in
4928	* handy when validating features for raw mode.
4929	*/
4930	CPUMCPUID aRawStd[16];
4931	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4932	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4933	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4934	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4935
4936	CPUMCPUID aRawExt[32];
4937	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4938	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4939	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4940	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4941	}
4942
4943
4944	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4945	{
4946	uint32_t cCpuIds;
4947	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4948	if (RT_SUCCESS(rc))
4949	{
4950	if (cCpuIds < 64)
4951	{
4952	for (uint32_t i = 0; i < cCpuIds; i++)
4953	{
4954	CPUMCPUID CpuId;
4955	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4956	if (RT_FAILURE(rc))
4957	break;
4958
4959	CPUMCPUIDLEAF NewLeaf;
4960	NewLeaf.uLeaf = uBase + i;
4961	NewLeaf.uSubLeaf = 0;
4962	NewLeaf.fSubLeafMask = 0;
4963	NewLeaf.uEax = CpuId.uEax;
4964	NewLeaf.uEbx = CpuId.uEbx;
4965	NewLeaf.uEcx = CpuId.uEcx;
4966	NewLeaf.uEdx = CpuId.uEdx;
4967	NewLeaf.fFlags = 0;
4968	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4969	}
4970	}
4971	else
4972	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4973	}
4974	if (RT_FAILURE(rc))
4975	{
4976	RTMemFree(*ppaLeaves);
4977	*ppaLeaves = NULL;
4978	*pcLeaves = 0;
4979	}
4980	return rc;
4981	}
4982
4983
4984	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4985	{
4986	*ppaLeaves = NULL;
4987	*pcLeaves = 0;
4988
4989	int rc;
4990	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4991	{
4992	/*
4993	* The new format. Starts by declaring the leave size and count.
4994	*/
4995	uint32_t cbLeaf;
4996	SSMR3GetU32(pSSM, &cbLeaf);
4997	uint32_t cLeaves;
4998	rc = SSMR3GetU32(pSSM, &cLeaves);
4999	if (RT_SUCCESS(rc))
5000	{
5001	if (cbLeaf == sizeof(**ppaLeaves))
5002	{
5003	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
5004	{
5005	/*
5006	* Load the leaves one by one.
5007	*
5008	* The uPrev stuff is a kludge for working around a week worth of bad saved
5009	* states during the CPUID revamp in March 2015. We saved too many leaves
5010	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
5011	* garbage entires at the end of the array when restoring. We also had
5012	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
5013	* this kludge doesn't deal correctly with that, but who cares...
5014	*/
5015	uint32_t uPrev = 0;
5016	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
5017	{
5018	CPUMCPUIDLEAF Leaf;
5019	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5020	if (RT_SUCCESS(rc))
5021	{
5022	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5023	\|\| Leaf.uLeaf >= uPrev)
5024	{
5025	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5026	uPrev = Leaf.uLeaf;
5027	}
5028	else
5029	uPrev = UINT32_MAX;
5030	}
5031	}
5032	}
5033	else
5034	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5035	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5036	}
5037	else
5038	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5039	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5040	}
5041	}
5042	else
5043	{
5044	/*
5045	* The old format with its three inflexible arrays.
5046	*/
5047	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5048	if (RT_SUCCESS(rc))
5049	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5050	if (RT_SUCCESS(rc))
5051	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5052	if (RT_SUCCESS(rc))
5053	{
5054	/*
5055	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5056	*/
5057	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5058	if ( pLeaf
5059	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5060	{
5061	CPUMCPUIDLEAF Leaf;
5062	Leaf.uLeaf = 4;
5063	Leaf.fSubLeafMask = UINT32_MAX;
5064	Leaf.uSubLeaf = 0;
5065	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5066	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5067	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5068	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5069	\| UINT32_C(63); /* system coherency line size - 1 */
5070	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5071	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5072	\| (UINT32_C(1) << 5) /* cache level */
5073	\| UINT32_C(1); /* cache type (data) */
5074	Leaf.fFlags = 0;
5075	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5076	if (RT_SUCCESS(rc))
5077	{
5078	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5079	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5080	}
5081	if (RT_SUCCESS(rc))
5082	{
5083	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5084	Leaf.uEcx = 4095; /* sets - 1 */
5085	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5086	Leaf.uEbx \|= UINT32_C(23) << 22;
5087	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5088	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5089	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5090	Leaf.uEax \|= UINT32_C(2) << 5;
5091	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5092	}
5093	}
5094	}
5095	}
5096	return rc;
5097	}
5098
5099
5100	/**
5101	* Loads the CPU ID leaves saved by pass 0, inner worker.
5102	*
5103	* @returns VBox status code.
5104	* @param pVM The cross context VM structure.
5105	* @param pSSM The saved state handle.
5106	* @param uVersion The format version.
5107	* @param paLeaves Guest CPUID leaves loaded from the state.
5108	* @param cLeaves The number of leaves in @a paLeaves.
5109	*/
5110	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
5111	{
5112	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5113
5114	/*
5115	* Continue loading the state into stack buffers.
5116	*/
5117	CPUMCPUID GuestDefCpuId;
5118	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5119	AssertRCReturn(rc, rc);
5120
5121	CPUMCPUID aRawStd[16];
5122	uint32_t cRawStd;
5123	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5124	if (cRawStd > RT_ELEMENTS(aRawStd))
5125	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5126	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5127	AssertRCReturn(rc, rc);
5128	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5129	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5130
5131	CPUMCPUID aRawExt[32];
5132	uint32_t cRawExt;
5133	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5134	if (cRawExt > RT_ELEMENTS(aRawExt))
5135	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5136	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5137	AssertRCReturn(rc, rc);
5138	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5139	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5140
5141	/*
5142	* Get the raw CPU IDs for the current host.
5143	*/
5144	CPUMCPUID aHostRawStd[16];
5145	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5146	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5147
5148	CPUMCPUID aHostRawExt[32];
5149	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5150	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5151	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5152
5153	/*
5154	* Get the host and guest overrides so we don't reject the state because
5155	* some feature was enabled thru these interfaces.
5156	* Note! We currently only need the feature leaves, so skip rest.
5157	*/
5158	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5159	CPUMCPUID aHostOverrideStd[2];
5160	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5161	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5162
5163	CPUMCPUID aHostOverrideExt[2];
5164	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5165	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5166
5167	/*
5168	* This can be skipped.
5169	*/
5170	bool fStrictCpuIdChecks;
5171	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5172
5173	/*
5174	* Define a bunch of macros for simplifying the santizing/checking code below.
5175	*/
5176	/* Generic expression + failure message. */
5177	#define CPUID_CHECK_RET(expr, fmt) \
5178	do { \
5179	if (!(expr)) \
5180	{ \
5181	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5182	if (fStrictCpuIdChecks) \
5183	{ \
5184	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5185	RTStrFree(pszMsg); \
5186	return rcCpuid; \
5187	} \
5188	LogRel(("CPUM: %s\n", pszMsg)); \
5189	RTStrFree(pszMsg); \
5190	} \
5191	} while (0)
5192	#define CPUID_CHECK_WRN(expr, fmt) \
5193	do { \
5194	if (!(expr)) \
5195	LogRel(fmt); \
5196	} while (0)
5197
5198	/* For comparing two values and bitch if they differs. */
5199	#define CPUID_CHECK2_RET(what, host, saved) \
5200	do { \
5201	if ((host) != (saved)) \
5202	{ \
5203	if (fStrictCpuIdChecks) \
5204	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5205	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5206	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5207	} \
5208	} while (0)
5209	#define CPUID_CHECK2_WRN(what, host, saved) \
5210	do { \
5211	if ((host) != (saved)) \
5212	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5213	} while (0)
5214
5215	/* For checking raw cpu features (raw mode). */
5216	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5217	do { \
5218	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5219	{ \
5220	if (fStrictCpuIdChecks) \
5221	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5222	N_(#bit " mismatch: host=%d saved=%d"), \
5223	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5224	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5225	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5226	} \
5227	} while (0)
5228	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5229	do { \
5230	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5231	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5232	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5233	} while (0)
5234	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5235
5236	/* For checking guest features. */
5237	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5238	do { \
5239	if ( (aGuestCpuId##set [1].reg & bit) \
5240	&& !(aHostRaw##set [1].reg & bit) \
5241	&& !(aHostOverride##set [1].reg & bit) \
5242	) \
5243	{ \
5244	if (fStrictCpuIdChecks) \
5245	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5246	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5247	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5248	} \
5249	} while (0)
5250	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5251	do { \
5252	if ( (aGuestCpuId##set [1].reg & bit) \
5253	&& !(aHostRaw##set [1].reg & bit) \
5254	&& !(aHostOverride##set [1].reg & bit) \
5255	) \
5256	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5257	} while (0)
5258	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5259	do { \
5260	if ( (aGuestCpuId##set [1].reg & bit) \
5261	&& !(aHostRaw##set [1].reg & bit) \
5262	&& !(aHostOverride##set [1].reg & bit) \
5263	) \
5264	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5265	} while (0)
5266	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5267
5268	/* For checking guest features if AMD guest CPU. */
5269	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5270	do { \
5271	if ( (aGuestCpuId##set [1].reg & bit) \
5272	&& fGuestAmd \
5273	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5274	&& !(aHostOverride##set [1].reg & bit) \
5275	) \
5276	{ \
5277	if (fStrictCpuIdChecks) \
5278	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5279	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5280	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5281	} \
5282	} while (0)
5283	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5284	do { \
5285	if ( (aGuestCpuId##set [1].reg & bit) \
5286	&& fGuestAmd \
5287	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5288	&& !(aHostOverride##set [1].reg & bit) \
5289	) \
5290	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5291	} while (0)
5292	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5293	do { \
5294	if ( (aGuestCpuId##set [1].reg & bit) \
5295	&& fGuestAmd \
5296	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5297	&& !(aHostOverride##set [1].reg & bit) \
5298	) \
5299	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5300	} while (0)
5301	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5302
5303	/* For checking AMD features which have a corresponding bit in the standard
5304	range. (Intel defines very few bits in the extended feature sets.) */
5305	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5306	do { \
5307	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5308	&& !(fHostAmd \
5309	? aHostRawExt[1].reg & (ExtBit) \
5310	: aHostRawStd[1].reg & (StdBit)) \
5311	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5312	) \
5313	{ \
5314	if (fStrictCpuIdChecks) \
5315	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5316	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5317	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5318	} \
5319	} while (0)
5320	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5321	do { \
5322	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5323	&& !(fHostAmd \
5324	? aHostRawExt[1].reg & (ExtBit) \
5325	: aHostRawStd[1].reg & (StdBit)) \
5326	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5327	) \
5328	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5329	} while (0)
5330	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5331	do { \
5332	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5333	&& !(fHostAmd \
5334	? aHostRawExt[1].reg & (ExtBit) \
5335	: aHostRawStd[1].reg & (StdBit)) \
5336	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5337	) \
5338	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5339	} while (0)
5340	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5341
5342	/*
5343	* For raw-mode we'll require that the CPUs are very similar since we don't
5344	* intercept CPUID instructions for user mode applications.
5345	*/
5346	if (VM_IS_RAW_MODE_ENABLED(pVM))
5347	{
5348	/* CPUID(0) */
5349	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
5350	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
5351	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
5352	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5353	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
5354	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
5355	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
5356	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
5357	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5358
5359	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
5360
5361	/* CPUID(1).eax */
5362	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
5363	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
5364	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
5365
5366	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
5367	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
5368	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
5369
5370	/* CPUID(1).ecx */
5371	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
5372	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
5373	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
5374	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5375	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
5376	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
5377	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
5378	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
5379	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
5380	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
5381	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
5382	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
5383	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
5384	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
5385	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
5386	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
5387	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5388	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5389	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
5390	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
5391	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
5392	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5393	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
5394	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
5395	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5396	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
5397	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
5398	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5399	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
5400	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5401	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5402	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
5403
5404	/* CPUID(1).edx */
5405	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5406	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5407	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
5408	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5409	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
5410	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
5411	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5412	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5413	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
5414	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5415	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5416	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5417	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5418	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5419	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5420	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
5421	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5422	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5423	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5424	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
5425	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5426	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
5427	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
5428	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
5429	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
5430	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
5431	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
5432	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
5433	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
5434	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
5435	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
5436	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
5437
5438	/* CPUID(2) - config, mostly about caches. ignore. */
5439	/* CPUID(3) - processor serial number. ignore. */
5440	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
5441	/* CPUID(5) - mwait/monitor config. ignore. */
5442	/* CPUID(6) - power management. ignore. */
5443	/* CPUID(7) - ???. ignore. */
5444	/* CPUID(8) - ???. ignore. */
5445	/* CPUID(9) - DCA. ignore for now. */
5446	/* CPUID(a) - PeMo info. ignore for now. */
5447	/* CPUID(b) - topology info - takes ECX as input. ignore. */
5448
5449	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
5450	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
5451	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
5452	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
5453	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
5454	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
5455	{
5456	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
5457	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
5458	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
5459	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
5460	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
5461	}
5462
5463	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
5464	Note! Intel have/is marking many of the fields here as reserved. We
5465	will verify them as if it's an AMD CPU. */
5466	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
5467	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
5468	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
5469	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
5470	{
5471	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
5472	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
5473	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
5474	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5475	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
5476	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
5477	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
5478
5479	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
5480	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
5481	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
5482	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
5483	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
5484	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5485
5486	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
5487	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
5488	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
5489	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
5490
5491	/* CPUID(0x80000001).ecx */
5492	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
5493	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
5494	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
5495	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
5496	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
5497	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
5498	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
5499	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
5500	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
5501	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
5502	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
5503	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
5504	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
5505	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
5506	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5507	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5508	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5509	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5510	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5511	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5512	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5513	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5514	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5515	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5516	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5517	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5518	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5519	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5520	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5521	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5522	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5523	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5524
5525	/* CPUID(0x80000001).edx */
5526	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
5527	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
5528	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
5529	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
5530	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
5531	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
5532	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
5533	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
5534	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
5535	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
5536	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5537	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
5538	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
5539	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
5540	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
5541	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
5542	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
5543	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
5544	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5545	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5546	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5547	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
5548	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5549	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
5550	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
5551	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5552	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5553	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5554	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
5555	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5556	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5557	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5558
5559	/** @todo verify the rest as well. */
5560	}
5561	}
5562
5563
5564
5565	/*
5566	* Verify that we can support the features already exposed to the guest on
5567	* this host.
5568	*
5569	* Most of the features we're emulating requires intercepting instruction
5570	* and doing it the slow way, so there is no need to warn when they aren't
5571	* present in the host CPU. Thus we use IGN instead of EMU on these.
5572	*
5573	* Trailing comments:
5574	* "EMU" - Possible to emulate, could be lots of work and very slow.
5575	* "EMU?" - Can this be emulated?
5576	*/
5577	CPUMCPUID aGuestCpuIdStd[2];
5578	RT_ZERO(aGuestCpuIdStd);
5579	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5580
5581	/* CPUID(1).ecx */
5582	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5583	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5584	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5585	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5586	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5587	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5588	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5589	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5590	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5591	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5592	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5593	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5594	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5595	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5596	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5597	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5598	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5599	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5600	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5601	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5602	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5603	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5604	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5605	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5606	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5607	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5608	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5609	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5610	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5611	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5612	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5613	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5614
5615	/* CPUID(1).edx */
5616	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5617	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5618	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5619	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5620	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5621	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5622	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5623	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5624	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5625	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5626	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5627	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5628	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5629	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5630	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5631	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5632	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5633	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5634	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5635	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5636	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5637	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5638	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5639	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5640	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5641	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5642	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5643	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5644	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5645	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5646	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5647	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5648
5649	/* CPUID(0x80000000). */
5650	CPUMCPUID aGuestCpuIdExt[2];
5651	RT_ZERO(aGuestCpuIdExt);
5652	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5653	{
5654	/** @todo deal with no 0x80000001 on the host. */
5655	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5656	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5657
5658	/* CPUID(0x80000001).ecx */
5659	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5660	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5661	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5662	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5663	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5664	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5665	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5666	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5667	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5668	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5669	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5670	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5671	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5672	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5673	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5674	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5675	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5676	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5677	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5678	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5679	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5680	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5681	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5682	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5683	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5684	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5685	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5686	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5687	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5688	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5689	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5690	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5691
5692	/* CPUID(0x80000001).edx */
5693	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5694	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5695	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5696	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5697	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5698	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5699	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5700	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5701	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5702	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5703	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5704	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5705	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5706	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5707	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5708	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5709	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5710	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5711	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5712	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5713	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5714	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5715	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5716	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5717	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5718	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5719	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5720	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5721	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5722	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5723	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5724	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5725	}
5726
5727	/** @todo check leaf 7 */
5728
5729	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5730	* ECX=0: EAX - Valid bits in XCR0[31:0].
5731	* EBX - Maximum state size as per current XCR0 value.
5732	* ECX - Maximum state size for all supported features.
5733	* EDX - Valid bits in XCR0[63:32].
5734	* ECX=1: EAX - Various X-features.
5735	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5736	* ECX - Valid bits in IA32_XSS[31:0].
5737	* EDX - Valid bits in IA32_XSS[63:32].
5738	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5739	* if the bit invalid all four registers are set to zero.
5740	* EAX - The state size for this feature.
5741	* EBX - The state byte offset of this feature.
5742	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5743	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5744	*/
5745	uint64_t fGuestXcr0Mask = 0;
5746	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5747	if ( pCurLeaf
5748	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5749	&& ( pCurLeaf->uEax
5750	\|\| pCurLeaf->uEbx
5751	\|\| pCurLeaf->uEcx
5752	\|\| pCurLeaf->uEdx) )
5753	{
5754	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5755	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5756	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5757	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5758	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5759	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5760	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5761	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5762
5763	/* We don't support any additional features yet. */
5764	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5765	if (pCurLeaf && pCurLeaf->uEax)
5766	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5767	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5768	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5769	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5770	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5771	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5772
5773
5774	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5775	{
5776	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5777	if (pCurLeaf)
5778	{
5779	/* If advertised, the state component offset and size must match the one used by host. */
5780	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5781	{
5782	CPUMCPUID RawHost;
5783	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5784	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5785	if ( RawHost.uEbx != pCurLeaf->uEbx
5786	\|\| RawHost.uEax != pCurLeaf->uEax)
5787	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5788	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5789	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5790	}
5791	}
5792	}
5793	}
5794	/* Clear leaf 0xd just in case we're loading an old state... */
5795	else if (pCurLeaf)
5796	{
5797	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5798	{
5799	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5800	if (pCurLeaf)
5801	{
5802	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5803	\|\| ( pCurLeaf->uEax == 0
5804	&& pCurLeaf->uEbx == 0
5805	&& pCurLeaf->uEcx == 0
5806	&& pCurLeaf->uEdx == 0),
5807	("uVersion=%#x; %#x %#x %#x %#x\n",
5808	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5809	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5810	}
5811	}
5812	}
5813
5814	/* Update the fXStateGuestMask value for the VM. */
5815	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5816	{
5817	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5818	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5819	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5820	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5821	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5822	}
5823
5824	#undef CPUID_CHECK_RET
5825	#undef CPUID_CHECK_WRN
5826	#undef CPUID_CHECK2_RET
5827	#undef CPUID_CHECK2_WRN
5828	#undef CPUID_RAW_FEATURE_RET
5829	#undef CPUID_RAW_FEATURE_WRN
5830	#undef CPUID_RAW_FEATURE_IGN
5831	#undef CPUID_GST_FEATURE_RET
5832	#undef CPUID_GST_FEATURE_WRN
5833	#undef CPUID_GST_FEATURE_EMU
5834	#undef CPUID_GST_FEATURE_IGN
5835	#undef CPUID_GST_FEATURE2_RET
5836	#undef CPUID_GST_FEATURE2_WRN
5837	#undef CPUID_GST_FEATURE2_EMU
5838	#undef CPUID_GST_FEATURE2_IGN
5839	#undef CPUID_GST_AMD_FEATURE_RET
5840	#undef CPUID_GST_AMD_FEATURE_WRN
5841	#undef CPUID_GST_AMD_FEATURE_EMU
5842	#undef CPUID_GST_AMD_FEATURE_IGN
5843
5844	/*
5845	* We're good, commit the CPU ID leaves.
5846	*/
5847	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5848	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5849	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5850	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
5851	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5852	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
5853	AssertLogRelRCReturn(rc, rc);
5854
5855	return VINF_SUCCESS;
5856	}
5857
5858
5859	/**
5860	* Loads the CPU ID leaves saved by pass 0.
5861	*
5862	* @returns VBox status code.
5863	* @param pVM The cross context VM structure.
5864	* @param pSSM The saved state handle.
5865	* @param uVersion The format version.
5866	*/
5867	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5868	{
5869	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5870
5871	/*
5872	* Load the CPUID leaves array first and call worker to do the rest, just so
5873	* we can free the memory when we need to without ending up in column 1000.
5874	*/
5875	PCPUMCPUIDLEAF paLeaves;
5876	uint32_t cLeaves;
5877	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5878	AssertRC(rc);
5879	if (RT_SUCCESS(rc))
5880	{
5881	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
5882	RTMemFree(paLeaves);
5883	}
5884	return rc;
5885	}
5886
5887
5888
5889	/**
5890	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5891	*
5892	* @returns VBox status code.
5893	* @param pVM The cross context VM structure.
5894	* @param pSSM The saved state handle.
5895	* @param uVersion The format version.
5896	*/
5897	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5898	{
5899	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5900
5901	/*
5902	* Restore the CPUID leaves.
5903	*
5904	* Note that we support restoring less than the current amount of standard
5905	* leaves because we've been allowed more is newer version of VBox.
5906	*/
5907	uint32_t cElements;
5908	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5909	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5910	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5911	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5912
5913	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5914	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5915	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5916	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5917
5918	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5919	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5920	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5921	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5922
5923	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5924
5925	/*
5926	* Check that the basic cpuid id information is unchanged.
5927	*/
5928	/** @todo we should check the 64 bits capabilities too! */
5929	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5930	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5931	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5932	uint32_t au32CpuIdSaved[8];
5933	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5934	if (RT_SUCCESS(rc))
5935	{
5936	/* Ignore CPU stepping. */
5937	au32CpuId[4] &= 0xfffffff0;
5938	au32CpuIdSaved[4] &= 0xfffffff0;
5939
5940	/* Ignore APIC ID (AMD specs). */
5941	au32CpuId[5] &= ~0xff000000;
5942	au32CpuIdSaved[5] &= ~0xff000000;
5943
5944	/* Ignore the number of Logical CPUs (AMD specs). */
5945	au32CpuId[5] &= ~0x00ff0000;
5946	au32CpuIdSaved[5] &= ~0x00ff0000;
5947
5948	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5949	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5950	\| X86_CPUID_FEATURE_ECX_VMX
5951	\| X86_CPUID_FEATURE_ECX_SMX
5952	\| X86_CPUID_FEATURE_ECX_EST
5953	\| X86_CPUID_FEATURE_ECX_TM2
5954	\| X86_CPUID_FEATURE_ECX_CNTXID
5955	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5956	\| X86_CPUID_FEATURE_ECX_PDCM
5957	\| X86_CPUID_FEATURE_ECX_DCA
5958	\| X86_CPUID_FEATURE_ECX_X2APIC
5959	);
5960	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5961	\| X86_CPUID_FEATURE_ECX_VMX
5962	\| X86_CPUID_FEATURE_ECX_SMX
5963	\| X86_CPUID_FEATURE_ECX_EST
5964	\| X86_CPUID_FEATURE_ECX_TM2
5965	\| X86_CPUID_FEATURE_ECX_CNTXID
5966	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5967	\| X86_CPUID_FEATURE_ECX_PDCM
5968	\| X86_CPUID_FEATURE_ECX_DCA
5969	\| X86_CPUID_FEATURE_ECX_X2APIC
5970	);
5971
5972	/* Make sure we don't forget to update the masks when enabling
5973	* features in the future.
5974	*/
5975	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5976	( X86_CPUID_FEATURE_ECX_DTES64
5977	\| X86_CPUID_FEATURE_ECX_VMX
5978	\| X86_CPUID_FEATURE_ECX_SMX
5979	\| X86_CPUID_FEATURE_ECX_EST
5980	\| X86_CPUID_FEATURE_ECX_TM2
5981	\| X86_CPUID_FEATURE_ECX_CNTXID
5982	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5983	\| X86_CPUID_FEATURE_ECX_PDCM
5984	\| X86_CPUID_FEATURE_ECX_DCA
5985	\| X86_CPUID_FEATURE_ECX_X2APIC
5986	)));
5987	/* do the compare */
5988	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5989	{
5990	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5991	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5992	"Saved=%.*Rhxs\n"
5993	"Real =%.*Rhxs\n",
5994	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5995	sizeof(au32CpuId), au32CpuId));
5996	else
5997	{
5998	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5999	"Saved=%.*Rhxs\n"
6000	"Real =%.*Rhxs\n",
6001	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6002	sizeof(au32CpuId), au32CpuId));
6003	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
6004	}
6005	}
6006	}
6007
6008	return rc;
6009	}
6010
6011
6012
6013	/*
6014	*
6015	*
6016	* CPUID Info Handler.
6017	* CPUID Info Handler.
6018	* CPUID Info Handler.
6019	*
6020	*
6021	*/
6022
6023
6024
6025	/**
6026	* Get L1 cache / TLS associativity.
6027	*/
6028	static const char getCacheAss(unsigned u, char pszBuf)
6029	{
6030	if (u == 0)
6031	return "res0 ";
6032	if (u == 1)
6033	return "direct";
6034	if (u == 255)
6035	return "fully";
6036	if (u >= 256)
6037	return "???";
6038
6039	RTStrPrintf(pszBuf, 16, "%d way", u);
6040	return pszBuf;
6041	}
6042
6043
6044	/**
6045	* Get L2 cache associativity.
6046	*/
6047	const char *getL2CacheAss(unsigned u)
6048	{
6049	switch (u)
6050	{
6051	case 0: return "off ";
6052	case 1: return "direct";
6053	case 2: return "2 way ";
6054	case 3: return "res3 ";
6055	case 4: return "4 way ";
6056	case 5: return "res5 ";
6057	case 6: return "8 way ";
6058	case 7: return "res7 ";
6059	case 8: return "16 way";
6060	case 9: return "res9 ";
6061	case 10: return "res10 ";
6062	case 11: return "res11 ";
6063	case 12: return "res12 ";
6064	case 13: return "res13 ";
6065	case 14: return "res14 ";
6066	case 15: return "fully ";
6067	default: return "????";
6068	}
6069	}
6070
6071
6072	/** CPUID(1).EDX field descriptions. */
6073	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6074	{
6075	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6076	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6077	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6078	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6079	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6080	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6081	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6082	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6083	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6084	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6085	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6086	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6087	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6088	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6089	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6090	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6091	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6092	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6093	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6094	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6095	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6096	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6097	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6098	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6099	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6100	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6101	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6102	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6103	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6104	DBGFREGSUBFIELD_TERMINATOR()
6105	};
6106
6107	/** CPUID(1).ECX field descriptions. */
6108	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6109	{
6110	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6111	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6112	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6113	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6114	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6115	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6116	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6117	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6118	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6119	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6120	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6121	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6122	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6123	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6124	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6125	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6126	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6127	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6128	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6129	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6130	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6131	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6132	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6133	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6134	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6135	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6136	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6137	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6138	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6139	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6140	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6141	DBGFREGSUBFIELD_TERMINATOR()
6142	};
6143
6144	/** CPUID(7,0).EBX field descriptions. */
6145	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6146	{
6147	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6148	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6149	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6150	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6151	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6152	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6153	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6154	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6155	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6156	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6157	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6158	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6159	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6160	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6161	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6162	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6163	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6164	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6165	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6166	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6167	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6168	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6169	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6170	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6171	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6172	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6173	DBGFREGSUBFIELD_TERMINATOR()
6174	};
6175
6176	/** CPUID(7,0).ECX field descriptions. */
6177	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6178	{
6179	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6180	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6181	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6182	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6183	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6184	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6185	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6186	DBGFREGSUBFIELD_TERMINATOR()
6187	};
6188
6189	/** CPUID(7,0).EDX field descriptions. */
6190	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6191	{
6192	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6193	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6194	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6195	DBGFREGSUBFIELD_TERMINATOR()
6196	};
6197
6198
6199	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6200	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6201	{
6202	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6203	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6204	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6205	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6206	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6207	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6208	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6209	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6210	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6211	DBGFREGSUBFIELD_TERMINATOR()
6212	};
6213
6214	/** CPUID(13,1).EAX field descriptions. */
6215	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6216	{
6217	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6218	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6219	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6220	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6221	DBGFREGSUBFIELD_TERMINATOR()
6222	};
6223
6224
6225	/** CPUID(0x80000001,0).EDX field descriptions. */
6226	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6227	{
6228	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6229	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6230	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6231	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6232	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6233	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6234	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6235	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6236	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6237	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6238	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6239	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6240	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6241	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6242	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6243	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6244	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6245	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6246	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6247	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6248	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6249	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6250	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6251	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6252	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6253	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6254	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6255	DBGFREGSUBFIELD_TERMINATOR()
6256	};
6257
6258	/** CPUID(0x80000001,0).ECX field descriptions. */
6259	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6260	{
6261	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6262	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6263	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6264	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6265	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6266	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6267	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6268	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6269	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6270	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6271	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6272	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6273	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6274	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6275	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6276	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6277	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6278	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6279	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6280	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6281	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6282	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6283	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6284	DBGFREGSUBFIELD_TERMINATOR()
6285	};
6286
6287	/** CPUID(0x8000000a,0).EDX field descriptions. */
6288	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6289	{
6290	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6291	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6292	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6293	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6294	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6295	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6296	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6297	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6298	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6299	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6300	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6301	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6302	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6303	DBGFREGSUBFIELD_TERMINATOR()
6304	};
6305
6306
6307	/** CPUID(0x80000007,0).EDX field descriptions. */
6308	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6309	{
6310	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6311	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6312	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6313	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6314	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6315	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6316	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6317	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6318	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6319	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6320	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6321	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6322	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6323	DBGFREGSUBFIELD_TERMINATOR()
6324	};
6325
6326	/** CPUID(0x80000008,0).EBX field descriptions. */
6327	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6328	{
6329	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6330	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6331	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6332	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6333	DBGFREGSUBFIELD_TERMINATOR()
6334	};
6335
6336
6337	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6338	const char *pszLeadIn, uint32_t cchWidth)
6339	{
6340	if (pszLeadIn)
6341	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6342
6343	for (uint32_t iBit = 0; iBit < 32; iBit++)
6344	if (RT_BIT_32(iBit) & uVal)
6345	{
6346	while ( pDesc->pszName != NULL
6347	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6348	pDesc++;
6349	if ( pDesc->pszName != NULL
6350	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6351	{
6352	if (pDesc->cBits == 1)
6353	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6354	else
6355	{
6356	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6357	if (pDesc->cBits < 32)
6358	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6359	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6360	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6361	}
6362	}
6363	else
6364	pHlp->pfnPrintf(pHlp, " %u", iBit);
6365	}
6366	if (pszLeadIn)
6367	pHlp->pfnPrintf(pHlp, "\n");
6368	}
6369
6370
6371	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6372	const char *pszLeadIn, uint32_t cchWidth)
6373	{
6374	if (pszLeadIn)
6375	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6376
6377	for (uint32_t iBit = 0; iBit < 64; iBit++)
6378	if (RT_BIT_64(iBit) & uVal)
6379	{
6380	while ( pDesc->pszName != NULL
6381	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6382	pDesc++;
6383	if ( pDesc->pszName != NULL
6384	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6385	{
6386	if (pDesc->cBits == 1)
6387	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6388	else
6389	{
6390	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6391	if (pDesc->cBits < 64)
6392	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6393	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6394	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6395	}
6396	}
6397	else
6398	pHlp->pfnPrintf(pHlp, " %u", iBit);
6399	}
6400	if (pszLeadIn)
6401	pHlp->pfnPrintf(pHlp, "\n");
6402	}
6403
6404
6405	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6406	const char *pszLeadIn, uint32_t cchWidth)
6407	{
6408	if (!uVal)
6409	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6410	else
6411	{
6412	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6413	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6414	pHlp->pfnPrintf(pHlp, " )\n");
6415	}
6416	}
6417
6418
6419	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6420	uint32_t cchWidth)
6421	{
6422	uint32_t uCombined = uVal1 \| uVal2;
6423	for (uint32_t iBit = 0; iBit < 32; iBit++)
6424	if ( (RT_BIT_32(iBit) & uCombined)
6425	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6426	{
6427	while ( pDesc->pszName != NULL
6428	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6429	pDesc++;
6430
6431	if ( pDesc->pszName != NULL
6432	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6433	{
6434	size_t cchMnemonic = strlen(pDesc->pszName);
6435	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6436	size_t cchDesc = strlen(pszDesc);
6437	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6438	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6439	if (pDesc->cBits < 32)
6440	{
6441	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6442	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6443	}
6444
6445	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6446	pDesc->pszName, pszDesc,
6447	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6448	uFieldValue1, uFieldValue2);
6449
6450	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6451	pDesc++;
6452	}
6453	else
6454	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6455	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6456	}
6457	}
6458
6459
6460	/**
6461	* Produces a detailed summary of standard leaf 0x00000001.
6462	*
6463	* @param pHlp The info helper functions.
6464	* @param pCurLeaf The 0x00000001 leaf.
6465	* @param fVerbose Whether to be very verbose or not.
6466	* @param fIntel Set if intel CPU.
6467	*/
6468	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6469	{
6470	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6471	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6472	uint32_t uEAX = pCurLeaf->uEax;
6473	uint32_t uEBX = pCurLeaf->uEbx;
6474
6475	pHlp->pfnPrintf(pHlp,
6476	"%36s %2d \tExtended: %d \tEffective: %d\n"
6477	"%36s %2d \tExtended: %d \tEffective: %d\n"
6478	"%36s %d\n"
6479	"%36s %d (%s)\n"
6480	"%36s %#04x\n"
6481	"%36s %d\n"
6482	"%36s %d\n"
6483	"%36s %#04x\n"
6484	,
6485	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6486	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6487	"Stepping:", ASMGetCpuStepping(uEAX),
6488	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6489	"APIC ID:", (uEBX >> 24) & 0xff,
6490	"Logical CPUs:",(uEBX >> 16) & 0xff,
6491	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6492	"Brand ID:", (uEBX >> 0) & 0xff);
6493	if (fVerbose)
6494	{
6495	CPUMCPUID Host;
6496	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6497	pHlp->pfnPrintf(pHlp, "Features\n");
6498	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6499	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6500	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6501	}
6502	else
6503	{
6504	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6505	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6506	}
6507	}
6508
6509
6510	/**
6511	* Produces a detailed summary of standard leaf 0x00000007.
6512	*
6513	* @param pHlp The info helper functions.
6514	* @param paLeaves The CPUID leaves array.
6515	* @param cLeaves The number of leaves in the array.
6516	* @param pCurLeaf The first 0x00000007 leaf.
6517	* @param fVerbose Whether to be very verbose or not.
6518	*/
6519	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6520	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6521	{
6522	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6523	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6524	for (;;)
6525	{
6526	CPUMCPUID Host;
6527	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6528
6529	switch (pCurLeaf->uSubLeaf)
6530	{
6531	case 0:
6532	if (fVerbose)
6533	{
6534	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6535	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6536	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6537	if (pCurLeaf->uEdx \|\| Host.uEdx)
6538	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6539	}
6540	else
6541	{
6542	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6543	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6544	if (pCurLeaf->uEdx)
6545	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6546	}
6547	break;
6548
6549	default:
6550	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6551	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6552	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6553	break;
6554
6555	}
6556
6557	/* advance. */
6558	pCurLeaf++;
6559	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6560	\|\| pCurLeaf->uLeaf != 0x7)
6561	break;
6562	}
6563	}
6564
6565
6566	/**
6567	* Produces a detailed summary of standard leaf 0x0000000d.
6568	*
6569	* @param pHlp The info helper functions.
6570	* @param paLeaves The CPUID leaves array.
6571	* @param cLeaves The number of leaves in the array.
6572	* @param pCurLeaf The first 0x00000007 leaf.
6573	* @param fVerbose Whether to be very verbose or not.
6574	*/
6575	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6576	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6577	{
6578	RT_NOREF_PV(fVerbose);
6579	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6580	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6581	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6582	{
6583	CPUMCPUID Host;
6584	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6585
6586	switch (uSubLeaf)
6587	{
6588	case 0:
6589	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6590	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6591	pCurLeaf->uEbx, pCurLeaf->uEcx);
6592	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6593
6594	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6595	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6596	"Valid XCR0 bits, guest:", 42);
6597	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6598	"Valid XCR0 bits, host:", 42);
6599	break;
6600
6601	case 1:
6602	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6603	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6604	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6605
6606	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6607	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6608	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6609
6610	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6611	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6612	" Valid IA32_XSS bits, guest:", 42);
6613	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6614	" Valid IA32_XSS bits, host:", 42);
6615	break;
6616
6617	default:
6618	if ( pCurLeaf
6619	&& pCurLeaf->uSubLeaf == uSubLeaf
6620	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6621	{
6622	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6623	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6624	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6625	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6626	if (pCurLeaf->uEdx)
6627	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6628	pHlp->pfnPrintf(pHlp, " --");
6629	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6630	pHlp->pfnPrintf(pHlp, "\n");
6631	}
6632	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6633	{
6634	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6635	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6636	if (Host.uEcx & ~RT_BIT_32(0))
6637	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6638	if (Host.uEdx)
6639	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6640	pHlp->pfnPrintf(pHlp, " --");
6641	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6642	pHlp->pfnPrintf(pHlp, "\n");
6643	}
6644	break;
6645
6646	}
6647
6648	/* advance. */
6649	if (pCurLeaf)
6650	{
6651	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6652	&& pCurLeaf->uSubLeaf <= uSubLeaf
6653	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6654	pCurLeaf++;
6655	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6656	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6657	pCurLeaf = NULL;
6658	}
6659	}
6660	}
6661
6662
6663	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6664	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6665	{
6666	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6667	&& pCurLeaf->uLeaf <= uUpToLeaf)
6668	{
6669	pHlp->pfnPrintf(pHlp,
6670	" %s\n"
6671	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6672	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6673	&& pCurLeaf->uLeaf <= uUpToLeaf)
6674	{
6675	CPUMCPUID Host;
6676	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6677	pHlp->pfnPrintf(pHlp,
6678	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6679	"Hst: %08x %08x %08x %08x\n",
6680	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6681	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6682	pCurLeaf++;
6683	}
6684	}
6685
6686	return pCurLeaf;
6687	}
6688
6689
6690	/**
6691	* Display the guest CpuId leaves.
6692	*
6693	* @param pVM The cross context VM structure.
6694	* @param pHlp The info helper functions.
6695	* @param pszArgs "terse", "default" or "verbose".
6696	*/
6697	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6698	{
6699	/*
6700	* Parse the argument.
6701	*/
6702	unsigned iVerbosity = 1;
6703	if (pszArgs)
6704	{
6705	pszArgs = RTStrStripL(pszArgs);
6706	if (!strcmp(pszArgs, "terse"))
6707	iVerbosity--;
6708	else if (!strcmp(pszArgs, "verbose"))
6709	iVerbosity++;
6710	}
6711
6712	uint32_t uLeaf;
6713	CPUMCPUID Host;
6714	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6715	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6716	PCCPUMCPUIDLEAF pCurLeaf;
6717	PCCPUMCPUIDLEAF pNextLeaf;
6718	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6719	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6720	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6721
6722	/*
6723	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6724	*/
6725	uint32_t cHstMax = ASMCpuId_EAX(0);
6726	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6727	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6728	pHlp->pfnPrintf(pHlp,
6729	" Raw Standard CPUID Leaves\n"
6730	" Leaf/sub-leaf eax ebx ecx edx\n");
6731	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6732	{
6733	uint32_t cMaxSubLeaves = 1;
6734	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6735	cMaxSubLeaves = 16;
6736	else if (uLeaf == 0xd)
6737	cMaxSubLeaves = 128;
6738
6739	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6740	{
6741	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6742	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6743	&& pCurLeaf->uLeaf == uLeaf
6744	&& pCurLeaf->uSubLeaf == uSubLeaf)
6745	{
6746	pHlp->pfnPrintf(pHlp,
6747	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6748	"Hst: %08x %08x %08x %08x\n",
6749	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6750	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6751	pCurLeaf++;
6752	}
6753	else if ( uLeaf != 0xd
6754	\|\| uSubLeaf <= 1
6755	\|\| Host.uEbx != 0 )
6756	pHlp->pfnPrintf(pHlp,
6757	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6758	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6759
6760	/* Done? */
6761	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6762	\|\| pCurLeaf->uLeaf != uLeaf)
6763	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6764	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6765	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6766	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6767	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6768	)
6769	)
6770	break;
6771	}
6772	}
6773	pNextLeaf = pCurLeaf;
6774
6775	/*
6776	* If verbose, decode it.
6777	*/
6778	if (iVerbosity && paLeaves[0].uLeaf == 0)
6779	pHlp->pfnPrintf(pHlp,
6780	"%36s %.04s%.04s%.04s\n"
6781	"%36s 0x00000000-%#010x\n"
6782	,
6783	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6784	"Supports:", paLeaves[0].uEax);
6785
6786	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6787	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6788
6789	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6790	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6791
6792	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6793	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6794
6795	pCurLeaf = pNextLeaf;
6796
6797	/*
6798	* Hypervisor leaves.
6799	*
6800	* Unlike most of the other leaves reported, the guest hypervisor leaves
6801	* aren't a subset of the host CPUID bits.
6802	*/
6803	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6804
6805	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6806	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6807	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6808	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6809	cMax = RT_MAX(cHstMax, cGstMax);
6810	if (cMax >= UINT32_C(0x40000000))
6811	{
6812	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6813
6814	/** @todo dump these in more detail. */
6815
6816	pCurLeaf = pNextLeaf;
6817	}
6818
6819
6820	/*
6821	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6822	* Implemented after AMD specs.
6823	*/
6824	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6825
6826	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6827	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6828	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6829	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6830	cMax = RT_MAX(cHstMax, cGstMax);
6831	if (cMax >= UINT32_C(0x80000000))
6832	{
6833
6834	pHlp->pfnPrintf(pHlp,
6835	" Raw Extended CPUID Leaves\n"
6836	" Leaf/sub-leaf eax ebx ecx edx\n");
6837	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6838	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6839	{
6840	uint32_t cMaxSubLeaves = 1;
6841	if (uLeaf == UINT32_C(0x8000001d))
6842	cMaxSubLeaves = 16;
6843
6844	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6845	{
6846	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6847	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6848	&& pCurLeaf->uLeaf == uLeaf
6849	&& pCurLeaf->uSubLeaf == uSubLeaf)
6850	{
6851	pHlp->pfnPrintf(pHlp,
6852	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6853	"Hst: %08x %08x %08x %08x\n",
6854	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6855	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6856	pCurLeaf++;
6857	}
6858	else if ( uLeaf != 0xd
6859	\|\| uSubLeaf <= 1
6860	\|\| Host.uEbx != 0 )
6861	pHlp->pfnPrintf(pHlp,
6862	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6863	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6864
6865	/* Done? */
6866	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6867	\|\| pCurLeaf->uLeaf != uLeaf)
6868	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6869	break;
6870	}
6871	}
6872	pNextLeaf = pCurLeaf;
6873
6874	/*
6875	* Understandable output
6876	*/
6877	if (iVerbosity)
6878	pHlp->pfnPrintf(pHlp,
6879	"Ext Name: %.4s%.4s%.4s\n"
6880	"Ext Supports: 0x80000000-%#010x\n",
6881	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6882
6883	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6884	if (iVerbosity && pCurLeaf)
6885	{
6886	uint32_t uEAX = pCurLeaf->uEax;
6887	pHlp->pfnPrintf(pHlp,
6888	"Family: %d \tExtended: %d \tEffective: %d\n"
6889	"Model: %d \tExtended: %d \tEffective: %d\n"
6890	"Stepping: %d\n"
6891	"Brand ID: %#05x\n",
6892	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6893	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6894	ASMGetCpuStepping(uEAX),
6895	pCurLeaf->uEbx & 0xfff);
6896
6897	if (iVerbosity == 1)
6898	{
6899	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6900	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6901	}
6902	else
6903	{
6904	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6905	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6906	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6907	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6908	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6909	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
6910	{
6911	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
6912	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6913	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
6914	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
6915	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
6916	}
6917	}
6918	}
6919
6920	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6921	{
6922	char szString[443+1] = {0};
6923	uint32_t pu32 = (uint32_t )szString;
6924	*pu32++ = pCurLeaf->uEax;
6925	*pu32++ = pCurLeaf->uEbx;
6926	*pu32++ = pCurLeaf->uEcx;
6927	*pu32++ = pCurLeaf->uEdx;
6928	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6929	if (pCurLeaf)
6930	{
6931	*pu32++ = pCurLeaf->uEax;
6932	*pu32++ = pCurLeaf->uEbx;
6933	*pu32++ = pCurLeaf->uEcx;
6934	*pu32++ = pCurLeaf->uEdx;
6935	}
6936	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6937	if (pCurLeaf)
6938	{
6939	*pu32++ = pCurLeaf->uEax;
6940	*pu32++ = pCurLeaf->uEbx;
6941	*pu32++ = pCurLeaf->uEcx;
6942	*pu32++ = pCurLeaf->uEdx;
6943	}
6944	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6945	}
6946
6947	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6948	{
6949	uint32_t uEAX = pCurLeaf->uEax;
6950	uint32_t uEBX = pCurLeaf->uEbx;
6951	uint32_t uECX = pCurLeaf->uEcx;
6952	uint32_t uEDX = pCurLeaf->uEdx;
6953	char sz1[32];
6954	char sz2[32];
6955
6956	pHlp->pfnPrintf(pHlp,
6957	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6958	"TLB 2/4M Data: %s %3d entries\n",
6959	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6960	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6961	pHlp->pfnPrintf(pHlp,
6962	"TLB 4K Instr/Uni: %s %3d entries\n"
6963	"TLB 4K Data: %s %3d entries\n",
6964	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6965	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6966	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6967	"L1 Instr Cache Lines Per Tag: %d\n"
6968	"L1 Instr Cache Associativity: %s\n"
6969	"L1 Instr Cache Size: %d KB\n",
6970	(uEDX >> 0) & 0xff,
6971	(uEDX >> 8) & 0xff,
6972	getCacheAss((uEDX >> 16) & 0xff, sz1),
6973	(uEDX >> 24) & 0xff);
6974	pHlp->pfnPrintf(pHlp,
6975	"L1 Data Cache Line Size: %d bytes\n"
6976	"L1 Data Cache Lines Per Tag: %d\n"
6977	"L1 Data Cache Associativity: %s\n"
6978	"L1 Data Cache Size: %d KB\n",
6979	(uECX >> 0) & 0xff,
6980	(uECX >> 8) & 0xff,
6981	getCacheAss((uECX >> 16) & 0xff, sz1),
6982	(uECX >> 24) & 0xff);
6983	}
6984
6985	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6986	{
6987	uint32_t uEAX = pCurLeaf->uEax;
6988	uint32_t uEBX = pCurLeaf->uEbx;
6989	uint32_t uEDX = pCurLeaf->uEdx;
6990
6991	pHlp->pfnPrintf(pHlp,
6992	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6993	"L2 TLB 2/4M Data: %s %4d entries\n",
6994	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6995	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6996	pHlp->pfnPrintf(pHlp,
6997	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6998	"L2 TLB 4K Data: %s %4d entries\n",
6999	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
7000	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
7001	pHlp->pfnPrintf(pHlp,
7002	"L2 Cache Line Size: %d bytes\n"
7003	"L2 Cache Lines Per Tag: %d\n"
7004	"L2 Cache Associativity: %s\n"
7005	"L2 Cache Size: %d KB\n",
7006	(uEDX >> 0) & 0xff,
7007	(uEDX >> 8) & 0xf,
7008	getL2CacheAss((uEDX >> 12) & 0xf),
7009	(uEDX >> 16) & 0xffff);
7010	}
7011
7012	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
7013	{
7014	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7015	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
7016	{
7017	if (iVerbosity < 1)
7018	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7019	else
7020	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7021	}
7022	}
7023
7024	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7025	if (pCurLeaf != NULL)
7026	{
7027	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7028	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7029	{
7030	if (iVerbosity < 1)
7031	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7032	else
7033	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7034	}
7035
7036	if (iVerbosity)
7037	{
7038	uint32_t uEAX = pCurLeaf->uEax;
7039	uint32_t uECX = pCurLeaf->uEcx;
7040
7041	pHlp->pfnPrintf(pHlp,
7042	"Physical Address Width: %d bits\n"
7043	"Virtual Address Width: %d bits\n"
7044	"Guest Physical Address Width: %d bits\n",
7045	(uEAX >> 0) & 0xff,
7046	(uEAX >> 8) & 0xff,
7047	(uEAX >> 16) & 0xff);
7048	pHlp->pfnPrintf(pHlp,
7049	"Physical Core Count: %d\n",
7050	((uECX >> 0) & 0xff) + 1);
7051	}
7052	}
7053
7054	pCurLeaf = pNextLeaf;
7055	}
7056
7057
7058
7059	/*
7060	* Centaur.
7061	*/
7062	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7063
7064	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7065	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7066	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7067	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7068	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7069	cMax = RT_MAX(cHstMax, cGstMax);
7070	if (cMax >= UINT32_C(0xc0000000))
7071	{
7072	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7073
7074	/*
7075	* Understandable output
7076	*/
7077	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7078	pHlp->pfnPrintf(pHlp,
7079	"Centaur Supports: 0xc0000000-%#010x\n",
7080	pCurLeaf->uEax);
7081
7082	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7083	{
7084	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7085	uint32_t uEdxGst = pCurLeaf->uEdx;
7086	uint32_t uEdxHst = Host.uEdx;
7087
7088	if (iVerbosity == 1)
7089	{
7090	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7091	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7092	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7093	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7094	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7095	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7096	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7097	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7098	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7099	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7100	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7101	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7102	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7103	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7104	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7105	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7106	for (unsigned iBit = 14; iBit < 32; iBit++)
7107	if (uEdxGst & RT_BIT(iBit))
7108	pHlp->pfnPrintf(pHlp, " %d", iBit);
7109	pHlp->pfnPrintf(pHlp, "\n");
7110	}
7111	else
7112	{
7113	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7114	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7115	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7116	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7117	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7118	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7119	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7120	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7121	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7122	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7123	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7124	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7125	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7126	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7127	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7128	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7129	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7130	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7131	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7132	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7133	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7134	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7135	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7136	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7137	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7138	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7139	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7140	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7141	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7142	for (unsigned iBit = 27; iBit < 32; iBit++)
7143	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7144	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7145	pHlp->pfnPrintf(pHlp, "\n");
7146	}
7147	}
7148
7149	pCurLeaf = pNextLeaf;
7150	}
7151
7152	/*
7153	* The remainder.
7154	*/
7155	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7156	}
7157
7158
7159
7160
7161
7162	/*
7163	*
7164	*
7165	* PATM interfaces.
7166	* PATM interfaces.
7167	* PATM interfaces.
7168	*
7169	*
7170	*/
7171
7172
7173	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
7174	/** @name Patchmanager CPUID legacy table APIs
7175	* @{
7176	*/
7177
7178	/**
7179	* Gets a pointer to the default CPUID leaf.
7180	*
7181	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
7182	* @param pVM The cross context VM structure.
7183	* @remark Intended for PATM only.
7184	*/
7185	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
7186	{
7187	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
7188	}
7189
7190
7191	/**
7192	* Gets a number of standard CPUID leaves (PATM only).
7193	*
7194	* @returns Number of leaves.
7195	* @param pVM The cross context VM structure.
7196	* @remark Intended for PATM - legacy, don't use in new code.
7197	*/
7198	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
7199	{
7200	RT_NOREF_PV(pVM);
7201	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
7202	}
7203
7204
7205	/**
7206	* Gets a number of extended CPUID leaves (PATM only).
7207	*
7208	* @returns Number of leaves.
7209	* @param pVM The cross context VM structure.
7210	* @remark Intended for PATM - legacy, don't use in new code.
7211	*/
7212	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
7213	{
7214	RT_NOREF_PV(pVM);
7215	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
7216	}
7217
7218
7219	/**
7220	* Gets a number of centaur CPUID leaves.
7221	*
7222	* @returns Number of leaves.
7223	* @param pVM The cross context VM structure.
7224	* @remark Intended for PATM - legacy, don't use in new code.
7225	*/
7226	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
7227	{
7228	RT_NOREF_PV(pVM);
7229	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
7230	}
7231
7232
7233	/**
7234	* Gets a pointer to the array of standard CPUID leaves.
7235	*
7236	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
7237	*
7238	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
7239	* @param pVM The cross context VM structure.
7240	* @remark Intended for PATM - legacy, don't use in new code.
7241	*/
7242	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
7243	{
7244	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
7245	}
7246
7247
7248	/**
7249	* Gets a pointer to the array of extended CPUID leaves.
7250	*
7251	* CPUMGetGuestCpuIdExtMax() give the size of the array.
7252	*
7253	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
7254	* @param pVM The cross context VM structure.
7255	* @remark Intended for PATM - legacy, don't use in new code.
7256	*/
7257	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
7258	{
7259	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
7260	}
7261
7262
7263	/**
7264	* Gets a pointer to the array of centaur CPUID leaves.
7265	*
7266	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
7267	*
7268	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
7269	* @param pVM The cross context VM structure.
7270	* @remark Intended for PATM - legacy, don't use in new code.
7271	*/
7272	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
7273	{
7274	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
7275	}
7276
7277	/** @} */
7278	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
7279
7280	#endif /* VBOX_IN_VMM */
7281

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 74113

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