CPUMR3CpuId.cpp@ 74168

Last change on this file since 74168 was 74163, checked in by vboxsync, 6 years ago
VMM: Nested VMX: bugref:9180 vmlaunch/vmresume bits.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 338.6 KB

Line
1	/* $Id: CPUMR3CpuId.cpp 74163 2018-09-09 15:51:39Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/mm.h>
31	#include <VBox/sup.h>
32
33	#include <VBox/err.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/ctype.h>
36	#include <iprt/mem.h>
37	#include <iprt/string.h>
38
39
40	/*********************************************************************************************************************************
41	* Defined Constants And Macros *
42	*********************************************************************************************************************************/
43	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
44	#define CPUM_CPUID_MAX_LEAVES 2048
45	/* Max size we accept for the XSAVE area. */
46	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
47	/* Min size we accept for the XSAVE area. */
48	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
49
50
51	/*********************************************************************************************************************************
52	* Global Variables *
53	*********************************************************************************************************************************/
54	/**
55	* The intel pentium family.
56	*/
57	static const CPUMMICROARCH g_aenmIntelFamily06[] =
58	{
59	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
60	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
61	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
63	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
64	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
65	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
66	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
67	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
68	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
69	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
70	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
71	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
72	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
73	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
74	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
75	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
81	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
82	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
83	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
86	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
88	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
89	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
90	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
91	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
97	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
98	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
99	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
102	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
104	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
105	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
106	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
107	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
113	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
114	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
115	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
118	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
121	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
122	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
130	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
131	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
136	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [78(0x4e)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed */
138	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / unconfirmed, Broadwell-E */
139	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu */
145	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
146	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
147	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
150	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
152	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
153	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
154	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
155	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
159	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
160	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
161	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
162	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
163	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
164	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
165	/[106(0x6a)] = / kCpumMicroarch_Intel_Unknown,
166	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
167	/[108(0x6c)] = / kCpumMicroarch_Intel_Unknown,
168	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
169	/[110(0x6e)] = / kCpumMicroarch_Intel_Unknown,
170	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
171	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
172	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
173	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
174	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
175	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
176	/[117(0x75)] = / kCpumMicroarch_Intel_Unknown,
177	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
178	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
179	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
180	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
181	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
182	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
183	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
184	/[125(0x7d)] = / kCpumMicroarch_Intel_Unknown,
185	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
186	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
187	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
188	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
189	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
190	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
191	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
192	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
193	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
194	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
195	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
196	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
197	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
198	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
199	/[140(0x8c)] = / kCpumMicroarch_Intel_Unknown,
200	/[141(0x8d)] = / kCpumMicroarch_Intel_Unknown,
201	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
202	/[143(0x8f)] = / kCpumMicroarch_Intel_Unknown,
203	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
204	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
205	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
206	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
207	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
208	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
209	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
210	/[151(0x97)] = / kCpumMicroarch_Intel_Unknown,
211	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
212	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
213	/[154(0x9a)] = / kCpumMicroarch_Intel_Unknown,
214	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
215	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
216	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
217	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
218	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
219	};
220	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0x9f+1);
221
222
223	/**
224	* Figures out the (sub-)micro architecture given a bit of CPUID info.
225	*
226	* @returns Micro architecture.
227	* @param enmVendor The CPU vendor .
228	* @param bFamily The CPU family.
229	* @param bModel The CPU model.
230	* @param bStepping The CPU stepping.
231	*/
232	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
233	uint8_t bModel, uint8_t bStepping)
234	{
235	if (enmVendor == CPUMCPUVENDOR_AMD)
236	{
237	switch (bFamily)
238	{
239	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
240	case 0x03: return kCpumMicroarch_AMD_Am386;
241	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
242	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
243	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
244	case 0x06:
245	switch (bModel)
246	{
247	case 0: return kCpumMicroarch_AMD_K7_Palomino;
248	case 1: return kCpumMicroarch_AMD_K7_Palomino;
249	case 2: return kCpumMicroarch_AMD_K7_Palomino;
250	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
251	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
252	case 6: return kCpumMicroarch_AMD_K7_Palomino;
253	case 7: return kCpumMicroarch_AMD_K7_Morgan;
254	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
255	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
256	}
257	return kCpumMicroarch_AMD_K7_Unknown;
258	case 0x0f:
259	/*
260	* This family is a friggin mess. Trying my best to make some
261	* sense out of it. Too much happened in the 0x0f family to
262	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
263	*
264	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
265	* cpu-world.com, and other places:
266	* - 130nm:
267	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
268	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
269	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
270	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
271	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
272	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
273	* - 90nm:
274	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
275	* - Oakville: 10FC0/DH-D0.
276	* - Georgetown: 10FC0/DH-D0.
277	* - Sonora: 10FC0/DH-D0.
278	* - Venus: 20F71/SH-E4
279	* - Troy: 20F51/SH-E4
280	* - Athens: 20F51/SH-E4
281	* - San Diego: 20F71/SH-E4.
282	* - Lancaster: 20F42/SH-E5
283	* - Newark: 20F42/SH-E5.
284	* - Albany: 20FC2/DH-E6.
285	* - Roma: 20FC2/DH-E6.
286	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
287	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
288	* - 90nm introducing Dual core:
289	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
290	* - Italy: 20F10/JH-E1, 20F12/JH-E6
291	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
292	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
293	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
294	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
295	* - Santa Ana: 40F32/JH-F2, /-F3
296	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
297	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
298	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
299	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
300	* - Keene: 40FC2/DH-F2.
301	* - Richmond: 40FC2/DH-F2
302	* - Taylor: 40F82/BH-F2
303	* - Trinidad: 40F82/BH-F2
304	*
305	* - 65nm:
306	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
307	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
308	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
309	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
310	* - Sherman: /-G1, 70FC2/DH-G2.
311	* - Huron: 70FF2/DH-G2.
312	*/
313	if (bModel < 0x10)
314	return kCpumMicroarch_AMD_K8_130nm;
315	if (bModel >= 0x60 && bModel < 0x80)
316	return kCpumMicroarch_AMD_K8_65nm;
317	if (bModel >= 0x40)
318	return kCpumMicroarch_AMD_K8_90nm_AMDV;
319	switch (bModel)
320	{
321	case 0x21:
322	case 0x23:
323	case 0x2b:
324	case 0x2f:
325	case 0x37:
326	case 0x3f:
327	return kCpumMicroarch_AMD_K8_90nm_DualCore;
328	}
329	return kCpumMicroarch_AMD_K8_90nm;
330	case 0x10:
331	return kCpumMicroarch_AMD_K10;
332	case 0x11:
333	return kCpumMicroarch_AMD_K10_Lion;
334	case 0x12:
335	return kCpumMicroarch_AMD_K10_Llano;
336	case 0x14:
337	return kCpumMicroarch_AMD_Bobcat;
338	case 0x15:
339	switch (bModel)
340	{
341	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
342	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
343	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
344	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
345	case 0x11: /* ?? */
346	case 0x12: /* ?? */
347	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
348	}
349	return kCpumMicroarch_AMD_15h_Unknown;
350	case 0x16:
351	return kCpumMicroarch_AMD_Jaguar;
352	case 0x17:
353	return kCpumMicroarch_AMD_Zen_Ryzen;
354	}
355	return kCpumMicroarch_AMD_Unknown;
356	}
357
358	if (enmVendor == CPUMCPUVENDOR_INTEL)
359	{
360	switch (bFamily)
361	{
362	case 3:
363	return kCpumMicroarch_Intel_80386;
364	case 4:
365	return kCpumMicroarch_Intel_80486;
366	case 5:
367	return kCpumMicroarch_Intel_P5;
368	case 6:
369	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
370	{
371	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
372	if ( enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake
373	&& bStepping >= 0xa)
374	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
375	return enmMicroArch;
376	}
377	return kCpumMicroarch_Intel_Atom_Unknown;
378	case 15:
379	switch (bModel)
380	{
381	case 0: return kCpumMicroarch_Intel_NB_Willamette;
382	case 1: return kCpumMicroarch_Intel_NB_Willamette;
383	case 2: return kCpumMicroarch_Intel_NB_Northwood;
384	case 3: return kCpumMicroarch_Intel_NB_Prescott;
385	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
386	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
387	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
388	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
389	default: return kCpumMicroarch_Intel_NB_Unknown;
390	}
391	break;
392	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
393	case 0:
394	return kCpumMicroarch_Intel_8086;
395	case 1:
396	return kCpumMicroarch_Intel_80186;
397	case 2:
398	return kCpumMicroarch_Intel_80286;
399	}
400	return kCpumMicroarch_Intel_Unknown;
401	}
402
403	if (enmVendor == CPUMCPUVENDOR_VIA)
404	{
405	switch (bFamily)
406	{
407	case 5:
408	switch (bModel)
409	{
410	case 1: return kCpumMicroarch_Centaur_C6;
411	case 4: return kCpumMicroarch_Centaur_C6;
412	case 8: return kCpumMicroarch_Centaur_C2;
413	case 9: return kCpumMicroarch_Centaur_C3;
414	}
415	break;
416
417	case 6:
418	switch (bModel)
419	{
420	case 5: return kCpumMicroarch_VIA_C3_M2;
421	case 6: return kCpumMicroarch_VIA_C3_C5A;
422	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
423	case 8: return kCpumMicroarch_VIA_C3_C5N;
424	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
425	case 10: return kCpumMicroarch_VIA_C7_C5J;
426	case 15: return kCpumMicroarch_VIA_Isaiah;
427	}
428	break;
429	}
430	return kCpumMicroarch_VIA_Unknown;
431	}
432
433	if (enmVendor == CPUMCPUVENDOR_CYRIX)
434	{
435	switch (bFamily)
436	{
437	case 4:
438	switch (bModel)
439	{
440	case 9: return kCpumMicroarch_Cyrix_5x86;
441	}
442	break;
443
444	case 5:
445	switch (bModel)
446	{
447	case 2: return kCpumMicroarch_Cyrix_M1;
448	case 4: return kCpumMicroarch_Cyrix_MediaGX;
449	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
450	}
451	break;
452
453	case 6:
454	switch (bModel)
455	{
456	case 0: return kCpumMicroarch_Cyrix_M2;
457	}
458	break;
459
460	}
461	return kCpumMicroarch_Cyrix_Unknown;
462	}
463
464	return kCpumMicroarch_Unknown;
465	}
466
467
468	/**
469	* Translates a microarchitecture enum value to the corresponding string
470	* constant.
471	*
472	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
473	* NULL if the value is invalid.
474	*
475	* @param enmMicroarch The enum value to convert.
476	*/
477	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
478	{
479	switch (enmMicroarch)
480	{
481	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
482	CASE_RET_STR(kCpumMicroarch_Intel_8086);
483	CASE_RET_STR(kCpumMicroarch_Intel_80186);
484	CASE_RET_STR(kCpumMicroarch_Intel_80286);
485	CASE_RET_STR(kCpumMicroarch_Intel_80386);
486	CASE_RET_STR(kCpumMicroarch_Intel_80486);
487	CASE_RET_STR(kCpumMicroarch_Intel_P5);
488
489	CASE_RET_STR(kCpumMicroarch_Intel_P6);
490	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
491	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
492
493	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
494	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
495	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
496
497	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
498	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
499
500	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
501	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
502	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
503	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
504	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
505	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
506	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
507	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
508	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
509	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
510	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
511	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
512
513	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
514	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
515	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
516	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
517	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
518	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
519	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
520	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
521
522	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
523	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
524	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
525	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
526	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
527
528	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
529	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
530	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
531	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
532	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
533	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
534	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
535
536	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
537
538	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
539	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
540	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
541	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
542	CASE_RET_STR(kCpumMicroarch_AMD_K5);
543	CASE_RET_STR(kCpumMicroarch_AMD_K6);
544
545	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
546	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
547	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
548	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
549	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
550	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
551	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
552
553	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
554	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
555	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
556	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
557	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
558
559	CASE_RET_STR(kCpumMicroarch_AMD_K10);
560	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
561	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
562	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
563	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
564
565	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
566	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
567	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
568	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
569	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
570
571	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
572
573	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
574
575	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
576
577	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
578	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
579	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
580	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
581	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
582	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
583	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
584	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
585	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
586	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
587	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
588	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
589	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
590
591	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
592	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
593	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
594	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
595	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
596	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
597
598	CASE_RET_STR(kCpumMicroarch_NEC_V20);
599	CASE_RET_STR(kCpumMicroarch_NEC_V30);
600
601	CASE_RET_STR(kCpumMicroarch_Unknown);
602
603	#undef CASE_RET_STR
604	case kCpumMicroarch_Invalid:
605	case kCpumMicroarch_Intel_End:
606	case kCpumMicroarch_Intel_Core2_End:
607	case kCpumMicroarch_Intel_Core7_End:
608	case kCpumMicroarch_Intel_Atom_End:
609	case kCpumMicroarch_Intel_P6_Core_Atom_End:
610	case kCpumMicroarch_Intel_Phi_End:
611	case kCpumMicroarch_Intel_NB_End:
612	case kCpumMicroarch_AMD_K7_End:
613	case kCpumMicroarch_AMD_K8_End:
614	case kCpumMicroarch_AMD_15h_End:
615	case kCpumMicroarch_AMD_16h_End:
616	case kCpumMicroarch_AMD_Zen_End:
617	case kCpumMicroarch_AMD_End:
618	case kCpumMicroarch_VIA_End:
619	case kCpumMicroarch_Cyrix_End:
620	case kCpumMicroarch_NEC_End:
621	case kCpumMicroarch_32BitHack:
622	break;
623	/* no default! */
624	}
625
626	return NULL;
627	}
628
629
630	/**
631	* Determins the host CPU MXCSR mask.
632	*
633	* @returns MXCSR mask.
634	*/
635	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
636	{
637	if ( ASMHasCpuId()
638	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
639	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
640	{
641	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
642	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
643	RT_ZERO(*pState);
644	ASMFxSave(pState);
645	if (pState->MXCSR_MASK == 0)
646	return 0xffbf;
647	return pState->MXCSR_MASK;
648	}
649	return 0;
650	}
651
652
653	/**
654	* Gets a matching leaf in the CPUID leaf array.
655	*
656	* @returns Pointer to the matching leaf, or NULL if not found.
657	* @param paLeaves The CPUID leaves to search. This is sorted.
658	* @param cLeaves The number of leaves in the array.
659	* @param uLeaf The leaf to locate.
660	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
661	*/
662	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
663	{
664	/* Lazy bird does linear lookup here since this is only used for the
665	occational CPUID overrides. */
666	for (uint32_t i = 0; i < cLeaves; i++)
667	if ( paLeaves[i].uLeaf == uLeaf
668	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
669	return &paLeaves[i];
670	return NULL;
671	}
672
673
674	#ifndef IN_VBOX_CPU_REPORT
675	/**
676	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
677	*
678	* @returns true if found, false it not.
679	* @param paLeaves The CPUID leaves to search. This is sorted.
680	* @param cLeaves The number of leaves in the array.
681	* @param uLeaf The leaf to locate.
682	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
683	* @param pLegacy The legacy output leaf.
684	*/
685	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
686	PCPUMCPUID pLegacy)
687	{
688	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
689	if (pLeaf)
690	{
691	pLegacy->uEax = pLeaf->uEax;
692	pLegacy->uEbx = pLeaf->uEbx;
693	pLegacy->uEcx = pLeaf->uEcx;
694	pLegacy->uEdx = pLeaf->uEdx;
695	return true;
696	}
697	return false;
698	}
699	#endif /* IN_VBOX_CPU_REPORT */
700
701
702	/**
703	* Ensures that the CPUID leaf array can hold one more leaf.
704	*
705	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
706	* failure.
707	* @param pVM The cross context VM structure. If NULL, use
708	* the process heap, otherwise the VM's hyper heap.
709	* @param ppaLeaves Pointer to the variable holding the array pointer
710	* (input/output).
711	* @param cLeaves The current array size.
712	*
713	* @remarks This function will automatically update the R0 and RC pointers when
714	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
715	* be the corresponding VM's CPUID arrays (which is asserted).
716	*/
717	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
718	{
719	/*
720	* If pVM is not specified, we're on the regular heap and can waste a
721	* little space to speed things up.
722	*/
723	uint32_t cAllocated;
724	if (!pVM)
725	{
726	cAllocated = RT_ALIGN(cLeaves, 16);
727	if (cLeaves + 1 > cAllocated)
728	{
729	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
730	if (pvNew)
731	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
732	else
733	{
734	RTMemFree(*ppaLeaves);
735	*ppaLeaves = NULL;
736	}
737	}
738	}
739	/*
740	* Otherwise, we're on the hyper heap and are probably just inserting
741	* one or two leaves and should conserve space.
742	*/
743	else
744	{
745	#ifdef IN_VBOX_CPU_REPORT
746	AssertReleaseFailed();
747	#else
748	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
749	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
750
751	size_t cb = cLeaves * sizeof(**ppaLeaves);
752	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
753	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
754	if (RT_SUCCESS(rc))
755	{
756	/* Update the R0 and RC pointers. */
757	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
758	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
759	}
760	else
761	{
762	*ppaLeaves = NULL;
763	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
764	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
765	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
766	}
767	#endif
768	}
769	return *ppaLeaves;
770	}
771
772
773	/**
774	* Append a CPUID leaf or sub-leaf.
775	*
776	* ASSUMES linear insertion order, so we'll won't need to do any searching or
777	* replace anything. Use cpumR3CpuIdInsert() for those cases.
778	*
779	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
780	* the caller need do no more work.
781	* @param ppaLeaves Pointer to the pointer to the array of sorted
782	* CPUID leaves and sub-leaves.
783	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
784	* @param uLeaf The leaf we're adding.
785	* @param uSubLeaf The sub-leaf number.
786	* @param fSubLeafMask The sub-leaf mask.
787	* @param uEax The EAX value.
788	* @param uEbx The EBX value.
789	* @param uEcx The ECX value.
790	* @param uEdx The EDX value.
791	* @param fFlags The flags.
792	*/
793	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
794	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
795	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
796	{
797	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
798	return VERR_NO_MEMORY;
799
800	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
801	Assert( *pcLeaves == 0
802	\|\| pNew[-1].uLeaf < uLeaf
803	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
804
805	pNew->uLeaf = uLeaf;
806	pNew->uSubLeaf = uSubLeaf;
807	pNew->fSubLeafMask = fSubLeafMask;
808	pNew->uEax = uEax;
809	pNew->uEbx = uEbx;
810	pNew->uEcx = uEcx;
811	pNew->uEdx = uEdx;
812	pNew->fFlags = fFlags;
813
814	*pcLeaves += 1;
815	return VINF_SUCCESS;
816	}
817
818
819	/**
820	* Checks that we've updated the CPUID leaves array correctly.
821	*
822	* This is a no-op in non-strict builds.
823	*
824	* @param paLeaves The leaves array.
825	* @param cLeaves The number of leaves.
826	*/
827	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
828	{
829	#ifdef VBOX_STRICT
830	for (uint32_t i = 1; i < cLeaves; i++)
831	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
832	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
833	else
834	{
835	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
836	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
837	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
838	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
839	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
840	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
841	}
842	#else
843	NOREF(paLeaves);
844	NOREF(cLeaves);
845	#endif
846	}
847
848
849	/**
850	* Inserts a CPU ID leaf, replacing any existing ones.
851	*
852	* When inserting a simple leaf where we already got a series of sub-leaves with
853	* the same leaf number (eax), the simple leaf will replace the whole series.
854	*
855	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
856	* host-context heap and has only been allocated/reallocated by the
857	* cpumR3CpuIdEnsureSpace function.
858	*
859	* @returns VBox status code.
860	* @param pVM The cross context VM structure. If NULL, use
861	* the process heap, otherwise the VM's hyper heap.
862	* @param ppaLeaves Pointer to the pointer to the array of sorted
863	* CPUID leaves and sub-leaves. Must be NULL if using
864	* the hyper heap.
865	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
866	* be NULL if using the hyper heap.
867	* @param pNewLeaf Pointer to the data of the new leaf we're about to
868	* insert.
869	*/
870	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
871	{
872	/*
873	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
874	*/
875	if (pVM)
876	{
877	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
878	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
879
880	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
881	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
882	}
883
884	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
885	uint32_t cLeaves = *pcLeaves;
886
887	/*
888	* Validate the new leaf a little.
889	*/
890	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
891	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
892	VERR_INVALID_FLAGS);
893	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
894	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
895	VERR_INVALID_PARAMETER);
896	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
897	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
898	VERR_INVALID_PARAMETER);
899	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
900	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
901	VERR_INVALID_PARAMETER);
902
903	/*
904	* Find insertion point. The lazy bird uses the same excuse as in
905	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
906	*/
907	uint32_t i;
908	if ( cLeaves > 0
909	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
910	{
911	/* Add at end. */
912	i = cLeaves;
913	}
914	else if ( cLeaves > 0
915	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
916	{
917	/* Either replacing the last leaf or dealing with sub-leaves. Spool
918	back to the first sub-leaf to pretend we did the linear search. */
919	i = cLeaves - 1;
920	while ( i > 0
921	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
922	i--;
923	}
924	else
925	{
926	/* Linear search from the start. */
927	i = 0;
928	while ( i < cLeaves
929	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
930	i++;
931	}
932	if ( i < cLeaves
933	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
934	{
935	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
936	{
937	/*
938	* The sub-leaf mask differs, replace all existing leaves with the
939	* same leaf number.
940	*/
941	uint32_t c = 1;
942	while ( i + c < cLeaves
943	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
944	c++;
945	if (c > 1 && i + c < cLeaves)
946	{
947	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
948	*pcLeaves = cLeaves -= c - 1;
949	}
950
951	paLeaves[i] = *pNewLeaf;
952	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
953	return VINF_SUCCESS;
954	}
955
956	/* Find sub-leaf insertion point. */
957	while ( i < cLeaves
958	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
959	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
960	i++;
961
962	/*
963	* If we've got an exactly matching leaf, replace it.
964	*/
965	if ( i < cLeaves
966	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
967	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
968	{
969	paLeaves[i] = *pNewLeaf;
970	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
971	return VINF_SUCCESS;
972	}
973	}
974
975	/*
976	* Adding a new leaf at 'i'.
977	*/
978	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
979	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
980	if (!paLeaves)
981	return VERR_NO_MEMORY;
982
983	if (i < cLeaves)
984	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
985	*pcLeaves += 1;
986	paLeaves[i] = *pNewLeaf;
987
988	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
989	return VINF_SUCCESS;
990	}
991
992
993	#ifndef IN_VBOX_CPU_REPORT
994	/**
995	* Removes a range of CPUID leaves.
996	*
997	* This will not reallocate the array.
998	*
999	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1000	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1001	* @param uFirst The first leaf.
1002	* @param uLast The last leaf.
1003	*/
1004	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1005	{
1006	uint32_t cLeaves = *pcLeaves;
1007
1008	Assert(uFirst <= uLast);
1009
1010	/*
1011	* Find the first one.
1012	*/
1013	uint32_t iFirst = 0;
1014	while ( iFirst < cLeaves
1015	&& paLeaves[iFirst].uLeaf < uFirst)
1016	iFirst++;
1017
1018	/*
1019	* Find the end (last + 1).
1020	*/
1021	uint32_t iEnd = iFirst;
1022	while ( iEnd < cLeaves
1023	&& paLeaves[iEnd].uLeaf <= uLast)
1024	iEnd++;
1025
1026	/*
1027	* Adjust the array if anything needs removing.
1028	*/
1029	if (iFirst < iEnd)
1030	{
1031	if (iEnd < cLeaves)
1032	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1033	*pcLeaves = cLeaves -= (iEnd - iFirst);
1034	}
1035
1036	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1037	}
1038	#endif /* IN_VBOX_CPU_REPORT */
1039
1040
1041	/**
1042	* Checks if ECX make a difference when reading a given CPUID leaf.
1043	*
1044	* @returns @c true if it does, @c false if it doesn't.
1045	* @param uLeaf The leaf we're reading.
1046	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1047	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1048	* final sub-leaf (for leaf 0xb only).
1049	*/
1050	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1051	{
1052	*pfFinalEcxUnchanged = false;
1053
1054	uint32_t auCur[4];
1055	uint32_t auPrev[4];
1056	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1057
1058	/* Look for sub-leaves. */
1059	uint32_t uSubLeaf = 1;
1060	for (;;)
1061	{
1062	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1063	if (memcmp(auCur, auPrev, sizeof(auCur)))
1064	break;
1065
1066	/* Advance / give up. */
1067	uSubLeaf++;
1068	if (uSubLeaf >= 64)
1069	{
1070	*pcSubLeaves = 1;
1071	return false;
1072	}
1073	}
1074
1075	/* Count sub-leaves. */
1076	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1077	uint32_t cRepeats = 0;
1078	uSubLeaf = 0;
1079	for (;;)
1080	{
1081	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1082
1083	/* Figuring out when to stop isn't entirely straight forward as we need
1084	to cover undocumented behavior up to a point and implementation shortcuts. */
1085
1086	/* 1. Look for more than 4 repeating value sets. */
1087	if ( auCur[0] == auPrev[0]
1088	&& auCur[1] == auPrev[1]
1089	&& ( auCur[2] == auPrev[2]
1090	\|\| ( auCur[2] == uSubLeaf
1091	&& auPrev[2] == uSubLeaf - 1) )
1092	&& auCur[3] == auPrev[3])
1093	{
1094	if ( uLeaf != 0xd
1095	\|\| uSubLeaf >= 64
1096	\|\| ( auCur[0] == 0
1097	&& auCur[1] == 0
1098	&& auCur[2] == 0
1099	&& auCur[3] == 0
1100	&& auPrev[2] == 0) )
1101	cRepeats++;
1102	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1103	break;
1104	}
1105	else
1106	cRepeats = 0;
1107
1108	/* 2. Look for zero values. */
1109	if ( auCur[0] == 0
1110	&& auCur[1] == 0
1111	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1112	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1113	&& uSubLeaf >= cMinLeaves)
1114	{
1115	cRepeats = 0;
1116	break;
1117	}
1118
1119	/* 3. Leaf 0xb level type 0 check. */
1120	if ( uLeaf == 0xb
1121	&& (auCur[2] & 0xff00) == 0
1122	&& (auPrev[2] & 0xff00) == 0)
1123	{
1124	cRepeats = 0;
1125	break;
1126	}
1127
1128	/* 99. Give up. */
1129	if (uSubLeaf >= 128)
1130	{
1131	#ifndef IN_VBOX_CPU_REPORT
1132	/* Ok, limit it according to the documentation if possible just to
1133	avoid annoying users with these detection issues. */
1134	uint32_t cDocLimit = UINT32_MAX;
1135	if (uLeaf == 0x4)
1136	cDocLimit = 4;
1137	else if (uLeaf == 0x7)
1138	cDocLimit = 1;
1139	else if (uLeaf == 0xd)
1140	cDocLimit = 63;
1141	else if (uLeaf == 0xf)
1142	cDocLimit = 2;
1143	if (cDocLimit != UINT32_MAX)
1144	{
1145	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1146	*pcSubLeaves = cDocLimit + 3;
1147	return true;
1148	}
1149	#endif
1150	*pcSubLeaves = UINT32_MAX;
1151	return true;
1152	}
1153
1154	/* Advance. */
1155	uSubLeaf++;
1156	memcpy(auPrev, auCur, sizeof(auCur));
1157	}
1158
1159	/* Standard exit. */
1160	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1161	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1162	if (*pcSubLeaves == 0)
1163	*pcSubLeaves = 1;
1164	return true;
1165	}
1166
1167
1168	/**
1169	* Gets a CPU ID leaf.
1170	*
1171	* @returns VBox status code.
1172	* @param pVM The cross context VM structure.
1173	* @param pLeaf Where to store the found leaf.
1174	* @param uLeaf The leaf to locate.
1175	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1176	*/
1177	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1178	{
1179	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1180	uLeaf, uSubLeaf);
1181	if (pcLeaf)
1182	{
1183	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1184	return VINF_SUCCESS;
1185	}
1186
1187	return VERR_NOT_FOUND;
1188	}
1189
1190
1191	/**
1192	* Inserts a CPU ID leaf, replacing any existing ones.
1193	*
1194	* @returns VBox status code.
1195	* @param pVM The cross context VM structure.
1196	* @param pNewLeaf Pointer to the leaf being inserted.
1197	*/
1198	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1199	{
1200	/*
1201	* Validate parameters.
1202	*/
1203	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1204	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1205
1206	/*
1207	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1208	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1209	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1210	*/
1211	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1212	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1213	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1214	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1215	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1216	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1217	{
1218	return VERR_NOT_SUPPORTED;
1219	}
1220
1221	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1222	}
1223
1224	/**
1225	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1226	*
1227	* @returns VBox status code.
1228	* @param ppaLeaves Where to return the array pointer on success.
1229	* Use RTMemFree to release.
1230	* @param pcLeaves Where to return the size of the array on
1231	* success.
1232	*/
1233	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1234	{
1235	*ppaLeaves = NULL;
1236	*pcLeaves = 0;
1237
1238	/*
1239	* Try out various candidates. This must be sorted!
1240	*/
1241	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1242	{
1243	{ UINT32_C(0x00000000), false },
1244	{ UINT32_C(0x10000000), false },
1245	{ UINT32_C(0x20000000), false },
1246	{ UINT32_C(0x30000000), false },
1247	{ UINT32_C(0x40000000), false },
1248	{ UINT32_C(0x50000000), false },
1249	{ UINT32_C(0x60000000), false },
1250	{ UINT32_C(0x70000000), false },
1251	{ UINT32_C(0x80000000), false },
1252	{ UINT32_C(0x80860000), false },
1253	{ UINT32_C(0x8ffffffe), true },
1254	{ UINT32_C(0x8fffffff), true },
1255	{ UINT32_C(0x90000000), false },
1256	{ UINT32_C(0xa0000000), false },
1257	{ UINT32_C(0xb0000000), false },
1258	{ UINT32_C(0xc0000000), false },
1259	{ UINT32_C(0xd0000000), false },
1260	{ UINT32_C(0xe0000000), false },
1261	{ UINT32_C(0xf0000000), false },
1262	};
1263
1264	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1265	{
1266	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1267	uint32_t uEax, uEbx, uEcx, uEdx;
1268	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1269
1270	/*
1271	* Does EAX look like a typical leaf count value?
1272	*/
1273	if ( uEax > uLeaf
1274	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1275	{
1276	/* Yes, dump them. */
1277	uint32_t cLeaves = uEax - uLeaf + 1;
1278	while (cLeaves-- > 0)
1279	{
1280	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1281
1282	uint32_t fFlags = 0;
1283
1284	/* There are currently three known leaves containing an APIC ID
1285	that needs EMT specific attention */
1286	if (uLeaf == 1)
1287	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1288	else if (uLeaf == 0xb && uEcx != 0)
1289	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1290	else if ( uLeaf == UINT32_C(0x8000001e)
1291	&& ( uEax
1292	\|\| uEbx
1293	\|\| uEdx
1294	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1295	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1296
1297	/* The APIC bit is per-VCpu and needs flagging. */
1298	if (uLeaf == 1)
1299	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1300	else if ( uLeaf == UINT32_C(0x80000001)
1301	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1302	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1303	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1304
1305	/* Check three times here to reduce the chance of CPU migration
1306	resulting in false positives with things like the APIC ID. */
1307	uint32_t cSubLeaves;
1308	bool fFinalEcxUnchanged;
1309	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1310	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1311	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1312	{
1313	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1314	{
1315	/* This shouldn't happen. But in case it does, file all
1316	relevant details in the release log. */
1317	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1318	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1319	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1320	{
1321	uint32_t auTmp[4];
1322	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1323	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1324	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1325	}
1326	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1327	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1328	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1329	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1330	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1331	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1332	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1333	}
1334
1335	if (fFinalEcxUnchanged)
1336	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1337
1338	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1339	{
1340	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1341	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1342	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1343	if (RT_FAILURE(rc))
1344	return rc;
1345	}
1346	}
1347	else
1348	{
1349	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1350	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1351	if (RT_FAILURE(rc))
1352	return rc;
1353	}
1354
1355	/* next */
1356	uLeaf++;
1357	}
1358	}
1359	/*
1360	* Special CPUIDs needs special handling as they don't follow the
1361	* leaf count principle used above.
1362	*/
1363	else if (s_aCandidates[iOuter].fSpecial)
1364	{
1365	bool fKeep = false;
1366	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1367	fKeep = true;
1368	else if ( uLeaf == 0x8fffffff
1369	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1370	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1371	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1372	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1373	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1374	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1375	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1376	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1377	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1378	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1379	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1380	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1381	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1382	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1383	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1384	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1385	fKeep = true;
1386	if (fKeep)
1387	{
1388	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1389	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1390	if (RT_FAILURE(rc))
1391	return rc;
1392	}
1393	}
1394	}
1395
1396	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1397	return VINF_SUCCESS;
1398	}
1399
1400
1401	/**
1402	* Determines the method the CPU uses to handle unknown CPUID leaves.
1403	*
1404	* @returns VBox status code.
1405	* @param penmUnknownMethod Where to return the method.
1406	* @param pDefUnknown Where to return default unknown values. This
1407	* will be set, even if the resulting method
1408	* doesn't actually needs it.
1409	*/
1410	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1411	{
1412	uint32_t uLastStd = ASMCpuId_EAX(0);
1413	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1414	if (!ASMIsValidExtRange(uLastExt))
1415	uLastExt = 0x80000000;
1416
1417	uint32_t auChecks[] =
1418	{
1419	uLastStd + 1,
1420	uLastStd + 5,
1421	uLastStd + 8,
1422	uLastStd + 32,
1423	uLastStd + 251,
1424	uLastExt + 1,
1425	uLastExt + 8,
1426	uLastExt + 15,
1427	uLastExt + 63,
1428	uLastExt + 255,
1429	0x7fbbffcc,
1430	0x833f7872,
1431	0xefff2353,
1432	0x35779456,
1433	0x1ef6d33e,
1434	};
1435
1436	static const uint32_t s_auValues[] =
1437	{
1438	0xa95d2156,
1439	0x00000001,
1440	0x00000002,
1441	0x00000008,
1442	0x00000000,
1443	0x55773399,
1444	0x93401769,
1445	0x12039587,
1446	};
1447
1448	/*
1449	* Simple method, all zeros.
1450	*/
1451	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1452	pDefUnknown->uEax = 0;
1453	pDefUnknown->uEbx = 0;
1454	pDefUnknown->uEcx = 0;
1455	pDefUnknown->uEdx = 0;
1456
1457	/*
1458	* Intel has been observed returning the last standard leaf.
1459	*/
1460	uint32_t auLast[4];
1461	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1462
1463	uint32_t cChecks = RT_ELEMENTS(auChecks);
1464	while (cChecks > 0)
1465	{
1466	uint32_t auCur[4];
1467	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1468	if (memcmp(auCur, auLast, sizeof(auCur)))
1469	break;
1470	cChecks--;
1471	}
1472	if (cChecks == 0)
1473	{
1474	/* Now, what happens when the input changes? Esp. ECX. */
1475	uint32_t cTotal = 0;
1476	uint32_t cSame = 0;
1477	uint32_t cLastWithEcx = 0;
1478	uint32_t cNeither = 0;
1479	uint32_t cValues = RT_ELEMENTS(s_auValues);
1480	while (cValues > 0)
1481	{
1482	uint32_t uValue = s_auValues[cValues - 1];
1483	uint32_t auLastWithEcx[4];
1484	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1485	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1486
1487	cChecks = RT_ELEMENTS(auChecks);
1488	while (cChecks > 0)
1489	{
1490	uint32_t auCur[4];
1491	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1492	if (!memcmp(auCur, auLast, sizeof(auCur)))
1493	{
1494	cSame++;
1495	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1496	cLastWithEcx++;
1497	}
1498	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1499	cLastWithEcx++;
1500	else
1501	cNeither++;
1502	cTotal++;
1503	cChecks--;
1504	}
1505	cValues--;
1506	}
1507
1508	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1509	if (cSame == cTotal)
1510	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1511	else if (cLastWithEcx == cTotal)
1512	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1513	else
1514	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1515	pDefUnknown->uEax = auLast[0];
1516	pDefUnknown->uEbx = auLast[1];
1517	pDefUnknown->uEcx = auLast[2];
1518	pDefUnknown->uEdx = auLast[3];
1519	return VINF_SUCCESS;
1520	}
1521
1522	/*
1523	* Unchanged register values?
1524	*/
1525	cChecks = RT_ELEMENTS(auChecks);
1526	while (cChecks > 0)
1527	{
1528	uint32_t const uLeaf = auChecks[cChecks - 1];
1529	uint32_t cValues = RT_ELEMENTS(s_auValues);
1530	while (cValues > 0)
1531	{
1532	uint32_t uValue = s_auValues[cValues - 1];
1533	uint32_t auCur[4];
1534	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1535	if ( auCur[0] != uLeaf
1536	\|\| auCur[1] != uValue
1537	\|\| auCur[2] != uValue
1538	\|\| auCur[3] != uValue)
1539	break;
1540	cValues--;
1541	}
1542	if (cValues != 0)
1543	break;
1544	cChecks--;
1545	}
1546	if (cChecks == 0)
1547	{
1548	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1549	return VINF_SUCCESS;
1550	}
1551
1552	/*
1553	* Just go with the simple method.
1554	*/
1555	return VINF_SUCCESS;
1556	}
1557
1558
1559	/**
1560	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1561	*
1562	* @returns Read only name string.
1563	* @param enmUnknownMethod The method to translate.
1564	*/
1565	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1566	{
1567	switch (enmUnknownMethod)
1568	{
1569	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1570	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1571	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1572	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1573
1574	case CPUMUNKNOWNCPUID_INVALID:
1575	case CPUMUNKNOWNCPUID_END:
1576	case CPUMUNKNOWNCPUID_32BIT_HACK:
1577	break;
1578	}
1579	return "Invalid-unknown-CPUID-method";
1580	}
1581
1582
1583	/**
1584	* Detect the CPU vendor give n the
1585	*
1586	* @returns The vendor.
1587	* @param uEAX EAX from CPUID(0).
1588	* @param uEBX EBX from CPUID(0).
1589	* @param uECX ECX from CPUID(0).
1590	* @param uEDX EDX from CPUID(0).
1591	*/
1592	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1593	{
1594	if (ASMIsValidStdRange(uEAX))
1595	{
1596	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1597	return CPUMCPUVENDOR_AMD;
1598
1599	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1600	return CPUMCPUVENDOR_INTEL;
1601
1602	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1603	return CPUMCPUVENDOR_VIA;
1604
1605	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1606	&& uECX == UINT32_C(0x64616574)
1607	&& uEDX == UINT32_C(0x736E4978))
1608	return CPUMCPUVENDOR_CYRIX;
1609
1610	/* "Geode by NSC", example: family 5, model 9. */
1611
1612	/** @todo detect the other buggers... */
1613	}
1614
1615	return CPUMCPUVENDOR_UNKNOWN;
1616	}
1617
1618
1619	/**
1620	* Translates a CPU vendor enum value into the corresponding string constant.
1621	*
1622	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1623	* value name. This can be useful when generating code.
1624	*
1625	* @returns Read only name string.
1626	* @param enmVendor The CPU vendor value.
1627	*/
1628	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1629	{
1630	switch (enmVendor)
1631	{
1632	case CPUMCPUVENDOR_INTEL: return "INTEL";
1633	case CPUMCPUVENDOR_AMD: return "AMD";
1634	case CPUMCPUVENDOR_VIA: return "VIA";
1635	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1636	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1637
1638	case CPUMCPUVENDOR_INVALID:
1639	case CPUMCPUVENDOR_32BIT_HACK:
1640	break;
1641	}
1642	return "Invalid-cpu-vendor";
1643	}
1644
1645
1646	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1647	{
1648	/* Could do binary search, doing linear now because I'm lazy. */
1649	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1650	while (cLeaves-- > 0)
1651	{
1652	if (pLeaf->uLeaf == uLeaf)
1653	return pLeaf;
1654	pLeaf++;
1655	}
1656	return NULL;
1657	}
1658
1659
1660	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1661	{
1662	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1663	if ( !pLeaf
1664	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1665	return pLeaf;
1666
1667	/* Linear sub-leaf search. Lazy as usual. */
1668	cLeaves -= pLeaf - paLeaves;
1669	while ( cLeaves-- > 0
1670	&& pLeaf->uLeaf == uLeaf)
1671	{
1672	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1673	return pLeaf;
1674	pLeaf++;
1675	}
1676
1677	return NULL;
1678	}
1679
1680
1681	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1682	{
1683	RT_ZERO(*pFeatures);
1684	if (cLeaves >= 2)
1685	{
1686	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1687	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1688	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1689	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1690	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1691	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1692
1693	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1694	pStd0Leaf->uEbx,
1695	pStd0Leaf->uEcx,
1696	pStd0Leaf->uEdx);
1697	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1698	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1699	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1700	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1701	pFeatures->uFamily,
1702	pFeatures->uModel,
1703	pFeatures->uStepping);
1704
1705	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1706	if (pExtLeaf8)
1707	{
1708	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1709	pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1710	}
1711	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1712	{
1713	pFeatures->cMaxPhysAddrWidth = 36;
1714	pFeatures->cMaxLinearAddrWidth = 36;
1715	}
1716	else
1717	{
1718	pFeatures->cMaxPhysAddrWidth = 32;
1719	pFeatures->cMaxLinearAddrWidth = 32;
1720	}
1721
1722	/* Standard features. */
1723	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1724	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1725	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1726	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1727	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1728	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1729	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1730	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1731	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1732	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1733	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1734	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1735	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1736	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1737	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1738	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1739	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1740	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1741	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1742	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1743	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1744	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1745	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1746	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1747	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1748	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1749	/* VMX sub-features will be initialized in cpumR3InitVmxCpuFeatures(). */
1750
1751	/* Structured extended features. */
1752	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1753	if (pSxfLeaf0)
1754	{
1755	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1756	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1757	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1758	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1759	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1760
1761	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1762	pFeatures->fIbrs = pFeatures->fIbpb;
1763	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1764	#if 0 // Disabled until IA32_ARCH_CAPABILITIES support can be tested
1765	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1766	#endif
1767	}
1768
1769	/* MWAIT/MONITOR leaf. */
1770	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1771	if (pMWaitLeaf)
1772	{
1773	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1774	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1775	}
1776
1777	/* Extended features. */
1778	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1779	if (pExtLeaf)
1780	{
1781	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1782	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1783	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1784	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1785	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1786	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1787	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1788	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1789	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1790	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1791	}
1792
1793	/* VMX (VMXON, VMCS region and related data structures') physical address width (depends on long-mode). */
1794	pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
1795
1796	if ( pExtLeaf
1797	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1798	{
1799	/* AMD features. */
1800	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1801	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1802	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1803	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1804	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1805	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1806	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1807	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1808	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1809	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1810	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1811	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1812	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1813	if (pFeatures->fSvm)
1814	{
1815	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1816	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1817	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1818	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1819	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1820	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1821	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1822	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1823	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1824	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1825	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1826	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1827	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1828	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1829	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1830	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1831	}
1832	}
1833
1834	/*
1835	* Quirks.
1836	*/
1837	pFeatures->fLeakyFxSR = pExtLeaf
1838	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1839	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1840	&& pFeatures->uFamily >= 6 /* K7 and up */;
1841
1842	/*
1843	* Max extended (/FPU) state.
1844	*/
1845	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1846	if (pFeatures->fXSaveRstor)
1847	{
1848	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1849	if (pXStateLeaf0)
1850	{
1851	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1852	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1853	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1854	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1855	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1856	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1857	{
1858	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1859
1860	/* (paranoia:) */
1861	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1862	if ( pXStateLeaf1
1863	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1864	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1865	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1866	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1867	}
1868	else
1869	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1870	pFeatures->fXSaveRstor = 0);
1871	}
1872	else
1873	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1874	pFeatures->fXSaveRstor = 0);
1875	}
1876	}
1877	else
1878	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1879	return VINF_SUCCESS;
1880	}
1881
1882
1883	/*
1884	*
1885	* Init related code.
1886	* Init related code.
1887	* Init related code.
1888	*
1889	*
1890	*/
1891	#ifdef VBOX_IN_VMM
1892
1893
1894	/**
1895	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1896	*
1897	* This ignores the fSubLeafMask.
1898	*
1899	* @returns Pointer to the matching leaf, or NULL if not found.
1900	* @param paLeaves The CPUID leaves to search. This is sorted.
1901	* @param cLeaves The number of leaves in the array.
1902	* @param uLeaf The leaf to locate.
1903	* @param uSubLeaf The subleaf to locate.
1904	*/
1905	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1906	{
1907	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1908	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1909	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1910	if (iEnd)
1911	{
1912	uint32_t iBegin = 0;
1913	for (;;)
1914	{
1915	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1916	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1917	if (uNeedle < uCur)
1918	{
1919	if (i > iBegin)
1920	iEnd = i;
1921	else
1922	break;
1923	}
1924	else if (uNeedle > uCur)
1925	{
1926	if (i + 1 < iEnd)
1927	iBegin = i + 1;
1928	else
1929	break;
1930	}
1931	else
1932	return &paLeaves[i];
1933	}
1934	}
1935	return NULL;
1936	}
1937
1938
1939	/**
1940	* Loads MSR range overrides.
1941	*
1942	* This must be called before the MSR ranges are moved from the normal heap to
1943	* the hyper heap!
1944	*
1945	* @returns VBox status code (VMSetError called).
1946	* @param pVM The cross context VM structure.
1947	* @param pMsrNode The CFGM node with the MSR overrides.
1948	*/
1949	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1950	{
1951	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1952	{
1953	/*
1954	* Assemble a valid MSR range.
1955	*/
1956	CPUMMSRRANGE MsrRange;
1957	MsrRange.offCpumCpu = 0;
1958	MsrRange.fReserved = 0;
1959
1960	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1961	if (RT_FAILURE(rc))
1962	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1963
1964	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1965	if (RT_FAILURE(rc))
1966	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1967	MsrRange.szName, rc);
1968
1969	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1970	if (RT_FAILURE(rc))
1971	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1972	MsrRange.szName, rc);
1973
1974	char szType[32];
1975	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1976	if (RT_FAILURE(rc))
1977	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1978	MsrRange.szName, rc);
1979	if (!RTStrICmp(szType, "FixedValue"))
1980	{
1981	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1982	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1983
1984	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1985	if (RT_FAILURE(rc))
1986	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1987	MsrRange.szName, rc);
1988
1989	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1990	if (RT_FAILURE(rc))
1991	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1992	MsrRange.szName, rc);
1993
1994	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1995	if (RT_FAILURE(rc))
1996	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1997	MsrRange.szName, rc);
1998	}
1999	else
2000	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
2001	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
2002
2003	/*
2004	* Insert the range into the table (replaces/splits/shrinks existing
2005	* MSR ranges).
2006	*/
2007	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
2008	&MsrRange);
2009	if (RT_FAILURE(rc))
2010	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
2011	}
2012
2013	return VINF_SUCCESS;
2014	}
2015
2016
2017	/**
2018	* Loads CPUID leaf overrides.
2019	*
2020	* This must be called before the CPUID leaves are moved from the normal
2021	* heap to the hyper heap!
2022	*
2023	* @returns VBox status code (VMSetError called).
2024	* @param pVM The cross context VM structure.
2025	* @param pParentNode The CFGM node with the CPUID leaves.
2026	* @param pszLabel How to label the overrides we're loading.
2027	*/
2028	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2029	{
2030	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2031	{
2032	/*
2033	* Get the leaf and subleaf numbers.
2034	*/
2035	char szName[128];
2036	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2037	if (RT_FAILURE(rc))
2038	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2039
2040	/* The leaf number is either specified directly or thru the node name. */
2041	uint32_t uLeaf;
2042	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2043	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2044	{
2045	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2046	if (rc != VINF_SUCCESS)
2047	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2048	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2049	}
2050	else if (RT_FAILURE(rc))
2051	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2052	pszLabel, szName, rc);
2053
2054	uint32_t uSubLeaf;
2055	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2056	if (RT_FAILURE(rc))
2057	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2058	pszLabel, szName, rc);
2059
2060	uint32_t fSubLeafMask;
2061	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2062	if (RT_FAILURE(rc))
2063	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2064	pszLabel, szName, rc);
2065
2066	/*
2067	* Look up the specified leaf, since the output register values
2068	* defaults to any existing values. This allows overriding a single
2069	* register, without needing to know the other values.
2070	*/
2071	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2072	CPUMCPUIDLEAF Leaf;
2073	if (pLeaf)
2074	Leaf = *pLeaf;
2075	else
2076	RT_ZERO(Leaf);
2077	Leaf.uLeaf = uLeaf;
2078	Leaf.uSubLeaf = uSubLeaf;
2079	Leaf.fSubLeafMask = fSubLeafMask;
2080
2081	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2082	if (RT_FAILURE(rc))
2083	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2084	pszLabel, szName, rc);
2085	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2086	if (RT_FAILURE(rc))
2087	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2088	pszLabel, szName, rc);
2089	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2090	if (RT_FAILURE(rc))
2091	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2092	pszLabel, szName, rc);
2093	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2094	if (RT_FAILURE(rc))
2095	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2096	pszLabel, szName, rc);
2097
2098	/*
2099	* Insert the leaf into the table (replaces existing ones).
2100	*/
2101	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2102	&Leaf);
2103	if (RT_FAILURE(rc))
2104	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2105	}
2106
2107	return VINF_SUCCESS;
2108	}
2109
2110
2111
2112	/**
2113	* Fetches overrides for a CPUID leaf.
2114	*
2115	* @returns VBox status code.
2116	* @param pLeaf The leaf to load the overrides into.
2117	* @param pCfgNode The CFGM node containing the overrides
2118	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2119	* @param iLeaf The CPUID leaf number.
2120	*/
2121	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2122	{
2123	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2124	if (pLeafNode)
2125	{
2126	uint32_t u32;
2127	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2128	if (RT_SUCCESS(rc))
2129	pLeaf->uEax = u32;
2130	else
2131	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2132
2133	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2134	if (RT_SUCCESS(rc))
2135	pLeaf->uEbx = u32;
2136	else
2137	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2138
2139	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2140	if (RT_SUCCESS(rc))
2141	pLeaf->uEcx = u32;
2142	else
2143	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2144
2145	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2146	if (RT_SUCCESS(rc))
2147	pLeaf->uEdx = u32;
2148	else
2149	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2150
2151	}
2152	return VINF_SUCCESS;
2153	}
2154
2155
2156	/**
2157	* Load the overrides for a set of CPUID leaves.
2158	*
2159	* @returns VBox status code.
2160	* @param paLeaves The leaf array.
2161	* @param cLeaves The number of leaves.
2162	* @param uStart The start leaf number.
2163	* @param pCfgNode The CFGM node containing the overrides
2164	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2165	*/
2166	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2167	{
2168	for (uint32_t i = 0; i < cLeaves; i++)
2169	{
2170	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2171	if (RT_FAILURE(rc))
2172	return rc;
2173	}
2174
2175	return VINF_SUCCESS;
2176	}
2177
2178
2179	/**
2180	* Installs the CPUID leaves and explods the data into structures like
2181	* GuestFeatures and CPUMCTX::aoffXState.
2182	*
2183	* @returns VBox status code.
2184	* @param pVM The cross context VM structure.
2185	* @param pCpum The CPUM part of @a VM.
2186	* @param paLeaves The leaves. These will be copied (but not freed).
2187	* @param cLeaves The number of leaves.
2188	*/
2189	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
2190	{
2191	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2192
2193	/*
2194	* Install the CPUID information.
2195	*/
2196	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2197	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2198
2199	AssertLogRelRCReturn(rc, rc);
2200	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2201	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2202	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2203	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2204	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2205
2206	/*
2207	* Update the default CPUID leaf if necessary.
2208	*/
2209	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2210	{
2211	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2212	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2213	{
2214	/* We don't use CPUID(0).eax here because of the NT hack that only
2215	changes that value without actually removing any leaves. */
2216	uint32_t i = 0;
2217	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2218	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2219	{
2220	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2221	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2222	i++;
2223	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2224	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2225	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2226	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2227	}
2228	break;
2229	}
2230	default:
2231	break;
2232	}
2233
2234	/*
2235	* Explode the guest CPU features.
2236	*/
2237	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
2238	AssertLogRelRCReturn(rc, rc);
2239
2240	/*
2241	* Adjust the scalable bus frequency according to the CPUID information
2242	* we're now using.
2243	*/
2244	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2245	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2246	? UINT64_C(100000000) /* 100MHz */
2247	: UINT64_C(133333333); /* 133MHz */
2248
2249	/*
2250	* Populate the legacy arrays. Currently used for everything, later only
2251	* for patch manager.
2252	*/
2253	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2254	{
2255	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2256	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2257	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2258	};
2259	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2260	{
2261	uint32_t cLeft = aOldRanges[i].cCpuIds;
2262	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2263	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2264	while (cLeft-- > 0)
2265	{
2266	uLeaf--;
2267	pLegacyLeaf--;
2268
2269	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2270	if (pLeaf)
2271	{
2272	pLegacyLeaf->uEax = pLeaf->uEax;
2273	pLegacyLeaf->uEbx = pLeaf->uEbx;
2274	pLegacyLeaf->uEcx = pLeaf->uEcx;
2275	pLegacyLeaf->uEdx = pLeaf->uEdx;
2276	}
2277	else
2278	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2279	}
2280	}
2281
2282	/*
2283	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2284	*/
2285	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2286	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2287	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2288	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2289	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2290	{
2291	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2292	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2293	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2294	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2295	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2296	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2297	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2298	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2299	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2300	pCpum->GuestFeatures.cbMaxExtendedState),
2301	VERR_CPUM_IPE_1);
2302	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2303	}
2304	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2305
2306	/* Copy the CPU #0 data to the other CPUs. */
2307	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2308	{
2309	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2310	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2311	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2312	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2313	}
2314
2315	return VINF_SUCCESS;
2316	}
2317
2318
2319	/** @name Instruction Set Extension Options
2320	* @{ */
2321	/** Configuration option type (extended boolean, really). */
2322	typedef uint8_t CPUMISAEXTCFG;
2323	/** Always disable the extension. */
2324	#define CPUMISAEXTCFG_DISABLED false
2325	/** Enable the extension if it's supported by the host CPU. */
2326	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2327	/** Enable the extension if it's supported by the host CPU, but don't let
2328	* the portable CPUID feature disable it. */
2329	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2330	/** Always enable the extension. */
2331	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2332	/** @} */
2333
2334	/**
2335	* CPUID Configuration (from CFGM).
2336	*
2337	* @remarks The members aren't document since we would only be duplicating the
2338	* \@cfgm entries in cpumR3CpuIdReadConfig.
2339	*/
2340	typedef struct CPUMCPUIDCONFIG
2341	{
2342	bool fNt4LeafLimit;
2343	bool fInvariantTsc;
2344	bool fForceVme;
2345	bool fNestedHWVirt;
2346
2347	CPUMISAEXTCFG enmCmpXchg16b;
2348	CPUMISAEXTCFG enmMonitor;
2349	CPUMISAEXTCFG enmMWaitExtensions;
2350	CPUMISAEXTCFG enmSse41;
2351	CPUMISAEXTCFG enmSse42;
2352	CPUMISAEXTCFG enmAvx;
2353	CPUMISAEXTCFG enmAvx2;
2354	CPUMISAEXTCFG enmXSave;
2355	CPUMISAEXTCFG enmAesNi;
2356	CPUMISAEXTCFG enmPClMul;
2357	CPUMISAEXTCFG enmPopCnt;
2358	CPUMISAEXTCFG enmMovBe;
2359	CPUMISAEXTCFG enmRdRand;
2360	CPUMISAEXTCFG enmRdSeed;
2361	CPUMISAEXTCFG enmCLFlushOpt;
2362	CPUMISAEXTCFG enmFsGsBase;
2363	CPUMISAEXTCFG enmPcid;
2364	CPUMISAEXTCFG enmInvpcid;
2365
2366	CPUMISAEXTCFG enmAbm;
2367	CPUMISAEXTCFG enmSse4A;
2368	CPUMISAEXTCFG enmMisAlnSse;
2369	CPUMISAEXTCFG enm3dNowPrf;
2370	CPUMISAEXTCFG enmAmdExtMmx;
2371
2372	uint32_t uMaxStdLeaf;
2373	uint32_t uMaxExtLeaf;
2374	uint32_t uMaxCentaurLeaf;
2375	uint32_t uMaxIntelFamilyModelStep;
2376	char szCpuName[128];
2377	} CPUMCPUIDCONFIG;
2378	/** Pointer to CPUID config (from CFGM). */
2379	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2380
2381
2382	/**
2383	* Mini CPU selection support for making Mac OS X happy.
2384	*
2385	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2386	*
2387	* @param pCpum The CPUM instance data.
2388	* @param pConfig The CPUID configuration we've read from CFGM.
2389	*/
2390	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2391	{
2392	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2393	{
2394	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2395	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2396	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2397	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2398	0);
2399	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2400	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2401	{
2402	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2403	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2404	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2405	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2406	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2407	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2408	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2409	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2410	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2411	pStdFeatureLeaf->uEax = uNew;
2412	}
2413	}
2414	}
2415
2416
2417
2418	/**
2419	* Limit it the number of entries, zapping the remainder.
2420	*
2421	* The limits are masking off stuff about power saving and similar, this
2422	* is perhaps a bit crudely done as there is probably some relatively harmless
2423	* info too in these leaves (like words about having a constant TSC).
2424	*
2425	* @param pCpum The CPUM instance data.
2426	* @param pConfig The CPUID configuration we've read from CFGM.
2427	*/
2428	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2429	{
2430	/*
2431	* Standard leaves.
2432	*/
2433	uint32_t uSubLeaf = 0;
2434	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2435	if (pCurLeaf)
2436	{
2437	uint32_t uLimit = pCurLeaf->uEax;
2438	if (uLimit <= UINT32_C(0x000fffff))
2439	{
2440	if (uLimit > pConfig->uMaxStdLeaf)
2441	{
2442	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2443	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2444	uLimit + 1, UINT32_C(0x000fffff));
2445	}
2446
2447	/* NT4 hack, no zapping of extra leaves here. */
2448	if (pConfig->fNt4LeafLimit && uLimit > 3)
2449	pCurLeaf->uEax = uLimit = 3;
2450
2451	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2452	pCurLeaf->uEax = uLimit;
2453	}
2454	else
2455	{
2456	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2457	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2458	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2459	}
2460	}
2461
2462	/*
2463	* Extended leaves.
2464	*/
2465	uSubLeaf = 0;
2466	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2467	if (pCurLeaf)
2468	{
2469	uint32_t uLimit = pCurLeaf->uEax;
2470	if ( uLimit >= UINT32_C(0x80000000)
2471	&& uLimit <= UINT32_C(0x800fffff))
2472	{
2473	if (uLimit > pConfig->uMaxExtLeaf)
2474	{
2475	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2476	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2477	uLimit + 1, UINT32_C(0x800fffff));
2478	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2479	pCurLeaf->uEax = uLimit;
2480	}
2481	}
2482	else
2483	{
2484	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2485	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2486	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2487	}
2488	}
2489
2490	/*
2491	* Centaur leaves (VIA).
2492	*/
2493	uSubLeaf = 0;
2494	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2495	if (pCurLeaf)
2496	{
2497	uint32_t uLimit = pCurLeaf->uEax;
2498	if ( uLimit >= UINT32_C(0xc0000000)
2499	&& uLimit <= UINT32_C(0xc00fffff))
2500	{
2501	if (uLimit > pConfig->uMaxCentaurLeaf)
2502	{
2503	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2504	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2505	uLimit + 1, UINT32_C(0xcfffffff));
2506	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2507	pCurLeaf->uEax = uLimit;
2508	}
2509	}
2510	else
2511	{
2512	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2513	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2514	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2515	}
2516	}
2517	}
2518
2519
2520	/**
2521	* Clears a CPUID leaf and all sub-leaves (to zero).
2522	*
2523	* @param pCpum The CPUM instance data.
2524	* @param uLeaf The leaf to clear.
2525	*/
2526	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2527	{
2528	uint32_t uSubLeaf = 0;
2529	PCPUMCPUIDLEAF pCurLeaf;
2530	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2531	{
2532	pCurLeaf->uEax = 0;
2533	pCurLeaf->uEbx = 0;
2534	pCurLeaf->uEcx = 0;
2535	pCurLeaf->uEdx = 0;
2536	uSubLeaf++;
2537	}
2538	}
2539
2540
2541	/**
2542	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2543	* the given leaf.
2544	*
2545	* @returns pLeaf.
2546	* @param pCpum The CPUM instance data.
2547	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2548	*/
2549	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2550	{
2551	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2552	if (pLeaf->fSubLeafMask != 0)
2553	{
2554	/*
2555	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2556	* Log everything while we're at it.
2557	*/
2558	LogRel(("CPUM:\n"
2559	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2560	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2561	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2562	for (;;)
2563	{
2564	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2565	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2566	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2567	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2568	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2569	break;
2570	pSubLeaf++;
2571	}
2572	LogRel(("CPUM:\n"));
2573
2574	/*
2575	* Remove the offending sub-leaves.
2576	*/
2577	if (pSubLeaf != pLeaf)
2578	{
2579	if (pSubLeaf != pLast)
2580	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2581	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2582	}
2583
2584	/*
2585	* Convert the first sub-leaf into a single leaf.
2586	*/
2587	pLeaf->uSubLeaf = 0;
2588	pLeaf->fSubLeafMask = 0;
2589	}
2590	return pLeaf;
2591	}
2592
2593
2594	/**
2595	* Sanitizes and adjust the CPUID leaves.
2596	*
2597	* Drop features that aren't virtualized (or virtualizable). Adjust information
2598	* and capabilities to fit the virtualized hardware. Remove information the
2599	* guest shouldn't have (because it's wrong in the virtual world or because it
2600	* gives away host details) or that we don't have documentation for and no idea
2601	* what means.
2602	*
2603	* @returns VBox status code.
2604	* @param pVM The cross context VM structure (for cCpus).
2605	* @param pCpum The CPUM instance data.
2606	* @param pConfig The CPUID configuration we've read from CFGM.
2607	*/
2608	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2609	{
2610	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2611	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2612	{ \
2613	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2614	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2615	}
2616	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2617	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2618	{ \
2619	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2620	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2621	}
2622	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2623	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2624	&& ((a_pLeafReg) & (fBitMask)) \
2625	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2626	{ \
2627	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2628	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2629	}
2630	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2631
2632	/* Cpuid 1:
2633	* EAX: CPU model, family and stepping.
2634	*
2635	* ECX + EDX: Supported features. Only report features we can support.
2636	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2637	* options may require adjusting (i.e. stripping what was enabled).
2638	*
2639	* EBX: Branding, CLFLUSH line size, logical processors per package and
2640	* initial APIC ID.
2641	*/
2642	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2643	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2644	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2645
2646	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2647	\| X86_CPUID_FEATURE_EDX_VME
2648	\| X86_CPUID_FEATURE_EDX_DE
2649	\| X86_CPUID_FEATURE_EDX_PSE
2650	\| X86_CPUID_FEATURE_EDX_TSC
2651	\| X86_CPUID_FEATURE_EDX_MSR
2652	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2653	\| X86_CPUID_FEATURE_EDX_MCE
2654	\| X86_CPUID_FEATURE_EDX_CX8
2655	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2656	//\| RT_BIT_32(10) - not defined
2657	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2658	//\| X86_CPUID_FEATURE_EDX_SEP
2659	\| X86_CPUID_FEATURE_EDX_MTRR
2660	\| X86_CPUID_FEATURE_EDX_PGE
2661	\| X86_CPUID_FEATURE_EDX_MCA
2662	\| X86_CPUID_FEATURE_EDX_CMOV
2663	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2664	\| X86_CPUID_FEATURE_EDX_PSE36
2665	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2666	\| X86_CPUID_FEATURE_EDX_CLFSH
2667	//\| RT_BIT_32(20) - not defined
2668	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2669	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2670	\| X86_CPUID_FEATURE_EDX_MMX
2671	\| X86_CPUID_FEATURE_EDX_FXSR
2672	\| X86_CPUID_FEATURE_EDX_SSE
2673	\| X86_CPUID_FEATURE_EDX_SSE2
2674	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2675	\| X86_CPUID_FEATURE_EDX_HTT
2676	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2677	//\| RT_BIT_32(30) - not defined
2678	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2679	;
2680	pStdFeatureLeaf->uEcx &= 0
2681	\| X86_CPUID_FEATURE_ECX_SSE3
2682	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2683	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2684	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2685	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2686	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2687	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2688	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2689	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2690	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2691	\| X86_CPUID_FEATURE_ECX_SSSE3
2692	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2693	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2694	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2695	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2696	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2697	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2698	\| (pConfig->enmPcid ? X86_CPUID_FEATURE_ECX_PCID : 0)
2699	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2700	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2701	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2702	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2703	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2704	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2705	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2706	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2707	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2708	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2709	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2710	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2711	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2712	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2713	;
2714
2715	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2716	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2717	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2718	{
2719	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2720	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2721	}
2722
2723	if (pCpum->u8PortableCpuIdLevel > 0)
2724	{
2725	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2726	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2727	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2728	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2729	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2730	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2731	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2732	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2733	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2734	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2735	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2736	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2737	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2738	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2739	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2740	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2741	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2742	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2743	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2744	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2745
2746	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2747	\| X86_CPUID_FEATURE_EDX_PSN
2748	\| X86_CPUID_FEATURE_EDX_DS
2749	\| X86_CPUID_FEATURE_EDX_ACPI
2750	\| X86_CPUID_FEATURE_EDX_SS
2751	\| X86_CPUID_FEATURE_EDX_TM
2752	\| X86_CPUID_FEATURE_EDX_PBE
2753	)));
2754	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2755	\| X86_CPUID_FEATURE_ECX_CPLDS
2756	\| X86_CPUID_FEATURE_ECX_AES
2757	\| X86_CPUID_FEATURE_ECX_VMX
2758	\| X86_CPUID_FEATURE_ECX_SMX
2759	\| X86_CPUID_FEATURE_ECX_EST
2760	\| X86_CPUID_FEATURE_ECX_TM2
2761	\| X86_CPUID_FEATURE_ECX_CNTXID
2762	\| X86_CPUID_FEATURE_ECX_FMA
2763	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2764	\| X86_CPUID_FEATURE_ECX_PDCM
2765	\| X86_CPUID_FEATURE_ECX_DCA
2766	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2767	)));
2768	}
2769
2770	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2771	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2772
2773	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2774	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2775	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2776	*/
2777	#ifdef VBOX_WITH_MULTI_CORE
2778	if (pVM->cCpus > 1)
2779	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2780	#endif
2781	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2782	{
2783	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2784	core times the number of CPU cores per processor */
2785	#ifdef VBOX_WITH_MULTI_CORE
2786	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2787	#else
2788	/* Single logical processor in a package. */
2789	pStdFeatureLeaf->uEbx \|= (1 << 16);
2790	#endif
2791	}
2792
2793	uint32_t uMicrocodeRev;
2794	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2795	if (RT_SUCCESS(rc))
2796	{
2797	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2798	}
2799	else
2800	{
2801	uMicrocodeRev = 0;
2802	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2803	}
2804
2805	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2806	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2807	*/
2808	if ( (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen)
2809	&& uMicrocodeRev < 0x8001126
2810	&& !pConfig->fForceVme)
2811	{
2812	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2813	LogRel(("CPUM: Zen VME workaround engaged\n"));
2814	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2815	}
2816
2817	/* Force standard feature bits. */
2818	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2819	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2820	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2821	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2822	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2823	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2824	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2825	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2826	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2827	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2828	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2829	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2830	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2831	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2832	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2833	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2834	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2835	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2836	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2837	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2838	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2839	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2840
2841	pStdFeatureLeaf = NULL; /* Must refetch! */
2842
2843	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2844	* AMD:
2845	* EAX: CPU model, family and stepping.
2846	*
2847	* ECX + EDX: Supported features. Only report features we can support.
2848	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2849	* options may require adjusting (i.e. stripping what was enabled).
2850	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2851	*
2852	* EBX: Branding ID and package type (or reserved).
2853	*
2854	* Intel and probably most others:
2855	* EAX: 0
2856	* EBX: 0
2857	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2858	*/
2859	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2860	if (pExtFeatureLeaf)
2861	{
2862	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2863
2864	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2865	\| X86_CPUID_AMD_FEATURE_EDX_VME
2866	\| X86_CPUID_AMD_FEATURE_EDX_DE
2867	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2868	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2869	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2870	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2871	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2872	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2873	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2874	//\| RT_BIT_32(10) - reserved
2875	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2876	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2877	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2878	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2879	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2880	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2881	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2882	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2883	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2884	//\| RT_BIT_32(18) - reserved
2885	//\| RT_BIT_32(19) - reserved
2886	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2887	//\| RT_BIT_32(21) - reserved
2888	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2889	\| X86_CPUID_AMD_FEATURE_EDX_MMX
2890	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
2891	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
2892	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2893	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2894	//\| RT_BIT_32(28) - reserved
2895	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2896	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2897	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
2898	;
2899	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2900	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2901	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
2902	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2903	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
2904	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2905	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2906	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2907	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2908	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2909	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2910	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
2911	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
2912	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2913	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
2914	//\| RT_BIT_32(14) - reserved
2915	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2916	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2917	//\| RT_BIT_32(17) - reserved
2918	//\| RT_BIT_32(18) - reserved
2919	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2920	//\| RT_BIT_32(20) - reserved
2921	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2922	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2923	//\| RT_BIT_32(23) - reserved
2924	//\| RT_BIT_32(24) - reserved
2925	//\| RT_BIT_32(25) - reserved
2926	//\| RT_BIT_32(26) - reserved
2927	//\| RT_BIT_32(27) - reserved
2928	//\| RT_BIT_32(28) - reserved
2929	//\| RT_BIT_32(29) - reserved
2930	//\| RT_BIT_32(30) - reserved
2931	//\| RT_BIT_32(31) - reserved
2932	;
2933	#ifdef VBOX_WITH_MULTI_CORE
2934	if ( pVM->cCpus > 1
2935	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2936	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2937	#endif
2938
2939	if (pCpum->u8PortableCpuIdLevel > 0)
2940	{
2941	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2942	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
2943	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2944	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2945	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2946	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2947	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2948	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2949	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2950	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2951	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2952	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2953	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2954	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2955	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2956	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2957
2958	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2959	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2960	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2961	\| X86_CPUID_AMD_FEATURE_ECX_IBS
2962	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2963	\| X86_CPUID_AMD_FEATURE_ECX_WDT
2964	\| X86_CPUID_AMD_FEATURE_ECX_LWP
2965	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
2966	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2967	\| UINT32_C(0xff964000)
2968	)));
2969	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2970	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2971	\| RT_BIT(18)
2972	\| RT_BIT(19)
2973	\| RT_BIT(21)
2974	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2975	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2976	\| RT_BIT(28)
2977	)));
2978	}
2979
2980	/* Force extended feature bits. */
2981	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2982	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
2983	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2984	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2985	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2986	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2987	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2988	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2989	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2990	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2991	}
2992	pExtFeatureLeaf = NULL; /* Must refetch! */
2993
2994
2995	/* Cpuid 2:
2996	* Intel: (Nondeterministic) Cache and TLB information
2997	* AMD: Reserved
2998	* VIA: Reserved
2999	* Safe to expose.
3000	*/
3001	uint32_t uSubLeaf = 0;
3002	PCPUMCPUIDLEAF pCurLeaf;
3003	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
3004	{
3005	if ((pCurLeaf->uEax & 0xff) > 1)
3006	{
3007	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
3008	pCurLeaf->uEax &= UINT32_C(0xffffff01);
3009	}
3010	uSubLeaf++;
3011	}
3012
3013	/* Cpuid 3:
3014	* Intel: EAX, EBX - reserved (transmeta uses these)
3015	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3016	* AMD: Reserved
3017	* VIA: Reserved
3018	* Safe to expose
3019	*/
3020	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3021	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3022	{
3023	uSubLeaf = 0;
3024	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3025	{
3026	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3027	if (pCpum->u8PortableCpuIdLevel > 0)
3028	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3029	uSubLeaf++;
3030	}
3031	}
3032
3033	/* Cpuid 4 + ECX:
3034	* Intel: Deterministic Cache Parameters Leaf.
3035	* AMD: Reserved
3036	* VIA: Reserved
3037	* Safe to expose, except for EAX:
3038	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3039	* Bits 31-26: Maximum number of processor cores in this physical package**
3040	* Note: These SMP values are constant regardless of ECX
3041	*/
3042	uSubLeaf = 0;
3043	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3044	{
3045	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3046	#ifdef VBOX_WITH_MULTI_CORE
3047	if ( pVM->cCpus > 1
3048	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3049	{
3050	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3051	/* One logical processor with possibly multiple cores. */
3052	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3053	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3054	}
3055	#endif
3056	uSubLeaf++;
3057	}
3058
3059	/* Cpuid 5: Monitor/mwait Leaf
3060	* Intel: ECX, EDX - reserved
3061	* EAX, EBX - Smallest and largest monitor line size
3062	* AMD: EDX - reserved
3063	* EAX, EBX - Smallest and largest monitor line size
3064	* ECX - extensions (ignored for now)
3065	* VIA: Reserved
3066	* Safe to expose
3067	*/
3068	uSubLeaf = 0;
3069	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3070	{
3071	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3072	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3073	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3074
3075	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3076	if (pConfig->enmMWaitExtensions)
3077	{
3078	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3079	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3080	it shall be part of our power management virtualization model */
3081	#if 0
3082	/* MWAIT sub C-states */
3083	pCurLeaf->uEdx =
3084	(0 << 0) /* 0 in C0 */ \|
3085	(2 << 4) /* 2 in C1 */ \|
3086	(2 << 8) /* 2 in C2 */ \|
3087	(2 << 12) /* 2 in C3 */ \|
3088	(0 << 16) /* 0 in C4 */
3089	;
3090	#endif
3091	}
3092	else
3093	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3094	uSubLeaf++;
3095	}
3096
3097	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3098	* Intel: Various stuff.
3099	* AMD: EAX, EBX, EDX - reserved.
3100	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3101	* present. Same as intel.
3102	* VIA: ??
3103	*
3104	* We clear everything here for now.
3105	*/
3106	cpumR3CpuIdZeroLeaf(pCpum, 6);
3107
3108	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3109	* EAX: Number of sub leaves.
3110	* EBX+ECX+EDX: Feature flags
3111	*
3112	* We only have documentation for one sub-leaf, so clear all other (no need
3113	* to remove them as such, just set them to zero).
3114	*
3115	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3116	* options may require adjusting (i.e. stripping what was enabled).
3117	*/
3118	uSubLeaf = 0;
3119	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3120	{
3121	switch (uSubLeaf)
3122	{
3123	case 0:
3124	{
3125	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3126	pCurLeaf->uEbx &= 0
3127	\| (pConfig->enmFsGsBase ? X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE : 0)
3128	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3129	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3130	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3131	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3132	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3133	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3134	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3135	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3136	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3137	\| (pConfig->enmInvpcid ? X86_CPUID_STEXT_FEATURE_EBX_INVPCID : 0)
3138	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3139	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3140	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3141	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3142	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3143	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3144	//\| RT_BIT(17) - reserved
3145	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3146	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3147	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3148	//\| RT_BIT(21) - reserved
3149	//\| RT_BIT(22) - reserved
3150	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3151	//\| RT_BIT(24) - reserved
3152	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3153	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3154	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3155	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3156	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3157	//\| RT_BIT(30) - reserved
3158	//\| RT_BIT(31) - reserved
3159	;
3160	pCurLeaf->uEcx &= 0
3161	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3162	;
3163	pCurLeaf->uEdx &= 0
3164	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3165	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3166	//\| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT(29)
3167	;
3168
3169	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3170	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3171	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3172	{
3173	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3174	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3175	}
3176
3177	if (pCpum->u8PortableCpuIdLevel > 0)
3178	{
3179	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3180	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3181	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3182	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3183	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3184	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3185	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3186	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3187	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3188	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3189	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3190	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3191	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3192	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3193	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3194	}
3195
3196	/* Force standard feature bits. */
3197	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3198	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3199	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3200	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3201	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3202	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3203	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3204	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3205	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3206	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3207	break;
3208	}
3209
3210	default:
3211	/* Invalid index, all values are zero. */
3212	pCurLeaf->uEax = 0;
3213	pCurLeaf->uEbx = 0;
3214	pCurLeaf->uEcx = 0;
3215	pCurLeaf->uEdx = 0;
3216	break;
3217	}
3218	uSubLeaf++;
3219	}
3220
3221	/* Cpuid 8: Marked as reserved by Intel and AMD.
3222	* We zero this since we don't know what it may have been used for.
3223	*/
3224	cpumR3CpuIdZeroLeaf(pCpum, 8);
3225
3226	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3227	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3228	* EBX, ECX, EDX - reserved.
3229	* AMD: Reserved
3230	* VIA: ??
3231	*
3232	* We zero this.
3233	*/
3234	cpumR3CpuIdZeroLeaf(pCpum, 9);
3235
3236	/* Cpuid 0xa: Architectural Performance Monitor Features
3237	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3238	* EBX, ECX, EDX - reserved.
3239	* AMD: Reserved
3240	* VIA: ??
3241	*
3242	* We zero this, for now at least.
3243	*/
3244	cpumR3CpuIdZeroLeaf(pCpum, 10);
3245
3246	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3247	* Intel: EAX - APCI ID shift right for next level.
3248	* EBX - Factory configured cores/threads at this level.
3249	* ECX - Level number (same as input) and level type (1,2,0).
3250	* EDX - Extended initial APIC ID.
3251	* AMD: Reserved
3252	* VIA: ??
3253	*/
3254	uSubLeaf = 0;
3255	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3256	{
3257	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3258	{
3259	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3260	if (bLevelType == 1)
3261	{
3262	/* Thread level - we don't do threads at the moment. */
3263	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3264	pCurLeaf->uEbx = 1;
3265	}
3266	else if (bLevelType == 2)
3267	{
3268	/* Core level. */
3269	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3270	#ifdef VBOX_WITH_MULTI_CORE
3271	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3272	pCurLeaf->uEax++;
3273	#endif
3274	pCurLeaf->uEbx = pVM->cCpus;
3275	}
3276	else
3277	{
3278	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3279	pCurLeaf->uEax = 0;
3280	pCurLeaf->uEbx = 0;
3281	pCurLeaf->uEcx = 0;
3282	}
3283	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3284	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3285	}
3286	else
3287	{
3288	pCurLeaf->uEax = 0;
3289	pCurLeaf->uEbx = 0;
3290	pCurLeaf->uEcx = 0;
3291	pCurLeaf->uEdx = 0;
3292	}
3293	uSubLeaf++;
3294	}
3295
3296	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3297	* We zero this since we don't know what it may have been used for.
3298	*/
3299	cpumR3CpuIdZeroLeaf(pCpum, 12);
3300
3301	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3302	* ECX=0: EAX - Valid bits in XCR0[31:0].
3303	* EBX - Maximum state size as per current XCR0 value.
3304	* ECX - Maximum state size for all supported features.
3305	* EDX - Valid bits in XCR0[63:32].
3306	* ECX=1: EAX - Various X-features.
3307	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3308	* ECX - Valid bits in IA32_XSS[31:0].
3309	* EDX - Valid bits in IA32_XSS[63:32].
3310	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3311	* if the bit invalid all four registers are set to zero.
3312	* EAX - The state size for this feature.
3313	* EBX - The state byte offset of this feature.
3314	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3315	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3316	*
3317	* Clear them all as we don't currently implement extended CPU state.
3318	*/
3319	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3320	uint64_t fGuestXcr0Mask = 0;
3321	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3322	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3323	{
3324	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3325	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3326	fGuestXcr0Mask \|= XSAVE_C_YMM;
3327	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3328	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3329	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3330	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3331
3332	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3333	}
3334	pStdFeatureLeaf = NULL;
3335	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3336
3337	/* Work the sub-leaves. */
3338	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3339	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3340	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3341	{
3342	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3343	if (pCurLeaf)
3344	{
3345	if (fGuestXcr0Mask)
3346	{
3347	switch (uSubLeaf)
3348	{
3349	case 0:
3350	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3351	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3352	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3353	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3354	VERR_CPUM_IPE_1);
3355	cbXSaveMaxActual = pCurLeaf->uEcx;
3356	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3357	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3358	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3359	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3360	VERR_CPUM_IPE_2);
3361	continue;
3362	case 1:
3363	pCurLeaf->uEax &= 0;
3364	pCurLeaf->uEcx &= 0;
3365	pCurLeaf->uEdx &= 0;
3366	/** @todo what about checking ebx? */
3367	continue;
3368	default:
3369	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3370	{
3371	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3372	&& pCurLeaf->uEax > 0
3373	&& pCurLeaf->uEbx < cbXSaveMaxActual
3374	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3375	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3376	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3377	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3378	VERR_CPUM_IPE_2);
3379	AssertLogRel(!(pCurLeaf->uEcx & 1));
3380	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3381	pCurLeaf->uEdx = 0; /* it's reserved... */
3382	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3383	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3384	continue;
3385	}
3386	break;
3387	}
3388	}
3389
3390	/* Clear the leaf. */
3391	pCurLeaf->uEax = 0;
3392	pCurLeaf->uEbx = 0;
3393	pCurLeaf->uEcx = 0;
3394	pCurLeaf->uEdx = 0;
3395	}
3396	}
3397
3398	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3399	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3400	{
3401	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3402	if (pCurLeaf)
3403	{
3404	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3405	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3406	pCurLeaf->uEbx = cbXSaveMaxReport;
3407	pCurLeaf->uEcx = cbXSaveMaxReport;
3408	}
3409	}
3410
3411	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3412	* We zero this since we don't know what it may have been used for.
3413	*/
3414	cpumR3CpuIdZeroLeaf(pCpum, 14);
3415
3416	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3417	* also known as Intel Resource Director Technology (RDT) Monitoring
3418	* We zero this as we don't currently virtualize PQM.
3419	*/
3420	cpumR3CpuIdZeroLeaf(pCpum, 15);
3421
3422	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3423	* also known as Intel Resource Director Technology (RDT) Allocation
3424	* We zero this as we don't currently virtualize PQE.
3425	*/
3426	cpumR3CpuIdZeroLeaf(pCpum, 16);
3427
3428	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3429	* We zero this since we don't know what it may have been used for.
3430	*/
3431	cpumR3CpuIdZeroLeaf(pCpum, 17);
3432
3433	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3434	* We zero this as we don't currently virtualize this.
3435	*/
3436	cpumR3CpuIdZeroLeaf(pCpum, 18);
3437
3438	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3439	* We zero this since we don't know what it may have been used for.
3440	*/
3441	cpumR3CpuIdZeroLeaf(pCpum, 19);
3442
3443	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3444	* We zero this as we don't currently virtualize this.
3445	*/
3446	cpumR3CpuIdZeroLeaf(pCpum, 20);
3447
3448	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3449	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3450	* EAX - denominator (unsigned).
3451	* EBX - numerator (unsigned).
3452	* ECX, EDX - reserved.
3453	* AMD: Reserved / undefined / not implemented.
3454	* VIA: Reserved / undefined / not implemented.
3455	* We zero this as we don't currently virtualize this.
3456	*/
3457	cpumR3CpuIdZeroLeaf(pCpum, 21);
3458
3459	/* Cpuid 0x16: Processor frequency info
3460	* Intel: EAX - Core base frequency in MHz.
3461	* EBX - Core maximum frequency in MHz.
3462	* ECX - Bus (reference) frequency in MHz.
3463	* EDX - Reserved.
3464	* AMD: Reserved / undefined / not implemented.
3465	* VIA: Reserved / undefined / not implemented.
3466	* We zero this as we don't currently virtualize this.
3467	*/
3468	cpumR3CpuIdZeroLeaf(pCpum, 22);
3469
3470	/* Cpuid 0x17..0x10000000: Unknown.
3471	* We don't know these and what they mean, so remove them. */
3472	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3473	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3474
3475
3476	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3477	* We remove all these as we're a hypervisor and must provide our own.
3478	*/
3479	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3480	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3481
3482
3483	/* Cpuid 0x80000000 is harmless. */
3484
3485	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3486
3487	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3488
3489	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3490	* Safe to pass on to the guest.
3491	*
3492	* AMD: 0x800000005 L1 cache information
3493	* 0x800000006 L2/L3 cache information
3494	* Intel: 0x800000005 reserved
3495	* 0x800000006 L2 cache information
3496	* VIA: 0x800000005 TLB and L1 cache information
3497	* 0x800000006 L2 cache information
3498	*/
3499
3500	/* Cpuid 0x800000007: Advanced Power Management Information.
3501	* AMD: EAX: Processor feedback capabilities.
3502	* EBX: RAS capabilites.
3503	* ECX: Advanced power monitoring interface.
3504	* EDX: Enhanced power management capabilities.
3505	* Intel: EAX, EBX, ECX - reserved.
3506	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3507	* VIA: Reserved
3508	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3509	*/
3510	uSubLeaf = 0;
3511	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3512	{
3513	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3514	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3515	{
3516	/*
3517	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3518	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3519	* bit is now configurable.
3520	*/
3521	pCurLeaf->uEdx &= 0
3522	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3523	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3524	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3525	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3526	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3527	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3528	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3529	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3530	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3531	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3532	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3533	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3534	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3535	\| 0;
3536	}
3537	else
3538	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3539	if (!pConfig->fInvariantTsc)
3540	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3541	uSubLeaf++;
3542	}
3543
3544	/* Cpuid 0x80000008:
3545	* AMD: EBX, EDX - reserved
3546	* EAX: Virtual/Physical/Guest address Size
3547	* ECX: Number of cores + APICIdCoreIdSize
3548	* Intel: EAX: Virtual/Physical address Size
3549	* EBX, ECX, EDX - reserved
3550	* VIA: EAX: Virtual/Physical address Size
3551	* EBX, ECX, EDX - reserved
3552	*
3553	* We only expose the virtual+pysical address size to the guest atm.
3554	* On AMD we set the core count, but not the apic id stuff as we're
3555	* currently not doing the apic id assignments in a complatible manner.
3556	*/
3557	uSubLeaf = 0;
3558	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3559	{
3560	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3561	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3562	pCurLeaf->uEdx = 0; /* reserved */
3563
3564	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3565	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3566	pCurLeaf->uEcx = 0;
3567	#ifdef VBOX_WITH_MULTI_CORE
3568	if ( pVM->cCpus > 1
3569	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3570	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3571	#endif
3572	uSubLeaf++;
3573	}
3574
3575	/* Cpuid 0x80000009: Reserved
3576	* We zero this since we don't know what it may have been used for.
3577	*/
3578	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3579
3580	/* Cpuid 0x8000000a: SVM Information
3581	* AMD: EAX - SVM revision.
3582	* EBX - Number of ASIDs.
3583	* ECX - Reserved.
3584	* EDX - SVM Feature identification.
3585	*/
3586	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3587	if (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
3588	{
3589	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3590	pSvmFeatureLeaf->uEax = 0x1;
3591	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3592	pSvmFeatureLeaf->uEcx = 0;
3593	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3594	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3595	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3596	}
3597	else
3598	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3599
3600	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3601	* We clear these as we don't know what purpose they might have. */
3602	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3603	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3604
3605	/* Cpuid 0x80000019: TLB configuration
3606	* Seems to be harmless, pass them thru as is. */
3607
3608	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3609	* Strip anything we don't know what is or addresses feature we don't implement. */
3610	uSubLeaf = 0;
3611	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3612	{
3613	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3614	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3615	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3616	;
3617	pCurLeaf->uEbx = 0; /* reserved */
3618	pCurLeaf->uEcx = 0; /* reserved */
3619	pCurLeaf->uEdx = 0; /* reserved */
3620	uSubLeaf++;
3621	}
3622
3623	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3624	* Clear this as we don't currently virtualize this feature. */
3625	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3626
3627	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3628	* Clear this as we don't currently virtualize this feature. */
3629	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3630
3631	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3632	* We need to sanitize the cores per cache (EAX[25:14]).
3633	*
3634	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3635	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3636	* slightly different meaning.
3637	*/
3638	uSubLeaf = 0;
3639	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3640	{
3641	#ifdef VBOX_WITH_MULTI_CORE
3642	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3643	if (cCores > pVM->cCpus)
3644	cCores = pVM->cCpus;
3645	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3646	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3647	#else
3648	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3649	#endif
3650	uSubLeaf++;
3651	}
3652
3653	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3654	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3655	* setup, we have one compute unit with all the cores in it. Single node.
3656	*/
3657	uSubLeaf = 0;
3658	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3659	{
3660	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3661	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3662	{
3663	#ifdef VBOX_WITH_MULTI_CORE
3664	pCurLeaf->uEbx = pVM->cCpus < 0x100
3665	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3666	#else
3667	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3668	#endif
3669	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3670	}
3671	else
3672	{
3673	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3674	pCurLeaf->uEbx = 0; /* Reserved. */
3675	pCurLeaf->uEcx = 0; /* Reserved. */
3676	}
3677	pCurLeaf->uEdx = 0; /* Reserved. */
3678	uSubLeaf++;
3679	}
3680
3681	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3682	* We don't know these and what they mean, so remove them. */
3683	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3684	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3685
3686	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3687	* Just pass it thru for now. */
3688
3689	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3690	* Just pass it thru for now. */
3691
3692	/* Cpuid 0xc0000000: Centaur stuff.
3693	* Harmless, pass it thru. */
3694
3695	/* Cpuid 0xc0000001: Centaur features.
3696	* VIA: EAX - Family, model, stepping.
3697	* EDX - Centaur extended feature flags. Nothing interesting, except may
3698	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3699	* EBX, ECX - reserved.
3700	* We keep EAX but strips the rest.
3701	*/
3702	uSubLeaf = 0;
3703	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3704	{
3705	pCurLeaf->uEbx = 0;
3706	pCurLeaf->uEcx = 0;
3707	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3708	uSubLeaf++;
3709	}
3710
3711	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3712	* We only have fixed stale values, but should be harmless. */
3713
3714	/* Cpuid 0xc0000003: Reserved.
3715	* We zero this since we don't know what it may have been used for.
3716	*/
3717	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3718
3719	/* Cpuid 0xc0000004: Centaur Performance Info.
3720	* We only have fixed stale values, but should be harmless. */
3721
3722
3723	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3724	* We don't know these and what they mean, so remove them. */
3725	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3726	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3727
3728	return VINF_SUCCESS;
3729	#undef PORTABLE_DISABLE_FEATURE_BIT
3730	#undef PORTABLE_CLEAR_BITS_WHEN
3731	}
3732
3733
3734	/**
3735	* Reads a value in /CPUM/IsaExts/ node.
3736	*
3737	* @returns VBox status code (error message raised).
3738	* @param pVM The cross context VM structure. (For errors.)
3739	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3740	* @param pszValueName The value / extension name.
3741	* @param penmValue Where to return the choice.
3742	* @param enmDefault The default choice.
3743	*/
3744	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3745	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3746	{
3747	/*
3748	* Try integer encoding first.
3749	*/
3750	uint64_t uValue;
3751	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3752	if (RT_SUCCESS(rc))
3753	switch (uValue)
3754	{
3755	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3756	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3757	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3758	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3759	default:
3760	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3761	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3762	pszValueName, uValue);
3763	}
3764	/*
3765	* If missing, use default.
3766	*/
3767	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3768	*penmValue = enmDefault;
3769	else
3770	{
3771	if (rc == VERR_CFGM_NOT_INTEGER)
3772	{
3773	/*
3774	* Not an integer, try read it as a string.
3775	*/
3776	char szValue[32];
3777	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3778	if (RT_SUCCESS(rc))
3779	{
3780	RTStrToLower(szValue);
3781	size_t cchValue = strlen(szValue);
3782	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3783	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3784	*penmValue = CPUMISAEXTCFG_DISABLED;
3785	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3786	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3787	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3788	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3789	else if (EQ("portable"))
3790	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3791	else if (EQ("default") \|\| EQ("def"))
3792	*penmValue = enmDefault;
3793	else
3794	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3795	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3796	pszValueName, uValue);
3797	#undef EQ
3798	}
3799	}
3800	if (RT_FAILURE(rc))
3801	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3802	}
3803	return VINF_SUCCESS;
3804	}
3805
3806
3807	/**
3808	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3809	*
3810	* @returns VBox status code (error message raised).
3811	* @param pVM The cross context VM structure. (For errors.)
3812	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3813	* @param pszValueName The value / extension name.
3814	* @param penmValue Where to return the choice.
3815	* @param enmDefault The default choice.
3816	* @param fAllowed Allowed choice. Applied both to the result and to
3817	* the default value.
3818	*/
3819	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3820	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3821	{
3822	int rc;
3823	if (fAllowed)
3824	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3825	else
3826	{
3827	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3828	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3829	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3830	*penmValue = CPUMISAEXTCFG_DISABLED;
3831	}
3832	return rc;
3833	}
3834
3835
3836	/**
3837	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3838	*
3839	* @returns VBox status code (error message raised).
3840	* @param pVM The cross context VM structure. (For errors.)
3841	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3842	* @param pCpumCfg The /CPUM node (can be NULL).
3843	* @param pszValueName The value / extension name.
3844	* @param penmValue Where to return the choice.
3845	* @param enmDefault The default choice.
3846	*/
3847	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3848	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3849	{
3850	if (CFGMR3Exists(pCpumCfg, pszValueName))
3851	{
3852	if (!CFGMR3Exists(pIsaExts, pszValueName))
3853	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3854	else
3855	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3856	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3857	pszValueName, pszValueName);
3858
3859	bool fLegacy;
3860	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3861	if (RT_SUCCESS(rc))
3862	{
3863	*penmValue = fLegacy;
3864	return VINF_SUCCESS;
3865	}
3866	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3867	}
3868
3869	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3870	}
3871
3872
3873	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3874	{
3875	int rc;
3876
3877	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3878	* When non-zero CPUID features that could cause portability issues will be
3879	* stripped. The higher the value the more features gets stripped. Higher
3880	* values should only be used when older CPUs are involved since it may
3881	* harm performance and maybe also cause problems with specific guests. */
3882	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
3883	AssertLogRelRCReturn(rc, rc);
3884
3885	/** @cfgm{/CPUM/GuestCpuName, string}
3886	* The name of the CPU we're to emulate. The default is the host CPU.
3887	* Note! CPUs other than "host" one is currently unsupported. */
3888	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3889	AssertLogRelRCReturn(rc, rc);
3890
3891	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3892	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3893	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3894	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3895	*/
3896	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3897	AssertLogRelRCReturn(rc, rc);
3898
3899	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
3900	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
3901	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
3902	* 64-bit linux guests which assume the presence of AMD performance counters
3903	* that we do not virtualize.
3904	*/
3905	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
3906	AssertLogRelRCReturn(rc, rc);
3907
3908	/** @cfgm{/CPUM/ForceVme, boolean, false}
3909	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
3910	* By default the flag is passed thru as is from the host CPU, except
3911	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
3912	* guests and DOS boxes in general.
3913	*/
3914	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
3915	AssertLogRelRCReturn(rc, rc);
3916
3917	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3918	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
3919	* probably going to be a temporary hack, so don't depend on this.
3920	* The 1st byte of the value is the stepping, the 2nd byte value is the model
3921	* number and the 3rd byte value is the family, and the 4th value must be zero.
3922	*/
3923	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3924	AssertLogRelRCReturn(rc, rc);
3925
3926	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3927	* The last standard leaf to keep. The actual last value that is stored in EAX
3928	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3929	* removed. (This works independently of and differently from NT4LeafLimit.)
3930	* The default is usually set to what we're able to reasonably sanitize.
3931	*/
3932	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3933	AssertLogRelRCReturn(rc, rc);
3934
3935	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3936	* The last extended leaf to keep. The actual last value that is stored in EAX
3937	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3938	* leaf are removed. The default is set to what we're able to sanitize.
3939	*/
3940	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3941	AssertLogRelRCReturn(rc, rc);
3942
3943	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3944	* The last extended leaf to keep. The actual last value that is stored in EAX
3945	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3946	* leaf are removed. The default is set to what we're able to sanitize.
3947	*/
3948	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3949	AssertLogRelRCReturn(rc, rc);
3950
3951	bool fQueryNestedHwvirt = false;
3952	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3953	fQueryNestedHwvirt \|= RT_BOOL(pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD);
3954	#endif
3955	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3956	fQueryNestedHwvirt \|= RT_BOOL( pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
3957	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA);
3958	#endif
3959	if (fQueryNestedHwvirt)
3960	{
3961	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
3962	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
3963	* The default is false, and when enabled requires a 64-bit CPU with support for
3964	* nested-paging and AMD-V or unrestricted guest mode.
3965	*/
3966	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
3967	AssertLogRelRCReturn(rc, rc);
3968	if ( pConfig->fNestedHWVirt
3969	&& !fNestedPagingAndFullGuestExec)
3970	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
3971	"Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
3972
3973	/** @todo Think about enabling this later with NEM/KVM. */
3974	if ( pConfig->fNestedHWVirt
3975	&& VM_IS_NEM_ENABLED(pVM))
3976	{
3977	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
3978	pConfig->fNestedHWVirt = false;
3979	}
3980
3981	#if HC_ARCH_BITS == 32
3982	/* We don't support nested hardware virtualization on 32-bit hosts. */
3983	if (pConfig->fNestedHWVirt)
3984	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
3985	"Cannot enable nested VT-x/AMD-V on a 32-bit host\n");
3986	#endif
3987	}
3988
3989	/*
3990	* Instruction Set Architecture (ISA) Extensions.
3991	*/
3992	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3993	if (pIsaExts)
3994	{
3995	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3996	"CMPXCHG16B"
3997	"\|MONITOR"
3998	"\|MWaitExtensions"
3999	"\|SSE4.1"
4000	"\|SSE4.2"
4001	"\|XSAVE"
4002	"\|AVX"
4003	"\|AVX2"
4004	"\|AESNI"
4005	"\|PCLMUL"
4006	"\|POPCNT"
4007	"\|MOVBE"
4008	"\|RDRAND"
4009	"\|RDSEED"
4010	"\|CLFLUSHOPT"
4011	"\|FSGSBASE"
4012	"\|PCID"
4013	"\|INVPCID"
4014	"\|ABM"
4015	"\|SSE4A"
4016	"\|MISALNSSE"
4017	"\|3DNOWPRF"
4018	"\|AXMMX"
4019	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
4020	if (RT_FAILURE(rc))
4021	return rc;
4022	}
4023
4024	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
4025	* Expose CMPXCHG16B to the guest if supported by the host. For the time
4026	* being the default is to only do this for VMs with nested paging and AMD-V or
4027	* unrestricted guest mode.
4028	*/
4029	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
4030	AssertLogRelRCReturn(rc, rc);
4031
4032	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4033	* Expose MONITOR/MWAIT instructions to the guest.
4034	*/
4035	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4036	AssertLogRelRCReturn(rc, rc);
4037
4038	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4039	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4040	* break on interrupt feature (bit 1).
4041	*/
4042	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4043	AssertLogRelRCReturn(rc, rc);
4044
4045	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4046	* Expose SSE4.1 to the guest if available.
4047	*/
4048	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4049	AssertLogRelRCReturn(rc, rc);
4050
4051	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4052	* Expose SSE4.2 to the guest if available.
4053	*/
4054	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4055	AssertLogRelRCReturn(rc, rc);
4056
4057	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4058	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4059	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
4060	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
4061	&& ( !HMIsLongModeAllowed(pVM)
4062	\|\| NEMHCIsLongModeAllowed(pVM))
4063	#endif
4064	;
4065	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4066
4067	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4068	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4069	* default is to only expose this to VMs with nested paging and AMD-V or
4070	* unrestricted guest execution mode. Not possible to force this one without
4071	* host support at the moment.
4072	*/
4073	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4074	fMayHaveXSave /fAllowed/);
4075	AssertLogRelRCReturn(rc, rc);
4076
4077	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4078	* Expose the AVX instruction set extensions to the guest if available and
4079	* XSAVE is exposed too. For the time being the default is to only expose this
4080	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4081	*/
4082	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4083	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4084	AssertLogRelRCReturn(rc, rc);
4085
4086	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4087	* Expose the AVX2 instruction set extensions to the guest if available and
4088	* XSAVE is exposed too. For the time being the default is to only expose this
4089	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4090	*/
4091	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4092	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4093	AssertLogRelRCReturn(rc, rc);
4094
4095	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4096	* Whether to expose the AES instructions to the guest. For the time being the
4097	* default is to only do this for VMs with nested paging and AMD-V or
4098	* unrestricted guest mode.
4099	*/
4100	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4101	AssertLogRelRCReturn(rc, rc);
4102
4103	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4104	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4105	* being the default is to only do this for VMs with nested paging and AMD-V or
4106	* unrestricted guest mode.
4107	*/
4108	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4109	AssertLogRelRCReturn(rc, rc);
4110
4111	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4112	* Whether to expose the POPCNT instructions to the guest. For the time
4113	* being the default is to only do this for VMs with nested paging and AMD-V or
4114	* unrestricted guest mode.
4115	*/
4116	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4117	AssertLogRelRCReturn(rc, rc);
4118
4119	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4120	* Whether to expose the MOVBE instructions to the guest. For the time
4121	* being the default is to only do this for VMs with nested paging and AMD-V or
4122	* unrestricted guest mode.
4123	*/
4124	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4125	AssertLogRelRCReturn(rc, rc);
4126
4127	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4128	* Whether to expose the RDRAND instructions to the guest. For the time being
4129	* the default is to only do this for VMs with nested paging and AMD-V or
4130	* unrestricted guest mode.
4131	*/
4132	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4133	AssertLogRelRCReturn(rc, rc);
4134
4135	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4136	* Whether to expose the RDSEED instructions to the guest. For the time being
4137	* the default is to only do this for VMs with nested paging and AMD-V or
4138	* unrestricted guest mode.
4139	*/
4140	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4141	AssertLogRelRCReturn(rc, rc);
4142
4143	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4144	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4145	* being the default is to only do this for VMs with nested paging and AMD-V or
4146	* unrestricted guest mode.
4147	*/
4148	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4149	AssertLogRelRCReturn(rc, rc);
4150
4151	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4152	* Whether to expose the read/write FSGSBASE instructions to the guest.
4153	*/
4154	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4155	AssertLogRelRCReturn(rc, rc);
4156
4157	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4158	* Whether to expose the PCID feature to the guest.
4159	*/
4160	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4161	AssertLogRelRCReturn(rc, rc);
4162
4163	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4164	* Whether to expose the INVPCID instruction to the guest.
4165	*/
4166	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4167	AssertLogRelRCReturn(rc, rc);
4168
4169
4170	/* AMD: */
4171
4172	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4173	* Whether to expose the AMD ABM instructions to the guest. For the time
4174	* being the default is to only do this for VMs with nested paging and AMD-V or
4175	* unrestricted guest mode.
4176	*/
4177	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4178	AssertLogRelRCReturn(rc, rc);
4179
4180	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4181	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4182	* being the default is to only do this for VMs with nested paging and AMD-V or
4183	* unrestricted guest mode.
4184	*/
4185	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4186	AssertLogRelRCReturn(rc, rc);
4187
4188	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4189	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4190	* the time being the default is to only do this for VMs with nested paging and
4191	* AMD-V or unrestricted guest mode.
4192	*/
4193	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4194	AssertLogRelRCReturn(rc, rc);
4195
4196	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4197	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4198	* For the time being the default is to only do this for VMs with nested paging
4199	* and AMD-V or unrestricted guest mode.
4200	*/
4201	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4202	AssertLogRelRCReturn(rc, rc);
4203
4204	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4205	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4206	* the default is to only do this for VMs with nested paging and AMD-V or
4207	* unrestricted guest mode.
4208	*/
4209	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4210	AssertLogRelRCReturn(rc, rc);
4211
4212	return VINF_SUCCESS;
4213	}
4214
4215
4216	/**
4217	* Initializes the emulated CPU's CPUID & MSR information.
4218	*
4219	* @returns VBox status code.
4220	* @param pVM The cross context VM structure.
4221	*/
4222	int cpumR3InitCpuIdAndMsrs(PVM pVM)
4223	{
4224	PCPUM pCpum = &pVM->cpum.s;
4225	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4226
4227	/*
4228	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4229	* on construction and manage everything from here on.
4230	*/
4231	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
4232	pVM->aCpus[iCpu].cpum.s.fCpuIdApicFeatureVisible = true;
4233
4234	/*
4235	* Read the configuration.
4236	*/
4237	CPUMCPUIDCONFIG Config;
4238	RT_ZERO(Config);
4239
4240	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4241	AssertRCReturn(rc, rc);
4242
4243	/*
4244	* Get the guest CPU data from the database and/or the host.
4245	*
4246	* The CPUID and MSRs are currently living on the regular heap to avoid
4247	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4248	* API for the hyper heap). This means special cleanup considerations.
4249	*/
4250	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4251	if (RT_FAILURE(rc))
4252	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4253	? VMSetError(pVM, rc, RT_SRC_POS,
4254	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4255	: rc;
4256
4257	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4258	{
4259	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4260	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4261	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4262	}
4263	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4264
4265	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4266	* Overrides the guest MSRs.
4267	*/
4268	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4269
4270	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4271	* Overrides the CPUID leaf values (from the host CPU usually) used for
4272	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4273	* values when moving a VM to a different machine. Another use is restricting
4274	* (or extending) the feature set exposed to the guest. */
4275	if (RT_SUCCESS(rc))
4276	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4277
4278	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4279	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4280	"Found unsupported configuration node '/CPUM/CPUID/'. "
4281	"Please use IMachine::setCPUIDLeaf() instead.");
4282
4283	/*
4284	* Pre-explode the CPUID info.
4285	*/
4286	if (RT_SUCCESS(rc))
4287	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
4288
4289	/*
4290	* Sanitize the cpuid information passed on to the guest.
4291	*/
4292	if (RT_SUCCESS(rc))
4293	{
4294	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4295	if (RT_SUCCESS(rc))
4296	{
4297	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4298	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4299	}
4300	}
4301
4302	/*
4303	* MSR fudging.
4304	*/
4305	if (RT_SUCCESS(rc))
4306	{
4307	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4308	* Fudges some common MSRs if not present in the selected CPU database entry.
4309	* This is for trying to keep VMs running when moved between different hosts
4310	* and different CPU vendors. */
4311	bool fEnable;
4312	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4313	if (RT_SUCCESS(rc) && fEnable)
4314	{
4315	rc = cpumR3MsrApplyFudge(pVM);
4316	AssertLogRelRC(rc);
4317	}
4318	}
4319	if (RT_SUCCESS(rc))
4320	{
4321	/*
4322	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4323	* guest CPU features again.
4324	*/
4325	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4326	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4327	pCpum->GuestInfo.cCpuIdLeaves);
4328	RTMemFree(pvFree);
4329
4330	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4331	int rc2 = MMHyperDupMem(pVM, pvFree,
4332	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4333	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4334	RTMemFree(pvFree);
4335	AssertLogRelRCReturn(rc1, rc1);
4336	AssertLogRelRCReturn(rc2, rc2);
4337
4338	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4339	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4340
4341
4342	/*
4343	* Some more configuration that we're applying at the end of everything
4344	* via the CPUMSetGuestCpuIdFeature API.
4345	*/
4346
4347	/* Check if PAE was explicitely enabled by the user. */
4348	bool fEnable;
4349	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4350	AssertRCReturn(rc, rc);
4351	if (fEnable)
4352	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4353
4354	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4355	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4356	AssertRCReturn(rc, rc);
4357	if (fEnable)
4358	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4359
4360	/* Check if speculation control is enabled. */
4361	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4362	AssertRCReturn(rc, rc);
4363	if (fEnable)
4364	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4365
4366	return VINF_SUCCESS;
4367	}
4368
4369	/*
4370	* Failed before switching to hyper heap.
4371	*/
4372	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4373	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4374	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4375	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4376	return rc;
4377	}
4378
4379
4380	/**
4381	* Sets a CPUID feature bit during VM initialization.
4382	*
4383	* Since the CPUID feature bits are generally related to CPU features, other
4384	* CPUM configuration like MSRs can also be modified by calls to this API.
4385	*
4386	* @param pVM The cross context VM structure.
4387	* @param enmFeature The feature to set.
4388	*/
4389	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4390	{
4391	PCPUMCPUIDLEAF pLeaf;
4392	PCPUMMSRRANGE pMsrRange;
4393
4394	switch (enmFeature)
4395	{
4396	/*
4397	* Set the APIC bit in both feature masks.
4398	*/
4399	case CPUMCPUIDFEATURE_APIC:
4400	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4401	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4402	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4403
4404	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4405	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4406	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4407
4408	pVM->cpum.s.GuestFeatures.fApic = 1;
4409
4410	/* Make sure we've got the APICBASE MSR present. */
4411	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4412	if (!pMsrRange)
4413	{
4414	static CPUMMSRRANGE const s_ApicBase =
4415	{
4416	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4417	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4418	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4419	/.szName = / "IA32_APIC_BASE"
4420	};
4421	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4422	AssertLogRelRC(rc);
4423	}
4424
4425	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4426	break;
4427
4428	/*
4429	* Set the x2APIC bit in the standard feature mask.
4430	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4431	*/
4432	case CPUMCPUIDFEATURE_X2APIC:
4433	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4434	if (pLeaf)
4435	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4436	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4437
4438	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4439	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4440	if (pMsrRange)
4441	{
4442	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4443	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4444	}
4445
4446	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4447	break;
4448
4449	/*
4450	* Set the sysenter/sysexit bit in the standard feature mask.
4451	* Assumes the caller knows what it's doing! (host must support these)
4452	*/
4453	case CPUMCPUIDFEATURE_SEP:
4454	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4455	{
4456	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4457	return;
4458	}
4459
4460	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4461	if (pLeaf)
4462	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4463	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4464	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4465	break;
4466
4467	/*
4468	* Set the syscall/sysret bit in the extended feature mask.
4469	* Assumes the caller knows what it's doing! (host must support these)
4470	*/
4471	case CPUMCPUIDFEATURE_SYSCALL:
4472	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4473	if ( !pLeaf
4474	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4475	{
4476	#if HC_ARCH_BITS == 32
4477	/* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit
4478	mode by Intel, even when the cpu is capable of doing so in
4479	64-bit mode. Long mode requires syscall support. */
4480	if (!pVM->cpum.s.HostFeatures.fLongMode)
4481	#endif
4482	{
4483	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4484	return;
4485	}
4486	}
4487
4488	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4489	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4490	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4491	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4492	break;
4493
4494	/*
4495	* Set the PAE bit in both feature masks.
4496	* Assumes the caller knows what it's doing! (host must support these)
4497	*/
4498	case CPUMCPUIDFEATURE_PAE:
4499	if (!pVM->cpum.s.HostFeatures.fPae)
4500	{
4501	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4502	return;
4503	}
4504
4505	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4506	if (pLeaf)
4507	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4508
4509	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4510	if ( pLeaf
4511	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4512	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4513
4514	pVM->cpum.s.GuestFeatures.fPae = 1;
4515	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4516	break;
4517
4518	/*
4519	* Set the LONG MODE bit in the extended feature mask.
4520	* Assumes the caller knows what it's doing! (host must support these)
4521	*/
4522	case CPUMCPUIDFEATURE_LONG_MODE:
4523	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4524	if ( !pLeaf
4525	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4526	{
4527	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4528	return;
4529	}
4530
4531	/* Valid for both Intel and AMD. */
4532	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4533	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4534	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4535	break;
4536
4537	/*
4538	* Set the NX/XD bit in the extended feature mask.
4539	* Assumes the caller knows what it's doing! (host must support these)
4540	*/
4541	case CPUMCPUIDFEATURE_NX:
4542	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4543	if ( !pLeaf
4544	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4545	{
4546	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4547	return;
4548	}
4549
4550	/* Valid for both Intel and AMD. */
4551	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4552	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4553	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4554	break;
4555
4556
4557	/*
4558	* Set the LAHF/SAHF support in 64-bit mode.
4559	* Assumes the caller knows what it's doing! (host must support this)
4560	*/
4561	case CPUMCPUIDFEATURE_LAHF:
4562	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4563	if ( !pLeaf
4564	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4565	{
4566	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4567	return;
4568	}
4569
4570	/* Valid for both Intel and AMD. */
4571	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4572	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4573	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4574	break;
4575
4576	/*
4577	* Set the page attribute table bit. This is alternative page level
4578	* cache control that doesn't much matter when everything is
4579	* virtualized, though it may when passing thru device memory.
4580	*/
4581	case CPUMCPUIDFEATURE_PAT:
4582	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4583	if (pLeaf)
4584	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4585
4586	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4587	if ( pLeaf
4588	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4589	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4590
4591	pVM->cpum.s.GuestFeatures.fPat = 1;
4592	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4593	break;
4594
4595	/*
4596	* Set the RDTSCP support bit.
4597	* Assumes the caller knows what it's doing! (host must support this)
4598	*/
4599	case CPUMCPUIDFEATURE_RDTSCP:
4600	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4601	if ( !pLeaf
4602	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4603	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4604	{
4605	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4606	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4607	return;
4608	}
4609
4610	/* Valid for both Intel and AMD. */
4611	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4612	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4613	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4614	break;
4615
4616	/*
4617	* Set the Hypervisor Present bit in the standard feature mask.
4618	*/
4619	case CPUMCPUIDFEATURE_HVP:
4620	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4621	if (pLeaf)
4622	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4623	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4624	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4625	break;
4626
4627	/*
4628	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4629	* This currently includes the Present bit and MWAITBREAK bit as well.
4630	*/
4631	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4632	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4633	if ( !pLeaf
4634	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4635	{
4636	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4637	return;
4638	}
4639
4640	/* Valid for both Intel and AMD. */
4641	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4642	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4643	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4644	break;
4645
4646	/*
4647	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
4648	* on Intel CPUs, and different on AMDs.
4649	*/
4650	case CPUMCPUIDFEATURE_SPEC_CTRL:
4651	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4652	{
4653	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4654	if ( !pLeaf
4655	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
4656	{
4657	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4658	return;
4659	}
4660
4661	/* The feature can be enabled. Let's see what we can actually do. */
4662	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4663
4664	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4665	if (pVM->cpum.s.HostFeatures.fIbrs)
4666	{
4667	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4668	pVM->cpum.s.GuestFeatures.fIbrs = 1;
4669	if (pVM->cpum.s.HostFeatures.fStibp)
4670	{
4671	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4672	pVM->cpum.s.GuestFeatures.fStibp = 1;
4673	}
4674
4675	/* Make sure we have the speculation control MSR... */
4676	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4677	if (!pMsrRange)
4678	{
4679	static CPUMMSRRANGE const s_SpecCtrl =
4680	{
4681	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
4682	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
4683	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4684	/.szName = / "IA32_SPEC_CTRL"
4685	};
4686	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4687	AssertLogRelRC(rc);
4688	}
4689
4690	/* ... and the predictor command MSR. */
4691	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
4692	if (!pMsrRange)
4693	{
4694	static CPUMMSRRANGE const s_SpecCtrl =
4695	{
4696	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
4697	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
4698	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4699	/.szName = / "IA32_PRED_CMD"
4700	};
4701	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4702	AssertLogRelRC(rc);
4703	}
4704
4705	}
4706
4707	if (pVM->cpum.s.HostFeatures.fArchCap) {
4708	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
4709
4710	/* Install the architectural capabilities MSR. */
4711	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
4712	if (!pMsrRange)
4713	{
4714	static CPUMMSRRANGE const s_ArchCaps =
4715	{
4716	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
4717	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
4718	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
4719	/.szName = / "IA32_ARCH_CAPABILITIES"
4720	};
4721	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
4722	AssertLogRelRC(rc);
4723	}
4724	}
4725
4726	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
4727	}
4728	else if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4729	{
4730	/* The precise details of AMD's implementation are not yet clear. */
4731	}
4732	break;
4733
4734	default:
4735	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4736	break;
4737	}
4738
4739	/** @todo can probably kill this as this API is now init time only... */
4740	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4741	{
4742	PVMCPU pVCpu = &pVM->aCpus[i];
4743	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4744	}
4745	}
4746
4747
4748	/**
4749	* Queries a CPUID feature bit.
4750	*
4751	* @returns boolean for feature presence
4752	* @param pVM The cross context VM structure.
4753	* @param enmFeature The feature to query.
4754	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4755	*/
4756	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4757	{
4758	switch (enmFeature)
4759	{
4760	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4761	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4762	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4763	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4764	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4765	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4766	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4767	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4768	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4769	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4770	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4771	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4772	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
4773
4774	case CPUMCPUIDFEATURE_INVALID:
4775	case CPUMCPUIDFEATURE_32BIT_HACK:
4776	break;
4777	}
4778	AssertFailed();
4779	return false;
4780	}
4781
4782
4783	/**
4784	* Clears a CPUID feature bit.
4785	*
4786	* @param pVM The cross context VM structure.
4787	* @param enmFeature The feature to clear.
4788	*
4789	* @deprecated Probably better to default the feature to disabled and only allow
4790	* setting (enabling) it during construction.
4791	*/
4792	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4793	{
4794	PCPUMCPUIDLEAF pLeaf;
4795	switch (enmFeature)
4796	{
4797	case CPUMCPUIDFEATURE_APIC:
4798	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
4799	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4800	if (pLeaf)
4801	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
4802
4803	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4804	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4805	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4806
4807	pVM->cpum.s.GuestFeatures.fApic = 0;
4808	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4809	break;
4810
4811	case CPUMCPUIDFEATURE_X2APIC:
4812	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4813	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4814	if (pLeaf)
4815	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
4816	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
4817	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
4818	break;
4819
4820	case CPUMCPUIDFEATURE_PAE:
4821	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4822	if (pLeaf)
4823	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
4824
4825	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4826	if ( pLeaf
4827	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4828	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
4829
4830	pVM->cpum.s.GuestFeatures.fPae = 0;
4831	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
4832	break;
4833
4834	case CPUMCPUIDFEATURE_PAT:
4835	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4836	if (pLeaf)
4837	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
4838
4839	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4840	if ( pLeaf
4841	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4842	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
4843
4844	pVM->cpum.s.GuestFeatures.fPat = 0;
4845	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
4846	break;
4847
4848	case CPUMCPUIDFEATURE_LONG_MODE:
4849	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4850	if (pLeaf)
4851	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4852	pVM->cpum.s.GuestFeatures.fLongMode = 0;
4853	break;
4854
4855	case CPUMCPUIDFEATURE_LAHF:
4856	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4857	if (pLeaf)
4858	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4859	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
4860	break;
4861
4862	case CPUMCPUIDFEATURE_RDTSCP:
4863	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4864	if (pLeaf)
4865	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4866	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
4867	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
4868	break;
4869
4870	case CPUMCPUIDFEATURE_HVP:
4871	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4872	if (pLeaf)
4873	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
4874	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
4875	break;
4876
4877	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4878	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4879	if (pLeaf)
4880	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
4881	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
4882	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
4883	break;
4884
4885	case CPUMCPUIDFEATURE_SPEC_CTRL:
4886	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4887	if (pLeaf)
4888	/pVM->cpum.s.aGuestCpuIdPatmStd[7].uEdx =/ pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP \| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
4889	pVM->cpum.s.GuestFeatures.fSpeculationControl = 0;
4890	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
4891	break;
4892
4893	default:
4894	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4895	break;
4896	}
4897
4898	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4899	{
4900	PVMCPU pVCpu = &pVM->aCpus[i];
4901	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4902	}
4903	}
4904
4905
4906
4907	/*
4908	*
4909	*
4910	* Saved state related code.
4911	* Saved state related code.
4912	* Saved state related code.
4913	*
4914	*
4915	*/
4916
4917	/**
4918	* Called both in pass 0 and the final pass.
4919	*
4920	* @param pVM The cross context VM structure.
4921	* @param pSSM The saved state handle.
4922	*/
4923	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4924	{
4925	/*
4926	* Save all the CPU ID leaves.
4927	*/
4928	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4929	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4930	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4931	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4932
4933	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4934
4935	/*
4936	* Save a good portion of the raw CPU IDs as well as they may come in
4937	* handy when validating features for raw mode.
4938	*/
4939	CPUMCPUID aRawStd[16];
4940	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4941	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4942	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4943	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4944
4945	CPUMCPUID aRawExt[32];
4946	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4947	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4948	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4949	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4950	}
4951
4952
4953	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4954	{
4955	uint32_t cCpuIds;
4956	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4957	if (RT_SUCCESS(rc))
4958	{
4959	if (cCpuIds < 64)
4960	{
4961	for (uint32_t i = 0; i < cCpuIds; i++)
4962	{
4963	CPUMCPUID CpuId;
4964	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4965	if (RT_FAILURE(rc))
4966	break;
4967
4968	CPUMCPUIDLEAF NewLeaf;
4969	NewLeaf.uLeaf = uBase + i;
4970	NewLeaf.uSubLeaf = 0;
4971	NewLeaf.fSubLeafMask = 0;
4972	NewLeaf.uEax = CpuId.uEax;
4973	NewLeaf.uEbx = CpuId.uEbx;
4974	NewLeaf.uEcx = CpuId.uEcx;
4975	NewLeaf.uEdx = CpuId.uEdx;
4976	NewLeaf.fFlags = 0;
4977	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4978	}
4979	}
4980	else
4981	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4982	}
4983	if (RT_FAILURE(rc))
4984	{
4985	RTMemFree(*ppaLeaves);
4986	*ppaLeaves = NULL;
4987	*pcLeaves = 0;
4988	}
4989	return rc;
4990	}
4991
4992
4993	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4994	{
4995	*ppaLeaves = NULL;
4996	*pcLeaves = 0;
4997
4998	int rc;
4999	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
5000	{
5001	/*
5002	* The new format. Starts by declaring the leave size and count.
5003	*/
5004	uint32_t cbLeaf;
5005	SSMR3GetU32(pSSM, &cbLeaf);
5006	uint32_t cLeaves;
5007	rc = SSMR3GetU32(pSSM, &cLeaves);
5008	if (RT_SUCCESS(rc))
5009	{
5010	if (cbLeaf == sizeof(**ppaLeaves))
5011	{
5012	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
5013	{
5014	/*
5015	* Load the leaves one by one.
5016	*
5017	* The uPrev stuff is a kludge for working around a week worth of bad saved
5018	* states during the CPUID revamp in March 2015. We saved too many leaves
5019	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
5020	* garbage entires at the end of the array when restoring. We also had
5021	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
5022	* this kludge doesn't deal correctly with that, but who cares...
5023	*/
5024	uint32_t uPrev = 0;
5025	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
5026	{
5027	CPUMCPUIDLEAF Leaf;
5028	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5029	if (RT_SUCCESS(rc))
5030	{
5031	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5032	\|\| Leaf.uLeaf >= uPrev)
5033	{
5034	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5035	uPrev = Leaf.uLeaf;
5036	}
5037	else
5038	uPrev = UINT32_MAX;
5039	}
5040	}
5041	}
5042	else
5043	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5044	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5045	}
5046	else
5047	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5048	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5049	}
5050	}
5051	else
5052	{
5053	/*
5054	* The old format with its three inflexible arrays.
5055	*/
5056	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5057	if (RT_SUCCESS(rc))
5058	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5059	if (RT_SUCCESS(rc))
5060	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5061	if (RT_SUCCESS(rc))
5062	{
5063	/*
5064	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5065	*/
5066	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5067	if ( pLeaf
5068	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5069	{
5070	CPUMCPUIDLEAF Leaf;
5071	Leaf.uLeaf = 4;
5072	Leaf.fSubLeafMask = UINT32_MAX;
5073	Leaf.uSubLeaf = 0;
5074	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5075	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5076	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5077	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5078	\| UINT32_C(63); /* system coherency line size - 1 */
5079	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5080	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5081	\| (UINT32_C(1) << 5) /* cache level */
5082	\| UINT32_C(1); /* cache type (data) */
5083	Leaf.fFlags = 0;
5084	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5085	if (RT_SUCCESS(rc))
5086	{
5087	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5088	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5089	}
5090	if (RT_SUCCESS(rc))
5091	{
5092	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5093	Leaf.uEcx = 4095; /* sets - 1 */
5094	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5095	Leaf.uEbx \|= UINT32_C(23) << 22;
5096	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5097	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5098	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5099	Leaf.uEax \|= UINT32_C(2) << 5;
5100	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5101	}
5102	}
5103	}
5104	}
5105	return rc;
5106	}
5107
5108
5109	/**
5110	* Loads the CPU ID leaves saved by pass 0, inner worker.
5111	*
5112	* @returns VBox status code.
5113	* @param pVM The cross context VM structure.
5114	* @param pSSM The saved state handle.
5115	* @param uVersion The format version.
5116	* @param paLeaves Guest CPUID leaves loaded from the state.
5117	* @param cLeaves The number of leaves in @a paLeaves.
5118	*/
5119	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
5120	{
5121	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5122
5123	/*
5124	* Continue loading the state into stack buffers.
5125	*/
5126	CPUMCPUID GuestDefCpuId;
5127	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5128	AssertRCReturn(rc, rc);
5129
5130	CPUMCPUID aRawStd[16];
5131	uint32_t cRawStd;
5132	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5133	if (cRawStd > RT_ELEMENTS(aRawStd))
5134	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5135	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5136	AssertRCReturn(rc, rc);
5137	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5138	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5139
5140	CPUMCPUID aRawExt[32];
5141	uint32_t cRawExt;
5142	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5143	if (cRawExt > RT_ELEMENTS(aRawExt))
5144	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5145	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5146	AssertRCReturn(rc, rc);
5147	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5148	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5149
5150	/*
5151	* Get the raw CPU IDs for the current host.
5152	*/
5153	CPUMCPUID aHostRawStd[16];
5154	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5155	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5156
5157	CPUMCPUID aHostRawExt[32];
5158	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5159	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5160	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5161
5162	/*
5163	* Get the host and guest overrides so we don't reject the state because
5164	* some feature was enabled thru these interfaces.
5165	* Note! We currently only need the feature leaves, so skip rest.
5166	*/
5167	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5168	CPUMCPUID aHostOverrideStd[2];
5169	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5170	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5171
5172	CPUMCPUID aHostOverrideExt[2];
5173	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5174	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5175
5176	/*
5177	* This can be skipped.
5178	*/
5179	bool fStrictCpuIdChecks;
5180	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5181
5182	/*
5183	* Define a bunch of macros for simplifying the santizing/checking code below.
5184	*/
5185	/* Generic expression + failure message. */
5186	#define CPUID_CHECK_RET(expr, fmt) \
5187	do { \
5188	if (!(expr)) \
5189	{ \
5190	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5191	if (fStrictCpuIdChecks) \
5192	{ \
5193	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5194	RTStrFree(pszMsg); \
5195	return rcCpuid; \
5196	} \
5197	LogRel(("CPUM: %s\n", pszMsg)); \
5198	RTStrFree(pszMsg); \
5199	} \
5200	} while (0)
5201	#define CPUID_CHECK_WRN(expr, fmt) \
5202	do { \
5203	if (!(expr)) \
5204	LogRel(fmt); \
5205	} while (0)
5206
5207	/* For comparing two values and bitch if they differs. */
5208	#define CPUID_CHECK2_RET(what, host, saved) \
5209	do { \
5210	if ((host) != (saved)) \
5211	{ \
5212	if (fStrictCpuIdChecks) \
5213	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5214	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5215	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5216	} \
5217	} while (0)
5218	#define CPUID_CHECK2_WRN(what, host, saved) \
5219	do { \
5220	if ((host) != (saved)) \
5221	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5222	} while (0)
5223
5224	/* For checking raw cpu features (raw mode). */
5225	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5226	do { \
5227	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5228	{ \
5229	if (fStrictCpuIdChecks) \
5230	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5231	N_(#bit " mismatch: host=%d saved=%d"), \
5232	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5233	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5234	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5235	} \
5236	} while (0)
5237	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5238	do { \
5239	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5240	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5241	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5242	} while (0)
5243	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5244
5245	/* For checking guest features. */
5246	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5247	do { \
5248	if ( (aGuestCpuId##set [1].reg & bit) \
5249	&& !(aHostRaw##set [1].reg & bit) \
5250	&& !(aHostOverride##set [1].reg & bit) \
5251	) \
5252	{ \
5253	if (fStrictCpuIdChecks) \
5254	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5255	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5256	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5257	} \
5258	} while (0)
5259	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5260	do { \
5261	if ( (aGuestCpuId##set [1].reg & bit) \
5262	&& !(aHostRaw##set [1].reg & bit) \
5263	&& !(aHostOverride##set [1].reg & bit) \
5264	) \
5265	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5266	} while (0)
5267	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5268	do { \
5269	if ( (aGuestCpuId##set [1].reg & bit) \
5270	&& !(aHostRaw##set [1].reg & bit) \
5271	&& !(aHostOverride##set [1].reg & bit) \
5272	) \
5273	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5274	} while (0)
5275	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5276
5277	/* For checking guest features if AMD guest CPU. */
5278	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5279	do { \
5280	if ( (aGuestCpuId##set [1].reg & bit) \
5281	&& fGuestAmd \
5282	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5283	&& !(aHostOverride##set [1].reg & bit) \
5284	) \
5285	{ \
5286	if (fStrictCpuIdChecks) \
5287	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5288	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5289	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5290	} \
5291	} while (0)
5292	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5293	do { \
5294	if ( (aGuestCpuId##set [1].reg & bit) \
5295	&& fGuestAmd \
5296	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5297	&& !(aHostOverride##set [1].reg & bit) \
5298	) \
5299	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5300	} while (0)
5301	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5302	do { \
5303	if ( (aGuestCpuId##set [1].reg & bit) \
5304	&& fGuestAmd \
5305	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5306	&& !(aHostOverride##set [1].reg & bit) \
5307	) \
5308	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5309	} while (0)
5310	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5311
5312	/* For checking AMD features which have a corresponding bit in the standard
5313	range. (Intel defines very few bits in the extended feature sets.) */
5314	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5315	do { \
5316	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5317	&& !(fHostAmd \
5318	? aHostRawExt[1].reg & (ExtBit) \
5319	: aHostRawStd[1].reg & (StdBit)) \
5320	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5321	) \
5322	{ \
5323	if (fStrictCpuIdChecks) \
5324	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5325	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5326	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5327	} \
5328	} while (0)
5329	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5330	do { \
5331	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5332	&& !(fHostAmd \
5333	? aHostRawExt[1].reg & (ExtBit) \
5334	: aHostRawStd[1].reg & (StdBit)) \
5335	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5336	) \
5337	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5338	} while (0)
5339	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5340	do { \
5341	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5342	&& !(fHostAmd \
5343	? aHostRawExt[1].reg & (ExtBit) \
5344	: aHostRawStd[1].reg & (StdBit)) \
5345	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5346	) \
5347	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5348	} while (0)
5349	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5350
5351	/*
5352	* For raw-mode we'll require that the CPUs are very similar since we don't
5353	* intercept CPUID instructions for user mode applications.
5354	*/
5355	if (VM_IS_RAW_MODE_ENABLED(pVM))
5356	{
5357	/* CPUID(0) */
5358	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
5359	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
5360	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
5361	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5362	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
5363	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
5364	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
5365	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
5366	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5367
5368	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
5369
5370	/* CPUID(1).eax */
5371	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
5372	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
5373	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
5374
5375	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
5376	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
5377	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
5378
5379	/* CPUID(1).ecx */
5380	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
5381	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
5382	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
5383	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5384	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
5385	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
5386	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
5387	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
5388	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
5389	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
5390	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
5391	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
5392	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
5393	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
5394	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
5395	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
5396	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5397	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5398	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
5399	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
5400	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
5401	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5402	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
5403	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
5404	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5405	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
5406	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
5407	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5408	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
5409	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5410	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5411	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
5412
5413	/* CPUID(1).edx */
5414	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5415	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5416	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
5417	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5418	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
5419	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
5420	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5421	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5422	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
5423	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5424	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5425	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5426	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5427	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5428	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5429	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
5430	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5431	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5432	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5433	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
5434	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5435	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
5436	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
5437	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
5438	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
5439	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
5440	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
5441	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
5442	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
5443	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
5444	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
5445	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
5446
5447	/* CPUID(2) - config, mostly about caches. ignore. */
5448	/* CPUID(3) - processor serial number. ignore. */
5449	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
5450	/* CPUID(5) - mwait/monitor config. ignore. */
5451	/* CPUID(6) - power management. ignore. */
5452	/* CPUID(7) - ???. ignore. */
5453	/* CPUID(8) - ???. ignore. */
5454	/* CPUID(9) - DCA. ignore for now. */
5455	/* CPUID(a) - PeMo info. ignore for now. */
5456	/* CPUID(b) - topology info - takes ECX as input. ignore. */
5457
5458	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
5459	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
5460	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
5461	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
5462	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
5463	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
5464	{
5465	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
5466	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
5467	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
5468	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
5469	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
5470	}
5471
5472	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
5473	Note! Intel have/is marking many of the fields here as reserved. We
5474	will verify them as if it's an AMD CPU. */
5475	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
5476	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
5477	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
5478	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
5479	{
5480	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
5481	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
5482	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
5483	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5484	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
5485	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
5486	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
5487
5488	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
5489	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
5490	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
5491	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
5492	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
5493	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5494
5495	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
5496	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
5497	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
5498	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
5499
5500	/* CPUID(0x80000001).ecx */
5501	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
5502	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
5503	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
5504	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
5505	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
5506	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
5507	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
5508	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
5509	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
5510	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
5511	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
5512	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
5513	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
5514	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
5515	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5516	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5517	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5518	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5519	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5520	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5521	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5522	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5523	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5524	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5525	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5526	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5527	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5528	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5529	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5530	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5531	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5532	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5533
5534	/* CPUID(0x80000001).edx */
5535	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
5536	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
5537	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
5538	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
5539	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
5540	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
5541	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
5542	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
5543	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
5544	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
5545	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5546	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
5547	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
5548	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
5549	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
5550	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
5551	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
5552	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
5553	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5554	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5555	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5556	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
5557	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5558	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
5559	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
5560	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5561	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5562	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5563	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
5564	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5565	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5566	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5567
5568	/** @todo verify the rest as well. */
5569	}
5570	}
5571
5572
5573
5574	/*
5575	* Verify that we can support the features already exposed to the guest on
5576	* this host.
5577	*
5578	* Most of the features we're emulating requires intercepting instruction
5579	* and doing it the slow way, so there is no need to warn when they aren't
5580	* present in the host CPU. Thus we use IGN instead of EMU on these.
5581	*
5582	* Trailing comments:
5583	* "EMU" - Possible to emulate, could be lots of work and very slow.
5584	* "EMU?" - Can this be emulated?
5585	*/
5586	CPUMCPUID aGuestCpuIdStd[2];
5587	RT_ZERO(aGuestCpuIdStd);
5588	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5589
5590	/* CPUID(1).ecx */
5591	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5592	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5593	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5594	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5595	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5596	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5597	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5598	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5599	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5600	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5601	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5602	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5603	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5604	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5605	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5606	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5607	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5608	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5609	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5610	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5611	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5612	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5613	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5614	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5615	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5616	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5617	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5618	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5619	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5620	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5621	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5622	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5623
5624	/* CPUID(1).edx */
5625	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5626	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5627	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5628	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5629	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5630	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5631	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5632	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5633	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5634	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5635	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5636	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5637	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5638	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5639	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5640	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5641	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5642	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5643	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5644	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5645	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5646	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5647	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5648	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5649	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5650	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5651	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5652	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5653	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5654	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5655	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5656	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5657
5658	/* CPUID(0x80000000). */
5659	CPUMCPUID aGuestCpuIdExt[2];
5660	RT_ZERO(aGuestCpuIdExt);
5661	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5662	{
5663	/** @todo deal with no 0x80000001 on the host. */
5664	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5665	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5666
5667	/* CPUID(0x80000001).ecx */
5668	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5669	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5670	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5671	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5672	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5673	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5674	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5675	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5676	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5677	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5678	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5679	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5680	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5681	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5682	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5683	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5684	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5685	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5686	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5687	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5688	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5689	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5690	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5691	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5692	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5693	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5694	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5695	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5696	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5697	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5698	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5699	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5700
5701	/* CPUID(0x80000001).edx */
5702	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5703	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5704	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5705	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5706	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5707	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5708	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5709	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5710	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5711	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5712	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5713	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5714	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5715	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5716	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5717	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5718	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5719	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5720	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5721	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5722	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5723	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5724	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5725	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5726	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5727	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5728	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5729	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5730	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5731	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5732	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5733	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5734	}
5735
5736	/** @todo check leaf 7 */
5737
5738	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5739	* ECX=0: EAX - Valid bits in XCR0[31:0].
5740	* EBX - Maximum state size as per current XCR0 value.
5741	* ECX - Maximum state size for all supported features.
5742	* EDX - Valid bits in XCR0[63:32].
5743	* ECX=1: EAX - Various X-features.
5744	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5745	* ECX - Valid bits in IA32_XSS[31:0].
5746	* EDX - Valid bits in IA32_XSS[63:32].
5747	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5748	* if the bit invalid all four registers are set to zero.
5749	* EAX - The state size for this feature.
5750	* EBX - The state byte offset of this feature.
5751	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5752	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5753	*/
5754	uint64_t fGuestXcr0Mask = 0;
5755	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5756	if ( pCurLeaf
5757	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5758	&& ( pCurLeaf->uEax
5759	\|\| pCurLeaf->uEbx
5760	\|\| pCurLeaf->uEcx
5761	\|\| pCurLeaf->uEdx) )
5762	{
5763	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5764	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5765	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5766	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5767	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5768	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5769	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5770	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5771
5772	/* We don't support any additional features yet. */
5773	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5774	if (pCurLeaf && pCurLeaf->uEax)
5775	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5776	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5777	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5778	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5779	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5780	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5781
5782
5783	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5784	{
5785	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5786	if (pCurLeaf)
5787	{
5788	/* If advertised, the state component offset and size must match the one used by host. */
5789	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5790	{
5791	CPUMCPUID RawHost;
5792	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5793	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5794	if ( RawHost.uEbx != pCurLeaf->uEbx
5795	\|\| RawHost.uEax != pCurLeaf->uEax)
5796	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5797	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5798	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5799	}
5800	}
5801	}
5802	}
5803	/* Clear leaf 0xd just in case we're loading an old state... */
5804	else if (pCurLeaf)
5805	{
5806	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5807	{
5808	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5809	if (pCurLeaf)
5810	{
5811	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5812	\|\| ( pCurLeaf->uEax == 0
5813	&& pCurLeaf->uEbx == 0
5814	&& pCurLeaf->uEcx == 0
5815	&& pCurLeaf->uEdx == 0),
5816	("uVersion=%#x; %#x %#x %#x %#x\n",
5817	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5818	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5819	}
5820	}
5821	}
5822
5823	/* Update the fXStateGuestMask value for the VM. */
5824	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5825	{
5826	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5827	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5828	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5829	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5830	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5831	}
5832
5833	#undef CPUID_CHECK_RET
5834	#undef CPUID_CHECK_WRN
5835	#undef CPUID_CHECK2_RET
5836	#undef CPUID_CHECK2_WRN
5837	#undef CPUID_RAW_FEATURE_RET
5838	#undef CPUID_RAW_FEATURE_WRN
5839	#undef CPUID_RAW_FEATURE_IGN
5840	#undef CPUID_GST_FEATURE_RET
5841	#undef CPUID_GST_FEATURE_WRN
5842	#undef CPUID_GST_FEATURE_EMU
5843	#undef CPUID_GST_FEATURE_IGN
5844	#undef CPUID_GST_FEATURE2_RET
5845	#undef CPUID_GST_FEATURE2_WRN
5846	#undef CPUID_GST_FEATURE2_EMU
5847	#undef CPUID_GST_FEATURE2_IGN
5848	#undef CPUID_GST_AMD_FEATURE_RET
5849	#undef CPUID_GST_AMD_FEATURE_WRN
5850	#undef CPUID_GST_AMD_FEATURE_EMU
5851	#undef CPUID_GST_AMD_FEATURE_IGN
5852
5853	/*
5854	* We're good, commit the CPU ID leaves.
5855	*/
5856	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5857	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5858	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5859	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
5860	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5861	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
5862	AssertLogRelRCReturn(rc, rc);
5863
5864	return VINF_SUCCESS;
5865	}
5866
5867
5868	/**
5869	* Loads the CPU ID leaves saved by pass 0.
5870	*
5871	* @returns VBox status code.
5872	* @param pVM The cross context VM structure.
5873	* @param pSSM The saved state handle.
5874	* @param uVersion The format version.
5875	*/
5876	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5877	{
5878	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5879
5880	/*
5881	* Load the CPUID leaves array first and call worker to do the rest, just so
5882	* we can free the memory when we need to without ending up in column 1000.
5883	*/
5884	PCPUMCPUIDLEAF paLeaves;
5885	uint32_t cLeaves;
5886	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5887	AssertRC(rc);
5888	if (RT_SUCCESS(rc))
5889	{
5890	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
5891	RTMemFree(paLeaves);
5892	}
5893	return rc;
5894	}
5895
5896
5897
5898	/**
5899	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5900	*
5901	* @returns VBox status code.
5902	* @param pVM The cross context VM structure.
5903	* @param pSSM The saved state handle.
5904	* @param uVersion The format version.
5905	*/
5906	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5907	{
5908	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5909
5910	/*
5911	* Restore the CPUID leaves.
5912	*
5913	* Note that we support restoring less than the current amount of standard
5914	* leaves because we've been allowed more is newer version of VBox.
5915	*/
5916	uint32_t cElements;
5917	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5918	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5919	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5920	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5921
5922	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5923	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5924	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5925	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5926
5927	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5928	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5929	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5930	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5931
5932	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5933
5934	/*
5935	* Check that the basic cpuid id information is unchanged.
5936	*/
5937	/** @todo we should check the 64 bits capabilities too! */
5938	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5939	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5940	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5941	uint32_t au32CpuIdSaved[8];
5942	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5943	if (RT_SUCCESS(rc))
5944	{
5945	/* Ignore CPU stepping. */
5946	au32CpuId[4] &= 0xfffffff0;
5947	au32CpuIdSaved[4] &= 0xfffffff0;
5948
5949	/* Ignore APIC ID (AMD specs). */
5950	au32CpuId[5] &= ~0xff000000;
5951	au32CpuIdSaved[5] &= ~0xff000000;
5952
5953	/* Ignore the number of Logical CPUs (AMD specs). */
5954	au32CpuId[5] &= ~0x00ff0000;
5955	au32CpuIdSaved[5] &= ~0x00ff0000;
5956
5957	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5958	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5959	\| X86_CPUID_FEATURE_ECX_VMX
5960	\| X86_CPUID_FEATURE_ECX_SMX
5961	\| X86_CPUID_FEATURE_ECX_EST
5962	\| X86_CPUID_FEATURE_ECX_TM2
5963	\| X86_CPUID_FEATURE_ECX_CNTXID
5964	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5965	\| X86_CPUID_FEATURE_ECX_PDCM
5966	\| X86_CPUID_FEATURE_ECX_DCA
5967	\| X86_CPUID_FEATURE_ECX_X2APIC
5968	);
5969	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5970	\| X86_CPUID_FEATURE_ECX_VMX
5971	\| X86_CPUID_FEATURE_ECX_SMX
5972	\| X86_CPUID_FEATURE_ECX_EST
5973	\| X86_CPUID_FEATURE_ECX_TM2
5974	\| X86_CPUID_FEATURE_ECX_CNTXID
5975	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5976	\| X86_CPUID_FEATURE_ECX_PDCM
5977	\| X86_CPUID_FEATURE_ECX_DCA
5978	\| X86_CPUID_FEATURE_ECX_X2APIC
5979	);
5980
5981	/* Make sure we don't forget to update the masks when enabling
5982	* features in the future.
5983	*/
5984	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5985	( X86_CPUID_FEATURE_ECX_DTES64
5986	\| X86_CPUID_FEATURE_ECX_VMX
5987	\| X86_CPUID_FEATURE_ECX_SMX
5988	\| X86_CPUID_FEATURE_ECX_EST
5989	\| X86_CPUID_FEATURE_ECX_TM2
5990	\| X86_CPUID_FEATURE_ECX_CNTXID
5991	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5992	\| X86_CPUID_FEATURE_ECX_PDCM
5993	\| X86_CPUID_FEATURE_ECX_DCA
5994	\| X86_CPUID_FEATURE_ECX_X2APIC
5995	)));
5996	/* do the compare */
5997	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5998	{
5999	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
6000	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
6001	"Saved=%.*Rhxs\n"
6002	"Real =%.*Rhxs\n",
6003	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6004	sizeof(au32CpuId), au32CpuId));
6005	else
6006	{
6007	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
6008	"Saved=%.*Rhxs\n"
6009	"Real =%.*Rhxs\n",
6010	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6011	sizeof(au32CpuId), au32CpuId));
6012	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
6013	}
6014	}
6015	}
6016
6017	return rc;
6018	}
6019
6020
6021
6022	/*
6023	*
6024	*
6025	* CPUID Info Handler.
6026	* CPUID Info Handler.
6027	* CPUID Info Handler.
6028	*
6029	*
6030	*/
6031
6032
6033
6034	/**
6035	* Get L1 cache / TLS associativity.
6036	*/
6037	static const char getCacheAss(unsigned u, char pszBuf)
6038	{
6039	if (u == 0)
6040	return "res0 ";
6041	if (u == 1)
6042	return "direct";
6043	if (u == 255)
6044	return "fully";
6045	if (u >= 256)
6046	return "???";
6047
6048	RTStrPrintf(pszBuf, 16, "%d way", u);
6049	return pszBuf;
6050	}
6051
6052
6053	/**
6054	* Get L2 cache associativity.
6055	*/
6056	const char *getL2CacheAss(unsigned u)
6057	{
6058	switch (u)
6059	{
6060	case 0: return "off ";
6061	case 1: return "direct";
6062	case 2: return "2 way ";
6063	case 3: return "res3 ";
6064	case 4: return "4 way ";
6065	case 5: return "res5 ";
6066	case 6: return "8 way ";
6067	case 7: return "res7 ";
6068	case 8: return "16 way";
6069	case 9: return "res9 ";
6070	case 10: return "res10 ";
6071	case 11: return "res11 ";
6072	case 12: return "res12 ";
6073	case 13: return "res13 ";
6074	case 14: return "res14 ";
6075	case 15: return "fully ";
6076	default: return "????";
6077	}
6078	}
6079
6080
6081	/** CPUID(1).EDX field descriptions. */
6082	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6083	{
6084	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6085	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6086	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6087	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6088	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6089	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6090	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6091	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6092	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6093	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6094	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6095	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6096	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6097	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6098	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6099	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6100	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6101	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6102	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6103	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6104	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6105	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6106	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6107	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6108	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6109	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6110	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6111	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6112	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6113	DBGFREGSUBFIELD_TERMINATOR()
6114	};
6115
6116	/** CPUID(1).ECX field descriptions. */
6117	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6118	{
6119	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6120	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6121	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6122	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6123	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6124	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6125	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6126	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6127	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6128	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6129	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6130	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6131	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6132	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6133	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6134	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6135	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6136	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6137	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6138	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6139	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6140	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6141	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6142	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6143	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6144	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6145	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6146	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6147	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6148	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6149	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6150	DBGFREGSUBFIELD_TERMINATOR()
6151	};
6152
6153	/** CPUID(7,0).EBX field descriptions. */
6154	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6155	{
6156	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6157	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6158	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6159	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6160	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6161	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6162	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6163	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6164	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6165	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6166	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6167	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6168	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6169	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6170	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6171	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6172	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6173	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6174	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6175	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6176	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6177	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6178	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6179	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6180	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6181	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6182	DBGFREGSUBFIELD_TERMINATOR()
6183	};
6184
6185	/** CPUID(7,0).ECX field descriptions. */
6186	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6187	{
6188	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6189	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6190	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6191	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6192	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6193	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6194	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6195	DBGFREGSUBFIELD_TERMINATOR()
6196	};
6197
6198	/** CPUID(7,0).EDX field descriptions. */
6199	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6200	{
6201	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6202	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6203	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6204	DBGFREGSUBFIELD_TERMINATOR()
6205	};
6206
6207
6208	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6209	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6210	{
6211	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6212	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6213	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6214	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6215	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6216	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6217	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6218	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6219	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6220	DBGFREGSUBFIELD_TERMINATOR()
6221	};
6222
6223	/** CPUID(13,1).EAX field descriptions. */
6224	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6225	{
6226	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6227	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6228	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6229	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6230	DBGFREGSUBFIELD_TERMINATOR()
6231	};
6232
6233
6234	/** CPUID(0x80000001,0).EDX field descriptions. */
6235	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6236	{
6237	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6238	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6239	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6240	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6241	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6242	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6243	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6244	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6245	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6246	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6247	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6248	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6249	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6250	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6251	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6252	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6253	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6254	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6255	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6256	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6257	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6258	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6259	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6260	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6261	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6262	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6263	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6264	DBGFREGSUBFIELD_TERMINATOR()
6265	};
6266
6267	/** CPUID(0x80000001,0).ECX field descriptions. */
6268	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6269	{
6270	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6271	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6272	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6273	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6274	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6275	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6276	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6277	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6278	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6279	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6280	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6281	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6282	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6283	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6284	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6285	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6286	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6287	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6288	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6289	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6290	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6291	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6292	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6293	DBGFREGSUBFIELD_TERMINATOR()
6294	};
6295
6296	/** CPUID(0x8000000a,0).EDX field descriptions. */
6297	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6298	{
6299	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6300	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6301	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6302	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6303	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6304	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6305	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6306	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6307	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6308	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6309	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6310	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6311	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6312	DBGFREGSUBFIELD_TERMINATOR()
6313	};
6314
6315
6316	/** CPUID(0x80000007,0).EDX field descriptions. */
6317	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6318	{
6319	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6320	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6321	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6322	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6323	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6324	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6325	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6326	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6327	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6328	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6329	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6330	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6331	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6332	DBGFREGSUBFIELD_TERMINATOR()
6333	};
6334
6335	/** CPUID(0x80000008,0).EBX field descriptions. */
6336	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6337	{
6338	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6339	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6340	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6341	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6342	DBGFREGSUBFIELD_TERMINATOR()
6343	};
6344
6345
6346	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6347	const char *pszLeadIn, uint32_t cchWidth)
6348	{
6349	if (pszLeadIn)
6350	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6351
6352	for (uint32_t iBit = 0; iBit < 32; iBit++)
6353	if (RT_BIT_32(iBit) & uVal)
6354	{
6355	while ( pDesc->pszName != NULL
6356	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6357	pDesc++;
6358	if ( pDesc->pszName != NULL
6359	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6360	{
6361	if (pDesc->cBits == 1)
6362	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6363	else
6364	{
6365	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6366	if (pDesc->cBits < 32)
6367	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6368	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6369	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6370	}
6371	}
6372	else
6373	pHlp->pfnPrintf(pHlp, " %u", iBit);
6374	}
6375	if (pszLeadIn)
6376	pHlp->pfnPrintf(pHlp, "\n");
6377	}
6378
6379
6380	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6381	const char *pszLeadIn, uint32_t cchWidth)
6382	{
6383	if (pszLeadIn)
6384	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6385
6386	for (uint32_t iBit = 0; iBit < 64; iBit++)
6387	if (RT_BIT_64(iBit) & uVal)
6388	{
6389	while ( pDesc->pszName != NULL
6390	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6391	pDesc++;
6392	if ( pDesc->pszName != NULL
6393	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6394	{
6395	if (pDesc->cBits == 1)
6396	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6397	else
6398	{
6399	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6400	if (pDesc->cBits < 64)
6401	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6402	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6403	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6404	}
6405	}
6406	else
6407	pHlp->pfnPrintf(pHlp, " %u", iBit);
6408	}
6409	if (pszLeadIn)
6410	pHlp->pfnPrintf(pHlp, "\n");
6411	}
6412
6413
6414	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6415	const char *pszLeadIn, uint32_t cchWidth)
6416	{
6417	if (!uVal)
6418	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6419	else
6420	{
6421	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6422	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6423	pHlp->pfnPrintf(pHlp, " )\n");
6424	}
6425	}
6426
6427
6428	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6429	uint32_t cchWidth)
6430	{
6431	uint32_t uCombined = uVal1 \| uVal2;
6432	for (uint32_t iBit = 0; iBit < 32; iBit++)
6433	if ( (RT_BIT_32(iBit) & uCombined)
6434	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6435	{
6436	while ( pDesc->pszName != NULL
6437	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6438	pDesc++;
6439
6440	if ( pDesc->pszName != NULL
6441	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6442	{
6443	size_t cchMnemonic = strlen(pDesc->pszName);
6444	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6445	size_t cchDesc = strlen(pszDesc);
6446	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6447	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6448	if (pDesc->cBits < 32)
6449	{
6450	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6451	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6452	}
6453
6454	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6455	pDesc->pszName, pszDesc,
6456	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6457	uFieldValue1, uFieldValue2);
6458
6459	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6460	pDesc++;
6461	}
6462	else
6463	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6464	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6465	}
6466	}
6467
6468
6469	/**
6470	* Produces a detailed summary of standard leaf 0x00000001.
6471	*
6472	* @param pHlp The info helper functions.
6473	* @param pCurLeaf The 0x00000001 leaf.
6474	* @param fVerbose Whether to be very verbose or not.
6475	* @param fIntel Set if intel CPU.
6476	*/
6477	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6478	{
6479	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6480	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6481	uint32_t uEAX = pCurLeaf->uEax;
6482	uint32_t uEBX = pCurLeaf->uEbx;
6483
6484	pHlp->pfnPrintf(pHlp,
6485	"%36s %2d \tExtended: %d \tEffective: %d\n"
6486	"%36s %2d \tExtended: %d \tEffective: %d\n"
6487	"%36s %d\n"
6488	"%36s %d (%s)\n"
6489	"%36s %#04x\n"
6490	"%36s %d\n"
6491	"%36s %d\n"
6492	"%36s %#04x\n"
6493	,
6494	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6495	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6496	"Stepping:", ASMGetCpuStepping(uEAX),
6497	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6498	"APIC ID:", (uEBX >> 24) & 0xff,
6499	"Logical CPUs:",(uEBX >> 16) & 0xff,
6500	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6501	"Brand ID:", (uEBX >> 0) & 0xff);
6502	if (fVerbose)
6503	{
6504	CPUMCPUID Host;
6505	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6506	pHlp->pfnPrintf(pHlp, "Features\n");
6507	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6508	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6509	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6510	}
6511	else
6512	{
6513	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6514	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6515	}
6516	}
6517
6518
6519	/**
6520	* Produces a detailed summary of standard leaf 0x00000007.
6521	*
6522	* @param pHlp The info helper functions.
6523	* @param paLeaves The CPUID leaves array.
6524	* @param cLeaves The number of leaves in the array.
6525	* @param pCurLeaf The first 0x00000007 leaf.
6526	* @param fVerbose Whether to be very verbose or not.
6527	*/
6528	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6529	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6530	{
6531	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6532	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6533	for (;;)
6534	{
6535	CPUMCPUID Host;
6536	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6537
6538	switch (pCurLeaf->uSubLeaf)
6539	{
6540	case 0:
6541	if (fVerbose)
6542	{
6543	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6544	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6545	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6546	if (pCurLeaf->uEdx \|\| Host.uEdx)
6547	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6548	}
6549	else
6550	{
6551	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6552	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6553	if (pCurLeaf->uEdx)
6554	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6555	}
6556	break;
6557
6558	default:
6559	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6560	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6561	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6562	break;
6563
6564	}
6565
6566	/* advance. */
6567	pCurLeaf++;
6568	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6569	\|\| pCurLeaf->uLeaf != 0x7)
6570	break;
6571	}
6572	}
6573
6574
6575	/**
6576	* Produces a detailed summary of standard leaf 0x0000000d.
6577	*
6578	* @param pHlp The info helper functions.
6579	* @param paLeaves The CPUID leaves array.
6580	* @param cLeaves The number of leaves in the array.
6581	* @param pCurLeaf The first 0x00000007 leaf.
6582	* @param fVerbose Whether to be very verbose or not.
6583	*/
6584	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6585	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6586	{
6587	RT_NOREF_PV(fVerbose);
6588	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6589	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6590	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6591	{
6592	CPUMCPUID Host;
6593	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6594
6595	switch (uSubLeaf)
6596	{
6597	case 0:
6598	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6599	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6600	pCurLeaf->uEbx, pCurLeaf->uEcx);
6601	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6602
6603	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6604	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6605	"Valid XCR0 bits, guest:", 42);
6606	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6607	"Valid XCR0 bits, host:", 42);
6608	break;
6609
6610	case 1:
6611	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6612	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6613	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6614
6615	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6616	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6617	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6618
6619	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6620	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6621	" Valid IA32_XSS bits, guest:", 42);
6622	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6623	" Valid IA32_XSS bits, host:", 42);
6624	break;
6625
6626	default:
6627	if ( pCurLeaf
6628	&& pCurLeaf->uSubLeaf == uSubLeaf
6629	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6630	{
6631	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6632	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6633	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6634	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6635	if (pCurLeaf->uEdx)
6636	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6637	pHlp->pfnPrintf(pHlp, " --");
6638	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6639	pHlp->pfnPrintf(pHlp, "\n");
6640	}
6641	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6642	{
6643	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6644	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6645	if (Host.uEcx & ~RT_BIT_32(0))
6646	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6647	if (Host.uEdx)
6648	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6649	pHlp->pfnPrintf(pHlp, " --");
6650	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6651	pHlp->pfnPrintf(pHlp, "\n");
6652	}
6653	break;
6654
6655	}
6656
6657	/* advance. */
6658	if (pCurLeaf)
6659	{
6660	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6661	&& pCurLeaf->uSubLeaf <= uSubLeaf
6662	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6663	pCurLeaf++;
6664	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6665	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6666	pCurLeaf = NULL;
6667	}
6668	}
6669	}
6670
6671
6672	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6673	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6674	{
6675	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6676	&& pCurLeaf->uLeaf <= uUpToLeaf)
6677	{
6678	pHlp->pfnPrintf(pHlp,
6679	" %s\n"
6680	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6681	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6682	&& pCurLeaf->uLeaf <= uUpToLeaf)
6683	{
6684	CPUMCPUID Host;
6685	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6686	pHlp->pfnPrintf(pHlp,
6687	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6688	"Hst: %08x %08x %08x %08x\n",
6689	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6690	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6691	pCurLeaf++;
6692	}
6693	}
6694
6695	return pCurLeaf;
6696	}
6697
6698
6699	/**
6700	* Display the guest CpuId leaves.
6701	*
6702	* @param pVM The cross context VM structure.
6703	* @param pHlp The info helper functions.
6704	* @param pszArgs "terse", "default" or "verbose".
6705	*/
6706	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6707	{
6708	/*
6709	* Parse the argument.
6710	*/
6711	unsigned iVerbosity = 1;
6712	if (pszArgs)
6713	{
6714	pszArgs = RTStrStripL(pszArgs);
6715	if (!strcmp(pszArgs, "terse"))
6716	iVerbosity--;
6717	else if (!strcmp(pszArgs, "verbose"))
6718	iVerbosity++;
6719	}
6720
6721	uint32_t uLeaf;
6722	CPUMCPUID Host;
6723	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6724	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6725	PCCPUMCPUIDLEAF pCurLeaf;
6726	PCCPUMCPUIDLEAF pNextLeaf;
6727	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6728	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6729	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6730
6731	/*
6732	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6733	*/
6734	uint32_t cHstMax = ASMCpuId_EAX(0);
6735	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6736	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6737	pHlp->pfnPrintf(pHlp,
6738	" Raw Standard CPUID Leaves\n"
6739	" Leaf/sub-leaf eax ebx ecx edx\n");
6740	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6741	{
6742	uint32_t cMaxSubLeaves = 1;
6743	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6744	cMaxSubLeaves = 16;
6745	else if (uLeaf == 0xd)
6746	cMaxSubLeaves = 128;
6747
6748	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6749	{
6750	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6751	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6752	&& pCurLeaf->uLeaf == uLeaf
6753	&& pCurLeaf->uSubLeaf == uSubLeaf)
6754	{
6755	pHlp->pfnPrintf(pHlp,
6756	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6757	"Hst: %08x %08x %08x %08x\n",
6758	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6759	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6760	pCurLeaf++;
6761	}
6762	else if ( uLeaf != 0xd
6763	\|\| uSubLeaf <= 1
6764	\|\| Host.uEbx != 0 )
6765	pHlp->pfnPrintf(pHlp,
6766	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6767	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6768
6769	/* Done? */
6770	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6771	\|\| pCurLeaf->uLeaf != uLeaf)
6772	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6773	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6774	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6775	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6776	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6777	)
6778	)
6779	break;
6780	}
6781	}
6782	pNextLeaf = pCurLeaf;
6783
6784	/*
6785	* If verbose, decode it.
6786	*/
6787	if (iVerbosity && paLeaves[0].uLeaf == 0)
6788	pHlp->pfnPrintf(pHlp,
6789	"%36s %.04s%.04s%.04s\n"
6790	"%36s 0x00000000-%#010x\n"
6791	,
6792	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6793	"Supports:", paLeaves[0].uEax);
6794
6795	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6796	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6797
6798	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6799	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6800
6801	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6802	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6803
6804	pCurLeaf = pNextLeaf;
6805
6806	/*
6807	* Hypervisor leaves.
6808	*
6809	* Unlike most of the other leaves reported, the guest hypervisor leaves
6810	* aren't a subset of the host CPUID bits.
6811	*/
6812	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6813
6814	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6815	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6816	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6817	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6818	cMax = RT_MAX(cHstMax, cGstMax);
6819	if (cMax >= UINT32_C(0x40000000))
6820	{
6821	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6822
6823	/** @todo dump these in more detail. */
6824
6825	pCurLeaf = pNextLeaf;
6826	}
6827
6828
6829	/*
6830	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6831	* Implemented after AMD specs.
6832	*/
6833	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6834
6835	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6836	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6837	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6838	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6839	cMax = RT_MAX(cHstMax, cGstMax);
6840	if (cMax >= UINT32_C(0x80000000))
6841	{
6842
6843	pHlp->pfnPrintf(pHlp,
6844	" Raw Extended CPUID Leaves\n"
6845	" Leaf/sub-leaf eax ebx ecx edx\n");
6846	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6847	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6848	{
6849	uint32_t cMaxSubLeaves = 1;
6850	if (uLeaf == UINT32_C(0x8000001d))
6851	cMaxSubLeaves = 16;
6852
6853	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6854	{
6855	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6856	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6857	&& pCurLeaf->uLeaf == uLeaf
6858	&& pCurLeaf->uSubLeaf == uSubLeaf)
6859	{
6860	pHlp->pfnPrintf(pHlp,
6861	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6862	"Hst: %08x %08x %08x %08x\n",
6863	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6864	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6865	pCurLeaf++;
6866	}
6867	else if ( uLeaf != 0xd
6868	\|\| uSubLeaf <= 1
6869	\|\| Host.uEbx != 0 )
6870	pHlp->pfnPrintf(pHlp,
6871	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6872	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6873
6874	/* Done? */
6875	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6876	\|\| pCurLeaf->uLeaf != uLeaf)
6877	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6878	break;
6879	}
6880	}
6881	pNextLeaf = pCurLeaf;
6882
6883	/*
6884	* Understandable output
6885	*/
6886	if (iVerbosity)
6887	pHlp->pfnPrintf(pHlp,
6888	"Ext Name: %.4s%.4s%.4s\n"
6889	"Ext Supports: 0x80000000-%#010x\n",
6890	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6891
6892	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6893	if (iVerbosity && pCurLeaf)
6894	{
6895	uint32_t uEAX = pCurLeaf->uEax;
6896	pHlp->pfnPrintf(pHlp,
6897	"Family: %d \tExtended: %d \tEffective: %d\n"
6898	"Model: %d \tExtended: %d \tEffective: %d\n"
6899	"Stepping: %d\n"
6900	"Brand ID: %#05x\n",
6901	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6902	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6903	ASMGetCpuStepping(uEAX),
6904	pCurLeaf->uEbx & 0xfff);
6905
6906	if (iVerbosity == 1)
6907	{
6908	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6909	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6910	}
6911	else
6912	{
6913	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6914	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6915	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6916	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6917	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6918	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
6919	{
6920	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
6921	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6922	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
6923	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
6924	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
6925	}
6926	}
6927	}
6928
6929	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6930	{
6931	char szString[443+1] = {0};
6932	uint32_t pu32 = (uint32_t )szString;
6933	*pu32++ = pCurLeaf->uEax;
6934	*pu32++ = pCurLeaf->uEbx;
6935	*pu32++ = pCurLeaf->uEcx;
6936	*pu32++ = pCurLeaf->uEdx;
6937	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6938	if (pCurLeaf)
6939	{
6940	*pu32++ = pCurLeaf->uEax;
6941	*pu32++ = pCurLeaf->uEbx;
6942	*pu32++ = pCurLeaf->uEcx;
6943	*pu32++ = pCurLeaf->uEdx;
6944	}
6945	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6946	if (pCurLeaf)
6947	{
6948	*pu32++ = pCurLeaf->uEax;
6949	*pu32++ = pCurLeaf->uEbx;
6950	*pu32++ = pCurLeaf->uEcx;
6951	*pu32++ = pCurLeaf->uEdx;
6952	}
6953	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6954	}
6955
6956	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6957	{
6958	uint32_t uEAX = pCurLeaf->uEax;
6959	uint32_t uEBX = pCurLeaf->uEbx;
6960	uint32_t uECX = pCurLeaf->uEcx;
6961	uint32_t uEDX = pCurLeaf->uEdx;
6962	char sz1[32];
6963	char sz2[32];
6964
6965	pHlp->pfnPrintf(pHlp,
6966	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6967	"TLB 2/4M Data: %s %3d entries\n",
6968	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6969	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6970	pHlp->pfnPrintf(pHlp,
6971	"TLB 4K Instr/Uni: %s %3d entries\n"
6972	"TLB 4K Data: %s %3d entries\n",
6973	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6974	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6975	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6976	"L1 Instr Cache Lines Per Tag: %d\n"
6977	"L1 Instr Cache Associativity: %s\n"
6978	"L1 Instr Cache Size: %d KB\n",
6979	(uEDX >> 0) & 0xff,
6980	(uEDX >> 8) & 0xff,
6981	getCacheAss((uEDX >> 16) & 0xff, sz1),
6982	(uEDX >> 24) & 0xff);
6983	pHlp->pfnPrintf(pHlp,
6984	"L1 Data Cache Line Size: %d bytes\n"
6985	"L1 Data Cache Lines Per Tag: %d\n"
6986	"L1 Data Cache Associativity: %s\n"
6987	"L1 Data Cache Size: %d KB\n",
6988	(uECX >> 0) & 0xff,
6989	(uECX >> 8) & 0xff,
6990	getCacheAss((uECX >> 16) & 0xff, sz1),
6991	(uECX >> 24) & 0xff);
6992	}
6993
6994	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6995	{
6996	uint32_t uEAX = pCurLeaf->uEax;
6997	uint32_t uEBX = pCurLeaf->uEbx;
6998	uint32_t uEDX = pCurLeaf->uEdx;
6999
7000	pHlp->pfnPrintf(pHlp,
7001	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
7002	"L2 TLB 2/4M Data: %s %4d entries\n",
7003	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
7004	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
7005	pHlp->pfnPrintf(pHlp,
7006	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
7007	"L2 TLB 4K Data: %s %4d entries\n",
7008	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
7009	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
7010	pHlp->pfnPrintf(pHlp,
7011	"L2 Cache Line Size: %d bytes\n"
7012	"L2 Cache Lines Per Tag: %d\n"
7013	"L2 Cache Associativity: %s\n"
7014	"L2 Cache Size: %d KB\n",
7015	(uEDX >> 0) & 0xff,
7016	(uEDX >> 8) & 0xf,
7017	getL2CacheAss((uEDX >> 12) & 0xf),
7018	(uEDX >> 16) & 0xffff);
7019	}
7020
7021	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
7022	{
7023	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7024	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
7025	{
7026	if (iVerbosity < 1)
7027	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7028	else
7029	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7030	}
7031	}
7032
7033	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7034	if (pCurLeaf != NULL)
7035	{
7036	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7037	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7038	{
7039	if (iVerbosity < 1)
7040	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7041	else
7042	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7043	}
7044
7045	if (iVerbosity)
7046	{
7047	uint32_t uEAX = pCurLeaf->uEax;
7048	uint32_t uECX = pCurLeaf->uEcx;
7049
7050	pHlp->pfnPrintf(pHlp,
7051	"Physical Address Width: %d bits\n"
7052	"Virtual Address Width: %d bits\n"
7053	"Guest Physical Address Width: %d bits\n",
7054	(uEAX >> 0) & 0xff,
7055	(uEAX >> 8) & 0xff,
7056	(uEAX >> 16) & 0xff);
7057	pHlp->pfnPrintf(pHlp,
7058	"Physical Core Count: %d\n",
7059	((uECX >> 0) & 0xff) + 1);
7060	}
7061	}
7062
7063	pCurLeaf = pNextLeaf;
7064	}
7065
7066
7067
7068	/*
7069	* Centaur.
7070	*/
7071	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7072
7073	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7074	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7075	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7076	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7077	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7078	cMax = RT_MAX(cHstMax, cGstMax);
7079	if (cMax >= UINT32_C(0xc0000000))
7080	{
7081	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7082
7083	/*
7084	* Understandable output
7085	*/
7086	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7087	pHlp->pfnPrintf(pHlp,
7088	"Centaur Supports: 0xc0000000-%#010x\n",
7089	pCurLeaf->uEax);
7090
7091	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7092	{
7093	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7094	uint32_t uEdxGst = pCurLeaf->uEdx;
7095	uint32_t uEdxHst = Host.uEdx;
7096
7097	if (iVerbosity == 1)
7098	{
7099	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7100	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7101	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7102	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7103	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7104	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7105	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7106	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7107	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7108	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7109	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7110	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7111	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7112	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7113	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7114	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7115	for (unsigned iBit = 14; iBit < 32; iBit++)
7116	if (uEdxGst & RT_BIT(iBit))
7117	pHlp->pfnPrintf(pHlp, " %d", iBit);
7118	pHlp->pfnPrintf(pHlp, "\n");
7119	}
7120	else
7121	{
7122	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7123	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7124	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7125	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7126	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7127	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7128	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7129	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7130	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7131	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7132	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7133	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7134	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7135	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7136	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7137	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7138	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7139	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7140	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7141	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7142	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7143	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7144	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7145	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7146	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7147	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7148	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7149	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7150	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7151	for (unsigned iBit = 27; iBit < 32; iBit++)
7152	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7153	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7154	pHlp->pfnPrintf(pHlp, "\n");
7155	}
7156	}
7157
7158	pCurLeaf = pNextLeaf;
7159	}
7160
7161	/*
7162	* The remainder.
7163	*/
7164	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7165	}
7166
7167
7168
7169
7170
7171	/*
7172	*
7173	*
7174	* PATM interfaces.
7175	* PATM interfaces.
7176	* PATM interfaces.
7177	*
7178	*
7179	*/
7180
7181
7182	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
7183	/** @name Patchmanager CPUID legacy table APIs
7184	* @{
7185	*/
7186
7187	/**
7188	* Gets a pointer to the default CPUID leaf.
7189	*
7190	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
7191	* @param pVM The cross context VM structure.
7192	* @remark Intended for PATM only.
7193	*/
7194	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
7195	{
7196	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
7197	}
7198
7199
7200	/**
7201	* Gets a number of standard CPUID leaves (PATM only).
7202	*
7203	* @returns Number of leaves.
7204	* @param pVM The cross context VM structure.
7205	* @remark Intended for PATM - legacy, don't use in new code.
7206	*/
7207	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
7208	{
7209	RT_NOREF_PV(pVM);
7210	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
7211	}
7212
7213
7214	/**
7215	* Gets a number of extended CPUID leaves (PATM only).
7216	*
7217	* @returns Number of leaves.
7218	* @param pVM The cross context VM structure.
7219	* @remark Intended for PATM - legacy, don't use in new code.
7220	*/
7221	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
7222	{
7223	RT_NOREF_PV(pVM);
7224	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
7225	}
7226
7227
7228	/**
7229	* Gets a number of centaur CPUID leaves.
7230	*
7231	* @returns Number of leaves.
7232	* @param pVM The cross context VM structure.
7233	* @remark Intended for PATM - legacy, don't use in new code.
7234	*/
7235	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
7236	{
7237	RT_NOREF_PV(pVM);
7238	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
7239	}
7240
7241
7242	/**
7243	* Gets a pointer to the array of standard CPUID leaves.
7244	*
7245	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
7246	*
7247	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
7248	* @param pVM The cross context VM structure.
7249	* @remark Intended for PATM - legacy, don't use in new code.
7250	*/
7251	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
7252	{
7253	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
7254	}
7255
7256
7257	/**
7258	* Gets a pointer to the array of extended CPUID leaves.
7259	*
7260	* CPUMGetGuestCpuIdExtMax() give the size of the array.
7261	*
7262	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
7263	* @param pVM The cross context VM structure.
7264	* @remark Intended for PATM - legacy, don't use in new code.
7265	*/
7266	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
7267	{
7268	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
7269	}
7270
7271
7272	/**
7273	* Gets a pointer to the array of centaur CPUID leaves.
7274	*
7275	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
7276	*
7277	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
7278	* @param pVM The cross context VM structure.
7279	* @remark Intended for PATM - legacy, don't use in new code.
7280	*/
7281	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
7282	{
7283	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
7284	}
7285
7286	/** @} */
7287	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
7288
7289	#endif /* VBOX_IN_VMM */
7290

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 74168

Download in other formats: