CPUMR3CpuId.cpp@ 76886

Last change on this file since 76886 was 76886, checked in by vboxsync, 6 years ago
VMM (and related changes): Add support for Shanghai/Zhaoxin CPUs. Modified and improved contribution by Journey Ren submitted under MIT license. Thank you!
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 348.7 KB

Line
1	/* $Id: CPUMR3CpuId.cpp 76886 2019-01-18 10:57:02Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/mm.h>
31	#include <VBox/sup.h>
32
33	#include <VBox/err.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/ctype.h>
36	#include <iprt/mem.h>
37	#include <iprt/string.h>
38
39
40	/*********************************************************************************************************************************
41	* Defined Constants And Macros *
42	*********************************************************************************************************************************/
43	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
44	#define CPUM_CPUID_MAX_LEAVES 2048
45	/* Max size we accept for the XSAVE area. */
46	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
47	/* Min size we accept for the XSAVE area. */
48	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
49
50
51	/*********************************************************************************************************************************
52	* Global Variables *
53	*********************************************************************************************************************************/
54	/**
55	* The intel pentium family.
56	*/
57	static const CPUMMICROARCH g_aenmIntelFamily06[] =
58	{
59	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
60	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
61	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
63	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
64	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
65	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
66	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
67	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
68	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
69	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
70	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
71	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
72	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
73	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
74	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
75	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
81	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
82	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
83	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
86	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
88	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
89	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
90	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
91	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
97	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
98	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
99	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
102	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
104	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
105	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
106	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
107	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
113	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
114	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
115	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
118	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
121	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
122	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
130	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
131	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
136	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [78(0x4e)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed */
138	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / unconfirmed, Broadwell-E */
139	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu */
145	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
146	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
147	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
150	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
152	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
153	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
154	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
155	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
159	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
160	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
161	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
162	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
163	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
164	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
165	/[106(0x6a)] = / kCpumMicroarch_Intel_Unknown,
166	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
167	/[108(0x6c)] = / kCpumMicroarch_Intel_Unknown,
168	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
169	/[110(0x6e)] = / kCpumMicroarch_Intel_Unknown,
170	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
171	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
172	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
173	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
174	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
175	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
176	/[117(0x75)] = / kCpumMicroarch_Intel_Unknown,
177	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
178	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
179	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
180	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
181	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
182	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
183	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
184	/[125(0x7d)] = / kCpumMicroarch_Intel_Unknown,
185	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
186	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
187	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
188	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
189	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
190	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
191	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
192	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
193	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
194	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
195	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
196	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
197	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
198	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
199	/[140(0x8c)] = / kCpumMicroarch_Intel_Unknown,
200	/[141(0x8d)] = / kCpumMicroarch_Intel_Unknown,
201	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
202	/[143(0x8f)] = / kCpumMicroarch_Intel_Unknown,
203	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
204	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
205	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
206	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
207	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
208	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
209	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
210	/[151(0x97)] = / kCpumMicroarch_Intel_Unknown,
211	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
212	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
213	/[154(0x9a)] = / kCpumMicroarch_Intel_Unknown,
214	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
215	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
216	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
217	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
218	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
219	};
220	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0x9f+1);
221
222
223	/**
224	* Figures out the (sub-)micro architecture given a bit of CPUID info.
225	*
226	* @returns Micro architecture.
227	* @param enmVendor The CPU vendor .
228	* @param bFamily The CPU family.
229	* @param bModel The CPU model.
230	* @param bStepping The CPU stepping.
231	*/
232	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
233	uint8_t bModel, uint8_t bStepping)
234	{
235	if (enmVendor == CPUMCPUVENDOR_AMD)
236	{
237	switch (bFamily)
238	{
239	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
240	case 0x03: return kCpumMicroarch_AMD_Am386;
241	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
242	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
243	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
244	case 0x06:
245	switch (bModel)
246	{
247	case 0: return kCpumMicroarch_AMD_K7_Palomino;
248	case 1: return kCpumMicroarch_AMD_K7_Palomino;
249	case 2: return kCpumMicroarch_AMD_K7_Palomino;
250	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
251	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
252	case 6: return kCpumMicroarch_AMD_K7_Palomino;
253	case 7: return kCpumMicroarch_AMD_K7_Morgan;
254	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
255	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
256	}
257	return kCpumMicroarch_AMD_K7_Unknown;
258	case 0x0f:
259	/*
260	* This family is a friggin mess. Trying my best to make some
261	* sense out of it. Too much happened in the 0x0f family to
262	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
263	*
264	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
265	* cpu-world.com, and other places:
266	* - 130nm:
267	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
268	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
269	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
270	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
271	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
272	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
273	* - 90nm:
274	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
275	* - Oakville: 10FC0/DH-D0.
276	* - Georgetown: 10FC0/DH-D0.
277	* - Sonora: 10FC0/DH-D0.
278	* - Venus: 20F71/SH-E4
279	* - Troy: 20F51/SH-E4
280	* - Athens: 20F51/SH-E4
281	* - San Diego: 20F71/SH-E4.
282	* - Lancaster: 20F42/SH-E5
283	* - Newark: 20F42/SH-E5.
284	* - Albany: 20FC2/DH-E6.
285	* - Roma: 20FC2/DH-E6.
286	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
287	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
288	* - 90nm introducing Dual core:
289	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
290	* - Italy: 20F10/JH-E1, 20F12/JH-E6
291	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
292	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
293	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
294	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
295	* - Santa Ana: 40F32/JH-F2, /-F3
296	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
297	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
298	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
299	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
300	* - Keene: 40FC2/DH-F2.
301	* - Richmond: 40FC2/DH-F2
302	* - Taylor: 40F82/BH-F2
303	* - Trinidad: 40F82/BH-F2
304	*
305	* - 65nm:
306	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
307	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
308	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
309	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
310	* - Sherman: /-G1, 70FC2/DH-G2.
311	* - Huron: 70FF2/DH-G2.
312	*/
313	if (bModel < 0x10)
314	return kCpumMicroarch_AMD_K8_130nm;
315	if (bModel >= 0x60 && bModel < 0x80)
316	return kCpumMicroarch_AMD_K8_65nm;
317	if (bModel >= 0x40)
318	return kCpumMicroarch_AMD_K8_90nm_AMDV;
319	switch (bModel)
320	{
321	case 0x21:
322	case 0x23:
323	case 0x2b:
324	case 0x2f:
325	case 0x37:
326	case 0x3f:
327	return kCpumMicroarch_AMD_K8_90nm_DualCore;
328	}
329	return kCpumMicroarch_AMD_K8_90nm;
330	case 0x10:
331	return kCpumMicroarch_AMD_K10;
332	case 0x11:
333	return kCpumMicroarch_AMD_K10_Lion;
334	case 0x12:
335	return kCpumMicroarch_AMD_K10_Llano;
336	case 0x14:
337	return kCpumMicroarch_AMD_Bobcat;
338	case 0x15:
339	switch (bModel)
340	{
341	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
342	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
343	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
344	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
345	case 0x11: /* ?? */
346	case 0x12: /* ?? */
347	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
348	}
349	return kCpumMicroarch_AMD_15h_Unknown;
350	case 0x16:
351	return kCpumMicroarch_AMD_Jaguar;
352	case 0x17:
353	return kCpumMicroarch_AMD_Zen_Ryzen;
354	}
355	return kCpumMicroarch_AMD_Unknown;
356	}
357
358	if (enmVendor == CPUMCPUVENDOR_INTEL)
359	{
360	switch (bFamily)
361	{
362	case 3:
363	return kCpumMicroarch_Intel_80386;
364	case 4:
365	return kCpumMicroarch_Intel_80486;
366	case 5:
367	return kCpumMicroarch_Intel_P5;
368	case 6:
369	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
370	{
371	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
372	if ( enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake
373	&& bStepping >= 0xa)
374	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
375	return enmMicroArch;
376	}
377	return kCpumMicroarch_Intel_Atom_Unknown;
378	case 15:
379	switch (bModel)
380	{
381	case 0: return kCpumMicroarch_Intel_NB_Willamette;
382	case 1: return kCpumMicroarch_Intel_NB_Willamette;
383	case 2: return kCpumMicroarch_Intel_NB_Northwood;
384	case 3: return kCpumMicroarch_Intel_NB_Prescott;
385	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
386	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
387	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
388	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
389	default: return kCpumMicroarch_Intel_NB_Unknown;
390	}
391	break;
392	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
393	case 0:
394	return kCpumMicroarch_Intel_8086;
395	case 1:
396	return kCpumMicroarch_Intel_80186;
397	case 2:
398	return kCpumMicroarch_Intel_80286;
399	}
400	return kCpumMicroarch_Intel_Unknown;
401	}
402
403	if (enmVendor == CPUMCPUVENDOR_VIA)
404	{
405	switch (bFamily)
406	{
407	case 5:
408	switch (bModel)
409	{
410	case 1: return kCpumMicroarch_Centaur_C6;
411	case 4: return kCpumMicroarch_Centaur_C6;
412	case 8: return kCpumMicroarch_Centaur_C2;
413	case 9: return kCpumMicroarch_Centaur_C3;
414	}
415	break;
416
417	case 6:
418	switch (bModel)
419	{
420	case 5: return kCpumMicroarch_VIA_C3_M2;
421	case 6: return kCpumMicroarch_VIA_C3_C5A;
422	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
423	case 8: return kCpumMicroarch_VIA_C3_C5N;
424	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
425	case 10: return kCpumMicroarch_VIA_C7_C5J;
426	case 15: return kCpumMicroarch_VIA_Isaiah;
427	}
428	break;
429	}
430	return kCpumMicroarch_VIA_Unknown;
431	}
432
433	if (enmVendor == CPUMCPUVENDOR_SHANGHAI)
434	{
435	switch (bFamily)
436	{
437	case 6:
438	case 7:
439	return kCpumMicroarch_Shanghai_Wudaokou;
440	default:
441	break;
442	}
443	return kCpumMicroarch_Shanghai_Unknown;
444	}
445
446	if (enmVendor == CPUMCPUVENDOR_CYRIX)
447	{
448	switch (bFamily)
449	{
450	case 4:
451	switch (bModel)
452	{
453	case 9: return kCpumMicroarch_Cyrix_5x86;
454	}
455	break;
456
457	case 5:
458	switch (bModel)
459	{
460	case 2: return kCpumMicroarch_Cyrix_M1;
461	case 4: return kCpumMicroarch_Cyrix_MediaGX;
462	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
463	}
464	break;
465
466	case 6:
467	switch (bModel)
468	{
469	case 0: return kCpumMicroarch_Cyrix_M2;
470	}
471	break;
472
473	}
474	return kCpumMicroarch_Cyrix_Unknown;
475	}
476
477	return kCpumMicroarch_Unknown;
478	}
479
480
481	/**
482	* Translates a microarchitecture enum value to the corresponding string
483	* constant.
484	*
485	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
486	* NULL if the value is invalid.
487	*
488	* @param enmMicroarch The enum value to convert.
489	*/
490	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
491	{
492	switch (enmMicroarch)
493	{
494	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
495	CASE_RET_STR(kCpumMicroarch_Intel_8086);
496	CASE_RET_STR(kCpumMicroarch_Intel_80186);
497	CASE_RET_STR(kCpumMicroarch_Intel_80286);
498	CASE_RET_STR(kCpumMicroarch_Intel_80386);
499	CASE_RET_STR(kCpumMicroarch_Intel_80486);
500	CASE_RET_STR(kCpumMicroarch_Intel_P5);
501
502	CASE_RET_STR(kCpumMicroarch_Intel_P6);
503	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
504	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
505
506	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
507	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
508	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
509
510	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
511	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
512
513	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
514	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
515	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
516	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
517	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
518	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
519	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
520	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
521	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
522	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
523	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
524	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
525
526	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
527	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
528	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
529	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
530	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
531	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
532	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
533	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
534
535	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
536	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
537	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
538	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
539	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
540
541	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
542	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
543	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
544	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
545	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
546	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
547	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
548
549	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
550
551	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
552	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
553	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
554	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
555	CASE_RET_STR(kCpumMicroarch_AMD_K5);
556	CASE_RET_STR(kCpumMicroarch_AMD_K6);
557
558	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
559	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
560	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
561	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
562	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
563	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
564	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
565
566	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
567	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
568	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
569	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
570	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
571
572	CASE_RET_STR(kCpumMicroarch_AMD_K10);
573	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
574	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
575	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
576	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
577
578	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
579	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
580	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
581	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
582	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
583
584	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
585
586	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
587
588	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
589
590	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
591	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
592	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
593	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
594	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
595	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
596	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
597	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
598	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
599	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
600	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
601	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
602	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
603
604	CASE_RET_STR(kCpumMicroarch_Shanghai_Wudaokou);
605	CASE_RET_STR(kCpumMicroarch_Shanghai_Unknown);
606
607	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
608	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
609	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
610	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
611	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
612	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
613
614	CASE_RET_STR(kCpumMicroarch_NEC_V20);
615	CASE_RET_STR(kCpumMicroarch_NEC_V30);
616
617	CASE_RET_STR(kCpumMicroarch_Unknown);
618
619	#undef CASE_RET_STR
620	case kCpumMicroarch_Invalid:
621	case kCpumMicroarch_Intel_End:
622	case kCpumMicroarch_Intel_Core2_End:
623	case kCpumMicroarch_Intel_Core7_End:
624	case kCpumMicroarch_Intel_Atom_End:
625	case kCpumMicroarch_Intel_P6_Core_Atom_End:
626	case kCpumMicroarch_Intel_Phi_End:
627	case kCpumMicroarch_Intel_NB_End:
628	case kCpumMicroarch_AMD_K7_End:
629	case kCpumMicroarch_AMD_K8_End:
630	case kCpumMicroarch_AMD_15h_End:
631	case kCpumMicroarch_AMD_16h_End:
632	case kCpumMicroarch_AMD_Zen_End:
633	case kCpumMicroarch_AMD_End:
634	case kCpumMicroarch_VIA_End:
635	case kCpumMicroarch_Cyrix_End:
636	case kCpumMicroarch_NEC_End:
637	case kCpumMicroarch_Shanghai_End:
638	case kCpumMicroarch_32BitHack:
639	break;
640	/* no default! */
641	}
642
643	return NULL;
644	}
645
646
647	/**
648	* Determins the host CPU MXCSR mask.
649	*
650	* @returns MXCSR mask.
651	*/
652	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
653	{
654	if ( ASMHasCpuId()
655	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
656	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
657	{
658	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
659	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
660	RT_ZERO(*pState);
661	ASMFxSave(pState);
662	if (pState->MXCSR_MASK == 0)
663	return 0xffbf;
664	return pState->MXCSR_MASK;
665	}
666	return 0;
667	}
668
669
670	/**
671	* Gets a matching leaf in the CPUID leaf array.
672	*
673	* @returns Pointer to the matching leaf, or NULL if not found.
674	* @param paLeaves The CPUID leaves to search. This is sorted.
675	* @param cLeaves The number of leaves in the array.
676	* @param uLeaf The leaf to locate.
677	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
678	*/
679	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
680	{
681	/* Lazy bird does linear lookup here since this is only used for the
682	occational CPUID overrides. */
683	for (uint32_t i = 0; i < cLeaves; i++)
684	if ( paLeaves[i].uLeaf == uLeaf
685	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
686	return &paLeaves[i];
687	return NULL;
688	}
689
690
691	#ifndef IN_VBOX_CPU_REPORT
692	/**
693	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
694	*
695	* @returns true if found, false it not.
696	* @param paLeaves The CPUID leaves to search. This is sorted.
697	* @param cLeaves The number of leaves in the array.
698	* @param uLeaf The leaf to locate.
699	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
700	* @param pLegacy The legacy output leaf.
701	*/
702	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
703	PCPUMCPUID pLegacy)
704	{
705	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
706	if (pLeaf)
707	{
708	pLegacy->uEax = pLeaf->uEax;
709	pLegacy->uEbx = pLeaf->uEbx;
710	pLegacy->uEcx = pLeaf->uEcx;
711	pLegacy->uEdx = pLeaf->uEdx;
712	return true;
713	}
714	return false;
715	}
716	#endif /* IN_VBOX_CPU_REPORT */
717
718
719	/**
720	* Ensures that the CPUID leaf array can hold one more leaf.
721	*
722	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
723	* failure.
724	* @param pVM The cross context VM structure. If NULL, use
725	* the process heap, otherwise the VM's hyper heap.
726	* @param ppaLeaves Pointer to the variable holding the array pointer
727	* (input/output).
728	* @param cLeaves The current array size.
729	*
730	* @remarks This function will automatically update the R0 and RC pointers when
731	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
732	* be the corresponding VM's CPUID arrays (which is asserted).
733	*/
734	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
735	{
736	/*
737	* If pVM is not specified, we're on the regular heap and can waste a
738	* little space to speed things up.
739	*/
740	uint32_t cAllocated;
741	if (!pVM)
742	{
743	cAllocated = RT_ALIGN(cLeaves, 16);
744	if (cLeaves + 1 > cAllocated)
745	{
746	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
747	if (pvNew)
748	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
749	else
750	{
751	RTMemFree(*ppaLeaves);
752	*ppaLeaves = NULL;
753	}
754	}
755	}
756	/*
757	* Otherwise, we're on the hyper heap and are probably just inserting
758	* one or two leaves and should conserve space.
759	*/
760	else
761	{
762	#ifdef IN_VBOX_CPU_REPORT
763	AssertReleaseFailed();
764	#else
765	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
766	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
767
768	size_t cb = cLeaves * sizeof(**ppaLeaves);
769	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
770	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
771	if (RT_SUCCESS(rc))
772	{
773	/* Update the R0 and RC pointers. */
774	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
775	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
776	}
777	else
778	{
779	*ppaLeaves = NULL;
780	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
781	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
782	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
783	}
784	#endif
785	}
786	return *ppaLeaves;
787	}
788
789
790	/**
791	* Append a CPUID leaf or sub-leaf.
792	*
793	* ASSUMES linear insertion order, so we'll won't need to do any searching or
794	* replace anything. Use cpumR3CpuIdInsert() for those cases.
795	*
796	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
797	* the caller need do no more work.
798	* @param ppaLeaves Pointer to the pointer to the array of sorted
799	* CPUID leaves and sub-leaves.
800	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
801	* @param uLeaf The leaf we're adding.
802	* @param uSubLeaf The sub-leaf number.
803	* @param fSubLeafMask The sub-leaf mask.
804	* @param uEax The EAX value.
805	* @param uEbx The EBX value.
806	* @param uEcx The ECX value.
807	* @param uEdx The EDX value.
808	* @param fFlags The flags.
809	*/
810	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
811	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
812	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
813	{
814	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
815	return VERR_NO_MEMORY;
816
817	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
818	Assert( *pcLeaves == 0
819	\|\| pNew[-1].uLeaf < uLeaf
820	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
821
822	pNew->uLeaf = uLeaf;
823	pNew->uSubLeaf = uSubLeaf;
824	pNew->fSubLeafMask = fSubLeafMask;
825	pNew->uEax = uEax;
826	pNew->uEbx = uEbx;
827	pNew->uEcx = uEcx;
828	pNew->uEdx = uEdx;
829	pNew->fFlags = fFlags;
830
831	*pcLeaves += 1;
832	return VINF_SUCCESS;
833	}
834
835
836	/**
837	* Checks that we've updated the CPUID leaves array correctly.
838	*
839	* This is a no-op in non-strict builds.
840	*
841	* @param paLeaves The leaves array.
842	* @param cLeaves The number of leaves.
843	*/
844	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
845	{
846	#ifdef VBOX_STRICT
847	for (uint32_t i = 1; i < cLeaves; i++)
848	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
849	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
850	else
851	{
852	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
853	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
854	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
855	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
856	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
857	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
858	}
859	#else
860	NOREF(paLeaves);
861	NOREF(cLeaves);
862	#endif
863	}
864
865
866	/**
867	* Inserts a CPU ID leaf, replacing any existing ones.
868	*
869	* When inserting a simple leaf where we already got a series of sub-leaves with
870	* the same leaf number (eax), the simple leaf will replace the whole series.
871	*
872	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
873	* host-context heap and has only been allocated/reallocated by the
874	* cpumR3CpuIdEnsureSpace function.
875	*
876	* @returns VBox status code.
877	* @param pVM The cross context VM structure. If NULL, use
878	* the process heap, otherwise the VM's hyper heap.
879	* @param ppaLeaves Pointer to the pointer to the array of sorted
880	* CPUID leaves and sub-leaves. Must be NULL if using
881	* the hyper heap.
882	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
883	* be NULL if using the hyper heap.
884	* @param pNewLeaf Pointer to the data of the new leaf we're about to
885	* insert.
886	*/
887	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
888	{
889	/*
890	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
891	*/
892	if (pVM)
893	{
894	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
895	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
896
897	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
898	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
899	}
900
901	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
902	uint32_t cLeaves = *pcLeaves;
903
904	/*
905	* Validate the new leaf a little.
906	*/
907	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
908	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
909	VERR_INVALID_FLAGS);
910	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
911	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
912	VERR_INVALID_PARAMETER);
913	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
914	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
915	VERR_INVALID_PARAMETER);
916	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
917	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
918	VERR_INVALID_PARAMETER);
919
920	/*
921	* Find insertion point. The lazy bird uses the same excuse as in
922	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
923	*/
924	uint32_t i;
925	if ( cLeaves > 0
926	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
927	{
928	/* Add at end. */
929	i = cLeaves;
930	}
931	else if ( cLeaves > 0
932	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
933	{
934	/* Either replacing the last leaf or dealing with sub-leaves. Spool
935	back to the first sub-leaf to pretend we did the linear search. */
936	i = cLeaves - 1;
937	while ( i > 0
938	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
939	i--;
940	}
941	else
942	{
943	/* Linear search from the start. */
944	i = 0;
945	while ( i < cLeaves
946	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
947	i++;
948	}
949	if ( i < cLeaves
950	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
951	{
952	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
953	{
954	/*
955	* The sub-leaf mask differs, replace all existing leaves with the
956	* same leaf number.
957	*/
958	uint32_t c = 1;
959	while ( i + c < cLeaves
960	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
961	c++;
962	if (c > 1 && i + c < cLeaves)
963	{
964	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
965	*pcLeaves = cLeaves -= c - 1;
966	}
967
968	paLeaves[i] = *pNewLeaf;
969	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
970	return VINF_SUCCESS;
971	}
972
973	/* Find sub-leaf insertion point. */
974	while ( i < cLeaves
975	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
976	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
977	i++;
978
979	/*
980	* If we've got an exactly matching leaf, replace it.
981	*/
982	if ( i < cLeaves
983	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
984	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
985	{
986	paLeaves[i] = *pNewLeaf;
987	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
988	return VINF_SUCCESS;
989	}
990	}
991
992	/*
993	* Adding a new leaf at 'i'.
994	*/
995	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
996	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
997	if (!paLeaves)
998	return VERR_NO_MEMORY;
999
1000	if (i < cLeaves)
1001	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
1002	*pcLeaves += 1;
1003	paLeaves[i] = *pNewLeaf;
1004
1005	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1006	return VINF_SUCCESS;
1007	}
1008
1009
1010	#ifndef IN_VBOX_CPU_REPORT
1011	/**
1012	* Removes a range of CPUID leaves.
1013	*
1014	* This will not reallocate the array.
1015	*
1016	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1017	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1018	* @param uFirst The first leaf.
1019	* @param uLast The last leaf.
1020	*/
1021	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1022	{
1023	uint32_t cLeaves = *pcLeaves;
1024
1025	Assert(uFirst <= uLast);
1026
1027	/*
1028	* Find the first one.
1029	*/
1030	uint32_t iFirst = 0;
1031	while ( iFirst < cLeaves
1032	&& paLeaves[iFirst].uLeaf < uFirst)
1033	iFirst++;
1034
1035	/*
1036	* Find the end (last + 1).
1037	*/
1038	uint32_t iEnd = iFirst;
1039	while ( iEnd < cLeaves
1040	&& paLeaves[iEnd].uLeaf <= uLast)
1041	iEnd++;
1042
1043	/*
1044	* Adjust the array if anything needs removing.
1045	*/
1046	if (iFirst < iEnd)
1047	{
1048	if (iEnd < cLeaves)
1049	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1050	*pcLeaves = cLeaves -= (iEnd - iFirst);
1051	}
1052
1053	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1054	}
1055	#endif /* IN_VBOX_CPU_REPORT */
1056
1057
1058	/**
1059	* Checks if ECX make a difference when reading a given CPUID leaf.
1060	*
1061	* @returns @c true if it does, @c false if it doesn't.
1062	* @param uLeaf The leaf we're reading.
1063	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1064	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1065	* final sub-leaf (for leaf 0xb only).
1066	*/
1067	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1068	{
1069	*pfFinalEcxUnchanged = false;
1070
1071	uint32_t auCur[4];
1072	uint32_t auPrev[4];
1073	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1074
1075	/* Look for sub-leaves. */
1076	uint32_t uSubLeaf = 1;
1077	for (;;)
1078	{
1079	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1080	if (memcmp(auCur, auPrev, sizeof(auCur)))
1081	break;
1082
1083	/* Advance / give up. */
1084	uSubLeaf++;
1085	if (uSubLeaf >= 64)
1086	{
1087	*pcSubLeaves = 1;
1088	return false;
1089	}
1090	}
1091
1092	/* Count sub-leaves. */
1093	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1094	uint32_t cRepeats = 0;
1095	uSubLeaf = 0;
1096	for (;;)
1097	{
1098	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1099
1100	/* Figuring out when to stop isn't entirely straight forward as we need
1101	to cover undocumented behavior up to a point and implementation shortcuts. */
1102
1103	/* 1. Look for more than 4 repeating value sets. */
1104	if ( auCur[0] == auPrev[0]
1105	&& auCur[1] == auPrev[1]
1106	&& ( auCur[2] == auPrev[2]
1107	\|\| ( auCur[2] == uSubLeaf
1108	&& auPrev[2] == uSubLeaf - 1) )
1109	&& auCur[3] == auPrev[3])
1110	{
1111	if ( uLeaf != 0xd
1112	\|\| uSubLeaf >= 64
1113	\|\| ( auCur[0] == 0
1114	&& auCur[1] == 0
1115	&& auCur[2] == 0
1116	&& auCur[3] == 0
1117	&& auPrev[2] == 0) )
1118	cRepeats++;
1119	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1120	break;
1121	}
1122	else
1123	cRepeats = 0;
1124
1125	/* 2. Look for zero values. */
1126	if ( auCur[0] == 0
1127	&& auCur[1] == 0
1128	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1129	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1130	&& uSubLeaf >= cMinLeaves)
1131	{
1132	cRepeats = 0;
1133	break;
1134	}
1135
1136	/* 3. Leaf 0xb level type 0 check. */
1137	if ( uLeaf == 0xb
1138	&& (auCur[2] & 0xff00) == 0
1139	&& (auPrev[2] & 0xff00) == 0)
1140	{
1141	cRepeats = 0;
1142	break;
1143	}
1144
1145	/* 99. Give up. */
1146	if (uSubLeaf >= 128)
1147	{
1148	#ifndef IN_VBOX_CPU_REPORT
1149	/* Ok, limit it according to the documentation if possible just to
1150	avoid annoying users with these detection issues. */
1151	uint32_t cDocLimit = UINT32_MAX;
1152	if (uLeaf == 0x4)
1153	cDocLimit = 4;
1154	else if (uLeaf == 0x7)
1155	cDocLimit = 1;
1156	else if (uLeaf == 0xd)
1157	cDocLimit = 63;
1158	else if (uLeaf == 0xf)
1159	cDocLimit = 2;
1160	if (cDocLimit != UINT32_MAX)
1161	{
1162	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1163	*pcSubLeaves = cDocLimit + 3;
1164	return true;
1165	}
1166	#endif
1167	*pcSubLeaves = UINT32_MAX;
1168	return true;
1169	}
1170
1171	/* Advance. */
1172	uSubLeaf++;
1173	memcpy(auPrev, auCur, sizeof(auCur));
1174	}
1175
1176	/* Standard exit. */
1177	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1178	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1179	if (*pcSubLeaves == 0)
1180	*pcSubLeaves = 1;
1181	return true;
1182	}
1183
1184
1185	/**
1186	* Gets a CPU ID leaf.
1187	*
1188	* @returns VBox status code.
1189	* @param pVM The cross context VM structure.
1190	* @param pLeaf Where to store the found leaf.
1191	* @param uLeaf The leaf to locate.
1192	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1193	*/
1194	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1195	{
1196	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1197	uLeaf, uSubLeaf);
1198	if (pcLeaf)
1199	{
1200	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1201	return VINF_SUCCESS;
1202	}
1203
1204	return VERR_NOT_FOUND;
1205	}
1206
1207
1208	/**
1209	* Inserts a CPU ID leaf, replacing any existing ones.
1210	*
1211	* @returns VBox status code.
1212	* @param pVM The cross context VM structure.
1213	* @param pNewLeaf Pointer to the leaf being inserted.
1214	*/
1215	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1216	{
1217	/*
1218	* Validate parameters.
1219	*/
1220	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1221	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1222
1223	/*
1224	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1225	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1226	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1227	*/
1228	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1229	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1230	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1231	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1232	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1233	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1234	{
1235	return VERR_NOT_SUPPORTED;
1236	}
1237
1238	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1239	}
1240
1241	/**
1242	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1243	*
1244	* @returns VBox status code.
1245	* @param ppaLeaves Where to return the array pointer on success.
1246	* Use RTMemFree to release.
1247	* @param pcLeaves Where to return the size of the array on
1248	* success.
1249	*/
1250	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1251	{
1252	*ppaLeaves = NULL;
1253	*pcLeaves = 0;
1254
1255	/*
1256	* Try out various candidates. This must be sorted!
1257	*/
1258	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1259	{
1260	{ UINT32_C(0x00000000), false },
1261	{ UINT32_C(0x10000000), false },
1262	{ UINT32_C(0x20000000), false },
1263	{ UINT32_C(0x30000000), false },
1264	{ UINT32_C(0x40000000), false },
1265	{ UINT32_C(0x50000000), false },
1266	{ UINT32_C(0x60000000), false },
1267	{ UINT32_C(0x70000000), false },
1268	{ UINT32_C(0x80000000), false },
1269	{ UINT32_C(0x80860000), false },
1270	{ UINT32_C(0x8ffffffe), true },
1271	{ UINT32_C(0x8fffffff), true },
1272	{ UINT32_C(0x90000000), false },
1273	{ UINT32_C(0xa0000000), false },
1274	{ UINT32_C(0xb0000000), false },
1275	{ UINT32_C(0xc0000000), false },
1276	{ UINT32_C(0xd0000000), false },
1277	{ UINT32_C(0xe0000000), false },
1278	{ UINT32_C(0xf0000000), false },
1279	};
1280
1281	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1282	{
1283	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1284	uint32_t uEax, uEbx, uEcx, uEdx;
1285	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1286
1287	/*
1288	* Does EAX look like a typical leaf count value?
1289	*/
1290	if ( uEax > uLeaf
1291	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1292	{
1293	/* Yes, dump them. */
1294	uint32_t cLeaves = uEax - uLeaf + 1;
1295	while (cLeaves-- > 0)
1296	{
1297	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1298
1299	uint32_t fFlags = 0;
1300
1301	/* There are currently three known leaves containing an APIC ID
1302	that needs EMT specific attention */
1303	if (uLeaf == 1)
1304	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1305	else if (uLeaf == 0xb && uEcx != 0)
1306	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1307	else if ( uLeaf == UINT32_C(0x8000001e)
1308	&& ( uEax
1309	\|\| uEbx
1310	\|\| uEdx
1311	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1312	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1313
1314	/* The APIC bit is per-VCpu and needs flagging. */
1315	if (uLeaf == 1)
1316	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1317	else if ( uLeaf == UINT32_C(0x80000001)
1318	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1319	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1320	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1321
1322	/* Check three times here to reduce the chance of CPU migration
1323	resulting in false positives with things like the APIC ID. */
1324	uint32_t cSubLeaves;
1325	bool fFinalEcxUnchanged;
1326	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1327	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1328	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1329	{
1330	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1331	{
1332	/* This shouldn't happen. But in case it does, file all
1333	relevant details in the release log. */
1334	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1335	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1336	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1337	{
1338	uint32_t auTmp[4];
1339	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1340	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1341	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1342	}
1343	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1344	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1345	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1346	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1347	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1348	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1349	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1350	}
1351
1352	if (fFinalEcxUnchanged)
1353	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1354
1355	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1356	{
1357	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1358	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1359	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1360	if (RT_FAILURE(rc))
1361	return rc;
1362	}
1363	}
1364	else
1365	{
1366	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1367	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1368	if (RT_FAILURE(rc))
1369	return rc;
1370	}
1371
1372	/* next */
1373	uLeaf++;
1374	}
1375	}
1376	/*
1377	* Special CPUIDs needs special handling as they don't follow the
1378	* leaf count principle used above.
1379	*/
1380	else if (s_aCandidates[iOuter].fSpecial)
1381	{
1382	bool fKeep = false;
1383	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1384	fKeep = true;
1385	else if ( uLeaf == 0x8fffffff
1386	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1387	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1388	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1389	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1390	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1391	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1392	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1393	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1394	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1395	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1396	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1397	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1398	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1399	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1400	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1401	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1402	fKeep = true;
1403	if (fKeep)
1404	{
1405	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1406	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1407	if (RT_FAILURE(rc))
1408	return rc;
1409	}
1410	}
1411	}
1412
1413	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1414	return VINF_SUCCESS;
1415	}
1416
1417
1418	/**
1419	* Determines the method the CPU uses to handle unknown CPUID leaves.
1420	*
1421	* @returns VBox status code.
1422	* @param penmUnknownMethod Where to return the method.
1423	* @param pDefUnknown Where to return default unknown values. This
1424	* will be set, even if the resulting method
1425	* doesn't actually needs it.
1426	*/
1427	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1428	{
1429	uint32_t uLastStd = ASMCpuId_EAX(0);
1430	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1431	if (!ASMIsValidExtRange(uLastExt))
1432	uLastExt = 0x80000000;
1433
1434	uint32_t auChecks[] =
1435	{
1436	uLastStd + 1,
1437	uLastStd + 5,
1438	uLastStd + 8,
1439	uLastStd + 32,
1440	uLastStd + 251,
1441	uLastExt + 1,
1442	uLastExt + 8,
1443	uLastExt + 15,
1444	uLastExt + 63,
1445	uLastExt + 255,
1446	0x7fbbffcc,
1447	0x833f7872,
1448	0xefff2353,
1449	0x35779456,
1450	0x1ef6d33e,
1451	};
1452
1453	static const uint32_t s_auValues[] =
1454	{
1455	0xa95d2156,
1456	0x00000001,
1457	0x00000002,
1458	0x00000008,
1459	0x00000000,
1460	0x55773399,
1461	0x93401769,
1462	0x12039587,
1463	};
1464
1465	/*
1466	* Simple method, all zeros.
1467	*/
1468	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1469	pDefUnknown->uEax = 0;
1470	pDefUnknown->uEbx = 0;
1471	pDefUnknown->uEcx = 0;
1472	pDefUnknown->uEdx = 0;
1473
1474	/*
1475	* Intel has been observed returning the last standard leaf.
1476	*/
1477	uint32_t auLast[4];
1478	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1479
1480	uint32_t cChecks = RT_ELEMENTS(auChecks);
1481	while (cChecks > 0)
1482	{
1483	uint32_t auCur[4];
1484	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1485	if (memcmp(auCur, auLast, sizeof(auCur)))
1486	break;
1487	cChecks--;
1488	}
1489	if (cChecks == 0)
1490	{
1491	/* Now, what happens when the input changes? Esp. ECX. */
1492	uint32_t cTotal = 0;
1493	uint32_t cSame = 0;
1494	uint32_t cLastWithEcx = 0;
1495	uint32_t cNeither = 0;
1496	uint32_t cValues = RT_ELEMENTS(s_auValues);
1497	while (cValues > 0)
1498	{
1499	uint32_t uValue = s_auValues[cValues - 1];
1500	uint32_t auLastWithEcx[4];
1501	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1502	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1503
1504	cChecks = RT_ELEMENTS(auChecks);
1505	while (cChecks > 0)
1506	{
1507	uint32_t auCur[4];
1508	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1509	if (!memcmp(auCur, auLast, sizeof(auCur)))
1510	{
1511	cSame++;
1512	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1513	cLastWithEcx++;
1514	}
1515	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1516	cLastWithEcx++;
1517	else
1518	cNeither++;
1519	cTotal++;
1520	cChecks--;
1521	}
1522	cValues--;
1523	}
1524
1525	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1526	if (cSame == cTotal)
1527	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1528	else if (cLastWithEcx == cTotal)
1529	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1530	else
1531	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1532	pDefUnknown->uEax = auLast[0];
1533	pDefUnknown->uEbx = auLast[1];
1534	pDefUnknown->uEcx = auLast[2];
1535	pDefUnknown->uEdx = auLast[3];
1536	return VINF_SUCCESS;
1537	}
1538
1539	/*
1540	* Unchanged register values?
1541	*/
1542	cChecks = RT_ELEMENTS(auChecks);
1543	while (cChecks > 0)
1544	{
1545	uint32_t const uLeaf = auChecks[cChecks - 1];
1546	uint32_t cValues = RT_ELEMENTS(s_auValues);
1547	while (cValues > 0)
1548	{
1549	uint32_t uValue = s_auValues[cValues - 1];
1550	uint32_t auCur[4];
1551	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1552	if ( auCur[0] != uLeaf
1553	\|\| auCur[1] != uValue
1554	\|\| auCur[2] != uValue
1555	\|\| auCur[3] != uValue)
1556	break;
1557	cValues--;
1558	}
1559	if (cValues != 0)
1560	break;
1561	cChecks--;
1562	}
1563	if (cChecks == 0)
1564	{
1565	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1566	return VINF_SUCCESS;
1567	}
1568
1569	/*
1570	* Just go with the simple method.
1571	*/
1572	return VINF_SUCCESS;
1573	}
1574
1575
1576	/**
1577	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1578	*
1579	* @returns Read only name string.
1580	* @param enmUnknownMethod The method to translate.
1581	*/
1582	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1583	{
1584	switch (enmUnknownMethod)
1585	{
1586	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1587	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1588	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1589	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1590
1591	case CPUMUNKNOWNCPUID_INVALID:
1592	case CPUMUNKNOWNCPUID_END:
1593	case CPUMUNKNOWNCPUID_32BIT_HACK:
1594	break;
1595	}
1596	return "Invalid-unknown-CPUID-method";
1597	}
1598
1599
1600	/**
1601	* Detect the CPU vendor give n the
1602	*
1603	* @returns The vendor.
1604	* @param uEAX EAX from CPUID(0).
1605	* @param uEBX EBX from CPUID(0).
1606	* @param uECX ECX from CPUID(0).
1607	* @param uEDX EDX from CPUID(0).
1608	*/
1609	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1610	{
1611	if (ASMIsValidStdRange(uEAX))
1612	{
1613	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1614	return CPUMCPUVENDOR_AMD;
1615
1616	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1617	return CPUMCPUVENDOR_INTEL;
1618
1619	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1620	return CPUMCPUVENDOR_VIA;
1621
1622	if (ASMIsShanghaiCpuEx(uEBX, uECX, uEDX))
1623	return CPUMCPUVENDOR_SHANGHAI;
1624
1625	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1626	&& uECX == UINT32_C(0x64616574)
1627	&& uEDX == UINT32_C(0x736E4978))
1628	return CPUMCPUVENDOR_CYRIX;
1629
1630	/* "Geode by NSC", example: family 5, model 9. */
1631
1632	/** @todo detect the other buggers... */
1633	}
1634
1635	return CPUMCPUVENDOR_UNKNOWN;
1636	}
1637
1638
1639	/**
1640	* Translates a CPU vendor enum value into the corresponding string constant.
1641	*
1642	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1643	* value name. This can be useful when generating code.
1644	*
1645	* @returns Read only name string.
1646	* @param enmVendor The CPU vendor value.
1647	*/
1648	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1649	{
1650	switch (enmVendor)
1651	{
1652	case CPUMCPUVENDOR_INTEL: return "INTEL";
1653	case CPUMCPUVENDOR_AMD: return "AMD";
1654	case CPUMCPUVENDOR_VIA: return "VIA";
1655	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1656	case CPUMCPUVENDOR_SHANGHAI: return "SHANGHAI";
1657	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1658
1659	case CPUMCPUVENDOR_INVALID:
1660	case CPUMCPUVENDOR_32BIT_HACK:
1661	break;
1662	}
1663	return "Invalid-cpu-vendor";
1664	}
1665
1666
1667	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1668	{
1669	/* Could do binary search, doing linear now because I'm lazy. */
1670	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1671	while (cLeaves-- > 0)
1672	{
1673	if (pLeaf->uLeaf == uLeaf)
1674	return pLeaf;
1675	pLeaf++;
1676	}
1677	return NULL;
1678	}
1679
1680
1681	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1682	{
1683	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1684	if ( !pLeaf
1685	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1686	return pLeaf;
1687
1688	/* Linear sub-leaf search. Lazy as usual. */
1689	cLeaves -= pLeaf - paLeaves;
1690	while ( cLeaves-- > 0
1691	&& pLeaf->uLeaf == uLeaf)
1692	{
1693	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1694	return pLeaf;
1695	pLeaf++;
1696	}
1697
1698	return NULL;
1699	}
1700
1701
1702	static void cpumR3ExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURES pFeatures)
1703	{
1704	Assert(pVmxMsrs);
1705	Assert(pFeatures);
1706	Assert(pFeatures->fVmx);
1707
1708	/* Basic information. */
1709	{
1710	uint64_t const u64Basic = pVmxMsrs->u64Basic;
1711	pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1712	}
1713
1714	/* Pin-based VM-execution controls. */
1715	{
1716	uint32_t const fPinCtls = pVmxMsrs->PinCtls.n.allowed1;
1717	pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1718	pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1719	pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1720	pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1721	pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1722	}
1723
1724	/* Processor-based VM-execution controls. */
1725	{
1726	uint32_t const fProcCtls = pVmxMsrs->ProcCtls.n.allowed1;
1727	pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1728	pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1729	pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1730	pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1731	pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1732	pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1733	pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1734	pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1735	pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1736	pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1737	pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1738	pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1739	pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1740	pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1741	pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1742	pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1743	pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1744	pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1745	pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1746	pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1747	pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1748	}
1749
1750	/* Secondary processor-based VM-execution controls. */
1751	{
1752	uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1753	pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1754	pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1755	pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1756	pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1757	pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1758	pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1759	pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1760	pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1761	pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1762	pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1763	pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1764	pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1765	pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1766	pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1767	pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1768	pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1769	pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1770	pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_VE);
1771	pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1772	pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1773	}
1774
1775	/* VM-exit controls. */
1776	{
1777	uint32_t const fExitCtls = pVmxMsrs->ExitCtls.n.allowed1;
1778	pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1779	pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1780	pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1781	pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1782	pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1783	pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1784	pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1785	pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1786	}
1787
1788	/* VM-entry controls. */
1789	{
1790	uint32_t const fEntryCtls = pVmxMsrs->EntryCtls.n.allowed1;
1791	pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1792	pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1793	pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1794	pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1795	}
1796
1797	/* Miscellaneous data. */
1798	{
1799	uint32_t const fMiscData = pVmxMsrs->u64Misc;
1800	pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1801	pFeatures->fVmxIntelPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1802	pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1803	pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1804	}
1805	}
1806
1807
1808	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures)
1809	{
1810	Assert(pMsrs);
1811	RT_ZERO(*pFeatures);
1812	if (cLeaves >= 2)
1813	{
1814	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1815	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1816	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1817	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1818	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1819	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1820
1821	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1822	pStd0Leaf->uEbx,
1823	pStd0Leaf->uEcx,
1824	pStd0Leaf->uEdx);
1825	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1826	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1827	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1828	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1829	pFeatures->uFamily,
1830	pFeatures->uModel,
1831	pFeatures->uStepping);
1832
1833	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1834	if (pExtLeaf8)
1835	{
1836	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1837	pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1838	}
1839	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1840	{
1841	pFeatures->cMaxPhysAddrWidth = 36;
1842	pFeatures->cMaxLinearAddrWidth = 36;
1843	}
1844	else
1845	{
1846	pFeatures->cMaxPhysAddrWidth = 32;
1847	pFeatures->cMaxLinearAddrWidth = 32;
1848	}
1849
1850	/* Standard features. */
1851	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1852	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1853	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1854	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1855	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1856	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1857	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1858	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1859	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1860	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1861	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1862	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1863	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1864	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1865	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1866	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1867	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1868	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1869	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1870	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1871	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1872	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1873	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1874	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1875	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1876	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1877	if (pFeatures->fVmx)
1878	cpumR3ExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1879
1880	/* Structured extended features. */
1881	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1882	if (pSxfLeaf0)
1883	{
1884	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1885	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1886	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1887	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1888	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1889
1890	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1891	pFeatures->fIbrs = pFeatures->fIbpb;
1892	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1893	pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
1894	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1895	}
1896
1897	/* MWAIT/MONITOR leaf. */
1898	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1899	if (pMWaitLeaf)
1900	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1901	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1902
1903	/* Extended features. */
1904	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1905	if (pExtLeaf)
1906	{
1907	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1908	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1909	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1910	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1911	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1912	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1913	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1914	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1915	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1916	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1917	}
1918
1919	/* VMX (VMXON, VMCS region and related data structures') physical address width (depends on long-mode). */
1920	pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
1921
1922	if ( pExtLeaf
1923	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1924	{
1925	/* AMD features. */
1926	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1927	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1928	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1929	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1930	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1931	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1932	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1933	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1934	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1935	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1936	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1937	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1938	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1939	if (pFeatures->fSvm)
1940	{
1941	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1942	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1943	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1944	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1945	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1946	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1947	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1948	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1949	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1950	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1951	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1952	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1953	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1954	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1955	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1956	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1957	}
1958	}
1959
1960	/*
1961	* Quirks.
1962	*/
1963	pFeatures->fLeakyFxSR = pExtLeaf
1964	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1965	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1966	&& pFeatures->uFamily >= 6 /* K7 and up */;
1967
1968	/*
1969	* Max extended (/FPU) state.
1970	*/
1971	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1972	if (pFeatures->fXSaveRstor)
1973	{
1974	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1975	if (pXStateLeaf0)
1976	{
1977	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1978	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1979	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1980	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1981	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1982	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1983	{
1984	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1985
1986	/* (paranoia:) */
1987	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1988	if ( pXStateLeaf1
1989	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1990	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1991	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1992	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1993	}
1994	else
1995	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1996	pFeatures->fXSaveRstor = 0);
1997	}
1998	else
1999	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
2000	pFeatures->fXSaveRstor = 0);
2001	}
2002	}
2003	else
2004	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
2005	return VINF_SUCCESS;
2006	}
2007
2008
2009	/*
2010	*
2011	* Init related code.
2012	* Init related code.
2013	* Init related code.
2014	*
2015	*
2016	*/
2017	#ifdef VBOX_IN_VMM
2018
2019
2020	/**
2021	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
2022	*
2023	* This ignores the fSubLeafMask.
2024	*
2025	* @returns Pointer to the matching leaf, or NULL if not found.
2026	* @param paLeaves The CPUID leaves to search. This is sorted.
2027	* @param cLeaves The number of leaves in the array.
2028	* @param uLeaf The leaf to locate.
2029	* @param uSubLeaf The subleaf to locate.
2030	*/
2031	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
2032	{
2033	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
2034	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
2035	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
2036	if (iEnd)
2037	{
2038	uint32_t iBegin = 0;
2039	for (;;)
2040	{
2041	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
2042	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
2043	if (uNeedle < uCur)
2044	{
2045	if (i > iBegin)
2046	iEnd = i;
2047	else
2048	break;
2049	}
2050	else if (uNeedle > uCur)
2051	{
2052	if (i + 1 < iEnd)
2053	iBegin = i + 1;
2054	else
2055	break;
2056	}
2057	else
2058	return &paLeaves[i];
2059	}
2060	}
2061	return NULL;
2062	}
2063
2064
2065	/**
2066	* Loads MSR range overrides.
2067	*
2068	* This must be called before the MSR ranges are moved from the normal heap to
2069	* the hyper heap!
2070	*
2071	* @returns VBox status code (VMSetError called).
2072	* @param pVM The cross context VM structure.
2073	* @param pMsrNode The CFGM node with the MSR overrides.
2074	*/
2075	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
2076	{
2077	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2078	{
2079	/*
2080	* Assemble a valid MSR range.
2081	*/
2082	CPUMMSRRANGE MsrRange;
2083	MsrRange.offCpumCpu = 0;
2084	MsrRange.fReserved = 0;
2085
2086	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
2087	if (RT_FAILURE(rc))
2088	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
2089
2090	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
2091	if (RT_FAILURE(rc))
2092	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
2093	MsrRange.szName, rc);
2094
2095	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
2096	if (RT_FAILURE(rc))
2097	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
2098	MsrRange.szName, rc);
2099
2100	char szType[32];
2101	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
2102	if (RT_FAILURE(rc))
2103	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
2104	MsrRange.szName, rc);
2105	if (!RTStrICmp(szType, "FixedValue"))
2106	{
2107	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
2108	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
2109
2110	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
2111	if (RT_FAILURE(rc))
2112	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
2113	MsrRange.szName, rc);
2114
2115	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
2116	if (RT_FAILURE(rc))
2117	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
2118	MsrRange.szName, rc);
2119
2120	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
2121	if (RT_FAILURE(rc))
2122	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
2123	MsrRange.szName, rc);
2124	}
2125	else
2126	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
2127	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
2128
2129	/*
2130	* Insert the range into the table (replaces/splits/shrinks existing
2131	* MSR ranges).
2132	*/
2133	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
2134	&MsrRange);
2135	if (RT_FAILURE(rc))
2136	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
2137	}
2138
2139	return VINF_SUCCESS;
2140	}
2141
2142
2143	/**
2144	* Loads CPUID leaf overrides.
2145	*
2146	* This must be called before the CPUID leaves are moved from the normal
2147	* heap to the hyper heap!
2148	*
2149	* @returns VBox status code (VMSetError called).
2150	* @param pVM The cross context VM structure.
2151	* @param pParentNode The CFGM node with the CPUID leaves.
2152	* @param pszLabel How to label the overrides we're loading.
2153	*/
2154	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2155	{
2156	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2157	{
2158	/*
2159	* Get the leaf and subleaf numbers.
2160	*/
2161	char szName[128];
2162	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2163	if (RT_FAILURE(rc))
2164	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2165
2166	/* The leaf number is either specified directly or thru the node name. */
2167	uint32_t uLeaf;
2168	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2169	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2170	{
2171	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2172	if (rc != VINF_SUCCESS)
2173	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2174	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2175	}
2176	else if (RT_FAILURE(rc))
2177	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2178	pszLabel, szName, rc);
2179
2180	uint32_t uSubLeaf;
2181	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2182	if (RT_FAILURE(rc))
2183	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2184	pszLabel, szName, rc);
2185
2186	uint32_t fSubLeafMask;
2187	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2188	if (RT_FAILURE(rc))
2189	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2190	pszLabel, szName, rc);
2191
2192	/*
2193	* Look up the specified leaf, since the output register values
2194	* defaults to any existing values. This allows overriding a single
2195	* register, without needing to know the other values.
2196	*/
2197	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2198	CPUMCPUIDLEAF Leaf;
2199	if (pLeaf)
2200	Leaf = *pLeaf;
2201	else
2202	RT_ZERO(Leaf);
2203	Leaf.uLeaf = uLeaf;
2204	Leaf.uSubLeaf = uSubLeaf;
2205	Leaf.fSubLeafMask = fSubLeafMask;
2206
2207	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2208	if (RT_FAILURE(rc))
2209	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2210	pszLabel, szName, rc);
2211	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2212	if (RT_FAILURE(rc))
2213	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2214	pszLabel, szName, rc);
2215	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2216	if (RT_FAILURE(rc))
2217	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2218	pszLabel, szName, rc);
2219	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2220	if (RT_FAILURE(rc))
2221	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2222	pszLabel, szName, rc);
2223
2224	/*
2225	* Insert the leaf into the table (replaces existing ones).
2226	*/
2227	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2228	&Leaf);
2229	if (RT_FAILURE(rc))
2230	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2231	}
2232
2233	return VINF_SUCCESS;
2234	}
2235
2236
2237
2238	/**
2239	* Fetches overrides for a CPUID leaf.
2240	*
2241	* @returns VBox status code.
2242	* @param pLeaf The leaf to load the overrides into.
2243	* @param pCfgNode The CFGM node containing the overrides
2244	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2245	* @param iLeaf The CPUID leaf number.
2246	*/
2247	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2248	{
2249	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2250	if (pLeafNode)
2251	{
2252	uint32_t u32;
2253	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2254	if (RT_SUCCESS(rc))
2255	pLeaf->uEax = u32;
2256	else
2257	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2258
2259	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2260	if (RT_SUCCESS(rc))
2261	pLeaf->uEbx = u32;
2262	else
2263	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2264
2265	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2266	if (RT_SUCCESS(rc))
2267	pLeaf->uEcx = u32;
2268	else
2269	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2270
2271	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2272	if (RT_SUCCESS(rc))
2273	pLeaf->uEdx = u32;
2274	else
2275	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2276
2277	}
2278	return VINF_SUCCESS;
2279	}
2280
2281
2282	/**
2283	* Load the overrides for a set of CPUID leaves.
2284	*
2285	* @returns VBox status code.
2286	* @param paLeaves The leaf array.
2287	* @param cLeaves The number of leaves.
2288	* @param uStart The start leaf number.
2289	* @param pCfgNode The CFGM node containing the overrides
2290	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2291	*/
2292	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2293	{
2294	for (uint32_t i = 0; i < cLeaves; i++)
2295	{
2296	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2297	if (RT_FAILURE(rc))
2298	return rc;
2299	}
2300
2301	return VINF_SUCCESS;
2302	}
2303
2304
2305	/**
2306	* Installs the CPUID leaves and explods the data into structures like
2307	* GuestFeatures and CPUMCTX::aoffXState.
2308	*
2309	* @returns VBox status code.
2310	* @param pVM The cross context VM structure.
2311	* @param pCpum The CPUM part of @a VM.
2312	* @param paLeaves The leaves. These will be copied (but not freed).
2313	* @param cLeaves The number of leaves.
2314	* @param pMsrs The MSRs.
2315	*/
2316	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
2317	{
2318	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2319
2320	/*
2321	* Install the CPUID information.
2322	*/
2323	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2324	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2325
2326	AssertLogRelRCReturn(rc, rc);
2327	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2328	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2329	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2330	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2331	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2332
2333	/*
2334	* Update the default CPUID leaf if necessary.
2335	*/
2336	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2337	{
2338	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2339	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2340	{
2341	/* We don't use CPUID(0).eax here because of the NT hack that only
2342	changes that value without actually removing any leaves. */
2343	uint32_t i = 0;
2344	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2345	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2346	{
2347	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2348	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2349	i++;
2350	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2351	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2352	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2353	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2354	}
2355	break;
2356	}
2357	default:
2358	break;
2359	}
2360
2361	/*
2362	* Explode the guest CPU features.
2363	*/
2364	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
2365	&pCpum->GuestFeatures);
2366	AssertLogRelRCReturn(rc, rc);
2367
2368	/*
2369	* Adjust the scalable bus frequency according to the CPUID information
2370	* we're now using.
2371	*/
2372	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2373	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2374	? UINT64_C(100000000) /* 100MHz */
2375	: UINT64_C(133333333); /* 133MHz */
2376
2377	/*
2378	* Populate the legacy arrays. Currently used for everything, later only
2379	* for patch manager.
2380	*/
2381	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2382	{
2383	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2384	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2385	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2386	};
2387	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2388	{
2389	uint32_t cLeft = aOldRanges[i].cCpuIds;
2390	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2391	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2392	while (cLeft-- > 0)
2393	{
2394	uLeaf--;
2395	pLegacyLeaf--;
2396
2397	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2398	if (pLeaf)
2399	{
2400	pLegacyLeaf->uEax = pLeaf->uEax;
2401	pLegacyLeaf->uEbx = pLeaf->uEbx;
2402	pLegacyLeaf->uEcx = pLeaf->uEcx;
2403	pLegacyLeaf->uEdx = pLeaf->uEdx;
2404	}
2405	else
2406	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2407	}
2408	}
2409
2410	/*
2411	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2412	*/
2413	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2414	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2415	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2416	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2417	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2418	{
2419	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2420	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2421	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2422	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2423	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2424	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2425	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2426	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2427	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2428	pCpum->GuestFeatures.cbMaxExtendedState),
2429	VERR_CPUM_IPE_1);
2430	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2431	}
2432	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2433
2434	/* Copy the CPU #0 data to the other CPUs. */
2435	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2436	{
2437	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2438	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2439	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2440	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2441	}
2442
2443	return VINF_SUCCESS;
2444	}
2445
2446
2447	/** @name Instruction Set Extension Options
2448	* @{ */
2449	/** Configuration option type (extended boolean, really). */
2450	typedef uint8_t CPUMISAEXTCFG;
2451	/** Always disable the extension. */
2452	#define CPUMISAEXTCFG_DISABLED false
2453	/** Enable the extension if it's supported by the host CPU. */
2454	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2455	/** Enable the extension if it's supported by the host CPU, but don't let
2456	* the portable CPUID feature disable it. */
2457	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2458	/** Always enable the extension. */
2459	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2460	/** @} */
2461
2462	/**
2463	* CPUID Configuration (from CFGM).
2464	*
2465	* @remarks The members aren't document since we would only be duplicating the
2466	* \@cfgm entries in cpumR3CpuIdReadConfig.
2467	*/
2468	typedef struct CPUMCPUIDCONFIG
2469	{
2470	bool fNt4LeafLimit;
2471	bool fInvariantTsc;
2472	bool fForceVme;
2473	bool fNestedHWVirt;
2474
2475	CPUMISAEXTCFG enmCmpXchg16b;
2476	CPUMISAEXTCFG enmMonitor;
2477	CPUMISAEXTCFG enmMWaitExtensions;
2478	CPUMISAEXTCFG enmSse41;
2479	CPUMISAEXTCFG enmSse42;
2480	CPUMISAEXTCFG enmAvx;
2481	CPUMISAEXTCFG enmAvx2;
2482	CPUMISAEXTCFG enmXSave;
2483	CPUMISAEXTCFG enmAesNi;
2484	CPUMISAEXTCFG enmPClMul;
2485	CPUMISAEXTCFG enmPopCnt;
2486	CPUMISAEXTCFG enmMovBe;
2487	CPUMISAEXTCFG enmRdRand;
2488	CPUMISAEXTCFG enmRdSeed;
2489	CPUMISAEXTCFG enmCLFlushOpt;
2490	CPUMISAEXTCFG enmFsGsBase;
2491	CPUMISAEXTCFG enmPcid;
2492	CPUMISAEXTCFG enmInvpcid;
2493	CPUMISAEXTCFG enmFlushCmdMsr;
2494
2495	CPUMISAEXTCFG enmAbm;
2496	CPUMISAEXTCFG enmSse4A;
2497	CPUMISAEXTCFG enmMisAlnSse;
2498	CPUMISAEXTCFG enm3dNowPrf;
2499	CPUMISAEXTCFG enmAmdExtMmx;
2500
2501	uint32_t uMaxStdLeaf;
2502	uint32_t uMaxExtLeaf;
2503	uint32_t uMaxCentaurLeaf;
2504	uint32_t uMaxIntelFamilyModelStep;
2505	char szCpuName[128];
2506	} CPUMCPUIDCONFIG;
2507	/** Pointer to CPUID config (from CFGM). */
2508	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2509
2510
2511	/**
2512	* Mini CPU selection support for making Mac OS X happy.
2513	*
2514	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2515	*
2516	* @param pCpum The CPUM instance data.
2517	* @param pConfig The CPUID configuration we've read from CFGM.
2518	*/
2519	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2520	{
2521	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2522	{
2523	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2524	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2525	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2526	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2527	0);
2528	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2529	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2530	{
2531	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2532	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2533	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2534	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2535	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2536	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2537	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2538	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2539	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2540	pStdFeatureLeaf->uEax = uNew;
2541	}
2542	}
2543	}
2544
2545
2546
2547	/**
2548	* Limit it the number of entries, zapping the remainder.
2549	*
2550	* The limits are masking off stuff about power saving and similar, this
2551	* is perhaps a bit crudely done as there is probably some relatively harmless
2552	* info too in these leaves (like words about having a constant TSC).
2553	*
2554	* @param pCpum The CPUM instance data.
2555	* @param pConfig The CPUID configuration we've read from CFGM.
2556	*/
2557	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2558	{
2559	/*
2560	* Standard leaves.
2561	*/
2562	uint32_t uSubLeaf = 0;
2563	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2564	if (pCurLeaf)
2565	{
2566	uint32_t uLimit = pCurLeaf->uEax;
2567	if (uLimit <= UINT32_C(0x000fffff))
2568	{
2569	if (uLimit > pConfig->uMaxStdLeaf)
2570	{
2571	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2572	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2573	uLimit + 1, UINT32_C(0x000fffff));
2574	}
2575
2576	/* NT4 hack, no zapping of extra leaves here. */
2577	if (pConfig->fNt4LeafLimit && uLimit > 3)
2578	pCurLeaf->uEax = uLimit = 3;
2579
2580	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2581	pCurLeaf->uEax = uLimit;
2582	}
2583	else
2584	{
2585	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2586	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2587	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2588	}
2589	}
2590
2591	/*
2592	* Extended leaves.
2593	*/
2594	uSubLeaf = 0;
2595	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2596	if (pCurLeaf)
2597	{
2598	uint32_t uLimit = pCurLeaf->uEax;
2599	if ( uLimit >= UINT32_C(0x80000000)
2600	&& uLimit <= UINT32_C(0x800fffff))
2601	{
2602	if (uLimit > pConfig->uMaxExtLeaf)
2603	{
2604	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2605	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2606	uLimit + 1, UINT32_C(0x800fffff));
2607	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2608	pCurLeaf->uEax = uLimit;
2609	}
2610	}
2611	else
2612	{
2613	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2614	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2615	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2616	}
2617	}
2618
2619	/*
2620	* Centaur leaves (VIA).
2621	*/
2622	uSubLeaf = 0;
2623	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2624	if (pCurLeaf)
2625	{
2626	uint32_t uLimit = pCurLeaf->uEax;
2627	if ( uLimit >= UINT32_C(0xc0000000)
2628	&& uLimit <= UINT32_C(0xc00fffff))
2629	{
2630	if (uLimit > pConfig->uMaxCentaurLeaf)
2631	{
2632	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2633	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2634	uLimit + 1, UINT32_C(0xcfffffff));
2635	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2636	pCurLeaf->uEax = uLimit;
2637	}
2638	}
2639	else
2640	{
2641	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2642	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2643	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2644	}
2645	}
2646	}
2647
2648
2649	/**
2650	* Clears a CPUID leaf and all sub-leaves (to zero).
2651	*
2652	* @param pCpum The CPUM instance data.
2653	* @param uLeaf The leaf to clear.
2654	*/
2655	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2656	{
2657	uint32_t uSubLeaf = 0;
2658	PCPUMCPUIDLEAF pCurLeaf;
2659	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2660	{
2661	pCurLeaf->uEax = 0;
2662	pCurLeaf->uEbx = 0;
2663	pCurLeaf->uEcx = 0;
2664	pCurLeaf->uEdx = 0;
2665	uSubLeaf++;
2666	}
2667	}
2668
2669
2670	/**
2671	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2672	* the given leaf.
2673	*
2674	* @returns pLeaf.
2675	* @param pCpum The CPUM instance data.
2676	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2677	*/
2678	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2679	{
2680	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2681	if (pLeaf->fSubLeafMask != 0)
2682	{
2683	/*
2684	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2685	* Log everything while we're at it.
2686	*/
2687	LogRel(("CPUM:\n"
2688	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2689	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2690	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2691	for (;;)
2692	{
2693	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2694	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2695	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2696	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2697	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2698	break;
2699	pSubLeaf++;
2700	}
2701	LogRel(("CPUM:\n"));
2702
2703	/*
2704	* Remove the offending sub-leaves.
2705	*/
2706	if (pSubLeaf != pLeaf)
2707	{
2708	if (pSubLeaf != pLast)
2709	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2710	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2711	}
2712
2713	/*
2714	* Convert the first sub-leaf into a single leaf.
2715	*/
2716	pLeaf->uSubLeaf = 0;
2717	pLeaf->fSubLeafMask = 0;
2718	}
2719	return pLeaf;
2720	}
2721
2722
2723	/**
2724	* Sanitizes and adjust the CPUID leaves.
2725	*
2726	* Drop features that aren't virtualized (or virtualizable). Adjust information
2727	* and capabilities to fit the virtualized hardware. Remove information the
2728	* guest shouldn't have (because it's wrong in the virtual world or because it
2729	* gives away host details) or that we don't have documentation for and no idea
2730	* what means.
2731	*
2732	* @returns VBox status code.
2733	* @param pVM The cross context VM structure (for cCpus).
2734	* @param pCpum The CPUM instance data.
2735	* @param pConfig The CPUID configuration we've read from CFGM.
2736	*/
2737	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2738	{
2739	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2740	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2741	{ \
2742	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2743	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2744	}
2745	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2746	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2747	{ \
2748	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2749	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2750	}
2751	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2752	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2753	&& ((a_pLeafReg) & (fBitMask)) \
2754	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2755	{ \
2756	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2757	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2758	}
2759	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2760
2761	/* Cpuid 1:
2762	* EAX: CPU model, family and stepping.
2763	*
2764	* ECX + EDX: Supported features. Only report features we can support.
2765	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2766	* options may require adjusting (i.e. stripping what was enabled).
2767	*
2768	* EBX: Branding, CLFLUSH line size, logical processors per package and
2769	* initial APIC ID.
2770	*/
2771	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2772	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2773	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2774
2775	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2776	\| X86_CPUID_FEATURE_EDX_VME
2777	\| X86_CPUID_FEATURE_EDX_DE
2778	\| X86_CPUID_FEATURE_EDX_PSE
2779	\| X86_CPUID_FEATURE_EDX_TSC
2780	\| X86_CPUID_FEATURE_EDX_MSR
2781	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2782	\| X86_CPUID_FEATURE_EDX_MCE
2783	\| X86_CPUID_FEATURE_EDX_CX8
2784	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2785	//\| RT_BIT_32(10) - not defined
2786	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2787	//\| X86_CPUID_FEATURE_EDX_SEP
2788	\| X86_CPUID_FEATURE_EDX_MTRR
2789	\| X86_CPUID_FEATURE_EDX_PGE
2790	\| X86_CPUID_FEATURE_EDX_MCA
2791	\| X86_CPUID_FEATURE_EDX_CMOV
2792	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2793	\| X86_CPUID_FEATURE_EDX_PSE36
2794	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2795	\| X86_CPUID_FEATURE_EDX_CLFSH
2796	//\| RT_BIT_32(20) - not defined
2797	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2798	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2799	\| X86_CPUID_FEATURE_EDX_MMX
2800	\| X86_CPUID_FEATURE_EDX_FXSR
2801	\| X86_CPUID_FEATURE_EDX_SSE
2802	\| X86_CPUID_FEATURE_EDX_SSE2
2803	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2804	\| X86_CPUID_FEATURE_EDX_HTT
2805	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2806	//\| RT_BIT_32(30) - not defined
2807	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2808	;
2809	pStdFeatureLeaf->uEcx &= 0
2810	\| X86_CPUID_FEATURE_ECX_SSE3
2811	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2812	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2813	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2814	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2815	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2816	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2817	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2818	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2819	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2820	\| X86_CPUID_FEATURE_ECX_SSSE3
2821	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2822	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2823	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2824	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2825	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2826	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2827	\| (pConfig->enmPcid ? X86_CPUID_FEATURE_ECX_PCID : 0)
2828	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2829	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2830	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2831	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2832	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2833	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2834	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2835	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2836	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2837	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2838	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2839	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2840	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2841	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2842	;
2843
2844	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2845	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2846	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2847	{
2848	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2849	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2850	}
2851
2852	if (pCpum->u8PortableCpuIdLevel > 0)
2853	{
2854	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2855	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2856	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2857	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2858	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2859	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2860	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2861	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2862	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2863	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2864	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2865	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2866	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2867	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2868	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2869	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2870	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2871	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2872	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2873	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2874
2875	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2876	\| X86_CPUID_FEATURE_EDX_PSN
2877	\| X86_CPUID_FEATURE_EDX_DS
2878	\| X86_CPUID_FEATURE_EDX_ACPI
2879	\| X86_CPUID_FEATURE_EDX_SS
2880	\| X86_CPUID_FEATURE_EDX_TM
2881	\| X86_CPUID_FEATURE_EDX_PBE
2882	)));
2883	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2884	\| X86_CPUID_FEATURE_ECX_CPLDS
2885	\| X86_CPUID_FEATURE_ECX_AES
2886	\| X86_CPUID_FEATURE_ECX_VMX
2887	\| X86_CPUID_FEATURE_ECX_SMX
2888	\| X86_CPUID_FEATURE_ECX_EST
2889	\| X86_CPUID_FEATURE_ECX_TM2
2890	\| X86_CPUID_FEATURE_ECX_CNTXID
2891	\| X86_CPUID_FEATURE_ECX_FMA
2892	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2893	\| X86_CPUID_FEATURE_ECX_PDCM
2894	\| X86_CPUID_FEATURE_ECX_DCA
2895	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2896	)));
2897	}
2898
2899	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2900	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2901
2902	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2903	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2904	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2905	*/
2906	#ifdef VBOX_WITH_MULTI_CORE
2907	if (pVM->cCpus > 1)
2908	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2909	#endif
2910	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2911	{
2912	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2913	core times the number of CPU cores per processor */
2914	#ifdef VBOX_WITH_MULTI_CORE
2915	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2916	#else
2917	/* Single logical processor in a package. */
2918	pStdFeatureLeaf->uEbx \|= (1 << 16);
2919	#endif
2920	}
2921
2922	uint32_t uMicrocodeRev;
2923	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2924	if (RT_SUCCESS(rc))
2925	{
2926	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2927	}
2928	else
2929	{
2930	uMicrocodeRev = 0;
2931	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2932	}
2933
2934	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2935	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2936	*/
2937	if ( (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen)
2938	&& uMicrocodeRev < 0x8001126
2939	&& !pConfig->fForceVme)
2940	{
2941	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2942	LogRel(("CPUM: Zen VME workaround engaged\n"));
2943	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2944	}
2945
2946	/* Force standard feature bits. */
2947	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2948	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2949	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2950	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2951	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2952	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2953	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2954	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2955	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2956	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2957	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2958	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2959	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2960	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2961	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2962	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2963	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2964	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2965	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2966	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2967	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2968	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2969
2970	pStdFeatureLeaf = NULL; /* Must refetch! */
2971
2972	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2973	* AMD:
2974	* EAX: CPU model, family and stepping.
2975	*
2976	* ECX + EDX: Supported features. Only report features we can support.
2977	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2978	* options may require adjusting (i.e. stripping what was enabled).
2979	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2980	*
2981	* EBX: Branding ID and package type (or reserved).
2982	*
2983	* Intel and probably most others:
2984	* EAX: 0
2985	* EBX: 0
2986	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2987	*/
2988	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2989	if (pExtFeatureLeaf)
2990	{
2991	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2992
2993	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2994	\| X86_CPUID_AMD_FEATURE_EDX_VME
2995	\| X86_CPUID_AMD_FEATURE_EDX_DE
2996	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2997	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2998	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2999	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
3000	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
3001	\| X86_CPUID_AMD_FEATURE_EDX_CX8
3002	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
3003	//\| RT_BIT_32(10) - reserved
3004	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
3005	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
3006	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3007	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
3008	\| X86_CPUID_AMD_FEATURE_EDX_PGE
3009	\| X86_CPUID_AMD_FEATURE_EDX_MCA
3010	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
3011	\| X86_CPUID_AMD_FEATURE_EDX_PAT
3012	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
3013	//\| RT_BIT_32(18) - reserved
3014	//\| RT_BIT_32(19) - reserved
3015	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
3016	//\| RT_BIT_32(21) - reserved
3017	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
3018	\| X86_CPUID_AMD_FEATURE_EDX_MMX
3019	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
3020	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
3021	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3022	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
3023	//\| RT_BIT_32(28) - reserved
3024	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
3025	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
3026	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
3027	;
3028	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
3029	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
3030	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
3031	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3032	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
3033	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
3034	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
3035	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
3036	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
3037	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
3038	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3039	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
3040	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
3041	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3042	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
3043	//\| RT_BIT_32(14) - reserved
3044	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
3045	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
3046	//\| RT_BIT_32(17) - reserved
3047	//\| RT_BIT_32(18) - reserved
3048	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
3049	//\| RT_BIT_32(20) - reserved
3050	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
3051	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
3052	//\| RT_BIT_32(23) - reserved
3053	//\| RT_BIT_32(24) - reserved
3054	//\| RT_BIT_32(25) - reserved
3055	//\| RT_BIT_32(26) - reserved
3056	//\| RT_BIT_32(27) - reserved
3057	//\| RT_BIT_32(28) - reserved
3058	//\| RT_BIT_32(29) - reserved
3059	//\| RT_BIT_32(30) - reserved
3060	//\| RT_BIT_32(31) - reserved
3061	;
3062	#ifdef VBOX_WITH_MULTI_CORE
3063	if ( pVM->cCpus > 1
3064	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3065	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
3066	#endif
3067
3068	if (pCpum->u8PortableCpuIdLevel > 0)
3069	{
3070	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
3071	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
3072	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
3073	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
3074	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
3075	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
3076	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
3077	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
3078	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
3079	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
3080	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
3081	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
3082	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
3083	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
3084	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
3085	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
3086
3087	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
3088	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3089	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3090	\| X86_CPUID_AMD_FEATURE_ECX_IBS
3091	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3092	\| X86_CPUID_AMD_FEATURE_ECX_WDT
3093	\| X86_CPUID_AMD_FEATURE_ECX_LWP
3094	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
3095	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
3096	\| UINT32_C(0xff964000)
3097	)));
3098	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
3099	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3100	\| RT_BIT(18)
3101	\| RT_BIT(19)
3102	\| RT_BIT(21)
3103	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
3104	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3105	\| RT_BIT(28)
3106	)));
3107	}
3108
3109	/* Force extended feature bits. */
3110	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
3111	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
3112	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
3113	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
3114	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
3115	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
3116	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
3117	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
3118	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3119	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
3120	}
3121	pExtFeatureLeaf = NULL; /* Must refetch! */
3122
3123
3124	/* Cpuid 2:
3125	* Intel: (Nondeterministic) Cache and TLB information
3126	* AMD: Reserved
3127	* VIA: Reserved
3128	* Safe to expose.
3129	*/
3130	uint32_t uSubLeaf = 0;
3131	PCPUMCPUIDLEAF pCurLeaf;
3132	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
3133	{
3134	if ((pCurLeaf->uEax & 0xff) > 1)
3135	{
3136	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
3137	pCurLeaf->uEax &= UINT32_C(0xffffff01);
3138	}
3139	uSubLeaf++;
3140	}
3141
3142	/* Cpuid 3:
3143	* Intel: EAX, EBX - reserved (transmeta uses these)
3144	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3145	* AMD: Reserved
3146	* VIA: Reserved
3147	* Safe to expose
3148	*/
3149	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3150	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3151	{
3152	uSubLeaf = 0;
3153	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3154	{
3155	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3156	if (pCpum->u8PortableCpuIdLevel > 0)
3157	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3158	uSubLeaf++;
3159	}
3160	}
3161
3162	/* Cpuid 4 + ECX:
3163	* Intel: Deterministic Cache Parameters Leaf.
3164	* AMD: Reserved
3165	* VIA: Reserved
3166	* Safe to expose, except for EAX:
3167	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3168	* Bits 31-26: Maximum number of processor cores in this physical package**
3169	* Note: These SMP values are constant regardless of ECX
3170	*/
3171	uSubLeaf = 0;
3172	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3173	{
3174	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3175	#ifdef VBOX_WITH_MULTI_CORE
3176	if ( pVM->cCpus > 1
3177	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3178	{
3179	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3180	/* One logical processor with possibly multiple cores. */
3181	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3182	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3183	}
3184	#endif
3185	uSubLeaf++;
3186	}
3187
3188	/* Cpuid 5: Monitor/mwait Leaf
3189	* Intel: ECX, EDX - reserved
3190	* EAX, EBX - Smallest and largest monitor line size
3191	* AMD: EDX - reserved
3192	* EAX, EBX - Smallest and largest monitor line size
3193	* ECX - extensions (ignored for now)
3194	* VIA: Reserved
3195	* Safe to expose
3196	*/
3197	uSubLeaf = 0;
3198	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3199	{
3200	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3201	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3202	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3203
3204	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3205	if (pConfig->enmMWaitExtensions)
3206	{
3207	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3208	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3209	it shall be part of our power management virtualization model */
3210	#if 0
3211	/* MWAIT sub C-states */
3212	pCurLeaf->uEdx =
3213	(0 << 0) /* 0 in C0 */ \|
3214	(2 << 4) /* 2 in C1 */ \|
3215	(2 << 8) /* 2 in C2 */ \|
3216	(2 << 12) /* 2 in C3 */ \|
3217	(0 << 16) /* 0 in C4 */
3218	;
3219	#endif
3220	}
3221	else
3222	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3223	uSubLeaf++;
3224	}
3225
3226	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3227	* Intel: Various stuff.
3228	* AMD: EAX, EBX, EDX - reserved.
3229	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3230	* present. Same as intel.
3231	* VIA: ??
3232	*
3233	* We clear everything here for now.
3234	*/
3235	cpumR3CpuIdZeroLeaf(pCpum, 6);
3236
3237	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3238	* EAX: Number of sub leaves.
3239	* EBX+ECX+EDX: Feature flags
3240	*
3241	* We only have documentation for one sub-leaf, so clear all other (no need
3242	* to remove them as such, just set them to zero).
3243	*
3244	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3245	* options may require adjusting (i.e. stripping what was enabled).
3246	*/
3247	uSubLeaf = 0;
3248	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3249	{
3250	switch (uSubLeaf)
3251	{
3252	case 0:
3253	{
3254	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3255	pCurLeaf->uEbx &= 0
3256	\| (pConfig->enmFsGsBase ? X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE : 0)
3257	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3258	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3259	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3260	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3261	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3262	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3263	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3264	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3265	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3266	\| (pConfig->enmInvpcid ? X86_CPUID_STEXT_FEATURE_EBX_INVPCID : 0)
3267	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3268	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3269	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3270	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3271	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3272	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3273	//\| RT_BIT(17) - reserved
3274	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3275	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3276	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3277	//\| RT_BIT(21) - reserved
3278	//\| RT_BIT(22) - reserved
3279	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3280	//\| RT_BIT(24) - reserved
3281	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3282	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3283	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3284	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3285	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3286	//\| RT_BIT(30) - reserved
3287	//\| RT_BIT(31) - reserved
3288	;
3289	pCurLeaf->uEcx &= 0
3290	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3291	;
3292	pCurLeaf->uEdx &= 0
3293	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3294	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3295	\| (pConfig->enmFlushCmdMsr ? X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD : 0)
3296	//\| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT(29)
3297	;
3298
3299	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3300	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3301	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3302	{
3303	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3304	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3305	}
3306
3307	if (pCpum->u8PortableCpuIdLevel > 0)
3308	{
3309	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3310	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3311	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3312	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3313	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3314	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3315	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3316	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3317	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3318	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3319	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3320	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3321	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3322	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3323	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3324	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
3325	}
3326
3327	/* Force standard feature bits. */
3328	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3329	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3330	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3331	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3332	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3333	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3334	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3335	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3336	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3337	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3338	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3339	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
3340	break;
3341	}
3342
3343	default:
3344	/* Invalid index, all values are zero. */
3345	pCurLeaf->uEax = 0;
3346	pCurLeaf->uEbx = 0;
3347	pCurLeaf->uEcx = 0;
3348	pCurLeaf->uEdx = 0;
3349	break;
3350	}
3351	uSubLeaf++;
3352	}
3353
3354	/* Cpuid 8: Marked as reserved by Intel and AMD.
3355	* We zero this since we don't know what it may have been used for.
3356	*/
3357	cpumR3CpuIdZeroLeaf(pCpum, 8);
3358
3359	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3360	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3361	* EBX, ECX, EDX - reserved.
3362	* AMD: Reserved
3363	* VIA: ??
3364	*
3365	* We zero this.
3366	*/
3367	cpumR3CpuIdZeroLeaf(pCpum, 9);
3368
3369	/* Cpuid 0xa: Architectural Performance Monitor Features
3370	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3371	* EBX, ECX, EDX - reserved.
3372	* AMD: Reserved
3373	* VIA: ??
3374	*
3375	* We zero this, for now at least.
3376	*/
3377	cpumR3CpuIdZeroLeaf(pCpum, 10);
3378
3379	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3380	* Intel: EAX - APCI ID shift right for next level.
3381	* EBX - Factory configured cores/threads at this level.
3382	* ECX - Level number (same as input) and level type (1,2,0).
3383	* EDX - Extended initial APIC ID.
3384	* AMD: Reserved
3385	* VIA: ??
3386	*/
3387	uSubLeaf = 0;
3388	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3389	{
3390	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3391	{
3392	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3393	if (bLevelType == 1)
3394	{
3395	/* Thread level - we don't do threads at the moment. */
3396	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3397	pCurLeaf->uEbx = 1;
3398	}
3399	else if (bLevelType == 2)
3400	{
3401	/* Core level. */
3402	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3403	#ifdef VBOX_WITH_MULTI_CORE
3404	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3405	pCurLeaf->uEax++;
3406	#endif
3407	pCurLeaf->uEbx = pVM->cCpus;
3408	}
3409	else
3410	{
3411	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3412	pCurLeaf->uEax = 0;
3413	pCurLeaf->uEbx = 0;
3414	pCurLeaf->uEcx = 0;
3415	}
3416	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3417	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3418	}
3419	else
3420	{
3421	pCurLeaf->uEax = 0;
3422	pCurLeaf->uEbx = 0;
3423	pCurLeaf->uEcx = 0;
3424	pCurLeaf->uEdx = 0;
3425	}
3426	uSubLeaf++;
3427	}
3428
3429	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3430	* We zero this since we don't know what it may have been used for.
3431	*/
3432	cpumR3CpuIdZeroLeaf(pCpum, 12);
3433
3434	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3435	* ECX=0: EAX - Valid bits in XCR0[31:0].
3436	* EBX - Maximum state size as per current XCR0 value.
3437	* ECX - Maximum state size for all supported features.
3438	* EDX - Valid bits in XCR0[63:32].
3439	* ECX=1: EAX - Various X-features.
3440	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3441	* ECX - Valid bits in IA32_XSS[31:0].
3442	* EDX - Valid bits in IA32_XSS[63:32].
3443	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3444	* if the bit invalid all four registers are set to zero.
3445	* EAX - The state size for this feature.
3446	* EBX - The state byte offset of this feature.
3447	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3448	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3449	*
3450	* Clear them all as we don't currently implement extended CPU state.
3451	*/
3452	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3453	uint64_t fGuestXcr0Mask = 0;
3454	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3455	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3456	{
3457	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3458	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3459	fGuestXcr0Mask \|= XSAVE_C_YMM;
3460	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3461	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3462	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3463	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3464
3465	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3466	}
3467	pStdFeatureLeaf = NULL;
3468	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3469
3470	/* Work the sub-leaves. */
3471	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3472	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3473	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3474	{
3475	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3476	if (pCurLeaf)
3477	{
3478	if (fGuestXcr0Mask)
3479	{
3480	switch (uSubLeaf)
3481	{
3482	case 0:
3483	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3484	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3485	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3486	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3487	VERR_CPUM_IPE_1);
3488	cbXSaveMaxActual = pCurLeaf->uEcx;
3489	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3490	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3491	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3492	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3493	VERR_CPUM_IPE_2);
3494	continue;
3495	case 1:
3496	pCurLeaf->uEax &= 0;
3497	pCurLeaf->uEcx &= 0;
3498	pCurLeaf->uEdx &= 0;
3499	/** @todo what about checking ebx? */
3500	continue;
3501	default:
3502	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3503	{
3504	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3505	&& pCurLeaf->uEax > 0
3506	&& pCurLeaf->uEbx < cbXSaveMaxActual
3507	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3508	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3509	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3510	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3511	VERR_CPUM_IPE_2);
3512	AssertLogRel(!(pCurLeaf->uEcx & 1));
3513	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3514	pCurLeaf->uEdx = 0; /* it's reserved... */
3515	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3516	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3517	continue;
3518	}
3519	break;
3520	}
3521	}
3522
3523	/* Clear the leaf. */
3524	pCurLeaf->uEax = 0;
3525	pCurLeaf->uEbx = 0;
3526	pCurLeaf->uEcx = 0;
3527	pCurLeaf->uEdx = 0;
3528	}
3529	}
3530
3531	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3532	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3533	{
3534	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3535	if (pCurLeaf)
3536	{
3537	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3538	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3539	pCurLeaf->uEbx = cbXSaveMaxReport;
3540	pCurLeaf->uEcx = cbXSaveMaxReport;
3541	}
3542	}
3543
3544	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3545	* We zero this since we don't know what it may have been used for.
3546	*/
3547	cpumR3CpuIdZeroLeaf(pCpum, 14);
3548
3549	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3550	* also known as Intel Resource Director Technology (RDT) Monitoring
3551	* We zero this as we don't currently virtualize PQM.
3552	*/
3553	cpumR3CpuIdZeroLeaf(pCpum, 15);
3554
3555	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3556	* also known as Intel Resource Director Technology (RDT) Allocation
3557	* We zero this as we don't currently virtualize PQE.
3558	*/
3559	cpumR3CpuIdZeroLeaf(pCpum, 16);
3560
3561	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3562	* We zero this since we don't know what it may have been used for.
3563	*/
3564	cpumR3CpuIdZeroLeaf(pCpum, 17);
3565
3566	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3567	* We zero this as we don't currently virtualize this.
3568	*/
3569	cpumR3CpuIdZeroLeaf(pCpum, 18);
3570
3571	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3572	* We zero this since we don't know what it may have been used for.
3573	*/
3574	cpumR3CpuIdZeroLeaf(pCpum, 19);
3575
3576	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3577	* We zero this as we don't currently virtualize this.
3578	*/
3579	cpumR3CpuIdZeroLeaf(pCpum, 20);
3580
3581	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3582	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3583	* EAX - denominator (unsigned).
3584	* EBX - numerator (unsigned).
3585	* ECX, EDX - reserved.
3586	* AMD: Reserved / undefined / not implemented.
3587	* VIA: Reserved / undefined / not implemented.
3588	* We zero this as we don't currently virtualize this.
3589	*/
3590	cpumR3CpuIdZeroLeaf(pCpum, 21);
3591
3592	/* Cpuid 0x16: Processor frequency info
3593	* Intel: EAX - Core base frequency in MHz.
3594	* EBX - Core maximum frequency in MHz.
3595	* ECX - Bus (reference) frequency in MHz.
3596	* EDX - Reserved.
3597	* AMD: Reserved / undefined / not implemented.
3598	* VIA: Reserved / undefined / not implemented.
3599	* We zero this as we don't currently virtualize this.
3600	*/
3601	cpumR3CpuIdZeroLeaf(pCpum, 22);
3602
3603	/* Cpuid 0x17..0x10000000: Unknown.
3604	* We don't know these and what they mean, so remove them. */
3605	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3606	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3607
3608
3609	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3610	* We remove all these as we're a hypervisor and must provide our own.
3611	*/
3612	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3613	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3614
3615
3616	/* Cpuid 0x80000000 is harmless. */
3617
3618	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3619
3620	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3621
3622	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3623	* Safe to pass on to the guest.
3624	*
3625	* AMD: 0x800000005 L1 cache information
3626	* 0x800000006 L2/L3 cache information
3627	* Intel: 0x800000005 reserved
3628	* 0x800000006 L2 cache information
3629	* VIA: 0x800000005 TLB and L1 cache information
3630	* 0x800000006 L2 cache information
3631	*/
3632
3633	/* Cpuid 0x800000007: Advanced Power Management Information.
3634	* AMD: EAX: Processor feedback capabilities.
3635	* EBX: RAS capabilites.
3636	* ECX: Advanced power monitoring interface.
3637	* EDX: Enhanced power management capabilities.
3638	* Intel: EAX, EBX, ECX - reserved.
3639	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3640	* VIA: Reserved
3641	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3642	*/
3643	uSubLeaf = 0;
3644	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3645	{
3646	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3647	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3648	{
3649	/*
3650	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3651	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3652	* bit is now configurable.
3653	*/
3654	pCurLeaf->uEdx &= 0
3655	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3656	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3657	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3658	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3659	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3660	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3661	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3662	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3663	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3664	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3665	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3666	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3667	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3668	\| 0;
3669	}
3670	else
3671	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3672	if (!pConfig->fInvariantTsc)
3673	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3674	uSubLeaf++;
3675	}
3676
3677	/* Cpuid 0x80000008:
3678	* AMD: EBX, EDX - reserved
3679	* EAX: Virtual/Physical/Guest address Size
3680	* ECX: Number of cores + APICIdCoreIdSize
3681	* Intel: EAX: Virtual/Physical address Size
3682	* EBX, ECX, EDX - reserved
3683	* VIA: EAX: Virtual/Physical address Size
3684	* EBX, ECX, EDX - reserved
3685	*
3686	* We only expose the virtual+pysical address size to the guest atm.
3687	* On AMD we set the core count, but not the apic id stuff as we're
3688	* currently not doing the apic id assignments in a complatible manner.
3689	*/
3690	uSubLeaf = 0;
3691	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3692	{
3693	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3694	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3695	pCurLeaf->uEdx = 0; /* reserved */
3696
3697	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3698	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3699	pCurLeaf->uEcx = 0;
3700	#ifdef VBOX_WITH_MULTI_CORE
3701	if ( pVM->cCpus > 1
3702	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3703	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3704	#endif
3705	uSubLeaf++;
3706	}
3707
3708	/* Cpuid 0x80000009: Reserved
3709	* We zero this since we don't know what it may have been used for.
3710	*/
3711	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3712
3713	/* Cpuid 0x8000000a: SVM Information
3714	* AMD: EAX - SVM revision.
3715	* EBX - Number of ASIDs.
3716	* ECX - Reserved.
3717	* EDX - SVM Feature identification.
3718	*/
3719	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3720	if (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
3721	{
3722	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3723	pSvmFeatureLeaf->uEax = 0x1;
3724	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3725	pSvmFeatureLeaf->uEcx = 0;
3726	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3727	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3728	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3729	}
3730	else
3731	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3732
3733	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3734	* We clear these as we don't know what purpose they might have. */
3735	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3736	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3737
3738	/* Cpuid 0x80000019: TLB configuration
3739	* Seems to be harmless, pass them thru as is. */
3740
3741	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3742	* Strip anything we don't know what is or addresses feature we don't implement. */
3743	uSubLeaf = 0;
3744	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3745	{
3746	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3747	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3748	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3749	;
3750	pCurLeaf->uEbx = 0; /* reserved */
3751	pCurLeaf->uEcx = 0; /* reserved */
3752	pCurLeaf->uEdx = 0; /* reserved */
3753	uSubLeaf++;
3754	}
3755
3756	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3757	* Clear this as we don't currently virtualize this feature. */
3758	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3759
3760	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3761	* Clear this as we don't currently virtualize this feature. */
3762	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3763
3764	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3765	* We need to sanitize the cores per cache (EAX[25:14]).
3766	*
3767	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3768	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3769	* slightly different meaning.
3770	*/
3771	uSubLeaf = 0;
3772	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3773	{
3774	#ifdef VBOX_WITH_MULTI_CORE
3775	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3776	if (cCores > pVM->cCpus)
3777	cCores = pVM->cCpus;
3778	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3779	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3780	#else
3781	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3782	#endif
3783	uSubLeaf++;
3784	}
3785
3786	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3787	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3788	* setup, we have one compute unit with all the cores in it. Single node.
3789	*/
3790	uSubLeaf = 0;
3791	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3792	{
3793	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3794	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3795	{
3796	#ifdef VBOX_WITH_MULTI_CORE
3797	pCurLeaf->uEbx = pVM->cCpus < 0x100
3798	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3799	#else
3800	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3801	#endif
3802	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3803	}
3804	else
3805	{
3806	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3807	pCurLeaf->uEbx = 0; /* Reserved. */
3808	pCurLeaf->uEcx = 0; /* Reserved. */
3809	}
3810	pCurLeaf->uEdx = 0; /* Reserved. */
3811	uSubLeaf++;
3812	}
3813
3814	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3815	* We don't know these and what they mean, so remove them. */
3816	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3817	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3818
3819	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3820	* Just pass it thru for now. */
3821
3822	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3823	* Just pass it thru for now. */
3824
3825	/* Cpuid 0xc0000000: Centaur stuff.
3826	* Harmless, pass it thru. */
3827
3828	/* Cpuid 0xc0000001: Centaur features.
3829	* VIA: EAX - Family, model, stepping.
3830	* EDX - Centaur extended feature flags. Nothing interesting, except may
3831	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3832	* EBX, ECX - reserved.
3833	* We keep EAX but strips the rest.
3834	*/
3835	uSubLeaf = 0;
3836	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3837	{
3838	pCurLeaf->uEbx = 0;
3839	pCurLeaf->uEcx = 0;
3840	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3841	uSubLeaf++;
3842	}
3843
3844	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3845	* We only have fixed stale values, but should be harmless. */
3846
3847	/* Cpuid 0xc0000003: Reserved.
3848	* We zero this since we don't know what it may have been used for.
3849	*/
3850	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3851
3852	/* Cpuid 0xc0000004: Centaur Performance Info.
3853	* We only have fixed stale values, but should be harmless. */
3854
3855
3856	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3857	* We don't know these and what they mean, so remove them. */
3858	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3859	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3860
3861	return VINF_SUCCESS;
3862	#undef PORTABLE_DISABLE_FEATURE_BIT
3863	#undef PORTABLE_CLEAR_BITS_WHEN
3864	}
3865
3866
3867	/**
3868	* Reads a value in /CPUM/IsaExts/ node.
3869	*
3870	* @returns VBox status code (error message raised).
3871	* @param pVM The cross context VM structure. (For errors.)
3872	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3873	* @param pszValueName The value / extension name.
3874	* @param penmValue Where to return the choice.
3875	* @param enmDefault The default choice.
3876	*/
3877	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3878	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3879	{
3880	/*
3881	* Try integer encoding first.
3882	*/
3883	uint64_t uValue;
3884	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3885	if (RT_SUCCESS(rc))
3886	switch (uValue)
3887	{
3888	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3889	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3890	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3891	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3892	default:
3893	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3894	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3895	pszValueName, uValue);
3896	}
3897	/*
3898	* If missing, use default.
3899	*/
3900	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3901	*penmValue = enmDefault;
3902	else
3903	{
3904	if (rc == VERR_CFGM_NOT_INTEGER)
3905	{
3906	/*
3907	* Not an integer, try read it as a string.
3908	*/
3909	char szValue[32];
3910	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3911	if (RT_SUCCESS(rc))
3912	{
3913	RTStrToLower(szValue);
3914	size_t cchValue = strlen(szValue);
3915	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3916	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3917	*penmValue = CPUMISAEXTCFG_DISABLED;
3918	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3919	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3920	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3921	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3922	else if (EQ("portable"))
3923	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3924	else if (EQ("default") \|\| EQ("def"))
3925	*penmValue = enmDefault;
3926	else
3927	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3928	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3929	pszValueName, uValue);
3930	#undef EQ
3931	}
3932	}
3933	if (RT_FAILURE(rc))
3934	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3935	}
3936	return VINF_SUCCESS;
3937	}
3938
3939
3940	/**
3941	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3942	*
3943	* @returns VBox status code (error message raised).
3944	* @param pVM The cross context VM structure. (For errors.)
3945	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3946	* @param pszValueName The value / extension name.
3947	* @param penmValue Where to return the choice.
3948	* @param enmDefault The default choice.
3949	* @param fAllowed Allowed choice. Applied both to the result and to
3950	* the default value.
3951	*/
3952	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3953	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3954	{
3955	int rc;
3956	if (fAllowed)
3957	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3958	else
3959	{
3960	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3961	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3962	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3963	*penmValue = CPUMISAEXTCFG_DISABLED;
3964	}
3965	return rc;
3966	}
3967
3968
3969	/**
3970	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3971	*
3972	* @returns VBox status code (error message raised).
3973	* @param pVM The cross context VM structure. (For errors.)
3974	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3975	* @param pCpumCfg The /CPUM node (can be NULL).
3976	* @param pszValueName The value / extension name.
3977	* @param penmValue Where to return the choice.
3978	* @param enmDefault The default choice.
3979	*/
3980	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3981	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3982	{
3983	if (CFGMR3Exists(pCpumCfg, pszValueName))
3984	{
3985	if (!CFGMR3Exists(pIsaExts, pszValueName))
3986	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3987	else
3988	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3989	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3990	pszValueName, pszValueName);
3991
3992	bool fLegacy;
3993	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3994	if (RT_SUCCESS(rc))
3995	{
3996	*penmValue = fLegacy;
3997	return VINF_SUCCESS;
3998	}
3999	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
4000	}
4001
4002	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4003	}
4004
4005
4006	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
4007	{
4008	int rc;
4009
4010	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
4011	* When non-zero CPUID features that could cause portability issues will be
4012	* stripped. The higher the value the more features gets stripped. Higher
4013	* values should only be used when older CPUs are involved since it may
4014	* harm performance and maybe also cause problems with specific guests. */
4015	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
4016	AssertLogRelRCReturn(rc, rc);
4017
4018	/** @cfgm{/CPUM/GuestCpuName, string}
4019	* The name of the CPU we're to emulate. The default is the host CPU.
4020	* Note! CPUs other than "host" one is currently unsupported. */
4021	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
4022	AssertLogRelRCReturn(rc, rc);
4023
4024	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
4025	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
4026	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
4027	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
4028	*/
4029	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
4030	AssertLogRelRCReturn(rc, rc);
4031
4032	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
4033	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
4034	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
4035	* 64-bit linux guests which assume the presence of AMD performance counters
4036	* that we do not virtualize.
4037	*/
4038	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
4039	AssertLogRelRCReturn(rc, rc);
4040
4041	/** @cfgm{/CPUM/ForceVme, boolean, false}
4042	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
4043	* By default the flag is passed thru as is from the host CPU, except
4044	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
4045	* guests and DOS boxes in general.
4046	*/
4047	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
4048	AssertLogRelRCReturn(rc, rc);
4049
4050	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
4051	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
4052	* probably going to be a temporary hack, so don't depend on this.
4053	* The 1st byte of the value is the stepping, the 2nd byte value is the model
4054	* number and the 3rd byte value is the family, and the 4th value must be zero.
4055	*/
4056	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
4057	AssertLogRelRCReturn(rc, rc);
4058
4059	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
4060	* The last standard leaf to keep. The actual last value that is stored in EAX
4061	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
4062	* removed. (This works independently of and differently from NT4LeafLimit.)
4063	* The default is usually set to what we're able to reasonably sanitize.
4064	*/
4065	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
4066	AssertLogRelRCReturn(rc, rc);
4067
4068	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
4069	* The last extended leaf to keep. The actual last value that is stored in EAX
4070	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
4071	* leaf are removed. The default is set to what we're able to sanitize.
4072	*/
4073	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
4074	AssertLogRelRCReturn(rc, rc);
4075
4076	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
4077	* The last extended leaf to keep. The actual last value that is stored in EAX
4078	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
4079	* leaf are removed. The default is set to what we're able to sanitize.
4080	*/
4081	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
4082	AssertLogRelRCReturn(rc, rc);
4083
4084	bool fQueryNestedHwvirt = false;
4085	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4086	fQueryNestedHwvirt \|= RT_BOOL(pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD);
4087	#endif
4088	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4089	fQueryNestedHwvirt \|= RT_BOOL( pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
4090	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA);
4091	#endif
4092	if (fQueryNestedHwvirt)
4093	{
4094	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
4095	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
4096	* The default is false, and when enabled requires a 64-bit CPU with support for
4097	* nested-paging and AMD-V or unrestricted guest mode.
4098	*/
4099	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
4100	AssertLogRelRCReturn(rc, rc);
4101	if ( pConfig->fNestedHWVirt
4102	&& !fNestedPagingAndFullGuestExec)
4103	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4104	"Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
4105
4106	/** @todo Think about enabling this later with NEM/KVM. */
4107	if ( pConfig->fNestedHWVirt
4108	&& VM_IS_NEM_ENABLED(pVM))
4109	{
4110	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
4111	pConfig->fNestedHWVirt = false;
4112	}
4113
4114	#if HC_ARCH_BITS == 32
4115	/* We don't support nested hardware virtualization on 32-bit hosts. */
4116	if (pConfig->fNestedHWVirt)
4117	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4118	"Cannot enable nested VT-x/AMD-V on a 32-bit host\n");
4119	#endif
4120	}
4121
4122	/*
4123	* Instruction Set Architecture (ISA) Extensions.
4124	*/
4125	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
4126	if (pIsaExts)
4127	{
4128	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
4129	"CMPXCHG16B"
4130	"\|MONITOR"
4131	"\|MWaitExtensions"
4132	"\|SSE4.1"
4133	"\|SSE4.2"
4134	"\|XSAVE"
4135	"\|AVX"
4136	"\|AVX2"
4137	"\|AESNI"
4138	"\|PCLMUL"
4139	"\|POPCNT"
4140	"\|MOVBE"
4141	"\|RDRAND"
4142	"\|RDSEED"
4143	"\|CLFLUSHOPT"
4144	"\|FSGSBASE"
4145	"\|PCID"
4146	"\|INVPCID"
4147	"\|FlushCmdMsr"
4148	"\|ABM"
4149	"\|SSE4A"
4150	"\|MISALNSSE"
4151	"\|3DNOWPRF"
4152	"\|AXMMX"
4153	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
4154	if (RT_FAILURE(rc))
4155	return rc;
4156	}
4157
4158	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
4159	* Expose CMPXCHG16B to the guest if supported by the host. For the time
4160	* being the default is to only do this for VMs with nested paging and AMD-V or
4161	* unrestricted guest mode.
4162	*/
4163	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
4164	AssertLogRelRCReturn(rc, rc);
4165
4166	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4167	* Expose MONITOR/MWAIT instructions to the guest.
4168	*/
4169	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4170	AssertLogRelRCReturn(rc, rc);
4171
4172	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4173	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4174	* break on interrupt feature (bit 1).
4175	*/
4176	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4177	AssertLogRelRCReturn(rc, rc);
4178
4179	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4180	* Expose SSE4.1 to the guest if available.
4181	*/
4182	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4183	AssertLogRelRCReturn(rc, rc);
4184
4185	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4186	* Expose SSE4.2 to the guest if available.
4187	*/
4188	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4189	AssertLogRelRCReturn(rc, rc);
4190
4191	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4192	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4193	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
4194	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
4195	&& ( !HMIsLongModeAllowed(pVM)
4196	\|\| NEMHCIsLongModeAllowed(pVM))
4197	#endif
4198	;
4199	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4200
4201	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4202	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4203	* default is to only expose this to VMs with nested paging and AMD-V or
4204	* unrestricted guest execution mode. Not possible to force this one without
4205	* host support at the moment.
4206	*/
4207	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4208	fMayHaveXSave /fAllowed/);
4209	AssertLogRelRCReturn(rc, rc);
4210
4211	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4212	* Expose the AVX instruction set extensions to the guest if available and
4213	* XSAVE is exposed too. For the time being the default is to only expose this
4214	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4215	*/
4216	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4217	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4218	AssertLogRelRCReturn(rc, rc);
4219
4220	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4221	* Expose the AVX2 instruction set extensions to the guest if available and
4222	* XSAVE is exposed too. For the time being the default is to only expose this
4223	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4224	*/
4225	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4226	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4227	AssertLogRelRCReturn(rc, rc);
4228
4229	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4230	* Whether to expose the AES instructions to the guest. For the time being the
4231	* default is to only do this for VMs with nested paging and AMD-V or
4232	* unrestricted guest mode.
4233	*/
4234	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4235	AssertLogRelRCReturn(rc, rc);
4236
4237	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4238	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4239	* being the default is to only do this for VMs with nested paging and AMD-V or
4240	* unrestricted guest mode.
4241	*/
4242	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4243	AssertLogRelRCReturn(rc, rc);
4244
4245	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4246	* Whether to expose the POPCNT instructions to the guest. For the time
4247	* being the default is to only do this for VMs with nested paging and AMD-V or
4248	* unrestricted guest mode.
4249	*/
4250	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4251	AssertLogRelRCReturn(rc, rc);
4252
4253	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4254	* Whether to expose the MOVBE instructions to the guest. For the time
4255	* being the default is to only do this for VMs with nested paging and AMD-V or
4256	* unrestricted guest mode.
4257	*/
4258	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4259	AssertLogRelRCReturn(rc, rc);
4260
4261	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4262	* Whether to expose the RDRAND instructions to the guest. For the time being
4263	* the default is to only do this for VMs with nested paging and AMD-V or
4264	* unrestricted guest mode.
4265	*/
4266	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4267	AssertLogRelRCReturn(rc, rc);
4268
4269	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4270	* Whether to expose the RDSEED instructions to the guest. For the time being
4271	* the default is to only do this for VMs with nested paging and AMD-V or
4272	* unrestricted guest mode.
4273	*/
4274	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4275	AssertLogRelRCReturn(rc, rc);
4276
4277	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4278	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4279	* being the default is to only do this for VMs with nested paging and AMD-V or
4280	* unrestricted guest mode.
4281	*/
4282	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4283	AssertLogRelRCReturn(rc, rc);
4284
4285	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4286	* Whether to expose the read/write FSGSBASE instructions to the guest.
4287	*/
4288	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4289	AssertLogRelRCReturn(rc, rc);
4290
4291	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4292	* Whether to expose the PCID feature to the guest.
4293	*/
4294	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4295	AssertLogRelRCReturn(rc, rc);
4296
4297	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4298	* Whether to expose the INVPCID instruction to the guest.
4299	*/
4300	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4301	AssertLogRelRCReturn(rc, rc);
4302
4303	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
4304	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
4305	*/
4306	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4307	AssertLogRelRCReturn(rc, rc);
4308
4309
4310	/* AMD: */
4311
4312	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4313	* Whether to expose the AMD ABM instructions to the guest. For the time
4314	* being the default is to only do this for VMs with nested paging and AMD-V or
4315	* unrestricted guest mode.
4316	*/
4317	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4318	AssertLogRelRCReturn(rc, rc);
4319
4320	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4321	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4322	* being the default is to only do this for VMs with nested paging and AMD-V or
4323	* unrestricted guest mode.
4324	*/
4325	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4326	AssertLogRelRCReturn(rc, rc);
4327
4328	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4329	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4330	* the time being the default is to only do this for VMs with nested paging and
4331	* AMD-V or unrestricted guest mode.
4332	*/
4333	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4334	AssertLogRelRCReturn(rc, rc);
4335
4336	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4337	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4338	* For the time being the default is to only do this for VMs with nested paging
4339	* and AMD-V or unrestricted guest mode.
4340	*/
4341	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4342	AssertLogRelRCReturn(rc, rc);
4343
4344	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4345	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4346	* the default is to only do this for VMs with nested paging and AMD-V or
4347	* unrestricted guest mode.
4348	*/
4349	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4350	AssertLogRelRCReturn(rc, rc);
4351
4352	return VINF_SUCCESS;
4353	}
4354
4355
4356	/**
4357	* Initializes the emulated CPU's CPUID & MSR information.
4358	*
4359	* @returns VBox status code.
4360	* @param pVM The cross context VM structure.
4361	* @param pHostMsrs Pointer to the host MSRs.
4362	*/
4363	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
4364	{
4365	Assert(pHostMsrs);
4366
4367	PCPUM pCpum = &pVM->cpum.s;
4368	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4369
4370	/*
4371	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4372	* on construction and manage everything from here on.
4373	*/
4374	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
4375	pVM->aCpus[iCpu].cpum.s.fCpuIdApicFeatureVisible = true;
4376
4377	/*
4378	* Read the configuration.
4379	*/
4380	CPUMCPUIDCONFIG Config;
4381	RT_ZERO(Config);
4382
4383	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4384	AssertRCReturn(rc, rc);
4385
4386	/*
4387	* Get the guest CPU data from the database and/or the host.
4388	*
4389	* The CPUID and MSRs are currently living on the regular heap to avoid
4390	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4391	* API for the hyper heap). This means special cleanup considerations.
4392	*/
4393	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4394	if (RT_FAILURE(rc))
4395	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4396	? VMSetError(pVM, rc, RT_SRC_POS,
4397	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4398	: rc;
4399
4400	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4401	{
4402	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4403	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4404	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4405	}
4406	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4407
4408	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4409	* Overrides the guest MSRs.
4410	*/
4411	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4412
4413	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4414	* Overrides the CPUID leaf values (from the host CPU usually) used for
4415	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4416	* values when moving a VM to a different machine. Another use is restricting
4417	* (or extending) the feature set exposed to the guest. */
4418	if (RT_SUCCESS(rc))
4419	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4420
4421	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4422	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4423	"Found unsupported configuration node '/CPUM/CPUID/'. "
4424	"Please use IMachine::setCPUIDLeaf() instead.");
4425
4426	CPUMMSRS GuestMsrs;
4427	RT_ZERO(GuestMsrs);
4428
4429	/*
4430	* Pre-explode the CPUID info.
4431	*/
4432	if (RT_SUCCESS(rc))
4433	{
4434	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
4435	&pCpum->GuestFeatures);
4436	}
4437
4438	/*
4439	* Sanitize the cpuid information passed on to the guest.
4440	*/
4441	if (RT_SUCCESS(rc))
4442	{
4443	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4444	if (RT_SUCCESS(rc))
4445	{
4446	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4447	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4448	}
4449	}
4450
4451	/*
4452	* Setup MSRs introduced in microcode updates or that are otherwise not in
4453	* the CPU profile, but are advertised in the CPUID info we just sanitized.
4454	*/
4455	if (RT_SUCCESS(rc))
4456	rc = cpumR3MsrReconcileWithCpuId(pVM);
4457	/*
4458	* MSR fudging.
4459	*/
4460	if (RT_SUCCESS(rc))
4461	{
4462	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4463	* Fudges some common MSRs if not present in the selected CPU database entry.
4464	* This is for trying to keep VMs running when moved between different hosts
4465	* and different CPU vendors. */
4466	bool fEnable;
4467	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4468	if (RT_SUCCESS(rc) && fEnable)
4469	{
4470	rc = cpumR3MsrApplyFudge(pVM);
4471	AssertLogRelRC(rc);
4472	}
4473	}
4474	if (RT_SUCCESS(rc))
4475	{
4476	/*
4477	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4478	* guest CPU features again.
4479	*/
4480	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4481	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4482	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
4483	RTMemFree(pvFree);
4484
4485	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4486	int rc2 = MMHyperDupMem(pVM, pvFree,
4487	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4488	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4489	RTMemFree(pvFree);
4490	AssertLogRelRCReturn(rc1, rc1);
4491	AssertLogRelRCReturn(rc2, rc2);
4492
4493	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4494	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4495
4496	/*
4497	* Finally, initialize guest VMX MSRs.
4498	*
4499	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
4500	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
4501	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
4502	*/
4503	if (pVM->cpum.s.GuestFeatures.fVmx)
4504	{
4505	Assert(Config.fNestedHWVirt);
4506	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
4507
4508	/* Copy MSRs to all VCPUs */
4509	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
4510	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4511	{
4512	PVMCPU pVCpu = &pVM->aCpus[idCpu];
4513	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
4514	}
4515	}
4516
4517	/*
4518	* Some more configuration that we're applying at the end of everything
4519	* via the CPUMSetGuestCpuIdFeature API.
4520	*/
4521
4522	/* Check if PAE was explicitely enabled by the user. */
4523	bool fEnable;
4524	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4525	AssertRCReturn(rc, rc);
4526	if (fEnable)
4527	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4528
4529	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4530	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4531	AssertRCReturn(rc, rc);
4532	if (fEnable)
4533	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4534
4535	/* Check if speculation control is enabled. */
4536	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4537	AssertRCReturn(rc, rc);
4538	if (fEnable)
4539	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4540
4541	return VINF_SUCCESS;
4542	}
4543
4544	/*
4545	* Failed before switching to hyper heap.
4546	*/
4547	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4548	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4549	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4550	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4551	return rc;
4552	}
4553
4554
4555	/**
4556	* Sets a CPUID feature bit during VM initialization.
4557	*
4558	* Since the CPUID feature bits are generally related to CPU features, other
4559	* CPUM configuration like MSRs can also be modified by calls to this API.
4560	*
4561	* @param pVM The cross context VM structure.
4562	* @param enmFeature The feature to set.
4563	*/
4564	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4565	{
4566	PCPUMCPUIDLEAF pLeaf;
4567	PCPUMMSRRANGE pMsrRange;
4568
4569	switch (enmFeature)
4570	{
4571	/*
4572	* Set the APIC bit in both feature masks.
4573	*/
4574	case CPUMCPUIDFEATURE_APIC:
4575	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4576	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4577	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4578
4579	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4580	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4581	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4582
4583	pVM->cpum.s.GuestFeatures.fApic = 1;
4584
4585	/* Make sure we've got the APICBASE MSR present. */
4586	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4587	if (!pMsrRange)
4588	{
4589	static CPUMMSRRANGE const s_ApicBase =
4590	{
4591	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4592	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4593	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4594	/.szName = / "IA32_APIC_BASE"
4595	};
4596	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4597	AssertLogRelRC(rc);
4598	}
4599
4600	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4601	break;
4602
4603	/*
4604	* Set the x2APIC bit in the standard feature mask.
4605	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4606	*/
4607	case CPUMCPUIDFEATURE_X2APIC:
4608	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4609	if (pLeaf)
4610	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4611	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4612
4613	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4614	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4615	if (pMsrRange)
4616	{
4617	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4618	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4619	}
4620
4621	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4622	break;
4623
4624	/*
4625	* Set the sysenter/sysexit bit in the standard feature mask.
4626	* Assumes the caller knows what it's doing! (host must support these)
4627	*/
4628	case CPUMCPUIDFEATURE_SEP:
4629	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4630	{
4631	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4632	return;
4633	}
4634
4635	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4636	if (pLeaf)
4637	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4638	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4639	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4640	break;
4641
4642	/*
4643	* Set the syscall/sysret bit in the extended feature mask.
4644	* Assumes the caller knows what it's doing! (host must support these)
4645	*/
4646	case CPUMCPUIDFEATURE_SYSCALL:
4647	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4648	if ( !pLeaf
4649	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4650	{
4651	#if HC_ARCH_BITS == 32
4652	/* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit
4653	mode by Intel, even when the cpu is capable of doing so in
4654	64-bit mode. Long mode requires syscall support. */
4655	if (!pVM->cpum.s.HostFeatures.fLongMode)
4656	#endif
4657	{
4658	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4659	return;
4660	}
4661	}
4662
4663	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4664	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4665	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4666	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4667	break;
4668
4669	/*
4670	* Set the PAE bit in both feature masks.
4671	* Assumes the caller knows what it's doing! (host must support these)
4672	*/
4673	case CPUMCPUIDFEATURE_PAE:
4674	if (!pVM->cpum.s.HostFeatures.fPae)
4675	{
4676	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4677	return;
4678	}
4679
4680	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4681	if (pLeaf)
4682	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4683
4684	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4685	if ( pLeaf
4686	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4687	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4688
4689	pVM->cpum.s.GuestFeatures.fPae = 1;
4690	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4691	break;
4692
4693	/*
4694	* Set the LONG MODE bit in the extended feature mask.
4695	* Assumes the caller knows what it's doing! (host must support these)
4696	*/
4697	case CPUMCPUIDFEATURE_LONG_MODE:
4698	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4699	if ( !pLeaf
4700	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4701	{
4702	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4703	return;
4704	}
4705
4706	/* Valid for both Intel and AMD. */
4707	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4708	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4709	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4710	break;
4711
4712	/*
4713	* Set the NX/XD bit in the extended feature mask.
4714	* Assumes the caller knows what it's doing! (host must support these)
4715	*/
4716	case CPUMCPUIDFEATURE_NX:
4717	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4718	if ( !pLeaf
4719	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4720	{
4721	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4722	return;
4723	}
4724
4725	/* Valid for both Intel and AMD. */
4726	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4727	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4728	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4729	break;
4730
4731
4732	/*
4733	* Set the LAHF/SAHF support in 64-bit mode.
4734	* Assumes the caller knows what it's doing! (host must support this)
4735	*/
4736	case CPUMCPUIDFEATURE_LAHF:
4737	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4738	if ( !pLeaf
4739	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4740	{
4741	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4742	return;
4743	}
4744
4745	/* Valid for both Intel and AMD. */
4746	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4747	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4748	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4749	break;
4750
4751	/*
4752	* Set the page attribute table bit. This is alternative page level
4753	* cache control that doesn't much matter when everything is
4754	* virtualized, though it may when passing thru device memory.
4755	*/
4756	case CPUMCPUIDFEATURE_PAT:
4757	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4758	if (pLeaf)
4759	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4760
4761	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4762	if ( pLeaf
4763	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4764	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4765
4766	pVM->cpum.s.GuestFeatures.fPat = 1;
4767	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4768	break;
4769
4770	/*
4771	* Set the RDTSCP support bit.
4772	* Assumes the caller knows what it's doing! (host must support this)
4773	*/
4774	case CPUMCPUIDFEATURE_RDTSCP:
4775	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4776	if ( !pLeaf
4777	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4778	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4779	{
4780	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4781	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4782	return;
4783	}
4784
4785	/* Valid for both Intel and AMD. */
4786	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4787	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4788	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4789	break;
4790
4791	/*
4792	* Set the Hypervisor Present bit in the standard feature mask.
4793	*/
4794	case CPUMCPUIDFEATURE_HVP:
4795	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4796	if (pLeaf)
4797	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4798	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4799	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4800	break;
4801
4802	/*
4803	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4804	* This currently includes the Present bit and MWAITBREAK bit as well.
4805	*/
4806	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4807	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4808	if ( !pLeaf
4809	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4810	{
4811	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4812	return;
4813	}
4814
4815	/* Valid for both Intel and AMD. */
4816	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4817	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4818	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4819	break;
4820
4821	/*
4822	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
4823	* on Intel CPUs, and different on AMDs.
4824	*/
4825	case CPUMCPUIDFEATURE_SPEC_CTRL:
4826	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4827	{
4828	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4829	if ( !pLeaf
4830	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
4831	{
4832	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4833	return;
4834	}
4835
4836	/* The feature can be enabled. Let's see what we can actually do. */
4837	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4838
4839	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4840	if (pVM->cpum.s.HostFeatures.fIbrs)
4841	{
4842	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4843	pVM->cpum.s.GuestFeatures.fIbrs = 1;
4844	if (pVM->cpum.s.HostFeatures.fStibp)
4845	{
4846	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4847	pVM->cpum.s.GuestFeatures.fStibp = 1;
4848	}
4849
4850	/* Make sure we have the speculation control MSR... */
4851	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4852	if (!pMsrRange)
4853	{
4854	static CPUMMSRRANGE const s_SpecCtrl =
4855	{
4856	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
4857	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
4858	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4859	/.szName = / "IA32_SPEC_CTRL"
4860	};
4861	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4862	AssertLogRelRC(rc);
4863	}
4864
4865	/* ... and the predictor command MSR. */
4866	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
4867	if (!pMsrRange)
4868	{
4869	/** @todo incorrect fWrGpMask. */
4870	static CPUMMSRRANGE const s_SpecCtrl =
4871	{
4872	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
4873	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
4874	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4875	/.szName = / "IA32_PRED_CMD"
4876	};
4877	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4878	AssertLogRelRC(rc);
4879	}
4880
4881	}
4882
4883	if (pVM->cpum.s.HostFeatures.fArchCap)
4884	{
4885	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
4886
4887	/* Install the architectural capabilities MSR. */
4888	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
4889	if (!pMsrRange)
4890	{
4891	static CPUMMSRRANGE const s_ArchCaps =
4892	{
4893	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
4894	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
4895	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
4896	/.szName = / "IA32_ARCH_CAPABILITIES"
4897	};
4898	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
4899	AssertLogRelRC(rc);
4900	}
4901	}
4902
4903	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
4904	}
4905	else if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4906	{
4907	/* The precise details of AMD's implementation are not yet clear. */
4908	}
4909	break;
4910
4911	default:
4912	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4913	break;
4914	}
4915
4916	/** @todo can probably kill this as this API is now init time only... */
4917	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4918	{
4919	PVMCPU pVCpu = &pVM->aCpus[i];
4920	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4921	}
4922	}
4923
4924
4925	/**
4926	* Queries a CPUID feature bit.
4927	*
4928	* @returns boolean for feature presence
4929	* @param pVM The cross context VM structure.
4930	* @param enmFeature The feature to query.
4931	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4932	*/
4933	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4934	{
4935	switch (enmFeature)
4936	{
4937	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4938	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4939	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4940	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4941	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4942	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4943	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4944	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4945	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4946	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4947	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4948	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4949	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
4950
4951	case CPUMCPUIDFEATURE_INVALID:
4952	case CPUMCPUIDFEATURE_32BIT_HACK:
4953	break;
4954	}
4955	AssertFailed();
4956	return false;
4957	}
4958
4959
4960	/**
4961	* Clears a CPUID feature bit.
4962	*
4963	* @param pVM The cross context VM structure.
4964	* @param enmFeature The feature to clear.
4965	*
4966	* @deprecated Probably better to default the feature to disabled and only allow
4967	* setting (enabling) it during construction.
4968	*/
4969	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4970	{
4971	PCPUMCPUIDLEAF pLeaf;
4972	switch (enmFeature)
4973	{
4974	case CPUMCPUIDFEATURE_APIC:
4975	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
4976	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4977	if (pLeaf)
4978	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
4979
4980	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4981	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4982	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4983
4984	pVM->cpum.s.GuestFeatures.fApic = 0;
4985	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4986	break;
4987
4988	case CPUMCPUIDFEATURE_X2APIC:
4989	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4990	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4991	if (pLeaf)
4992	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
4993	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
4994	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
4995	break;
4996
4997	case CPUMCPUIDFEATURE_PAE:
4998	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4999	if (pLeaf)
5000	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
5001
5002	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5003	if ( pLeaf
5004	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
5005	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
5006
5007	pVM->cpum.s.GuestFeatures.fPae = 0;
5008	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
5009	break;
5010
5011	case CPUMCPUIDFEATURE_PAT:
5012	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5013	if (pLeaf)
5014	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
5015
5016	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5017	if ( pLeaf
5018	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
5019	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
5020
5021	pVM->cpum.s.GuestFeatures.fPat = 0;
5022	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
5023	break;
5024
5025	case CPUMCPUIDFEATURE_LONG_MODE:
5026	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5027	if (pLeaf)
5028	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
5029	pVM->cpum.s.GuestFeatures.fLongMode = 0;
5030	break;
5031
5032	case CPUMCPUIDFEATURE_LAHF:
5033	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5034	if (pLeaf)
5035	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
5036	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
5037	break;
5038
5039	case CPUMCPUIDFEATURE_RDTSCP:
5040	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5041	if (pLeaf)
5042	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
5043	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
5044	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
5045	break;
5046
5047	case CPUMCPUIDFEATURE_HVP:
5048	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5049	if (pLeaf)
5050	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
5051	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
5052	break;
5053
5054	case CPUMCPUIDFEATURE_MWAIT_EXTS:
5055	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
5056	if (pLeaf)
5057	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
5058	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
5059	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
5060	break;
5061
5062	case CPUMCPUIDFEATURE_SPEC_CTRL:
5063	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
5064	if (pLeaf)
5065	pLeaf->uEdx &= ~( X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP
5066	\| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
5067	pVM->cpum.s.GuestFeatures.fSpeculationControl = 0;
5068	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
5069	break;
5070
5071	default:
5072	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5073	break;
5074	}
5075
5076	for (VMCPUID i = 0; i < pVM->cCpus; i++)
5077	{
5078	PVMCPU pVCpu = &pVM->aCpus[i];
5079	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5080	}
5081	}
5082
5083
5084
5085	/*
5086	*
5087	*
5088	* Saved state related code.
5089	* Saved state related code.
5090	* Saved state related code.
5091	*
5092	*
5093	*/
5094
5095	/**
5096	* Called both in pass 0 and the final pass.
5097	*
5098	* @param pVM The cross context VM structure.
5099	* @param pSSM The saved state handle.
5100	*/
5101	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
5102	{
5103	/*
5104	* Save all the CPU ID leaves.
5105	*/
5106	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
5107	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5108	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
5109	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5110
5111	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5112
5113	/*
5114	* Save a good portion of the raw CPU IDs as well as they may come in
5115	* handy when validating features for raw mode.
5116	*/
5117	CPUMCPUID aRawStd[16];
5118	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
5119	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5120	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
5121	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
5122
5123	CPUMCPUID aRawExt[32];
5124	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
5125	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5126	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
5127	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
5128	}
5129
5130
5131	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5132	{
5133	uint32_t cCpuIds;
5134	int rc = SSMR3GetU32(pSSM, &cCpuIds);
5135	if (RT_SUCCESS(rc))
5136	{
5137	if (cCpuIds < 64)
5138	{
5139	for (uint32_t i = 0; i < cCpuIds; i++)
5140	{
5141	CPUMCPUID CpuId;
5142	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
5143	if (RT_FAILURE(rc))
5144	break;
5145
5146	CPUMCPUIDLEAF NewLeaf;
5147	NewLeaf.uLeaf = uBase + i;
5148	NewLeaf.uSubLeaf = 0;
5149	NewLeaf.fSubLeafMask = 0;
5150	NewLeaf.uEax = CpuId.uEax;
5151	NewLeaf.uEbx = CpuId.uEbx;
5152	NewLeaf.uEcx = CpuId.uEcx;
5153	NewLeaf.uEdx = CpuId.uEdx;
5154	NewLeaf.fFlags = 0;
5155	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
5156	}
5157	}
5158	else
5159	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5160	}
5161	if (RT_FAILURE(rc))
5162	{
5163	RTMemFree(*ppaLeaves);
5164	*ppaLeaves = NULL;
5165	*pcLeaves = 0;
5166	}
5167	return rc;
5168	}
5169
5170
5171	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5172	{
5173	*ppaLeaves = NULL;
5174	*pcLeaves = 0;
5175
5176	int rc;
5177	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
5178	{
5179	/*
5180	* The new format. Starts by declaring the leave size and count.
5181	*/
5182	uint32_t cbLeaf;
5183	SSMR3GetU32(pSSM, &cbLeaf);
5184	uint32_t cLeaves;
5185	rc = SSMR3GetU32(pSSM, &cLeaves);
5186	if (RT_SUCCESS(rc))
5187	{
5188	if (cbLeaf == sizeof(**ppaLeaves))
5189	{
5190	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
5191	{
5192	/*
5193	* Load the leaves one by one.
5194	*
5195	* The uPrev stuff is a kludge for working around a week worth of bad saved
5196	* states during the CPUID revamp in March 2015. We saved too many leaves
5197	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
5198	* garbage entires at the end of the array when restoring. We also had
5199	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
5200	* this kludge doesn't deal correctly with that, but who cares...
5201	*/
5202	uint32_t uPrev = 0;
5203	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
5204	{
5205	CPUMCPUIDLEAF Leaf;
5206	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5207	if (RT_SUCCESS(rc))
5208	{
5209	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5210	\|\| Leaf.uLeaf >= uPrev)
5211	{
5212	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5213	uPrev = Leaf.uLeaf;
5214	}
5215	else
5216	uPrev = UINT32_MAX;
5217	}
5218	}
5219	}
5220	else
5221	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5222	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5223	}
5224	else
5225	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5226	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5227	}
5228	}
5229	else
5230	{
5231	/*
5232	* The old format with its three inflexible arrays.
5233	*/
5234	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5235	if (RT_SUCCESS(rc))
5236	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5237	if (RT_SUCCESS(rc))
5238	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5239	if (RT_SUCCESS(rc))
5240	{
5241	/*
5242	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5243	*/
5244	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5245	if ( pLeaf
5246	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5247	{
5248	CPUMCPUIDLEAF Leaf;
5249	Leaf.uLeaf = 4;
5250	Leaf.fSubLeafMask = UINT32_MAX;
5251	Leaf.uSubLeaf = 0;
5252	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5253	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5254	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5255	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5256	\| UINT32_C(63); /* system coherency line size - 1 */
5257	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5258	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5259	\| (UINT32_C(1) << 5) /* cache level */
5260	\| UINT32_C(1); /* cache type (data) */
5261	Leaf.fFlags = 0;
5262	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5263	if (RT_SUCCESS(rc))
5264	{
5265	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5266	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5267	}
5268	if (RT_SUCCESS(rc))
5269	{
5270	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5271	Leaf.uEcx = 4095; /* sets - 1 */
5272	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5273	Leaf.uEbx \|= UINT32_C(23) << 22;
5274	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5275	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5276	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5277	Leaf.uEax \|= UINT32_C(2) << 5;
5278	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5279	}
5280	}
5281	}
5282	}
5283	return rc;
5284	}
5285
5286
5287	/**
5288	* Loads the CPU ID leaves saved by pass 0, inner worker.
5289	*
5290	* @returns VBox status code.
5291	* @param pVM The cross context VM structure.
5292	* @param pSSM The saved state handle.
5293	* @param uVersion The format version.
5294	* @param paLeaves Guest CPUID leaves loaded from the state.
5295	* @param cLeaves The number of leaves in @a paLeaves.
5296	* @param pMsrs The guest MSRs.
5297	*/
5298	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
5299	{
5300	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5301
5302	/*
5303	* Continue loading the state into stack buffers.
5304	*/
5305	CPUMCPUID GuestDefCpuId;
5306	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5307	AssertRCReturn(rc, rc);
5308
5309	CPUMCPUID aRawStd[16];
5310	uint32_t cRawStd;
5311	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5312	if (cRawStd > RT_ELEMENTS(aRawStd))
5313	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5314	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5315	AssertRCReturn(rc, rc);
5316	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5317	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5318
5319	CPUMCPUID aRawExt[32];
5320	uint32_t cRawExt;
5321	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5322	if (cRawExt > RT_ELEMENTS(aRawExt))
5323	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5324	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5325	AssertRCReturn(rc, rc);
5326	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5327	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5328
5329	/*
5330	* Get the raw CPU IDs for the current host.
5331	*/
5332	CPUMCPUID aHostRawStd[16];
5333	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5334	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5335
5336	CPUMCPUID aHostRawExt[32];
5337	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5338	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5339	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5340
5341	/*
5342	* Get the host and guest overrides so we don't reject the state because
5343	* some feature was enabled thru these interfaces.
5344	* Note! We currently only need the feature leaves, so skip rest.
5345	*/
5346	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5347	CPUMCPUID aHostOverrideStd[2];
5348	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5349	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5350
5351	CPUMCPUID aHostOverrideExt[2];
5352	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5353	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5354
5355	/*
5356	* This can be skipped.
5357	*/
5358	bool fStrictCpuIdChecks;
5359	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5360
5361	/*
5362	* Define a bunch of macros for simplifying the santizing/checking code below.
5363	*/
5364	/* Generic expression + failure message. */
5365	#define CPUID_CHECK_RET(expr, fmt) \
5366	do { \
5367	if (!(expr)) \
5368	{ \
5369	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5370	if (fStrictCpuIdChecks) \
5371	{ \
5372	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5373	RTStrFree(pszMsg); \
5374	return rcCpuid; \
5375	} \
5376	LogRel(("CPUM: %s\n", pszMsg)); \
5377	RTStrFree(pszMsg); \
5378	} \
5379	} while (0)
5380	#define CPUID_CHECK_WRN(expr, fmt) \
5381	do { \
5382	if (!(expr)) \
5383	LogRel(fmt); \
5384	} while (0)
5385
5386	/* For comparing two values and bitch if they differs. */
5387	#define CPUID_CHECK2_RET(what, host, saved) \
5388	do { \
5389	if ((host) != (saved)) \
5390	{ \
5391	if (fStrictCpuIdChecks) \
5392	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5393	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5394	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5395	} \
5396	} while (0)
5397	#define CPUID_CHECK2_WRN(what, host, saved) \
5398	do { \
5399	if ((host) != (saved)) \
5400	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5401	} while (0)
5402
5403	/* For checking raw cpu features (raw mode). */
5404	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5405	do { \
5406	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5407	{ \
5408	if (fStrictCpuIdChecks) \
5409	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5410	N_(#bit " mismatch: host=%d saved=%d"), \
5411	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5412	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5413	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5414	} \
5415	} while (0)
5416	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5417	do { \
5418	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5419	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5420	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5421	} while (0)
5422	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5423
5424	/* For checking guest features. */
5425	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5426	do { \
5427	if ( (aGuestCpuId##set [1].reg & bit) \
5428	&& !(aHostRaw##set [1].reg & bit) \
5429	&& !(aHostOverride##set [1].reg & bit) \
5430	) \
5431	{ \
5432	if (fStrictCpuIdChecks) \
5433	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5434	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5435	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5436	} \
5437	} while (0)
5438	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5439	do { \
5440	if ( (aGuestCpuId##set [1].reg & bit) \
5441	&& !(aHostRaw##set [1].reg & bit) \
5442	&& !(aHostOverride##set [1].reg & bit) \
5443	) \
5444	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5445	} while (0)
5446	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5447	do { \
5448	if ( (aGuestCpuId##set [1].reg & bit) \
5449	&& !(aHostRaw##set [1].reg & bit) \
5450	&& !(aHostOverride##set [1].reg & bit) \
5451	) \
5452	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5453	} while (0)
5454	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5455
5456	/* For checking guest features if AMD guest CPU. */
5457	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5458	do { \
5459	if ( (aGuestCpuId##set [1].reg & bit) \
5460	&& fGuestAmd \
5461	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5462	&& !(aHostOverride##set [1].reg & bit) \
5463	) \
5464	{ \
5465	if (fStrictCpuIdChecks) \
5466	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5467	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5468	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5469	} \
5470	} while (0)
5471	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5472	do { \
5473	if ( (aGuestCpuId##set [1].reg & bit) \
5474	&& fGuestAmd \
5475	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5476	&& !(aHostOverride##set [1].reg & bit) \
5477	) \
5478	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5479	} while (0)
5480	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5481	do { \
5482	if ( (aGuestCpuId##set [1].reg & bit) \
5483	&& fGuestAmd \
5484	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5485	&& !(aHostOverride##set [1].reg & bit) \
5486	) \
5487	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5488	} while (0)
5489	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5490
5491	/* For checking AMD features which have a corresponding bit in the standard
5492	range. (Intel defines very few bits in the extended feature sets.) */
5493	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5494	do { \
5495	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5496	&& !(fHostAmd \
5497	? aHostRawExt[1].reg & (ExtBit) \
5498	: aHostRawStd[1].reg & (StdBit)) \
5499	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5500	) \
5501	{ \
5502	if (fStrictCpuIdChecks) \
5503	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5504	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5505	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5506	} \
5507	} while (0)
5508	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5509	do { \
5510	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5511	&& !(fHostAmd \
5512	? aHostRawExt[1].reg & (ExtBit) \
5513	: aHostRawStd[1].reg & (StdBit)) \
5514	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5515	) \
5516	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5517	} while (0)
5518	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5519	do { \
5520	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5521	&& !(fHostAmd \
5522	? aHostRawExt[1].reg & (ExtBit) \
5523	: aHostRawStd[1].reg & (StdBit)) \
5524	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5525	) \
5526	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5527	} while (0)
5528	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5529
5530	/*
5531	* For raw-mode we'll require that the CPUs are very similar since we don't
5532	* intercept CPUID instructions for user mode applications.
5533	*/
5534	if (VM_IS_RAW_MODE_ENABLED(pVM))
5535	{
5536	/* CPUID(0) */
5537	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
5538	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
5539	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
5540	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5541	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
5542	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
5543	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
5544	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
5545	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5546
5547	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
5548
5549	/* CPUID(1).eax */
5550	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
5551	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
5552	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
5553
5554	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
5555	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
5556	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
5557
5558	/* CPUID(1).ecx */
5559	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
5560	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
5561	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
5562	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5563	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
5564	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
5565	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
5566	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
5567	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
5568	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
5569	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
5570	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
5571	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
5572	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
5573	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
5574	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
5575	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5576	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5577	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
5578	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
5579	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
5580	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5581	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
5582	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
5583	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5584	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
5585	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
5586	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5587	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
5588	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5589	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5590	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
5591
5592	/* CPUID(1).edx */
5593	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5594	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5595	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
5596	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5597	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
5598	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
5599	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5600	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5601	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
5602	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5603	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5604	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5605	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5606	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5607	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5608	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
5609	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5610	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5611	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5612	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
5613	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5614	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
5615	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
5616	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
5617	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
5618	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
5619	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
5620	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
5621	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
5622	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
5623	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
5624	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
5625
5626	/* CPUID(2) - config, mostly about caches. ignore. */
5627	/* CPUID(3) - processor serial number. ignore. */
5628	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
5629	/* CPUID(5) - mwait/monitor config. ignore. */
5630	/* CPUID(6) - power management. ignore. */
5631	/* CPUID(7) - ???. ignore. */
5632	/* CPUID(8) - ???. ignore. */
5633	/* CPUID(9) - DCA. ignore for now. */
5634	/* CPUID(a) - PeMo info. ignore for now. */
5635	/* CPUID(b) - topology info - takes ECX as input. ignore. */
5636
5637	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
5638	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
5639	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
5640	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
5641	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
5642	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
5643	{
5644	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
5645	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
5646	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
5647	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
5648	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
5649	}
5650
5651	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
5652	Note! Intel have/is marking many of the fields here as reserved. We
5653	will verify them as if it's an AMD CPU. */
5654	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
5655	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
5656	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
5657	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
5658	{
5659	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
5660	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
5661	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
5662	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5663	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
5664	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
5665	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
5666
5667	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
5668	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
5669	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
5670	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
5671	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
5672	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5673
5674	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
5675	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
5676	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
5677	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
5678
5679	/* CPUID(0x80000001).ecx */
5680	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
5681	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
5682	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
5683	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
5684	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
5685	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
5686	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
5687	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
5688	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
5689	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
5690	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
5691	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
5692	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
5693	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
5694	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5695	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5696	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5697	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5698	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5699	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5700	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5701	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5702	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5703	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5704	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5705	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5706	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5707	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5708	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5709	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5710	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5711	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5712
5713	/* CPUID(0x80000001).edx */
5714	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
5715	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
5716	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
5717	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
5718	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
5719	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
5720	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
5721	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
5722	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
5723	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
5724	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5725	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
5726	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
5727	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
5728	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
5729	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
5730	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
5731	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
5732	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5733	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5734	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5735	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
5736	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5737	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
5738	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
5739	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5740	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5741	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5742	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
5743	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5744	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5745	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5746
5747	/** @todo verify the rest as well. */
5748	}
5749	}
5750
5751
5752
5753	/*
5754	* Verify that we can support the features already exposed to the guest on
5755	* this host.
5756	*
5757	* Most of the features we're emulating requires intercepting instruction
5758	* and doing it the slow way, so there is no need to warn when they aren't
5759	* present in the host CPU. Thus we use IGN instead of EMU on these.
5760	*
5761	* Trailing comments:
5762	* "EMU" - Possible to emulate, could be lots of work and very slow.
5763	* "EMU?" - Can this be emulated?
5764	*/
5765	CPUMCPUID aGuestCpuIdStd[2];
5766	RT_ZERO(aGuestCpuIdStd);
5767	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5768
5769	/* CPUID(1).ecx */
5770	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5771	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5772	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5773	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5774	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5775	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5776	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5777	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5778	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5779	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5780	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5781	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5782	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5783	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5784	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5785	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5786	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5787	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5788	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5789	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5790	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5791	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5792	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5793	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5794	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5795	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5796	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5797	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5798	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5799	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5800	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5801	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5802
5803	/* CPUID(1).edx */
5804	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5805	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5806	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5807	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5808	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5809	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5810	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5811	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5812	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5813	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5814	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5815	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5816	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5817	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5818	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5819	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5820	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5821	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5822	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5823	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5824	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5825	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5826	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5827	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5828	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5829	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5830	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5831	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5832	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5833	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5834	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5835	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5836
5837	/* CPUID(0x80000000). */
5838	CPUMCPUID aGuestCpuIdExt[2];
5839	RT_ZERO(aGuestCpuIdExt);
5840	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5841	{
5842	/** @todo deal with no 0x80000001 on the host. */
5843	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5844	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5845
5846	/* CPUID(0x80000001).ecx */
5847	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5848	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5849	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5850	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5851	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5852	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5853	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5854	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5855	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5856	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5857	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5858	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5859	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5860	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5861	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5862	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5863	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5864	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5865	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5866	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5867	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5868	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5869	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5870	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5871	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5872	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5873	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5874	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5875	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5876	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5877	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5878	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5879
5880	/* CPUID(0x80000001).edx */
5881	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5882	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5883	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5884	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5885	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5886	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5887	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5888	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5889	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5890	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5891	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5892	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5893	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5894	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5895	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5896	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5897	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5898	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5899	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5900	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5901	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5902	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5903	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5904	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5905	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5906	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5907	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5908	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5909	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5910	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5911	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5912	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5913	}
5914
5915	/** @todo check leaf 7 */
5916
5917	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5918	* ECX=0: EAX - Valid bits in XCR0[31:0].
5919	* EBX - Maximum state size as per current XCR0 value.
5920	* ECX - Maximum state size for all supported features.
5921	* EDX - Valid bits in XCR0[63:32].
5922	* ECX=1: EAX - Various X-features.
5923	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5924	* ECX - Valid bits in IA32_XSS[31:0].
5925	* EDX - Valid bits in IA32_XSS[63:32].
5926	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5927	* if the bit invalid all four registers are set to zero.
5928	* EAX - The state size for this feature.
5929	* EBX - The state byte offset of this feature.
5930	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5931	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5932	*/
5933	uint64_t fGuestXcr0Mask = 0;
5934	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5935	if ( pCurLeaf
5936	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5937	&& ( pCurLeaf->uEax
5938	\|\| pCurLeaf->uEbx
5939	\|\| pCurLeaf->uEcx
5940	\|\| pCurLeaf->uEdx) )
5941	{
5942	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5943	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5944	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5945	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5946	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5947	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5948	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5949	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5950
5951	/* We don't support any additional features yet. */
5952	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5953	if (pCurLeaf && pCurLeaf->uEax)
5954	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5955	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5956	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5957	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5958	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5959	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5960
5961
5962	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5963	{
5964	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5965	if (pCurLeaf)
5966	{
5967	/* If advertised, the state component offset and size must match the one used by host. */
5968	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5969	{
5970	CPUMCPUID RawHost;
5971	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5972	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5973	if ( RawHost.uEbx != pCurLeaf->uEbx
5974	\|\| RawHost.uEax != pCurLeaf->uEax)
5975	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5976	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5977	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5978	}
5979	}
5980	}
5981	}
5982	/* Clear leaf 0xd just in case we're loading an old state... */
5983	else if (pCurLeaf)
5984	{
5985	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5986	{
5987	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5988	if (pCurLeaf)
5989	{
5990	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5991	\|\| ( pCurLeaf->uEax == 0
5992	&& pCurLeaf->uEbx == 0
5993	&& pCurLeaf->uEcx == 0
5994	&& pCurLeaf->uEdx == 0),
5995	("uVersion=%#x; %#x %#x %#x %#x\n",
5996	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5997	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5998	}
5999	}
6000	}
6001
6002	/* Update the fXStateGuestMask value for the VM. */
6003	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
6004	{
6005	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
6006	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
6007	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
6008	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
6009	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
6010	}
6011
6012	#undef CPUID_CHECK_RET
6013	#undef CPUID_CHECK_WRN
6014	#undef CPUID_CHECK2_RET
6015	#undef CPUID_CHECK2_WRN
6016	#undef CPUID_RAW_FEATURE_RET
6017	#undef CPUID_RAW_FEATURE_WRN
6018	#undef CPUID_RAW_FEATURE_IGN
6019	#undef CPUID_GST_FEATURE_RET
6020	#undef CPUID_GST_FEATURE_WRN
6021	#undef CPUID_GST_FEATURE_EMU
6022	#undef CPUID_GST_FEATURE_IGN
6023	#undef CPUID_GST_FEATURE2_RET
6024	#undef CPUID_GST_FEATURE2_WRN
6025	#undef CPUID_GST_FEATURE2_EMU
6026	#undef CPUID_GST_FEATURE2_IGN
6027	#undef CPUID_GST_AMD_FEATURE_RET
6028	#undef CPUID_GST_AMD_FEATURE_WRN
6029	#undef CPUID_GST_AMD_FEATURE_EMU
6030	#undef CPUID_GST_AMD_FEATURE_IGN
6031
6032	/*
6033	* We're good, commit the CPU ID leaves.
6034	*/
6035	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
6036	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
6037	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
6038	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
6039	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
6040	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
6041	AssertLogRelRCReturn(rc, rc);
6042
6043	return VINF_SUCCESS;
6044	}
6045
6046
6047	/**
6048	* Loads the CPU ID leaves saved by pass 0.
6049	*
6050	* @returns VBox status code.
6051	* @param pVM The cross context VM structure.
6052	* @param pSSM The saved state handle.
6053	* @param uVersion The format version.
6054	* @param pMsrs The guest MSRs.
6055	*/
6056	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
6057	{
6058	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
6059
6060	/*
6061	* Load the CPUID leaves array first and call worker to do the rest, just so
6062	* we can free the memory when we need to without ending up in column 1000.
6063	*/
6064	PCPUMCPUIDLEAF paLeaves;
6065	uint32_t cLeaves;
6066	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
6067	AssertRC(rc);
6068	if (RT_SUCCESS(rc))
6069	{
6070	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
6071	RTMemFree(paLeaves);
6072	}
6073	return rc;
6074	}
6075
6076
6077
6078	/**
6079	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
6080	*
6081	* @returns VBox status code.
6082	* @param pVM The cross context VM structure.
6083	* @param pSSM The saved state handle.
6084	* @param uVersion The format version.
6085	*/
6086	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
6087	{
6088	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
6089
6090	/*
6091	* Restore the CPUID leaves.
6092	*
6093	* Note that we support restoring less than the current amount of standard
6094	* leaves because we've been allowed more is newer version of VBox.
6095	*/
6096	uint32_t cElements;
6097	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6098	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
6099	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6100	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
6101
6102	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6103	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
6104	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6105	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
6106
6107	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6108	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
6109	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6110	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
6111
6112	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
6113
6114	/*
6115	* Check that the basic cpuid id information is unchanged.
6116	*/
6117	/** @todo we should check the 64 bits capabilities too! */
6118	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
6119	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
6120	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
6121	uint32_t au32CpuIdSaved[8];
6122	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
6123	if (RT_SUCCESS(rc))
6124	{
6125	/* Ignore CPU stepping. */
6126	au32CpuId[4] &= 0xfffffff0;
6127	au32CpuIdSaved[4] &= 0xfffffff0;
6128
6129	/* Ignore APIC ID (AMD specs). */
6130	au32CpuId[5] &= ~0xff000000;
6131	au32CpuIdSaved[5] &= ~0xff000000;
6132
6133	/* Ignore the number of Logical CPUs (AMD specs). */
6134	au32CpuId[5] &= ~0x00ff0000;
6135	au32CpuIdSaved[5] &= ~0x00ff0000;
6136
6137	/* Ignore some advanced capability bits, that we don't expose to the guest. */
6138	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6139	\| X86_CPUID_FEATURE_ECX_VMX
6140	\| X86_CPUID_FEATURE_ECX_SMX
6141	\| X86_CPUID_FEATURE_ECX_EST
6142	\| X86_CPUID_FEATURE_ECX_TM2
6143	\| X86_CPUID_FEATURE_ECX_CNTXID
6144	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6145	\| X86_CPUID_FEATURE_ECX_PDCM
6146	\| X86_CPUID_FEATURE_ECX_DCA
6147	\| X86_CPUID_FEATURE_ECX_X2APIC
6148	);
6149	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6150	\| X86_CPUID_FEATURE_ECX_VMX
6151	\| X86_CPUID_FEATURE_ECX_SMX
6152	\| X86_CPUID_FEATURE_ECX_EST
6153	\| X86_CPUID_FEATURE_ECX_TM2
6154	\| X86_CPUID_FEATURE_ECX_CNTXID
6155	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6156	\| X86_CPUID_FEATURE_ECX_PDCM
6157	\| X86_CPUID_FEATURE_ECX_DCA
6158	\| X86_CPUID_FEATURE_ECX_X2APIC
6159	);
6160
6161	/* Make sure we don't forget to update the masks when enabling
6162	* features in the future.
6163	*/
6164	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
6165	( X86_CPUID_FEATURE_ECX_DTES64
6166	\| X86_CPUID_FEATURE_ECX_VMX
6167	\| X86_CPUID_FEATURE_ECX_SMX
6168	\| X86_CPUID_FEATURE_ECX_EST
6169	\| X86_CPUID_FEATURE_ECX_TM2
6170	\| X86_CPUID_FEATURE_ECX_CNTXID
6171	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6172	\| X86_CPUID_FEATURE_ECX_PDCM
6173	\| X86_CPUID_FEATURE_ECX_DCA
6174	\| X86_CPUID_FEATURE_ECX_X2APIC
6175	)));
6176	/* do the compare */
6177	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
6178	{
6179	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
6180	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
6181	"Saved=%.*Rhxs\n"
6182	"Real =%.*Rhxs\n",
6183	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6184	sizeof(au32CpuId), au32CpuId));
6185	else
6186	{
6187	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
6188	"Saved=%.*Rhxs\n"
6189	"Real =%.*Rhxs\n",
6190	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6191	sizeof(au32CpuId), au32CpuId));
6192	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
6193	}
6194	}
6195	}
6196
6197	return rc;
6198	}
6199
6200
6201
6202	/*
6203	*
6204	*
6205	* CPUID Info Handler.
6206	* CPUID Info Handler.
6207	* CPUID Info Handler.
6208	*
6209	*
6210	*/
6211
6212
6213
6214	/**
6215	* Get L1 cache / TLS associativity.
6216	*/
6217	static const char getCacheAss(unsigned u, char pszBuf)
6218	{
6219	if (u == 0)
6220	return "res0 ";
6221	if (u == 1)
6222	return "direct";
6223	if (u == 255)
6224	return "fully";
6225	if (u >= 256)
6226	return "???";
6227
6228	RTStrPrintf(pszBuf, 16, "%d way", u);
6229	return pszBuf;
6230	}
6231
6232
6233	/**
6234	* Get L2 cache associativity.
6235	*/
6236	const char *getL2CacheAss(unsigned u)
6237	{
6238	switch (u)
6239	{
6240	case 0: return "off ";
6241	case 1: return "direct";
6242	case 2: return "2 way ";
6243	case 3: return "res3 ";
6244	case 4: return "4 way ";
6245	case 5: return "res5 ";
6246	case 6: return "8 way ";
6247	case 7: return "res7 ";
6248	case 8: return "16 way";
6249	case 9: return "res9 ";
6250	case 10: return "res10 ";
6251	case 11: return "res11 ";
6252	case 12: return "res12 ";
6253	case 13: return "res13 ";
6254	case 14: return "res14 ";
6255	case 15: return "fully ";
6256	default: return "????";
6257	}
6258	}
6259
6260
6261	/** CPUID(1).EDX field descriptions. */
6262	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6263	{
6264	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6265	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6266	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6267	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6268	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6269	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6270	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6271	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6272	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6273	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6274	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6275	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6276	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6277	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6278	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6279	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6280	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6281	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6282	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6283	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6284	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6285	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6286	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6287	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6288	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6289	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6290	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6291	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6292	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6293	DBGFREGSUBFIELD_TERMINATOR()
6294	};
6295
6296	/** CPUID(1).ECX field descriptions. */
6297	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6298	{
6299	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6300	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6301	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6302	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6303	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6304	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6305	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6306	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6307	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6308	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6309	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6310	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6311	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6312	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6313	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6314	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6315	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6316	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6317	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6318	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6319	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6320	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6321	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6322	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6323	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6324	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6325	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6326	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6327	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6328	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6329	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6330	DBGFREGSUBFIELD_TERMINATOR()
6331	};
6332
6333	/** CPUID(7,0).EBX field descriptions. */
6334	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6335	{
6336	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6337	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6338	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6339	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6340	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6341	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6342	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6343	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6344	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6345	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6346	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6347	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6348	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6349	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6350	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6351	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6352	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6353	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6354	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6355	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6356	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6357	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6358	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6359	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6360	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6361	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6362	DBGFREGSUBFIELD_TERMINATOR()
6363	};
6364
6365	/** CPUID(7,0).ECX field descriptions. */
6366	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6367	{
6368	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6369	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6370	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6371	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6372	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6373	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6374	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6375	DBGFREGSUBFIELD_TERMINATOR()
6376	};
6377
6378	/** CPUID(7,0).EDX field descriptions. */
6379	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6380	{
6381	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6382	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6383	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
6384	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6385	DBGFREGSUBFIELD_TERMINATOR()
6386	};
6387
6388
6389	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6390	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6391	{
6392	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6393	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6394	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6395	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6396	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6397	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6398	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6399	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6400	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6401	DBGFREGSUBFIELD_TERMINATOR()
6402	};
6403
6404	/** CPUID(13,1).EAX field descriptions. */
6405	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6406	{
6407	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6408	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6409	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6410	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6411	DBGFREGSUBFIELD_TERMINATOR()
6412	};
6413
6414
6415	/** CPUID(0x80000001,0).EDX field descriptions. */
6416	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6417	{
6418	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6419	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6420	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6421	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6422	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6423	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6424	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6425	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6426	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6427	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6428	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6429	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6430	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6431	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6432	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6433	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6434	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6435	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6436	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6437	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6438	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6439	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6440	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6441	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6442	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6443	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6444	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6445	DBGFREGSUBFIELD_TERMINATOR()
6446	};
6447
6448	/** CPUID(0x80000001,0).ECX field descriptions. */
6449	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6450	{
6451	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6452	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6453	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6454	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6455	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6456	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6457	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6458	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6459	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6460	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6461	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6462	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6463	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6464	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6465	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6466	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6467	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6468	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6469	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6470	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6471	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6472	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6473	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6474	DBGFREGSUBFIELD_TERMINATOR()
6475	};
6476
6477	/** CPUID(0x8000000a,0).EDX field descriptions. */
6478	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6479	{
6480	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6481	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6482	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6483	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6484	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6485	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6486	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6487	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6488	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6489	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6490	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6491	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6492	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6493	DBGFREGSUBFIELD_TERMINATOR()
6494	};
6495
6496
6497	/** CPUID(0x80000007,0).EDX field descriptions. */
6498	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6499	{
6500	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6501	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6502	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6503	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6504	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6505	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6506	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6507	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6508	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6509	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6510	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6511	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6512	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6513	DBGFREGSUBFIELD_TERMINATOR()
6514	};
6515
6516	/** CPUID(0x80000008,0).EBX field descriptions. */
6517	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6518	{
6519	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6520	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6521	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6522	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6523	DBGFREGSUBFIELD_TERMINATOR()
6524	};
6525
6526
6527	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6528	const char *pszLeadIn, uint32_t cchWidth)
6529	{
6530	if (pszLeadIn)
6531	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6532
6533	for (uint32_t iBit = 0; iBit < 32; iBit++)
6534	if (RT_BIT_32(iBit) & uVal)
6535	{
6536	while ( pDesc->pszName != NULL
6537	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6538	pDesc++;
6539	if ( pDesc->pszName != NULL
6540	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6541	{
6542	if (pDesc->cBits == 1)
6543	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6544	else
6545	{
6546	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6547	if (pDesc->cBits < 32)
6548	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6549	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6550	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6551	}
6552	}
6553	else
6554	pHlp->pfnPrintf(pHlp, " %u", iBit);
6555	}
6556	if (pszLeadIn)
6557	pHlp->pfnPrintf(pHlp, "\n");
6558	}
6559
6560
6561	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6562	const char *pszLeadIn, uint32_t cchWidth)
6563	{
6564	if (pszLeadIn)
6565	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6566
6567	for (uint32_t iBit = 0; iBit < 64; iBit++)
6568	if (RT_BIT_64(iBit) & uVal)
6569	{
6570	while ( pDesc->pszName != NULL
6571	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6572	pDesc++;
6573	if ( pDesc->pszName != NULL
6574	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6575	{
6576	if (pDesc->cBits == 1)
6577	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6578	else
6579	{
6580	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6581	if (pDesc->cBits < 64)
6582	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6583	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6584	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6585	}
6586	}
6587	else
6588	pHlp->pfnPrintf(pHlp, " %u", iBit);
6589	}
6590	if (pszLeadIn)
6591	pHlp->pfnPrintf(pHlp, "\n");
6592	}
6593
6594
6595	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6596	const char *pszLeadIn, uint32_t cchWidth)
6597	{
6598	if (!uVal)
6599	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6600	else
6601	{
6602	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6603	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6604	pHlp->pfnPrintf(pHlp, " )\n");
6605	}
6606	}
6607
6608
6609	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6610	uint32_t cchWidth)
6611	{
6612	uint32_t uCombined = uVal1 \| uVal2;
6613	for (uint32_t iBit = 0; iBit < 32; iBit++)
6614	if ( (RT_BIT_32(iBit) & uCombined)
6615	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6616	{
6617	while ( pDesc->pszName != NULL
6618	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6619	pDesc++;
6620
6621	if ( pDesc->pszName != NULL
6622	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6623	{
6624	size_t cchMnemonic = strlen(pDesc->pszName);
6625	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6626	size_t cchDesc = strlen(pszDesc);
6627	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6628	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6629	if (pDesc->cBits < 32)
6630	{
6631	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6632	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6633	}
6634
6635	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6636	pDesc->pszName, pszDesc,
6637	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6638	uFieldValue1, uFieldValue2);
6639
6640	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6641	pDesc++;
6642	}
6643	else
6644	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6645	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6646	}
6647	}
6648
6649
6650	/**
6651	* Produces a detailed summary of standard leaf 0x00000001.
6652	*
6653	* @param pHlp The info helper functions.
6654	* @param pCurLeaf The 0x00000001 leaf.
6655	* @param fVerbose Whether to be very verbose or not.
6656	* @param fIntel Set if intel CPU.
6657	*/
6658	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6659	{
6660	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6661	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6662	uint32_t uEAX = pCurLeaf->uEax;
6663	uint32_t uEBX = pCurLeaf->uEbx;
6664
6665	pHlp->pfnPrintf(pHlp,
6666	"%36s %2d \tExtended: %d \tEffective: %d\n"
6667	"%36s %2d \tExtended: %d \tEffective: %d\n"
6668	"%36s %d\n"
6669	"%36s %d (%s)\n"
6670	"%36s %#04x\n"
6671	"%36s %d\n"
6672	"%36s %d\n"
6673	"%36s %#04x\n"
6674	,
6675	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6676	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6677	"Stepping:", ASMGetCpuStepping(uEAX),
6678	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6679	"APIC ID:", (uEBX >> 24) & 0xff,
6680	"Logical CPUs:",(uEBX >> 16) & 0xff,
6681	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6682	"Brand ID:", (uEBX >> 0) & 0xff);
6683	if (fVerbose)
6684	{
6685	CPUMCPUID Host;
6686	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6687	pHlp->pfnPrintf(pHlp, "Features\n");
6688	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6689	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6690	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6691	}
6692	else
6693	{
6694	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6695	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6696	}
6697	}
6698
6699
6700	/**
6701	* Produces a detailed summary of standard leaf 0x00000007.
6702	*
6703	* @param pHlp The info helper functions.
6704	* @param paLeaves The CPUID leaves array.
6705	* @param cLeaves The number of leaves in the array.
6706	* @param pCurLeaf The first 0x00000007 leaf.
6707	* @param fVerbose Whether to be very verbose or not.
6708	*/
6709	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6710	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6711	{
6712	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6713	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6714	for (;;)
6715	{
6716	CPUMCPUID Host;
6717	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6718
6719	switch (pCurLeaf->uSubLeaf)
6720	{
6721	case 0:
6722	if (fVerbose)
6723	{
6724	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6725	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6726	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6727	if (pCurLeaf->uEdx \|\| Host.uEdx)
6728	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6729	}
6730	else
6731	{
6732	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6733	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6734	if (pCurLeaf->uEdx)
6735	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6736	}
6737	break;
6738
6739	default:
6740	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6741	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6742	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6743	break;
6744
6745	}
6746
6747	/* advance. */
6748	pCurLeaf++;
6749	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6750	\|\| pCurLeaf->uLeaf != 0x7)
6751	break;
6752	}
6753	}
6754
6755
6756	/**
6757	* Produces a detailed summary of standard leaf 0x0000000d.
6758	*
6759	* @param pHlp The info helper functions.
6760	* @param paLeaves The CPUID leaves array.
6761	* @param cLeaves The number of leaves in the array.
6762	* @param pCurLeaf The first 0x00000007 leaf.
6763	* @param fVerbose Whether to be very verbose or not.
6764	*/
6765	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6766	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6767	{
6768	RT_NOREF_PV(fVerbose);
6769	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6770	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6771	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6772	{
6773	CPUMCPUID Host;
6774	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6775
6776	switch (uSubLeaf)
6777	{
6778	case 0:
6779	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6780	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6781	pCurLeaf->uEbx, pCurLeaf->uEcx);
6782	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6783
6784	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6785	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6786	"Valid XCR0 bits, guest:", 42);
6787	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6788	"Valid XCR0 bits, host:", 42);
6789	break;
6790
6791	case 1:
6792	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6793	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6794	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6795
6796	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6797	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6798	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6799
6800	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6801	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6802	" Valid IA32_XSS bits, guest:", 42);
6803	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6804	" Valid IA32_XSS bits, host:", 42);
6805	break;
6806
6807	default:
6808	if ( pCurLeaf
6809	&& pCurLeaf->uSubLeaf == uSubLeaf
6810	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6811	{
6812	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6813	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6814	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6815	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6816	if (pCurLeaf->uEdx)
6817	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6818	pHlp->pfnPrintf(pHlp, " --");
6819	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6820	pHlp->pfnPrintf(pHlp, "\n");
6821	}
6822	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6823	{
6824	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6825	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6826	if (Host.uEcx & ~RT_BIT_32(0))
6827	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6828	if (Host.uEdx)
6829	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6830	pHlp->pfnPrintf(pHlp, " --");
6831	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6832	pHlp->pfnPrintf(pHlp, "\n");
6833	}
6834	break;
6835
6836	}
6837
6838	/* advance. */
6839	if (pCurLeaf)
6840	{
6841	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6842	&& pCurLeaf->uSubLeaf <= uSubLeaf
6843	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6844	pCurLeaf++;
6845	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6846	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6847	pCurLeaf = NULL;
6848	}
6849	}
6850	}
6851
6852
6853	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6854	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6855	{
6856	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6857	&& pCurLeaf->uLeaf <= uUpToLeaf)
6858	{
6859	pHlp->pfnPrintf(pHlp,
6860	" %s\n"
6861	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6862	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6863	&& pCurLeaf->uLeaf <= uUpToLeaf)
6864	{
6865	CPUMCPUID Host;
6866	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6867	pHlp->pfnPrintf(pHlp,
6868	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6869	"Hst: %08x %08x %08x %08x\n",
6870	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6871	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6872	pCurLeaf++;
6873	}
6874	}
6875
6876	return pCurLeaf;
6877	}
6878
6879
6880	/**
6881	* Display the guest CpuId leaves.
6882	*
6883	* @param pVM The cross context VM structure.
6884	* @param pHlp The info helper functions.
6885	* @param pszArgs "terse", "default" or "verbose".
6886	*/
6887	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6888	{
6889	/*
6890	* Parse the argument.
6891	*/
6892	unsigned iVerbosity = 1;
6893	if (pszArgs)
6894	{
6895	pszArgs = RTStrStripL(pszArgs);
6896	if (!strcmp(pszArgs, "terse"))
6897	iVerbosity--;
6898	else if (!strcmp(pszArgs, "verbose"))
6899	iVerbosity++;
6900	}
6901
6902	uint32_t uLeaf;
6903	CPUMCPUID Host;
6904	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6905	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6906	PCCPUMCPUIDLEAF pCurLeaf;
6907	PCCPUMCPUIDLEAF pNextLeaf;
6908	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6909	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6910	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6911
6912	/*
6913	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6914	*/
6915	uint32_t cHstMax = ASMCpuId_EAX(0);
6916	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6917	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6918	pHlp->pfnPrintf(pHlp,
6919	" Raw Standard CPUID Leaves\n"
6920	" Leaf/sub-leaf eax ebx ecx edx\n");
6921	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6922	{
6923	uint32_t cMaxSubLeaves = 1;
6924	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6925	cMaxSubLeaves = 16;
6926	else if (uLeaf == 0xd)
6927	cMaxSubLeaves = 128;
6928
6929	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6930	{
6931	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6932	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6933	&& pCurLeaf->uLeaf == uLeaf
6934	&& pCurLeaf->uSubLeaf == uSubLeaf)
6935	{
6936	pHlp->pfnPrintf(pHlp,
6937	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6938	"Hst: %08x %08x %08x %08x\n",
6939	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6940	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6941	pCurLeaf++;
6942	}
6943	else if ( uLeaf != 0xd
6944	\|\| uSubLeaf <= 1
6945	\|\| Host.uEbx != 0 )
6946	pHlp->pfnPrintf(pHlp,
6947	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6948	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6949
6950	/* Done? */
6951	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6952	\|\| pCurLeaf->uLeaf != uLeaf)
6953	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6954	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6955	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6956	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6957	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6958	)
6959	)
6960	break;
6961	}
6962	}
6963	pNextLeaf = pCurLeaf;
6964
6965	/*
6966	* If verbose, decode it.
6967	*/
6968	if (iVerbosity && paLeaves[0].uLeaf == 0)
6969	pHlp->pfnPrintf(pHlp,
6970	"%36s %.04s%.04s%.04s\n"
6971	"%36s 0x00000000-%#010x\n"
6972	,
6973	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6974	"Supports:", paLeaves[0].uEax);
6975
6976	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6977	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6978
6979	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6980	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6981
6982	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6983	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6984
6985	pCurLeaf = pNextLeaf;
6986
6987	/*
6988	* Hypervisor leaves.
6989	*
6990	* Unlike most of the other leaves reported, the guest hypervisor leaves
6991	* aren't a subset of the host CPUID bits.
6992	*/
6993	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6994
6995	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6996	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6997	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6998	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6999	cMax = RT_MAX(cHstMax, cGstMax);
7000	if (cMax >= UINT32_C(0x40000000))
7001	{
7002	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
7003
7004	/** @todo dump these in more detail. */
7005
7006	pCurLeaf = pNextLeaf;
7007	}
7008
7009
7010	/*
7011	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
7012	* Implemented after AMD specs.
7013	*/
7014	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
7015
7016	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7017	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
7018	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
7019	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
7020	cMax = RT_MAX(cHstMax, cGstMax);
7021	if (cMax >= UINT32_C(0x80000000))
7022	{
7023
7024	pHlp->pfnPrintf(pHlp,
7025	" Raw Extended CPUID Leaves\n"
7026	" Leaf/sub-leaf eax ebx ecx edx\n");
7027	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
7028	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
7029	{
7030	uint32_t cMaxSubLeaves = 1;
7031	if (uLeaf == UINT32_C(0x8000001d))
7032	cMaxSubLeaves = 16;
7033
7034	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
7035	{
7036	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7037	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
7038	&& pCurLeaf->uLeaf == uLeaf
7039	&& pCurLeaf->uSubLeaf == uSubLeaf)
7040	{
7041	pHlp->pfnPrintf(pHlp,
7042	"Gst: %08x/%04x %08x %08x %08x %08x\n"
7043	"Hst: %08x %08x %08x %08x\n",
7044	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
7045	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
7046	pCurLeaf++;
7047	}
7048	else if ( uLeaf != 0xd
7049	\|\| uSubLeaf <= 1
7050	\|\| Host.uEbx != 0 )
7051	pHlp->pfnPrintf(pHlp,
7052	"Hst: %08x/%04x %08x %08x %08x %08x\n",
7053	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
7054
7055	/* Done? */
7056	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
7057	\|\| pCurLeaf->uLeaf != uLeaf)
7058	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
7059	break;
7060	}
7061	}
7062	pNextLeaf = pCurLeaf;
7063
7064	/*
7065	* Understandable output
7066	*/
7067	if (iVerbosity)
7068	pHlp->pfnPrintf(pHlp,
7069	"Ext Name: %.4s%.4s%.4s\n"
7070	"Ext Supports: 0x80000000-%#010x\n",
7071	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
7072
7073	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
7074	if (iVerbosity && pCurLeaf)
7075	{
7076	uint32_t uEAX = pCurLeaf->uEax;
7077	pHlp->pfnPrintf(pHlp,
7078	"Family: %d \tExtended: %d \tEffective: %d\n"
7079	"Model: %d \tExtended: %d \tEffective: %d\n"
7080	"Stepping: %d\n"
7081	"Brand ID: %#05x\n",
7082	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
7083	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
7084	ASMGetCpuStepping(uEAX),
7085	pCurLeaf->uEbx & 0xfff);
7086
7087	if (iVerbosity == 1)
7088	{
7089	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
7090	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
7091	}
7092	else
7093	{
7094	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7095	pHlp->pfnPrintf(pHlp, "Ext Features\n");
7096	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
7097	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
7098	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
7099	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
7100	{
7101	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
7102	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7103	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
7104	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
7105	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
7106	}
7107	}
7108	}
7109
7110	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
7111	{
7112	char szString[443+1] = {0};
7113	uint32_t pu32 = (uint32_t )szString;
7114	*pu32++ = pCurLeaf->uEax;
7115	*pu32++ = pCurLeaf->uEbx;
7116	*pu32++ = pCurLeaf->uEcx;
7117	*pu32++ = pCurLeaf->uEdx;
7118	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
7119	if (pCurLeaf)
7120	{
7121	*pu32++ = pCurLeaf->uEax;
7122	*pu32++ = pCurLeaf->uEbx;
7123	*pu32++ = pCurLeaf->uEcx;
7124	*pu32++ = pCurLeaf->uEdx;
7125	}
7126	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
7127	if (pCurLeaf)
7128	{
7129	*pu32++ = pCurLeaf->uEax;
7130	*pu32++ = pCurLeaf->uEbx;
7131	*pu32++ = pCurLeaf->uEcx;
7132	*pu32++ = pCurLeaf->uEdx;
7133	}
7134	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
7135	}
7136
7137	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
7138	{
7139	uint32_t uEAX = pCurLeaf->uEax;
7140	uint32_t uEBX = pCurLeaf->uEbx;
7141	uint32_t uECX = pCurLeaf->uEcx;
7142	uint32_t uEDX = pCurLeaf->uEdx;
7143	char sz1[32];
7144	char sz2[32];
7145
7146	pHlp->pfnPrintf(pHlp,
7147	"TLB 2/4M Instr/Uni: %s %3d entries\n"
7148	"TLB 2/4M Data: %s %3d entries\n",
7149	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
7150	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
7151	pHlp->pfnPrintf(pHlp,
7152	"TLB 4K Instr/Uni: %s %3d entries\n"
7153	"TLB 4K Data: %s %3d entries\n",
7154	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
7155	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
7156	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
7157	"L1 Instr Cache Lines Per Tag: %d\n"
7158	"L1 Instr Cache Associativity: %s\n"
7159	"L1 Instr Cache Size: %d KB\n",
7160	(uEDX >> 0) & 0xff,
7161	(uEDX >> 8) & 0xff,
7162	getCacheAss((uEDX >> 16) & 0xff, sz1),
7163	(uEDX >> 24) & 0xff);
7164	pHlp->pfnPrintf(pHlp,
7165	"L1 Data Cache Line Size: %d bytes\n"
7166	"L1 Data Cache Lines Per Tag: %d\n"
7167	"L1 Data Cache Associativity: %s\n"
7168	"L1 Data Cache Size: %d KB\n",
7169	(uECX >> 0) & 0xff,
7170	(uECX >> 8) & 0xff,
7171	getCacheAss((uECX >> 16) & 0xff, sz1),
7172	(uECX >> 24) & 0xff);
7173	}
7174
7175	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
7176	{
7177	uint32_t uEAX = pCurLeaf->uEax;
7178	uint32_t uEBX = pCurLeaf->uEbx;
7179	uint32_t uEDX = pCurLeaf->uEdx;
7180
7181	pHlp->pfnPrintf(pHlp,
7182	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
7183	"L2 TLB 2/4M Data: %s %4d entries\n",
7184	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
7185	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
7186	pHlp->pfnPrintf(pHlp,
7187	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
7188	"L2 TLB 4K Data: %s %4d entries\n",
7189	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
7190	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
7191	pHlp->pfnPrintf(pHlp,
7192	"L2 Cache Line Size: %d bytes\n"
7193	"L2 Cache Lines Per Tag: %d\n"
7194	"L2 Cache Associativity: %s\n"
7195	"L2 Cache Size: %d KB\n",
7196	(uEDX >> 0) & 0xff,
7197	(uEDX >> 8) & 0xf,
7198	getL2CacheAss((uEDX >> 12) & 0xf),
7199	(uEDX >> 16) & 0xffff);
7200	}
7201
7202	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
7203	{
7204	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7205	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
7206	{
7207	if (iVerbosity < 1)
7208	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7209	else
7210	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7211	}
7212	}
7213
7214	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7215	if (pCurLeaf != NULL)
7216	{
7217	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7218	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7219	{
7220	if (iVerbosity < 1)
7221	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7222	else
7223	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7224	}
7225
7226	if (iVerbosity)
7227	{
7228	uint32_t uEAX = pCurLeaf->uEax;
7229	uint32_t uECX = pCurLeaf->uEcx;
7230
7231	pHlp->pfnPrintf(pHlp,
7232	"Physical Address Width: %d bits\n"
7233	"Virtual Address Width: %d bits\n"
7234	"Guest Physical Address Width: %d bits\n",
7235	(uEAX >> 0) & 0xff,
7236	(uEAX >> 8) & 0xff,
7237	(uEAX >> 16) & 0xff);
7238	pHlp->pfnPrintf(pHlp,
7239	"Physical Core Count: %d\n",
7240	((uECX >> 0) & 0xff) + 1);
7241	}
7242	}
7243
7244	pCurLeaf = pNextLeaf;
7245	}
7246
7247
7248
7249	/*
7250	* Centaur.
7251	*/
7252	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7253
7254	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7255	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7256	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7257	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7258	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7259	cMax = RT_MAX(cHstMax, cGstMax);
7260	if (cMax >= UINT32_C(0xc0000000))
7261	{
7262	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7263
7264	/*
7265	* Understandable output
7266	*/
7267	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7268	pHlp->pfnPrintf(pHlp,
7269	"Centaur Supports: 0xc0000000-%#010x\n",
7270	pCurLeaf->uEax);
7271
7272	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7273	{
7274	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7275	uint32_t uEdxGst = pCurLeaf->uEdx;
7276	uint32_t uEdxHst = Host.uEdx;
7277
7278	if (iVerbosity == 1)
7279	{
7280	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7281	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7282	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7283	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7284	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7285	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7286	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7287	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7288	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7289	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7290	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7291	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7292	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7293	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7294	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7295	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7296	for (unsigned iBit = 14; iBit < 32; iBit++)
7297	if (uEdxGst & RT_BIT(iBit))
7298	pHlp->pfnPrintf(pHlp, " %d", iBit);
7299	pHlp->pfnPrintf(pHlp, "\n");
7300	}
7301	else
7302	{
7303	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7304	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7305	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7306	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7307	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7308	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7309	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7310	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7311	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7312	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7313	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7314	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7315	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7316	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7317	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7318	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7319	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7320	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7321	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7322	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7323	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7324	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7325	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7326	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7327	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7328	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7329	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7330	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7331	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7332	for (unsigned iBit = 27; iBit < 32; iBit++)
7333	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7334	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7335	pHlp->pfnPrintf(pHlp, "\n");
7336	}
7337	}
7338
7339	pCurLeaf = pNextLeaf;
7340	}
7341
7342	/*
7343	* The remainder.
7344	*/
7345	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7346	}
7347
7348
7349
7350
7351
7352	/*
7353	*
7354	*
7355	* PATM interfaces.
7356	* PATM interfaces.
7357	* PATM interfaces.
7358	*
7359	*
7360	*/
7361
7362
7363	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
7364	/** @name Patchmanager CPUID legacy table APIs
7365	* @{
7366	*/
7367
7368	/**
7369	* Gets a pointer to the default CPUID leaf.
7370	*
7371	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
7372	* @param pVM The cross context VM structure.
7373	* @remark Intended for PATM only.
7374	*/
7375	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
7376	{
7377	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
7378	}
7379
7380
7381	/**
7382	* Gets a number of standard CPUID leaves (PATM only).
7383	*
7384	* @returns Number of leaves.
7385	* @param pVM The cross context VM structure.
7386	* @remark Intended for PATM - legacy, don't use in new code.
7387	*/
7388	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
7389	{
7390	RT_NOREF_PV(pVM);
7391	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
7392	}
7393
7394
7395	/**
7396	* Gets a number of extended CPUID leaves (PATM only).
7397	*
7398	* @returns Number of leaves.
7399	* @param pVM The cross context VM structure.
7400	* @remark Intended for PATM - legacy, don't use in new code.
7401	*/
7402	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
7403	{
7404	RT_NOREF_PV(pVM);
7405	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
7406	}
7407
7408
7409	/**
7410	* Gets a number of centaur CPUID leaves.
7411	*
7412	* @returns Number of leaves.
7413	* @param pVM The cross context VM structure.
7414	* @remark Intended for PATM - legacy, don't use in new code.
7415	*/
7416	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
7417	{
7418	RT_NOREF_PV(pVM);
7419	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
7420	}
7421
7422
7423	/**
7424	* Gets a pointer to the array of standard CPUID leaves.
7425	*
7426	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
7427	*
7428	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
7429	* @param pVM The cross context VM structure.
7430	* @remark Intended for PATM - legacy, don't use in new code.
7431	*/
7432	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
7433	{
7434	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
7435	}
7436
7437
7438	/**
7439	* Gets a pointer to the array of extended CPUID leaves.
7440	*
7441	* CPUMGetGuestCpuIdExtMax() give the size of the array.
7442	*
7443	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
7444	* @param pVM The cross context VM structure.
7445	* @remark Intended for PATM - legacy, don't use in new code.
7446	*/
7447	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
7448	{
7449	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
7450	}
7451
7452
7453	/**
7454	* Gets a pointer to the array of centaur CPUID leaves.
7455	*
7456	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
7457	*
7458	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
7459	* @param pVM The cross context VM structure.
7460	* @remark Intended for PATM - legacy, don't use in new code.
7461	*/
7462	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
7463	{
7464	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
7465	}
7466
7467	/** @} */
7468	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
7469
7470	#endif /* VBOX_IN_VMM */
7471

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 76886

Download in other formats: