CPUMR3CpuId.cpp@ 78425

Last change on this file since 78425 was 77032, checked in by vboxsync, 6 years ago
VMM/CPUM: bugref:9375 Check for existence of leafs before exploding SVM features.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 349.0 KB

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1	/* $Id: CPUMR3CpuId.cpp 77032 2019-01-29 14:28:03Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/mm.h>
31	#include <VBox/sup.h>
32
33	#include <VBox/err.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/ctype.h>
36	#include <iprt/mem.h>
37	#include <iprt/string.h>
38
39
40	/*********************************************************************************************************************************
41	* Defined Constants And Macros *
42	*********************************************************************************************************************************/
43	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
44	#define CPUM_CPUID_MAX_LEAVES 2048
45	/* Max size we accept for the XSAVE area. */
46	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
47	/* Min size we accept for the XSAVE area. */
48	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
49
50
51	/*********************************************************************************************************************************
52	* Global Variables *
53	*********************************************************************************************************************************/
54	/**
55	* The intel pentium family.
56	*/
57	static const CPUMMICROARCH g_aenmIntelFamily06[] =
58	{
59	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
60	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
61	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
63	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
64	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
65	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
66	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
67	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
68	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
69	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
70	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
71	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
72	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
73	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
74	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
75	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
81	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
82	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
83	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
86	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
88	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
89	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
90	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
91	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
97	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
98	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
99	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
102	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
104	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
105	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
106	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
107	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
113	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
114	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
115	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
118	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
121	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
122	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
130	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
131	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
136	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [78(0x4e)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed */
138	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / unconfirmed, Broadwell-E */
139	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu */
145	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
146	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
147	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
150	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
152	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
153	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
154	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
155	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
159	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
160	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
161	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
162	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
163	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
164	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
165	/[106(0x6a)] = / kCpumMicroarch_Intel_Unknown,
166	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
167	/[108(0x6c)] = / kCpumMicroarch_Intel_Unknown,
168	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
169	/[110(0x6e)] = / kCpumMicroarch_Intel_Unknown,
170	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
171	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
172	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
173	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
174	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
175	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
176	/[117(0x75)] = / kCpumMicroarch_Intel_Unknown,
177	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
178	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
179	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
180	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
181	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
182	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
183	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
184	/[125(0x7d)] = / kCpumMicroarch_Intel_Unknown,
185	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
186	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
187	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
188	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
189	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
190	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
191	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
192	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
193	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
194	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
195	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
196	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
197	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
198	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
199	/[140(0x8c)] = / kCpumMicroarch_Intel_Unknown,
200	/[141(0x8d)] = / kCpumMicroarch_Intel_Unknown,
201	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
202	/[143(0x8f)] = / kCpumMicroarch_Intel_Unknown,
203	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
204	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
205	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
206	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
207	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
208	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
209	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
210	/[151(0x97)] = / kCpumMicroarch_Intel_Unknown,
211	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
212	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
213	/[154(0x9a)] = / kCpumMicroarch_Intel_Unknown,
214	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
215	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
216	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
217	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
218	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
219	};
220	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0x9f+1);
221
222
223	/**
224	* Figures out the (sub-)micro architecture given a bit of CPUID info.
225	*
226	* @returns Micro architecture.
227	* @param enmVendor The CPU vendor .
228	* @param bFamily The CPU family.
229	* @param bModel The CPU model.
230	* @param bStepping The CPU stepping.
231	*/
232	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
233	uint8_t bModel, uint8_t bStepping)
234	{
235	if (enmVendor == CPUMCPUVENDOR_AMD)
236	{
237	switch (bFamily)
238	{
239	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
240	case 0x03: return kCpumMicroarch_AMD_Am386;
241	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
242	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
243	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
244	case 0x06:
245	switch (bModel)
246	{
247	case 0: return kCpumMicroarch_AMD_K7_Palomino;
248	case 1: return kCpumMicroarch_AMD_K7_Palomino;
249	case 2: return kCpumMicroarch_AMD_K7_Palomino;
250	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
251	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
252	case 6: return kCpumMicroarch_AMD_K7_Palomino;
253	case 7: return kCpumMicroarch_AMD_K7_Morgan;
254	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
255	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
256	}
257	return kCpumMicroarch_AMD_K7_Unknown;
258	case 0x0f:
259	/*
260	* This family is a friggin mess. Trying my best to make some
261	* sense out of it. Too much happened in the 0x0f family to
262	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
263	*
264	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
265	* cpu-world.com, and other places:
266	* - 130nm:
267	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
268	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
269	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
270	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
271	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
272	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
273	* - 90nm:
274	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
275	* - Oakville: 10FC0/DH-D0.
276	* - Georgetown: 10FC0/DH-D0.
277	* - Sonora: 10FC0/DH-D0.
278	* - Venus: 20F71/SH-E4
279	* - Troy: 20F51/SH-E4
280	* - Athens: 20F51/SH-E4
281	* - San Diego: 20F71/SH-E4.
282	* - Lancaster: 20F42/SH-E5
283	* - Newark: 20F42/SH-E5.
284	* - Albany: 20FC2/DH-E6.
285	* - Roma: 20FC2/DH-E6.
286	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
287	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
288	* - 90nm introducing Dual core:
289	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
290	* - Italy: 20F10/JH-E1, 20F12/JH-E6
291	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
292	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
293	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
294	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
295	* - Santa Ana: 40F32/JH-F2, /-F3
296	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
297	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
298	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
299	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
300	* - Keene: 40FC2/DH-F2.
301	* - Richmond: 40FC2/DH-F2
302	* - Taylor: 40F82/BH-F2
303	* - Trinidad: 40F82/BH-F2
304	*
305	* - 65nm:
306	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
307	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
308	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
309	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
310	* - Sherman: /-G1, 70FC2/DH-G2.
311	* - Huron: 70FF2/DH-G2.
312	*/
313	if (bModel < 0x10)
314	return kCpumMicroarch_AMD_K8_130nm;
315	if (bModel >= 0x60 && bModel < 0x80)
316	return kCpumMicroarch_AMD_K8_65nm;
317	if (bModel >= 0x40)
318	return kCpumMicroarch_AMD_K8_90nm_AMDV;
319	switch (bModel)
320	{
321	case 0x21:
322	case 0x23:
323	case 0x2b:
324	case 0x2f:
325	case 0x37:
326	case 0x3f:
327	return kCpumMicroarch_AMD_K8_90nm_DualCore;
328	}
329	return kCpumMicroarch_AMD_K8_90nm;
330	case 0x10:
331	return kCpumMicroarch_AMD_K10;
332	case 0x11:
333	return kCpumMicroarch_AMD_K10_Lion;
334	case 0x12:
335	return kCpumMicroarch_AMD_K10_Llano;
336	case 0x14:
337	return kCpumMicroarch_AMD_Bobcat;
338	case 0x15:
339	switch (bModel)
340	{
341	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
342	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
343	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
344	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
345	case 0x11: /* ?? */
346	case 0x12: /* ?? */
347	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
348	}
349	return kCpumMicroarch_AMD_15h_Unknown;
350	case 0x16:
351	return kCpumMicroarch_AMD_Jaguar;
352	case 0x17:
353	return kCpumMicroarch_AMD_Zen_Ryzen;
354	}
355	return kCpumMicroarch_AMD_Unknown;
356	}
357
358	if (enmVendor == CPUMCPUVENDOR_INTEL)
359	{
360	switch (bFamily)
361	{
362	case 3:
363	return kCpumMicroarch_Intel_80386;
364	case 4:
365	return kCpumMicroarch_Intel_80486;
366	case 5:
367	return kCpumMicroarch_Intel_P5;
368	case 6:
369	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
370	{
371	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
372	if ( enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake
373	&& bStepping >= 0xa)
374	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
375	return enmMicroArch;
376	}
377	return kCpumMicroarch_Intel_Atom_Unknown;
378	case 15:
379	switch (bModel)
380	{
381	case 0: return kCpumMicroarch_Intel_NB_Willamette;
382	case 1: return kCpumMicroarch_Intel_NB_Willamette;
383	case 2: return kCpumMicroarch_Intel_NB_Northwood;
384	case 3: return kCpumMicroarch_Intel_NB_Prescott;
385	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
386	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
387	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
388	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
389	default: return kCpumMicroarch_Intel_NB_Unknown;
390	}
391	break;
392	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
393	case 0:
394	return kCpumMicroarch_Intel_8086;
395	case 1:
396	return kCpumMicroarch_Intel_80186;
397	case 2:
398	return kCpumMicroarch_Intel_80286;
399	}
400	return kCpumMicroarch_Intel_Unknown;
401	}
402
403	if (enmVendor == CPUMCPUVENDOR_VIA)
404	{
405	switch (bFamily)
406	{
407	case 5:
408	switch (bModel)
409	{
410	case 1: return kCpumMicroarch_Centaur_C6;
411	case 4: return kCpumMicroarch_Centaur_C6;
412	case 8: return kCpumMicroarch_Centaur_C2;
413	case 9: return kCpumMicroarch_Centaur_C3;
414	}
415	break;
416
417	case 6:
418	switch (bModel)
419	{
420	case 5: return kCpumMicroarch_VIA_C3_M2;
421	case 6: return kCpumMicroarch_VIA_C3_C5A;
422	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
423	case 8: return kCpumMicroarch_VIA_C3_C5N;
424	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
425	case 10: return kCpumMicroarch_VIA_C7_C5J;
426	case 15: return kCpumMicroarch_VIA_Isaiah;
427	}
428	break;
429	}
430	return kCpumMicroarch_VIA_Unknown;
431	}
432
433	if (enmVendor == CPUMCPUVENDOR_SHANGHAI)
434	{
435	switch (bFamily)
436	{
437	case 6:
438	case 7:
439	return kCpumMicroarch_Shanghai_Wudaokou;
440	default:
441	break;
442	}
443	return kCpumMicroarch_Shanghai_Unknown;
444	}
445
446	if (enmVendor == CPUMCPUVENDOR_CYRIX)
447	{
448	switch (bFamily)
449	{
450	case 4:
451	switch (bModel)
452	{
453	case 9: return kCpumMicroarch_Cyrix_5x86;
454	}
455	break;
456
457	case 5:
458	switch (bModel)
459	{
460	case 2: return kCpumMicroarch_Cyrix_M1;
461	case 4: return kCpumMicroarch_Cyrix_MediaGX;
462	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
463	}
464	break;
465
466	case 6:
467	switch (bModel)
468	{
469	case 0: return kCpumMicroarch_Cyrix_M2;
470	}
471	break;
472
473	}
474	return kCpumMicroarch_Cyrix_Unknown;
475	}
476
477	return kCpumMicroarch_Unknown;
478	}
479
480
481	/**
482	* Translates a microarchitecture enum value to the corresponding string
483	* constant.
484	*
485	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
486	* NULL if the value is invalid.
487	*
488	* @param enmMicroarch The enum value to convert.
489	*/
490	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
491	{
492	switch (enmMicroarch)
493	{
494	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
495	CASE_RET_STR(kCpumMicroarch_Intel_8086);
496	CASE_RET_STR(kCpumMicroarch_Intel_80186);
497	CASE_RET_STR(kCpumMicroarch_Intel_80286);
498	CASE_RET_STR(kCpumMicroarch_Intel_80386);
499	CASE_RET_STR(kCpumMicroarch_Intel_80486);
500	CASE_RET_STR(kCpumMicroarch_Intel_P5);
501
502	CASE_RET_STR(kCpumMicroarch_Intel_P6);
503	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
504	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
505
506	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
507	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
508	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
509
510	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
511	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
512
513	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
514	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
515	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
516	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
517	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
518	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
519	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
520	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
521	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
522	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
523	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
524	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
525
526	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
527	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
528	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
529	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
530	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
531	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
532	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
533	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
534
535	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
536	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
537	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
538	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
539	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
540
541	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
542	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
543	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
544	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
545	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
546	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
547	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
548
549	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
550
551	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
552	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
553	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
554	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
555	CASE_RET_STR(kCpumMicroarch_AMD_K5);
556	CASE_RET_STR(kCpumMicroarch_AMD_K6);
557
558	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
559	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
560	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
561	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
562	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
563	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
564	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
565
566	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
567	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
568	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
569	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
570	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
571
572	CASE_RET_STR(kCpumMicroarch_AMD_K10);
573	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
574	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
575	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
576	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
577
578	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
579	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
580	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
581	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
582	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
583
584	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
585
586	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
587
588	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
589
590	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
591	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
592	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
593	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
594	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
595	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
596	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
597	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
598	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
599	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
600	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
601	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
602	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
603
604	CASE_RET_STR(kCpumMicroarch_Shanghai_Wudaokou);
605	CASE_RET_STR(kCpumMicroarch_Shanghai_Unknown);
606
607	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
608	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
609	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
610	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
611	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
612	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
613
614	CASE_RET_STR(kCpumMicroarch_NEC_V20);
615	CASE_RET_STR(kCpumMicroarch_NEC_V30);
616
617	CASE_RET_STR(kCpumMicroarch_Unknown);
618
619	#undef CASE_RET_STR
620	case kCpumMicroarch_Invalid:
621	case kCpumMicroarch_Intel_End:
622	case kCpumMicroarch_Intel_Core2_End:
623	case kCpumMicroarch_Intel_Core7_End:
624	case kCpumMicroarch_Intel_Atom_End:
625	case kCpumMicroarch_Intel_P6_Core_Atom_End:
626	case kCpumMicroarch_Intel_Phi_End:
627	case kCpumMicroarch_Intel_NB_End:
628	case kCpumMicroarch_AMD_K7_End:
629	case kCpumMicroarch_AMD_K8_End:
630	case kCpumMicroarch_AMD_15h_End:
631	case kCpumMicroarch_AMD_16h_End:
632	case kCpumMicroarch_AMD_Zen_End:
633	case kCpumMicroarch_AMD_End:
634	case kCpumMicroarch_VIA_End:
635	case kCpumMicroarch_Cyrix_End:
636	case kCpumMicroarch_NEC_End:
637	case kCpumMicroarch_Shanghai_End:
638	case kCpumMicroarch_32BitHack:
639	break;
640	/* no default! */
641	}
642
643	return NULL;
644	}
645
646
647	/**
648	* Determins the host CPU MXCSR mask.
649	*
650	* @returns MXCSR mask.
651	*/
652	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
653	{
654	if ( ASMHasCpuId()
655	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
656	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
657	{
658	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
659	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
660	RT_ZERO(*pState);
661	ASMFxSave(pState);
662	if (pState->MXCSR_MASK == 0)
663	return 0xffbf;
664	return pState->MXCSR_MASK;
665	}
666	return 0;
667	}
668
669
670	/**
671	* Gets a matching leaf in the CPUID leaf array.
672	*
673	* @returns Pointer to the matching leaf, or NULL if not found.
674	* @param paLeaves The CPUID leaves to search. This is sorted.
675	* @param cLeaves The number of leaves in the array.
676	* @param uLeaf The leaf to locate.
677	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
678	*/
679	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
680	{
681	/* Lazy bird does linear lookup here since this is only used for the
682	occational CPUID overrides. */
683	for (uint32_t i = 0; i < cLeaves; i++)
684	if ( paLeaves[i].uLeaf == uLeaf
685	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
686	return &paLeaves[i];
687	return NULL;
688	}
689
690
691	#ifndef IN_VBOX_CPU_REPORT
692	/**
693	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
694	*
695	* @returns true if found, false it not.
696	* @param paLeaves The CPUID leaves to search. This is sorted.
697	* @param cLeaves The number of leaves in the array.
698	* @param uLeaf The leaf to locate.
699	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
700	* @param pLegacy The legacy output leaf.
701	*/
702	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
703	PCPUMCPUID pLegacy)
704	{
705	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
706	if (pLeaf)
707	{
708	pLegacy->uEax = pLeaf->uEax;
709	pLegacy->uEbx = pLeaf->uEbx;
710	pLegacy->uEcx = pLeaf->uEcx;
711	pLegacy->uEdx = pLeaf->uEdx;
712	return true;
713	}
714	return false;
715	}
716	#endif /* IN_VBOX_CPU_REPORT */
717
718
719	/**
720	* Ensures that the CPUID leaf array can hold one more leaf.
721	*
722	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
723	* failure.
724	* @param pVM The cross context VM structure. If NULL, use
725	* the process heap, otherwise the VM's hyper heap.
726	* @param ppaLeaves Pointer to the variable holding the array pointer
727	* (input/output).
728	* @param cLeaves The current array size.
729	*
730	* @remarks This function will automatically update the R0 and RC pointers when
731	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
732	* be the corresponding VM's CPUID arrays (which is asserted).
733	*/
734	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
735	{
736	/*
737	* If pVM is not specified, we're on the regular heap and can waste a
738	* little space to speed things up.
739	*/
740	uint32_t cAllocated;
741	if (!pVM)
742	{
743	cAllocated = RT_ALIGN(cLeaves, 16);
744	if (cLeaves + 1 > cAllocated)
745	{
746	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
747	if (pvNew)
748	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
749	else
750	{
751	RTMemFree(*ppaLeaves);
752	*ppaLeaves = NULL;
753	}
754	}
755	}
756	/*
757	* Otherwise, we're on the hyper heap and are probably just inserting
758	* one or two leaves and should conserve space.
759	*/
760	else
761	{
762	#ifdef IN_VBOX_CPU_REPORT
763	AssertReleaseFailed();
764	#else
765	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
766	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
767
768	size_t cb = cLeaves * sizeof(**ppaLeaves);
769	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
770	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
771	if (RT_SUCCESS(rc))
772	{
773	/* Update the R0 and RC pointers. */
774	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
775	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
776	}
777	else
778	{
779	*ppaLeaves = NULL;
780	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
781	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
782	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
783	}
784	#endif
785	}
786	return *ppaLeaves;
787	}
788
789
790	/**
791	* Append a CPUID leaf or sub-leaf.
792	*
793	* ASSUMES linear insertion order, so we'll won't need to do any searching or
794	* replace anything. Use cpumR3CpuIdInsert() for those cases.
795	*
796	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
797	* the caller need do no more work.
798	* @param ppaLeaves Pointer to the pointer to the array of sorted
799	* CPUID leaves and sub-leaves.
800	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
801	* @param uLeaf The leaf we're adding.
802	* @param uSubLeaf The sub-leaf number.
803	* @param fSubLeafMask The sub-leaf mask.
804	* @param uEax The EAX value.
805	* @param uEbx The EBX value.
806	* @param uEcx The ECX value.
807	* @param uEdx The EDX value.
808	* @param fFlags The flags.
809	*/
810	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
811	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
812	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
813	{
814	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
815	return VERR_NO_MEMORY;
816
817	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
818	Assert( *pcLeaves == 0
819	\|\| pNew[-1].uLeaf < uLeaf
820	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
821
822	pNew->uLeaf = uLeaf;
823	pNew->uSubLeaf = uSubLeaf;
824	pNew->fSubLeafMask = fSubLeafMask;
825	pNew->uEax = uEax;
826	pNew->uEbx = uEbx;
827	pNew->uEcx = uEcx;
828	pNew->uEdx = uEdx;
829	pNew->fFlags = fFlags;
830
831	*pcLeaves += 1;
832	return VINF_SUCCESS;
833	}
834
835
836	/**
837	* Checks that we've updated the CPUID leaves array correctly.
838	*
839	* This is a no-op in non-strict builds.
840	*
841	* @param paLeaves The leaves array.
842	* @param cLeaves The number of leaves.
843	*/
844	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
845	{
846	#ifdef VBOX_STRICT
847	for (uint32_t i = 1; i < cLeaves; i++)
848	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
849	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
850	else
851	{
852	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
853	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
854	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
855	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
856	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
857	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
858	}
859	#else
860	NOREF(paLeaves);
861	NOREF(cLeaves);
862	#endif
863	}
864
865
866	/**
867	* Inserts a CPU ID leaf, replacing any existing ones.
868	*
869	* When inserting a simple leaf where we already got a series of sub-leaves with
870	* the same leaf number (eax), the simple leaf will replace the whole series.
871	*
872	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
873	* host-context heap and has only been allocated/reallocated by the
874	* cpumR3CpuIdEnsureSpace function.
875	*
876	* @returns VBox status code.
877	* @param pVM The cross context VM structure. If NULL, use
878	* the process heap, otherwise the VM's hyper heap.
879	* @param ppaLeaves Pointer to the pointer to the array of sorted
880	* CPUID leaves and sub-leaves. Must be NULL if using
881	* the hyper heap.
882	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
883	* be NULL if using the hyper heap.
884	* @param pNewLeaf Pointer to the data of the new leaf we're about to
885	* insert.
886	*/
887	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
888	{
889	/*
890	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
891	*/
892	if (pVM)
893	{
894	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
895	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
896
897	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
898	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
899	}
900
901	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
902	uint32_t cLeaves = *pcLeaves;
903
904	/*
905	* Validate the new leaf a little.
906	*/
907	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
908	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
909	VERR_INVALID_FLAGS);
910	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
911	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
912	VERR_INVALID_PARAMETER);
913	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
914	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
915	VERR_INVALID_PARAMETER);
916	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
917	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
918	VERR_INVALID_PARAMETER);
919
920	/*
921	* Find insertion point. The lazy bird uses the same excuse as in
922	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
923	*/
924	uint32_t i;
925	if ( cLeaves > 0
926	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
927	{
928	/* Add at end. */
929	i = cLeaves;
930	}
931	else if ( cLeaves > 0
932	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
933	{
934	/* Either replacing the last leaf or dealing with sub-leaves. Spool
935	back to the first sub-leaf to pretend we did the linear search. */
936	i = cLeaves - 1;
937	while ( i > 0
938	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
939	i--;
940	}
941	else
942	{
943	/* Linear search from the start. */
944	i = 0;
945	while ( i < cLeaves
946	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
947	i++;
948	}
949	if ( i < cLeaves
950	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
951	{
952	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
953	{
954	/*
955	* The sub-leaf mask differs, replace all existing leaves with the
956	* same leaf number.
957	*/
958	uint32_t c = 1;
959	while ( i + c < cLeaves
960	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
961	c++;
962	if (c > 1 && i + c < cLeaves)
963	{
964	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
965	*pcLeaves = cLeaves -= c - 1;
966	}
967
968	paLeaves[i] = *pNewLeaf;
969	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
970	return VINF_SUCCESS;
971	}
972
973	/* Find sub-leaf insertion point. */
974	while ( i < cLeaves
975	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
976	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
977	i++;
978
979	/*
980	* If we've got an exactly matching leaf, replace it.
981	*/
982	if ( i < cLeaves
983	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
984	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
985	{
986	paLeaves[i] = *pNewLeaf;
987	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
988	return VINF_SUCCESS;
989	}
990	}
991
992	/*
993	* Adding a new leaf at 'i'.
994	*/
995	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
996	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
997	if (!paLeaves)
998	return VERR_NO_MEMORY;
999
1000	if (i < cLeaves)
1001	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
1002	*pcLeaves += 1;
1003	paLeaves[i] = *pNewLeaf;
1004
1005	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1006	return VINF_SUCCESS;
1007	}
1008
1009
1010	#ifndef IN_VBOX_CPU_REPORT
1011	/**
1012	* Removes a range of CPUID leaves.
1013	*
1014	* This will not reallocate the array.
1015	*
1016	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1017	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1018	* @param uFirst The first leaf.
1019	* @param uLast The last leaf.
1020	*/
1021	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1022	{
1023	uint32_t cLeaves = *pcLeaves;
1024
1025	Assert(uFirst <= uLast);
1026
1027	/*
1028	* Find the first one.
1029	*/
1030	uint32_t iFirst = 0;
1031	while ( iFirst < cLeaves
1032	&& paLeaves[iFirst].uLeaf < uFirst)
1033	iFirst++;
1034
1035	/*
1036	* Find the end (last + 1).
1037	*/
1038	uint32_t iEnd = iFirst;
1039	while ( iEnd < cLeaves
1040	&& paLeaves[iEnd].uLeaf <= uLast)
1041	iEnd++;
1042
1043	/*
1044	* Adjust the array if anything needs removing.
1045	*/
1046	if (iFirst < iEnd)
1047	{
1048	if (iEnd < cLeaves)
1049	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1050	*pcLeaves = cLeaves -= (iEnd - iFirst);
1051	}
1052
1053	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1054	}
1055	#endif /* IN_VBOX_CPU_REPORT */
1056
1057
1058	/**
1059	* Checks if ECX make a difference when reading a given CPUID leaf.
1060	*
1061	* @returns @c true if it does, @c false if it doesn't.
1062	* @param uLeaf The leaf we're reading.
1063	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1064	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1065	* final sub-leaf (for leaf 0xb only).
1066	*/
1067	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1068	{
1069	*pfFinalEcxUnchanged = false;
1070
1071	uint32_t auCur[4];
1072	uint32_t auPrev[4];
1073	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1074
1075	/* Look for sub-leaves. */
1076	uint32_t uSubLeaf = 1;
1077	for (;;)
1078	{
1079	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1080	if (memcmp(auCur, auPrev, sizeof(auCur)))
1081	break;
1082
1083	/* Advance / give up. */
1084	uSubLeaf++;
1085	if (uSubLeaf >= 64)
1086	{
1087	*pcSubLeaves = 1;
1088	return false;
1089	}
1090	}
1091
1092	/* Count sub-leaves. */
1093	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1094	uint32_t cRepeats = 0;
1095	uSubLeaf = 0;
1096	for (;;)
1097	{
1098	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1099
1100	/* Figuring out when to stop isn't entirely straight forward as we need
1101	to cover undocumented behavior up to a point and implementation shortcuts. */
1102
1103	/* 1. Look for more than 4 repeating value sets. */
1104	if ( auCur[0] == auPrev[0]
1105	&& auCur[1] == auPrev[1]
1106	&& ( auCur[2] == auPrev[2]
1107	\|\| ( auCur[2] == uSubLeaf
1108	&& auPrev[2] == uSubLeaf - 1) )
1109	&& auCur[3] == auPrev[3])
1110	{
1111	if ( uLeaf != 0xd
1112	\|\| uSubLeaf >= 64
1113	\|\| ( auCur[0] == 0
1114	&& auCur[1] == 0
1115	&& auCur[2] == 0
1116	&& auCur[3] == 0
1117	&& auPrev[2] == 0) )
1118	cRepeats++;
1119	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1120	break;
1121	}
1122	else
1123	cRepeats = 0;
1124
1125	/* 2. Look for zero values. */
1126	if ( auCur[0] == 0
1127	&& auCur[1] == 0
1128	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1129	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1130	&& uSubLeaf >= cMinLeaves)
1131	{
1132	cRepeats = 0;
1133	break;
1134	}
1135
1136	/* 3. Leaf 0xb level type 0 check. */
1137	if ( uLeaf == 0xb
1138	&& (auCur[2] & 0xff00) == 0
1139	&& (auPrev[2] & 0xff00) == 0)
1140	{
1141	cRepeats = 0;
1142	break;
1143	}
1144
1145	/* 99. Give up. */
1146	if (uSubLeaf >= 128)
1147	{
1148	#ifndef IN_VBOX_CPU_REPORT
1149	/* Ok, limit it according to the documentation if possible just to
1150	avoid annoying users with these detection issues. */
1151	uint32_t cDocLimit = UINT32_MAX;
1152	if (uLeaf == 0x4)
1153	cDocLimit = 4;
1154	else if (uLeaf == 0x7)
1155	cDocLimit = 1;
1156	else if (uLeaf == 0xd)
1157	cDocLimit = 63;
1158	else if (uLeaf == 0xf)
1159	cDocLimit = 2;
1160	if (cDocLimit != UINT32_MAX)
1161	{
1162	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1163	*pcSubLeaves = cDocLimit + 3;
1164	return true;
1165	}
1166	#endif
1167	*pcSubLeaves = UINT32_MAX;
1168	return true;
1169	}
1170
1171	/* Advance. */
1172	uSubLeaf++;
1173	memcpy(auPrev, auCur, sizeof(auCur));
1174	}
1175
1176	/* Standard exit. */
1177	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1178	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1179	if (*pcSubLeaves == 0)
1180	*pcSubLeaves = 1;
1181	return true;
1182	}
1183
1184
1185	/**
1186	* Gets a CPU ID leaf.
1187	*
1188	* @returns VBox status code.
1189	* @param pVM The cross context VM structure.
1190	* @param pLeaf Where to store the found leaf.
1191	* @param uLeaf The leaf to locate.
1192	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1193	*/
1194	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1195	{
1196	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1197	uLeaf, uSubLeaf);
1198	if (pcLeaf)
1199	{
1200	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1201	return VINF_SUCCESS;
1202	}
1203
1204	return VERR_NOT_FOUND;
1205	}
1206
1207
1208	/**
1209	* Inserts a CPU ID leaf, replacing any existing ones.
1210	*
1211	* @returns VBox status code.
1212	* @param pVM The cross context VM structure.
1213	* @param pNewLeaf Pointer to the leaf being inserted.
1214	*/
1215	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1216	{
1217	/*
1218	* Validate parameters.
1219	*/
1220	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1221	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1222
1223	/*
1224	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1225	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1226	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1227	*/
1228	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1229	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1230	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1231	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1232	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1233	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1234	{
1235	return VERR_NOT_SUPPORTED;
1236	}
1237
1238	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1239	}
1240
1241	/**
1242	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1243	*
1244	* @returns VBox status code.
1245	* @param ppaLeaves Where to return the array pointer on success.
1246	* Use RTMemFree to release.
1247	* @param pcLeaves Where to return the size of the array on
1248	* success.
1249	*/
1250	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1251	{
1252	*ppaLeaves = NULL;
1253	*pcLeaves = 0;
1254
1255	/*
1256	* Try out various candidates. This must be sorted!
1257	*/
1258	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1259	{
1260	{ UINT32_C(0x00000000), false },
1261	{ UINT32_C(0x10000000), false },
1262	{ UINT32_C(0x20000000), false },
1263	{ UINT32_C(0x30000000), false },
1264	{ UINT32_C(0x40000000), false },
1265	{ UINT32_C(0x50000000), false },
1266	{ UINT32_C(0x60000000), false },
1267	{ UINT32_C(0x70000000), false },
1268	{ UINT32_C(0x80000000), false },
1269	{ UINT32_C(0x80860000), false },
1270	{ UINT32_C(0x8ffffffe), true },
1271	{ UINT32_C(0x8fffffff), true },
1272	{ UINT32_C(0x90000000), false },
1273	{ UINT32_C(0xa0000000), false },
1274	{ UINT32_C(0xb0000000), false },
1275	{ UINT32_C(0xc0000000), false },
1276	{ UINT32_C(0xd0000000), false },
1277	{ UINT32_C(0xe0000000), false },
1278	{ UINT32_C(0xf0000000), false },
1279	};
1280
1281	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1282	{
1283	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1284	uint32_t uEax, uEbx, uEcx, uEdx;
1285	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1286
1287	/*
1288	* Does EAX look like a typical leaf count value?
1289	*/
1290	if ( uEax > uLeaf
1291	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1292	{
1293	/* Yes, dump them. */
1294	uint32_t cLeaves = uEax - uLeaf + 1;
1295	while (cLeaves-- > 0)
1296	{
1297	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1298
1299	uint32_t fFlags = 0;
1300
1301	/* There are currently three known leaves containing an APIC ID
1302	that needs EMT specific attention */
1303	if (uLeaf == 1)
1304	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1305	else if (uLeaf == 0xb && uEcx != 0)
1306	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1307	else if ( uLeaf == UINT32_C(0x8000001e)
1308	&& ( uEax
1309	\|\| uEbx
1310	\|\| uEdx
1311	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1312	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1313
1314	/* The APIC bit is per-VCpu and needs flagging. */
1315	if (uLeaf == 1)
1316	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1317	else if ( uLeaf == UINT32_C(0x80000001)
1318	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1319	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1320	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1321
1322	/* Check three times here to reduce the chance of CPU migration
1323	resulting in false positives with things like the APIC ID. */
1324	uint32_t cSubLeaves;
1325	bool fFinalEcxUnchanged;
1326	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1327	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1328	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1329	{
1330	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1331	{
1332	/* This shouldn't happen. But in case it does, file all
1333	relevant details in the release log. */
1334	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1335	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1336	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1337	{
1338	uint32_t auTmp[4];
1339	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1340	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1341	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1342	}
1343	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1344	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1345	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1346	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1347	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1348	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1349	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1350	}
1351
1352	if (fFinalEcxUnchanged)
1353	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1354
1355	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1356	{
1357	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1358	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1359	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1360	if (RT_FAILURE(rc))
1361	return rc;
1362	}
1363	}
1364	else
1365	{
1366	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1367	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1368	if (RT_FAILURE(rc))
1369	return rc;
1370	}
1371
1372	/* next */
1373	uLeaf++;
1374	}
1375	}
1376	/*
1377	* Special CPUIDs needs special handling as they don't follow the
1378	* leaf count principle used above.
1379	*/
1380	else if (s_aCandidates[iOuter].fSpecial)
1381	{
1382	bool fKeep = false;
1383	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1384	fKeep = true;
1385	else if ( uLeaf == 0x8fffffff
1386	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1387	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1388	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1389	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1390	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1391	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1392	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1393	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1394	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1395	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1396	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1397	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1398	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1399	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1400	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1401	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1402	fKeep = true;
1403	if (fKeep)
1404	{
1405	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1406	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1407	if (RT_FAILURE(rc))
1408	return rc;
1409	}
1410	}
1411	}
1412
1413	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1414	return VINF_SUCCESS;
1415	}
1416
1417
1418	/**
1419	* Determines the method the CPU uses to handle unknown CPUID leaves.
1420	*
1421	* @returns VBox status code.
1422	* @param penmUnknownMethod Where to return the method.
1423	* @param pDefUnknown Where to return default unknown values. This
1424	* will be set, even if the resulting method
1425	* doesn't actually needs it.
1426	*/
1427	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1428	{
1429	uint32_t uLastStd = ASMCpuId_EAX(0);
1430	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1431	if (!ASMIsValidExtRange(uLastExt))
1432	uLastExt = 0x80000000;
1433
1434	uint32_t auChecks[] =
1435	{
1436	uLastStd + 1,
1437	uLastStd + 5,
1438	uLastStd + 8,
1439	uLastStd + 32,
1440	uLastStd + 251,
1441	uLastExt + 1,
1442	uLastExt + 8,
1443	uLastExt + 15,
1444	uLastExt + 63,
1445	uLastExt + 255,
1446	0x7fbbffcc,
1447	0x833f7872,
1448	0xefff2353,
1449	0x35779456,
1450	0x1ef6d33e,
1451	};
1452
1453	static const uint32_t s_auValues[] =
1454	{
1455	0xa95d2156,
1456	0x00000001,
1457	0x00000002,
1458	0x00000008,
1459	0x00000000,
1460	0x55773399,
1461	0x93401769,
1462	0x12039587,
1463	};
1464
1465	/*
1466	* Simple method, all zeros.
1467	*/
1468	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1469	pDefUnknown->uEax = 0;
1470	pDefUnknown->uEbx = 0;
1471	pDefUnknown->uEcx = 0;
1472	pDefUnknown->uEdx = 0;
1473
1474	/*
1475	* Intel has been observed returning the last standard leaf.
1476	*/
1477	uint32_t auLast[4];
1478	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1479
1480	uint32_t cChecks = RT_ELEMENTS(auChecks);
1481	while (cChecks > 0)
1482	{
1483	uint32_t auCur[4];
1484	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1485	if (memcmp(auCur, auLast, sizeof(auCur)))
1486	break;
1487	cChecks--;
1488	}
1489	if (cChecks == 0)
1490	{
1491	/* Now, what happens when the input changes? Esp. ECX. */
1492	uint32_t cTotal = 0;
1493	uint32_t cSame = 0;
1494	uint32_t cLastWithEcx = 0;
1495	uint32_t cNeither = 0;
1496	uint32_t cValues = RT_ELEMENTS(s_auValues);
1497	while (cValues > 0)
1498	{
1499	uint32_t uValue = s_auValues[cValues - 1];
1500	uint32_t auLastWithEcx[4];
1501	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1502	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1503
1504	cChecks = RT_ELEMENTS(auChecks);
1505	while (cChecks > 0)
1506	{
1507	uint32_t auCur[4];
1508	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1509	if (!memcmp(auCur, auLast, sizeof(auCur)))
1510	{
1511	cSame++;
1512	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1513	cLastWithEcx++;
1514	}
1515	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1516	cLastWithEcx++;
1517	else
1518	cNeither++;
1519	cTotal++;
1520	cChecks--;
1521	}
1522	cValues--;
1523	}
1524
1525	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1526	if (cSame == cTotal)
1527	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1528	else if (cLastWithEcx == cTotal)
1529	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1530	else
1531	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1532	pDefUnknown->uEax = auLast[0];
1533	pDefUnknown->uEbx = auLast[1];
1534	pDefUnknown->uEcx = auLast[2];
1535	pDefUnknown->uEdx = auLast[3];
1536	return VINF_SUCCESS;
1537	}
1538
1539	/*
1540	* Unchanged register values?
1541	*/
1542	cChecks = RT_ELEMENTS(auChecks);
1543	while (cChecks > 0)
1544	{
1545	uint32_t const uLeaf = auChecks[cChecks - 1];
1546	uint32_t cValues = RT_ELEMENTS(s_auValues);
1547	while (cValues > 0)
1548	{
1549	uint32_t uValue = s_auValues[cValues - 1];
1550	uint32_t auCur[4];
1551	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1552	if ( auCur[0] != uLeaf
1553	\|\| auCur[1] != uValue
1554	\|\| auCur[2] != uValue
1555	\|\| auCur[3] != uValue)
1556	break;
1557	cValues--;
1558	}
1559	if (cValues != 0)
1560	break;
1561	cChecks--;
1562	}
1563	if (cChecks == 0)
1564	{
1565	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1566	return VINF_SUCCESS;
1567	}
1568
1569	/*
1570	* Just go with the simple method.
1571	*/
1572	return VINF_SUCCESS;
1573	}
1574
1575
1576	/**
1577	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1578	*
1579	* @returns Read only name string.
1580	* @param enmUnknownMethod The method to translate.
1581	*/
1582	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1583	{
1584	switch (enmUnknownMethod)
1585	{
1586	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1587	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1588	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1589	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1590
1591	case CPUMUNKNOWNCPUID_INVALID:
1592	case CPUMUNKNOWNCPUID_END:
1593	case CPUMUNKNOWNCPUID_32BIT_HACK:
1594	break;
1595	}
1596	return "Invalid-unknown-CPUID-method";
1597	}
1598
1599
1600	/**
1601	* Detect the CPU vendor give n the
1602	*
1603	* @returns The vendor.
1604	* @param uEAX EAX from CPUID(0).
1605	* @param uEBX EBX from CPUID(0).
1606	* @param uECX ECX from CPUID(0).
1607	* @param uEDX EDX from CPUID(0).
1608	*/
1609	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1610	{
1611	if (ASMIsValidStdRange(uEAX))
1612	{
1613	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1614	return CPUMCPUVENDOR_AMD;
1615
1616	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1617	return CPUMCPUVENDOR_INTEL;
1618
1619	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1620	return CPUMCPUVENDOR_VIA;
1621
1622	if (ASMIsShanghaiCpuEx(uEBX, uECX, uEDX))
1623	return CPUMCPUVENDOR_SHANGHAI;
1624
1625	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1626	&& uECX == UINT32_C(0x64616574)
1627	&& uEDX == UINT32_C(0x736E4978))
1628	return CPUMCPUVENDOR_CYRIX;
1629
1630	/* "Geode by NSC", example: family 5, model 9. */
1631
1632	/** @todo detect the other buggers... */
1633	}
1634
1635	return CPUMCPUVENDOR_UNKNOWN;
1636	}
1637
1638
1639	/**
1640	* Translates a CPU vendor enum value into the corresponding string constant.
1641	*
1642	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1643	* value name. This can be useful when generating code.
1644	*
1645	* @returns Read only name string.
1646	* @param enmVendor The CPU vendor value.
1647	*/
1648	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1649	{
1650	switch (enmVendor)
1651	{
1652	case CPUMCPUVENDOR_INTEL: return "INTEL";
1653	case CPUMCPUVENDOR_AMD: return "AMD";
1654	case CPUMCPUVENDOR_VIA: return "VIA";
1655	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1656	case CPUMCPUVENDOR_SHANGHAI: return "SHANGHAI";
1657	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1658
1659	case CPUMCPUVENDOR_INVALID:
1660	case CPUMCPUVENDOR_32BIT_HACK:
1661	break;
1662	}
1663	return "Invalid-cpu-vendor";
1664	}
1665
1666
1667	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1668	{
1669	/* Could do binary search, doing linear now because I'm lazy. */
1670	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1671	while (cLeaves-- > 0)
1672	{
1673	if (pLeaf->uLeaf == uLeaf)
1674	return pLeaf;
1675	pLeaf++;
1676	}
1677	return NULL;
1678	}
1679
1680
1681	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1682	{
1683	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1684	if ( !pLeaf
1685	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1686	return pLeaf;
1687
1688	/* Linear sub-leaf search. Lazy as usual. */
1689	cLeaves -= pLeaf - paLeaves;
1690	while ( cLeaves-- > 0
1691	&& pLeaf->uLeaf == uLeaf)
1692	{
1693	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1694	return pLeaf;
1695	pLeaf++;
1696	}
1697
1698	return NULL;
1699	}
1700
1701
1702	static void cpumR3ExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURES pFeatures)
1703	{
1704	Assert(pVmxMsrs);
1705	Assert(pFeatures);
1706	Assert(pFeatures->fVmx);
1707
1708	/* Basic information. */
1709	{
1710	uint64_t const u64Basic = pVmxMsrs->u64Basic;
1711	pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1712	}
1713
1714	/* Pin-based VM-execution controls. */
1715	{
1716	uint32_t const fPinCtls = pVmxMsrs->PinCtls.n.allowed1;
1717	pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1718	pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1719	pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1720	pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1721	pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1722	}
1723
1724	/* Processor-based VM-execution controls. */
1725	{
1726	uint32_t const fProcCtls = pVmxMsrs->ProcCtls.n.allowed1;
1727	pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1728	pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1729	pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1730	pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1731	pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1732	pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1733	pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1734	pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1735	pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1736	pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1737	pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1738	pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1739	pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1740	pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1741	pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1742	pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1743	pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1744	pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1745	pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1746	pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1747	pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1748	}
1749
1750	/* Secondary processor-based VM-execution controls. */
1751	{
1752	uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1753	pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1754	pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1755	pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1756	pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1757	pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1758	pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1759	pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1760	pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1761	pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1762	pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1763	pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1764	pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1765	pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1766	pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1767	pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1768	pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1769	pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1770	pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_VE);
1771	pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1772	pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1773	}
1774
1775	/* VM-exit controls. */
1776	{
1777	uint32_t const fExitCtls = pVmxMsrs->ExitCtls.n.allowed1;
1778	pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1779	pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1780	pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1781	pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1782	pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1783	pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1784	pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1785	pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1786	}
1787
1788	/* VM-entry controls. */
1789	{
1790	uint32_t const fEntryCtls = pVmxMsrs->EntryCtls.n.allowed1;
1791	pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1792	pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1793	pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1794	pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1795	}
1796
1797	/* Miscellaneous data. */
1798	{
1799	uint32_t const fMiscData = pVmxMsrs->u64Misc;
1800	pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1801	pFeatures->fVmxIntelPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1802	pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1803	pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1804	}
1805	}
1806
1807
1808	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures)
1809	{
1810	Assert(pMsrs);
1811	RT_ZERO(*pFeatures);
1812	if (cLeaves >= 2)
1813	{
1814	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1815	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1816	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1817	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1818	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1819	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1820
1821	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1822	pStd0Leaf->uEbx,
1823	pStd0Leaf->uEcx,
1824	pStd0Leaf->uEdx);
1825	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1826	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1827	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1828	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1829	pFeatures->uFamily,
1830	pFeatures->uModel,
1831	pFeatures->uStepping);
1832
1833	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1834	if (pExtLeaf8)
1835	{
1836	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1837	pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1838	}
1839	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1840	{
1841	pFeatures->cMaxPhysAddrWidth = 36;
1842	pFeatures->cMaxLinearAddrWidth = 36;
1843	}
1844	else
1845	{
1846	pFeatures->cMaxPhysAddrWidth = 32;
1847	pFeatures->cMaxLinearAddrWidth = 32;
1848	}
1849
1850	/* Standard features. */
1851	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1852	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1853	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1854	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1855	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1856	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1857	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1858	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1859	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1860	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1861	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1862	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1863	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1864	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1865	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1866	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1867	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1868	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1869	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1870	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1871	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1872	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1873	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1874	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1875	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1876	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1877	if (pFeatures->fVmx)
1878	cpumR3ExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1879
1880	/* Structured extended features. */
1881	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1882	if (pSxfLeaf0)
1883	{
1884	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1885	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1886	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1887	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1888	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1889
1890	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1891	pFeatures->fIbrs = pFeatures->fIbpb;
1892	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1893	pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
1894	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1895	}
1896
1897	/* MWAIT/MONITOR leaf. */
1898	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1899	if (pMWaitLeaf)
1900	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1901	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1902
1903	/* Extended features. */
1904	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1905	if (pExtLeaf)
1906	{
1907	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1908	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1909	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1910	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1911	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1912	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1913	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1914	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1915	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1916	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1917	}
1918
1919	/* VMX (VMXON, VMCS region and related data structures') physical address width (depends on long-mode). */
1920	pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
1921
1922	if ( pExtLeaf
1923	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1924	{
1925	/* AMD features. */
1926	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1927	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1928	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1929	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1930	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1931	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1932	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1933	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1934	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1935	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1936	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1937	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1938	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1939	if (pFeatures->fSvm)
1940	{
1941	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1942	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1943	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1944	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1945	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1946	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1947	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1948	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1949	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1950	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1951	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1952	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1953	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1954	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1955	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1956	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1957	}
1958	}
1959
1960	/*
1961	* Quirks.
1962	*/
1963	pFeatures->fLeakyFxSR = pExtLeaf
1964	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1965	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1966	&& pFeatures->uFamily >= 6 /* K7 and up */;
1967
1968	/*
1969	* Max extended (/FPU) state.
1970	*/
1971	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1972	if (pFeatures->fXSaveRstor)
1973	{
1974	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1975	if (pXStateLeaf0)
1976	{
1977	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1978	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1979	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1980	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1981	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1982	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1983	{
1984	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1985
1986	/* (paranoia:) */
1987	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1988	if ( pXStateLeaf1
1989	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1990	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1991	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1992	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1993	}
1994	else
1995	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1996	pFeatures->fXSaveRstor = 0);
1997	}
1998	else
1999	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
2000	pFeatures->fXSaveRstor = 0);
2001	}
2002	}
2003	else
2004	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
2005	return VINF_SUCCESS;
2006	}
2007
2008
2009	/*
2010	*
2011	* Init related code.
2012	* Init related code.
2013	* Init related code.
2014	*
2015	*
2016	*/
2017	#ifdef VBOX_IN_VMM
2018
2019
2020	/**
2021	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
2022	*
2023	* This ignores the fSubLeafMask.
2024	*
2025	* @returns Pointer to the matching leaf, or NULL if not found.
2026	* @param paLeaves The CPUID leaves to search. This is sorted.
2027	* @param cLeaves The number of leaves in the array.
2028	* @param uLeaf The leaf to locate.
2029	* @param uSubLeaf The subleaf to locate.
2030	*/
2031	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
2032	{
2033	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
2034	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
2035	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
2036	if (iEnd)
2037	{
2038	uint32_t iBegin = 0;
2039	for (;;)
2040	{
2041	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
2042	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
2043	if (uNeedle < uCur)
2044	{
2045	if (i > iBegin)
2046	iEnd = i;
2047	else
2048	break;
2049	}
2050	else if (uNeedle > uCur)
2051	{
2052	if (i + 1 < iEnd)
2053	iBegin = i + 1;
2054	else
2055	break;
2056	}
2057	else
2058	return &paLeaves[i];
2059	}
2060	}
2061	return NULL;
2062	}
2063
2064
2065	/**
2066	* Loads MSR range overrides.
2067	*
2068	* This must be called before the MSR ranges are moved from the normal heap to
2069	* the hyper heap!
2070	*
2071	* @returns VBox status code (VMSetError called).
2072	* @param pVM The cross context VM structure.
2073	* @param pMsrNode The CFGM node with the MSR overrides.
2074	*/
2075	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
2076	{
2077	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2078	{
2079	/*
2080	* Assemble a valid MSR range.
2081	*/
2082	CPUMMSRRANGE MsrRange;
2083	MsrRange.offCpumCpu = 0;
2084	MsrRange.fReserved = 0;
2085
2086	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
2087	if (RT_FAILURE(rc))
2088	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
2089
2090	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
2091	if (RT_FAILURE(rc))
2092	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
2093	MsrRange.szName, rc);
2094
2095	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
2096	if (RT_FAILURE(rc))
2097	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
2098	MsrRange.szName, rc);
2099
2100	char szType[32];
2101	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
2102	if (RT_FAILURE(rc))
2103	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
2104	MsrRange.szName, rc);
2105	if (!RTStrICmp(szType, "FixedValue"))
2106	{
2107	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
2108	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
2109
2110	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
2111	if (RT_FAILURE(rc))
2112	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
2113	MsrRange.szName, rc);
2114
2115	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
2116	if (RT_FAILURE(rc))
2117	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
2118	MsrRange.szName, rc);
2119
2120	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
2121	if (RT_FAILURE(rc))
2122	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
2123	MsrRange.szName, rc);
2124	}
2125	else
2126	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
2127	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
2128
2129	/*
2130	* Insert the range into the table (replaces/splits/shrinks existing
2131	* MSR ranges).
2132	*/
2133	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
2134	&MsrRange);
2135	if (RT_FAILURE(rc))
2136	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
2137	}
2138
2139	return VINF_SUCCESS;
2140	}
2141
2142
2143	/**
2144	* Loads CPUID leaf overrides.
2145	*
2146	* This must be called before the CPUID leaves are moved from the normal
2147	* heap to the hyper heap!
2148	*
2149	* @returns VBox status code (VMSetError called).
2150	* @param pVM The cross context VM structure.
2151	* @param pParentNode The CFGM node with the CPUID leaves.
2152	* @param pszLabel How to label the overrides we're loading.
2153	*/
2154	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2155	{
2156	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2157	{
2158	/*
2159	* Get the leaf and subleaf numbers.
2160	*/
2161	char szName[128];
2162	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2163	if (RT_FAILURE(rc))
2164	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2165
2166	/* The leaf number is either specified directly or thru the node name. */
2167	uint32_t uLeaf;
2168	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2169	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2170	{
2171	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2172	if (rc != VINF_SUCCESS)
2173	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2174	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2175	}
2176	else if (RT_FAILURE(rc))
2177	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2178	pszLabel, szName, rc);
2179
2180	uint32_t uSubLeaf;
2181	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2182	if (RT_FAILURE(rc))
2183	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2184	pszLabel, szName, rc);
2185
2186	uint32_t fSubLeafMask;
2187	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2188	if (RT_FAILURE(rc))
2189	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2190	pszLabel, szName, rc);
2191
2192	/*
2193	* Look up the specified leaf, since the output register values
2194	* defaults to any existing values. This allows overriding a single
2195	* register, without needing to know the other values.
2196	*/
2197	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2198	CPUMCPUIDLEAF Leaf;
2199	if (pLeaf)
2200	Leaf = *pLeaf;
2201	else
2202	RT_ZERO(Leaf);
2203	Leaf.uLeaf = uLeaf;
2204	Leaf.uSubLeaf = uSubLeaf;
2205	Leaf.fSubLeafMask = fSubLeafMask;
2206
2207	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2208	if (RT_FAILURE(rc))
2209	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2210	pszLabel, szName, rc);
2211	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2212	if (RT_FAILURE(rc))
2213	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2214	pszLabel, szName, rc);
2215	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2216	if (RT_FAILURE(rc))
2217	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2218	pszLabel, szName, rc);
2219	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2220	if (RT_FAILURE(rc))
2221	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2222	pszLabel, szName, rc);
2223
2224	/*
2225	* Insert the leaf into the table (replaces existing ones).
2226	*/
2227	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2228	&Leaf);
2229	if (RT_FAILURE(rc))
2230	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2231	}
2232
2233	return VINF_SUCCESS;
2234	}
2235
2236
2237
2238	/**
2239	* Fetches overrides for a CPUID leaf.
2240	*
2241	* @returns VBox status code.
2242	* @param pLeaf The leaf to load the overrides into.
2243	* @param pCfgNode The CFGM node containing the overrides
2244	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2245	* @param iLeaf The CPUID leaf number.
2246	*/
2247	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2248	{
2249	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2250	if (pLeafNode)
2251	{
2252	uint32_t u32;
2253	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2254	if (RT_SUCCESS(rc))
2255	pLeaf->uEax = u32;
2256	else
2257	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2258
2259	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2260	if (RT_SUCCESS(rc))
2261	pLeaf->uEbx = u32;
2262	else
2263	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2264
2265	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2266	if (RT_SUCCESS(rc))
2267	pLeaf->uEcx = u32;
2268	else
2269	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2270
2271	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2272	if (RT_SUCCESS(rc))
2273	pLeaf->uEdx = u32;
2274	else
2275	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2276
2277	}
2278	return VINF_SUCCESS;
2279	}
2280
2281
2282	/**
2283	* Load the overrides for a set of CPUID leaves.
2284	*
2285	* @returns VBox status code.
2286	* @param paLeaves The leaf array.
2287	* @param cLeaves The number of leaves.
2288	* @param uStart The start leaf number.
2289	* @param pCfgNode The CFGM node containing the overrides
2290	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2291	*/
2292	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2293	{
2294	for (uint32_t i = 0; i < cLeaves; i++)
2295	{
2296	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2297	if (RT_FAILURE(rc))
2298	return rc;
2299	}
2300
2301	return VINF_SUCCESS;
2302	}
2303
2304
2305	/**
2306	* Installs the CPUID leaves and explods the data into structures like
2307	* GuestFeatures and CPUMCTX::aoffXState.
2308	*
2309	* @returns VBox status code.
2310	* @param pVM The cross context VM structure.
2311	* @param pCpum The CPUM part of @a VM.
2312	* @param paLeaves The leaves. These will be copied (but not freed).
2313	* @param cLeaves The number of leaves.
2314	* @param pMsrs The MSRs.
2315	*/
2316	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
2317	{
2318	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2319
2320	/*
2321	* Install the CPUID information.
2322	*/
2323	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2324	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2325
2326	AssertLogRelRCReturn(rc, rc);
2327	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2328	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2329	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2330	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2331	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2332
2333	/*
2334	* Update the default CPUID leaf if necessary.
2335	*/
2336	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2337	{
2338	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2339	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2340	{
2341	/* We don't use CPUID(0).eax here because of the NT hack that only
2342	changes that value without actually removing any leaves. */
2343	uint32_t i = 0;
2344	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2345	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2346	{
2347	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2348	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2349	i++;
2350	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2351	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2352	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2353	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2354	}
2355	break;
2356	}
2357	default:
2358	break;
2359	}
2360
2361	/*
2362	* Explode the guest CPU features.
2363	*/
2364	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
2365	&pCpum->GuestFeatures);
2366	AssertLogRelRCReturn(rc, rc);
2367
2368	/*
2369	* Adjust the scalable bus frequency according to the CPUID information
2370	* we're now using.
2371	*/
2372	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2373	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2374	? UINT64_C(100000000) /* 100MHz */
2375	: UINT64_C(133333333); /* 133MHz */
2376
2377	/*
2378	* Populate the legacy arrays. Currently used for everything, later only
2379	* for patch manager.
2380	*/
2381	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2382	{
2383	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2384	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2385	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2386	};
2387	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2388	{
2389	uint32_t cLeft = aOldRanges[i].cCpuIds;
2390	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2391	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2392	while (cLeft-- > 0)
2393	{
2394	uLeaf--;
2395	pLegacyLeaf--;
2396
2397	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2398	if (pLeaf)
2399	{
2400	pLegacyLeaf->uEax = pLeaf->uEax;
2401	pLegacyLeaf->uEbx = pLeaf->uEbx;
2402	pLegacyLeaf->uEcx = pLeaf->uEcx;
2403	pLegacyLeaf->uEdx = pLeaf->uEdx;
2404	}
2405	else
2406	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2407	}
2408	}
2409
2410	/*
2411	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2412	*/
2413	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2414	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2415	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2416	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2417	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2418	{
2419	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2420	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2421	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2422	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2423	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2424	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2425	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2426	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2427	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2428	pCpum->GuestFeatures.cbMaxExtendedState),
2429	VERR_CPUM_IPE_1);
2430	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2431	}
2432	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2433
2434	/* Copy the CPU #0 data to the other CPUs. */
2435	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2436	{
2437	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2438	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2439	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2440	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2441	}
2442
2443	return VINF_SUCCESS;
2444	}
2445
2446
2447	/** @name Instruction Set Extension Options
2448	* @{ */
2449	/** Configuration option type (extended boolean, really). */
2450	typedef uint8_t CPUMISAEXTCFG;
2451	/** Always disable the extension. */
2452	#define CPUMISAEXTCFG_DISABLED false
2453	/** Enable the extension if it's supported by the host CPU. */
2454	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2455	/** Enable the extension if it's supported by the host CPU, but don't let
2456	* the portable CPUID feature disable it. */
2457	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2458	/** Always enable the extension. */
2459	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2460	/** @} */
2461
2462	/**
2463	* CPUID Configuration (from CFGM).
2464	*
2465	* @remarks The members aren't document since we would only be duplicating the
2466	* \@cfgm entries in cpumR3CpuIdReadConfig.
2467	*/
2468	typedef struct CPUMCPUIDCONFIG
2469	{
2470	bool fNt4LeafLimit;
2471	bool fInvariantTsc;
2472	bool fForceVme;
2473	bool fNestedHWVirt;
2474
2475	CPUMISAEXTCFG enmCmpXchg16b;
2476	CPUMISAEXTCFG enmMonitor;
2477	CPUMISAEXTCFG enmMWaitExtensions;
2478	CPUMISAEXTCFG enmSse41;
2479	CPUMISAEXTCFG enmSse42;
2480	CPUMISAEXTCFG enmAvx;
2481	CPUMISAEXTCFG enmAvx2;
2482	CPUMISAEXTCFG enmXSave;
2483	CPUMISAEXTCFG enmAesNi;
2484	CPUMISAEXTCFG enmPClMul;
2485	CPUMISAEXTCFG enmPopCnt;
2486	CPUMISAEXTCFG enmMovBe;
2487	CPUMISAEXTCFG enmRdRand;
2488	CPUMISAEXTCFG enmRdSeed;
2489	CPUMISAEXTCFG enmCLFlushOpt;
2490	CPUMISAEXTCFG enmFsGsBase;
2491	CPUMISAEXTCFG enmPcid;
2492	CPUMISAEXTCFG enmInvpcid;
2493	CPUMISAEXTCFG enmFlushCmdMsr;
2494
2495	CPUMISAEXTCFG enmAbm;
2496	CPUMISAEXTCFG enmSse4A;
2497	CPUMISAEXTCFG enmMisAlnSse;
2498	CPUMISAEXTCFG enm3dNowPrf;
2499	CPUMISAEXTCFG enmAmdExtMmx;
2500
2501	uint32_t uMaxStdLeaf;
2502	uint32_t uMaxExtLeaf;
2503	uint32_t uMaxCentaurLeaf;
2504	uint32_t uMaxIntelFamilyModelStep;
2505	char szCpuName[128];
2506	} CPUMCPUIDCONFIG;
2507	/** Pointer to CPUID config (from CFGM). */
2508	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2509
2510
2511	/**
2512	* Mini CPU selection support for making Mac OS X happy.
2513	*
2514	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2515	*
2516	* @param pCpum The CPUM instance data.
2517	* @param pConfig The CPUID configuration we've read from CFGM.
2518	*/
2519	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2520	{
2521	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2522	{
2523	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2524	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2525	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2526	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2527	0);
2528	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2529	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2530	{
2531	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2532	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2533	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2534	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2535	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2536	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2537	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2538	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2539	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2540	pStdFeatureLeaf->uEax = uNew;
2541	}
2542	}
2543	}
2544
2545
2546
2547	/**
2548	* Limit it the number of entries, zapping the remainder.
2549	*
2550	* The limits are masking off stuff about power saving and similar, this
2551	* is perhaps a bit crudely done as there is probably some relatively harmless
2552	* info too in these leaves (like words about having a constant TSC).
2553	*
2554	* @param pCpum The CPUM instance data.
2555	* @param pConfig The CPUID configuration we've read from CFGM.
2556	*/
2557	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2558	{
2559	/*
2560	* Standard leaves.
2561	*/
2562	uint32_t uSubLeaf = 0;
2563	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2564	if (pCurLeaf)
2565	{
2566	uint32_t uLimit = pCurLeaf->uEax;
2567	if (uLimit <= UINT32_C(0x000fffff))
2568	{
2569	if (uLimit > pConfig->uMaxStdLeaf)
2570	{
2571	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2572	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2573	uLimit + 1, UINT32_C(0x000fffff));
2574	}
2575
2576	/* NT4 hack, no zapping of extra leaves here. */
2577	if (pConfig->fNt4LeafLimit && uLimit > 3)
2578	pCurLeaf->uEax = uLimit = 3;
2579
2580	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2581	pCurLeaf->uEax = uLimit;
2582	}
2583	else
2584	{
2585	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2586	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2587	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2588	}
2589	}
2590
2591	/*
2592	* Extended leaves.
2593	*/
2594	uSubLeaf = 0;
2595	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2596	if (pCurLeaf)
2597	{
2598	uint32_t uLimit = pCurLeaf->uEax;
2599	if ( uLimit >= UINT32_C(0x80000000)
2600	&& uLimit <= UINT32_C(0x800fffff))
2601	{
2602	if (uLimit > pConfig->uMaxExtLeaf)
2603	{
2604	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2605	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2606	uLimit + 1, UINT32_C(0x800fffff));
2607	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2608	pCurLeaf->uEax = uLimit;
2609	}
2610	}
2611	else
2612	{
2613	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2614	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2615	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2616	}
2617	}
2618
2619	/*
2620	* Centaur leaves (VIA).
2621	*/
2622	uSubLeaf = 0;
2623	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2624	if (pCurLeaf)
2625	{
2626	uint32_t uLimit = pCurLeaf->uEax;
2627	if ( uLimit >= UINT32_C(0xc0000000)
2628	&& uLimit <= UINT32_C(0xc00fffff))
2629	{
2630	if (uLimit > pConfig->uMaxCentaurLeaf)
2631	{
2632	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2633	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2634	uLimit + 1, UINT32_C(0xcfffffff));
2635	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2636	pCurLeaf->uEax = uLimit;
2637	}
2638	}
2639	else
2640	{
2641	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2642	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2643	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2644	}
2645	}
2646	}
2647
2648
2649	/**
2650	* Clears a CPUID leaf and all sub-leaves (to zero).
2651	*
2652	* @param pCpum The CPUM instance data.
2653	* @param uLeaf The leaf to clear.
2654	*/
2655	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2656	{
2657	uint32_t uSubLeaf = 0;
2658	PCPUMCPUIDLEAF pCurLeaf;
2659	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2660	{
2661	pCurLeaf->uEax = 0;
2662	pCurLeaf->uEbx = 0;
2663	pCurLeaf->uEcx = 0;
2664	pCurLeaf->uEdx = 0;
2665	uSubLeaf++;
2666	}
2667	}
2668
2669
2670	/**
2671	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2672	* the given leaf.
2673	*
2674	* @returns pLeaf.
2675	* @param pCpum The CPUM instance data.
2676	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2677	*/
2678	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2679	{
2680	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2681	if (pLeaf->fSubLeafMask != 0)
2682	{
2683	/*
2684	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2685	* Log everything while we're at it.
2686	*/
2687	LogRel(("CPUM:\n"
2688	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2689	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2690	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2691	for (;;)
2692	{
2693	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2694	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2695	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2696	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2697	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2698	break;
2699	pSubLeaf++;
2700	}
2701	LogRel(("CPUM:\n"));
2702
2703	/*
2704	* Remove the offending sub-leaves.
2705	*/
2706	if (pSubLeaf != pLeaf)
2707	{
2708	if (pSubLeaf != pLast)
2709	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2710	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2711	}
2712
2713	/*
2714	* Convert the first sub-leaf into a single leaf.
2715	*/
2716	pLeaf->uSubLeaf = 0;
2717	pLeaf->fSubLeafMask = 0;
2718	}
2719	return pLeaf;
2720	}
2721
2722
2723	/**
2724	* Sanitizes and adjust the CPUID leaves.
2725	*
2726	* Drop features that aren't virtualized (or virtualizable). Adjust information
2727	* and capabilities to fit the virtualized hardware. Remove information the
2728	* guest shouldn't have (because it's wrong in the virtual world or because it
2729	* gives away host details) or that we don't have documentation for and no idea
2730	* what means.
2731	*
2732	* @returns VBox status code.
2733	* @param pVM The cross context VM structure (for cCpus).
2734	* @param pCpum The CPUM instance data.
2735	* @param pConfig The CPUID configuration we've read from CFGM.
2736	*/
2737	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2738	{
2739	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2740	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2741	{ \
2742	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2743	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2744	}
2745	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2746	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2747	{ \
2748	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2749	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2750	}
2751	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2752	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2753	&& ((a_pLeafReg) & (fBitMask)) \
2754	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2755	{ \
2756	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2757	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2758	}
2759	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2760
2761	/* Cpuid 1:
2762	* EAX: CPU model, family and stepping.
2763	*
2764	* ECX + EDX: Supported features. Only report features we can support.
2765	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2766	* options may require adjusting (i.e. stripping what was enabled).
2767	*
2768	* EBX: Branding, CLFLUSH line size, logical processors per package and
2769	* initial APIC ID.
2770	*/
2771	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2772	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2773	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2774
2775	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2776	\| X86_CPUID_FEATURE_EDX_VME
2777	\| X86_CPUID_FEATURE_EDX_DE
2778	\| X86_CPUID_FEATURE_EDX_PSE
2779	\| X86_CPUID_FEATURE_EDX_TSC
2780	\| X86_CPUID_FEATURE_EDX_MSR
2781	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2782	\| X86_CPUID_FEATURE_EDX_MCE
2783	\| X86_CPUID_FEATURE_EDX_CX8
2784	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2785	//\| RT_BIT_32(10) - not defined
2786	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2787	//\| X86_CPUID_FEATURE_EDX_SEP
2788	\| X86_CPUID_FEATURE_EDX_MTRR
2789	\| X86_CPUID_FEATURE_EDX_PGE
2790	\| X86_CPUID_FEATURE_EDX_MCA
2791	\| X86_CPUID_FEATURE_EDX_CMOV
2792	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2793	\| X86_CPUID_FEATURE_EDX_PSE36
2794	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2795	\| X86_CPUID_FEATURE_EDX_CLFSH
2796	//\| RT_BIT_32(20) - not defined
2797	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2798	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2799	\| X86_CPUID_FEATURE_EDX_MMX
2800	\| X86_CPUID_FEATURE_EDX_FXSR
2801	\| X86_CPUID_FEATURE_EDX_SSE
2802	\| X86_CPUID_FEATURE_EDX_SSE2
2803	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2804	\| X86_CPUID_FEATURE_EDX_HTT
2805	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2806	//\| RT_BIT_32(30) - not defined
2807	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2808	;
2809	pStdFeatureLeaf->uEcx &= 0
2810	\| X86_CPUID_FEATURE_ECX_SSE3
2811	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2812	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2813	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2814	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2815	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2816	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2817	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2818	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2819	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2820	\| X86_CPUID_FEATURE_ECX_SSSE3
2821	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2822	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2823	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2824	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2825	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2826	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2827	\| (pConfig->enmPcid ? X86_CPUID_FEATURE_ECX_PCID : 0)
2828	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2829	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2830	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2831	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2832	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2833	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2834	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2835	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2836	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2837	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2838	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2839	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2840	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2841	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2842	;
2843
2844	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2845	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2846	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2847	{
2848	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2849	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2850	}
2851
2852	if (pCpum->u8PortableCpuIdLevel > 0)
2853	{
2854	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2855	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2856	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2857	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2858	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2859	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2860	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2861	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2862	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2863	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2864	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2865	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2866	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2867	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2868	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2869	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2870	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2871	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2872	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2873	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2874
2875	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2876	\| X86_CPUID_FEATURE_EDX_PSN
2877	\| X86_CPUID_FEATURE_EDX_DS
2878	\| X86_CPUID_FEATURE_EDX_ACPI
2879	\| X86_CPUID_FEATURE_EDX_SS
2880	\| X86_CPUID_FEATURE_EDX_TM
2881	\| X86_CPUID_FEATURE_EDX_PBE
2882	)));
2883	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2884	\| X86_CPUID_FEATURE_ECX_CPLDS
2885	\| X86_CPUID_FEATURE_ECX_AES
2886	\| X86_CPUID_FEATURE_ECX_VMX
2887	\| X86_CPUID_FEATURE_ECX_SMX
2888	\| X86_CPUID_FEATURE_ECX_EST
2889	\| X86_CPUID_FEATURE_ECX_TM2
2890	\| X86_CPUID_FEATURE_ECX_CNTXID
2891	\| X86_CPUID_FEATURE_ECX_FMA
2892	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2893	\| X86_CPUID_FEATURE_ECX_PDCM
2894	\| X86_CPUID_FEATURE_ECX_DCA
2895	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2896	)));
2897	}
2898
2899	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2900	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2901
2902	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2903	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2904	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2905	*/
2906	#ifdef VBOX_WITH_MULTI_CORE
2907	if (pVM->cCpus > 1)
2908	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2909	#endif
2910	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2911	{
2912	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2913	core times the number of CPU cores per processor */
2914	#ifdef VBOX_WITH_MULTI_CORE
2915	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2916	#else
2917	/* Single logical processor in a package. */
2918	pStdFeatureLeaf->uEbx \|= (1 << 16);
2919	#endif
2920	}
2921
2922	uint32_t uMicrocodeRev;
2923	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2924	if (RT_SUCCESS(rc))
2925	{
2926	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2927	}
2928	else
2929	{
2930	uMicrocodeRev = 0;
2931	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2932	}
2933
2934	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2935	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2936	*/
2937	if ( (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen)
2938	&& uMicrocodeRev < 0x8001126
2939	&& !pConfig->fForceVme)
2940	{
2941	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2942	LogRel(("CPUM: Zen VME workaround engaged\n"));
2943	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2944	}
2945
2946	/* Force standard feature bits. */
2947	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2948	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2949	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2950	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2951	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2952	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2953	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2954	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2955	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2956	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2957	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2958	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2959	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2960	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2961	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2962	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2963	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2964	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2965	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2966	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2967	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2968	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2969
2970	pStdFeatureLeaf = NULL; /* Must refetch! */
2971
2972	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2973	* AMD:
2974	* EAX: CPU model, family and stepping.
2975	*
2976	* ECX + EDX: Supported features. Only report features we can support.
2977	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2978	* options may require adjusting (i.e. stripping what was enabled).
2979	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2980	*
2981	* EBX: Branding ID and package type (or reserved).
2982	*
2983	* Intel and probably most others:
2984	* EAX: 0
2985	* EBX: 0
2986	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2987	*/
2988	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2989	if (pExtFeatureLeaf)
2990	{
2991	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2992
2993	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2994	\| X86_CPUID_AMD_FEATURE_EDX_VME
2995	\| X86_CPUID_AMD_FEATURE_EDX_DE
2996	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2997	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2998	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2999	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
3000	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
3001	\| X86_CPUID_AMD_FEATURE_EDX_CX8
3002	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
3003	//\| RT_BIT_32(10) - reserved
3004	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
3005	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
3006	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3007	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
3008	\| X86_CPUID_AMD_FEATURE_EDX_PGE
3009	\| X86_CPUID_AMD_FEATURE_EDX_MCA
3010	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
3011	\| X86_CPUID_AMD_FEATURE_EDX_PAT
3012	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
3013	//\| RT_BIT_32(18) - reserved
3014	//\| RT_BIT_32(19) - reserved
3015	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
3016	//\| RT_BIT_32(21) - reserved
3017	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
3018	\| X86_CPUID_AMD_FEATURE_EDX_MMX
3019	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
3020	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
3021	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3022	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
3023	//\| RT_BIT_32(28) - reserved
3024	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
3025	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
3026	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
3027	;
3028	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
3029	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
3030	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
3031	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3032	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
3033	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
3034	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
3035	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
3036	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
3037	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
3038	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3039	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
3040	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
3041	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3042	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
3043	//\| RT_BIT_32(14) - reserved
3044	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
3045	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
3046	//\| RT_BIT_32(17) - reserved
3047	//\| RT_BIT_32(18) - reserved
3048	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
3049	//\| RT_BIT_32(20) - reserved
3050	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
3051	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
3052	//\| RT_BIT_32(23) - reserved
3053	//\| RT_BIT_32(24) - reserved
3054	//\| RT_BIT_32(25) - reserved
3055	//\| RT_BIT_32(26) - reserved
3056	//\| RT_BIT_32(27) - reserved
3057	//\| RT_BIT_32(28) - reserved
3058	//\| RT_BIT_32(29) - reserved
3059	//\| RT_BIT_32(30) - reserved
3060	//\| RT_BIT_32(31) - reserved
3061	;
3062	#ifdef VBOX_WITH_MULTI_CORE
3063	if ( pVM->cCpus > 1
3064	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3065	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
3066	#endif
3067
3068	if (pCpum->u8PortableCpuIdLevel > 0)
3069	{
3070	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
3071	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
3072	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
3073	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
3074	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
3075	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
3076	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
3077	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
3078	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
3079	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
3080	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
3081	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
3082	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
3083	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
3084	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
3085	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
3086
3087	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
3088	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3089	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3090	\| X86_CPUID_AMD_FEATURE_ECX_IBS
3091	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3092	\| X86_CPUID_AMD_FEATURE_ECX_WDT
3093	\| X86_CPUID_AMD_FEATURE_ECX_LWP
3094	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
3095	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
3096	\| UINT32_C(0xff964000)
3097	)));
3098	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
3099	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3100	\| RT_BIT(18)
3101	\| RT_BIT(19)
3102	\| RT_BIT(21)
3103	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
3104	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3105	\| RT_BIT(28)
3106	)));
3107	}
3108
3109	/* Force extended feature bits. */
3110	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
3111	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
3112	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
3113	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
3114	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
3115	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
3116	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
3117	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
3118	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3119	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
3120	}
3121	pExtFeatureLeaf = NULL; /* Must refetch! */
3122
3123
3124	/* Cpuid 2:
3125	* Intel: (Nondeterministic) Cache and TLB information
3126	* AMD: Reserved
3127	* VIA: Reserved
3128	* Safe to expose.
3129	*/
3130	uint32_t uSubLeaf = 0;
3131	PCPUMCPUIDLEAF pCurLeaf;
3132	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
3133	{
3134	if ((pCurLeaf->uEax & 0xff) > 1)
3135	{
3136	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
3137	pCurLeaf->uEax &= UINT32_C(0xffffff01);
3138	}
3139	uSubLeaf++;
3140	}
3141
3142	/* Cpuid 3:
3143	* Intel: EAX, EBX - reserved (transmeta uses these)
3144	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3145	* AMD: Reserved
3146	* VIA: Reserved
3147	* Safe to expose
3148	*/
3149	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3150	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3151	{
3152	uSubLeaf = 0;
3153	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3154	{
3155	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3156	if (pCpum->u8PortableCpuIdLevel > 0)
3157	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3158	uSubLeaf++;
3159	}
3160	}
3161
3162	/* Cpuid 4 + ECX:
3163	* Intel: Deterministic Cache Parameters Leaf.
3164	* AMD: Reserved
3165	* VIA: Reserved
3166	* Safe to expose, except for EAX:
3167	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3168	* Bits 31-26: Maximum number of processor cores in this physical package**
3169	* Note: These SMP values are constant regardless of ECX
3170	*/
3171	uSubLeaf = 0;
3172	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3173	{
3174	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3175	#ifdef VBOX_WITH_MULTI_CORE
3176	if ( pVM->cCpus > 1
3177	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3178	{
3179	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3180	/* One logical processor with possibly multiple cores. */
3181	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3182	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3183	}
3184	#endif
3185	uSubLeaf++;
3186	}
3187
3188	/* Cpuid 5: Monitor/mwait Leaf
3189	* Intel: ECX, EDX - reserved
3190	* EAX, EBX - Smallest and largest monitor line size
3191	* AMD: EDX - reserved
3192	* EAX, EBX - Smallest and largest monitor line size
3193	* ECX - extensions (ignored for now)
3194	* VIA: Reserved
3195	* Safe to expose
3196	*/
3197	uSubLeaf = 0;
3198	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3199	{
3200	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3201	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3202	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3203
3204	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3205	if (pConfig->enmMWaitExtensions)
3206	{
3207	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3208	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3209	it shall be part of our power management virtualization model */
3210	#if 0
3211	/* MWAIT sub C-states */
3212	pCurLeaf->uEdx =
3213	(0 << 0) /* 0 in C0 */ \|
3214	(2 << 4) /* 2 in C1 */ \|
3215	(2 << 8) /* 2 in C2 */ \|
3216	(2 << 12) /* 2 in C3 */ \|
3217	(0 << 16) /* 0 in C4 */
3218	;
3219	#endif
3220	}
3221	else
3222	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3223	uSubLeaf++;
3224	}
3225
3226	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3227	* Intel: Various stuff.
3228	* AMD: EAX, EBX, EDX - reserved.
3229	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3230	* present. Same as intel.
3231	* VIA: ??
3232	*
3233	* We clear everything here for now.
3234	*/
3235	cpumR3CpuIdZeroLeaf(pCpum, 6);
3236
3237	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3238	* EAX: Number of sub leaves.
3239	* EBX+ECX+EDX: Feature flags
3240	*
3241	* We only have documentation for one sub-leaf, so clear all other (no need
3242	* to remove them as such, just set them to zero).
3243	*
3244	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3245	* options may require adjusting (i.e. stripping what was enabled).
3246	*/
3247	uSubLeaf = 0;
3248	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3249	{
3250	switch (uSubLeaf)
3251	{
3252	case 0:
3253	{
3254	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3255	pCurLeaf->uEbx &= 0
3256	\| (pConfig->enmFsGsBase ? X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE : 0)
3257	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3258	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3259	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3260	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3261	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3262	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3263	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3264	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3265	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3266	\| (pConfig->enmInvpcid ? X86_CPUID_STEXT_FEATURE_EBX_INVPCID : 0)
3267	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3268	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3269	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3270	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3271	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3272	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3273	//\| RT_BIT(17) - reserved
3274	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3275	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3276	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3277	//\| RT_BIT(21) - reserved
3278	//\| RT_BIT(22) - reserved
3279	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3280	//\| RT_BIT(24) - reserved
3281	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3282	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3283	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3284	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3285	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3286	//\| RT_BIT(30) - reserved
3287	//\| RT_BIT(31) - reserved
3288	;
3289	pCurLeaf->uEcx &= 0
3290	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3291	;
3292	pCurLeaf->uEdx &= 0
3293	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3294	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3295	\| (pConfig->enmFlushCmdMsr ? X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD : 0)
3296	//\| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT(29)
3297	;
3298
3299	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3300	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3301	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3302	{
3303	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3304	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3305	}
3306
3307	if (pCpum->u8PortableCpuIdLevel > 0)
3308	{
3309	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3310	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3311	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3312	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3313	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3314	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3315	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3316	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3317	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3318	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3319	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3320	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3321	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3322	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3323	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3324	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
3325	}
3326
3327	/* Force standard feature bits. */
3328	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3329	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3330	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3331	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3332	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3333	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3334	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3335	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3336	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3337	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3338	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3339	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
3340	break;
3341	}
3342
3343	default:
3344	/* Invalid index, all values are zero. */
3345	pCurLeaf->uEax = 0;
3346	pCurLeaf->uEbx = 0;
3347	pCurLeaf->uEcx = 0;
3348	pCurLeaf->uEdx = 0;
3349	break;
3350	}
3351	uSubLeaf++;
3352	}
3353
3354	/* Cpuid 8: Marked as reserved by Intel and AMD.
3355	* We zero this since we don't know what it may have been used for.
3356	*/
3357	cpumR3CpuIdZeroLeaf(pCpum, 8);
3358
3359	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3360	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3361	* EBX, ECX, EDX - reserved.
3362	* AMD: Reserved
3363	* VIA: ??
3364	*
3365	* We zero this.
3366	*/
3367	cpumR3CpuIdZeroLeaf(pCpum, 9);
3368
3369	/* Cpuid 0xa: Architectural Performance Monitor Features
3370	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3371	* EBX, ECX, EDX - reserved.
3372	* AMD: Reserved
3373	* VIA: ??
3374	*
3375	* We zero this, for now at least.
3376	*/
3377	cpumR3CpuIdZeroLeaf(pCpum, 10);
3378
3379	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3380	* Intel: EAX - APCI ID shift right for next level.
3381	* EBX - Factory configured cores/threads at this level.
3382	* ECX - Level number (same as input) and level type (1,2,0).
3383	* EDX - Extended initial APIC ID.
3384	* AMD: Reserved
3385	* VIA: ??
3386	*/
3387	uSubLeaf = 0;
3388	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3389	{
3390	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3391	{
3392	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3393	if (bLevelType == 1)
3394	{
3395	/* Thread level - we don't do threads at the moment. */
3396	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3397	pCurLeaf->uEbx = 1;
3398	}
3399	else if (bLevelType == 2)
3400	{
3401	/* Core level. */
3402	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3403	#ifdef VBOX_WITH_MULTI_CORE
3404	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3405	pCurLeaf->uEax++;
3406	#endif
3407	pCurLeaf->uEbx = pVM->cCpus;
3408	}
3409	else
3410	{
3411	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3412	pCurLeaf->uEax = 0;
3413	pCurLeaf->uEbx = 0;
3414	pCurLeaf->uEcx = 0;
3415	}
3416	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3417	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3418	}
3419	else
3420	{
3421	pCurLeaf->uEax = 0;
3422	pCurLeaf->uEbx = 0;
3423	pCurLeaf->uEcx = 0;
3424	pCurLeaf->uEdx = 0;
3425	}
3426	uSubLeaf++;
3427	}
3428
3429	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3430	* We zero this since we don't know what it may have been used for.
3431	*/
3432	cpumR3CpuIdZeroLeaf(pCpum, 12);
3433
3434	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3435	* ECX=0: EAX - Valid bits in XCR0[31:0].
3436	* EBX - Maximum state size as per current XCR0 value.
3437	* ECX - Maximum state size for all supported features.
3438	* EDX - Valid bits in XCR0[63:32].
3439	* ECX=1: EAX - Various X-features.
3440	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3441	* ECX - Valid bits in IA32_XSS[31:0].
3442	* EDX - Valid bits in IA32_XSS[63:32].
3443	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3444	* if the bit invalid all four registers are set to zero.
3445	* EAX - The state size for this feature.
3446	* EBX - The state byte offset of this feature.
3447	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3448	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3449	*
3450	* Clear them all as we don't currently implement extended CPU state.
3451	*/
3452	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3453	uint64_t fGuestXcr0Mask = 0;
3454	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3455	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3456	{
3457	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3458	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3459	fGuestXcr0Mask \|= XSAVE_C_YMM;
3460	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3461	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3462	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3463	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3464
3465	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3466	}
3467	pStdFeatureLeaf = NULL;
3468	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3469
3470	/* Work the sub-leaves. */
3471	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3472	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3473	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3474	{
3475	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3476	if (pCurLeaf)
3477	{
3478	if (fGuestXcr0Mask)
3479	{
3480	switch (uSubLeaf)
3481	{
3482	case 0:
3483	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3484	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3485	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3486	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3487	VERR_CPUM_IPE_1);
3488	cbXSaveMaxActual = pCurLeaf->uEcx;
3489	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3490	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3491	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3492	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3493	VERR_CPUM_IPE_2);
3494	continue;
3495	case 1:
3496	pCurLeaf->uEax &= 0;
3497	pCurLeaf->uEcx &= 0;
3498	pCurLeaf->uEdx &= 0;
3499	/** @todo what about checking ebx? */
3500	continue;
3501	default:
3502	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3503	{
3504	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3505	&& pCurLeaf->uEax > 0
3506	&& pCurLeaf->uEbx < cbXSaveMaxActual
3507	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3508	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3509	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3510	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3511	VERR_CPUM_IPE_2);
3512	AssertLogRel(!(pCurLeaf->uEcx & 1));
3513	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3514	pCurLeaf->uEdx = 0; /* it's reserved... */
3515	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3516	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3517	continue;
3518	}
3519	break;
3520	}
3521	}
3522
3523	/* Clear the leaf. */
3524	pCurLeaf->uEax = 0;
3525	pCurLeaf->uEbx = 0;
3526	pCurLeaf->uEcx = 0;
3527	pCurLeaf->uEdx = 0;
3528	}
3529	}
3530
3531	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3532	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3533	{
3534	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3535	if (pCurLeaf)
3536	{
3537	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3538	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3539	pCurLeaf->uEbx = cbXSaveMaxReport;
3540	pCurLeaf->uEcx = cbXSaveMaxReport;
3541	}
3542	}
3543
3544	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3545	* We zero this since we don't know what it may have been used for.
3546	*/
3547	cpumR3CpuIdZeroLeaf(pCpum, 14);
3548
3549	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3550	* also known as Intel Resource Director Technology (RDT) Monitoring
3551	* We zero this as we don't currently virtualize PQM.
3552	*/
3553	cpumR3CpuIdZeroLeaf(pCpum, 15);
3554
3555	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3556	* also known as Intel Resource Director Technology (RDT) Allocation
3557	* We zero this as we don't currently virtualize PQE.
3558	*/
3559	cpumR3CpuIdZeroLeaf(pCpum, 16);
3560
3561	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3562	* We zero this since we don't know what it may have been used for.
3563	*/
3564	cpumR3CpuIdZeroLeaf(pCpum, 17);
3565
3566	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3567	* We zero this as we don't currently virtualize this.
3568	*/
3569	cpumR3CpuIdZeroLeaf(pCpum, 18);
3570
3571	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3572	* We zero this since we don't know what it may have been used for.
3573	*/
3574	cpumR3CpuIdZeroLeaf(pCpum, 19);
3575
3576	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3577	* We zero this as we don't currently virtualize this.
3578	*/
3579	cpumR3CpuIdZeroLeaf(pCpum, 20);
3580
3581	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3582	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3583	* EAX - denominator (unsigned).
3584	* EBX - numerator (unsigned).
3585	* ECX, EDX - reserved.
3586	* AMD: Reserved / undefined / not implemented.
3587	* VIA: Reserved / undefined / not implemented.
3588	* We zero this as we don't currently virtualize this.
3589	*/
3590	cpumR3CpuIdZeroLeaf(pCpum, 21);
3591
3592	/* Cpuid 0x16: Processor frequency info
3593	* Intel: EAX - Core base frequency in MHz.
3594	* EBX - Core maximum frequency in MHz.
3595	* ECX - Bus (reference) frequency in MHz.
3596	* EDX - Reserved.
3597	* AMD: Reserved / undefined / not implemented.
3598	* VIA: Reserved / undefined / not implemented.
3599	* We zero this as we don't currently virtualize this.
3600	*/
3601	cpumR3CpuIdZeroLeaf(pCpum, 22);
3602
3603	/* Cpuid 0x17..0x10000000: Unknown.
3604	* We don't know these and what they mean, so remove them. */
3605	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3606	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3607
3608
3609	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3610	* We remove all these as we're a hypervisor and must provide our own.
3611	*/
3612	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3613	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3614
3615
3616	/* Cpuid 0x80000000 is harmless. */
3617
3618	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3619
3620	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3621
3622	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3623	* Safe to pass on to the guest.
3624	*
3625	* AMD: 0x800000005 L1 cache information
3626	* 0x800000006 L2/L3 cache information
3627	* Intel: 0x800000005 reserved
3628	* 0x800000006 L2 cache information
3629	* VIA: 0x800000005 TLB and L1 cache information
3630	* 0x800000006 L2 cache information
3631	*/
3632
3633	/* Cpuid 0x800000007: Advanced Power Management Information.
3634	* AMD: EAX: Processor feedback capabilities.
3635	* EBX: RAS capabilites.
3636	* ECX: Advanced power monitoring interface.
3637	* EDX: Enhanced power management capabilities.
3638	* Intel: EAX, EBX, ECX - reserved.
3639	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3640	* VIA: Reserved
3641	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3642	*/
3643	uSubLeaf = 0;
3644	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3645	{
3646	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3647	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3648	{
3649	/*
3650	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3651	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3652	* bit is now configurable.
3653	*/
3654	pCurLeaf->uEdx &= 0
3655	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3656	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3657	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3658	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3659	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3660	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3661	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3662	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3663	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3664	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3665	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3666	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3667	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3668	\| 0;
3669	}
3670	else
3671	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3672	if (!pConfig->fInvariantTsc)
3673	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3674	uSubLeaf++;
3675	}
3676
3677	/* Cpuid 0x80000008:
3678	* AMD: EBX, EDX - reserved
3679	* EAX: Virtual/Physical/Guest address Size
3680	* ECX: Number of cores + APICIdCoreIdSize
3681	* Intel: EAX: Virtual/Physical address Size
3682	* EBX, ECX, EDX - reserved
3683	* VIA: EAX: Virtual/Physical address Size
3684	* EBX, ECX, EDX - reserved
3685	*
3686	* We only expose the virtual+pysical address size to the guest atm.
3687	* On AMD we set the core count, but not the apic id stuff as we're
3688	* currently not doing the apic id assignments in a complatible manner.
3689	*/
3690	uSubLeaf = 0;
3691	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3692	{
3693	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3694	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3695	pCurLeaf->uEdx = 0; /* reserved */
3696
3697	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3698	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3699	pCurLeaf->uEcx = 0;
3700	#ifdef VBOX_WITH_MULTI_CORE
3701	if ( pVM->cCpus > 1
3702	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3703	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3704	#endif
3705	uSubLeaf++;
3706	}
3707
3708	/* Cpuid 0x80000009: Reserved
3709	* We zero this since we don't know what it may have been used for.
3710	*/
3711	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3712
3713	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
3714	* AMD: EAX - SVM revision.
3715	* EBX - Number of ASIDs.
3716	* ECX - Reserved.
3717	* EDX - SVM Feature identification.
3718	*/
3719	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3720	if ( pExtFeatureLeaf
3721	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
3722	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3723	{
3724	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3725	if (pSvmFeatureLeaf)
3726	{
3727	pSvmFeatureLeaf->uEax = 0x1;
3728	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3729	pSvmFeatureLeaf->uEcx = 0;
3730	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3731	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3732	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3733	}
3734	else
3735	{
3736	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
3737	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3738	}
3739	}
3740
3741	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3742	* We clear these as we don't know what purpose they might have. */
3743	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3744	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3745
3746	/* Cpuid 0x80000019: TLB configuration
3747	* Seems to be harmless, pass them thru as is. */
3748
3749	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3750	* Strip anything we don't know what is or addresses feature we don't implement. */
3751	uSubLeaf = 0;
3752	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3753	{
3754	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3755	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3756	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3757	;
3758	pCurLeaf->uEbx = 0; /* reserved */
3759	pCurLeaf->uEcx = 0; /* reserved */
3760	pCurLeaf->uEdx = 0; /* reserved */
3761	uSubLeaf++;
3762	}
3763
3764	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3765	* Clear this as we don't currently virtualize this feature. */
3766	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3767
3768	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3769	* Clear this as we don't currently virtualize this feature. */
3770	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3771
3772	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3773	* We need to sanitize the cores per cache (EAX[25:14]).
3774	*
3775	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3776	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3777	* slightly different meaning.
3778	*/
3779	uSubLeaf = 0;
3780	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3781	{
3782	#ifdef VBOX_WITH_MULTI_CORE
3783	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3784	if (cCores > pVM->cCpus)
3785	cCores = pVM->cCpus;
3786	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3787	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3788	#else
3789	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3790	#endif
3791	uSubLeaf++;
3792	}
3793
3794	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3795	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3796	* setup, we have one compute unit with all the cores in it. Single node.
3797	*/
3798	uSubLeaf = 0;
3799	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3800	{
3801	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3802	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3803	{
3804	#ifdef VBOX_WITH_MULTI_CORE
3805	pCurLeaf->uEbx = pVM->cCpus < 0x100
3806	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3807	#else
3808	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3809	#endif
3810	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3811	}
3812	else
3813	{
3814	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3815	pCurLeaf->uEbx = 0; /* Reserved. */
3816	pCurLeaf->uEcx = 0; /* Reserved. */
3817	}
3818	pCurLeaf->uEdx = 0; /* Reserved. */
3819	uSubLeaf++;
3820	}
3821
3822	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3823	* We don't know these and what they mean, so remove them. */
3824	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3825	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3826
3827	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3828	* Just pass it thru for now. */
3829
3830	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3831	* Just pass it thru for now. */
3832
3833	/* Cpuid 0xc0000000: Centaur stuff.
3834	* Harmless, pass it thru. */
3835
3836	/* Cpuid 0xc0000001: Centaur features.
3837	* VIA: EAX - Family, model, stepping.
3838	* EDX - Centaur extended feature flags. Nothing interesting, except may
3839	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3840	* EBX, ECX - reserved.
3841	* We keep EAX but strips the rest.
3842	*/
3843	uSubLeaf = 0;
3844	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3845	{
3846	pCurLeaf->uEbx = 0;
3847	pCurLeaf->uEcx = 0;
3848	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3849	uSubLeaf++;
3850	}
3851
3852	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3853	* We only have fixed stale values, but should be harmless. */
3854
3855	/* Cpuid 0xc0000003: Reserved.
3856	* We zero this since we don't know what it may have been used for.
3857	*/
3858	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3859
3860	/* Cpuid 0xc0000004: Centaur Performance Info.
3861	* We only have fixed stale values, but should be harmless. */
3862
3863
3864	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3865	* We don't know these and what they mean, so remove them. */
3866	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3867	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3868
3869	return VINF_SUCCESS;
3870	#undef PORTABLE_DISABLE_FEATURE_BIT
3871	#undef PORTABLE_CLEAR_BITS_WHEN
3872	}
3873
3874
3875	/**
3876	* Reads a value in /CPUM/IsaExts/ node.
3877	*
3878	* @returns VBox status code (error message raised).
3879	* @param pVM The cross context VM structure. (For errors.)
3880	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3881	* @param pszValueName The value / extension name.
3882	* @param penmValue Where to return the choice.
3883	* @param enmDefault The default choice.
3884	*/
3885	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3886	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3887	{
3888	/*
3889	* Try integer encoding first.
3890	*/
3891	uint64_t uValue;
3892	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3893	if (RT_SUCCESS(rc))
3894	switch (uValue)
3895	{
3896	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3897	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3898	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3899	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3900	default:
3901	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3902	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3903	pszValueName, uValue);
3904	}
3905	/*
3906	* If missing, use default.
3907	*/
3908	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3909	*penmValue = enmDefault;
3910	else
3911	{
3912	if (rc == VERR_CFGM_NOT_INTEGER)
3913	{
3914	/*
3915	* Not an integer, try read it as a string.
3916	*/
3917	char szValue[32];
3918	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3919	if (RT_SUCCESS(rc))
3920	{
3921	RTStrToLower(szValue);
3922	size_t cchValue = strlen(szValue);
3923	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3924	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3925	*penmValue = CPUMISAEXTCFG_DISABLED;
3926	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3927	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3928	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3929	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3930	else if (EQ("portable"))
3931	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3932	else if (EQ("default") \|\| EQ("def"))
3933	*penmValue = enmDefault;
3934	else
3935	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3936	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3937	pszValueName, uValue);
3938	#undef EQ
3939	}
3940	}
3941	if (RT_FAILURE(rc))
3942	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3943	}
3944	return VINF_SUCCESS;
3945	}
3946
3947
3948	/**
3949	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3950	*
3951	* @returns VBox status code (error message raised).
3952	* @param pVM The cross context VM structure. (For errors.)
3953	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3954	* @param pszValueName The value / extension name.
3955	* @param penmValue Where to return the choice.
3956	* @param enmDefault The default choice.
3957	* @param fAllowed Allowed choice. Applied both to the result and to
3958	* the default value.
3959	*/
3960	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3961	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3962	{
3963	int rc;
3964	if (fAllowed)
3965	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3966	else
3967	{
3968	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3969	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3970	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3971	*penmValue = CPUMISAEXTCFG_DISABLED;
3972	}
3973	return rc;
3974	}
3975
3976
3977	/**
3978	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3979	*
3980	* @returns VBox status code (error message raised).
3981	* @param pVM The cross context VM structure. (For errors.)
3982	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3983	* @param pCpumCfg The /CPUM node (can be NULL).
3984	* @param pszValueName The value / extension name.
3985	* @param penmValue Where to return the choice.
3986	* @param enmDefault The default choice.
3987	*/
3988	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3989	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3990	{
3991	if (CFGMR3Exists(pCpumCfg, pszValueName))
3992	{
3993	if (!CFGMR3Exists(pIsaExts, pszValueName))
3994	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3995	else
3996	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3997	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3998	pszValueName, pszValueName);
3999
4000	bool fLegacy;
4001	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
4002	if (RT_SUCCESS(rc))
4003	{
4004	*penmValue = fLegacy;
4005	return VINF_SUCCESS;
4006	}
4007	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
4008	}
4009
4010	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4011	}
4012
4013
4014	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
4015	{
4016	int rc;
4017
4018	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
4019	* When non-zero CPUID features that could cause portability issues will be
4020	* stripped. The higher the value the more features gets stripped. Higher
4021	* values should only be used when older CPUs are involved since it may
4022	* harm performance and maybe also cause problems with specific guests. */
4023	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
4024	AssertLogRelRCReturn(rc, rc);
4025
4026	/** @cfgm{/CPUM/GuestCpuName, string}
4027	* The name of the CPU we're to emulate. The default is the host CPU.
4028	* Note! CPUs other than "host" one is currently unsupported. */
4029	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
4030	AssertLogRelRCReturn(rc, rc);
4031
4032	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
4033	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
4034	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
4035	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
4036	*/
4037	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
4038	AssertLogRelRCReturn(rc, rc);
4039
4040	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
4041	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
4042	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
4043	* 64-bit linux guests which assume the presence of AMD performance counters
4044	* that we do not virtualize.
4045	*/
4046	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
4047	AssertLogRelRCReturn(rc, rc);
4048
4049	/** @cfgm{/CPUM/ForceVme, boolean, false}
4050	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
4051	* By default the flag is passed thru as is from the host CPU, except
4052	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
4053	* guests and DOS boxes in general.
4054	*/
4055	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
4056	AssertLogRelRCReturn(rc, rc);
4057
4058	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
4059	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
4060	* probably going to be a temporary hack, so don't depend on this.
4061	* The 1st byte of the value is the stepping, the 2nd byte value is the model
4062	* number and the 3rd byte value is the family, and the 4th value must be zero.
4063	*/
4064	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
4065	AssertLogRelRCReturn(rc, rc);
4066
4067	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
4068	* The last standard leaf to keep. The actual last value that is stored in EAX
4069	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
4070	* removed. (This works independently of and differently from NT4LeafLimit.)
4071	* The default is usually set to what we're able to reasonably sanitize.
4072	*/
4073	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
4074	AssertLogRelRCReturn(rc, rc);
4075
4076	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
4077	* The last extended leaf to keep. The actual last value that is stored in EAX
4078	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
4079	* leaf are removed. The default is set to what we're able to sanitize.
4080	*/
4081	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
4082	AssertLogRelRCReturn(rc, rc);
4083
4084	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
4085	* The last extended leaf to keep. The actual last value that is stored in EAX
4086	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
4087	* leaf are removed. The default is set to what we're able to sanitize.
4088	*/
4089	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
4090	AssertLogRelRCReturn(rc, rc);
4091
4092	bool fQueryNestedHwvirt = false;
4093	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4094	fQueryNestedHwvirt \|= RT_BOOL(pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD);
4095	#endif
4096	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4097	fQueryNestedHwvirt \|= RT_BOOL( pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
4098	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA);
4099	#endif
4100	if (fQueryNestedHwvirt)
4101	{
4102	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
4103	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
4104	* The default is false, and when enabled requires a 64-bit CPU with support for
4105	* nested-paging and AMD-V or unrestricted guest mode.
4106	*/
4107	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
4108	AssertLogRelRCReturn(rc, rc);
4109	if ( pConfig->fNestedHWVirt
4110	&& !fNestedPagingAndFullGuestExec)
4111	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4112	"Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
4113
4114	/** @todo Think about enabling this later with NEM/KVM. */
4115	if ( pConfig->fNestedHWVirt
4116	&& VM_IS_NEM_ENABLED(pVM))
4117	{
4118	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
4119	pConfig->fNestedHWVirt = false;
4120	}
4121
4122	#if HC_ARCH_BITS == 32
4123	/* We don't support nested hardware virtualization on 32-bit hosts. */
4124	if (pConfig->fNestedHWVirt)
4125	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4126	"Cannot enable nested VT-x/AMD-V on a 32-bit host\n");
4127	#endif
4128	}
4129
4130	/*
4131	* Instruction Set Architecture (ISA) Extensions.
4132	*/
4133	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
4134	if (pIsaExts)
4135	{
4136	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
4137	"CMPXCHG16B"
4138	"\|MONITOR"
4139	"\|MWaitExtensions"
4140	"\|SSE4.1"
4141	"\|SSE4.2"
4142	"\|XSAVE"
4143	"\|AVX"
4144	"\|AVX2"
4145	"\|AESNI"
4146	"\|PCLMUL"
4147	"\|POPCNT"
4148	"\|MOVBE"
4149	"\|RDRAND"
4150	"\|RDSEED"
4151	"\|CLFLUSHOPT"
4152	"\|FSGSBASE"
4153	"\|PCID"
4154	"\|INVPCID"
4155	"\|FlushCmdMsr"
4156	"\|ABM"
4157	"\|SSE4A"
4158	"\|MISALNSSE"
4159	"\|3DNOWPRF"
4160	"\|AXMMX"
4161	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
4162	if (RT_FAILURE(rc))
4163	return rc;
4164	}
4165
4166	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
4167	* Expose CMPXCHG16B to the guest if supported by the host. For the time
4168	* being the default is to only do this for VMs with nested paging and AMD-V or
4169	* unrestricted guest mode.
4170	*/
4171	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
4172	AssertLogRelRCReturn(rc, rc);
4173
4174	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4175	* Expose MONITOR/MWAIT instructions to the guest.
4176	*/
4177	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4178	AssertLogRelRCReturn(rc, rc);
4179
4180	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4181	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4182	* break on interrupt feature (bit 1).
4183	*/
4184	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4185	AssertLogRelRCReturn(rc, rc);
4186
4187	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4188	* Expose SSE4.1 to the guest if available.
4189	*/
4190	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4191	AssertLogRelRCReturn(rc, rc);
4192
4193	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4194	* Expose SSE4.2 to the guest if available.
4195	*/
4196	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4197	AssertLogRelRCReturn(rc, rc);
4198
4199	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4200	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4201	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
4202	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
4203	&& ( !HMIsLongModeAllowed(pVM)
4204	\|\| NEMHCIsLongModeAllowed(pVM))
4205	#endif
4206	;
4207	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4208
4209	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4210	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4211	* default is to only expose this to VMs with nested paging and AMD-V or
4212	* unrestricted guest execution mode. Not possible to force this one without
4213	* host support at the moment.
4214	*/
4215	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4216	fMayHaveXSave /fAllowed/);
4217	AssertLogRelRCReturn(rc, rc);
4218
4219	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4220	* Expose the AVX instruction set extensions to the guest if available and
4221	* XSAVE is exposed too. For the time being the default is to only expose this
4222	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4223	*/
4224	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4225	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4226	AssertLogRelRCReturn(rc, rc);
4227
4228	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4229	* Expose the AVX2 instruction set extensions to the guest if available and
4230	* XSAVE is exposed too. For the time being the default is to only expose this
4231	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4232	*/
4233	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4234	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4235	AssertLogRelRCReturn(rc, rc);
4236
4237	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4238	* Whether to expose the AES instructions to the guest. For the time being the
4239	* default is to only do this for VMs with nested paging and AMD-V or
4240	* unrestricted guest mode.
4241	*/
4242	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4243	AssertLogRelRCReturn(rc, rc);
4244
4245	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4246	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4247	* being the default is to only do this for VMs with nested paging and AMD-V or
4248	* unrestricted guest mode.
4249	*/
4250	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4251	AssertLogRelRCReturn(rc, rc);
4252
4253	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4254	* Whether to expose the POPCNT instructions to the guest. For the time
4255	* being the default is to only do this for VMs with nested paging and AMD-V or
4256	* unrestricted guest mode.
4257	*/
4258	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4259	AssertLogRelRCReturn(rc, rc);
4260
4261	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4262	* Whether to expose the MOVBE instructions to the guest. For the time
4263	* being the default is to only do this for VMs with nested paging and AMD-V or
4264	* unrestricted guest mode.
4265	*/
4266	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4267	AssertLogRelRCReturn(rc, rc);
4268
4269	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4270	* Whether to expose the RDRAND instructions to the guest. For the time being
4271	* the default is to only do this for VMs with nested paging and AMD-V or
4272	* unrestricted guest mode.
4273	*/
4274	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4275	AssertLogRelRCReturn(rc, rc);
4276
4277	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4278	* Whether to expose the RDSEED instructions to the guest. For the time being
4279	* the default is to only do this for VMs with nested paging and AMD-V or
4280	* unrestricted guest mode.
4281	*/
4282	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4283	AssertLogRelRCReturn(rc, rc);
4284
4285	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4286	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4287	* being the default is to only do this for VMs with nested paging and AMD-V or
4288	* unrestricted guest mode.
4289	*/
4290	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4291	AssertLogRelRCReturn(rc, rc);
4292
4293	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4294	* Whether to expose the read/write FSGSBASE instructions to the guest.
4295	*/
4296	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4297	AssertLogRelRCReturn(rc, rc);
4298
4299	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4300	* Whether to expose the PCID feature to the guest.
4301	*/
4302	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4303	AssertLogRelRCReturn(rc, rc);
4304
4305	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4306	* Whether to expose the INVPCID instruction to the guest.
4307	*/
4308	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4309	AssertLogRelRCReturn(rc, rc);
4310
4311	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
4312	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
4313	*/
4314	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4315	AssertLogRelRCReturn(rc, rc);
4316
4317
4318	/* AMD: */
4319
4320	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4321	* Whether to expose the AMD ABM instructions to the guest. For the time
4322	* being the default is to only do this for VMs with nested paging and AMD-V or
4323	* unrestricted guest mode.
4324	*/
4325	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4326	AssertLogRelRCReturn(rc, rc);
4327
4328	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4329	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4330	* being the default is to only do this for VMs with nested paging and AMD-V or
4331	* unrestricted guest mode.
4332	*/
4333	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4334	AssertLogRelRCReturn(rc, rc);
4335
4336	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4337	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4338	* the time being the default is to only do this for VMs with nested paging and
4339	* AMD-V or unrestricted guest mode.
4340	*/
4341	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4342	AssertLogRelRCReturn(rc, rc);
4343
4344	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4345	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4346	* For the time being the default is to only do this for VMs with nested paging
4347	* and AMD-V or unrestricted guest mode.
4348	*/
4349	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4350	AssertLogRelRCReturn(rc, rc);
4351
4352	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4353	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4354	* the default is to only do this for VMs with nested paging and AMD-V or
4355	* unrestricted guest mode.
4356	*/
4357	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4358	AssertLogRelRCReturn(rc, rc);
4359
4360	return VINF_SUCCESS;
4361	}
4362
4363
4364	/**
4365	* Initializes the emulated CPU's CPUID & MSR information.
4366	*
4367	* @returns VBox status code.
4368	* @param pVM The cross context VM structure.
4369	* @param pHostMsrs Pointer to the host MSRs.
4370	*/
4371	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
4372	{
4373	Assert(pHostMsrs);
4374
4375	PCPUM pCpum = &pVM->cpum.s;
4376	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4377
4378	/*
4379	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4380	* on construction and manage everything from here on.
4381	*/
4382	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
4383	pVM->aCpus[iCpu].cpum.s.fCpuIdApicFeatureVisible = true;
4384
4385	/*
4386	* Read the configuration.
4387	*/
4388	CPUMCPUIDCONFIG Config;
4389	RT_ZERO(Config);
4390
4391	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4392	AssertRCReturn(rc, rc);
4393
4394	/*
4395	* Get the guest CPU data from the database and/or the host.
4396	*
4397	* The CPUID and MSRs are currently living on the regular heap to avoid
4398	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4399	* API for the hyper heap). This means special cleanup considerations.
4400	*/
4401	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4402	if (RT_FAILURE(rc))
4403	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4404	? VMSetError(pVM, rc, RT_SRC_POS,
4405	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4406	: rc;
4407
4408	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4409	{
4410	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4411	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4412	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4413	}
4414	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4415
4416	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4417	* Overrides the guest MSRs.
4418	*/
4419	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4420
4421	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4422	* Overrides the CPUID leaf values (from the host CPU usually) used for
4423	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4424	* values when moving a VM to a different machine. Another use is restricting
4425	* (or extending) the feature set exposed to the guest. */
4426	if (RT_SUCCESS(rc))
4427	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4428
4429	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4430	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4431	"Found unsupported configuration node '/CPUM/CPUID/'. "
4432	"Please use IMachine::setCPUIDLeaf() instead.");
4433
4434	CPUMMSRS GuestMsrs;
4435	RT_ZERO(GuestMsrs);
4436
4437	/*
4438	* Pre-explode the CPUID info.
4439	*/
4440	if (RT_SUCCESS(rc))
4441	{
4442	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
4443	&pCpum->GuestFeatures);
4444	}
4445
4446	/*
4447	* Sanitize the cpuid information passed on to the guest.
4448	*/
4449	if (RT_SUCCESS(rc))
4450	{
4451	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4452	if (RT_SUCCESS(rc))
4453	{
4454	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4455	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4456	}
4457	}
4458
4459	/*
4460	* Setup MSRs introduced in microcode updates or that are otherwise not in
4461	* the CPU profile, but are advertised in the CPUID info we just sanitized.
4462	*/
4463	if (RT_SUCCESS(rc))
4464	rc = cpumR3MsrReconcileWithCpuId(pVM);
4465	/*
4466	* MSR fudging.
4467	*/
4468	if (RT_SUCCESS(rc))
4469	{
4470	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4471	* Fudges some common MSRs if not present in the selected CPU database entry.
4472	* This is for trying to keep VMs running when moved between different hosts
4473	* and different CPU vendors. */
4474	bool fEnable;
4475	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4476	if (RT_SUCCESS(rc) && fEnable)
4477	{
4478	rc = cpumR3MsrApplyFudge(pVM);
4479	AssertLogRelRC(rc);
4480	}
4481	}
4482	if (RT_SUCCESS(rc))
4483	{
4484	/*
4485	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4486	* guest CPU features again.
4487	*/
4488	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4489	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4490	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
4491	RTMemFree(pvFree);
4492
4493	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4494	int rc2 = MMHyperDupMem(pVM, pvFree,
4495	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4496	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4497	RTMemFree(pvFree);
4498	AssertLogRelRCReturn(rc1, rc1);
4499	AssertLogRelRCReturn(rc2, rc2);
4500
4501	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4502	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4503
4504	/*
4505	* Finally, initialize guest VMX MSRs.
4506	*
4507	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
4508	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
4509	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
4510	*/
4511	if (pVM->cpum.s.GuestFeatures.fVmx)
4512	{
4513	Assert(Config.fNestedHWVirt);
4514	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
4515
4516	/* Copy MSRs to all VCPUs */
4517	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
4518	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4519	{
4520	PVMCPU pVCpu = &pVM->aCpus[idCpu];
4521	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
4522	}
4523	}
4524
4525	/*
4526	* Some more configuration that we're applying at the end of everything
4527	* via the CPUMSetGuestCpuIdFeature API.
4528	*/
4529
4530	/* Check if PAE was explicitely enabled by the user. */
4531	bool fEnable;
4532	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4533	AssertRCReturn(rc, rc);
4534	if (fEnable)
4535	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4536
4537	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4538	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4539	AssertRCReturn(rc, rc);
4540	if (fEnable)
4541	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4542
4543	/* Check if speculation control is enabled. */
4544	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4545	AssertRCReturn(rc, rc);
4546	if (fEnable)
4547	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4548
4549	return VINF_SUCCESS;
4550	}
4551
4552	/*
4553	* Failed before switching to hyper heap.
4554	*/
4555	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4556	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4557	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4558	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4559	return rc;
4560	}
4561
4562
4563	/**
4564	* Sets a CPUID feature bit during VM initialization.
4565	*
4566	* Since the CPUID feature bits are generally related to CPU features, other
4567	* CPUM configuration like MSRs can also be modified by calls to this API.
4568	*
4569	* @param pVM The cross context VM structure.
4570	* @param enmFeature The feature to set.
4571	*/
4572	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4573	{
4574	PCPUMCPUIDLEAF pLeaf;
4575	PCPUMMSRRANGE pMsrRange;
4576
4577	switch (enmFeature)
4578	{
4579	/*
4580	* Set the APIC bit in both feature masks.
4581	*/
4582	case CPUMCPUIDFEATURE_APIC:
4583	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4584	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4585	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4586
4587	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4588	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4589	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4590
4591	pVM->cpum.s.GuestFeatures.fApic = 1;
4592
4593	/* Make sure we've got the APICBASE MSR present. */
4594	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4595	if (!pMsrRange)
4596	{
4597	static CPUMMSRRANGE const s_ApicBase =
4598	{
4599	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4600	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4601	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4602	/.szName = / "IA32_APIC_BASE"
4603	};
4604	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4605	AssertLogRelRC(rc);
4606	}
4607
4608	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4609	break;
4610
4611	/*
4612	* Set the x2APIC bit in the standard feature mask.
4613	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4614	*/
4615	case CPUMCPUIDFEATURE_X2APIC:
4616	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4617	if (pLeaf)
4618	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4619	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4620
4621	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4622	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4623	if (pMsrRange)
4624	{
4625	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4626	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4627	}
4628
4629	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4630	break;
4631
4632	/*
4633	* Set the sysenter/sysexit bit in the standard feature mask.
4634	* Assumes the caller knows what it's doing! (host must support these)
4635	*/
4636	case CPUMCPUIDFEATURE_SEP:
4637	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4638	{
4639	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4640	return;
4641	}
4642
4643	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4644	if (pLeaf)
4645	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4646	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4647	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4648	break;
4649
4650	/*
4651	* Set the syscall/sysret bit in the extended feature mask.
4652	* Assumes the caller knows what it's doing! (host must support these)
4653	*/
4654	case CPUMCPUIDFEATURE_SYSCALL:
4655	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4656	if ( !pLeaf
4657	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4658	{
4659	#if HC_ARCH_BITS == 32
4660	/* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit
4661	mode by Intel, even when the cpu is capable of doing so in
4662	64-bit mode. Long mode requires syscall support. */
4663	if (!pVM->cpum.s.HostFeatures.fLongMode)
4664	#endif
4665	{
4666	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4667	return;
4668	}
4669	}
4670
4671	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4672	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4673	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4674	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4675	break;
4676
4677	/*
4678	* Set the PAE bit in both feature masks.
4679	* Assumes the caller knows what it's doing! (host must support these)
4680	*/
4681	case CPUMCPUIDFEATURE_PAE:
4682	if (!pVM->cpum.s.HostFeatures.fPae)
4683	{
4684	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4685	return;
4686	}
4687
4688	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4689	if (pLeaf)
4690	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4691
4692	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4693	if ( pLeaf
4694	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4695	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4696
4697	pVM->cpum.s.GuestFeatures.fPae = 1;
4698	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4699	break;
4700
4701	/*
4702	* Set the LONG MODE bit in the extended feature mask.
4703	* Assumes the caller knows what it's doing! (host must support these)
4704	*/
4705	case CPUMCPUIDFEATURE_LONG_MODE:
4706	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4707	if ( !pLeaf
4708	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4709	{
4710	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4711	return;
4712	}
4713
4714	/* Valid for both Intel and AMD. */
4715	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4716	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4717	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4718	break;
4719
4720	/*
4721	* Set the NX/XD bit in the extended feature mask.
4722	* Assumes the caller knows what it's doing! (host must support these)
4723	*/
4724	case CPUMCPUIDFEATURE_NX:
4725	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4726	if ( !pLeaf
4727	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4728	{
4729	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4730	return;
4731	}
4732
4733	/* Valid for both Intel and AMD. */
4734	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4735	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4736	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4737	break;
4738
4739
4740	/*
4741	* Set the LAHF/SAHF support in 64-bit mode.
4742	* Assumes the caller knows what it's doing! (host must support this)
4743	*/
4744	case CPUMCPUIDFEATURE_LAHF:
4745	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4746	if ( !pLeaf
4747	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4748	{
4749	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4750	return;
4751	}
4752
4753	/* Valid for both Intel and AMD. */
4754	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4755	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4756	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4757	break;
4758
4759	/*
4760	* Set the page attribute table bit. This is alternative page level
4761	* cache control that doesn't much matter when everything is
4762	* virtualized, though it may when passing thru device memory.
4763	*/
4764	case CPUMCPUIDFEATURE_PAT:
4765	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4766	if (pLeaf)
4767	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4768
4769	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4770	if ( pLeaf
4771	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4772	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4773
4774	pVM->cpum.s.GuestFeatures.fPat = 1;
4775	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4776	break;
4777
4778	/*
4779	* Set the RDTSCP support bit.
4780	* Assumes the caller knows what it's doing! (host must support this)
4781	*/
4782	case CPUMCPUIDFEATURE_RDTSCP:
4783	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4784	if ( !pLeaf
4785	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4786	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4787	{
4788	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4789	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4790	return;
4791	}
4792
4793	/* Valid for both Intel and AMD. */
4794	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4795	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4796	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4797	break;
4798
4799	/*
4800	* Set the Hypervisor Present bit in the standard feature mask.
4801	*/
4802	case CPUMCPUIDFEATURE_HVP:
4803	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4804	if (pLeaf)
4805	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4806	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4807	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4808	break;
4809
4810	/*
4811	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4812	* This currently includes the Present bit and MWAITBREAK bit as well.
4813	*/
4814	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4815	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4816	if ( !pLeaf
4817	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4818	{
4819	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4820	return;
4821	}
4822
4823	/* Valid for both Intel and AMD. */
4824	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4825	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4826	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4827	break;
4828
4829	/*
4830	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
4831	* on Intel CPUs, and different on AMDs.
4832	*/
4833	case CPUMCPUIDFEATURE_SPEC_CTRL:
4834	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4835	{
4836	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4837	if ( !pLeaf
4838	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
4839	{
4840	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4841	return;
4842	}
4843
4844	/* The feature can be enabled. Let's see what we can actually do. */
4845	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4846
4847	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4848	if (pVM->cpum.s.HostFeatures.fIbrs)
4849	{
4850	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4851	pVM->cpum.s.GuestFeatures.fIbrs = 1;
4852	if (pVM->cpum.s.HostFeatures.fStibp)
4853	{
4854	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4855	pVM->cpum.s.GuestFeatures.fStibp = 1;
4856	}
4857
4858	/* Make sure we have the speculation control MSR... */
4859	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4860	if (!pMsrRange)
4861	{
4862	static CPUMMSRRANGE const s_SpecCtrl =
4863	{
4864	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
4865	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
4866	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4867	/.szName = / "IA32_SPEC_CTRL"
4868	};
4869	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4870	AssertLogRelRC(rc);
4871	}
4872
4873	/* ... and the predictor command MSR. */
4874	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
4875	if (!pMsrRange)
4876	{
4877	/** @todo incorrect fWrGpMask. */
4878	static CPUMMSRRANGE const s_SpecCtrl =
4879	{
4880	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
4881	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
4882	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4883	/.szName = / "IA32_PRED_CMD"
4884	};
4885	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4886	AssertLogRelRC(rc);
4887	}
4888
4889	}
4890
4891	if (pVM->cpum.s.HostFeatures.fArchCap)
4892	{
4893	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
4894
4895	/* Install the architectural capabilities MSR. */
4896	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
4897	if (!pMsrRange)
4898	{
4899	static CPUMMSRRANGE const s_ArchCaps =
4900	{
4901	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
4902	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
4903	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
4904	/.szName = / "IA32_ARCH_CAPABILITIES"
4905	};
4906	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
4907	AssertLogRelRC(rc);
4908	}
4909	}
4910
4911	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
4912	}
4913	else if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4914	{
4915	/* The precise details of AMD's implementation are not yet clear. */
4916	}
4917	break;
4918
4919	default:
4920	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4921	break;
4922	}
4923
4924	/** @todo can probably kill this as this API is now init time only... */
4925	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4926	{
4927	PVMCPU pVCpu = &pVM->aCpus[i];
4928	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4929	}
4930	}
4931
4932
4933	/**
4934	* Queries a CPUID feature bit.
4935	*
4936	* @returns boolean for feature presence
4937	* @param pVM The cross context VM structure.
4938	* @param enmFeature The feature to query.
4939	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4940	*/
4941	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4942	{
4943	switch (enmFeature)
4944	{
4945	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4946	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4947	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4948	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4949	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4950	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4951	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4952	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4953	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4954	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4955	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4956	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4957	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
4958
4959	case CPUMCPUIDFEATURE_INVALID:
4960	case CPUMCPUIDFEATURE_32BIT_HACK:
4961	break;
4962	}
4963	AssertFailed();
4964	return false;
4965	}
4966
4967
4968	/**
4969	* Clears a CPUID feature bit.
4970	*
4971	* @param pVM The cross context VM structure.
4972	* @param enmFeature The feature to clear.
4973	*
4974	* @deprecated Probably better to default the feature to disabled and only allow
4975	* setting (enabling) it during construction.
4976	*/
4977	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4978	{
4979	PCPUMCPUIDLEAF pLeaf;
4980	switch (enmFeature)
4981	{
4982	case CPUMCPUIDFEATURE_APIC:
4983	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
4984	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4985	if (pLeaf)
4986	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
4987
4988	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4989	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4990	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4991
4992	pVM->cpum.s.GuestFeatures.fApic = 0;
4993	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4994	break;
4995
4996	case CPUMCPUIDFEATURE_X2APIC:
4997	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4998	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4999	if (pLeaf)
5000	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
5001	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
5002	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
5003	break;
5004
5005	case CPUMCPUIDFEATURE_PAE:
5006	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5007	if (pLeaf)
5008	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
5009
5010	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5011	if ( pLeaf
5012	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
5013	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
5014
5015	pVM->cpum.s.GuestFeatures.fPae = 0;
5016	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
5017	break;
5018
5019	case CPUMCPUIDFEATURE_PAT:
5020	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5021	if (pLeaf)
5022	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
5023
5024	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5025	if ( pLeaf
5026	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
5027	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
5028
5029	pVM->cpum.s.GuestFeatures.fPat = 0;
5030	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
5031	break;
5032
5033	case CPUMCPUIDFEATURE_LONG_MODE:
5034	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5035	if (pLeaf)
5036	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
5037	pVM->cpum.s.GuestFeatures.fLongMode = 0;
5038	break;
5039
5040	case CPUMCPUIDFEATURE_LAHF:
5041	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5042	if (pLeaf)
5043	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
5044	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
5045	break;
5046
5047	case CPUMCPUIDFEATURE_RDTSCP:
5048	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5049	if (pLeaf)
5050	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
5051	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
5052	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
5053	break;
5054
5055	case CPUMCPUIDFEATURE_HVP:
5056	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5057	if (pLeaf)
5058	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
5059	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
5060	break;
5061
5062	case CPUMCPUIDFEATURE_MWAIT_EXTS:
5063	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
5064	if (pLeaf)
5065	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
5066	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
5067	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
5068	break;
5069
5070	case CPUMCPUIDFEATURE_SPEC_CTRL:
5071	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
5072	if (pLeaf)
5073	pLeaf->uEdx &= ~( X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP
5074	\| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
5075	pVM->cpum.s.GuestFeatures.fSpeculationControl = 0;
5076	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
5077	break;
5078
5079	default:
5080	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5081	break;
5082	}
5083
5084	for (VMCPUID i = 0; i < pVM->cCpus; i++)
5085	{
5086	PVMCPU pVCpu = &pVM->aCpus[i];
5087	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5088	}
5089	}
5090
5091
5092
5093	/*
5094	*
5095	*
5096	* Saved state related code.
5097	* Saved state related code.
5098	* Saved state related code.
5099	*
5100	*
5101	*/
5102
5103	/**
5104	* Called both in pass 0 and the final pass.
5105	*
5106	* @param pVM The cross context VM structure.
5107	* @param pSSM The saved state handle.
5108	*/
5109	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
5110	{
5111	/*
5112	* Save all the CPU ID leaves.
5113	*/
5114	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
5115	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5116	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
5117	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5118
5119	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5120
5121	/*
5122	* Save a good portion of the raw CPU IDs as well as they may come in
5123	* handy when validating features for raw mode.
5124	*/
5125	CPUMCPUID aRawStd[16];
5126	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
5127	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5128	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
5129	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
5130
5131	CPUMCPUID aRawExt[32];
5132	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
5133	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5134	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
5135	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
5136	}
5137
5138
5139	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5140	{
5141	uint32_t cCpuIds;
5142	int rc = SSMR3GetU32(pSSM, &cCpuIds);
5143	if (RT_SUCCESS(rc))
5144	{
5145	if (cCpuIds < 64)
5146	{
5147	for (uint32_t i = 0; i < cCpuIds; i++)
5148	{
5149	CPUMCPUID CpuId;
5150	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
5151	if (RT_FAILURE(rc))
5152	break;
5153
5154	CPUMCPUIDLEAF NewLeaf;
5155	NewLeaf.uLeaf = uBase + i;
5156	NewLeaf.uSubLeaf = 0;
5157	NewLeaf.fSubLeafMask = 0;
5158	NewLeaf.uEax = CpuId.uEax;
5159	NewLeaf.uEbx = CpuId.uEbx;
5160	NewLeaf.uEcx = CpuId.uEcx;
5161	NewLeaf.uEdx = CpuId.uEdx;
5162	NewLeaf.fFlags = 0;
5163	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
5164	}
5165	}
5166	else
5167	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5168	}
5169	if (RT_FAILURE(rc))
5170	{
5171	RTMemFree(*ppaLeaves);
5172	*ppaLeaves = NULL;
5173	*pcLeaves = 0;
5174	}
5175	return rc;
5176	}
5177
5178
5179	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5180	{
5181	*ppaLeaves = NULL;
5182	*pcLeaves = 0;
5183
5184	int rc;
5185	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
5186	{
5187	/*
5188	* The new format. Starts by declaring the leave size and count.
5189	*/
5190	uint32_t cbLeaf;
5191	SSMR3GetU32(pSSM, &cbLeaf);
5192	uint32_t cLeaves;
5193	rc = SSMR3GetU32(pSSM, &cLeaves);
5194	if (RT_SUCCESS(rc))
5195	{
5196	if (cbLeaf == sizeof(**ppaLeaves))
5197	{
5198	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
5199	{
5200	/*
5201	* Load the leaves one by one.
5202	*
5203	* The uPrev stuff is a kludge for working around a week worth of bad saved
5204	* states during the CPUID revamp in March 2015. We saved too many leaves
5205	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
5206	* garbage entires at the end of the array when restoring. We also had
5207	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
5208	* this kludge doesn't deal correctly with that, but who cares...
5209	*/
5210	uint32_t uPrev = 0;
5211	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
5212	{
5213	CPUMCPUIDLEAF Leaf;
5214	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5215	if (RT_SUCCESS(rc))
5216	{
5217	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5218	\|\| Leaf.uLeaf >= uPrev)
5219	{
5220	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5221	uPrev = Leaf.uLeaf;
5222	}
5223	else
5224	uPrev = UINT32_MAX;
5225	}
5226	}
5227	}
5228	else
5229	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5230	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5231	}
5232	else
5233	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5234	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5235	}
5236	}
5237	else
5238	{
5239	/*
5240	* The old format with its three inflexible arrays.
5241	*/
5242	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5243	if (RT_SUCCESS(rc))
5244	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5245	if (RT_SUCCESS(rc))
5246	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5247	if (RT_SUCCESS(rc))
5248	{
5249	/*
5250	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5251	*/
5252	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5253	if ( pLeaf
5254	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5255	{
5256	CPUMCPUIDLEAF Leaf;
5257	Leaf.uLeaf = 4;
5258	Leaf.fSubLeafMask = UINT32_MAX;
5259	Leaf.uSubLeaf = 0;
5260	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5261	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5262	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5263	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5264	\| UINT32_C(63); /* system coherency line size - 1 */
5265	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5266	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5267	\| (UINT32_C(1) << 5) /* cache level */
5268	\| UINT32_C(1); /* cache type (data) */
5269	Leaf.fFlags = 0;
5270	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5271	if (RT_SUCCESS(rc))
5272	{
5273	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5274	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5275	}
5276	if (RT_SUCCESS(rc))
5277	{
5278	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5279	Leaf.uEcx = 4095; /* sets - 1 */
5280	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5281	Leaf.uEbx \|= UINT32_C(23) << 22;
5282	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5283	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5284	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5285	Leaf.uEax \|= UINT32_C(2) << 5;
5286	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5287	}
5288	}
5289	}
5290	}
5291	return rc;
5292	}
5293
5294
5295	/**
5296	* Loads the CPU ID leaves saved by pass 0, inner worker.
5297	*
5298	* @returns VBox status code.
5299	* @param pVM The cross context VM structure.
5300	* @param pSSM The saved state handle.
5301	* @param uVersion The format version.
5302	* @param paLeaves Guest CPUID leaves loaded from the state.
5303	* @param cLeaves The number of leaves in @a paLeaves.
5304	* @param pMsrs The guest MSRs.
5305	*/
5306	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
5307	{
5308	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5309
5310	/*
5311	* Continue loading the state into stack buffers.
5312	*/
5313	CPUMCPUID GuestDefCpuId;
5314	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5315	AssertRCReturn(rc, rc);
5316
5317	CPUMCPUID aRawStd[16];
5318	uint32_t cRawStd;
5319	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5320	if (cRawStd > RT_ELEMENTS(aRawStd))
5321	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5322	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5323	AssertRCReturn(rc, rc);
5324	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5325	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5326
5327	CPUMCPUID aRawExt[32];
5328	uint32_t cRawExt;
5329	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5330	if (cRawExt > RT_ELEMENTS(aRawExt))
5331	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5332	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5333	AssertRCReturn(rc, rc);
5334	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5335	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5336
5337	/*
5338	* Get the raw CPU IDs for the current host.
5339	*/
5340	CPUMCPUID aHostRawStd[16];
5341	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5342	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5343
5344	CPUMCPUID aHostRawExt[32];
5345	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5346	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5347	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5348
5349	/*
5350	* Get the host and guest overrides so we don't reject the state because
5351	* some feature was enabled thru these interfaces.
5352	* Note! We currently only need the feature leaves, so skip rest.
5353	*/
5354	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5355	CPUMCPUID aHostOverrideStd[2];
5356	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5357	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5358
5359	CPUMCPUID aHostOverrideExt[2];
5360	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5361	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5362
5363	/*
5364	* This can be skipped.
5365	*/
5366	bool fStrictCpuIdChecks;
5367	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5368
5369	/*
5370	* Define a bunch of macros for simplifying the santizing/checking code below.
5371	*/
5372	/* Generic expression + failure message. */
5373	#define CPUID_CHECK_RET(expr, fmt) \
5374	do { \
5375	if (!(expr)) \
5376	{ \
5377	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5378	if (fStrictCpuIdChecks) \
5379	{ \
5380	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5381	RTStrFree(pszMsg); \
5382	return rcCpuid; \
5383	} \
5384	LogRel(("CPUM: %s\n", pszMsg)); \
5385	RTStrFree(pszMsg); \
5386	} \
5387	} while (0)
5388	#define CPUID_CHECK_WRN(expr, fmt) \
5389	do { \
5390	if (!(expr)) \
5391	LogRel(fmt); \
5392	} while (0)
5393
5394	/* For comparing two values and bitch if they differs. */
5395	#define CPUID_CHECK2_RET(what, host, saved) \
5396	do { \
5397	if ((host) != (saved)) \
5398	{ \
5399	if (fStrictCpuIdChecks) \
5400	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5401	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5402	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5403	} \
5404	} while (0)
5405	#define CPUID_CHECK2_WRN(what, host, saved) \
5406	do { \
5407	if ((host) != (saved)) \
5408	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5409	} while (0)
5410
5411	/* For checking raw cpu features (raw mode). */
5412	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5413	do { \
5414	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5415	{ \
5416	if (fStrictCpuIdChecks) \
5417	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5418	N_(#bit " mismatch: host=%d saved=%d"), \
5419	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5420	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5421	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5422	} \
5423	} while (0)
5424	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5425	do { \
5426	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5427	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5428	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5429	} while (0)
5430	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5431
5432	/* For checking guest features. */
5433	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5434	do { \
5435	if ( (aGuestCpuId##set [1].reg & bit) \
5436	&& !(aHostRaw##set [1].reg & bit) \
5437	&& !(aHostOverride##set [1].reg & bit) \
5438	) \
5439	{ \
5440	if (fStrictCpuIdChecks) \
5441	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5442	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5443	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5444	} \
5445	} while (0)
5446	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5447	do { \
5448	if ( (aGuestCpuId##set [1].reg & bit) \
5449	&& !(aHostRaw##set [1].reg & bit) \
5450	&& !(aHostOverride##set [1].reg & bit) \
5451	) \
5452	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5453	} while (0)
5454	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5455	do { \
5456	if ( (aGuestCpuId##set [1].reg & bit) \
5457	&& !(aHostRaw##set [1].reg & bit) \
5458	&& !(aHostOverride##set [1].reg & bit) \
5459	) \
5460	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5461	} while (0)
5462	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5463
5464	/* For checking guest features if AMD guest CPU. */
5465	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5466	do { \
5467	if ( (aGuestCpuId##set [1].reg & bit) \
5468	&& fGuestAmd \
5469	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5470	&& !(aHostOverride##set [1].reg & bit) \
5471	) \
5472	{ \
5473	if (fStrictCpuIdChecks) \
5474	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5475	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5476	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5477	} \
5478	} while (0)
5479	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5480	do { \
5481	if ( (aGuestCpuId##set [1].reg & bit) \
5482	&& fGuestAmd \
5483	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5484	&& !(aHostOverride##set [1].reg & bit) \
5485	) \
5486	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5487	} while (0)
5488	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5489	do { \
5490	if ( (aGuestCpuId##set [1].reg & bit) \
5491	&& fGuestAmd \
5492	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5493	&& !(aHostOverride##set [1].reg & bit) \
5494	) \
5495	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5496	} while (0)
5497	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5498
5499	/* For checking AMD features which have a corresponding bit in the standard
5500	range. (Intel defines very few bits in the extended feature sets.) */
5501	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5502	do { \
5503	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5504	&& !(fHostAmd \
5505	? aHostRawExt[1].reg & (ExtBit) \
5506	: aHostRawStd[1].reg & (StdBit)) \
5507	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5508	) \
5509	{ \
5510	if (fStrictCpuIdChecks) \
5511	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5512	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5513	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5514	} \
5515	} while (0)
5516	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5517	do { \
5518	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5519	&& !(fHostAmd \
5520	? aHostRawExt[1].reg & (ExtBit) \
5521	: aHostRawStd[1].reg & (StdBit)) \
5522	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5523	) \
5524	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5525	} while (0)
5526	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5527	do { \
5528	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5529	&& !(fHostAmd \
5530	? aHostRawExt[1].reg & (ExtBit) \
5531	: aHostRawStd[1].reg & (StdBit)) \
5532	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5533	) \
5534	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5535	} while (0)
5536	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5537
5538	/*
5539	* For raw-mode we'll require that the CPUs are very similar since we don't
5540	* intercept CPUID instructions for user mode applications.
5541	*/
5542	if (VM_IS_RAW_MODE_ENABLED(pVM))
5543	{
5544	/* CPUID(0) */
5545	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
5546	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
5547	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
5548	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5549	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
5550	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
5551	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
5552	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
5553	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5554
5555	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
5556
5557	/* CPUID(1).eax */
5558	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
5559	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
5560	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
5561
5562	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
5563	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
5564	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
5565
5566	/* CPUID(1).ecx */
5567	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
5568	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
5569	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
5570	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5571	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
5572	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
5573	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
5574	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
5575	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
5576	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
5577	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
5578	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
5579	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
5580	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
5581	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
5582	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
5583	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5584	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5585	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
5586	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
5587	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
5588	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5589	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
5590	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
5591	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5592	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
5593	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
5594	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5595	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
5596	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5597	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5598	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
5599
5600	/* CPUID(1).edx */
5601	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5602	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5603	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
5604	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5605	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
5606	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
5607	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5608	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5609	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
5610	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5611	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5612	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5613	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5614	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5615	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5616	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
5617	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5618	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5619	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5620	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
5621	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5622	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
5623	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
5624	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
5625	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
5626	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
5627	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
5628	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
5629	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
5630	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
5631	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
5632	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
5633
5634	/* CPUID(2) - config, mostly about caches. ignore. */
5635	/* CPUID(3) - processor serial number. ignore. */
5636	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
5637	/* CPUID(5) - mwait/monitor config. ignore. */
5638	/* CPUID(6) - power management. ignore. */
5639	/* CPUID(7) - ???. ignore. */
5640	/* CPUID(8) - ???. ignore. */
5641	/* CPUID(9) - DCA. ignore for now. */
5642	/* CPUID(a) - PeMo info. ignore for now. */
5643	/* CPUID(b) - topology info - takes ECX as input. ignore. */
5644
5645	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
5646	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
5647	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
5648	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
5649	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
5650	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
5651	{
5652	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
5653	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
5654	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
5655	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
5656	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
5657	}
5658
5659	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
5660	Note! Intel have/is marking many of the fields here as reserved. We
5661	will verify them as if it's an AMD CPU. */
5662	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
5663	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
5664	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
5665	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
5666	{
5667	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
5668	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
5669	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
5670	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5671	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
5672	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
5673	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
5674
5675	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
5676	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
5677	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
5678	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
5679	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
5680	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5681
5682	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
5683	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
5684	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
5685	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
5686
5687	/* CPUID(0x80000001).ecx */
5688	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
5689	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
5690	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
5691	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
5692	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
5693	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
5694	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
5695	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
5696	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
5697	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
5698	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
5699	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
5700	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
5701	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
5702	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5703	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5704	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5705	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5706	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5707	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5708	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5709	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5710	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5711	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5712	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5713	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5714	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5715	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5716	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5717	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5718	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5719	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5720
5721	/* CPUID(0x80000001).edx */
5722	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
5723	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
5724	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
5725	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
5726	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
5727	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
5728	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
5729	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
5730	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
5731	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
5732	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5733	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
5734	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
5735	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
5736	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
5737	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
5738	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
5739	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
5740	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5741	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5742	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5743	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
5744	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5745	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
5746	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
5747	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5748	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5749	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5750	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
5751	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5752	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5753	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5754
5755	/** @todo verify the rest as well. */
5756	}
5757	}
5758
5759
5760
5761	/*
5762	* Verify that we can support the features already exposed to the guest on
5763	* this host.
5764	*
5765	* Most of the features we're emulating requires intercepting instruction
5766	* and doing it the slow way, so there is no need to warn when they aren't
5767	* present in the host CPU. Thus we use IGN instead of EMU on these.
5768	*
5769	* Trailing comments:
5770	* "EMU" - Possible to emulate, could be lots of work and very slow.
5771	* "EMU?" - Can this be emulated?
5772	*/
5773	CPUMCPUID aGuestCpuIdStd[2];
5774	RT_ZERO(aGuestCpuIdStd);
5775	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5776
5777	/* CPUID(1).ecx */
5778	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5779	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5780	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5781	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5782	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5783	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5784	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5785	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5786	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5787	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5788	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5789	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5790	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5791	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5792	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5793	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5794	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5795	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5796	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5797	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5798	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5799	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5800	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5801	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5802	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5803	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5804	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5805	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5806	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5807	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5808	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5809	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5810
5811	/* CPUID(1).edx */
5812	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5813	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5814	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5815	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5816	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5817	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5818	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5819	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5820	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5821	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5822	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5823	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5824	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5825	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5826	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5827	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5828	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5829	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5830	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5831	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5832	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5833	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5834	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5835	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5836	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5837	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5838	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5839	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5840	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5841	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5842	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5843	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5844
5845	/* CPUID(0x80000000). */
5846	CPUMCPUID aGuestCpuIdExt[2];
5847	RT_ZERO(aGuestCpuIdExt);
5848	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5849	{
5850	/** @todo deal with no 0x80000001 on the host. */
5851	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5852	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5853
5854	/* CPUID(0x80000001).ecx */
5855	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5856	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5857	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5858	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5859	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5860	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5861	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5862	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5863	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5864	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5865	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5866	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5867	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5868	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5869	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5870	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5871	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5872	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5873	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5874	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5875	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5876	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5877	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5878	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5879	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5880	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5881	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5882	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5883	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5884	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5885	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5886	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5887
5888	/* CPUID(0x80000001).edx */
5889	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5890	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5891	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5892	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5893	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5894	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5895	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5896	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5897	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5898	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5899	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5900	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5901	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5902	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5903	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5904	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5905	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5906	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5907	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5908	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5909	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5910	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5911	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5912	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5913	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5914	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5915	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5916	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5917	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5918	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5919	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5920	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5921	}
5922
5923	/** @todo check leaf 7 */
5924
5925	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5926	* ECX=0: EAX - Valid bits in XCR0[31:0].
5927	* EBX - Maximum state size as per current XCR0 value.
5928	* ECX - Maximum state size for all supported features.
5929	* EDX - Valid bits in XCR0[63:32].
5930	* ECX=1: EAX - Various X-features.
5931	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5932	* ECX - Valid bits in IA32_XSS[31:0].
5933	* EDX - Valid bits in IA32_XSS[63:32].
5934	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5935	* if the bit invalid all four registers are set to zero.
5936	* EAX - The state size for this feature.
5937	* EBX - The state byte offset of this feature.
5938	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5939	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5940	*/
5941	uint64_t fGuestXcr0Mask = 0;
5942	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5943	if ( pCurLeaf
5944	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5945	&& ( pCurLeaf->uEax
5946	\|\| pCurLeaf->uEbx
5947	\|\| pCurLeaf->uEcx
5948	\|\| pCurLeaf->uEdx) )
5949	{
5950	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5951	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5952	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5953	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5954	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5955	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5956	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5957	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5958
5959	/* We don't support any additional features yet. */
5960	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5961	if (pCurLeaf && pCurLeaf->uEax)
5962	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5963	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5964	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5965	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5966	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5967	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5968
5969
5970	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5971	{
5972	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5973	if (pCurLeaf)
5974	{
5975	/* If advertised, the state component offset and size must match the one used by host. */
5976	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5977	{
5978	CPUMCPUID RawHost;
5979	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5980	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5981	if ( RawHost.uEbx != pCurLeaf->uEbx
5982	\|\| RawHost.uEax != pCurLeaf->uEax)
5983	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5984	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5985	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5986	}
5987	}
5988	}
5989	}
5990	/* Clear leaf 0xd just in case we're loading an old state... */
5991	else if (pCurLeaf)
5992	{
5993	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5994	{
5995	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5996	if (pCurLeaf)
5997	{
5998	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5999	\|\| ( pCurLeaf->uEax == 0
6000	&& pCurLeaf->uEbx == 0
6001	&& pCurLeaf->uEcx == 0
6002	&& pCurLeaf->uEdx == 0),
6003	("uVersion=%#x; %#x %#x %#x %#x\n",
6004	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
6005	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
6006	}
6007	}
6008	}
6009
6010	/* Update the fXStateGuestMask value for the VM. */
6011	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
6012	{
6013	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
6014	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
6015	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
6016	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
6017	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
6018	}
6019
6020	#undef CPUID_CHECK_RET
6021	#undef CPUID_CHECK_WRN
6022	#undef CPUID_CHECK2_RET
6023	#undef CPUID_CHECK2_WRN
6024	#undef CPUID_RAW_FEATURE_RET
6025	#undef CPUID_RAW_FEATURE_WRN
6026	#undef CPUID_RAW_FEATURE_IGN
6027	#undef CPUID_GST_FEATURE_RET
6028	#undef CPUID_GST_FEATURE_WRN
6029	#undef CPUID_GST_FEATURE_EMU
6030	#undef CPUID_GST_FEATURE_IGN
6031	#undef CPUID_GST_FEATURE2_RET
6032	#undef CPUID_GST_FEATURE2_WRN
6033	#undef CPUID_GST_FEATURE2_EMU
6034	#undef CPUID_GST_FEATURE2_IGN
6035	#undef CPUID_GST_AMD_FEATURE_RET
6036	#undef CPUID_GST_AMD_FEATURE_WRN
6037	#undef CPUID_GST_AMD_FEATURE_EMU
6038	#undef CPUID_GST_AMD_FEATURE_IGN
6039
6040	/*
6041	* We're good, commit the CPU ID leaves.
6042	*/
6043	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
6044	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
6045	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
6046	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
6047	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
6048	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
6049	AssertLogRelRCReturn(rc, rc);
6050
6051	return VINF_SUCCESS;
6052	}
6053
6054
6055	/**
6056	* Loads the CPU ID leaves saved by pass 0.
6057	*
6058	* @returns VBox status code.
6059	* @param pVM The cross context VM structure.
6060	* @param pSSM The saved state handle.
6061	* @param uVersion The format version.
6062	* @param pMsrs The guest MSRs.
6063	*/
6064	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
6065	{
6066	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
6067
6068	/*
6069	* Load the CPUID leaves array first and call worker to do the rest, just so
6070	* we can free the memory when we need to without ending up in column 1000.
6071	*/
6072	PCPUMCPUIDLEAF paLeaves;
6073	uint32_t cLeaves;
6074	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
6075	AssertRC(rc);
6076	if (RT_SUCCESS(rc))
6077	{
6078	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
6079	RTMemFree(paLeaves);
6080	}
6081	return rc;
6082	}
6083
6084
6085
6086	/**
6087	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
6088	*
6089	* @returns VBox status code.
6090	* @param pVM The cross context VM structure.
6091	* @param pSSM The saved state handle.
6092	* @param uVersion The format version.
6093	*/
6094	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
6095	{
6096	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
6097
6098	/*
6099	* Restore the CPUID leaves.
6100	*
6101	* Note that we support restoring less than the current amount of standard
6102	* leaves because we've been allowed more is newer version of VBox.
6103	*/
6104	uint32_t cElements;
6105	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6106	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
6107	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6108	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
6109
6110	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6111	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
6112	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6113	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
6114
6115	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6116	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
6117	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6118	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
6119
6120	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
6121
6122	/*
6123	* Check that the basic cpuid id information is unchanged.
6124	*/
6125	/** @todo we should check the 64 bits capabilities too! */
6126	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
6127	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
6128	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
6129	uint32_t au32CpuIdSaved[8];
6130	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
6131	if (RT_SUCCESS(rc))
6132	{
6133	/* Ignore CPU stepping. */
6134	au32CpuId[4] &= 0xfffffff0;
6135	au32CpuIdSaved[4] &= 0xfffffff0;
6136
6137	/* Ignore APIC ID (AMD specs). */
6138	au32CpuId[5] &= ~0xff000000;
6139	au32CpuIdSaved[5] &= ~0xff000000;
6140
6141	/* Ignore the number of Logical CPUs (AMD specs). */
6142	au32CpuId[5] &= ~0x00ff0000;
6143	au32CpuIdSaved[5] &= ~0x00ff0000;
6144
6145	/* Ignore some advanced capability bits, that we don't expose to the guest. */
6146	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6147	\| X86_CPUID_FEATURE_ECX_VMX
6148	\| X86_CPUID_FEATURE_ECX_SMX
6149	\| X86_CPUID_FEATURE_ECX_EST
6150	\| X86_CPUID_FEATURE_ECX_TM2
6151	\| X86_CPUID_FEATURE_ECX_CNTXID
6152	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6153	\| X86_CPUID_FEATURE_ECX_PDCM
6154	\| X86_CPUID_FEATURE_ECX_DCA
6155	\| X86_CPUID_FEATURE_ECX_X2APIC
6156	);
6157	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6158	\| X86_CPUID_FEATURE_ECX_VMX
6159	\| X86_CPUID_FEATURE_ECX_SMX
6160	\| X86_CPUID_FEATURE_ECX_EST
6161	\| X86_CPUID_FEATURE_ECX_TM2
6162	\| X86_CPUID_FEATURE_ECX_CNTXID
6163	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6164	\| X86_CPUID_FEATURE_ECX_PDCM
6165	\| X86_CPUID_FEATURE_ECX_DCA
6166	\| X86_CPUID_FEATURE_ECX_X2APIC
6167	);
6168
6169	/* Make sure we don't forget to update the masks when enabling
6170	* features in the future.
6171	*/
6172	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
6173	( X86_CPUID_FEATURE_ECX_DTES64
6174	\| X86_CPUID_FEATURE_ECX_VMX
6175	\| X86_CPUID_FEATURE_ECX_SMX
6176	\| X86_CPUID_FEATURE_ECX_EST
6177	\| X86_CPUID_FEATURE_ECX_TM2
6178	\| X86_CPUID_FEATURE_ECX_CNTXID
6179	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6180	\| X86_CPUID_FEATURE_ECX_PDCM
6181	\| X86_CPUID_FEATURE_ECX_DCA
6182	\| X86_CPUID_FEATURE_ECX_X2APIC
6183	)));
6184	/* do the compare */
6185	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
6186	{
6187	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
6188	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
6189	"Saved=%.*Rhxs\n"
6190	"Real =%.*Rhxs\n",
6191	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6192	sizeof(au32CpuId), au32CpuId));
6193	else
6194	{
6195	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
6196	"Saved=%.*Rhxs\n"
6197	"Real =%.*Rhxs\n",
6198	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6199	sizeof(au32CpuId), au32CpuId));
6200	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
6201	}
6202	}
6203	}
6204
6205	return rc;
6206	}
6207
6208
6209
6210	/*
6211	*
6212	*
6213	* CPUID Info Handler.
6214	* CPUID Info Handler.
6215	* CPUID Info Handler.
6216	*
6217	*
6218	*/
6219
6220
6221
6222	/**
6223	* Get L1 cache / TLS associativity.
6224	*/
6225	static const char getCacheAss(unsigned u, char pszBuf)
6226	{
6227	if (u == 0)
6228	return "res0 ";
6229	if (u == 1)
6230	return "direct";
6231	if (u == 255)
6232	return "fully";
6233	if (u >= 256)
6234	return "???";
6235
6236	RTStrPrintf(pszBuf, 16, "%d way", u);
6237	return pszBuf;
6238	}
6239
6240
6241	/**
6242	* Get L2 cache associativity.
6243	*/
6244	const char *getL2CacheAss(unsigned u)
6245	{
6246	switch (u)
6247	{
6248	case 0: return "off ";
6249	case 1: return "direct";
6250	case 2: return "2 way ";
6251	case 3: return "res3 ";
6252	case 4: return "4 way ";
6253	case 5: return "res5 ";
6254	case 6: return "8 way ";
6255	case 7: return "res7 ";
6256	case 8: return "16 way";
6257	case 9: return "res9 ";
6258	case 10: return "res10 ";
6259	case 11: return "res11 ";
6260	case 12: return "res12 ";
6261	case 13: return "res13 ";
6262	case 14: return "res14 ";
6263	case 15: return "fully ";
6264	default: return "????";
6265	}
6266	}
6267
6268
6269	/** CPUID(1).EDX field descriptions. */
6270	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6271	{
6272	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6273	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6274	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6275	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6276	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6277	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6278	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6279	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6280	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6281	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6282	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6283	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6284	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6285	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6286	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6287	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6288	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6289	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6290	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6291	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6292	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6293	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6294	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6295	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6296	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6297	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6298	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6299	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6300	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6301	DBGFREGSUBFIELD_TERMINATOR()
6302	};
6303
6304	/** CPUID(1).ECX field descriptions. */
6305	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6306	{
6307	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6308	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6309	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6310	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6311	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6312	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6313	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6314	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6315	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6316	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6317	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6318	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6319	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6320	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6321	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6322	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6323	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6324	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6325	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6326	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6327	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6328	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6329	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6330	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6331	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6332	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6333	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6334	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6335	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6336	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6337	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6338	DBGFREGSUBFIELD_TERMINATOR()
6339	};
6340
6341	/** CPUID(7,0).EBX field descriptions. */
6342	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6343	{
6344	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6345	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6346	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6347	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6348	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6349	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6350	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6351	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6352	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6353	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6354	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6355	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6356	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6357	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6358	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6359	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6360	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6361	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6362	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6363	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6364	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6365	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6366	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6367	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6368	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6369	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6370	DBGFREGSUBFIELD_TERMINATOR()
6371	};
6372
6373	/** CPUID(7,0).ECX field descriptions. */
6374	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6375	{
6376	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6377	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6378	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6379	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6380	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6381	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6382	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6383	DBGFREGSUBFIELD_TERMINATOR()
6384	};
6385
6386	/** CPUID(7,0).EDX field descriptions. */
6387	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6388	{
6389	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6390	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6391	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
6392	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6393	DBGFREGSUBFIELD_TERMINATOR()
6394	};
6395
6396
6397	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6398	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6399	{
6400	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6401	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6402	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6403	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6404	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6405	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6406	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6407	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6408	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6409	DBGFREGSUBFIELD_TERMINATOR()
6410	};
6411
6412	/** CPUID(13,1).EAX field descriptions. */
6413	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6414	{
6415	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6416	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6417	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6418	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6419	DBGFREGSUBFIELD_TERMINATOR()
6420	};
6421
6422
6423	/** CPUID(0x80000001,0).EDX field descriptions. */
6424	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6425	{
6426	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6427	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6428	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6429	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6430	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6431	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6432	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6433	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6434	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6435	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6436	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6437	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6438	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6439	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6440	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6441	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6442	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6443	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6444	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6445	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6446	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6447	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6448	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6449	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6450	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6451	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6452	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6453	DBGFREGSUBFIELD_TERMINATOR()
6454	};
6455
6456	/** CPUID(0x80000001,0).ECX field descriptions. */
6457	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6458	{
6459	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6460	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6461	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6462	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6463	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6464	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6465	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6466	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6467	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6468	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6469	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6470	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6471	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6472	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6473	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6474	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6475	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6476	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6477	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6478	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6479	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6480	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6481	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6482	DBGFREGSUBFIELD_TERMINATOR()
6483	};
6484
6485	/** CPUID(0x8000000a,0).EDX field descriptions. */
6486	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6487	{
6488	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6489	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6490	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6491	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6492	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6493	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6494	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6495	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6496	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6497	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6498	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6499	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6500	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6501	DBGFREGSUBFIELD_TERMINATOR()
6502	};
6503
6504
6505	/** CPUID(0x80000007,0).EDX field descriptions. */
6506	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6507	{
6508	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6509	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6510	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6511	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6512	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6513	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6514	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6515	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6516	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6517	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6518	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6519	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6520	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6521	DBGFREGSUBFIELD_TERMINATOR()
6522	};
6523
6524	/** CPUID(0x80000008,0).EBX field descriptions. */
6525	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6526	{
6527	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6528	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6529	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6530	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6531	DBGFREGSUBFIELD_TERMINATOR()
6532	};
6533
6534
6535	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6536	const char *pszLeadIn, uint32_t cchWidth)
6537	{
6538	if (pszLeadIn)
6539	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6540
6541	for (uint32_t iBit = 0; iBit < 32; iBit++)
6542	if (RT_BIT_32(iBit) & uVal)
6543	{
6544	while ( pDesc->pszName != NULL
6545	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6546	pDesc++;
6547	if ( pDesc->pszName != NULL
6548	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6549	{
6550	if (pDesc->cBits == 1)
6551	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6552	else
6553	{
6554	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6555	if (pDesc->cBits < 32)
6556	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6557	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6558	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6559	}
6560	}
6561	else
6562	pHlp->pfnPrintf(pHlp, " %u", iBit);
6563	}
6564	if (pszLeadIn)
6565	pHlp->pfnPrintf(pHlp, "\n");
6566	}
6567
6568
6569	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6570	const char *pszLeadIn, uint32_t cchWidth)
6571	{
6572	if (pszLeadIn)
6573	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6574
6575	for (uint32_t iBit = 0; iBit < 64; iBit++)
6576	if (RT_BIT_64(iBit) & uVal)
6577	{
6578	while ( pDesc->pszName != NULL
6579	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6580	pDesc++;
6581	if ( pDesc->pszName != NULL
6582	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6583	{
6584	if (pDesc->cBits == 1)
6585	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6586	else
6587	{
6588	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6589	if (pDesc->cBits < 64)
6590	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6591	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6592	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6593	}
6594	}
6595	else
6596	pHlp->pfnPrintf(pHlp, " %u", iBit);
6597	}
6598	if (pszLeadIn)
6599	pHlp->pfnPrintf(pHlp, "\n");
6600	}
6601
6602
6603	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6604	const char *pszLeadIn, uint32_t cchWidth)
6605	{
6606	if (!uVal)
6607	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6608	else
6609	{
6610	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6611	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6612	pHlp->pfnPrintf(pHlp, " )\n");
6613	}
6614	}
6615
6616
6617	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6618	uint32_t cchWidth)
6619	{
6620	uint32_t uCombined = uVal1 \| uVal2;
6621	for (uint32_t iBit = 0; iBit < 32; iBit++)
6622	if ( (RT_BIT_32(iBit) & uCombined)
6623	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6624	{
6625	while ( pDesc->pszName != NULL
6626	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6627	pDesc++;
6628
6629	if ( pDesc->pszName != NULL
6630	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6631	{
6632	size_t cchMnemonic = strlen(pDesc->pszName);
6633	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6634	size_t cchDesc = strlen(pszDesc);
6635	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6636	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6637	if (pDesc->cBits < 32)
6638	{
6639	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6640	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6641	}
6642
6643	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6644	pDesc->pszName, pszDesc,
6645	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6646	uFieldValue1, uFieldValue2);
6647
6648	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6649	pDesc++;
6650	}
6651	else
6652	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6653	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6654	}
6655	}
6656
6657
6658	/**
6659	* Produces a detailed summary of standard leaf 0x00000001.
6660	*
6661	* @param pHlp The info helper functions.
6662	* @param pCurLeaf The 0x00000001 leaf.
6663	* @param fVerbose Whether to be very verbose or not.
6664	* @param fIntel Set if intel CPU.
6665	*/
6666	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6667	{
6668	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6669	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6670	uint32_t uEAX = pCurLeaf->uEax;
6671	uint32_t uEBX = pCurLeaf->uEbx;
6672
6673	pHlp->pfnPrintf(pHlp,
6674	"%36s %2d \tExtended: %d \tEffective: %d\n"
6675	"%36s %2d \tExtended: %d \tEffective: %d\n"
6676	"%36s %d\n"
6677	"%36s %d (%s)\n"
6678	"%36s %#04x\n"
6679	"%36s %d\n"
6680	"%36s %d\n"
6681	"%36s %#04x\n"
6682	,
6683	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6684	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6685	"Stepping:", ASMGetCpuStepping(uEAX),
6686	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6687	"APIC ID:", (uEBX >> 24) & 0xff,
6688	"Logical CPUs:",(uEBX >> 16) & 0xff,
6689	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6690	"Brand ID:", (uEBX >> 0) & 0xff);
6691	if (fVerbose)
6692	{
6693	CPUMCPUID Host;
6694	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6695	pHlp->pfnPrintf(pHlp, "Features\n");
6696	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6697	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6698	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6699	}
6700	else
6701	{
6702	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6703	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6704	}
6705	}
6706
6707
6708	/**
6709	* Produces a detailed summary of standard leaf 0x00000007.
6710	*
6711	* @param pHlp The info helper functions.
6712	* @param paLeaves The CPUID leaves array.
6713	* @param cLeaves The number of leaves in the array.
6714	* @param pCurLeaf The first 0x00000007 leaf.
6715	* @param fVerbose Whether to be very verbose or not.
6716	*/
6717	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6718	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6719	{
6720	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6721	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6722	for (;;)
6723	{
6724	CPUMCPUID Host;
6725	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6726
6727	switch (pCurLeaf->uSubLeaf)
6728	{
6729	case 0:
6730	if (fVerbose)
6731	{
6732	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6733	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6734	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6735	if (pCurLeaf->uEdx \|\| Host.uEdx)
6736	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6737	}
6738	else
6739	{
6740	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6741	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6742	if (pCurLeaf->uEdx)
6743	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6744	}
6745	break;
6746
6747	default:
6748	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6749	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6750	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6751	break;
6752
6753	}
6754
6755	/* advance. */
6756	pCurLeaf++;
6757	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6758	\|\| pCurLeaf->uLeaf != 0x7)
6759	break;
6760	}
6761	}
6762
6763
6764	/**
6765	* Produces a detailed summary of standard leaf 0x0000000d.
6766	*
6767	* @param pHlp The info helper functions.
6768	* @param paLeaves The CPUID leaves array.
6769	* @param cLeaves The number of leaves in the array.
6770	* @param pCurLeaf The first 0x00000007 leaf.
6771	* @param fVerbose Whether to be very verbose or not.
6772	*/
6773	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6774	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6775	{
6776	RT_NOREF_PV(fVerbose);
6777	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6778	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6779	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6780	{
6781	CPUMCPUID Host;
6782	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6783
6784	switch (uSubLeaf)
6785	{
6786	case 0:
6787	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6788	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6789	pCurLeaf->uEbx, pCurLeaf->uEcx);
6790	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6791
6792	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6793	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6794	"Valid XCR0 bits, guest:", 42);
6795	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6796	"Valid XCR0 bits, host:", 42);
6797	break;
6798
6799	case 1:
6800	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6801	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6802	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6803
6804	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6805	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6806	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6807
6808	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6809	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6810	" Valid IA32_XSS bits, guest:", 42);
6811	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6812	" Valid IA32_XSS bits, host:", 42);
6813	break;
6814
6815	default:
6816	if ( pCurLeaf
6817	&& pCurLeaf->uSubLeaf == uSubLeaf
6818	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6819	{
6820	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6821	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6822	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6823	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6824	if (pCurLeaf->uEdx)
6825	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6826	pHlp->pfnPrintf(pHlp, " --");
6827	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6828	pHlp->pfnPrintf(pHlp, "\n");
6829	}
6830	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6831	{
6832	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6833	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6834	if (Host.uEcx & ~RT_BIT_32(0))
6835	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6836	if (Host.uEdx)
6837	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6838	pHlp->pfnPrintf(pHlp, " --");
6839	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6840	pHlp->pfnPrintf(pHlp, "\n");
6841	}
6842	break;
6843
6844	}
6845
6846	/* advance. */
6847	if (pCurLeaf)
6848	{
6849	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6850	&& pCurLeaf->uSubLeaf <= uSubLeaf
6851	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6852	pCurLeaf++;
6853	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6854	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6855	pCurLeaf = NULL;
6856	}
6857	}
6858	}
6859
6860
6861	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6862	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6863	{
6864	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6865	&& pCurLeaf->uLeaf <= uUpToLeaf)
6866	{
6867	pHlp->pfnPrintf(pHlp,
6868	" %s\n"
6869	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6870	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6871	&& pCurLeaf->uLeaf <= uUpToLeaf)
6872	{
6873	CPUMCPUID Host;
6874	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6875	pHlp->pfnPrintf(pHlp,
6876	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6877	"Hst: %08x %08x %08x %08x\n",
6878	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6879	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6880	pCurLeaf++;
6881	}
6882	}
6883
6884	return pCurLeaf;
6885	}
6886
6887
6888	/**
6889	* Display the guest CpuId leaves.
6890	*
6891	* @param pVM The cross context VM structure.
6892	* @param pHlp The info helper functions.
6893	* @param pszArgs "terse", "default" or "verbose".
6894	*/
6895	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6896	{
6897	/*
6898	* Parse the argument.
6899	*/
6900	unsigned iVerbosity = 1;
6901	if (pszArgs)
6902	{
6903	pszArgs = RTStrStripL(pszArgs);
6904	if (!strcmp(pszArgs, "terse"))
6905	iVerbosity--;
6906	else if (!strcmp(pszArgs, "verbose"))
6907	iVerbosity++;
6908	}
6909
6910	uint32_t uLeaf;
6911	CPUMCPUID Host;
6912	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6913	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6914	PCCPUMCPUIDLEAF pCurLeaf;
6915	PCCPUMCPUIDLEAF pNextLeaf;
6916	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6917	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6918	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6919
6920	/*
6921	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6922	*/
6923	uint32_t cHstMax = ASMCpuId_EAX(0);
6924	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6925	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6926	pHlp->pfnPrintf(pHlp,
6927	" Raw Standard CPUID Leaves\n"
6928	" Leaf/sub-leaf eax ebx ecx edx\n");
6929	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6930	{
6931	uint32_t cMaxSubLeaves = 1;
6932	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6933	cMaxSubLeaves = 16;
6934	else if (uLeaf == 0xd)
6935	cMaxSubLeaves = 128;
6936
6937	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6938	{
6939	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6940	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6941	&& pCurLeaf->uLeaf == uLeaf
6942	&& pCurLeaf->uSubLeaf == uSubLeaf)
6943	{
6944	pHlp->pfnPrintf(pHlp,
6945	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6946	"Hst: %08x %08x %08x %08x\n",
6947	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6948	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6949	pCurLeaf++;
6950	}
6951	else if ( uLeaf != 0xd
6952	\|\| uSubLeaf <= 1
6953	\|\| Host.uEbx != 0 )
6954	pHlp->pfnPrintf(pHlp,
6955	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6956	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6957
6958	/* Done? */
6959	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6960	\|\| pCurLeaf->uLeaf != uLeaf)
6961	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6962	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6963	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6964	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6965	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6966	)
6967	)
6968	break;
6969	}
6970	}
6971	pNextLeaf = pCurLeaf;
6972
6973	/*
6974	* If verbose, decode it.
6975	*/
6976	if (iVerbosity && paLeaves[0].uLeaf == 0)
6977	pHlp->pfnPrintf(pHlp,
6978	"%36s %.04s%.04s%.04s\n"
6979	"%36s 0x00000000-%#010x\n"
6980	,
6981	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6982	"Supports:", paLeaves[0].uEax);
6983
6984	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6985	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6986
6987	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6988	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6989
6990	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6991	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6992
6993	pCurLeaf = pNextLeaf;
6994
6995	/*
6996	* Hypervisor leaves.
6997	*
6998	* Unlike most of the other leaves reported, the guest hypervisor leaves
6999	* aren't a subset of the host CPUID bits.
7000	*/
7001	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
7002
7003	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7004	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
7005	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
7006	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
7007	cMax = RT_MAX(cHstMax, cGstMax);
7008	if (cMax >= UINT32_C(0x40000000))
7009	{
7010	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
7011
7012	/** @todo dump these in more detail. */
7013
7014	pCurLeaf = pNextLeaf;
7015	}
7016
7017
7018	/*
7019	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
7020	* Implemented after AMD specs.
7021	*/
7022	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
7023
7024	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7025	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
7026	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
7027	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
7028	cMax = RT_MAX(cHstMax, cGstMax);
7029	if (cMax >= UINT32_C(0x80000000))
7030	{
7031
7032	pHlp->pfnPrintf(pHlp,
7033	" Raw Extended CPUID Leaves\n"
7034	" Leaf/sub-leaf eax ebx ecx edx\n");
7035	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
7036	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
7037	{
7038	uint32_t cMaxSubLeaves = 1;
7039	if (uLeaf == UINT32_C(0x8000001d))
7040	cMaxSubLeaves = 16;
7041
7042	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
7043	{
7044	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7045	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
7046	&& pCurLeaf->uLeaf == uLeaf
7047	&& pCurLeaf->uSubLeaf == uSubLeaf)
7048	{
7049	pHlp->pfnPrintf(pHlp,
7050	"Gst: %08x/%04x %08x %08x %08x %08x\n"
7051	"Hst: %08x %08x %08x %08x\n",
7052	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
7053	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
7054	pCurLeaf++;
7055	}
7056	else if ( uLeaf != 0xd
7057	\|\| uSubLeaf <= 1
7058	\|\| Host.uEbx != 0 )
7059	pHlp->pfnPrintf(pHlp,
7060	"Hst: %08x/%04x %08x %08x %08x %08x\n",
7061	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
7062
7063	/* Done? */
7064	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
7065	\|\| pCurLeaf->uLeaf != uLeaf)
7066	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
7067	break;
7068	}
7069	}
7070	pNextLeaf = pCurLeaf;
7071
7072	/*
7073	* Understandable output
7074	*/
7075	if (iVerbosity)
7076	pHlp->pfnPrintf(pHlp,
7077	"Ext Name: %.4s%.4s%.4s\n"
7078	"Ext Supports: 0x80000000-%#010x\n",
7079	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
7080
7081	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
7082	if (iVerbosity && pCurLeaf)
7083	{
7084	uint32_t uEAX = pCurLeaf->uEax;
7085	pHlp->pfnPrintf(pHlp,
7086	"Family: %d \tExtended: %d \tEffective: %d\n"
7087	"Model: %d \tExtended: %d \tEffective: %d\n"
7088	"Stepping: %d\n"
7089	"Brand ID: %#05x\n",
7090	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
7091	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
7092	ASMGetCpuStepping(uEAX),
7093	pCurLeaf->uEbx & 0xfff);
7094
7095	if (iVerbosity == 1)
7096	{
7097	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
7098	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
7099	}
7100	else
7101	{
7102	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7103	pHlp->pfnPrintf(pHlp, "Ext Features\n");
7104	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
7105	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
7106	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
7107	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
7108	{
7109	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
7110	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7111	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
7112	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
7113	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
7114	}
7115	}
7116	}
7117
7118	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
7119	{
7120	char szString[443+1] = {0};
7121	uint32_t pu32 = (uint32_t )szString;
7122	*pu32++ = pCurLeaf->uEax;
7123	*pu32++ = pCurLeaf->uEbx;
7124	*pu32++ = pCurLeaf->uEcx;
7125	*pu32++ = pCurLeaf->uEdx;
7126	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
7127	if (pCurLeaf)
7128	{
7129	*pu32++ = pCurLeaf->uEax;
7130	*pu32++ = pCurLeaf->uEbx;
7131	*pu32++ = pCurLeaf->uEcx;
7132	*pu32++ = pCurLeaf->uEdx;
7133	}
7134	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
7135	if (pCurLeaf)
7136	{
7137	*pu32++ = pCurLeaf->uEax;
7138	*pu32++ = pCurLeaf->uEbx;
7139	*pu32++ = pCurLeaf->uEcx;
7140	*pu32++ = pCurLeaf->uEdx;
7141	}
7142	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
7143	}
7144
7145	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
7146	{
7147	uint32_t uEAX = pCurLeaf->uEax;
7148	uint32_t uEBX = pCurLeaf->uEbx;
7149	uint32_t uECX = pCurLeaf->uEcx;
7150	uint32_t uEDX = pCurLeaf->uEdx;
7151	char sz1[32];
7152	char sz2[32];
7153
7154	pHlp->pfnPrintf(pHlp,
7155	"TLB 2/4M Instr/Uni: %s %3d entries\n"
7156	"TLB 2/4M Data: %s %3d entries\n",
7157	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
7158	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
7159	pHlp->pfnPrintf(pHlp,
7160	"TLB 4K Instr/Uni: %s %3d entries\n"
7161	"TLB 4K Data: %s %3d entries\n",
7162	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
7163	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
7164	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
7165	"L1 Instr Cache Lines Per Tag: %d\n"
7166	"L1 Instr Cache Associativity: %s\n"
7167	"L1 Instr Cache Size: %d KB\n",
7168	(uEDX >> 0) & 0xff,
7169	(uEDX >> 8) & 0xff,
7170	getCacheAss((uEDX >> 16) & 0xff, sz1),
7171	(uEDX >> 24) & 0xff);
7172	pHlp->pfnPrintf(pHlp,
7173	"L1 Data Cache Line Size: %d bytes\n"
7174	"L1 Data Cache Lines Per Tag: %d\n"
7175	"L1 Data Cache Associativity: %s\n"
7176	"L1 Data Cache Size: %d KB\n",
7177	(uECX >> 0) & 0xff,
7178	(uECX >> 8) & 0xff,
7179	getCacheAss((uECX >> 16) & 0xff, sz1),
7180	(uECX >> 24) & 0xff);
7181	}
7182
7183	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
7184	{
7185	uint32_t uEAX = pCurLeaf->uEax;
7186	uint32_t uEBX = pCurLeaf->uEbx;
7187	uint32_t uEDX = pCurLeaf->uEdx;
7188
7189	pHlp->pfnPrintf(pHlp,
7190	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
7191	"L2 TLB 2/4M Data: %s %4d entries\n",
7192	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
7193	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
7194	pHlp->pfnPrintf(pHlp,
7195	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
7196	"L2 TLB 4K Data: %s %4d entries\n",
7197	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
7198	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
7199	pHlp->pfnPrintf(pHlp,
7200	"L2 Cache Line Size: %d bytes\n"
7201	"L2 Cache Lines Per Tag: %d\n"
7202	"L2 Cache Associativity: %s\n"
7203	"L2 Cache Size: %d KB\n",
7204	(uEDX >> 0) & 0xff,
7205	(uEDX >> 8) & 0xf,
7206	getL2CacheAss((uEDX >> 12) & 0xf),
7207	(uEDX >> 16) & 0xffff);
7208	}
7209
7210	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
7211	{
7212	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7213	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
7214	{
7215	if (iVerbosity < 1)
7216	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7217	else
7218	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7219	}
7220	}
7221
7222	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7223	if (pCurLeaf != NULL)
7224	{
7225	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7226	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7227	{
7228	if (iVerbosity < 1)
7229	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7230	else
7231	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7232	}
7233
7234	if (iVerbosity)
7235	{
7236	uint32_t uEAX = pCurLeaf->uEax;
7237	uint32_t uECX = pCurLeaf->uEcx;
7238
7239	pHlp->pfnPrintf(pHlp,
7240	"Physical Address Width: %d bits\n"
7241	"Virtual Address Width: %d bits\n"
7242	"Guest Physical Address Width: %d bits\n",
7243	(uEAX >> 0) & 0xff,
7244	(uEAX >> 8) & 0xff,
7245	(uEAX >> 16) & 0xff);
7246	pHlp->pfnPrintf(pHlp,
7247	"Physical Core Count: %d\n",
7248	((uECX >> 0) & 0xff) + 1);
7249	}
7250	}
7251
7252	pCurLeaf = pNextLeaf;
7253	}
7254
7255
7256
7257	/*
7258	* Centaur.
7259	*/
7260	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7261
7262	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7263	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7264	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7265	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7266	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7267	cMax = RT_MAX(cHstMax, cGstMax);
7268	if (cMax >= UINT32_C(0xc0000000))
7269	{
7270	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7271
7272	/*
7273	* Understandable output
7274	*/
7275	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7276	pHlp->pfnPrintf(pHlp,
7277	"Centaur Supports: 0xc0000000-%#010x\n",
7278	pCurLeaf->uEax);
7279
7280	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7281	{
7282	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7283	uint32_t uEdxGst = pCurLeaf->uEdx;
7284	uint32_t uEdxHst = Host.uEdx;
7285
7286	if (iVerbosity == 1)
7287	{
7288	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7289	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7290	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7291	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7292	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7293	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7294	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7295	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7296	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7297	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7298	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7299	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7300	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7301	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7302	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7303	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7304	for (unsigned iBit = 14; iBit < 32; iBit++)
7305	if (uEdxGst & RT_BIT(iBit))
7306	pHlp->pfnPrintf(pHlp, " %d", iBit);
7307	pHlp->pfnPrintf(pHlp, "\n");
7308	}
7309	else
7310	{
7311	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7312	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7313	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7314	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7315	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7316	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7317	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7318	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7319	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7320	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7321	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7322	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7323	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7324	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7325	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7326	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7327	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7328	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7329	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7330	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7331	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7332	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7333	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7334	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7335	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7336	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7337	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7338	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7339	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7340	for (unsigned iBit = 27; iBit < 32; iBit++)
7341	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7342	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7343	pHlp->pfnPrintf(pHlp, "\n");
7344	}
7345	}
7346
7347	pCurLeaf = pNextLeaf;
7348	}
7349
7350	/*
7351	* The remainder.
7352	*/
7353	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7354	}
7355
7356
7357
7358
7359
7360	/*
7361	*
7362	*
7363	* PATM interfaces.
7364	* PATM interfaces.
7365	* PATM interfaces.
7366	*
7367	*
7368	*/
7369
7370
7371	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
7372	/** @name Patchmanager CPUID legacy table APIs
7373	* @{
7374	*/
7375
7376	/**
7377	* Gets a pointer to the default CPUID leaf.
7378	*
7379	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
7380	* @param pVM The cross context VM structure.
7381	* @remark Intended for PATM only.
7382	*/
7383	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
7384	{
7385	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
7386	}
7387
7388
7389	/**
7390	* Gets a number of standard CPUID leaves (PATM only).
7391	*
7392	* @returns Number of leaves.
7393	* @param pVM The cross context VM structure.
7394	* @remark Intended for PATM - legacy, don't use in new code.
7395	*/
7396	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
7397	{
7398	RT_NOREF_PV(pVM);
7399	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
7400	}
7401
7402
7403	/**
7404	* Gets a number of extended CPUID leaves (PATM only).
7405	*
7406	* @returns Number of leaves.
7407	* @param pVM The cross context VM structure.
7408	* @remark Intended for PATM - legacy, don't use in new code.
7409	*/
7410	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
7411	{
7412	RT_NOREF_PV(pVM);
7413	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
7414	}
7415
7416
7417	/**
7418	* Gets a number of centaur CPUID leaves.
7419	*
7420	* @returns Number of leaves.
7421	* @param pVM The cross context VM structure.
7422	* @remark Intended for PATM - legacy, don't use in new code.
7423	*/
7424	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
7425	{
7426	RT_NOREF_PV(pVM);
7427	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
7428	}
7429
7430
7431	/**
7432	* Gets a pointer to the array of standard CPUID leaves.
7433	*
7434	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
7435	*
7436	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
7437	* @param pVM The cross context VM structure.
7438	* @remark Intended for PATM - legacy, don't use in new code.
7439	*/
7440	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
7441	{
7442	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
7443	}
7444
7445
7446	/**
7447	* Gets a pointer to the array of extended CPUID leaves.
7448	*
7449	* CPUMGetGuestCpuIdExtMax() give the size of the array.
7450	*
7451	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
7452	* @param pVM The cross context VM structure.
7453	* @remark Intended for PATM - legacy, don't use in new code.
7454	*/
7455	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
7456	{
7457	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
7458	}
7459
7460
7461	/**
7462	* Gets a pointer to the array of centaur CPUID leaves.
7463	*
7464	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
7465	*
7466	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
7467	* @param pVM The cross context VM structure.
7468	* @remark Intended for PATM - legacy, don't use in new code.
7469	*/
7470	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
7471	{
7472	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
7473	}
7474
7475	/** @} */
7476	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
7477
7478	#endif /* VBOX_IN_VMM */
7479

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 78425

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