CPUMR3CpuId.cpp@ 79345

Last change on this file since 79345 was 78632, checked in by vboxsync, 6 years ago
Forward ported 130474,130475,130477,130479. bugref:9453
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 351.3 KB

Line
1	/* $Id: CPUMR3CpuId.cpp 78632 2019-05-21 13:56:11Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/mm.h>
31	#include <VBox/sup.h>
32
33	#include <VBox/err.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/ctype.h>
36	#include <iprt/mem.h>
37	#include <iprt/string.h>
38
39
40	/*********************************************************************************************************************************
41	* Defined Constants And Macros *
42	*********************************************************************************************************************************/
43	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
44	#define CPUM_CPUID_MAX_LEAVES 2048
45	/* Max size we accept for the XSAVE area. */
46	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
47	/* Min size we accept for the XSAVE area. */
48	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
49
50
51	/*********************************************************************************************************************************
52	* Global Variables *
53	*********************************************************************************************************************************/
54	/**
55	* The intel pentium family.
56	*/
57	static const CPUMMICROARCH g_aenmIntelFamily06[] =
58	{
59	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
60	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
61	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
63	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
64	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
65	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
66	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
67	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
68	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
69	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
70	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
71	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
72	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
73	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
74	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
75	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
81	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
82	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
83	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [26(0x1a)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Nehalem-EP */
86	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
88	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
89	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
90	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
91	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
97	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
98	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
99	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
102	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
104	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
105	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
106	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
107	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
113	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
114	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
115	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
118	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
121	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
122	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
130	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
131	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
136	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,
138	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Broadwell-E */
139	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu; skylake <= 4, cascade lake > 5 */
145	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
146	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
147	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
150	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
152	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
153	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
154	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
155	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
159	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
160	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
161	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
162	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
163	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
164	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
165	/[106(0x6a)] = / kCpumMicroarch_Intel_Unknown,
166	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
167	/[108(0x6c)] = / kCpumMicroarch_Intel_Unknown,
168	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
169	/[110(0x6e)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
170	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
171	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
172	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
173	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
174	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
175	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
176	/[117(0x75)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
177	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
178	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
179	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
180	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
181	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
182	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
183	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
184	/[125(0x7d)] = / kCpumMicroarch_Intel_Unknown,
185	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
186	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
187	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
188	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
189	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
190	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
191	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
192	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
193	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
194	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
195	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
196	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
197	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
198	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
199	/[140(0x8c)] = / kCpumMicroarch_Intel_Unknown,
200	/[141(0x8d)] = / kCpumMicroarch_Intel_Unknown,
201	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
202	/[143(0x8f)] = / kCpumMicroarch_Intel_Unknown,
203	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
204	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
205	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
206	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
207	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
208	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
209	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
210	/[151(0x97)] = / kCpumMicroarch_Intel_Unknown,
211	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
212	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
213	/[154(0x9a)] = / kCpumMicroarch_Intel_Unknown,
214	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
215	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
216	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
217	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
218	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
219	};
220	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0x9f+1);
221
222
223	/**
224	* Figures out the (sub-)micro architecture given a bit of CPUID info.
225	*
226	* @returns Micro architecture.
227	* @param enmVendor The CPU vendor .
228	* @param bFamily The CPU family.
229	* @param bModel The CPU model.
230	* @param bStepping The CPU stepping.
231	*/
232	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
233	uint8_t bModel, uint8_t bStepping)
234	{
235	if (enmVendor == CPUMCPUVENDOR_AMD)
236	{
237	switch (bFamily)
238	{
239	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
240	case 0x03: return kCpumMicroarch_AMD_Am386;
241	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
242	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
243	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
244	case 0x06:
245	switch (bModel)
246	{
247	case 0: return kCpumMicroarch_AMD_K7_Palomino;
248	case 1: return kCpumMicroarch_AMD_K7_Palomino;
249	case 2: return kCpumMicroarch_AMD_K7_Palomino;
250	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
251	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
252	case 6: return kCpumMicroarch_AMD_K7_Palomino;
253	case 7: return kCpumMicroarch_AMD_K7_Morgan;
254	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
255	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
256	}
257	return kCpumMicroarch_AMD_K7_Unknown;
258	case 0x0f:
259	/*
260	* This family is a friggin mess. Trying my best to make some
261	* sense out of it. Too much happened in the 0x0f family to
262	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
263	*
264	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
265	* cpu-world.com, and other places:
266	* - 130nm:
267	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
268	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
269	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
270	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
271	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
272	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
273	* - 90nm:
274	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
275	* - Oakville: 10FC0/DH-D0.
276	* - Georgetown: 10FC0/DH-D0.
277	* - Sonora: 10FC0/DH-D0.
278	* - Venus: 20F71/SH-E4
279	* - Troy: 20F51/SH-E4
280	* - Athens: 20F51/SH-E4
281	* - San Diego: 20F71/SH-E4.
282	* - Lancaster: 20F42/SH-E5
283	* - Newark: 20F42/SH-E5.
284	* - Albany: 20FC2/DH-E6.
285	* - Roma: 20FC2/DH-E6.
286	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
287	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
288	* - 90nm introducing Dual core:
289	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
290	* - Italy: 20F10/JH-E1, 20F12/JH-E6
291	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
292	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
293	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
294	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
295	* - Santa Ana: 40F32/JH-F2, /-F3
296	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
297	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
298	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
299	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
300	* - Keene: 40FC2/DH-F2.
301	* - Richmond: 40FC2/DH-F2
302	* - Taylor: 40F82/BH-F2
303	* - Trinidad: 40F82/BH-F2
304	*
305	* - 65nm:
306	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
307	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
308	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
309	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
310	* - Sherman: /-G1, 70FC2/DH-G2.
311	* - Huron: 70FF2/DH-G2.
312	*/
313	if (bModel < 0x10)
314	return kCpumMicroarch_AMD_K8_130nm;
315	if (bModel >= 0x60 && bModel < 0x80)
316	return kCpumMicroarch_AMD_K8_65nm;
317	if (bModel >= 0x40)
318	return kCpumMicroarch_AMD_K8_90nm_AMDV;
319	switch (bModel)
320	{
321	case 0x21:
322	case 0x23:
323	case 0x2b:
324	case 0x2f:
325	case 0x37:
326	case 0x3f:
327	return kCpumMicroarch_AMD_K8_90nm_DualCore;
328	}
329	return kCpumMicroarch_AMD_K8_90nm;
330	case 0x10:
331	return kCpumMicroarch_AMD_K10;
332	case 0x11:
333	return kCpumMicroarch_AMD_K10_Lion;
334	case 0x12:
335	return kCpumMicroarch_AMD_K10_Llano;
336	case 0x14:
337	return kCpumMicroarch_AMD_Bobcat;
338	case 0x15:
339	switch (bModel)
340	{
341	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
342	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
343	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
344	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
345	case 0x11: /* ?? */
346	case 0x12: /* ?? */
347	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
348	}
349	return kCpumMicroarch_AMD_15h_Unknown;
350	case 0x16:
351	return kCpumMicroarch_AMD_Jaguar;
352	case 0x17:
353	return kCpumMicroarch_AMD_Zen_Ryzen;
354	}
355	return kCpumMicroarch_AMD_Unknown;
356	}
357
358	if (enmVendor == CPUMCPUVENDOR_INTEL)
359	{
360	switch (bFamily)
361	{
362	case 3:
363	return kCpumMicroarch_Intel_80386;
364	case 4:
365	return kCpumMicroarch_Intel_80486;
366	case 5:
367	return kCpumMicroarch_Intel_P5;
368	case 6:
369	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
370	{
371	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
372	if (enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake)
373	{
374	if (bStepping >= 0xa && bStepping <= 0xc)
375	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
376	else if (bStepping >= 0xc)
377	enmMicroArch = kCpumMicroarch_Intel_Core7_WhiskeyLake;
378	}
379	else if ( enmMicroArch == kCpumMicroarch_Intel_Core7_Skylake
380	&& bModel == 0x55
381	&& bStepping >= 5)
382	enmMicroArch = kCpumMicroarch_Intel_Core7_CascadeLake;
383	return enmMicroArch;
384	}
385	return kCpumMicroarch_Intel_Atom_Unknown;
386	case 15:
387	switch (bModel)
388	{
389	case 0: return kCpumMicroarch_Intel_NB_Willamette;
390	case 1: return kCpumMicroarch_Intel_NB_Willamette;
391	case 2: return kCpumMicroarch_Intel_NB_Northwood;
392	case 3: return kCpumMicroarch_Intel_NB_Prescott;
393	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
394	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
395	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
396	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
397	default: return kCpumMicroarch_Intel_NB_Unknown;
398	}
399	break;
400	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
401	case 0:
402	return kCpumMicroarch_Intel_8086;
403	case 1:
404	return kCpumMicroarch_Intel_80186;
405	case 2:
406	return kCpumMicroarch_Intel_80286;
407	}
408	return kCpumMicroarch_Intel_Unknown;
409	}
410
411	if (enmVendor == CPUMCPUVENDOR_VIA)
412	{
413	switch (bFamily)
414	{
415	case 5:
416	switch (bModel)
417	{
418	case 1: return kCpumMicroarch_Centaur_C6;
419	case 4: return kCpumMicroarch_Centaur_C6;
420	case 8: return kCpumMicroarch_Centaur_C2;
421	case 9: return kCpumMicroarch_Centaur_C3;
422	}
423	break;
424
425	case 6:
426	switch (bModel)
427	{
428	case 5: return kCpumMicroarch_VIA_C3_M2;
429	case 6: return kCpumMicroarch_VIA_C3_C5A;
430	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
431	case 8: return kCpumMicroarch_VIA_C3_C5N;
432	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
433	case 10: return kCpumMicroarch_VIA_C7_C5J;
434	case 15: return kCpumMicroarch_VIA_Isaiah;
435	}
436	break;
437	}
438	return kCpumMicroarch_VIA_Unknown;
439	}
440
441	if (enmVendor == CPUMCPUVENDOR_SHANGHAI)
442	{
443	switch (bFamily)
444	{
445	case 6:
446	case 7:
447	return kCpumMicroarch_Shanghai_Wudaokou;
448	default:
449	break;
450	}
451	return kCpumMicroarch_Shanghai_Unknown;
452	}
453
454	if (enmVendor == CPUMCPUVENDOR_CYRIX)
455	{
456	switch (bFamily)
457	{
458	case 4:
459	switch (bModel)
460	{
461	case 9: return kCpumMicroarch_Cyrix_5x86;
462	}
463	break;
464
465	case 5:
466	switch (bModel)
467	{
468	case 2: return kCpumMicroarch_Cyrix_M1;
469	case 4: return kCpumMicroarch_Cyrix_MediaGX;
470	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
471	}
472	break;
473
474	case 6:
475	switch (bModel)
476	{
477	case 0: return kCpumMicroarch_Cyrix_M2;
478	}
479	break;
480
481	}
482	return kCpumMicroarch_Cyrix_Unknown;
483	}
484
485	return kCpumMicroarch_Unknown;
486	}
487
488
489	/**
490	* Translates a microarchitecture enum value to the corresponding string
491	* constant.
492	*
493	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
494	* NULL if the value is invalid.
495	*
496	* @param enmMicroarch The enum value to convert.
497	*/
498	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
499	{
500	switch (enmMicroarch)
501	{
502	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
503	CASE_RET_STR(kCpumMicroarch_Intel_8086);
504	CASE_RET_STR(kCpumMicroarch_Intel_80186);
505	CASE_RET_STR(kCpumMicroarch_Intel_80286);
506	CASE_RET_STR(kCpumMicroarch_Intel_80386);
507	CASE_RET_STR(kCpumMicroarch_Intel_80486);
508	CASE_RET_STR(kCpumMicroarch_Intel_P5);
509
510	CASE_RET_STR(kCpumMicroarch_Intel_P6);
511	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
512	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
513
514	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
515	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
516	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
517
518	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
519	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
520
521	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
522	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
523	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
524	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
525	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
526	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
527	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
528	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
529	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
530	CASE_RET_STR(kCpumMicroarch_Intel_Core7_WhiskeyLake);
531	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CascadeLake);
532	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
533	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
534	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
535
536	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
537	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
538	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
539	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
540	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
541	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
542	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
543	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
544
545	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
546	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
547	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
548	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
549	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
550
551	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
552	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
553	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
554	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
555	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
556	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
557	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
558
559	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
560
561	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
562	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
563	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
564	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
565	CASE_RET_STR(kCpumMicroarch_AMD_K5);
566	CASE_RET_STR(kCpumMicroarch_AMD_K6);
567
568	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
569	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
570	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
571	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
572	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
573	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
574	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
575
576	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
577	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
578	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
579	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
580	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
581
582	CASE_RET_STR(kCpumMicroarch_AMD_K10);
583	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
584	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
585	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
586	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
587
588	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
589	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
590	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
591	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
592	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
593
594	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
595
596	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
597
598	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
599
600	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
601	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
602	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
603	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
604	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
605	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
606	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
607	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
608	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
609	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
610	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
611	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
612	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
613
614	CASE_RET_STR(kCpumMicroarch_Shanghai_Wudaokou);
615	CASE_RET_STR(kCpumMicroarch_Shanghai_Unknown);
616
617	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
618	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
619	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
620	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
621	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
622	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
623
624	CASE_RET_STR(kCpumMicroarch_NEC_V20);
625	CASE_RET_STR(kCpumMicroarch_NEC_V30);
626
627	CASE_RET_STR(kCpumMicroarch_Unknown);
628
629	#undef CASE_RET_STR
630	case kCpumMicroarch_Invalid:
631	case kCpumMicroarch_Intel_End:
632	case kCpumMicroarch_Intel_Core2_End:
633	case kCpumMicroarch_Intel_Core7_End:
634	case kCpumMicroarch_Intel_Atom_End:
635	case kCpumMicroarch_Intel_P6_Core_Atom_End:
636	case kCpumMicroarch_Intel_Phi_End:
637	case kCpumMicroarch_Intel_NB_End:
638	case kCpumMicroarch_AMD_K7_End:
639	case kCpumMicroarch_AMD_K8_End:
640	case kCpumMicroarch_AMD_15h_End:
641	case kCpumMicroarch_AMD_16h_End:
642	case kCpumMicroarch_AMD_Zen_End:
643	case kCpumMicroarch_AMD_End:
644	case kCpumMicroarch_VIA_End:
645	case kCpumMicroarch_Cyrix_End:
646	case kCpumMicroarch_NEC_End:
647	case kCpumMicroarch_Shanghai_End:
648	case kCpumMicroarch_32BitHack:
649	break;
650	/* no default! */
651	}
652
653	return NULL;
654	}
655
656
657	/**
658	* Determins the host CPU MXCSR mask.
659	*
660	* @returns MXCSR mask.
661	*/
662	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
663	{
664	if ( ASMHasCpuId()
665	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
666	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
667	{
668	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
669	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
670	RT_ZERO(*pState);
671	ASMFxSave(pState);
672	if (pState->MXCSR_MASK == 0)
673	return 0xffbf;
674	return pState->MXCSR_MASK;
675	}
676	return 0;
677	}
678
679
680	/**
681	* Gets a matching leaf in the CPUID leaf array.
682	*
683	* @returns Pointer to the matching leaf, or NULL if not found.
684	* @param paLeaves The CPUID leaves to search. This is sorted.
685	* @param cLeaves The number of leaves in the array.
686	* @param uLeaf The leaf to locate.
687	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
688	*/
689	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
690	{
691	/* Lazy bird does linear lookup here since this is only used for the
692	occational CPUID overrides. */
693	for (uint32_t i = 0; i < cLeaves; i++)
694	if ( paLeaves[i].uLeaf == uLeaf
695	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
696	return &paLeaves[i];
697	return NULL;
698	}
699
700
701	#ifndef IN_VBOX_CPU_REPORT
702	/**
703	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
704	*
705	* @returns true if found, false it not.
706	* @param paLeaves The CPUID leaves to search. This is sorted.
707	* @param cLeaves The number of leaves in the array.
708	* @param uLeaf The leaf to locate.
709	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
710	* @param pLegacy The legacy output leaf.
711	*/
712	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
713	PCPUMCPUID pLegacy)
714	{
715	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
716	if (pLeaf)
717	{
718	pLegacy->uEax = pLeaf->uEax;
719	pLegacy->uEbx = pLeaf->uEbx;
720	pLegacy->uEcx = pLeaf->uEcx;
721	pLegacy->uEdx = pLeaf->uEdx;
722	return true;
723	}
724	return false;
725	}
726	#endif /* IN_VBOX_CPU_REPORT */
727
728
729	/**
730	* Ensures that the CPUID leaf array can hold one more leaf.
731	*
732	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
733	* failure.
734	* @param pVM The cross context VM structure. If NULL, use
735	* the process heap, otherwise the VM's hyper heap.
736	* @param ppaLeaves Pointer to the variable holding the array pointer
737	* (input/output).
738	* @param cLeaves The current array size.
739	*
740	* @remarks This function will automatically update the R0 and RC pointers when
741	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
742	* be the corresponding VM's CPUID arrays (which is asserted).
743	*/
744	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
745	{
746	/*
747	* If pVM is not specified, we're on the regular heap and can waste a
748	* little space to speed things up.
749	*/
750	uint32_t cAllocated;
751	if (!pVM)
752	{
753	cAllocated = RT_ALIGN(cLeaves, 16);
754	if (cLeaves + 1 > cAllocated)
755	{
756	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
757	if (pvNew)
758	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
759	else
760	{
761	RTMemFree(*ppaLeaves);
762	*ppaLeaves = NULL;
763	}
764	}
765	}
766	/*
767	* Otherwise, we're on the hyper heap and are probably just inserting
768	* one or two leaves and should conserve space.
769	*/
770	else
771	{
772	#ifdef IN_VBOX_CPU_REPORT
773	AssertReleaseFailed();
774	#else
775	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
776	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
777
778	size_t cb = cLeaves * sizeof(**ppaLeaves);
779	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
780	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
781	if (RT_SUCCESS(rc))
782	{
783	/* Update the R0 and RC pointers. */
784	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
785	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
786	}
787	else
788	{
789	*ppaLeaves = NULL;
790	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
791	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
792	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
793	}
794	#endif
795	}
796	return *ppaLeaves;
797	}
798
799
800	/**
801	* Append a CPUID leaf or sub-leaf.
802	*
803	* ASSUMES linear insertion order, so we'll won't need to do any searching or
804	* replace anything. Use cpumR3CpuIdInsert() for those cases.
805	*
806	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
807	* the caller need do no more work.
808	* @param ppaLeaves Pointer to the pointer to the array of sorted
809	* CPUID leaves and sub-leaves.
810	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
811	* @param uLeaf The leaf we're adding.
812	* @param uSubLeaf The sub-leaf number.
813	* @param fSubLeafMask The sub-leaf mask.
814	* @param uEax The EAX value.
815	* @param uEbx The EBX value.
816	* @param uEcx The ECX value.
817	* @param uEdx The EDX value.
818	* @param fFlags The flags.
819	*/
820	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
821	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
822	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
823	{
824	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
825	return VERR_NO_MEMORY;
826
827	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
828	Assert( *pcLeaves == 0
829	\|\| pNew[-1].uLeaf < uLeaf
830	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
831
832	pNew->uLeaf = uLeaf;
833	pNew->uSubLeaf = uSubLeaf;
834	pNew->fSubLeafMask = fSubLeafMask;
835	pNew->uEax = uEax;
836	pNew->uEbx = uEbx;
837	pNew->uEcx = uEcx;
838	pNew->uEdx = uEdx;
839	pNew->fFlags = fFlags;
840
841	*pcLeaves += 1;
842	return VINF_SUCCESS;
843	}
844
845
846	/**
847	* Checks that we've updated the CPUID leaves array correctly.
848	*
849	* This is a no-op in non-strict builds.
850	*
851	* @param paLeaves The leaves array.
852	* @param cLeaves The number of leaves.
853	*/
854	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
855	{
856	#ifdef VBOX_STRICT
857	for (uint32_t i = 1; i < cLeaves; i++)
858	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
859	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
860	else
861	{
862	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
863	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
864	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
865	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
866	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
867	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
868	}
869	#else
870	NOREF(paLeaves);
871	NOREF(cLeaves);
872	#endif
873	}
874
875
876	/**
877	* Inserts a CPU ID leaf, replacing any existing ones.
878	*
879	* When inserting a simple leaf where we already got a series of sub-leaves with
880	* the same leaf number (eax), the simple leaf will replace the whole series.
881	*
882	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
883	* host-context heap and has only been allocated/reallocated by the
884	* cpumR3CpuIdEnsureSpace function.
885	*
886	* @returns VBox status code.
887	* @param pVM The cross context VM structure. If NULL, use
888	* the process heap, otherwise the VM's hyper heap.
889	* @param ppaLeaves Pointer to the pointer to the array of sorted
890	* CPUID leaves and sub-leaves. Must be NULL if using
891	* the hyper heap.
892	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
893	* be NULL if using the hyper heap.
894	* @param pNewLeaf Pointer to the data of the new leaf we're about to
895	* insert.
896	*/
897	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
898	{
899	/*
900	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
901	*/
902	if (pVM)
903	{
904	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
905	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
906
907	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
908	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
909	}
910
911	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
912	uint32_t cLeaves = *pcLeaves;
913
914	/*
915	* Validate the new leaf a little.
916	*/
917	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
918	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
919	VERR_INVALID_FLAGS);
920	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
921	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
922	VERR_INVALID_PARAMETER);
923	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
924	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
925	VERR_INVALID_PARAMETER);
926	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
927	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
928	VERR_INVALID_PARAMETER);
929
930	/*
931	* Find insertion point. The lazy bird uses the same excuse as in
932	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
933	*/
934	uint32_t i;
935	if ( cLeaves > 0
936	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
937	{
938	/* Add at end. */
939	i = cLeaves;
940	}
941	else if ( cLeaves > 0
942	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
943	{
944	/* Either replacing the last leaf or dealing with sub-leaves. Spool
945	back to the first sub-leaf to pretend we did the linear search. */
946	i = cLeaves - 1;
947	while ( i > 0
948	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
949	i--;
950	}
951	else
952	{
953	/* Linear search from the start. */
954	i = 0;
955	while ( i < cLeaves
956	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
957	i++;
958	}
959	if ( i < cLeaves
960	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
961	{
962	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
963	{
964	/*
965	* The sub-leaf mask differs, replace all existing leaves with the
966	* same leaf number.
967	*/
968	uint32_t c = 1;
969	while ( i + c < cLeaves
970	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
971	c++;
972	if (c > 1 && i + c < cLeaves)
973	{
974	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
975	*pcLeaves = cLeaves -= c - 1;
976	}
977
978	paLeaves[i] = *pNewLeaf;
979	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
980	return VINF_SUCCESS;
981	}
982
983	/* Find sub-leaf insertion point. */
984	while ( i < cLeaves
985	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
986	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
987	i++;
988
989	/*
990	* If we've got an exactly matching leaf, replace it.
991	*/
992	if ( i < cLeaves
993	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
994	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
995	{
996	paLeaves[i] = *pNewLeaf;
997	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
998	return VINF_SUCCESS;
999	}
1000	}
1001
1002	/*
1003	* Adding a new leaf at 'i'.
1004	*/
1005	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
1006	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
1007	if (!paLeaves)
1008	return VERR_NO_MEMORY;
1009
1010	if (i < cLeaves)
1011	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
1012	*pcLeaves += 1;
1013	paLeaves[i] = *pNewLeaf;
1014
1015	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1016	return VINF_SUCCESS;
1017	}
1018
1019
1020	#ifndef IN_VBOX_CPU_REPORT
1021	/**
1022	* Removes a range of CPUID leaves.
1023	*
1024	* This will not reallocate the array.
1025	*
1026	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1027	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1028	* @param uFirst The first leaf.
1029	* @param uLast The last leaf.
1030	*/
1031	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1032	{
1033	uint32_t cLeaves = *pcLeaves;
1034
1035	Assert(uFirst <= uLast);
1036
1037	/*
1038	* Find the first one.
1039	*/
1040	uint32_t iFirst = 0;
1041	while ( iFirst < cLeaves
1042	&& paLeaves[iFirst].uLeaf < uFirst)
1043	iFirst++;
1044
1045	/*
1046	* Find the end (last + 1).
1047	*/
1048	uint32_t iEnd = iFirst;
1049	while ( iEnd < cLeaves
1050	&& paLeaves[iEnd].uLeaf <= uLast)
1051	iEnd++;
1052
1053	/*
1054	* Adjust the array if anything needs removing.
1055	*/
1056	if (iFirst < iEnd)
1057	{
1058	if (iEnd < cLeaves)
1059	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1060	*pcLeaves = cLeaves -= (iEnd - iFirst);
1061	}
1062
1063	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1064	}
1065	#endif /* IN_VBOX_CPU_REPORT */
1066
1067
1068	/**
1069	* Checks if ECX make a difference when reading a given CPUID leaf.
1070	*
1071	* @returns @c true if it does, @c false if it doesn't.
1072	* @param uLeaf The leaf we're reading.
1073	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1074	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1075	* final sub-leaf (for leaf 0xb only).
1076	*/
1077	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1078	{
1079	*pfFinalEcxUnchanged = false;
1080
1081	uint32_t auCur[4];
1082	uint32_t auPrev[4];
1083	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1084
1085	/* Look for sub-leaves. */
1086	uint32_t uSubLeaf = 1;
1087	for (;;)
1088	{
1089	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1090	if (memcmp(auCur, auPrev, sizeof(auCur)))
1091	break;
1092
1093	/* Advance / give up. */
1094	uSubLeaf++;
1095	if (uSubLeaf >= 64)
1096	{
1097	*pcSubLeaves = 1;
1098	return false;
1099	}
1100	}
1101
1102	/* Count sub-leaves. */
1103	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1104	uint32_t cRepeats = 0;
1105	uSubLeaf = 0;
1106	for (;;)
1107	{
1108	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1109
1110	/* Figuring out when to stop isn't entirely straight forward as we need
1111	to cover undocumented behavior up to a point and implementation shortcuts. */
1112
1113	/* 1. Look for more than 4 repeating value sets. */
1114	if ( auCur[0] == auPrev[0]
1115	&& auCur[1] == auPrev[1]
1116	&& ( auCur[2] == auPrev[2]
1117	\|\| ( auCur[2] == uSubLeaf
1118	&& auPrev[2] == uSubLeaf - 1) )
1119	&& auCur[3] == auPrev[3])
1120	{
1121	if ( uLeaf != 0xd
1122	\|\| uSubLeaf >= 64
1123	\|\| ( auCur[0] == 0
1124	&& auCur[1] == 0
1125	&& auCur[2] == 0
1126	&& auCur[3] == 0
1127	&& auPrev[2] == 0) )
1128	cRepeats++;
1129	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1130	break;
1131	}
1132	else
1133	cRepeats = 0;
1134
1135	/* 2. Look for zero values. */
1136	if ( auCur[0] == 0
1137	&& auCur[1] == 0
1138	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1139	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1140	&& uSubLeaf >= cMinLeaves)
1141	{
1142	cRepeats = 0;
1143	break;
1144	}
1145
1146	/* 3. Leaf 0xb level type 0 check. */
1147	if ( uLeaf == 0xb
1148	&& (auCur[2] & 0xff00) == 0
1149	&& (auPrev[2] & 0xff00) == 0)
1150	{
1151	cRepeats = 0;
1152	break;
1153	}
1154
1155	/* 99. Give up. */
1156	if (uSubLeaf >= 128)
1157	{
1158	#ifndef IN_VBOX_CPU_REPORT
1159	/* Ok, limit it according to the documentation if possible just to
1160	avoid annoying users with these detection issues. */
1161	uint32_t cDocLimit = UINT32_MAX;
1162	if (uLeaf == 0x4)
1163	cDocLimit = 4;
1164	else if (uLeaf == 0x7)
1165	cDocLimit = 1;
1166	else if (uLeaf == 0xd)
1167	cDocLimit = 63;
1168	else if (uLeaf == 0xf)
1169	cDocLimit = 2;
1170	if (cDocLimit != UINT32_MAX)
1171	{
1172	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1173	*pcSubLeaves = cDocLimit + 3;
1174	return true;
1175	}
1176	#endif
1177	*pcSubLeaves = UINT32_MAX;
1178	return true;
1179	}
1180
1181	/* Advance. */
1182	uSubLeaf++;
1183	memcpy(auPrev, auCur, sizeof(auCur));
1184	}
1185
1186	/* Standard exit. */
1187	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1188	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1189	if (*pcSubLeaves == 0)
1190	*pcSubLeaves = 1;
1191	return true;
1192	}
1193
1194
1195	/**
1196	* Gets a CPU ID leaf.
1197	*
1198	* @returns VBox status code.
1199	* @param pVM The cross context VM structure.
1200	* @param pLeaf Where to store the found leaf.
1201	* @param uLeaf The leaf to locate.
1202	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1203	*/
1204	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1205	{
1206	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1207	uLeaf, uSubLeaf);
1208	if (pcLeaf)
1209	{
1210	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1211	return VINF_SUCCESS;
1212	}
1213
1214	return VERR_NOT_FOUND;
1215	}
1216
1217
1218	/**
1219	* Inserts a CPU ID leaf, replacing any existing ones.
1220	*
1221	* @returns VBox status code.
1222	* @param pVM The cross context VM structure.
1223	* @param pNewLeaf Pointer to the leaf being inserted.
1224	*/
1225	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1226	{
1227	/*
1228	* Validate parameters.
1229	*/
1230	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1231	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1232
1233	/*
1234	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1235	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1236	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1237	*/
1238	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1239	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1240	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1241	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1242	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1243	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1244	{
1245	return VERR_NOT_SUPPORTED;
1246	}
1247
1248	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1249	}
1250
1251	/**
1252	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1253	*
1254	* @returns VBox status code.
1255	* @param ppaLeaves Where to return the array pointer on success.
1256	* Use RTMemFree to release.
1257	* @param pcLeaves Where to return the size of the array on
1258	* success.
1259	*/
1260	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1261	{
1262	*ppaLeaves = NULL;
1263	*pcLeaves = 0;
1264
1265	/*
1266	* Try out various candidates. This must be sorted!
1267	*/
1268	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1269	{
1270	{ UINT32_C(0x00000000), false },
1271	{ UINT32_C(0x10000000), false },
1272	{ UINT32_C(0x20000000), false },
1273	{ UINT32_C(0x30000000), false },
1274	{ UINT32_C(0x40000000), false },
1275	{ UINT32_C(0x50000000), false },
1276	{ UINT32_C(0x60000000), false },
1277	{ UINT32_C(0x70000000), false },
1278	{ UINT32_C(0x80000000), false },
1279	{ UINT32_C(0x80860000), false },
1280	{ UINT32_C(0x8ffffffe), true },
1281	{ UINT32_C(0x8fffffff), true },
1282	{ UINT32_C(0x90000000), false },
1283	{ UINT32_C(0xa0000000), false },
1284	{ UINT32_C(0xb0000000), false },
1285	{ UINT32_C(0xc0000000), false },
1286	{ UINT32_C(0xd0000000), false },
1287	{ UINT32_C(0xe0000000), false },
1288	{ UINT32_C(0xf0000000), false },
1289	};
1290
1291	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1292	{
1293	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1294	uint32_t uEax, uEbx, uEcx, uEdx;
1295	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1296
1297	/*
1298	* Does EAX look like a typical leaf count value?
1299	*/
1300	if ( uEax > uLeaf
1301	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1302	{
1303	/* Yes, dump them. */
1304	uint32_t cLeaves = uEax - uLeaf + 1;
1305	while (cLeaves-- > 0)
1306	{
1307	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1308
1309	uint32_t fFlags = 0;
1310
1311	/* There are currently three known leaves containing an APIC ID
1312	that needs EMT specific attention */
1313	if (uLeaf == 1)
1314	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1315	else if (uLeaf == 0xb && uEcx != 0)
1316	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1317	else if ( uLeaf == UINT32_C(0x8000001e)
1318	&& ( uEax
1319	\|\| uEbx
1320	\|\| uEdx
1321	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1322	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1323
1324	/* The APIC bit is per-VCpu and needs flagging. */
1325	if (uLeaf == 1)
1326	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1327	else if ( uLeaf == UINT32_C(0x80000001)
1328	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1329	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1330	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1331
1332	/* Check three times here to reduce the chance of CPU migration
1333	resulting in false positives with things like the APIC ID. */
1334	uint32_t cSubLeaves;
1335	bool fFinalEcxUnchanged;
1336	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1337	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1338	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1339	{
1340	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1341	{
1342	/* This shouldn't happen. But in case it does, file all
1343	relevant details in the release log. */
1344	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1345	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1346	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1347	{
1348	uint32_t auTmp[4];
1349	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1350	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1351	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1352	}
1353	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1354	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1355	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1356	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1357	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1358	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1359	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1360	}
1361
1362	if (fFinalEcxUnchanged)
1363	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1364
1365	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1366	{
1367	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1368	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1369	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1370	if (RT_FAILURE(rc))
1371	return rc;
1372	}
1373	}
1374	else
1375	{
1376	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1377	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1378	if (RT_FAILURE(rc))
1379	return rc;
1380	}
1381
1382	/* next */
1383	uLeaf++;
1384	}
1385	}
1386	/*
1387	* Special CPUIDs needs special handling as they don't follow the
1388	* leaf count principle used above.
1389	*/
1390	else if (s_aCandidates[iOuter].fSpecial)
1391	{
1392	bool fKeep = false;
1393	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1394	fKeep = true;
1395	else if ( uLeaf == 0x8fffffff
1396	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1397	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1398	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1399	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1400	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1401	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1402	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1403	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1404	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1405	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1406	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1407	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1408	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1409	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1410	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1411	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1412	fKeep = true;
1413	if (fKeep)
1414	{
1415	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1416	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1417	if (RT_FAILURE(rc))
1418	return rc;
1419	}
1420	}
1421	}
1422
1423	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1424	return VINF_SUCCESS;
1425	}
1426
1427
1428	/**
1429	* Determines the method the CPU uses to handle unknown CPUID leaves.
1430	*
1431	* @returns VBox status code.
1432	* @param penmUnknownMethod Where to return the method.
1433	* @param pDefUnknown Where to return default unknown values. This
1434	* will be set, even if the resulting method
1435	* doesn't actually needs it.
1436	*/
1437	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1438	{
1439	uint32_t uLastStd = ASMCpuId_EAX(0);
1440	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1441	if (!ASMIsValidExtRange(uLastExt))
1442	uLastExt = 0x80000000;
1443
1444	uint32_t auChecks[] =
1445	{
1446	uLastStd + 1,
1447	uLastStd + 5,
1448	uLastStd + 8,
1449	uLastStd + 32,
1450	uLastStd + 251,
1451	uLastExt + 1,
1452	uLastExt + 8,
1453	uLastExt + 15,
1454	uLastExt + 63,
1455	uLastExt + 255,
1456	0x7fbbffcc,
1457	0x833f7872,
1458	0xefff2353,
1459	0x35779456,
1460	0x1ef6d33e,
1461	};
1462
1463	static const uint32_t s_auValues[] =
1464	{
1465	0xa95d2156,
1466	0x00000001,
1467	0x00000002,
1468	0x00000008,
1469	0x00000000,
1470	0x55773399,
1471	0x93401769,
1472	0x12039587,
1473	};
1474
1475	/*
1476	* Simple method, all zeros.
1477	*/
1478	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1479	pDefUnknown->uEax = 0;
1480	pDefUnknown->uEbx = 0;
1481	pDefUnknown->uEcx = 0;
1482	pDefUnknown->uEdx = 0;
1483
1484	/*
1485	* Intel has been observed returning the last standard leaf.
1486	*/
1487	uint32_t auLast[4];
1488	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1489
1490	uint32_t cChecks = RT_ELEMENTS(auChecks);
1491	while (cChecks > 0)
1492	{
1493	uint32_t auCur[4];
1494	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1495	if (memcmp(auCur, auLast, sizeof(auCur)))
1496	break;
1497	cChecks--;
1498	}
1499	if (cChecks == 0)
1500	{
1501	/* Now, what happens when the input changes? Esp. ECX. */
1502	uint32_t cTotal = 0;
1503	uint32_t cSame = 0;
1504	uint32_t cLastWithEcx = 0;
1505	uint32_t cNeither = 0;
1506	uint32_t cValues = RT_ELEMENTS(s_auValues);
1507	while (cValues > 0)
1508	{
1509	uint32_t uValue = s_auValues[cValues - 1];
1510	uint32_t auLastWithEcx[4];
1511	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1512	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1513
1514	cChecks = RT_ELEMENTS(auChecks);
1515	while (cChecks > 0)
1516	{
1517	uint32_t auCur[4];
1518	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1519	if (!memcmp(auCur, auLast, sizeof(auCur)))
1520	{
1521	cSame++;
1522	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1523	cLastWithEcx++;
1524	}
1525	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1526	cLastWithEcx++;
1527	else
1528	cNeither++;
1529	cTotal++;
1530	cChecks--;
1531	}
1532	cValues--;
1533	}
1534
1535	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1536	if (cSame == cTotal)
1537	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1538	else if (cLastWithEcx == cTotal)
1539	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1540	else
1541	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1542	pDefUnknown->uEax = auLast[0];
1543	pDefUnknown->uEbx = auLast[1];
1544	pDefUnknown->uEcx = auLast[2];
1545	pDefUnknown->uEdx = auLast[3];
1546	return VINF_SUCCESS;
1547	}
1548
1549	/*
1550	* Unchanged register values?
1551	*/
1552	cChecks = RT_ELEMENTS(auChecks);
1553	while (cChecks > 0)
1554	{
1555	uint32_t const uLeaf = auChecks[cChecks - 1];
1556	uint32_t cValues = RT_ELEMENTS(s_auValues);
1557	while (cValues > 0)
1558	{
1559	uint32_t uValue = s_auValues[cValues - 1];
1560	uint32_t auCur[4];
1561	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1562	if ( auCur[0] != uLeaf
1563	\|\| auCur[1] != uValue
1564	\|\| auCur[2] != uValue
1565	\|\| auCur[3] != uValue)
1566	break;
1567	cValues--;
1568	}
1569	if (cValues != 0)
1570	break;
1571	cChecks--;
1572	}
1573	if (cChecks == 0)
1574	{
1575	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1576	return VINF_SUCCESS;
1577	}
1578
1579	/*
1580	* Just go with the simple method.
1581	*/
1582	return VINF_SUCCESS;
1583	}
1584
1585
1586	/**
1587	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1588	*
1589	* @returns Read only name string.
1590	* @param enmUnknownMethod The method to translate.
1591	*/
1592	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1593	{
1594	switch (enmUnknownMethod)
1595	{
1596	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1597	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1598	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1599	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1600
1601	case CPUMUNKNOWNCPUID_INVALID:
1602	case CPUMUNKNOWNCPUID_END:
1603	case CPUMUNKNOWNCPUID_32BIT_HACK:
1604	break;
1605	}
1606	return "Invalid-unknown-CPUID-method";
1607	}
1608
1609
1610	/**
1611	* Detect the CPU vendor give n the
1612	*
1613	* @returns The vendor.
1614	* @param uEAX EAX from CPUID(0).
1615	* @param uEBX EBX from CPUID(0).
1616	* @param uECX ECX from CPUID(0).
1617	* @param uEDX EDX from CPUID(0).
1618	*/
1619	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1620	{
1621	if (ASMIsValidStdRange(uEAX))
1622	{
1623	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1624	return CPUMCPUVENDOR_AMD;
1625
1626	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1627	return CPUMCPUVENDOR_INTEL;
1628
1629	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1630	return CPUMCPUVENDOR_VIA;
1631
1632	if (ASMIsShanghaiCpuEx(uEBX, uECX, uEDX))
1633	return CPUMCPUVENDOR_SHANGHAI;
1634
1635	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1636	&& uECX == UINT32_C(0x64616574)
1637	&& uEDX == UINT32_C(0x736E4978))
1638	return CPUMCPUVENDOR_CYRIX;
1639
1640	/* "Geode by NSC", example: family 5, model 9. */
1641
1642	/** @todo detect the other buggers... */
1643	}
1644
1645	return CPUMCPUVENDOR_UNKNOWN;
1646	}
1647
1648
1649	/**
1650	* Translates a CPU vendor enum value into the corresponding string constant.
1651	*
1652	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1653	* value name. This can be useful when generating code.
1654	*
1655	* @returns Read only name string.
1656	* @param enmVendor The CPU vendor value.
1657	*/
1658	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1659	{
1660	switch (enmVendor)
1661	{
1662	case CPUMCPUVENDOR_INTEL: return "INTEL";
1663	case CPUMCPUVENDOR_AMD: return "AMD";
1664	case CPUMCPUVENDOR_VIA: return "VIA";
1665	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1666	case CPUMCPUVENDOR_SHANGHAI: return "SHANGHAI";
1667	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1668
1669	case CPUMCPUVENDOR_INVALID:
1670	case CPUMCPUVENDOR_32BIT_HACK:
1671	break;
1672	}
1673	return "Invalid-cpu-vendor";
1674	}
1675
1676
1677	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1678	{
1679	/* Could do binary search, doing linear now because I'm lazy. */
1680	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1681	while (cLeaves-- > 0)
1682	{
1683	if (pLeaf->uLeaf == uLeaf)
1684	return pLeaf;
1685	pLeaf++;
1686	}
1687	return NULL;
1688	}
1689
1690
1691	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1692	{
1693	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1694	if ( !pLeaf
1695	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1696	return pLeaf;
1697
1698	/* Linear sub-leaf search. Lazy as usual. */
1699	cLeaves -= pLeaf - paLeaves;
1700	while ( cLeaves-- > 0
1701	&& pLeaf->uLeaf == uLeaf)
1702	{
1703	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1704	return pLeaf;
1705	pLeaf++;
1706	}
1707
1708	return NULL;
1709	}
1710
1711
1712	static void cpumR3ExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURES pFeatures)
1713	{
1714	Assert(pVmxMsrs);
1715	Assert(pFeatures);
1716	Assert(pFeatures->fVmx);
1717
1718	/* Basic information. */
1719	{
1720	uint64_t const u64Basic = pVmxMsrs->u64Basic;
1721	pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1722	}
1723
1724	/* Pin-based VM-execution controls. */
1725	{
1726	uint32_t const fPinCtls = pVmxMsrs->PinCtls.n.allowed1;
1727	pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1728	pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1729	pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1730	pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1731	pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1732	}
1733
1734	/* Processor-based VM-execution controls. */
1735	{
1736	uint32_t const fProcCtls = pVmxMsrs->ProcCtls.n.allowed1;
1737	pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1738	pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1739	pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1740	pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1741	pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1742	pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1743	pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1744	pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1745	pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1746	pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1747	pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1748	pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1749	pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1750	pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1751	pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1752	pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1753	pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1754	pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1755	pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1756	pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1757	pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1758	}
1759
1760	/* Secondary processor-based VM-execution controls. */
1761	{
1762	uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1763	pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1764	pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1765	pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1766	pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1767	pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1768	pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1769	pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1770	pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1771	pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1772	pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1773	pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1774	pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1775	pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1776	pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1777	pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1778	pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1779	pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1780	pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_VE);
1781	pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1782	pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1783	}
1784
1785	/* VM-exit controls. */
1786	{
1787	uint32_t const fExitCtls = pVmxMsrs->ExitCtls.n.allowed1;
1788	pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1789	pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1790	pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1791	pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1792	pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1793	pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1794	pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1795	pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1796	}
1797
1798	/* VM-entry controls. */
1799	{
1800	uint32_t const fEntryCtls = pVmxMsrs->EntryCtls.n.allowed1;
1801	pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1802	pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1803	pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1804	pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1805	}
1806
1807	/* Miscellaneous data. */
1808	{
1809	uint32_t const fMiscData = pVmxMsrs->u64Misc;
1810	pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1811	pFeatures->fVmxIntelPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1812	pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1813	pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1814	}
1815	}
1816
1817
1818	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures)
1819	{
1820	Assert(pMsrs);
1821	RT_ZERO(*pFeatures);
1822	if (cLeaves >= 2)
1823	{
1824	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1825	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1826	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1827	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1828	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1829	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1830
1831	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1832	pStd0Leaf->uEbx,
1833	pStd0Leaf->uEcx,
1834	pStd0Leaf->uEdx);
1835	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1836	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1837	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1838	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1839	pFeatures->uFamily,
1840	pFeatures->uModel,
1841	pFeatures->uStepping);
1842
1843	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1844	if (pExtLeaf8)
1845	{
1846	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1847	pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1848	}
1849	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1850	{
1851	pFeatures->cMaxPhysAddrWidth = 36;
1852	pFeatures->cMaxLinearAddrWidth = 36;
1853	}
1854	else
1855	{
1856	pFeatures->cMaxPhysAddrWidth = 32;
1857	pFeatures->cMaxLinearAddrWidth = 32;
1858	}
1859
1860	/* Standard features. */
1861	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1862	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1863	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1864	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1865	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1866	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1867	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1868	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1869	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1870	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1871	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1872	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1873	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1874	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1875	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1876	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1877	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1878	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1879	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1880	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1881	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1882	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1883	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1884	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1885	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1886	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1887	if (pFeatures->fVmx)
1888	cpumR3ExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1889
1890	/* Structured extended features. */
1891	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1892	if (pSxfLeaf0)
1893	{
1894	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1895	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1896	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1897	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1898	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1899
1900	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1901	pFeatures->fIbrs = pFeatures->fIbpb;
1902	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1903	pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
1904	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1905	pFeatures->fMdsClear = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
1906	}
1907
1908	/* MWAIT/MONITOR leaf. */
1909	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1910	if (pMWaitLeaf)
1911	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1912	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1913
1914	/* Extended features. */
1915	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1916	if (pExtLeaf)
1917	{
1918	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1919	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1920	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1921	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1922	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1923	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1924	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1925	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1926	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1927	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1928	}
1929
1930	/* VMX (VMXON, VMCS region and related data structures') physical address width (depends on long-mode). */
1931	pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
1932
1933	if ( pExtLeaf
1934	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1935	{
1936	/* AMD features. */
1937	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1938	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1939	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1940	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1941	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1942	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1943	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1944	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1945	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1946	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1947	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1948	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1949	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1950	if (pFeatures->fSvm)
1951	{
1952	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1953	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1954	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1955	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1956	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1957	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1958	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1959	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1960	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1961	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1962	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1963	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1964	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1965	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1966	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1967	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1968	}
1969	}
1970
1971	/*
1972	* Quirks.
1973	*/
1974	pFeatures->fLeakyFxSR = pExtLeaf
1975	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1976	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1977	&& pFeatures->uFamily >= 6 /* K7 and up */;
1978
1979	/*
1980	* Max extended (/FPU) state.
1981	*/
1982	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1983	if (pFeatures->fXSaveRstor)
1984	{
1985	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1986	if (pXStateLeaf0)
1987	{
1988	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1989	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1990	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1991	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1992	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1993	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1994	{
1995	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1996
1997	/* (paranoia:) */
1998	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1999	if ( pXStateLeaf1
2000	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
2001	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
2002	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
2003	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
2004	}
2005	else
2006	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
2007	pFeatures->fXSaveRstor = 0);
2008	}
2009	else
2010	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
2011	pFeatures->fXSaveRstor = 0);
2012	}
2013	}
2014	else
2015	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
2016	return VINF_SUCCESS;
2017	}
2018
2019
2020	/*
2021	*
2022	* Init related code.
2023	* Init related code.
2024	* Init related code.
2025	*
2026	*
2027	*/
2028	#ifdef VBOX_IN_VMM
2029
2030
2031	/**
2032	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
2033	*
2034	* This ignores the fSubLeafMask.
2035	*
2036	* @returns Pointer to the matching leaf, or NULL if not found.
2037	* @param paLeaves The CPUID leaves to search. This is sorted.
2038	* @param cLeaves The number of leaves in the array.
2039	* @param uLeaf The leaf to locate.
2040	* @param uSubLeaf The subleaf to locate.
2041	*/
2042	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
2043	{
2044	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
2045	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
2046	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
2047	if (iEnd)
2048	{
2049	uint32_t iBegin = 0;
2050	for (;;)
2051	{
2052	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
2053	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
2054	if (uNeedle < uCur)
2055	{
2056	if (i > iBegin)
2057	iEnd = i;
2058	else
2059	break;
2060	}
2061	else if (uNeedle > uCur)
2062	{
2063	if (i + 1 < iEnd)
2064	iBegin = i + 1;
2065	else
2066	break;
2067	}
2068	else
2069	return &paLeaves[i];
2070	}
2071	}
2072	return NULL;
2073	}
2074
2075
2076	/**
2077	* Loads MSR range overrides.
2078	*
2079	* This must be called before the MSR ranges are moved from the normal heap to
2080	* the hyper heap!
2081	*
2082	* @returns VBox status code (VMSetError called).
2083	* @param pVM The cross context VM structure.
2084	* @param pMsrNode The CFGM node with the MSR overrides.
2085	*/
2086	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
2087	{
2088	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2089	{
2090	/*
2091	* Assemble a valid MSR range.
2092	*/
2093	CPUMMSRRANGE MsrRange;
2094	MsrRange.offCpumCpu = 0;
2095	MsrRange.fReserved = 0;
2096
2097	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
2098	if (RT_FAILURE(rc))
2099	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
2100
2101	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
2102	if (RT_FAILURE(rc))
2103	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
2104	MsrRange.szName, rc);
2105
2106	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
2107	if (RT_FAILURE(rc))
2108	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
2109	MsrRange.szName, rc);
2110
2111	char szType[32];
2112	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
2113	if (RT_FAILURE(rc))
2114	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
2115	MsrRange.szName, rc);
2116	if (!RTStrICmp(szType, "FixedValue"))
2117	{
2118	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
2119	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
2120
2121	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
2122	if (RT_FAILURE(rc))
2123	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
2124	MsrRange.szName, rc);
2125
2126	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
2127	if (RT_FAILURE(rc))
2128	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
2129	MsrRange.szName, rc);
2130
2131	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
2132	if (RT_FAILURE(rc))
2133	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
2134	MsrRange.szName, rc);
2135	}
2136	else
2137	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
2138	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
2139
2140	/*
2141	* Insert the range into the table (replaces/splits/shrinks existing
2142	* MSR ranges).
2143	*/
2144	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
2145	&MsrRange);
2146	if (RT_FAILURE(rc))
2147	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
2148	}
2149
2150	return VINF_SUCCESS;
2151	}
2152
2153
2154	/**
2155	* Loads CPUID leaf overrides.
2156	*
2157	* This must be called before the CPUID leaves are moved from the normal
2158	* heap to the hyper heap!
2159	*
2160	* @returns VBox status code (VMSetError called).
2161	* @param pVM The cross context VM structure.
2162	* @param pParentNode The CFGM node with the CPUID leaves.
2163	* @param pszLabel How to label the overrides we're loading.
2164	*/
2165	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2166	{
2167	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2168	{
2169	/*
2170	* Get the leaf and subleaf numbers.
2171	*/
2172	char szName[128];
2173	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2174	if (RT_FAILURE(rc))
2175	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2176
2177	/* The leaf number is either specified directly or thru the node name. */
2178	uint32_t uLeaf;
2179	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2180	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2181	{
2182	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2183	if (rc != VINF_SUCCESS)
2184	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2185	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2186	}
2187	else if (RT_FAILURE(rc))
2188	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2189	pszLabel, szName, rc);
2190
2191	uint32_t uSubLeaf;
2192	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2193	if (RT_FAILURE(rc))
2194	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2195	pszLabel, szName, rc);
2196
2197	uint32_t fSubLeafMask;
2198	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2199	if (RT_FAILURE(rc))
2200	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2201	pszLabel, szName, rc);
2202
2203	/*
2204	* Look up the specified leaf, since the output register values
2205	* defaults to any existing values. This allows overriding a single
2206	* register, without needing to know the other values.
2207	*/
2208	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2209	CPUMCPUIDLEAF Leaf;
2210	if (pLeaf)
2211	Leaf = *pLeaf;
2212	else
2213	RT_ZERO(Leaf);
2214	Leaf.uLeaf = uLeaf;
2215	Leaf.uSubLeaf = uSubLeaf;
2216	Leaf.fSubLeafMask = fSubLeafMask;
2217
2218	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2219	if (RT_FAILURE(rc))
2220	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2221	pszLabel, szName, rc);
2222	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2223	if (RT_FAILURE(rc))
2224	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2225	pszLabel, szName, rc);
2226	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2227	if (RT_FAILURE(rc))
2228	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2229	pszLabel, szName, rc);
2230	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2231	if (RT_FAILURE(rc))
2232	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2233	pszLabel, szName, rc);
2234
2235	/*
2236	* Insert the leaf into the table (replaces existing ones).
2237	*/
2238	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2239	&Leaf);
2240	if (RT_FAILURE(rc))
2241	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2242	}
2243
2244	return VINF_SUCCESS;
2245	}
2246
2247
2248
2249	/**
2250	* Fetches overrides for a CPUID leaf.
2251	*
2252	* @returns VBox status code.
2253	* @param pLeaf The leaf to load the overrides into.
2254	* @param pCfgNode The CFGM node containing the overrides
2255	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2256	* @param iLeaf The CPUID leaf number.
2257	*/
2258	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2259	{
2260	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2261	if (pLeafNode)
2262	{
2263	uint32_t u32;
2264	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2265	if (RT_SUCCESS(rc))
2266	pLeaf->uEax = u32;
2267	else
2268	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2269
2270	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2271	if (RT_SUCCESS(rc))
2272	pLeaf->uEbx = u32;
2273	else
2274	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2275
2276	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2277	if (RT_SUCCESS(rc))
2278	pLeaf->uEcx = u32;
2279	else
2280	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2281
2282	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2283	if (RT_SUCCESS(rc))
2284	pLeaf->uEdx = u32;
2285	else
2286	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2287
2288	}
2289	return VINF_SUCCESS;
2290	}
2291
2292
2293	/**
2294	* Load the overrides for a set of CPUID leaves.
2295	*
2296	* @returns VBox status code.
2297	* @param paLeaves The leaf array.
2298	* @param cLeaves The number of leaves.
2299	* @param uStart The start leaf number.
2300	* @param pCfgNode The CFGM node containing the overrides
2301	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2302	*/
2303	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2304	{
2305	for (uint32_t i = 0; i < cLeaves; i++)
2306	{
2307	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2308	if (RT_FAILURE(rc))
2309	return rc;
2310	}
2311
2312	return VINF_SUCCESS;
2313	}
2314
2315
2316	/**
2317	* Installs the CPUID leaves and explods the data into structures like
2318	* GuestFeatures and CPUMCTX::aoffXState.
2319	*
2320	* @returns VBox status code.
2321	* @param pVM The cross context VM structure.
2322	* @param pCpum The CPUM part of @a VM.
2323	* @param paLeaves The leaves. These will be copied (but not freed).
2324	* @param cLeaves The number of leaves.
2325	* @param pMsrs The MSRs.
2326	*/
2327	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
2328	{
2329	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2330
2331	/*
2332	* Install the CPUID information.
2333	*/
2334	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2335	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2336
2337	AssertLogRelRCReturn(rc, rc);
2338	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2339	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2340	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2341	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2342	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2343
2344	/*
2345	* Update the default CPUID leaf if necessary.
2346	*/
2347	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2348	{
2349	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2350	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2351	{
2352	/* We don't use CPUID(0).eax here because of the NT hack that only
2353	changes that value without actually removing any leaves. */
2354	uint32_t i = 0;
2355	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2356	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2357	{
2358	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2359	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2360	i++;
2361	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2362	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2363	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2364	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2365	}
2366	break;
2367	}
2368	default:
2369	break;
2370	}
2371
2372	/*
2373	* Explode the guest CPU features.
2374	*/
2375	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
2376	&pCpum->GuestFeatures);
2377	AssertLogRelRCReturn(rc, rc);
2378
2379	/*
2380	* Adjust the scalable bus frequency according to the CPUID information
2381	* we're now using.
2382	*/
2383	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2384	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2385	? UINT64_C(100000000) /* 100MHz */
2386	: UINT64_C(133333333); /* 133MHz */
2387
2388	/*
2389	* Populate the legacy arrays. Currently used for everything, later only
2390	* for patch manager.
2391	*/
2392	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2393	{
2394	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2395	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2396	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2397	};
2398	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2399	{
2400	uint32_t cLeft = aOldRanges[i].cCpuIds;
2401	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2402	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2403	while (cLeft-- > 0)
2404	{
2405	uLeaf--;
2406	pLegacyLeaf--;
2407
2408	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2409	if (pLeaf)
2410	{
2411	pLegacyLeaf->uEax = pLeaf->uEax;
2412	pLegacyLeaf->uEbx = pLeaf->uEbx;
2413	pLegacyLeaf->uEcx = pLeaf->uEcx;
2414	pLegacyLeaf->uEdx = pLeaf->uEdx;
2415	}
2416	else
2417	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2418	}
2419	}
2420
2421	/*
2422	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2423	*/
2424	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2425	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2426	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2427	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2428	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2429	{
2430	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2431	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2432	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2433	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2434	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2435	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2436	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2437	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2438	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2439	pCpum->GuestFeatures.cbMaxExtendedState),
2440	VERR_CPUM_IPE_1);
2441	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2442	}
2443	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2444
2445	/* Copy the CPU #0 data to the other CPUs. */
2446	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2447	{
2448	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2449	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2450	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2451	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2452	}
2453
2454	return VINF_SUCCESS;
2455	}
2456
2457
2458	/** @name Instruction Set Extension Options
2459	* @{ */
2460	/** Configuration option type (extended boolean, really). */
2461	typedef uint8_t CPUMISAEXTCFG;
2462	/** Always disable the extension. */
2463	#define CPUMISAEXTCFG_DISABLED false
2464	/** Enable the extension if it's supported by the host CPU. */
2465	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2466	/** Enable the extension if it's supported by the host CPU, but don't let
2467	* the portable CPUID feature disable it. */
2468	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2469	/** Always enable the extension. */
2470	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2471	/** @} */
2472
2473	/**
2474	* CPUID Configuration (from CFGM).
2475	*
2476	* @remarks The members aren't document since we would only be duplicating the
2477	* \@cfgm entries in cpumR3CpuIdReadConfig.
2478	*/
2479	typedef struct CPUMCPUIDCONFIG
2480	{
2481	bool fNt4LeafLimit;
2482	bool fInvariantTsc;
2483	bool fForceVme;
2484	bool fNestedHWVirt;
2485
2486	CPUMISAEXTCFG enmCmpXchg16b;
2487	CPUMISAEXTCFG enmMonitor;
2488	CPUMISAEXTCFG enmMWaitExtensions;
2489	CPUMISAEXTCFG enmSse41;
2490	CPUMISAEXTCFG enmSse42;
2491	CPUMISAEXTCFG enmAvx;
2492	CPUMISAEXTCFG enmAvx2;
2493	CPUMISAEXTCFG enmXSave;
2494	CPUMISAEXTCFG enmAesNi;
2495	CPUMISAEXTCFG enmPClMul;
2496	CPUMISAEXTCFG enmPopCnt;
2497	CPUMISAEXTCFG enmMovBe;
2498	CPUMISAEXTCFG enmRdRand;
2499	CPUMISAEXTCFG enmRdSeed;
2500	CPUMISAEXTCFG enmCLFlushOpt;
2501	CPUMISAEXTCFG enmFsGsBase;
2502	CPUMISAEXTCFG enmPcid;
2503	CPUMISAEXTCFG enmInvpcid;
2504	CPUMISAEXTCFG enmFlushCmdMsr;
2505	CPUMISAEXTCFG enmMdsClear;
2506	CPUMISAEXTCFG enmArchCapMsr;
2507
2508	CPUMISAEXTCFG enmAbm;
2509	CPUMISAEXTCFG enmSse4A;
2510	CPUMISAEXTCFG enmMisAlnSse;
2511	CPUMISAEXTCFG enm3dNowPrf;
2512	CPUMISAEXTCFG enmAmdExtMmx;
2513
2514	uint32_t uMaxStdLeaf;
2515	uint32_t uMaxExtLeaf;
2516	uint32_t uMaxCentaurLeaf;
2517	uint32_t uMaxIntelFamilyModelStep;
2518	char szCpuName[128];
2519	} CPUMCPUIDCONFIG;
2520	/** Pointer to CPUID config (from CFGM). */
2521	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2522
2523
2524	/**
2525	* Mini CPU selection support for making Mac OS X happy.
2526	*
2527	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2528	*
2529	* @param pCpum The CPUM instance data.
2530	* @param pConfig The CPUID configuration we've read from CFGM.
2531	*/
2532	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2533	{
2534	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2535	{
2536	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2537	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2538	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2539	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2540	0);
2541	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2542	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2543	{
2544	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2545	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2546	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2547	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2548	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2549	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2550	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2551	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2552	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2553	pStdFeatureLeaf->uEax = uNew;
2554	}
2555	}
2556	}
2557
2558
2559
2560	/**
2561	* Limit it the number of entries, zapping the remainder.
2562	*
2563	* The limits are masking off stuff about power saving and similar, this
2564	* is perhaps a bit crudely done as there is probably some relatively harmless
2565	* info too in these leaves (like words about having a constant TSC).
2566	*
2567	* @param pCpum The CPUM instance data.
2568	* @param pConfig The CPUID configuration we've read from CFGM.
2569	*/
2570	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2571	{
2572	/*
2573	* Standard leaves.
2574	*/
2575	uint32_t uSubLeaf = 0;
2576	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2577	if (pCurLeaf)
2578	{
2579	uint32_t uLimit = pCurLeaf->uEax;
2580	if (uLimit <= UINT32_C(0x000fffff))
2581	{
2582	if (uLimit > pConfig->uMaxStdLeaf)
2583	{
2584	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2585	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2586	uLimit + 1, UINT32_C(0x000fffff));
2587	}
2588
2589	/* NT4 hack, no zapping of extra leaves here. */
2590	if (pConfig->fNt4LeafLimit && uLimit > 3)
2591	pCurLeaf->uEax = uLimit = 3;
2592
2593	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2594	pCurLeaf->uEax = uLimit;
2595	}
2596	else
2597	{
2598	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2599	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2600	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2601	}
2602	}
2603
2604	/*
2605	* Extended leaves.
2606	*/
2607	uSubLeaf = 0;
2608	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2609	if (pCurLeaf)
2610	{
2611	uint32_t uLimit = pCurLeaf->uEax;
2612	if ( uLimit >= UINT32_C(0x80000000)
2613	&& uLimit <= UINT32_C(0x800fffff))
2614	{
2615	if (uLimit > pConfig->uMaxExtLeaf)
2616	{
2617	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2618	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2619	uLimit + 1, UINT32_C(0x800fffff));
2620	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2621	pCurLeaf->uEax = uLimit;
2622	}
2623	}
2624	else
2625	{
2626	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2627	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2628	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2629	}
2630	}
2631
2632	/*
2633	* Centaur leaves (VIA).
2634	*/
2635	uSubLeaf = 0;
2636	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2637	if (pCurLeaf)
2638	{
2639	uint32_t uLimit = pCurLeaf->uEax;
2640	if ( uLimit >= UINT32_C(0xc0000000)
2641	&& uLimit <= UINT32_C(0xc00fffff))
2642	{
2643	if (uLimit > pConfig->uMaxCentaurLeaf)
2644	{
2645	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2646	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2647	uLimit + 1, UINT32_C(0xcfffffff));
2648	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2649	pCurLeaf->uEax = uLimit;
2650	}
2651	}
2652	else
2653	{
2654	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2655	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2656	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2657	}
2658	}
2659	}
2660
2661
2662	/**
2663	* Clears a CPUID leaf and all sub-leaves (to zero).
2664	*
2665	* @param pCpum The CPUM instance data.
2666	* @param uLeaf The leaf to clear.
2667	*/
2668	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2669	{
2670	uint32_t uSubLeaf = 0;
2671	PCPUMCPUIDLEAF pCurLeaf;
2672	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2673	{
2674	pCurLeaf->uEax = 0;
2675	pCurLeaf->uEbx = 0;
2676	pCurLeaf->uEcx = 0;
2677	pCurLeaf->uEdx = 0;
2678	uSubLeaf++;
2679	}
2680	}
2681
2682
2683	/**
2684	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2685	* the given leaf.
2686	*
2687	* @returns pLeaf.
2688	* @param pCpum The CPUM instance data.
2689	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2690	*/
2691	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2692	{
2693	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2694	if (pLeaf->fSubLeafMask != 0)
2695	{
2696	/*
2697	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2698	* Log everything while we're at it.
2699	*/
2700	LogRel(("CPUM:\n"
2701	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2702	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2703	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2704	for (;;)
2705	{
2706	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2707	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2708	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2709	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2710	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2711	break;
2712	pSubLeaf++;
2713	}
2714	LogRel(("CPUM:\n"));
2715
2716	/*
2717	* Remove the offending sub-leaves.
2718	*/
2719	if (pSubLeaf != pLeaf)
2720	{
2721	if (pSubLeaf != pLast)
2722	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2723	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2724	}
2725
2726	/*
2727	* Convert the first sub-leaf into a single leaf.
2728	*/
2729	pLeaf->uSubLeaf = 0;
2730	pLeaf->fSubLeafMask = 0;
2731	}
2732	return pLeaf;
2733	}
2734
2735
2736	/**
2737	* Sanitizes and adjust the CPUID leaves.
2738	*
2739	* Drop features that aren't virtualized (or virtualizable). Adjust information
2740	* and capabilities to fit the virtualized hardware. Remove information the
2741	* guest shouldn't have (because it's wrong in the virtual world or because it
2742	* gives away host details) or that we don't have documentation for and no idea
2743	* what means.
2744	*
2745	* @returns VBox status code.
2746	* @param pVM The cross context VM structure (for cCpus).
2747	* @param pCpum The CPUM instance data.
2748	* @param pConfig The CPUID configuration we've read from CFGM.
2749	*/
2750	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2751	{
2752	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2753	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2754	{ \
2755	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2756	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2757	}
2758	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2759	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2760	{ \
2761	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2762	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2763	}
2764	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2765	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2766	&& ((a_pLeafReg) & (fBitMask)) \
2767	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2768	{ \
2769	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2770	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2771	}
2772	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2773
2774	/* Cpuid 1:
2775	* EAX: CPU model, family and stepping.
2776	*
2777	* ECX + EDX: Supported features. Only report features we can support.
2778	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2779	* options may require adjusting (i.e. stripping what was enabled).
2780	*
2781	* EBX: Branding, CLFLUSH line size, logical processors per package and
2782	* initial APIC ID.
2783	*/
2784	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2785	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2786	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2787
2788	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2789	\| X86_CPUID_FEATURE_EDX_VME
2790	\| X86_CPUID_FEATURE_EDX_DE
2791	\| X86_CPUID_FEATURE_EDX_PSE
2792	\| X86_CPUID_FEATURE_EDX_TSC
2793	\| X86_CPUID_FEATURE_EDX_MSR
2794	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2795	\| X86_CPUID_FEATURE_EDX_MCE
2796	\| X86_CPUID_FEATURE_EDX_CX8
2797	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2798	//\| RT_BIT_32(10) - not defined
2799	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2800	//\| X86_CPUID_FEATURE_EDX_SEP
2801	\| X86_CPUID_FEATURE_EDX_MTRR
2802	\| X86_CPUID_FEATURE_EDX_PGE
2803	\| X86_CPUID_FEATURE_EDX_MCA
2804	\| X86_CPUID_FEATURE_EDX_CMOV
2805	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2806	\| X86_CPUID_FEATURE_EDX_PSE36
2807	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2808	\| X86_CPUID_FEATURE_EDX_CLFSH
2809	//\| RT_BIT_32(20) - not defined
2810	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2811	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2812	\| X86_CPUID_FEATURE_EDX_MMX
2813	\| X86_CPUID_FEATURE_EDX_FXSR
2814	\| X86_CPUID_FEATURE_EDX_SSE
2815	\| X86_CPUID_FEATURE_EDX_SSE2
2816	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2817	\| X86_CPUID_FEATURE_EDX_HTT
2818	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2819	//\| RT_BIT_32(30) - not defined
2820	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2821	;
2822	pStdFeatureLeaf->uEcx &= 0
2823	\| X86_CPUID_FEATURE_ECX_SSE3
2824	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2825	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2826	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2827	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2828	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2829	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2830	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2831	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2832	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2833	\| X86_CPUID_FEATURE_ECX_SSSE3
2834	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2835	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2836	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2837	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2838	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2839	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2840	\| (pConfig->enmPcid ? X86_CPUID_FEATURE_ECX_PCID : 0)
2841	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2842	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2843	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2844	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2845	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2846	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2847	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2848	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2849	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2850	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2851	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2852	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2853	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2854	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2855	;
2856
2857	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2858	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2859	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2860	{
2861	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2862	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2863	}
2864
2865	if (pCpum->u8PortableCpuIdLevel > 0)
2866	{
2867	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2868	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2869	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2870	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2871	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2872	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2873	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2874	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2875	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2876	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2877	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2878	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2879	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2880	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2881	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2882	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2883	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2884	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2885	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2886	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2887
2888	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2889	\| X86_CPUID_FEATURE_EDX_PSN
2890	\| X86_CPUID_FEATURE_EDX_DS
2891	\| X86_CPUID_FEATURE_EDX_ACPI
2892	\| X86_CPUID_FEATURE_EDX_SS
2893	\| X86_CPUID_FEATURE_EDX_TM
2894	\| X86_CPUID_FEATURE_EDX_PBE
2895	)));
2896	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2897	\| X86_CPUID_FEATURE_ECX_CPLDS
2898	\| X86_CPUID_FEATURE_ECX_AES
2899	\| X86_CPUID_FEATURE_ECX_VMX
2900	\| X86_CPUID_FEATURE_ECX_SMX
2901	\| X86_CPUID_FEATURE_ECX_EST
2902	\| X86_CPUID_FEATURE_ECX_TM2
2903	\| X86_CPUID_FEATURE_ECX_CNTXID
2904	\| X86_CPUID_FEATURE_ECX_FMA
2905	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2906	\| X86_CPUID_FEATURE_ECX_PDCM
2907	\| X86_CPUID_FEATURE_ECX_DCA
2908	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2909	)));
2910	}
2911
2912	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2913	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2914
2915	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2916	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2917	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2918	*/
2919	#ifdef VBOX_WITH_MULTI_CORE
2920	if (pVM->cCpus > 1)
2921	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2922	#endif
2923	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2924	{
2925	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2926	core times the number of CPU cores per processor */
2927	#ifdef VBOX_WITH_MULTI_CORE
2928	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2929	#else
2930	/* Single logical processor in a package. */
2931	pStdFeatureLeaf->uEbx \|= (1 << 16);
2932	#endif
2933	}
2934
2935	uint32_t uMicrocodeRev;
2936	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2937	if (RT_SUCCESS(rc))
2938	{
2939	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2940	}
2941	else
2942	{
2943	uMicrocodeRev = 0;
2944	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2945	}
2946
2947	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2948	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2949	*/
2950	if ( (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen)
2951	&& uMicrocodeRev < 0x8001126
2952	&& !pConfig->fForceVme)
2953	{
2954	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2955	LogRel(("CPUM: Zen VME workaround engaged\n"));
2956	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2957	}
2958
2959	/* Force standard feature bits. */
2960	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2961	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2962	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2963	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2964	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2965	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2966	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2967	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2968	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2969	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2970	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2971	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2972	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2973	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2974	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2975	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2976	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2977	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2978	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2979	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2980	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2981	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2982
2983	pStdFeatureLeaf = NULL; /* Must refetch! */
2984
2985	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2986	* AMD:
2987	* EAX: CPU model, family and stepping.
2988	*
2989	* ECX + EDX: Supported features. Only report features we can support.
2990	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2991	* options may require adjusting (i.e. stripping what was enabled).
2992	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2993	*
2994	* EBX: Branding ID and package type (or reserved).
2995	*
2996	* Intel and probably most others:
2997	* EAX: 0
2998	* EBX: 0
2999	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
3000	*/
3001	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3002	if (pExtFeatureLeaf)
3003	{
3004	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
3005
3006	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
3007	\| X86_CPUID_AMD_FEATURE_EDX_VME
3008	\| X86_CPUID_AMD_FEATURE_EDX_DE
3009	\| X86_CPUID_AMD_FEATURE_EDX_PSE
3010	\| X86_CPUID_AMD_FEATURE_EDX_TSC
3011	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
3012	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
3013	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
3014	\| X86_CPUID_AMD_FEATURE_EDX_CX8
3015	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
3016	//\| RT_BIT_32(10) - reserved
3017	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
3018	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
3019	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3020	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
3021	\| X86_CPUID_AMD_FEATURE_EDX_PGE
3022	\| X86_CPUID_AMD_FEATURE_EDX_MCA
3023	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
3024	\| X86_CPUID_AMD_FEATURE_EDX_PAT
3025	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
3026	//\| RT_BIT_32(18) - reserved
3027	//\| RT_BIT_32(19) - reserved
3028	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
3029	//\| RT_BIT_32(21) - reserved
3030	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
3031	\| X86_CPUID_AMD_FEATURE_EDX_MMX
3032	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
3033	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
3034	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3035	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
3036	//\| RT_BIT_32(28) - reserved
3037	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
3038	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
3039	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
3040	;
3041	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
3042	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
3043	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
3044	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3045	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
3046	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
3047	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
3048	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
3049	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
3050	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
3051	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3052	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
3053	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
3054	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3055	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
3056	//\| RT_BIT_32(14) - reserved
3057	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
3058	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
3059	//\| RT_BIT_32(17) - reserved
3060	//\| RT_BIT_32(18) - reserved
3061	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
3062	//\| RT_BIT_32(20) - reserved
3063	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
3064	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
3065	//\| RT_BIT_32(23) - reserved
3066	//\| RT_BIT_32(24) - reserved
3067	//\| RT_BIT_32(25) - reserved
3068	//\| RT_BIT_32(26) - reserved
3069	//\| RT_BIT_32(27) - reserved
3070	//\| RT_BIT_32(28) - reserved
3071	//\| RT_BIT_32(29) - reserved
3072	//\| RT_BIT_32(30) - reserved
3073	//\| RT_BIT_32(31) - reserved
3074	;
3075	#ifdef VBOX_WITH_MULTI_CORE
3076	if ( pVM->cCpus > 1
3077	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3078	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
3079	#endif
3080
3081	if (pCpum->u8PortableCpuIdLevel > 0)
3082	{
3083	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
3084	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
3085	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
3086	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
3087	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
3088	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
3089	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
3090	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
3091	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
3092	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
3093	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
3094	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
3095	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
3096	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
3097	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
3098	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
3099
3100	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
3101	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3102	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3103	\| X86_CPUID_AMD_FEATURE_ECX_IBS
3104	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3105	\| X86_CPUID_AMD_FEATURE_ECX_WDT
3106	\| X86_CPUID_AMD_FEATURE_ECX_LWP
3107	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
3108	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
3109	\| UINT32_C(0xff964000)
3110	)));
3111	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
3112	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3113	\| RT_BIT(18)
3114	\| RT_BIT(19)
3115	\| RT_BIT(21)
3116	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
3117	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3118	\| RT_BIT(28)
3119	)));
3120	}
3121
3122	/* Force extended feature bits. */
3123	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
3124	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
3125	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
3126	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
3127	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
3128	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
3129	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
3130	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
3131	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3132	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
3133	}
3134	pExtFeatureLeaf = NULL; /* Must refetch! */
3135
3136
3137	/* Cpuid 2:
3138	* Intel: (Nondeterministic) Cache and TLB information
3139	* AMD: Reserved
3140	* VIA: Reserved
3141	* Safe to expose.
3142	*/
3143	uint32_t uSubLeaf = 0;
3144	PCPUMCPUIDLEAF pCurLeaf;
3145	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
3146	{
3147	if ((pCurLeaf->uEax & 0xff) > 1)
3148	{
3149	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
3150	pCurLeaf->uEax &= UINT32_C(0xffffff01);
3151	}
3152	uSubLeaf++;
3153	}
3154
3155	/* Cpuid 3:
3156	* Intel: EAX, EBX - reserved (transmeta uses these)
3157	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3158	* AMD: Reserved
3159	* VIA: Reserved
3160	* Safe to expose
3161	*/
3162	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3163	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3164	{
3165	uSubLeaf = 0;
3166	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3167	{
3168	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3169	if (pCpum->u8PortableCpuIdLevel > 0)
3170	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3171	uSubLeaf++;
3172	}
3173	}
3174
3175	/* Cpuid 4 + ECX:
3176	* Intel: Deterministic Cache Parameters Leaf.
3177	* AMD: Reserved
3178	* VIA: Reserved
3179	* Safe to expose, except for EAX:
3180	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3181	* Bits 31-26: Maximum number of processor cores in this physical package**
3182	* Note: These SMP values are constant regardless of ECX
3183	*/
3184	uSubLeaf = 0;
3185	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3186	{
3187	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3188	#ifdef VBOX_WITH_MULTI_CORE
3189	if ( pVM->cCpus > 1
3190	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3191	{
3192	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3193	/* One logical processor with possibly multiple cores. */
3194	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3195	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3196	}
3197	#endif
3198	uSubLeaf++;
3199	}
3200
3201	/* Cpuid 5: Monitor/mwait Leaf
3202	* Intel: ECX, EDX - reserved
3203	* EAX, EBX - Smallest and largest monitor line size
3204	* AMD: EDX - reserved
3205	* EAX, EBX - Smallest and largest monitor line size
3206	* ECX - extensions (ignored for now)
3207	* VIA: Reserved
3208	* Safe to expose
3209	*/
3210	uSubLeaf = 0;
3211	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3212	{
3213	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3214	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3215	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3216
3217	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3218	if (pConfig->enmMWaitExtensions)
3219	{
3220	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3221	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3222	it shall be part of our power management virtualization model */
3223	#if 0
3224	/* MWAIT sub C-states */
3225	pCurLeaf->uEdx =
3226	(0 << 0) /* 0 in C0 */ \|
3227	(2 << 4) /* 2 in C1 */ \|
3228	(2 << 8) /* 2 in C2 */ \|
3229	(2 << 12) /* 2 in C3 */ \|
3230	(0 << 16) /* 0 in C4 */
3231	;
3232	#endif
3233	}
3234	else
3235	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3236	uSubLeaf++;
3237	}
3238
3239	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3240	* Intel: Various stuff.
3241	* AMD: EAX, EBX, EDX - reserved.
3242	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3243	* present. Same as intel.
3244	* VIA: ??
3245	*
3246	* We clear everything here for now.
3247	*/
3248	cpumR3CpuIdZeroLeaf(pCpum, 6);
3249
3250	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3251	* EAX: Number of sub leaves.
3252	* EBX+ECX+EDX: Feature flags
3253	*
3254	* We only have documentation for one sub-leaf, so clear all other (no need
3255	* to remove them as such, just set them to zero).
3256	*
3257	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3258	* options may require adjusting (i.e. stripping what was enabled).
3259	*/
3260	uSubLeaf = 0;
3261	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3262	{
3263	switch (uSubLeaf)
3264	{
3265	case 0:
3266	{
3267	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3268	pCurLeaf->uEbx &= 0
3269	\| (pConfig->enmFsGsBase ? X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE : 0)
3270	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3271	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3272	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3273	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3274	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3275	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3276	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3277	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3278	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3279	\| (pConfig->enmInvpcid ? X86_CPUID_STEXT_FEATURE_EBX_INVPCID : 0)
3280	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3281	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3282	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3283	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3284	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3285	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3286	//\| RT_BIT(17) - reserved
3287	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3288	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3289	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3290	//\| RT_BIT(21) - reserved
3291	//\| RT_BIT(22) - reserved
3292	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3293	//\| RT_BIT(24) - reserved
3294	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3295	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3296	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3297	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3298	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3299	//\| RT_BIT(30) - reserved
3300	//\| RT_BIT(31) - reserved
3301	;
3302	pCurLeaf->uEcx &= 0
3303	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3304	;
3305	pCurLeaf->uEdx &= 0
3306	\| (pConfig->enmMdsClear ? X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR : 0)
3307	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3308	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3309	\| (pConfig->enmFlushCmdMsr ? X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD : 0)
3310	\| (pConfig->enmArchCapMsr ? X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP : 0)
3311	;
3312
3313	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3314	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3315	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3316	{
3317	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3318	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3319	}
3320
3321	if (pCpum->u8PortableCpuIdLevel > 0)
3322	{
3323	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3324	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3325	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3326	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3327	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3328	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3329	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3330	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3331	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3332	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3333	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3334	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3335	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3336	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3337	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3338	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
3339	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
3340	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
3341	}
3342
3343	/* Dependencies. */
3344	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
3345	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3346
3347	/* Force standard feature bits. */
3348	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3349	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3350	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3351	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3352	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3353	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3354	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3355	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3356	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3357	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3358	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3359	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
3360	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
3361	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3362	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3363	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
3364	break;
3365	}
3366
3367	default:
3368	/* Invalid index, all values are zero. */
3369	pCurLeaf->uEax = 0;
3370	pCurLeaf->uEbx = 0;
3371	pCurLeaf->uEcx = 0;
3372	pCurLeaf->uEdx = 0;
3373	break;
3374	}
3375	uSubLeaf++;
3376	}
3377
3378	/* Cpuid 8: Marked as reserved by Intel and AMD.
3379	* We zero this since we don't know what it may have been used for.
3380	*/
3381	cpumR3CpuIdZeroLeaf(pCpum, 8);
3382
3383	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3384	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3385	* EBX, ECX, EDX - reserved.
3386	* AMD: Reserved
3387	* VIA: ??
3388	*
3389	* We zero this.
3390	*/
3391	cpumR3CpuIdZeroLeaf(pCpum, 9);
3392
3393	/* Cpuid 0xa: Architectural Performance Monitor Features
3394	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3395	* EBX, ECX, EDX - reserved.
3396	* AMD: Reserved
3397	* VIA: ??
3398	*
3399	* We zero this, for now at least.
3400	*/
3401	cpumR3CpuIdZeroLeaf(pCpum, 10);
3402
3403	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3404	* Intel: EAX - APCI ID shift right for next level.
3405	* EBX - Factory configured cores/threads at this level.
3406	* ECX - Level number (same as input) and level type (1,2,0).
3407	* EDX - Extended initial APIC ID.
3408	* AMD: Reserved
3409	* VIA: ??
3410	*/
3411	uSubLeaf = 0;
3412	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3413	{
3414	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3415	{
3416	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3417	if (bLevelType == 1)
3418	{
3419	/* Thread level - we don't do threads at the moment. */
3420	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3421	pCurLeaf->uEbx = 1;
3422	}
3423	else if (bLevelType == 2)
3424	{
3425	/* Core level. */
3426	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3427	#ifdef VBOX_WITH_MULTI_CORE
3428	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3429	pCurLeaf->uEax++;
3430	#endif
3431	pCurLeaf->uEbx = pVM->cCpus;
3432	}
3433	else
3434	{
3435	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3436	pCurLeaf->uEax = 0;
3437	pCurLeaf->uEbx = 0;
3438	pCurLeaf->uEcx = 0;
3439	}
3440	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3441	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3442	}
3443	else
3444	{
3445	pCurLeaf->uEax = 0;
3446	pCurLeaf->uEbx = 0;
3447	pCurLeaf->uEcx = 0;
3448	pCurLeaf->uEdx = 0;
3449	}
3450	uSubLeaf++;
3451	}
3452
3453	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3454	* We zero this since we don't know what it may have been used for.
3455	*/
3456	cpumR3CpuIdZeroLeaf(pCpum, 12);
3457
3458	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3459	* ECX=0: EAX - Valid bits in XCR0[31:0].
3460	* EBX - Maximum state size as per current XCR0 value.
3461	* ECX - Maximum state size for all supported features.
3462	* EDX - Valid bits in XCR0[63:32].
3463	* ECX=1: EAX - Various X-features.
3464	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3465	* ECX - Valid bits in IA32_XSS[31:0].
3466	* EDX - Valid bits in IA32_XSS[63:32].
3467	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3468	* if the bit invalid all four registers are set to zero.
3469	* EAX - The state size for this feature.
3470	* EBX - The state byte offset of this feature.
3471	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3472	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3473	*
3474	* Clear them all as we don't currently implement extended CPU state.
3475	*/
3476	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3477	uint64_t fGuestXcr0Mask = 0;
3478	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3479	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3480	{
3481	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3482	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3483	fGuestXcr0Mask \|= XSAVE_C_YMM;
3484	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3485	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3486	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3487	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3488
3489	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3490	}
3491	pStdFeatureLeaf = NULL;
3492	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3493
3494	/* Work the sub-leaves. */
3495	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3496	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3497	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3498	{
3499	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3500	if (pCurLeaf)
3501	{
3502	if (fGuestXcr0Mask)
3503	{
3504	switch (uSubLeaf)
3505	{
3506	case 0:
3507	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3508	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3509	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3510	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3511	VERR_CPUM_IPE_1);
3512	cbXSaveMaxActual = pCurLeaf->uEcx;
3513	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3514	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3515	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3516	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3517	VERR_CPUM_IPE_2);
3518	continue;
3519	case 1:
3520	pCurLeaf->uEax &= 0;
3521	pCurLeaf->uEcx &= 0;
3522	pCurLeaf->uEdx &= 0;
3523	/** @todo what about checking ebx? */
3524	continue;
3525	default:
3526	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3527	{
3528	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3529	&& pCurLeaf->uEax > 0
3530	&& pCurLeaf->uEbx < cbXSaveMaxActual
3531	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3532	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3533	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3534	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3535	VERR_CPUM_IPE_2);
3536	AssertLogRel(!(pCurLeaf->uEcx & 1));
3537	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3538	pCurLeaf->uEdx = 0; /* it's reserved... */
3539	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3540	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3541	continue;
3542	}
3543	break;
3544	}
3545	}
3546
3547	/* Clear the leaf. */
3548	pCurLeaf->uEax = 0;
3549	pCurLeaf->uEbx = 0;
3550	pCurLeaf->uEcx = 0;
3551	pCurLeaf->uEdx = 0;
3552	}
3553	}
3554
3555	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3556	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3557	{
3558	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3559	if (pCurLeaf)
3560	{
3561	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3562	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3563	pCurLeaf->uEbx = cbXSaveMaxReport;
3564	pCurLeaf->uEcx = cbXSaveMaxReport;
3565	}
3566	}
3567
3568	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3569	* We zero this since we don't know what it may have been used for.
3570	*/
3571	cpumR3CpuIdZeroLeaf(pCpum, 14);
3572
3573	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3574	* also known as Intel Resource Director Technology (RDT) Monitoring
3575	* We zero this as we don't currently virtualize PQM.
3576	*/
3577	cpumR3CpuIdZeroLeaf(pCpum, 15);
3578
3579	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3580	* also known as Intel Resource Director Technology (RDT) Allocation
3581	* We zero this as we don't currently virtualize PQE.
3582	*/
3583	cpumR3CpuIdZeroLeaf(pCpum, 16);
3584
3585	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3586	* We zero this since we don't know what it may have been used for.
3587	*/
3588	cpumR3CpuIdZeroLeaf(pCpum, 17);
3589
3590	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3591	* We zero this as we don't currently virtualize this.
3592	*/
3593	cpumR3CpuIdZeroLeaf(pCpum, 18);
3594
3595	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3596	* We zero this since we don't know what it may have been used for.
3597	*/
3598	cpumR3CpuIdZeroLeaf(pCpum, 19);
3599
3600	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3601	* We zero this as we don't currently virtualize this.
3602	*/
3603	cpumR3CpuIdZeroLeaf(pCpum, 20);
3604
3605	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3606	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3607	* EAX - denominator (unsigned).
3608	* EBX - numerator (unsigned).
3609	* ECX, EDX - reserved.
3610	* AMD: Reserved / undefined / not implemented.
3611	* VIA: Reserved / undefined / not implemented.
3612	* We zero this as we don't currently virtualize this.
3613	*/
3614	cpumR3CpuIdZeroLeaf(pCpum, 21);
3615
3616	/* Cpuid 0x16: Processor frequency info
3617	* Intel: EAX - Core base frequency in MHz.
3618	* EBX - Core maximum frequency in MHz.
3619	* ECX - Bus (reference) frequency in MHz.
3620	* EDX - Reserved.
3621	* AMD: Reserved / undefined / not implemented.
3622	* VIA: Reserved / undefined / not implemented.
3623	* We zero this as we don't currently virtualize this.
3624	*/
3625	cpumR3CpuIdZeroLeaf(pCpum, 22);
3626
3627	/* Cpuid 0x17..0x10000000: Unknown.
3628	* We don't know these and what they mean, so remove them. */
3629	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3630	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3631
3632
3633	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3634	* We remove all these as we're a hypervisor and must provide our own.
3635	*/
3636	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3637	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3638
3639
3640	/* Cpuid 0x80000000 is harmless. */
3641
3642	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3643
3644	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3645
3646	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3647	* Safe to pass on to the guest.
3648	*
3649	* AMD: 0x800000005 L1 cache information
3650	* 0x800000006 L2/L3 cache information
3651	* Intel: 0x800000005 reserved
3652	* 0x800000006 L2 cache information
3653	* VIA: 0x800000005 TLB and L1 cache information
3654	* 0x800000006 L2 cache information
3655	*/
3656
3657	/* Cpuid 0x800000007: Advanced Power Management Information.
3658	* AMD: EAX: Processor feedback capabilities.
3659	* EBX: RAS capabilites.
3660	* ECX: Advanced power monitoring interface.
3661	* EDX: Enhanced power management capabilities.
3662	* Intel: EAX, EBX, ECX - reserved.
3663	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3664	* VIA: Reserved
3665	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3666	*/
3667	uSubLeaf = 0;
3668	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3669	{
3670	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3671	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3672	{
3673	/*
3674	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3675	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3676	* bit is now configurable.
3677	*/
3678	pCurLeaf->uEdx &= 0
3679	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3680	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3681	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3682	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3683	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3684	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3685	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3686	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3687	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3688	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3689	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3690	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3691	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3692	\| 0;
3693	}
3694	else
3695	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3696	if (!pConfig->fInvariantTsc)
3697	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3698	uSubLeaf++;
3699	}
3700
3701	/* Cpuid 0x80000008:
3702	* AMD: EBX, EDX - reserved
3703	* EAX: Virtual/Physical/Guest address Size
3704	* ECX: Number of cores + APICIdCoreIdSize
3705	* Intel: EAX: Virtual/Physical address Size
3706	* EBX, ECX, EDX - reserved
3707	* VIA: EAX: Virtual/Physical address Size
3708	* EBX, ECX, EDX - reserved
3709	*
3710	* We only expose the virtual+pysical address size to the guest atm.
3711	* On AMD we set the core count, but not the apic id stuff as we're
3712	* currently not doing the apic id assignments in a complatible manner.
3713	*/
3714	uSubLeaf = 0;
3715	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3716	{
3717	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3718	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3719	pCurLeaf->uEdx = 0; /* reserved */
3720
3721	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3722	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3723	pCurLeaf->uEcx = 0;
3724	#ifdef VBOX_WITH_MULTI_CORE
3725	if ( pVM->cCpus > 1
3726	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3727	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3728	#endif
3729	uSubLeaf++;
3730	}
3731
3732	/* Cpuid 0x80000009: Reserved
3733	* We zero this since we don't know what it may have been used for.
3734	*/
3735	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3736
3737	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
3738	* AMD: EAX - SVM revision.
3739	* EBX - Number of ASIDs.
3740	* ECX - Reserved.
3741	* EDX - SVM Feature identification.
3742	*/
3743	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3744	if ( pExtFeatureLeaf
3745	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
3746	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3747	{
3748	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3749	if (pSvmFeatureLeaf)
3750	{
3751	pSvmFeatureLeaf->uEax = 0x1;
3752	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3753	pSvmFeatureLeaf->uEcx = 0;
3754	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3755	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3756	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3757	}
3758	else
3759	{
3760	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
3761	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3762	}
3763	}
3764
3765	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3766	* We clear these as we don't know what purpose they might have. */
3767	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3768	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3769
3770	/* Cpuid 0x80000019: TLB configuration
3771	* Seems to be harmless, pass them thru as is. */
3772
3773	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3774	* Strip anything we don't know what is or addresses feature we don't implement. */
3775	uSubLeaf = 0;
3776	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3777	{
3778	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3779	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3780	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3781	;
3782	pCurLeaf->uEbx = 0; /* reserved */
3783	pCurLeaf->uEcx = 0; /* reserved */
3784	pCurLeaf->uEdx = 0; /* reserved */
3785	uSubLeaf++;
3786	}
3787
3788	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3789	* Clear this as we don't currently virtualize this feature. */
3790	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3791
3792	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3793	* Clear this as we don't currently virtualize this feature. */
3794	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3795
3796	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3797	* We need to sanitize the cores per cache (EAX[25:14]).
3798	*
3799	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3800	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3801	* slightly different meaning.
3802	*/
3803	uSubLeaf = 0;
3804	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3805	{
3806	#ifdef VBOX_WITH_MULTI_CORE
3807	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3808	if (cCores > pVM->cCpus)
3809	cCores = pVM->cCpus;
3810	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3811	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3812	#else
3813	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3814	#endif
3815	uSubLeaf++;
3816	}
3817
3818	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3819	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3820	* setup, we have one compute unit with all the cores in it. Single node.
3821	*/
3822	uSubLeaf = 0;
3823	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3824	{
3825	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3826	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3827	{
3828	#ifdef VBOX_WITH_MULTI_CORE
3829	pCurLeaf->uEbx = pVM->cCpus < 0x100
3830	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3831	#else
3832	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3833	#endif
3834	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3835	}
3836	else
3837	{
3838	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3839	pCurLeaf->uEbx = 0; /* Reserved. */
3840	pCurLeaf->uEcx = 0; /* Reserved. */
3841	}
3842	pCurLeaf->uEdx = 0; /* Reserved. */
3843	uSubLeaf++;
3844	}
3845
3846	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3847	* We don't know these and what they mean, so remove them. */
3848	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3849	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3850
3851	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3852	* Just pass it thru for now. */
3853
3854	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3855	* Just pass it thru for now. */
3856
3857	/* Cpuid 0xc0000000: Centaur stuff.
3858	* Harmless, pass it thru. */
3859
3860	/* Cpuid 0xc0000001: Centaur features.
3861	* VIA: EAX - Family, model, stepping.
3862	* EDX - Centaur extended feature flags. Nothing interesting, except may
3863	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3864	* EBX, ECX - reserved.
3865	* We keep EAX but strips the rest.
3866	*/
3867	uSubLeaf = 0;
3868	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3869	{
3870	pCurLeaf->uEbx = 0;
3871	pCurLeaf->uEcx = 0;
3872	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3873	uSubLeaf++;
3874	}
3875
3876	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3877	* We only have fixed stale values, but should be harmless. */
3878
3879	/* Cpuid 0xc0000003: Reserved.
3880	* We zero this since we don't know what it may have been used for.
3881	*/
3882	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3883
3884	/* Cpuid 0xc0000004: Centaur Performance Info.
3885	* We only have fixed stale values, but should be harmless. */
3886
3887
3888	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3889	* We don't know these and what they mean, so remove them. */
3890	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3891	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3892
3893	return VINF_SUCCESS;
3894	#undef PORTABLE_DISABLE_FEATURE_BIT
3895	#undef PORTABLE_CLEAR_BITS_WHEN
3896	}
3897
3898
3899	/**
3900	* Reads a value in /CPUM/IsaExts/ node.
3901	*
3902	* @returns VBox status code (error message raised).
3903	* @param pVM The cross context VM structure. (For errors.)
3904	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3905	* @param pszValueName The value / extension name.
3906	* @param penmValue Where to return the choice.
3907	* @param enmDefault The default choice.
3908	*/
3909	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3910	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3911	{
3912	/*
3913	* Try integer encoding first.
3914	*/
3915	uint64_t uValue;
3916	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3917	if (RT_SUCCESS(rc))
3918	switch (uValue)
3919	{
3920	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3921	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3922	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3923	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3924	default:
3925	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3926	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3927	pszValueName, uValue);
3928	}
3929	/*
3930	* If missing, use default.
3931	*/
3932	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3933	*penmValue = enmDefault;
3934	else
3935	{
3936	if (rc == VERR_CFGM_NOT_INTEGER)
3937	{
3938	/*
3939	* Not an integer, try read it as a string.
3940	*/
3941	char szValue[32];
3942	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3943	if (RT_SUCCESS(rc))
3944	{
3945	RTStrToLower(szValue);
3946	size_t cchValue = strlen(szValue);
3947	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3948	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3949	*penmValue = CPUMISAEXTCFG_DISABLED;
3950	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3951	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3952	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3953	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3954	else if (EQ("portable"))
3955	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3956	else if (EQ("default") \|\| EQ("def"))
3957	*penmValue = enmDefault;
3958	else
3959	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3960	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3961	pszValueName, uValue);
3962	#undef EQ
3963	}
3964	}
3965	if (RT_FAILURE(rc))
3966	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3967	}
3968	return VINF_SUCCESS;
3969	}
3970
3971
3972	/**
3973	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3974	*
3975	* @returns VBox status code (error message raised).
3976	* @param pVM The cross context VM structure. (For errors.)
3977	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3978	* @param pszValueName The value / extension name.
3979	* @param penmValue Where to return the choice.
3980	* @param enmDefault The default choice.
3981	* @param fAllowed Allowed choice. Applied both to the result and to
3982	* the default value.
3983	*/
3984	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3985	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3986	{
3987	int rc;
3988	if (fAllowed)
3989	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3990	else
3991	{
3992	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3993	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3994	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3995	*penmValue = CPUMISAEXTCFG_DISABLED;
3996	}
3997	return rc;
3998	}
3999
4000
4001	/**
4002	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
4003	*
4004	* @returns VBox status code (error message raised).
4005	* @param pVM The cross context VM structure. (For errors.)
4006	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4007	* @param pCpumCfg The /CPUM node (can be NULL).
4008	* @param pszValueName The value / extension name.
4009	* @param penmValue Where to return the choice.
4010	* @param enmDefault The default choice.
4011	*/
4012	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
4013	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
4014	{
4015	if (CFGMR3Exists(pCpumCfg, pszValueName))
4016	{
4017	if (!CFGMR3Exists(pIsaExts, pszValueName))
4018	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
4019	else
4020	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
4021	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
4022	pszValueName, pszValueName);
4023
4024	bool fLegacy;
4025	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
4026	if (RT_SUCCESS(rc))
4027	{
4028	*penmValue = fLegacy;
4029	return VINF_SUCCESS;
4030	}
4031	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
4032	}
4033
4034	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4035	}
4036
4037
4038	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
4039	{
4040	int rc;
4041
4042	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
4043	* When non-zero CPUID features that could cause portability issues will be
4044	* stripped. The higher the value the more features gets stripped. Higher
4045	* values should only be used when older CPUs are involved since it may
4046	* harm performance and maybe also cause problems with specific guests. */
4047	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
4048	AssertLogRelRCReturn(rc, rc);
4049
4050	/** @cfgm{/CPUM/GuestCpuName, string}
4051	* The name of the CPU we're to emulate. The default is the host CPU.
4052	* Note! CPUs other than "host" one is currently unsupported. */
4053	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
4054	AssertLogRelRCReturn(rc, rc);
4055
4056	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
4057	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
4058	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
4059	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
4060	*/
4061	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
4062	AssertLogRelRCReturn(rc, rc);
4063
4064	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
4065	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
4066	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
4067	* 64-bit linux guests which assume the presence of AMD performance counters
4068	* that we do not virtualize.
4069	*/
4070	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
4071	AssertLogRelRCReturn(rc, rc);
4072
4073	/** @cfgm{/CPUM/ForceVme, boolean, false}
4074	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
4075	* By default the flag is passed thru as is from the host CPU, except
4076	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
4077	* guests and DOS boxes in general.
4078	*/
4079	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
4080	AssertLogRelRCReturn(rc, rc);
4081
4082	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
4083	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
4084	* probably going to be a temporary hack, so don't depend on this.
4085	* The 1st byte of the value is the stepping, the 2nd byte value is the model
4086	* number and the 3rd byte value is the family, and the 4th value must be zero.
4087	*/
4088	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
4089	AssertLogRelRCReturn(rc, rc);
4090
4091	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
4092	* The last standard leaf to keep. The actual last value that is stored in EAX
4093	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
4094	* removed. (This works independently of and differently from NT4LeafLimit.)
4095	* The default is usually set to what we're able to reasonably sanitize.
4096	*/
4097	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
4098	AssertLogRelRCReturn(rc, rc);
4099
4100	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
4101	* The last extended leaf to keep. The actual last value that is stored in EAX
4102	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
4103	* leaf are removed. The default is set to what we're able to sanitize.
4104	*/
4105	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
4106	AssertLogRelRCReturn(rc, rc);
4107
4108	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
4109	* The last extended leaf to keep. The actual last value that is stored in EAX
4110	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
4111	* leaf are removed. The default is set to what we're able to sanitize.
4112	*/
4113	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
4114	AssertLogRelRCReturn(rc, rc);
4115
4116	bool fQueryNestedHwvirt = false;
4117	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4118	fQueryNestedHwvirt \|= RT_BOOL(pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD);
4119	#endif
4120	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4121	fQueryNestedHwvirt \|= RT_BOOL( pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
4122	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA);
4123	#endif
4124	if (fQueryNestedHwvirt)
4125	{
4126	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
4127	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
4128	* The default is false, and when enabled requires a 64-bit CPU with support for
4129	* nested-paging and AMD-V or unrestricted guest mode.
4130	*/
4131	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
4132	AssertLogRelRCReturn(rc, rc);
4133	if ( pConfig->fNestedHWVirt
4134	&& !fNestedPagingAndFullGuestExec)
4135	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4136	"Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
4137
4138	/** @todo Think about enabling this later with NEM/KVM. */
4139	if ( pConfig->fNestedHWVirt
4140	&& VM_IS_NEM_ENABLED(pVM))
4141	{
4142	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
4143	pConfig->fNestedHWVirt = false;
4144	}
4145
4146	#if HC_ARCH_BITS == 32
4147	/* We don't support nested hardware virtualization on 32-bit hosts. */
4148	if (pConfig->fNestedHWVirt)
4149	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4150	"Cannot enable nested VT-x/AMD-V on a 32-bit host\n");
4151	#endif
4152	}
4153
4154	/*
4155	* Instruction Set Architecture (ISA) Extensions.
4156	*/
4157	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
4158	if (pIsaExts)
4159	{
4160	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
4161	"CMPXCHG16B"
4162	"\|MONITOR"
4163	"\|MWaitExtensions"
4164	"\|SSE4.1"
4165	"\|SSE4.2"
4166	"\|XSAVE"
4167	"\|AVX"
4168	"\|AVX2"
4169	"\|AESNI"
4170	"\|PCLMUL"
4171	"\|POPCNT"
4172	"\|MOVBE"
4173	"\|RDRAND"
4174	"\|RDSEED"
4175	"\|CLFLUSHOPT"
4176	"\|FSGSBASE"
4177	"\|PCID"
4178	"\|INVPCID"
4179	"\|FlushCmdMsr"
4180	"\|ABM"
4181	"\|SSE4A"
4182	"\|MISALNSSE"
4183	"\|3DNOWPRF"
4184	"\|AXMMX"
4185	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
4186	if (RT_FAILURE(rc))
4187	return rc;
4188	}
4189
4190	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
4191	* Expose CMPXCHG16B to the guest if supported by the host. For the time
4192	* being the default is to only do this for VMs with nested paging and AMD-V or
4193	* unrestricted guest mode.
4194	*/
4195	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
4196	AssertLogRelRCReturn(rc, rc);
4197
4198	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4199	* Expose MONITOR/MWAIT instructions to the guest.
4200	*/
4201	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4202	AssertLogRelRCReturn(rc, rc);
4203
4204	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4205	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4206	* break on interrupt feature (bit 1).
4207	*/
4208	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4209	AssertLogRelRCReturn(rc, rc);
4210
4211	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4212	* Expose SSE4.1 to the guest if available.
4213	*/
4214	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4215	AssertLogRelRCReturn(rc, rc);
4216
4217	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4218	* Expose SSE4.2 to the guest if available.
4219	*/
4220	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4221	AssertLogRelRCReturn(rc, rc);
4222
4223	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4224	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4225	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
4226	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
4227	&& ( !HMIsLongModeAllowed(pVM)
4228	\|\| NEMHCIsLongModeAllowed(pVM))
4229	#endif
4230	;
4231	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4232
4233	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4234	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4235	* default is to only expose this to VMs with nested paging and AMD-V or
4236	* unrestricted guest execution mode. Not possible to force this one without
4237	* host support at the moment.
4238	*/
4239	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4240	fMayHaveXSave /fAllowed/);
4241	AssertLogRelRCReturn(rc, rc);
4242
4243	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4244	* Expose the AVX instruction set extensions to the guest if available and
4245	* XSAVE is exposed too. For the time being the default is to only expose this
4246	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4247	*/
4248	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4249	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4250	AssertLogRelRCReturn(rc, rc);
4251
4252	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4253	* Expose the AVX2 instruction set extensions to the guest if available and
4254	* XSAVE is exposed too. For the time being the default is to only expose this
4255	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4256	*/
4257	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4258	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4259	AssertLogRelRCReturn(rc, rc);
4260
4261	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4262	* Whether to expose the AES instructions to the guest. For the time being the
4263	* default is to only do this for VMs with nested paging and AMD-V or
4264	* unrestricted guest mode.
4265	*/
4266	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4267	AssertLogRelRCReturn(rc, rc);
4268
4269	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4270	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4271	* being the default is to only do this for VMs with nested paging and AMD-V or
4272	* unrestricted guest mode.
4273	*/
4274	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4275	AssertLogRelRCReturn(rc, rc);
4276
4277	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4278	* Whether to expose the POPCNT instructions to the guest. For the time
4279	* being the default is to only do this for VMs with nested paging and AMD-V or
4280	* unrestricted guest mode.
4281	*/
4282	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4283	AssertLogRelRCReturn(rc, rc);
4284
4285	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4286	* Whether to expose the MOVBE instructions to the guest. For the time
4287	* being the default is to only do this for VMs with nested paging and AMD-V or
4288	* unrestricted guest mode.
4289	*/
4290	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4291	AssertLogRelRCReturn(rc, rc);
4292
4293	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4294	* Whether to expose the RDRAND instructions to the guest. For the time being
4295	* the default is to only do this for VMs with nested paging and AMD-V or
4296	* unrestricted guest mode.
4297	*/
4298	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4299	AssertLogRelRCReturn(rc, rc);
4300
4301	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4302	* Whether to expose the RDSEED instructions to the guest. For the time being
4303	* the default is to only do this for VMs with nested paging and AMD-V or
4304	* unrestricted guest mode.
4305	*/
4306	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4307	AssertLogRelRCReturn(rc, rc);
4308
4309	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4310	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4311	* being the default is to only do this for VMs with nested paging and AMD-V or
4312	* unrestricted guest mode.
4313	*/
4314	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4315	AssertLogRelRCReturn(rc, rc);
4316
4317	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4318	* Whether to expose the read/write FSGSBASE instructions to the guest.
4319	*/
4320	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4321	AssertLogRelRCReturn(rc, rc);
4322
4323	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4324	* Whether to expose the PCID feature to the guest.
4325	*/
4326	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4327	AssertLogRelRCReturn(rc, rc);
4328
4329	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4330	* Whether to expose the INVPCID instruction to the guest.
4331	*/
4332	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4333	AssertLogRelRCReturn(rc, rc);
4334
4335	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
4336	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
4337	*/
4338	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4339	AssertLogRelRCReturn(rc, rc);
4340
4341	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
4342	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
4343	* the guest. Requires FlushCmdMsr to be present too.
4344	*/
4345	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4346	AssertLogRelRCReturn(rc, rc);
4347
4348	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
4349	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
4350	*/
4351	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4352	AssertLogRelRCReturn(rc, rc);
4353
4354
4355	/* AMD: */
4356
4357	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4358	* Whether to expose the AMD ABM instructions to the guest. For the time
4359	* being the default is to only do this for VMs with nested paging and AMD-V or
4360	* unrestricted guest mode.
4361	*/
4362	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4363	AssertLogRelRCReturn(rc, rc);
4364
4365	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4366	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4367	* being the default is to only do this for VMs with nested paging and AMD-V or
4368	* unrestricted guest mode.
4369	*/
4370	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4371	AssertLogRelRCReturn(rc, rc);
4372
4373	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4374	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4375	* the time being the default is to only do this for VMs with nested paging and
4376	* AMD-V or unrestricted guest mode.
4377	*/
4378	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4379	AssertLogRelRCReturn(rc, rc);
4380
4381	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4382	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4383	* For the time being the default is to only do this for VMs with nested paging
4384	* and AMD-V or unrestricted guest mode.
4385	*/
4386	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4387	AssertLogRelRCReturn(rc, rc);
4388
4389	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4390	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4391	* the default is to only do this for VMs with nested paging and AMD-V or
4392	* unrestricted guest mode.
4393	*/
4394	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4395	AssertLogRelRCReturn(rc, rc);
4396
4397	return VINF_SUCCESS;
4398	}
4399
4400
4401	/**
4402	* Initializes the emulated CPU's CPUID & MSR information.
4403	*
4404	* @returns VBox status code.
4405	* @param pVM The cross context VM structure.
4406	* @param pHostMsrs Pointer to the host MSRs.
4407	*/
4408	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
4409	{
4410	Assert(pHostMsrs);
4411
4412	PCPUM pCpum = &pVM->cpum.s;
4413	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4414
4415	/*
4416	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4417	* on construction and manage everything from here on.
4418	*/
4419	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
4420	pVM->aCpus[iCpu].cpum.s.fCpuIdApicFeatureVisible = true;
4421
4422	/*
4423	* Read the configuration.
4424	*/
4425	CPUMCPUIDCONFIG Config;
4426	RT_ZERO(Config);
4427
4428	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4429	AssertRCReturn(rc, rc);
4430
4431	/*
4432	* Get the guest CPU data from the database and/or the host.
4433	*
4434	* The CPUID and MSRs are currently living on the regular heap to avoid
4435	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4436	* API for the hyper heap). This means special cleanup considerations.
4437	*/
4438	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4439	if (RT_FAILURE(rc))
4440	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4441	? VMSetError(pVM, rc, RT_SRC_POS,
4442	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4443	: rc;
4444
4445	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4446	{
4447	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4448	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4449	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4450	}
4451	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4452
4453	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4454	* Overrides the guest MSRs.
4455	*/
4456	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4457
4458	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4459	* Overrides the CPUID leaf values (from the host CPU usually) used for
4460	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4461	* values when moving a VM to a different machine. Another use is restricting
4462	* (or extending) the feature set exposed to the guest. */
4463	if (RT_SUCCESS(rc))
4464	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4465
4466	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4467	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4468	"Found unsupported configuration node '/CPUM/CPUID/'. "
4469	"Please use IMachine::setCPUIDLeaf() instead.");
4470
4471	CPUMMSRS GuestMsrs;
4472	RT_ZERO(GuestMsrs);
4473
4474	/*
4475	* Pre-explode the CPUID info.
4476	*/
4477	if (RT_SUCCESS(rc))
4478	{
4479	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
4480	&pCpum->GuestFeatures);
4481	}
4482
4483	/*
4484	* Sanitize the cpuid information passed on to the guest.
4485	*/
4486	if (RT_SUCCESS(rc))
4487	{
4488	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4489	if (RT_SUCCESS(rc))
4490	{
4491	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4492	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4493	}
4494	}
4495
4496	/*
4497	* Setup MSRs introduced in microcode updates or that are otherwise not in
4498	* the CPU profile, but are advertised in the CPUID info we just sanitized.
4499	*/
4500	if (RT_SUCCESS(rc))
4501	rc = cpumR3MsrReconcileWithCpuId(pVM);
4502	/*
4503	* MSR fudging.
4504	*/
4505	if (RT_SUCCESS(rc))
4506	{
4507	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4508	* Fudges some common MSRs if not present in the selected CPU database entry.
4509	* This is for trying to keep VMs running when moved between different hosts
4510	* and different CPU vendors. */
4511	bool fEnable;
4512	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4513	if (RT_SUCCESS(rc) && fEnable)
4514	{
4515	rc = cpumR3MsrApplyFudge(pVM);
4516	AssertLogRelRC(rc);
4517	}
4518	}
4519	if (RT_SUCCESS(rc))
4520	{
4521	/*
4522	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4523	* guest CPU features again.
4524	*/
4525	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4526	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4527	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
4528	RTMemFree(pvFree);
4529
4530	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4531	int rc2 = MMHyperDupMem(pVM, pvFree,
4532	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4533	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4534	RTMemFree(pvFree);
4535	AssertLogRelRCReturn(rc1, rc1);
4536	AssertLogRelRCReturn(rc2, rc2);
4537
4538	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4539	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4540
4541	/*
4542	* Finally, initialize guest VMX MSRs.
4543	*
4544	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
4545	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
4546	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
4547	*/
4548	if (pVM->cpum.s.GuestFeatures.fVmx)
4549	{
4550	Assert(Config.fNestedHWVirt);
4551	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
4552
4553	/* Copy MSRs to all VCPUs */
4554	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
4555	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4556	{
4557	PVMCPU pVCpu = &pVM->aCpus[idCpu];
4558	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
4559	}
4560	}
4561
4562	/*
4563	* Some more configuration that we're applying at the end of everything
4564	* via the CPUMSetGuestCpuIdFeature API.
4565	*/
4566
4567	/* Check if PAE was explicitely enabled by the user. */
4568	bool fEnable;
4569	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4570	AssertRCReturn(rc, rc);
4571	if (fEnable)
4572	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4573
4574	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4575	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4576	AssertRCReturn(rc, rc);
4577	if (fEnable)
4578	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4579
4580	/* Check if speculation control is enabled. */
4581	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4582	AssertRCReturn(rc, rc);
4583	if (fEnable)
4584	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4585
4586	return VINF_SUCCESS;
4587	}
4588
4589	/*
4590	* Failed before switching to hyper heap.
4591	*/
4592	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4593	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4594	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4595	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4596	return rc;
4597	}
4598
4599
4600	/**
4601	* Sets a CPUID feature bit during VM initialization.
4602	*
4603	* Since the CPUID feature bits are generally related to CPU features, other
4604	* CPUM configuration like MSRs can also be modified by calls to this API.
4605	*
4606	* @param pVM The cross context VM structure.
4607	* @param enmFeature The feature to set.
4608	*/
4609	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4610	{
4611	PCPUMCPUIDLEAF pLeaf;
4612	PCPUMMSRRANGE pMsrRange;
4613
4614	switch (enmFeature)
4615	{
4616	/*
4617	* Set the APIC bit in both feature masks.
4618	*/
4619	case CPUMCPUIDFEATURE_APIC:
4620	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4621	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4622	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4623
4624	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4625	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4626	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4627
4628	pVM->cpum.s.GuestFeatures.fApic = 1;
4629
4630	/* Make sure we've got the APICBASE MSR present. */
4631	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4632	if (!pMsrRange)
4633	{
4634	static CPUMMSRRANGE const s_ApicBase =
4635	{
4636	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4637	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4638	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4639	/.szName = / "IA32_APIC_BASE"
4640	};
4641	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4642	AssertLogRelRC(rc);
4643	}
4644
4645	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4646	break;
4647
4648	/*
4649	* Set the x2APIC bit in the standard feature mask.
4650	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4651	*/
4652	case CPUMCPUIDFEATURE_X2APIC:
4653	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4654	if (pLeaf)
4655	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4656	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4657
4658	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4659	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4660	if (pMsrRange)
4661	{
4662	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4663	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4664	}
4665
4666	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4667	break;
4668
4669	/*
4670	* Set the sysenter/sysexit bit in the standard feature mask.
4671	* Assumes the caller knows what it's doing! (host must support these)
4672	*/
4673	case CPUMCPUIDFEATURE_SEP:
4674	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4675	{
4676	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4677	return;
4678	}
4679
4680	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4681	if (pLeaf)
4682	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4683	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4684	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4685	break;
4686
4687	/*
4688	* Set the syscall/sysret bit in the extended feature mask.
4689	* Assumes the caller knows what it's doing! (host must support these)
4690	*/
4691	case CPUMCPUIDFEATURE_SYSCALL:
4692	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4693	if ( !pLeaf
4694	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4695	{
4696	#if HC_ARCH_BITS == 32
4697	/* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit
4698	mode by Intel, even when the cpu is capable of doing so in
4699	64-bit mode. Long mode requires syscall support. */
4700	if (!pVM->cpum.s.HostFeatures.fLongMode)
4701	#endif
4702	{
4703	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4704	return;
4705	}
4706	}
4707
4708	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4709	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4710	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4711	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4712	break;
4713
4714	/*
4715	* Set the PAE bit in both feature masks.
4716	* Assumes the caller knows what it's doing! (host must support these)
4717	*/
4718	case CPUMCPUIDFEATURE_PAE:
4719	if (!pVM->cpum.s.HostFeatures.fPae)
4720	{
4721	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4722	return;
4723	}
4724
4725	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4726	if (pLeaf)
4727	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4728
4729	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4730	if ( pLeaf
4731	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4732	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4733
4734	pVM->cpum.s.GuestFeatures.fPae = 1;
4735	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4736	break;
4737
4738	/*
4739	* Set the LONG MODE bit in the extended feature mask.
4740	* Assumes the caller knows what it's doing! (host must support these)
4741	*/
4742	case CPUMCPUIDFEATURE_LONG_MODE:
4743	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4744	if ( !pLeaf
4745	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4746	{
4747	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4748	return;
4749	}
4750
4751	/* Valid for both Intel and AMD. */
4752	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4753	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4754	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4755	break;
4756
4757	/*
4758	* Set the NX/XD bit in the extended feature mask.
4759	* Assumes the caller knows what it's doing! (host must support these)
4760	*/
4761	case CPUMCPUIDFEATURE_NX:
4762	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4763	if ( !pLeaf
4764	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4765	{
4766	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4767	return;
4768	}
4769
4770	/* Valid for both Intel and AMD. */
4771	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4772	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4773	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4774	break;
4775
4776
4777	/*
4778	* Set the LAHF/SAHF support in 64-bit mode.
4779	* Assumes the caller knows what it's doing! (host must support this)
4780	*/
4781	case CPUMCPUIDFEATURE_LAHF:
4782	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4783	if ( !pLeaf
4784	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4785	{
4786	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4787	return;
4788	}
4789
4790	/* Valid for both Intel and AMD. */
4791	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4792	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4793	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4794	break;
4795
4796	/*
4797	* Set the page attribute table bit. This is alternative page level
4798	* cache control that doesn't much matter when everything is
4799	* virtualized, though it may when passing thru device memory.
4800	*/
4801	case CPUMCPUIDFEATURE_PAT:
4802	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4803	if (pLeaf)
4804	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4805
4806	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4807	if ( pLeaf
4808	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4809	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4810
4811	pVM->cpum.s.GuestFeatures.fPat = 1;
4812	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4813	break;
4814
4815	/*
4816	* Set the RDTSCP support bit.
4817	* Assumes the caller knows what it's doing! (host must support this)
4818	*/
4819	case CPUMCPUIDFEATURE_RDTSCP:
4820	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4821	if ( !pLeaf
4822	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4823	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4824	{
4825	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4826	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4827	return;
4828	}
4829
4830	/* Valid for both Intel and AMD. */
4831	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4832	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4833	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4834	break;
4835
4836	/*
4837	* Set the Hypervisor Present bit in the standard feature mask.
4838	*/
4839	case CPUMCPUIDFEATURE_HVP:
4840	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4841	if (pLeaf)
4842	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4843	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4844	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4845	break;
4846
4847	/*
4848	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4849	* This currently includes the Present bit and MWAITBREAK bit as well.
4850	*/
4851	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4852	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4853	if ( !pLeaf
4854	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4855	{
4856	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4857	return;
4858	}
4859
4860	/* Valid for both Intel and AMD. */
4861	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4862	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4863	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4864	break;
4865
4866	/*
4867	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
4868	* on Intel CPUs, and different on AMDs.
4869	*/
4870	case CPUMCPUIDFEATURE_SPEC_CTRL:
4871	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4872	{
4873	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4874	if ( !pLeaf
4875	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
4876	{
4877	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4878	return;
4879	}
4880
4881	/* The feature can be enabled. Let's see what we can actually do. */
4882	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4883
4884	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4885	if (pVM->cpum.s.HostFeatures.fIbrs)
4886	{
4887	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4888	pVM->cpum.s.GuestFeatures.fIbrs = 1;
4889	if (pVM->cpum.s.HostFeatures.fStibp)
4890	{
4891	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4892	pVM->cpum.s.GuestFeatures.fStibp = 1;
4893	}
4894
4895	/* Make sure we have the speculation control MSR... */
4896	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4897	if (!pMsrRange)
4898	{
4899	static CPUMMSRRANGE const s_SpecCtrl =
4900	{
4901	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
4902	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
4903	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4904	/.szName = / "IA32_SPEC_CTRL"
4905	};
4906	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4907	AssertLogRelRC(rc);
4908	}
4909
4910	/* ... and the predictor command MSR. */
4911	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
4912	if (!pMsrRange)
4913	{
4914	/** @todo incorrect fWrGpMask. */
4915	static CPUMMSRRANGE const s_SpecCtrl =
4916	{
4917	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
4918	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
4919	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4920	/.szName = / "IA32_PRED_CMD"
4921	};
4922	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4923	AssertLogRelRC(rc);
4924	}
4925
4926	}
4927
4928	if (pVM->cpum.s.HostFeatures.fArchCap)
4929	{
4930	/* Install the architectural capabilities MSR. */
4931	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
4932	if (!pMsrRange)
4933	{
4934	static CPUMMSRRANGE const s_ArchCaps =
4935	{
4936	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
4937	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
4938	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
4939	/.szName = / "IA32_ARCH_CAPABILITIES"
4940	};
4941	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
4942	AssertLogRelRC(rc);
4943	}
4944	}
4945
4946	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
4947	}
4948	else if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4949	{
4950	/* The precise details of AMD's implementation are not yet clear. */
4951	}
4952	break;
4953
4954	default:
4955	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4956	break;
4957	}
4958
4959	/** @todo can probably kill this as this API is now init time only... */
4960	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4961	{
4962	PVMCPU pVCpu = &pVM->aCpus[i];
4963	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4964	}
4965	}
4966
4967
4968	/**
4969	* Queries a CPUID feature bit.
4970	*
4971	* @returns boolean for feature presence
4972	* @param pVM The cross context VM structure.
4973	* @param enmFeature The feature to query.
4974	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4975	*/
4976	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4977	{
4978	switch (enmFeature)
4979	{
4980	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4981	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4982	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4983	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4984	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4985	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4986	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4987	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4988	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4989	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4990	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4991	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4992	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
4993
4994	case CPUMCPUIDFEATURE_INVALID:
4995	case CPUMCPUIDFEATURE_32BIT_HACK:
4996	break;
4997	}
4998	AssertFailed();
4999	return false;
5000	}
5001
5002
5003	/**
5004	* Clears a CPUID feature bit.
5005	*
5006	* @param pVM The cross context VM structure.
5007	* @param enmFeature The feature to clear.
5008	*
5009	* @deprecated Probably better to default the feature to disabled and only allow
5010	* setting (enabling) it during construction.
5011	*/
5012	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5013	{
5014	PCPUMCPUIDLEAF pLeaf;
5015	switch (enmFeature)
5016	{
5017	case CPUMCPUIDFEATURE_APIC:
5018	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
5019	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5020	if (pLeaf)
5021	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
5022
5023	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5024	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
5025	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
5026
5027	pVM->cpum.s.GuestFeatures.fApic = 0;
5028	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
5029	break;
5030
5031	case CPUMCPUIDFEATURE_X2APIC:
5032	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
5033	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5034	if (pLeaf)
5035	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
5036	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
5037	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
5038	break;
5039
5040	case CPUMCPUIDFEATURE_PAE:
5041	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5042	if (pLeaf)
5043	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
5044
5045	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5046	if ( pLeaf
5047	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
5048	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
5049
5050	pVM->cpum.s.GuestFeatures.fPae = 0;
5051	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
5052	break;
5053
5054	case CPUMCPUIDFEATURE_PAT:
5055	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5056	if (pLeaf)
5057	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
5058
5059	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5060	if ( pLeaf
5061	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
5062	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
5063
5064	pVM->cpum.s.GuestFeatures.fPat = 0;
5065	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
5066	break;
5067
5068	case CPUMCPUIDFEATURE_LONG_MODE:
5069	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5070	if (pLeaf)
5071	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
5072	pVM->cpum.s.GuestFeatures.fLongMode = 0;
5073	break;
5074
5075	case CPUMCPUIDFEATURE_LAHF:
5076	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5077	if (pLeaf)
5078	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
5079	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
5080	break;
5081
5082	case CPUMCPUIDFEATURE_RDTSCP:
5083	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5084	if (pLeaf)
5085	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
5086	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
5087	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
5088	break;
5089
5090	case CPUMCPUIDFEATURE_HVP:
5091	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5092	if (pLeaf)
5093	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
5094	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
5095	break;
5096
5097	case CPUMCPUIDFEATURE_MWAIT_EXTS:
5098	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
5099	if (pLeaf)
5100	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
5101	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
5102	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
5103	break;
5104
5105	case CPUMCPUIDFEATURE_SPEC_CTRL:
5106	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
5107	if (pLeaf)
5108	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
5109	pVM->cpum.s.GuestFeatures.fSpeculationControl = 0;
5110	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
5111	break;
5112
5113	default:
5114	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5115	break;
5116	}
5117
5118	for (VMCPUID i = 0; i < pVM->cCpus; i++)
5119	{
5120	PVMCPU pVCpu = &pVM->aCpus[i];
5121	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5122	}
5123	}
5124
5125
5126
5127	/*
5128	*
5129	*
5130	* Saved state related code.
5131	* Saved state related code.
5132	* Saved state related code.
5133	*
5134	*
5135	*/
5136
5137	/**
5138	* Called both in pass 0 and the final pass.
5139	*
5140	* @param pVM The cross context VM structure.
5141	* @param pSSM The saved state handle.
5142	*/
5143	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
5144	{
5145	/*
5146	* Save all the CPU ID leaves.
5147	*/
5148	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
5149	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5150	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
5151	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5152
5153	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5154
5155	/*
5156	* Save a good portion of the raw CPU IDs as well as they may come in
5157	* handy when validating features for raw mode.
5158	*/
5159	CPUMCPUID aRawStd[16];
5160	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
5161	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5162	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
5163	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
5164
5165	CPUMCPUID aRawExt[32];
5166	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
5167	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5168	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
5169	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
5170	}
5171
5172
5173	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5174	{
5175	uint32_t cCpuIds;
5176	int rc = SSMR3GetU32(pSSM, &cCpuIds);
5177	if (RT_SUCCESS(rc))
5178	{
5179	if (cCpuIds < 64)
5180	{
5181	for (uint32_t i = 0; i < cCpuIds; i++)
5182	{
5183	CPUMCPUID CpuId;
5184	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
5185	if (RT_FAILURE(rc))
5186	break;
5187
5188	CPUMCPUIDLEAF NewLeaf;
5189	NewLeaf.uLeaf = uBase + i;
5190	NewLeaf.uSubLeaf = 0;
5191	NewLeaf.fSubLeafMask = 0;
5192	NewLeaf.uEax = CpuId.uEax;
5193	NewLeaf.uEbx = CpuId.uEbx;
5194	NewLeaf.uEcx = CpuId.uEcx;
5195	NewLeaf.uEdx = CpuId.uEdx;
5196	NewLeaf.fFlags = 0;
5197	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
5198	}
5199	}
5200	else
5201	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5202	}
5203	if (RT_FAILURE(rc))
5204	{
5205	RTMemFree(*ppaLeaves);
5206	*ppaLeaves = NULL;
5207	*pcLeaves = 0;
5208	}
5209	return rc;
5210	}
5211
5212
5213	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5214	{
5215	*ppaLeaves = NULL;
5216	*pcLeaves = 0;
5217
5218	int rc;
5219	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
5220	{
5221	/*
5222	* The new format. Starts by declaring the leave size and count.
5223	*/
5224	uint32_t cbLeaf;
5225	SSMR3GetU32(pSSM, &cbLeaf);
5226	uint32_t cLeaves;
5227	rc = SSMR3GetU32(pSSM, &cLeaves);
5228	if (RT_SUCCESS(rc))
5229	{
5230	if (cbLeaf == sizeof(**ppaLeaves))
5231	{
5232	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
5233	{
5234	/*
5235	* Load the leaves one by one.
5236	*
5237	* The uPrev stuff is a kludge for working around a week worth of bad saved
5238	* states during the CPUID revamp in March 2015. We saved too many leaves
5239	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
5240	* garbage entires at the end of the array when restoring. We also had
5241	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
5242	* this kludge doesn't deal correctly with that, but who cares...
5243	*/
5244	uint32_t uPrev = 0;
5245	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
5246	{
5247	CPUMCPUIDLEAF Leaf;
5248	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5249	if (RT_SUCCESS(rc))
5250	{
5251	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5252	\|\| Leaf.uLeaf >= uPrev)
5253	{
5254	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5255	uPrev = Leaf.uLeaf;
5256	}
5257	else
5258	uPrev = UINT32_MAX;
5259	}
5260	}
5261	}
5262	else
5263	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5264	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5265	}
5266	else
5267	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5268	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5269	}
5270	}
5271	else
5272	{
5273	/*
5274	* The old format with its three inflexible arrays.
5275	*/
5276	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5277	if (RT_SUCCESS(rc))
5278	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5279	if (RT_SUCCESS(rc))
5280	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5281	if (RT_SUCCESS(rc))
5282	{
5283	/*
5284	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5285	*/
5286	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5287	if ( pLeaf
5288	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5289	{
5290	CPUMCPUIDLEAF Leaf;
5291	Leaf.uLeaf = 4;
5292	Leaf.fSubLeafMask = UINT32_MAX;
5293	Leaf.uSubLeaf = 0;
5294	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5295	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5296	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5297	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5298	\| UINT32_C(63); /* system coherency line size - 1 */
5299	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5300	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5301	\| (UINT32_C(1) << 5) /* cache level */
5302	\| UINT32_C(1); /* cache type (data) */
5303	Leaf.fFlags = 0;
5304	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5305	if (RT_SUCCESS(rc))
5306	{
5307	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5308	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5309	}
5310	if (RT_SUCCESS(rc))
5311	{
5312	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5313	Leaf.uEcx = 4095; /* sets - 1 */
5314	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5315	Leaf.uEbx \|= UINT32_C(23) << 22;
5316	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5317	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5318	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5319	Leaf.uEax \|= UINT32_C(2) << 5;
5320	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5321	}
5322	}
5323	}
5324	}
5325	return rc;
5326	}
5327
5328
5329	/**
5330	* Loads the CPU ID leaves saved by pass 0, inner worker.
5331	*
5332	* @returns VBox status code.
5333	* @param pVM The cross context VM structure.
5334	* @param pSSM The saved state handle.
5335	* @param uVersion The format version.
5336	* @param paLeaves Guest CPUID leaves loaded from the state.
5337	* @param cLeaves The number of leaves in @a paLeaves.
5338	* @param pMsrs The guest MSRs.
5339	*/
5340	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
5341	{
5342	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5343
5344	/*
5345	* Continue loading the state into stack buffers.
5346	*/
5347	CPUMCPUID GuestDefCpuId;
5348	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5349	AssertRCReturn(rc, rc);
5350
5351	CPUMCPUID aRawStd[16];
5352	uint32_t cRawStd;
5353	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5354	if (cRawStd > RT_ELEMENTS(aRawStd))
5355	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5356	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5357	AssertRCReturn(rc, rc);
5358	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5359	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5360
5361	CPUMCPUID aRawExt[32];
5362	uint32_t cRawExt;
5363	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5364	if (cRawExt > RT_ELEMENTS(aRawExt))
5365	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5366	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5367	AssertRCReturn(rc, rc);
5368	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5369	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5370
5371	/*
5372	* Get the raw CPU IDs for the current host.
5373	*/
5374	CPUMCPUID aHostRawStd[16];
5375	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5376	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5377
5378	CPUMCPUID aHostRawExt[32];
5379	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5380	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5381	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5382
5383	/*
5384	* Get the host and guest overrides so we don't reject the state because
5385	* some feature was enabled thru these interfaces.
5386	* Note! We currently only need the feature leaves, so skip rest.
5387	*/
5388	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5389	CPUMCPUID aHostOverrideStd[2];
5390	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5391	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5392
5393	CPUMCPUID aHostOverrideExt[2];
5394	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5395	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5396
5397	/*
5398	* This can be skipped.
5399	*/
5400	bool fStrictCpuIdChecks;
5401	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5402
5403	/*
5404	* Define a bunch of macros for simplifying the santizing/checking code below.
5405	*/
5406	/* Generic expression + failure message. */
5407	#define CPUID_CHECK_RET(expr, fmt) \
5408	do { \
5409	if (!(expr)) \
5410	{ \
5411	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5412	if (fStrictCpuIdChecks) \
5413	{ \
5414	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5415	RTStrFree(pszMsg); \
5416	return rcCpuid; \
5417	} \
5418	LogRel(("CPUM: %s\n", pszMsg)); \
5419	RTStrFree(pszMsg); \
5420	} \
5421	} while (0)
5422	#define CPUID_CHECK_WRN(expr, fmt) \
5423	do { \
5424	if (!(expr)) \
5425	LogRel(fmt); \
5426	} while (0)
5427
5428	/* For comparing two values and bitch if they differs. */
5429	#define CPUID_CHECK2_RET(what, host, saved) \
5430	do { \
5431	if ((host) != (saved)) \
5432	{ \
5433	if (fStrictCpuIdChecks) \
5434	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5435	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5436	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5437	} \
5438	} while (0)
5439	#define CPUID_CHECK2_WRN(what, host, saved) \
5440	do { \
5441	if ((host) != (saved)) \
5442	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5443	} while (0)
5444
5445	/* For checking raw cpu features (raw mode). */
5446	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5447	do { \
5448	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5449	{ \
5450	if (fStrictCpuIdChecks) \
5451	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5452	N_(#bit " mismatch: host=%d saved=%d"), \
5453	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5454	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5455	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5456	} \
5457	} while (0)
5458	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5459	do { \
5460	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5461	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5462	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5463	} while (0)
5464	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5465
5466	/* For checking guest features. */
5467	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5468	do { \
5469	if ( (aGuestCpuId##set [1].reg & bit) \
5470	&& !(aHostRaw##set [1].reg & bit) \
5471	&& !(aHostOverride##set [1].reg & bit) \
5472	) \
5473	{ \
5474	if (fStrictCpuIdChecks) \
5475	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5476	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5477	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5478	} \
5479	} while (0)
5480	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5481	do { \
5482	if ( (aGuestCpuId##set [1].reg & bit) \
5483	&& !(aHostRaw##set [1].reg & bit) \
5484	&& !(aHostOverride##set [1].reg & bit) \
5485	) \
5486	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5487	} while (0)
5488	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5489	do { \
5490	if ( (aGuestCpuId##set [1].reg & bit) \
5491	&& !(aHostRaw##set [1].reg & bit) \
5492	&& !(aHostOverride##set [1].reg & bit) \
5493	) \
5494	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5495	} while (0)
5496	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5497
5498	/* For checking guest features if AMD guest CPU. */
5499	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5500	do { \
5501	if ( (aGuestCpuId##set [1].reg & bit) \
5502	&& fGuestAmd \
5503	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5504	&& !(aHostOverride##set [1].reg & bit) \
5505	) \
5506	{ \
5507	if (fStrictCpuIdChecks) \
5508	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5509	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5510	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5511	} \
5512	} while (0)
5513	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5514	do { \
5515	if ( (aGuestCpuId##set [1].reg & bit) \
5516	&& fGuestAmd \
5517	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5518	&& !(aHostOverride##set [1].reg & bit) \
5519	) \
5520	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5521	} while (0)
5522	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5523	do { \
5524	if ( (aGuestCpuId##set [1].reg & bit) \
5525	&& fGuestAmd \
5526	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5527	&& !(aHostOverride##set [1].reg & bit) \
5528	) \
5529	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5530	} while (0)
5531	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5532
5533	/* For checking AMD features which have a corresponding bit in the standard
5534	range. (Intel defines very few bits in the extended feature sets.) */
5535	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5536	do { \
5537	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5538	&& !(fHostAmd \
5539	? aHostRawExt[1].reg & (ExtBit) \
5540	: aHostRawStd[1].reg & (StdBit)) \
5541	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5542	) \
5543	{ \
5544	if (fStrictCpuIdChecks) \
5545	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5546	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5547	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5548	} \
5549	} while (0)
5550	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5551	do { \
5552	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5553	&& !(fHostAmd \
5554	? aHostRawExt[1].reg & (ExtBit) \
5555	: aHostRawStd[1].reg & (StdBit)) \
5556	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5557	) \
5558	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5559	} while (0)
5560	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5561	do { \
5562	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5563	&& !(fHostAmd \
5564	? aHostRawExt[1].reg & (ExtBit) \
5565	: aHostRawStd[1].reg & (StdBit)) \
5566	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5567	) \
5568	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5569	} while (0)
5570	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5571
5572	/*
5573	* For raw-mode we'll require that the CPUs are very similar since we don't
5574	* intercept CPUID instructions for user mode applications.
5575	*/
5576	if (VM_IS_RAW_MODE_ENABLED(pVM))
5577	{
5578	/* CPUID(0) */
5579	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
5580	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
5581	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
5582	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5583	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
5584	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
5585	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
5586	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
5587	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5588
5589	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
5590
5591	/* CPUID(1).eax */
5592	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
5593	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
5594	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
5595
5596	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
5597	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
5598	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
5599
5600	/* CPUID(1).ecx */
5601	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
5602	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
5603	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
5604	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5605	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
5606	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
5607	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
5608	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
5609	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
5610	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
5611	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
5612	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
5613	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
5614	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
5615	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
5616	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
5617	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5618	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5619	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
5620	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
5621	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
5622	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5623	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
5624	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
5625	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5626	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
5627	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
5628	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5629	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
5630	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5631	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5632	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
5633
5634	/* CPUID(1).edx */
5635	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5636	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5637	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
5638	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5639	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
5640	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
5641	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5642	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5643	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
5644	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5645	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5646	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5647	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5648	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5649	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5650	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
5651	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5652	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5653	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5654	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
5655	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5656	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
5657	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
5658	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
5659	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
5660	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
5661	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
5662	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
5663	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
5664	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
5665	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
5666	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
5667
5668	/* CPUID(2) - config, mostly about caches. ignore. */
5669	/* CPUID(3) - processor serial number. ignore. */
5670	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
5671	/* CPUID(5) - mwait/monitor config. ignore. */
5672	/* CPUID(6) - power management. ignore. */
5673	/* CPUID(7) - ???. ignore. */
5674	/* CPUID(8) - ???. ignore. */
5675	/* CPUID(9) - DCA. ignore for now. */
5676	/* CPUID(a) - PeMo info. ignore for now. */
5677	/* CPUID(b) - topology info - takes ECX as input. ignore. */
5678
5679	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
5680	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
5681	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
5682	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
5683	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
5684	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
5685	{
5686	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
5687	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
5688	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
5689	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
5690	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
5691	}
5692
5693	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
5694	Note! Intel have/is marking many of the fields here as reserved. We
5695	will verify them as if it's an AMD CPU. */
5696	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
5697	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
5698	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
5699	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
5700	{
5701	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
5702	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
5703	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
5704	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5705	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
5706	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
5707	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
5708
5709	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
5710	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
5711	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
5712	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
5713	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
5714	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5715
5716	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
5717	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
5718	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
5719	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
5720
5721	/* CPUID(0x80000001).ecx */
5722	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
5723	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
5724	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
5725	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
5726	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
5727	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
5728	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
5729	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
5730	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
5731	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
5732	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
5733	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
5734	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
5735	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
5736	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5737	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5738	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5739	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5740	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5741	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5742	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5743	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5744	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5745	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5746	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5747	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5748	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5749	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5750	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5751	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5752	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5753	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5754
5755	/* CPUID(0x80000001).edx */
5756	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
5757	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
5758	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
5759	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
5760	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
5761	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
5762	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
5763	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
5764	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
5765	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
5766	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5767	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
5768	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
5769	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
5770	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
5771	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
5772	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
5773	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
5774	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5775	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5776	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5777	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
5778	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5779	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
5780	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
5781	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5782	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5783	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5784	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
5785	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5786	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5787	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5788
5789	/** @todo verify the rest as well. */
5790	}
5791	}
5792
5793
5794
5795	/*
5796	* Verify that we can support the features already exposed to the guest on
5797	* this host.
5798	*
5799	* Most of the features we're emulating requires intercepting instruction
5800	* and doing it the slow way, so there is no need to warn when they aren't
5801	* present in the host CPU. Thus we use IGN instead of EMU on these.
5802	*
5803	* Trailing comments:
5804	* "EMU" - Possible to emulate, could be lots of work and very slow.
5805	* "EMU?" - Can this be emulated?
5806	*/
5807	CPUMCPUID aGuestCpuIdStd[2];
5808	RT_ZERO(aGuestCpuIdStd);
5809	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5810
5811	/* CPUID(1).ecx */
5812	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5813	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5814	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5815	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5816	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5817	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5818	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5819	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5820	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5821	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5822	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5823	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5824	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5825	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5826	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5827	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5828	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5829	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5830	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5831	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5832	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5833	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5834	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5835	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5836	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5837	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5838	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5839	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5840	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5841	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5842	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5843	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5844
5845	/* CPUID(1).edx */
5846	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5847	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5848	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5849	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5850	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5851	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5852	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5853	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5854	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5855	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5856	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5857	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5858	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5859	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5860	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5861	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5862	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5863	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5864	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5865	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5866	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5867	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5868	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5869	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5870	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5871	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5872	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5873	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5874	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5875	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5876	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5877	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5878
5879	/* CPUID(0x80000000). */
5880	CPUMCPUID aGuestCpuIdExt[2];
5881	RT_ZERO(aGuestCpuIdExt);
5882	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5883	{
5884	/** @todo deal with no 0x80000001 on the host. */
5885	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5886	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5887
5888	/* CPUID(0x80000001).ecx */
5889	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5890	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5891	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5892	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5893	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5894	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5895	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5896	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5897	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5898	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5899	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5900	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5901	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5902	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5903	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5904	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5905	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5906	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5907	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5908	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5909	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5910	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5911	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5912	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5913	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5914	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5915	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5916	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5917	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5918	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5919	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5920	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5921
5922	/* CPUID(0x80000001).edx */
5923	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5924	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5925	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5926	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5927	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5928	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5929	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5930	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5931	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5932	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5933	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5934	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5935	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5936	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5937	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5938	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5939	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5940	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5941	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5942	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5943	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5944	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5945	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5946	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5947	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5948	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5949	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5950	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5951	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5952	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5953	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5954	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5955	}
5956
5957	/** @todo check leaf 7 */
5958
5959	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5960	* ECX=0: EAX - Valid bits in XCR0[31:0].
5961	* EBX - Maximum state size as per current XCR0 value.
5962	* ECX - Maximum state size for all supported features.
5963	* EDX - Valid bits in XCR0[63:32].
5964	* ECX=1: EAX - Various X-features.
5965	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5966	* ECX - Valid bits in IA32_XSS[31:0].
5967	* EDX - Valid bits in IA32_XSS[63:32].
5968	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5969	* if the bit invalid all four registers are set to zero.
5970	* EAX - The state size for this feature.
5971	* EBX - The state byte offset of this feature.
5972	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5973	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5974	*/
5975	uint64_t fGuestXcr0Mask = 0;
5976	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5977	if ( pCurLeaf
5978	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5979	&& ( pCurLeaf->uEax
5980	\|\| pCurLeaf->uEbx
5981	\|\| pCurLeaf->uEcx
5982	\|\| pCurLeaf->uEdx) )
5983	{
5984	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5985	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5986	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5987	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5988	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5989	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5990	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5991	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5992
5993	/* We don't support any additional features yet. */
5994	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5995	if (pCurLeaf && pCurLeaf->uEax)
5996	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5997	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5998	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5999	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
6000	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
6001	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
6002
6003
6004	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
6005	{
6006	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
6007	if (pCurLeaf)
6008	{
6009	/* If advertised, the state component offset and size must match the one used by host. */
6010	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
6011	{
6012	CPUMCPUID RawHost;
6013	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
6014	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
6015	if ( RawHost.uEbx != pCurLeaf->uEbx
6016	\|\| RawHost.uEax != pCurLeaf->uEax)
6017	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
6018	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
6019	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
6020	}
6021	}
6022	}
6023	}
6024	/* Clear leaf 0xd just in case we're loading an old state... */
6025	else if (pCurLeaf)
6026	{
6027	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6028	{
6029	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
6030	if (pCurLeaf)
6031	{
6032	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
6033	\|\| ( pCurLeaf->uEax == 0
6034	&& pCurLeaf->uEbx == 0
6035	&& pCurLeaf->uEcx == 0
6036	&& pCurLeaf->uEdx == 0),
6037	("uVersion=%#x; %#x %#x %#x %#x\n",
6038	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
6039	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
6040	}
6041	}
6042	}
6043
6044	/* Update the fXStateGuestMask value for the VM. */
6045	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
6046	{
6047	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
6048	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
6049	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
6050	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
6051	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
6052	}
6053
6054	#undef CPUID_CHECK_RET
6055	#undef CPUID_CHECK_WRN
6056	#undef CPUID_CHECK2_RET
6057	#undef CPUID_CHECK2_WRN
6058	#undef CPUID_RAW_FEATURE_RET
6059	#undef CPUID_RAW_FEATURE_WRN
6060	#undef CPUID_RAW_FEATURE_IGN
6061	#undef CPUID_GST_FEATURE_RET
6062	#undef CPUID_GST_FEATURE_WRN
6063	#undef CPUID_GST_FEATURE_EMU
6064	#undef CPUID_GST_FEATURE_IGN
6065	#undef CPUID_GST_FEATURE2_RET
6066	#undef CPUID_GST_FEATURE2_WRN
6067	#undef CPUID_GST_FEATURE2_EMU
6068	#undef CPUID_GST_FEATURE2_IGN
6069	#undef CPUID_GST_AMD_FEATURE_RET
6070	#undef CPUID_GST_AMD_FEATURE_WRN
6071	#undef CPUID_GST_AMD_FEATURE_EMU
6072	#undef CPUID_GST_AMD_FEATURE_IGN
6073
6074	/*
6075	* We're good, commit the CPU ID leaves.
6076	*/
6077	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
6078	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
6079	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
6080	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
6081	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
6082	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
6083	AssertLogRelRCReturn(rc, rc);
6084
6085	return VINF_SUCCESS;
6086	}
6087
6088
6089	/**
6090	* Loads the CPU ID leaves saved by pass 0.
6091	*
6092	* @returns VBox status code.
6093	* @param pVM The cross context VM structure.
6094	* @param pSSM The saved state handle.
6095	* @param uVersion The format version.
6096	* @param pMsrs The guest MSRs.
6097	*/
6098	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
6099	{
6100	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
6101
6102	/*
6103	* Load the CPUID leaves array first and call worker to do the rest, just so
6104	* we can free the memory when we need to without ending up in column 1000.
6105	*/
6106	PCPUMCPUIDLEAF paLeaves;
6107	uint32_t cLeaves;
6108	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
6109	AssertRC(rc);
6110	if (RT_SUCCESS(rc))
6111	{
6112	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
6113	RTMemFree(paLeaves);
6114	}
6115	return rc;
6116	}
6117
6118
6119
6120	/**
6121	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
6122	*
6123	* @returns VBox status code.
6124	* @param pVM The cross context VM structure.
6125	* @param pSSM The saved state handle.
6126	* @param uVersion The format version.
6127	*/
6128	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
6129	{
6130	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
6131
6132	/*
6133	* Restore the CPUID leaves.
6134	*
6135	* Note that we support restoring less than the current amount of standard
6136	* leaves because we've been allowed more is newer version of VBox.
6137	*/
6138	uint32_t cElements;
6139	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6140	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
6141	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6142	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
6143
6144	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6145	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
6146	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6147	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
6148
6149	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6150	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
6151	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6152	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
6153
6154	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
6155
6156	/*
6157	* Check that the basic cpuid id information is unchanged.
6158	*/
6159	/** @todo we should check the 64 bits capabilities too! */
6160	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
6161	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
6162	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
6163	uint32_t au32CpuIdSaved[8];
6164	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
6165	if (RT_SUCCESS(rc))
6166	{
6167	/* Ignore CPU stepping. */
6168	au32CpuId[4] &= 0xfffffff0;
6169	au32CpuIdSaved[4] &= 0xfffffff0;
6170
6171	/* Ignore APIC ID (AMD specs). */
6172	au32CpuId[5] &= ~0xff000000;
6173	au32CpuIdSaved[5] &= ~0xff000000;
6174
6175	/* Ignore the number of Logical CPUs (AMD specs). */
6176	au32CpuId[5] &= ~0x00ff0000;
6177	au32CpuIdSaved[5] &= ~0x00ff0000;
6178
6179	/* Ignore some advanced capability bits, that we don't expose to the guest. */
6180	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6181	\| X86_CPUID_FEATURE_ECX_VMX
6182	\| X86_CPUID_FEATURE_ECX_SMX
6183	\| X86_CPUID_FEATURE_ECX_EST
6184	\| X86_CPUID_FEATURE_ECX_TM2
6185	\| X86_CPUID_FEATURE_ECX_CNTXID
6186	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6187	\| X86_CPUID_FEATURE_ECX_PDCM
6188	\| X86_CPUID_FEATURE_ECX_DCA
6189	\| X86_CPUID_FEATURE_ECX_X2APIC
6190	);
6191	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6192	\| X86_CPUID_FEATURE_ECX_VMX
6193	\| X86_CPUID_FEATURE_ECX_SMX
6194	\| X86_CPUID_FEATURE_ECX_EST
6195	\| X86_CPUID_FEATURE_ECX_TM2
6196	\| X86_CPUID_FEATURE_ECX_CNTXID
6197	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6198	\| X86_CPUID_FEATURE_ECX_PDCM
6199	\| X86_CPUID_FEATURE_ECX_DCA
6200	\| X86_CPUID_FEATURE_ECX_X2APIC
6201	);
6202
6203	/* Make sure we don't forget to update the masks when enabling
6204	* features in the future.
6205	*/
6206	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
6207	( X86_CPUID_FEATURE_ECX_DTES64
6208	\| X86_CPUID_FEATURE_ECX_VMX
6209	\| X86_CPUID_FEATURE_ECX_SMX
6210	\| X86_CPUID_FEATURE_ECX_EST
6211	\| X86_CPUID_FEATURE_ECX_TM2
6212	\| X86_CPUID_FEATURE_ECX_CNTXID
6213	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6214	\| X86_CPUID_FEATURE_ECX_PDCM
6215	\| X86_CPUID_FEATURE_ECX_DCA
6216	\| X86_CPUID_FEATURE_ECX_X2APIC
6217	)));
6218	/* do the compare */
6219	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
6220	{
6221	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
6222	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
6223	"Saved=%.*Rhxs\n"
6224	"Real =%.*Rhxs\n",
6225	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6226	sizeof(au32CpuId), au32CpuId));
6227	else
6228	{
6229	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
6230	"Saved=%.*Rhxs\n"
6231	"Real =%.*Rhxs\n",
6232	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6233	sizeof(au32CpuId), au32CpuId));
6234	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
6235	}
6236	}
6237	}
6238
6239	return rc;
6240	}
6241
6242
6243
6244	/*
6245	*
6246	*
6247	* CPUID Info Handler.
6248	* CPUID Info Handler.
6249	* CPUID Info Handler.
6250	*
6251	*
6252	*/
6253
6254
6255
6256	/**
6257	* Get L1 cache / TLS associativity.
6258	*/
6259	static const char getCacheAss(unsigned u, char pszBuf)
6260	{
6261	if (u == 0)
6262	return "res0 ";
6263	if (u == 1)
6264	return "direct";
6265	if (u == 255)
6266	return "fully";
6267	if (u >= 256)
6268	return "???";
6269
6270	RTStrPrintf(pszBuf, 16, "%d way", u);
6271	return pszBuf;
6272	}
6273
6274
6275	/**
6276	* Get L2 cache associativity.
6277	*/
6278	const char *getL2CacheAss(unsigned u)
6279	{
6280	switch (u)
6281	{
6282	case 0: return "off ";
6283	case 1: return "direct";
6284	case 2: return "2 way ";
6285	case 3: return "res3 ";
6286	case 4: return "4 way ";
6287	case 5: return "res5 ";
6288	case 6: return "8 way ";
6289	case 7: return "res7 ";
6290	case 8: return "16 way";
6291	case 9: return "res9 ";
6292	case 10: return "res10 ";
6293	case 11: return "res11 ";
6294	case 12: return "res12 ";
6295	case 13: return "res13 ";
6296	case 14: return "res14 ";
6297	case 15: return "fully ";
6298	default: return "????";
6299	}
6300	}
6301
6302
6303	/** CPUID(1).EDX field descriptions. */
6304	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6305	{
6306	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6307	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6308	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6309	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6310	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6311	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6312	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6313	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6314	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6315	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6316	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6317	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6318	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6319	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6320	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6321	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6322	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6323	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6324	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6325	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6326	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6327	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6328	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6329	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6330	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6331	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6332	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6333	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6334	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6335	DBGFREGSUBFIELD_TERMINATOR()
6336	};
6337
6338	/** CPUID(1).ECX field descriptions. */
6339	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6340	{
6341	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6342	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6343	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6344	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6345	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6346	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6347	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6348	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6349	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6350	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6351	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6352	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6353	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6354	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6355	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6356	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6357	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6358	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6359	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6360	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6361	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6362	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6363	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6364	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6365	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6366	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6367	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6368	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6369	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6370	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6371	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6372	DBGFREGSUBFIELD_TERMINATOR()
6373	};
6374
6375	/** CPUID(7,0).EBX field descriptions. */
6376	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6377	{
6378	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6379	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6380	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6381	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6382	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6383	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6384	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6385	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6386	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6387	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6388	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6389	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6390	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6391	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6392	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6393	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6394	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6395	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6396	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6397	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6398	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6399	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6400	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6401	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6402	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6403	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6404	DBGFREGSUBFIELD_TERMINATOR()
6405	};
6406
6407	/** CPUID(7,0).ECX field descriptions. */
6408	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6409	{
6410	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6411	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6412	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6413	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6414	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6415	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6416	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6417	DBGFREGSUBFIELD_TERMINATOR()
6418	};
6419
6420	/** CPUID(7,0).EDX field descriptions. */
6421	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6422	{
6423	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
6424	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6425	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6426	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
6427	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6428	DBGFREGSUBFIELD_TERMINATOR()
6429	};
6430
6431
6432	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6433	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6434	{
6435	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6436	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6437	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6438	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6439	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6440	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6441	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6442	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6443	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6444	DBGFREGSUBFIELD_TERMINATOR()
6445	};
6446
6447	/** CPUID(13,1).EAX field descriptions. */
6448	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6449	{
6450	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6451	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6452	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6453	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6454	DBGFREGSUBFIELD_TERMINATOR()
6455	};
6456
6457
6458	/** CPUID(0x80000001,0).EDX field descriptions. */
6459	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6460	{
6461	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6462	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6463	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6464	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6465	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6466	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6467	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6468	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6469	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6470	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6471	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6472	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6473	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6474	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6475	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6476	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6477	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6478	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6479	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6480	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6481	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6482	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6483	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6484	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6485	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6486	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6487	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6488	DBGFREGSUBFIELD_TERMINATOR()
6489	};
6490
6491	/** CPUID(0x80000001,0).ECX field descriptions. */
6492	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6493	{
6494	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6495	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6496	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6497	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6498	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6499	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6500	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6501	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6502	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6503	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6504	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6505	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6506	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6507	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6508	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6509	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6510	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6511	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6512	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6513	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6514	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6515	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6516	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6517	DBGFREGSUBFIELD_TERMINATOR()
6518	};
6519
6520	/** CPUID(0x8000000a,0).EDX field descriptions. */
6521	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6522	{
6523	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6524	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6525	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6526	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6527	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6528	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6529	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6530	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6531	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6532	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6533	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6534	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6535	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6536	DBGFREGSUBFIELD_TERMINATOR()
6537	};
6538
6539
6540	/** CPUID(0x80000007,0).EDX field descriptions. */
6541	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6542	{
6543	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6544	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6545	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6546	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6547	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6548	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6549	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6550	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6551	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6552	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6553	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6554	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6555	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6556	DBGFREGSUBFIELD_TERMINATOR()
6557	};
6558
6559	/** CPUID(0x80000008,0).EBX field descriptions. */
6560	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6561	{
6562	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6563	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6564	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6565	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6566	DBGFREGSUBFIELD_TERMINATOR()
6567	};
6568
6569
6570	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6571	const char *pszLeadIn, uint32_t cchWidth)
6572	{
6573	if (pszLeadIn)
6574	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6575
6576	for (uint32_t iBit = 0; iBit < 32; iBit++)
6577	if (RT_BIT_32(iBit) & uVal)
6578	{
6579	while ( pDesc->pszName != NULL
6580	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6581	pDesc++;
6582	if ( pDesc->pszName != NULL
6583	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6584	{
6585	if (pDesc->cBits == 1)
6586	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6587	else
6588	{
6589	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6590	if (pDesc->cBits < 32)
6591	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6592	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6593	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6594	}
6595	}
6596	else
6597	pHlp->pfnPrintf(pHlp, " %u", iBit);
6598	}
6599	if (pszLeadIn)
6600	pHlp->pfnPrintf(pHlp, "\n");
6601	}
6602
6603
6604	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6605	const char *pszLeadIn, uint32_t cchWidth)
6606	{
6607	if (pszLeadIn)
6608	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6609
6610	for (uint32_t iBit = 0; iBit < 64; iBit++)
6611	if (RT_BIT_64(iBit) & uVal)
6612	{
6613	while ( pDesc->pszName != NULL
6614	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6615	pDesc++;
6616	if ( pDesc->pszName != NULL
6617	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6618	{
6619	if (pDesc->cBits == 1)
6620	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6621	else
6622	{
6623	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6624	if (pDesc->cBits < 64)
6625	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6626	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6627	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6628	}
6629	}
6630	else
6631	pHlp->pfnPrintf(pHlp, " %u", iBit);
6632	}
6633	if (pszLeadIn)
6634	pHlp->pfnPrintf(pHlp, "\n");
6635	}
6636
6637
6638	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6639	const char *pszLeadIn, uint32_t cchWidth)
6640	{
6641	if (!uVal)
6642	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6643	else
6644	{
6645	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6646	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6647	pHlp->pfnPrintf(pHlp, " )\n");
6648	}
6649	}
6650
6651
6652	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6653	uint32_t cchWidth)
6654	{
6655	uint32_t uCombined = uVal1 \| uVal2;
6656	for (uint32_t iBit = 0; iBit < 32; iBit++)
6657	if ( (RT_BIT_32(iBit) & uCombined)
6658	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6659	{
6660	while ( pDesc->pszName != NULL
6661	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6662	pDesc++;
6663
6664	if ( pDesc->pszName != NULL
6665	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6666	{
6667	size_t cchMnemonic = strlen(pDesc->pszName);
6668	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6669	size_t cchDesc = strlen(pszDesc);
6670	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6671	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6672	if (pDesc->cBits < 32)
6673	{
6674	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6675	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6676	}
6677
6678	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6679	pDesc->pszName, pszDesc,
6680	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6681	uFieldValue1, uFieldValue2);
6682
6683	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6684	pDesc++;
6685	}
6686	else
6687	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6688	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6689	}
6690	}
6691
6692
6693	/**
6694	* Produces a detailed summary of standard leaf 0x00000001.
6695	*
6696	* @param pHlp The info helper functions.
6697	* @param pCurLeaf The 0x00000001 leaf.
6698	* @param fVerbose Whether to be very verbose or not.
6699	* @param fIntel Set if intel CPU.
6700	*/
6701	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6702	{
6703	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6704	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6705	uint32_t uEAX = pCurLeaf->uEax;
6706	uint32_t uEBX = pCurLeaf->uEbx;
6707
6708	pHlp->pfnPrintf(pHlp,
6709	"%36s %2d \tExtended: %d \tEffective: %d\n"
6710	"%36s %2d \tExtended: %d \tEffective: %d\n"
6711	"%36s %d\n"
6712	"%36s %d (%s)\n"
6713	"%36s %#04x\n"
6714	"%36s %d\n"
6715	"%36s %d\n"
6716	"%36s %#04x\n"
6717	,
6718	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6719	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6720	"Stepping:", ASMGetCpuStepping(uEAX),
6721	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6722	"APIC ID:", (uEBX >> 24) & 0xff,
6723	"Logical CPUs:",(uEBX >> 16) & 0xff,
6724	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6725	"Brand ID:", (uEBX >> 0) & 0xff);
6726	if (fVerbose)
6727	{
6728	CPUMCPUID Host;
6729	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6730	pHlp->pfnPrintf(pHlp, "Features\n");
6731	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6732	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6733	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6734	}
6735	else
6736	{
6737	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6738	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6739	}
6740	}
6741
6742
6743	/**
6744	* Produces a detailed summary of standard leaf 0x00000007.
6745	*
6746	* @param pHlp The info helper functions.
6747	* @param paLeaves The CPUID leaves array.
6748	* @param cLeaves The number of leaves in the array.
6749	* @param pCurLeaf The first 0x00000007 leaf.
6750	* @param fVerbose Whether to be very verbose or not.
6751	*/
6752	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6753	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6754	{
6755	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6756	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6757	for (;;)
6758	{
6759	CPUMCPUID Host;
6760	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6761
6762	switch (pCurLeaf->uSubLeaf)
6763	{
6764	case 0:
6765	if (fVerbose)
6766	{
6767	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6768	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6769	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6770	if (pCurLeaf->uEdx \|\| Host.uEdx)
6771	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6772	}
6773	else
6774	{
6775	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6776	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6777	if (pCurLeaf->uEdx)
6778	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6779	}
6780	break;
6781
6782	default:
6783	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6784	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6785	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6786	break;
6787
6788	}
6789
6790	/* advance. */
6791	pCurLeaf++;
6792	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6793	\|\| pCurLeaf->uLeaf != 0x7)
6794	break;
6795	}
6796	}
6797
6798
6799	/**
6800	* Produces a detailed summary of standard leaf 0x0000000d.
6801	*
6802	* @param pHlp The info helper functions.
6803	* @param paLeaves The CPUID leaves array.
6804	* @param cLeaves The number of leaves in the array.
6805	* @param pCurLeaf The first 0x00000007 leaf.
6806	* @param fVerbose Whether to be very verbose or not.
6807	*/
6808	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6809	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6810	{
6811	RT_NOREF_PV(fVerbose);
6812	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6813	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6814	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6815	{
6816	CPUMCPUID Host;
6817	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6818
6819	switch (uSubLeaf)
6820	{
6821	case 0:
6822	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6823	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6824	pCurLeaf->uEbx, pCurLeaf->uEcx);
6825	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6826
6827	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6828	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6829	"Valid XCR0 bits, guest:", 42);
6830	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6831	"Valid XCR0 bits, host:", 42);
6832	break;
6833
6834	case 1:
6835	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6836	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6837	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6838
6839	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6840	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6841	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6842
6843	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6844	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6845	" Valid IA32_XSS bits, guest:", 42);
6846	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6847	" Valid IA32_XSS bits, host:", 42);
6848	break;
6849
6850	default:
6851	if ( pCurLeaf
6852	&& pCurLeaf->uSubLeaf == uSubLeaf
6853	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6854	{
6855	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6856	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6857	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6858	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6859	if (pCurLeaf->uEdx)
6860	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6861	pHlp->pfnPrintf(pHlp, " --");
6862	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6863	pHlp->pfnPrintf(pHlp, "\n");
6864	}
6865	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6866	{
6867	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6868	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6869	if (Host.uEcx & ~RT_BIT_32(0))
6870	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6871	if (Host.uEdx)
6872	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6873	pHlp->pfnPrintf(pHlp, " --");
6874	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6875	pHlp->pfnPrintf(pHlp, "\n");
6876	}
6877	break;
6878
6879	}
6880
6881	/* advance. */
6882	if (pCurLeaf)
6883	{
6884	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6885	&& pCurLeaf->uSubLeaf <= uSubLeaf
6886	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6887	pCurLeaf++;
6888	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6889	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6890	pCurLeaf = NULL;
6891	}
6892	}
6893	}
6894
6895
6896	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6897	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6898	{
6899	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6900	&& pCurLeaf->uLeaf <= uUpToLeaf)
6901	{
6902	pHlp->pfnPrintf(pHlp,
6903	" %s\n"
6904	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6905	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6906	&& pCurLeaf->uLeaf <= uUpToLeaf)
6907	{
6908	CPUMCPUID Host;
6909	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6910	pHlp->pfnPrintf(pHlp,
6911	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6912	"Hst: %08x %08x %08x %08x\n",
6913	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6914	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6915	pCurLeaf++;
6916	}
6917	}
6918
6919	return pCurLeaf;
6920	}
6921
6922
6923	/**
6924	* Display the guest CpuId leaves.
6925	*
6926	* @param pVM The cross context VM structure.
6927	* @param pHlp The info helper functions.
6928	* @param pszArgs "terse", "default" or "verbose".
6929	*/
6930	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6931	{
6932	/*
6933	* Parse the argument.
6934	*/
6935	unsigned iVerbosity = 1;
6936	if (pszArgs)
6937	{
6938	pszArgs = RTStrStripL(pszArgs);
6939	if (!strcmp(pszArgs, "terse"))
6940	iVerbosity--;
6941	else if (!strcmp(pszArgs, "verbose"))
6942	iVerbosity++;
6943	}
6944
6945	uint32_t uLeaf;
6946	CPUMCPUID Host;
6947	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6948	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6949	PCCPUMCPUIDLEAF pCurLeaf;
6950	PCCPUMCPUIDLEAF pNextLeaf;
6951	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6952	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6953	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6954
6955	/*
6956	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6957	*/
6958	uint32_t cHstMax = ASMCpuId_EAX(0);
6959	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6960	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6961	pHlp->pfnPrintf(pHlp,
6962	" Raw Standard CPUID Leaves\n"
6963	" Leaf/sub-leaf eax ebx ecx edx\n");
6964	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6965	{
6966	uint32_t cMaxSubLeaves = 1;
6967	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6968	cMaxSubLeaves = 16;
6969	else if (uLeaf == 0xd)
6970	cMaxSubLeaves = 128;
6971
6972	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6973	{
6974	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6975	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6976	&& pCurLeaf->uLeaf == uLeaf
6977	&& pCurLeaf->uSubLeaf == uSubLeaf)
6978	{
6979	pHlp->pfnPrintf(pHlp,
6980	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6981	"Hst: %08x %08x %08x %08x\n",
6982	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6983	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6984	pCurLeaf++;
6985	}
6986	else if ( uLeaf != 0xd
6987	\|\| uSubLeaf <= 1
6988	\|\| Host.uEbx != 0 )
6989	pHlp->pfnPrintf(pHlp,
6990	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6991	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6992
6993	/* Done? */
6994	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6995	\|\| pCurLeaf->uLeaf != uLeaf)
6996	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6997	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6998	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6999	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
7000	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
7001	)
7002	)
7003	break;
7004	}
7005	}
7006	pNextLeaf = pCurLeaf;
7007
7008	/*
7009	* If verbose, decode it.
7010	*/
7011	if (iVerbosity && paLeaves[0].uLeaf == 0)
7012	pHlp->pfnPrintf(pHlp,
7013	"%36s %.04s%.04s%.04s\n"
7014	"%36s 0x00000000-%#010x\n"
7015	,
7016	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
7017	"Supports:", paLeaves[0].uEax);
7018
7019	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
7020	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
7021
7022	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
7023	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
7024
7025	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
7026	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
7027
7028	pCurLeaf = pNextLeaf;
7029
7030	/*
7031	* Hypervisor leaves.
7032	*
7033	* Unlike most of the other leaves reported, the guest hypervisor leaves
7034	* aren't a subset of the host CPUID bits.
7035	*/
7036	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
7037
7038	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7039	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
7040	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
7041	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
7042	cMax = RT_MAX(cHstMax, cGstMax);
7043	if (cMax >= UINT32_C(0x40000000))
7044	{
7045	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
7046
7047	/** @todo dump these in more detail. */
7048
7049	pCurLeaf = pNextLeaf;
7050	}
7051
7052
7053	/*
7054	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
7055	* Implemented after AMD specs.
7056	*/
7057	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
7058
7059	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7060	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
7061	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
7062	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
7063	cMax = RT_MAX(cHstMax, cGstMax);
7064	if (cMax >= UINT32_C(0x80000000))
7065	{
7066
7067	pHlp->pfnPrintf(pHlp,
7068	" Raw Extended CPUID Leaves\n"
7069	" Leaf/sub-leaf eax ebx ecx edx\n");
7070	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
7071	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
7072	{
7073	uint32_t cMaxSubLeaves = 1;
7074	if (uLeaf == UINT32_C(0x8000001d))
7075	cMaxSubLeaves = 16;
7076
7077	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
7078	{
7079	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7080	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
7081	&& pCurLeaf->uLeaf == uLeaf
7082	&& pCurLeaf->uSubLeaf == uSubLeaf)
7083	{
7084	pHlp->pfnPrintf(pHlp,
7085	"Gst: %08x/%04x %08x %08x %08x %08x\n"
7086	"Hst: %08x %08x %08x %08x\n",
7087	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
7088	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
7089	pCurLeaf++;
7090	}
7091	else if ( uLeaf != 0xd
7092	\|\| uSubLeaf <= 1
7093	\|\| Host.uEbx != 0 )
7094	pHlp->pfnPrintf(pHlp,
7095	"Hst: %08x/%04x %08x %08x %08x %08x\n",
7096	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
7097
7098	/* Done? */
7099	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
7100	\|\| pCurLeaf->uLeaf != uLeaf)
7101	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
7102	break;
7103	}
7104	}
7105	pNextLeaf = pCurLeaf;
7106
7107	/*
7108	* Understandable output
7109	*/
7110	if (iVerbosity)
7111	pHlp->pfnPrintf(pHlp,
7112	"Ext Name: %.4s%.4s%.4s\n"
7113	"Ext Supports: 0x80000000-%#010x\n",
7114	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
7115
7116	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
7117	if (iVerbosity && pCurLeaf)
7118	{
7119	uint32_t uEAX = pCurLeaf->uEax;
7120	pHlp->pfnPrintf(pHlp,
7121	"Family: %d \tExtended: %d \tEffective: %d\n"
7122	"Model: %d \tExtended: %d \tEffective: %d\n"
7123	"Stepping: %d\n"
7124	"Brand ID: %#05x\n",
7125	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
7126	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
7127	ASMGetCpuStepping(uEAX),
7128	pCurLeaf->uEbx & 0xfff);
7129
7130	if (iVerbosity == 1)
7131	{
7132	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
7133	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
7134	}
7135	else
7136	{
7137	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7138	pHlp->pfnPrintf(pHlp, "Ext Features\n");
7139	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
7140	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
7141	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
7142	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
7143	{
7144	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
7145	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7146	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
7147	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
7148	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
7149	}
7150	}
7151	}
7152
7153	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
7154	{
7155	char szString[443+1] = {0};
7156	uint32_t pu32 = (uint32_t )szString;
7157	*pu32++ = pCurLeaf->uEax;
7158	*pu32++ = pCurLeaf->uEbx;
7159	*pu32++ = pCurLeaf->uEcx;
7160	*pu32++ = pCurLeaf->uEdx;
7161	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
7162	if (pCurLeaf)
7163	{
7164	*pu32++ = pCurLeaf->uEax;
7165	*pu32++ = pCurLeaf->uEbx;
7166	*pu32++ = pCurLeaf->uEcx;
7167	*pu32++ = pCurLeaf->uEdx;
7168	}
7169	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
7170	if (pCurLeaf)
7171	{
7172	*pu32++ = pCurLeaf->uEax;
7173	*pu32++ = pCurLeaf->uEbx;
7174	*pu32++ = pCurLeaf->uEcx;
7175	*pu32++ = pCurLeaf->uEdx;
7176	}
7177	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
7178	}
7179
7180	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
7181	{
7182	uint32_t uEAX = pCurLeaf->uEax;
7183	uint32_t uEBX = pCurLeaf->uEbx;
7184	uint32_t uECX = pCurLeaf->uEcx;
7185	uint32_t uEDX = pCurLeaf->uEdx;
7186	char sz1[32];
7187	char sz2[32];
7188
7189	pHlp->pfnPrintf(pHlp,
7190	"TLB 2/4M Instr/Uni: %s %3d entries\n"
7191	"TLB 2/4M Data: %s %3d entries\n",
7192	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
7193	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
7194	pHlp->pfnPrintf(pHlp,
7195	"TLB 4K Instr/Uni: %s %3d entries\n"
7196	"TLB 4K Data: %s %3d entries\n",
7197	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
7198	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
7199	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
7200	"L1 Instr Cache Lines Per Tag: %d\n"
7201	"L1 Instr Cache Associativity: %s\n"
7202	"L1 Instr Cache Size: %d KB\n",
7203	(uEDX >> 0) & 0xff,
7204	(uEDX >> 8) & 0xff,
7205	getCacheAss((uEDX >> 16) & 0xff, sz1),
7206	(uEDX >> 24) & 0xff);
7207	pHlp->pfnPrintf(pHlp,
7208	"L1 Data Cache Line Size: %d bytes\n"
7209	"L1 Data Cache Lines Per Tag: %d\n"
7210	"L1 Data Cache Associativity: %s\n"
7211	"L1 Data Cache Size: %d KB\n",
7212	(uECX >> 0) & 0xff,
7213	(uECX >> 8) & 0xff,
7214	getCacheAss((uECX >> 16) & 0xff, sz1),
7215	(uECX >> 24) & 0xff);
7216	}
7217
7218	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
7219	{
7220	uint32_t uEAX = pCurLeaf->uEax;
7221	uint32_t uEBX = pCurLeaf->uEbx;
7222	uint32_t uEDX = pCurLeaf->uEdx;
7223
7224	pHlp->pfnPrintf(pHlp,
7225	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
7226	"L2 TLB 2/4M Data: %s %4d entries\n",
7227	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
7228	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
7229	pHlp->pfnPrintf(pHlp,
7230	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
7231	"L2 TLB 4K Data: %s %4d entries\n",
7232	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
7233	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
7234	pHlp->pfnPrintf(pHlp,
7235	"L2 Cache Line Size: %d bytes\n"
7236	"L2 Cache Lines Per Tag: %d\n"
7237	"L2 Cache Associativity: %s\n"
7238	"L2 Cache Size: %d KB\n",
7239	(uEDX >> 0) & 0xff,
7240	(uEDX >> 8) & 0xf,
7241	getL2CacheAss((uEDX >> 12) & 0xf),
7242	(uEDX >> 16) & 0xffff);
7243	}
7244
7245	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
7246	{
7247	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7248	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
7249	{
7250	if (iVerbosity < 1)
7251	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7252	else
7253	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7254	}
7255	}
7256
7257	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7258	if (pCurLeaf != NULL)
7259	{
7260	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7261	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7262	{
7263	if (iVerbosity < 1)
7264	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7265	else
7266	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7267	}
7268
7269	if (iVerbosity)
7270	{
7271	uint32_t uEAX = pCurLeaf->uEax;
7272	uint32_t uECX = pCurLeaf->uEcx;
7273
7274	pHlp->pfnPrintf(pHlp,
7275	"Physical Address Width: %d bits\n"
7276	"Virtual Address Width: %d bits\n"
7277	"Guest Physical Address Width: %d bits\n",
7278	(uEAX >> 0) & 0xff,
7279	(uEAX >> 8) & 0xff,
7280	(uEAX >> 16) & 0xff);
7281	pHlp->pfnPrintf(pHlp,
7282	"Physical Core Count: %d\n",
7283	((uECX >> 0) & 0xff) + 1);
7284	}
7285	}
7286
7287	pCurLeaf = pNextLeaf;
7288	}
7289
7290
7291
7292	/*
7293	* Centaur.
7294	*/
7295	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7296
7297	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7298	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7299	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7300	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7301	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7302	cMax = RT_MAX(cHstMax, cGstMax);
7303	if (cMax >= UINT32_C(0xc0000000))
7304	{
7305	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7306
7307	/*
7308	* Understandable output
7309	*/
7310	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7311	pHlp->pfnPrintf(pHlp,
7312	"Centaur Supports: 0xc0000000-%#010x\n",
7313	pCurLeaf->uEax);
7314
7315	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7316	{
7317	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7318	uint32_t uEdxGst = pCurLeaf->uEdx;
7319	uint32_t uEdxHst = Host.uEdx;
7320
7321	if (iVerbosity == 1)
7322	{
7323	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7324	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7325	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7326	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7327	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7328	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7329	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7330	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7331	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7332	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7333	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7334	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7335	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7336	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7337	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7338	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7339	for (unsigned iBit = 14; iBit < 32; iBit++)
7340	if (uEdxGst & RT_BIT(iBit))
7341	pHlp->pfnPrintf(pHlp, " %d", iBit);
7342	pHlp->pfnPrintf(pHlp, "\n");
7343	}
7344	else
7345	{
7346	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7347	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7348	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7349	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7350	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7351	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7352	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7353	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7354	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7355	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7356	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7357	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7358	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7359	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7360	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7361	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7362	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7363	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7364	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7365	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7366	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7367	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7368	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7369	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7370	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7371	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7372	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7373	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7374	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7375	for (unsigned iBit = 27; iBit < 32; iBit++)
7376	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7377	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7378	pHlp->pfnPrintf(pHlp, "\n");
7379	}
7380	}
7381
7382	pCurLeaf = pNextLeaf;
7383	}
7384
7385	/*
7386	* The remainder.
7387	*/
7388	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7389	}
7390
7391
7392
7393
7394
7395	/*
7396	*
7397	*
7398	* PATM interfaces.
7399	* PATM interfaces.
7400	* PATM interfaces.
7401	*
7402	*
7403	*/
7404
7405
7406	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
7407	/** @name Patchmanager CPUID legacy table APIs
7408	* @{
7409	*/
7410
7411	/**
7412	* Gets a pointer to the default CPUID leaf.
7413	*
7414	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
7415	* @param pVM The cross context VM structure.
7416	* @remark Intended for PATM only.
7417	*/
7418	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
7419	{
7420	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
7421	}
7422
7423
7424	/**
7425	* Gets a number of standard CPUID leaves (PATM only).
7426	*
7427	* @returns Number of leaves.
7428	* @param pVM The cross context VM structure.
7429	* @remark Intended for PATM - legacy, don't use in new code.
7430	*/
7431	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
7432	{
7433	RT_NOREF_PV(pVM);
7434	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
7435	}
7436
7437
7438	/**
7439	* Gets a number of extended CPUID leaves (PATM only).
7440	*
7441	* @returns Number of leaves.
7442	* @param pVM The cross context VM structure.
7443	* @remark Intended for PATM - legacy, don't use in new code.
7444	*/
7445	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
7446	{
7447	RT_NOREF_PV(pVM);
7448	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
7449	}
7450
7451
7452	/**
7453	* Gets a number of centaur CPUID leaves.
7454	*
7455	* @returns Number of leaves.
7456	* @param pVM The cross context VM structure.
7457	* @remark Intended for PATM - legacy, don't use in new code.
7458	*/
7459	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
7460	{
7461	RT_NOREF_PV(pVM);
7462	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
7463	}
7464
7465
7466	/**
7467	* Gets a pointer to the array of standard CPUID leaves.
7468	*
7469	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
7470	*
7471	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
7472	* @param pVM The cross context VM structure.
7473	* @remark Intended for PATM - legacy, don't use in new code.
7474	*/
7475	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
7476	{
7477	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
7478	}
7479
7480
7481	/**
7482	* Gets a pointer to the array of extended CPUID leaves.
7483	*
7484	* CPUMGetGuestCpuIdExtMax() give the size of the array.
7485	*
7486	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
7487	* @param pVM The cross context VM structure.
7488	* @remark Intended for PATM - legacy, don't use in new code.
7489	*/
7490	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
7491	{
7492	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
7493	}
7494
7495
7496	/**
7497	* Gets a pointer to the array of centaur CPUID leaves.
7498	*
7499	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
7500	*
7501	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
7502	* @param pVM The cross context VM structure.
7503	* @remark Intended for PATM - legacy, don't use in new code.
7504	*/
7505	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
7506	{
7507	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
7508	}
7509
7510	/** @} */
7511	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
7512
7513	#endif /* VBOX_IN_VMM */
7514

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 79345

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