CPUMR3CpuId.cpp@ 80074

Last change on this file since 80074 was 80064, checked in by vboxsync, 5 years ago
VMM: Kicking out raw-mode and 32-bit hosts - CPUM. bugref:9517 bugref:9511
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1	/* $Id: CPUMR3CpuId.cpp 80064 2019-07-31 10:31:36Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/mm.h>
31	#include <VBox/sup.h>
32
33	#include <VBox/err.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/ctype.h>
36	#include <iprt/mem.h>
37	#include <iprt/string.h>
38
39
40	/*********************************************************************************************************************************
41	* Defined Constants And Macros *
42	*********************************************************************************************************************************/
43	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
44	#define CPUM_CPUID_MAX_LEAVES 2048
45	/* Max size we accept for the XSAVE area. */
46	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
47	/* Min size we accept for the XSAVE area. */
48	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
49
50
51	/*********************************************************************************************************************************
52	* Global Variables *
53	*********************************************************************************************************************************/
54	/**
55	* The intel pentium family.
56	*/
57	static const CPUMMICROARCH g_aenmIntelFamily06[] =
58	{
59	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
60	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
61	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
63	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
64	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
65	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
66	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
67	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
68	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
69	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
70	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
71	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
72	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
73	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
74	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
75	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
81	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
82	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
83	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [26(0x1a)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Nehalem-EP */
86	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
88	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
89	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
90	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
91	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
97	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
98	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
99	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
102	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
104	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
105	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
106	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
107	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
113	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
114	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
115	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
118	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
121	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
122	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
130	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
131	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
136	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,
138	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Broadwell-E */
139	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu; skylake <= 4, cascade lake > 5 */
145	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
146	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
147	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
150	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
152	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
153	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
154	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
155	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
159	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
160	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
161	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
162	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
163	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
164	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
165	/[106(0x6a)] = / kCpumMicroarch_Intel_Unknown,
166	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
167	/[108(0x6c)] = / kCpumMicroarch_Intel_Unknown,
168	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
169	/[110(0x6e)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
170	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
171	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
172	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
173	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
174	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
175	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
176	/[117(0x75)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
177	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
178	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
179	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
180	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
181	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
182	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
183	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
184	/[125(0x7d)] = / kCpumMicroarch_Intel_Unknown,
185	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
186	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
187	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
188	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
189	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
190	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
191	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
192	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
193	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
194	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
195	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
196	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
197	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
198	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
199	/[140(0x8c)] = / kCpumMicroarch_Intel_Unknown,
200	/[141(0x8d)] = / kCpumMicroarch_Intel_Unknown,
201	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
202	/[143(0x8f)] = / kCpumMicroarch_Intel_Unknown,
203	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
204	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
205	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
206	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
207	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
208	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
209	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
210	/[151(0x97)] = / kCpumMicroarch_Intel_Unknown,
211	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
212	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
213	/[154(0x9a)] = / kCpumMicroarch_Intel_Unknown,
214	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
215	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
216	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
217	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
218	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
219	};
220	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0x9f+1);
221
222
223	/**
224	* Figures out the (sub-)micro architecture given a bit of CPUID info.
225	*
226	* @returns Micro architecture.
227	* @param enmVendor The CPU vendor .
228	* @param bFamily The CPU family.
229	* @param bModel The CPU model.
230	* @param bStepping The CPU stepping.
231	*/
232	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
233	uint8_t bModel, uint8_t bStepping)
234	{
235	if (enmVendor == CPUMCPUVENDOR_AMD)
236	{
237	switch (bFamily)
238	{
239	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
240	case 0x03: return kCpumMicroarch_AMD_Am386;
241	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
242	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
243	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
244	case 0x06:
245	switch (bModel)
246	{
247	case 0: return kCpumMicroarch_AMD_K7_Palomino;
248	case 1: return kCpumMicroarch_AMD_K7_Palomino;
249	case 2: return kCpumMicroarch_AMD_K7_Palomino;
250	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
251	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
252	case 6: return kCpumMicroarch_AMD_K7_Palomino;
253	case 7: return kCpumMicroarch_AMD_K7_Morgan;
254	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
255	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
256	}
257	return kCpumMicroarch_AMD_K7_Unknown;
258	case 0x0f:
259	/*
260	* This family is a friggin mess. Trying my best to make some
261	* sense out of it. Too much happened in the 0x0f family to
262	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
263	*
264	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
265	* cpu-world.com, and other places:
266	* - 130nm:
267	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
268	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
269	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
270	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
271	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
272	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
273	* - 90nm:
274	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
275	* - Oakville: 10FC0/DH-D0.
276	* - Georgetown: 10FC0/DH-D0.
277	* - Sonora: 10FC0/DH-D0.
278	* - Venus: 20F71/SH-E4
279	* - Troy: 20F51/SH-E4
280	* - Athens: 20F51/SH-E4
281	* - San Diego: 20F71/SH-E4.
282	* - Lancaster: 20F42/SH-E5
283	* - Newark: 20F42/SH-E5.
284	* - Albany: 20FC2/DH-E6.
285	* - Roma: 20FC2/DH-E6.
286	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
287	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
288	* - 90nm introducing Dual core:
289	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
290	* - Italy: 20F10/JH-E1, 20F12/JH-E6
291	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
292	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
293	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
294	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
295	* - Santa Ana: 40F32/JH-F2, /-F3
296	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
297	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
298	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
299	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
300	* - Keene: 40FC2/DH-F2.
301	* - Richmond: 40FC2/DH-F2
302	* - Taylor: 40F82/BH-F2
303	* - Trinidad: 40F82/BH-F2
304	*
305	* - 65nm:
306	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
307	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
308	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
309	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
310	* - Sherman: /-G1, 70FC2/DH-G2.
311	* - Huron: 70FF2/DH-G2.
312	*/
313	if (bModel < 0x10)
314	return kCpumMicroarch_AMD_K8_130nm;
315	if (bModel >= 0x60 && bModel < 0x80)
316	return kCpumMicroarch_AMD_K8_65nm;
317	if (bModel >= 0x40)
318	return kCpumMicroarch_AMD_K8_90nm_AMDV;
319	switch (bModel)
320	{
321	case 0x21:
322	case 0x23:
323	case 0x2b:
324	case 0x2f:
325	case 0x37:
326	case 0x3f:
327	return kCpumMicroarch_AMD_K8_90nm_DualCore;
328	}
329	return kCpumMicroarch_AMD_K8_90nm;
330	case 0x10:
331	return kCpumMicroarch_AMD_K10;
332	case 0x11:
333	return kCpumMicroarch_AMD_K10_Lion;
334	case 0x12:
335	return kCpumMicroarch_AMD_K10_Llano;
336	case 0x14:
337	return kCpumMicroarch_AMD_Bobcat;
338	case 0x15:
339	switch (bModel)
340	{
341	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
342	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
343	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
344	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
345	case 0x11: /* ?? */
346	case 0x12: /* ?? */
347	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
348	}
349	return kCpumMicroarch_AMD_15h_Unknown;
350	case 0x16:
351	return kCpumMicroarch_AMD_Jaguar;
352	case 0x17:
353	return kCpumMicroarch_AMD_Zen_Ryzen;
354	}
355	return kCpumMicroarch_AMD_Unknown;
356	}
357
358	if (enmVendor == CPUMCPUVENDOR_INTEL)
359	{
360	switch (bFamily)
361	{
362	case 3:
363	return kCpumMicroarch_Intel_80386;
364	case 4:
365	return kCpumMicroarch_Intel_80486;
366	case 5:
367	return kCpumMicroarch_Intel_P5;
368	case 6:
369	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
370	{
371	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
372	if (enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake)
373	{
374	if (bStepping >= 0xa && bStepping <= 0xc)
375	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
376	else if (bStepping >= 0xc)
377	enmMicroArch = kCpumMicroarch_Intel_Core7_WhiskeyLake;
378	}
379	else if ( enmMicroArch == kCpumMicroarch_Intel_Core7_Skylake
380	&& bModel == 0x55
381	&& bStepping >= 5)
382	enmMicroArch = kCpumMicroarch_Intel_Core7_CascadeLake;
383	return enmMicroArch;
384	}
385	return kCpumMicroarch_Intel_Atom_Unknown;
386	case 15:
387	switch (bModel)
388	{
389	case 0: return kCpumMicroarch_Intel_NB_Willamette;
390	case 1: return kCpumMicroarch_Intel_NB_Willamette;
391	case 2: return kCpumMicroarch_Intel_NB_Northwood;
392	case 3: return kCpumMicroarch_Intel_NB_Prescott;
393	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
394	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
395	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
396	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
397	default: return kCpumMicroarch_Intel_NB_Unknown;
398	}
399	break;
400	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
401	case 0:
402	return kCpumMicroarch_Intel_8086;
403	case 1:
404	return kCpumMicroarch_Intel_80186;
405	case 2:
406	return kCpumMicroarch_Intel_80286;
407	}
408	return kCpumMicroarch_Intel_Unknown;
409	}
410
411	if (enmVendor == CPUMCPUVENDOR_VIA)
412	{
413	switch (bFamily)
414	{
415	case 5:
416	switch (bModel)
417	{
418	case 1: return kCpumMicroarch_Centaur_C6;
419	case 4: return kCpumMicroarch_Centaur_C6;
420	case 8: return kCpumMicroarch_Centaur_C2;
421	case 9: return kCpumMicroarch_Centaur_C3;
422	}
423	break;
424
425	case 6:
426	switch (bModel)
427	{
428	case 5: return kCpumMicroarch_VIA_C3_M2;
429	case 6: return kCpumMicroarch_VIA_C3_C5A;
430	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
431	case 8: return kCpumMicroarch_VIA_C3_C5N;
432	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
433	case 10: return kCpumMicroarch_VIA_C7_C5J;
434	case 15: return kCpumMicroarch_VIA_Isaiah;
435	}
436	break;
437	}
438	return kCpumMicroarch_VIA_Unknown;
439	}
440
441	if (enmVendor == CPUMCPUVENDOR_SHANGHAI)
442	{
443	switch (bFamily)
444	{
445	case 6:
446	case 7:
447	return kCpumMicroarch_Shanghai_Wudaokou;
448	default:
449	break;
450	}
451	return kCpumMicroarch_Shanghai_Unknown;
452	}
453
454	if (enmVendor == CPUMCPUVENDOR_CYRIX)
455	{
456	switch (bFamily)
457	{
458	case 4:
459	switch (bModel)
460	{
461	case 9: return kCpumMicroarch_Cyrix_5x86;
462	}
463	break;
464
465	case 5:
466	switch (bModel)
467	{
468	case 2: return kCpumMicroarch_Cyrix_M1;
469	case 4: return kCpumMicroarch_Cyrix_MediaGX;
470	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
471	}
472	break;
473
474	case 6:
475	switch (bModel)
476	{
477	case 0: return kCpumMicroarch_Cyrix_M2;
478	}
479	break;
480
481	}
482	return kCpumMicroarch_Cyrix_Unknown;
483	}
484
485	return kCpumMicroarch_Unknown;
486	}
487
488
489	/**
490	* Translates a microarchitecture enum value to the corresponding string
491	* constant.
492	*
493	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
494	* NULL if the value is invalid.
495	*
496	* @param enmMicroarch The enum value to convert.
497	*/
498	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
499	{
500	switch (enmMicroarch)
501	{
502	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
503	CASE_RET_STR(kCpumMicroarch_Intel_8086);
504	CASE_RET_STR(kCpumMicroarch_Intel_80186);
505	CASE_RET_STR(kCpumMicroarch_Intel_80286);
506	CASE_RET_STR(kCpumMicroarch_Intel_80386);
507	CASE_RET_STR(kCpumMicroarch_Intel_80486);
508	CASE_RET_STR(kCpumMicroarch_Intel_P5);
509
510	CASE_RET_STR(kCpumMicroarch_Intel_P6);
511	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
512	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
513
514	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
515	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
516	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
517
518	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
519	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
520
521	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
522	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
523	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
524	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
525	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
526	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
527	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
528	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
529	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
530	CASE_RET_STR(kCpumMicroarch_Intel_Core7_WhiskeyLake);
531	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CascadeLake);
532	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
533	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
534	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
535
536	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
537	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
538	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
539	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
540	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
541	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
542	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
543	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
544
545	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
546	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
547	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
548	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
549	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
550
551	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
552	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
553	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
554	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
555	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
556	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
557	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
558
559	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
560
561	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
562	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
563	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
564	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
565	CASE_RET_STR(kCpumMicroarch_AMD_K5);
566	CASE_RET_STR(kCpumMicroarch_AMD_K6);
567
568	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
569	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
570	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
571	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
572	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
573	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
574	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
575
576	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
577	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
578	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
579	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
580	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
581
582	CASE_RET_STR(kCpumMicroarch_AMD_K10);
583	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
584	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
585	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
586	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
587
588	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
589	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
590	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
591	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
592	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
593
594	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
595
596	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
597
598	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
599
600	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
601	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
602	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
603	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
604	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
605	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
606	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
607	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
608	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
609	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
610	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
611	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
612	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
613
614	CASE_RET_STR(kCpumMicroarch_Shanghai_Wudaokou);
615	CASE_RET_STR(kCpumMicroarch_Shanghai_Unknown);
616
617	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
618	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
619	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
620	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
621	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
622	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
623
624	CASE_RET_STR(kCpumMicroarch_NEC_V20);
625	CASE_RET_STR(kCpumMicroarch_NEC_V30);
626
627	CASE_RET_STR(kCpumMicroarch_Unknown);
628
629	#undef CASE_RET_STR
630	case kCpumMicroarch_Invalid:
631	case kCpumMicroarch_Intel_End:
632	case kCpumMicroarch_Intel_Core2_End:
633	case kCpumMicroarch_Intel_Core7_End:
634	case kCpumMicroarch_Intel_Atom_End:
635	case kCpumMicroarch_Intel_P6_Core_Atom_End:
636	case kCpumMicroarch_Intel_Phi_End:
637	case kCpumMicroarch_Intel_NB_End:
638	case kCpumMicroarch_AMD_K7_End:
639	case kCpumMicroarch_AMD_K8_End:
640	case kCpumMicroarch_AMD_15h_End:
641	case kCpumMicroarch_AMD_16h_End:
642	case kCpumMicroarch_AMD_Zen_End:
643	case kCpumMicroarch_AMD_End:
644	case kCpumMicroarch_VIA_End:
645	case kCpumMicroarch_Cyrix_End:
646	case kCpumMicroarch_NEC_End:
647	case kCpumMicroarch_Shanghai_End:
648	case kCpumMicroarch_32BitHack:
649	break;
650	/* no default! */
651	}
652
653	return NULL;
654	}
655
656
657	/**
658	* Determins the host CPU MXCSR mask.
659	*
660	* @returns MXCSR mask.
661	*/
662	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
663	{
664	if ( ASMHasCpuId()
665	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
666	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
667	{
668	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
669	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
670	RT_ZERO(*pState);
671	ASMFxSave(pState);
672	if (pState->MXCSR_MASK == 0)
673	return 0xffbf;
674	return pState->MXCSR_MASK;
675	}
676	return 0;
677	}
678
679
680	/**
681	* Gets a matching leaf in the CPUID leaf array.
682	*
683	* @returns Pointer to the matching leaf, or NULL if not found.
684	* @param paLeaves The CPUID leaves to search. This is sorted.
685	* @param cLeaves The number of leaves in the array.
686	* @param uLeaf The leaf to locate.
687	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
688	*/
689	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
690	{
691	/* Lazy bird does linear lookup here since this is only used for the
692	occational CPUID overrides. */
693	for (uint32_t i = 0; i < cLeaves; i++)
694	if ( paLeaves[i].uLeaf == uLeaf
695	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
696	return &paLeaves[i];
697	return NULL;
698	}
699
700
701	#ifndef IN_VBOX_CPU_REPORT
702	/**
703	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
704	*
705	* @returns true if found, false it not.
706	* @param paLeaves The CPUID leaves to search. This is sorted.
707	* @param cLeaves The number of leaves in the array.
708	* @param uLeaf The leaf to locate.
709	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
710	* @param pLegacy The legacy output leaf.
711	*/
712	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
713	PCPUMCPUID pLegacy)
714	{
715	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
716	if (pLeaf)
717	{
718	pLegacy->uEax = pLeaf->uEax;
719	pLegacy->uEbx = pLeaf->uEbx;
720	pLegacy->uEcx = pLeaf->uEcx;
721	pLegacy->uEdx = pLeaf->uEdx;
722	return true;
723	}
724	return false;
725	}
726	#endif /* IN_VBOX_CPU_REPORT */
727
728
729	/**
730	* Ensures that the CPUID leaf array can hold one more leaf.
731	*
732	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
733	* failure.
734	* @param pVM The cross context VM structure. If NULL, use
735	* the process heap, otherwise the VM's hyper heap.
736	* @param ppaLeaves Pointer to the variable holding the array pointer
737	* (input/output).
738	* @param cLeaves The current array size.
739	*
740	* @remarks This function will automatically update the R0 and RC pointers when
741	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
742	* be the corresponding VM's CPUID arrays (which is asserted).
743	*/
744	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
745	{
746	/*
747	* If pVM is not specified, we're on the regular heap and can waste a
748	* little space to speed things up.
749	*/
750	uint32_t cAllocated;
751	if (!pVM)
752	{
753	cAllocated = RT_ALIGN(cLeaves, 16);
754	if (cLeaves + 1 > cAllocated)
755	{
756	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
757	if (pvNew)
758	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
759	else
760	{
761	RTMemFree(*ppaLeaves);
762	*ppaLeaves = NULL;
763	}
764	}
765	}
766	/*
767	* Otherwise, we're on the hyper heap and are probably just inserting
768	* one or two leaves and should conserve space.
769	*/
770	else
771	{
772	#ifdef IN_VBOX_CPU_REPORT
773	AssertReleaseFailed();
774	#else
775	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
776	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
777
778	size_t cb = cLeaves * sizeof(**ppaLeaves);
779	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
780	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
781	if (RT_SUCCESS(rc))
782	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
783	else
784	{
785	*ppaLeaves = NULL;
786	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
787	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
788	}
789	#endif
790	}
791	return *ppaLeaves;
792	}
793
794
795	/**
796	* Append a CPUID leaf or sub-leaf.
797	*
798	* ASSUMES linear insertion order, so we'll won't need to do any searching or
799	* replace anything. Use cpumR3CpuIdInsert() for those cases.
800	*
801	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
802	* the caller need do no more work.
803	* @param ppaLeaves Pointer to the pointer to the array of sorted
804	* CPUID leaves and sub-leaves.
805	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
806	* @param uLeaf The leaf we're adding.
807	* @param uSubLeaf The sub-leaf number.
808	* @param fSubLeafMask The sub-leaf mask.
809	* @param uEax The EAX value.
810	* @param uEbx The EBX value.
811	* @param uEcx The ECX value.
812	* @param uEdx The EDX value.
813	* @param fFlags The flags.
814	*/
815	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
816	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
817	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
818	{
819	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
820	return VERR_NO_MEMORY;
821
822	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
823	Assert( *pcLeaves == 0
824	\|\| pNew[-1].uLeaf < uLeaf
825	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
826
827	pNew->uLeaf = uLeaf;
828	pNew->uSubLeaf = uSubLeaf;
829	pNew->fSubLeafMask = fSubLeafMask;
830	pNew->uEax = uEax;
831	pNew->uEbx = uEbx;
832	pNew->uEcx = uEcx;
833	pNew->uEdx = uEdx;
834	pNew->fFlags = fFlags;
835
836	*pcLeaves += 1;
837	return VINF_SUCCESS;
838	}
839
840
841	/**
842	* Checks that we've updated the CPUID leaves array correctly.
843	*
844	* This is a no-op in non-strict builds.
845	*
846	* @param paLeaves The leaves array.
847	* @param cLeaves The number of leaves.
848	*/
849	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
850	{
851	#ifdef VBOX_STRICT
852	for (uint32_t i = 1; i < cLeaves; i++)
853	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
854	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
855	else
856	{
857	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
858	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
859	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
860	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
861	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
862	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
863	}
864	#else
865	NOREF(paLeaves);
866	NOREF(cLeaves);
867	#endif
868	}
869
870
871	/**
872	* Inserts a CPU ID leaf, replacing any existing ones.
873	*
874	* When inserting a simple leaf where we already got a series of sub-leaves with
875	* the same leaf number (eax), the simple leaf will replace the whole series.
876	*
877	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
878	* host-context heap and has only been allocated/reallocated by the
879	* cpumR3CpuIdEnsureSpace function.
880	*
881	* @returns VBox status code.
882	* @param pVM The cross context VM structure. If NULL, use
883	* the process heap, otherwise the VM's hyper heap.
884	* @param ppaLeaves Pointer to the pointer to the array of sorted
885	* CPUID leaves and sub-leaves. Must be NULL if using
886	* the hyper heap.
887	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
888	* be NULL if using the hyper heap.
889	* @param pNewLeaf Pointer to the data of the new leaf we're about to
890	* insert.
891	*/
892	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
893	{
894	/*
895	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
896	*/
897	if (pVM)
898	{
899	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
900	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
901
902	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
903	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
904	}
905
906	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
907	uint32_t cLeaves = *pcLeaves;
908
909	/*
910	* Validate the new leaf a little.
911	*/
912	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
913	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
914	VERR_INVALID_FLAGS);
915	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
916	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
917	VERR_INVALID_PARAMETER);
918	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
919	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
920	VERR_INVALID_PARAMETER);
921	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
922	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
923	VERR_INVALID_PARAMETER);
924
925	/*
926	* Find insertion point. The lazy bird uses the same excuse as in
927	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
928	*/
929	uint32_t i;
930	if ( cLeaves > 0
931	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
932	{
933	/* Add at end. */
934	i = cLeaves;
935	}
936	else if ( cLeaves > 0
937	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
938	{
939	/* Either replacing the last leaf or dealing with sub-leaves. Spool
940	back to the first sub-leaf to pretend we did the linear search. */
941	i = cLeaves - 1;
942	while ( i > 0
943	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
944	i--;
945	}
946	else
947	{
948	/* Linear search from the start. */
949	i = 0;
950	while ( i < cLeaves
951	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
952	i++;
953	}
954	if ( i < cLeaves
955	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
956	{
957	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
958	{
959	/*
960	* The sub-leaf mask differs, replace all existing leaves with the
961	* same leaf number.
962	*/
963	uint32_t c = 1;
964	while ( i + c < cLeaves
965	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
966	c++;
967	if (c > 1 && i + c < cLeaves)
968	{
969	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
970	*pcLeaves = cLeaves -= c - 1;
971	}
972
973	paLeaves[i] = *pNewLeaf;
974	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
975	return VINF_SUCCESS;
976	}
977
978	/* Find sub-leaf insertion point. */
979	while ( i < cLeaves
980	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
981	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
982	i++;
983
984	/*
985	* If we've got an exactly matching leaf, replace it.
986	*/
987	if ( i < cLeaves
988	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
989	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
990	{
991	paLeaves[i] = *pNewLeaf;
992	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
993	return VINF_SUCCESS;
994	}
995	}
996
997	/*
998	* Adding a new leaf at 'i'.
999	*/
1000	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
1001	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
1002	if (!paLeaves)
1003	return VERR_NO_MEMORY;
1004
1005	if (i < cLeaves)
1006	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
1007	*pcLeaves += 1;
1008	paLeaves[i] = *pNewLeaf;
1009
1010	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1011	return VINF_SUCCESS;
1012	}
1013
1014
1015	#ifndef IN_VBOX_CPU_REPORT
1016	/**
1017	* Removes a range of CPUID leaves.
1018	*
1019	* This will not reallocate the array.
1020	*
1021	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1022	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1023	* @param uFirst The first leaf.
1024	* @param uLast The last leaf.
1025	*/
1026	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1027	{
1028	uint32_t cLeaves = *pcLeaves;
1029
1030	Assert(uFirst <= uLast);
1031
1032	/*
1033	* Find the first one.
1034	*/
1035	uint32_t iFirst = 0;
1036	while ( iFirst < cLeaves
1037	&& paLeaves[iFirst].uLeaf < uFirst)
1038	iFirst++;
1039
1040	/*
1041	* Find the end (last + 1).
1042	*/
1043	uint32_t iEnd = iFirst;
1044	while ( iEnd < cLeaves
1045	&& paLeaves[iEnd].uLeaf <= uLast)
1046	iEnd++;
1047
1048	/*
1049	* Adjust the array if anything needs removing.
1050	*/
1051	if (iFirst < iEnd)
1052	{
1053	if (iEnd < cLeaves)
1054	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1055	*pcLeaves = cLeaves -= (iEnd - iFirst);
1056	}
1057
1058	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1059	}
1060	#endif /* IN_VBOX_CPU_REPORT */
1061
1062
1063	/**
1064	* Checks if ECX make a difference when reading a given CPUID leaf.
1065	*
1066	* @returns @c true if it does, @c false if it doesn't.
1067	* @param uLeaf The leaf we're reading.
1068	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1069	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1070	* final sub-leaf (for leaf 0xb only).
1071	*/
1072	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1073	{
1074	*pfFinalEcxUnchanged = false;
1075
1076	uint32_t auCur[4];
1077	uint32_t auPrev[4];
1078	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1079
1080	/* Look for sub-leaves. */
1081	uint32_t uSubLeaf = 1;
1082	for (;;)
1083	{
1084	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1085	if (memcmp(auCur, auPrev, sizeof(auCur)))
1086	break;
1087
1088	/* Advance / give up. */
1089	uSubLeaf++;
1090	if (uSubLeaf >= 64)
1091	{
1092	*pcSubLeaves = 1;
1093	return false;
1094	}
1095	}
1096
1097	/* Count sub-leaves. */
1098	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1099	uint32_t cRepeats = 0;
1100	uSubLeaf = 0;
1101	for (;;)
1102	{
1103	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1104
1105	/* Figuring out when to stop isn't entirely straight forward as we need
1106	to cover undocumented behavior up to a point and implementation shortcuts. */
1107
1108	/* 1. Look for more than 4 repeating value sets. */
1109	if ( auCur[0] == auPrev[0]
1110	&& auCur[1] == auPrev[1]
1111	&& ( auCur[2] == auPrev[2]
1112	\|\| ( auCur[2] == uSubLeaf
1113	&& auPrev[2] == uSubLeaf - 1) )
1114	&& auCur[3] == auPrev[3])
1115	{
1116	if ( uLeaf != 0xd
1117	\|\| uSubLeaf >= 64
1118	\|\| ( auCur[0] == 0
1119	&& auCur[1] == 0
1120	&& auCur[2] == 0
1121	&& auCur[3] == 0
1122	&& auPrev[2] == 0) )
1123	cRepeats++;
1124	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1125	break;
1126	}
1127	else
1128	cRepeats = 0;
1129
1130	/* 2. Look for zero values. */
1131	if ( auCur[0] == 0
1132	&& auCur[1] == 0
1133	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1134	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1135	&& uSubLeaf >= cMinLeaves)
1136	{
1137	cRepeats = 0;
1138	break;
1139	}
1140
1141	/* 3. Leaf 0xb level type 0 check. */
1142	if ( uLeaf == 0xb
1143	&& (auCur[2] & 0xff00) == 0
1144	&& (auPrev[2] & 0xff00) == 0)
1145	{
1146	cRepeats = 0;
1147	break;
1148	}
1149
1150	/* 99. Give up. */
1151	if (uSubLeaf >= 128)
1152	{
1153	#ifndef IN_VBOX_CPU_REPORT
1154	/* Ok, limit it according to the documentation if possible just to
1155	avoid annoying users with these detection issues. */
1156	uint32_t cDocLimit = UINT32_MAX;
1157	if (uLeaf == 0x4)
1158	cDocLimit = 4;
1159	else if (uLeaf == 0x7)
1160	cDocLimit = 1;
1161	else if (uLeaf == 0xd)
1162	cDocLimit = 63;
1163	else if (uLeaf == 0xf)
1164	cDocLimit = 2;
1165	if (cDocLimit != UINT32_MAX)
1166	{
1167	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1168	*pcSubLeaves = cDocLimit + 3;
1169	return true;
1170	}
1171	#endif
1172	*pcSubLeaves = UINT32_MAX;
1173	return true;
1174	}
1175
1176	/* Advance. */
1177	uSubLeaf++;
1178	memcpy(auPrev, auCur, sizeof(auCur));
1179	}
1180
1181	/* Standard exit. */
1182	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1183	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1184	if (*pcSubLeaves == 0)
1185	*pcSubLeaves = 1;
1186	return true;
1187	}
1188
1189
1190	/**
1191	* Gets a CPU ID leaf.
1192	*
1193	* @returns VBox status code.
1194	* @param pVM The cross context VM structure.
1195	* @param pLeaf Where to store the found leaf.
1196	* @param uLeaf The leaf to locate.
1197	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1198	*/
1199	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1200	{
1201	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1202	uLeaf, uSubLeaf);
1203	if (pcLeaf)
1204	{
1205	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1206	return VINF_SUCCESS;
1207	}
1208
1209	return VERR_NOT_FOUND;
1210	}
1211
1212
1213	/**
1214	* Inserts a CPU ID leaf, replacing any existing ones.
1215	*
1216	* @returns VBox status code.
1217	* @param pVM The cross context VM structure.
1218	* @param pNewLeaf Pointer to the leaf being inserted.
1219	*/
1220	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1221	{
1222	/*
1223	* Validate parameters.
1224	*/
1225	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1226	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1227
1228	/*
1229	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1230	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1231	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1232	*/
1233	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1234	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1235	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1236	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1237	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1238	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1239	{
1240	return VERR_NOT_SUPPORTED;
1241	}
1242
1243	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1244	}
1245
1246	/**
1247	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1248	*
1249	* @returns VBox status code.
1250	* @param ppaLeaves Where to return the array pointer on success.
1251	* Use RTMemFree to release.
1252	* @param pcLeaves Where to return the size of the array on
1253	* success.
1254	*/
1255	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1256	{
1257	*ppaLeaves = NULL;
1258	*pcLeaves = 0;
1259
1260	/*
1261	* Try out various candidates. This must be sorted!
1262	*/
1263	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1264	{
1265	{ UINT32_C(0x00000000), false },
1266	{ UINT32_C(0x10000000), false },
1267	{ UINT32_C(0x20000000), false },
1268	{ UINT32_C(0x30000000), false },
1269	{ UINT32_C(0x40000000), false },
1270	{ UINT32_C(0x50000000), false },
1271	{ UINT32_C(0x60000000), false },
1272	{ UINT32_C(0x70000000), false },
1273	{ UINT32_C(0x80000000), false },
1274	{ UINT32_C(0x80860000), false },
1275	{ UINT32_C(0x8ffffffe), true },
1276	{ UINT32_C(0x8fffffff), true },
1277	{ UINT32_C(0x90000000), false },
1278	{ UINT32_C(0xa0000000), false },
1279	{ UINT32_C(0xb0000000), false },
1280	{ UINT32_C(0xc0000000), false },
1281	{ UINT32_C(0xd0000000), false },
1282	{ UINT32_C(0xe0000000), false },
1283	{ UINT32_C(0xf0000000), false },
1284	};
1285
1286	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1287	{
1288	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1289	uint32_t uEax, uEbx, uEcx, uEdx;
1290	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1291
1292	/*
1293	* Does EAX look like a typical leaf count value?
1294	*/
1295	if ( uEax > uLeaf
1296	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1297	{
1298	/* Yes, dump them. */
1299	uint32_t cLeaves = uEax - uLeaf + 1;
1300	while (cLeaves-- > 0)
1301	{
1302	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1303
1304	uint32_t fFlags = 0;
1305
1306	/* There are currently three known leaves containing an APIC ID
1307	that needs EMT specific attention */
1308	if (uLeaf == 1)
1309	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1310	else if (uLeaf == 0xb && uEcx != 0)
1311	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1312	else if ( uLeaf == UINT32_C(0x8000001e)
1313	&& ( uEax
1314	\|\| uEbx
1315	\|\| uEdx
1316	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1317	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1318
1319	/* The APIC bit is per-VCpu and needs flagging. */
1320	if (uLeaf == 1)
1321	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1322	else if ( uLeaf == UINT32_C(0x80000001)
1323	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1324	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1325	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1326
1327	/* Check three times here to reduce the chance of CPU migration
1328	resulting in false positives with things like the APIC ID. */
1329	uint32_t cSubLeaves;
1330	bool fFinalEcxUnchanged;
1331	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1332	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1333	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1334	{
1335	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1336	{
1337	/* This shouldn't happen. But in case it does, file all
1338	relevant details in the release log. */
1339	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1340	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1341	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1342	{
1343	uint32_t auTmp[4];
1344	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1345	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1346	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1347	}
1348	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1349	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1350	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1351	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1352	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1353	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1354	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1355	}
1356
1357	if (fFinalEcxUnchanged)
1358	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1359
1360	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1361	{
1362	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1363	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1364	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1365	if (RT_FAILURE(rc))
1366	return rc;
1367	}
1368	}
1369	else
1370	{
1371	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1372	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1373	if (RT_FAILURE(rc))
1374	return rc;
1375	}
1376
1377	/* next */
1378	uLeaf++;
1379	}
1380	}
1381	/*
1382	* Special CPUIDs needs special handling as they don't follow the
1383	* leaf count principle used above.
1384	*/
1385	else if (s_aCandidates[iOuter].fSpecial)
1386	{
1387	bool fKeep = false;
1388	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1389	fKeep = true;
1390	else if ( uLeaf == 0x8fffffff
1391	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1392	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1393	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1394	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1395	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1396	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1397	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1398	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1399	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1400	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1401	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1402	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1403	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1404	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1405	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1406	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1407	fKeep = true;
1408	if (fKeep)
1409	{
1410	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1411	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1412	if (RT_FAILURE(rc))
1413	return rc;
1414	}
1415	}
1416	}
1417
1418	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1419	return VINF_SUCCESS;
1420	}
1421
1422
1423	/**
1424	* Determines the method the CPU uses to handle unknown CPUID leaves.
1425	*
1426	* @returns VBox status code.
1427	* @param penmUnknownMethod Where to return the method.
1428	* @param pDefUnknown Where to return default unknown values. This
1429	* will be set, even if the resulting method
1430	* doesn't actually needs it.
1431	*/
1432	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1433	{
1434	uint32_t uLastStd = ASMCpuId_EAX(0);
1435	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1436	if (!ASMIsValidExtRange(uLastExt))
1437	uLastExt = 0x80000000;
1438
1439	uint32_t auChecks[] =
1440	{
1441	uLastStd + 1,
1442	uLastStd + 5,
1443	uLastStd + 8,
1444	uLastStd + 32,
1445	uLastStd + 251,
1446	uLastExt + 1,
1447	uLastExt + 8,
1448	uLastExt + 15,
1449	uLastExt + 63,
1450	uLastExt + 255,
1451	0x7fbbffcc,
1452	0x833f7872,
1453	0xefff2353,
1454	0x35779456,
1455	0x1ef6d33e,
1456	};
1457
1458	static const uint32_t s_auValues[] =
1459	{
1460	0xa95d2156,
1461	0x00000001,
1462	0x00000002,
1463	0x00000008,
1464	0x00000000,
1465	0x55773399,
1466	0x93401769,
1467	0x12039587,
1468	};
1469
1470	/*
1471	* Simple method, all zeros.
1472	*/
1473	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1474	pDefUnknown->uEax = 0;
1475	pDefUnknown->uEbx = 0;
1476	pDefUnknown->uEcx = 0;
1477	pDefUnknown->uEdx = 0;
1478
1479	/*
1480	* Intel has been observed returning the last standard leaf.
1481	*/
1482	uint32_t auLast[4];
1483	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1484
1485	uint32_t cChecks = RT_ELEMENTS(auChecks);
1486	while (cChecks > 0)
1487	{
1488	uint32_t auCur[4];
1489	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1490	if (memcmp(auCur, auLast, sizeof(auCur)))
1491	break;
1492	cChecks--;
1493	}
1494	if (cChecks == 0)
1495	{
1496	/* Now, what happens when the input changes? Esp. ECX. */
1497	uint32_t cTotal = 0;
1498	uint32_t cSame = 0;
1499	uint32_t cLastWithEcx = 0;
1500	uint32_t cNeither = 0;
1501	uint32_t cValues = RT_ELEMENTS(s_auValues);
1502	while (cValues > 0)
1503	{
1504	uint32_t uValue = s_auValues[cValues - 1];
1505	uint32_t auLastWithEcx[4];
1506	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1507	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1508
1509	cChecks = RT_ELEMENTS(auChecks);
1510	while (cChecks > 0)
1511	{
1512	uint32_t auCur[4];
1513	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1514	if (!memcmp(auCur, auLast, sizeof(auCur)))
1515	{
1516	cSame++;
1517	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1518	cLastWithEcx++;
1519	}
1520	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1521	cLastWithEcx++;
1522	else
1523	cNeither++;
1524	cTotal++;
1525	cChecks--;
1526	}
1527	cValues--;
1528	}
1529
1530	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1531	if (cSame == cTotal)
1532	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1533	else if (cLastWithEcx == cTotal)
1534	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1535	else
1536	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1537	pDefUnknown->uEax = auLast[0];
1538	pDefUnknown->uEbx = auLast[1];
1539	pDefUnknown->uEcx = auLast[2];
1540	pDefUnknown->uEdx = auLast[3];
1541	return VINF_SUCCESS;
1542	}
1543
1544	/*
1545	* Unchanged register values?
1546	*/
1547	cChecks = RT_ELEMENTS(auChecks);
1548	while (cChecks > 0)
1549	{
1550	uint32_t const uLeaf = auChecks[cChecks - 1];
1551	uint32_t cValues = RT_ELEMENTS(s_auValues);
1552	while (cValues > 0)
1553	{
1554	uint32_t uValue = s_auValues[cValues - 1];
1555	uint32_t auCur[4];
1556	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1557	if ( auCur[0] != uLeaf
1558	\|\| auCur[1] != uValue
1559	\|\| auCur[2] != uValue
1560	\|\| auCur[3] != uValue)
1561	break;
1562	cValues--;
1563	}
1564	if (cValues != 0)
1565	break;
1566	cChecks--;
1567	}
1568	if (cChecks == 0)
1569	{
1570	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1571	return VINF_SUCCESS;
1572	}
1573
1574	/*
1575	* Just go with the simple method.
1576	*/
1577	return VINF_SUCCESS;
1578	}
1579
1580
1581	/**
1582	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1583	*
1584	* @returns Read only name string.
1585	* @param enmUnknownMethod The method to translate.
1586	*/
1587	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1588	{
1589	switch (enmUnknownMethod)
1590	{
1591	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1592	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1593	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1594	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1595
1596	case CPUMUNKNOWNCPUID_INVALID:
1597	case CPUMUNKNOWNCPUID_END:
1598	case CPUMUNKNOWNCPUID_32BIT_HACK:
1599	break;
1600	}
1601	return "Invalid-unknown-CPUID-method";
1602	}
1603
1604
1605	/**
1606	* Detect the CPU vendor give n the
1607	*
1608	* @returns The vendor.
1609	* @param uEAX EAX from CPUID(0).
1610	* @param uEBX EBX from CPUID(0).
1611	* @param uECX ECX from CPUID(0).
1612	* @param uEDX EDX from CPUID(0).
1613	*/
1614	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1615	{
1616	if (ASMIsValidStdRange(uEAX))
1617	{
1618	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1619	return CPUMCPUVENDOR_AMD;
1620
1621	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1622	return CPUMCPUVENDOR_INTEL;
1623
1624	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1625	return CPUMCPUVENDOR_VIA;
1626
1627	if (ASMIsShanghaiCpuEx(uEBX, uECX, uEDX))
1628	return CPUMCPUVENDOR_SHANGHAI;
1629
1630	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1631	&& uECX == UINT32_C(0x64616574)
1632	&& uEDX == UINT32_C(0x736E4978))
1633	return CPUMCPUVENDOR_CYRIX;
1634
1635	/* "Geode by NSC", example: family 5, model 9. */
1636
1637	/** @todo detect the other buggers... */
1638	}
1639
1640	return CPUMCPUVENDOR_UNKNOWN;
1641	}
1642
1643
1644	/**
1645	* Translates a CPU vendor enum value into the corresponding string constant.
1646	*
1647	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1648	* value name. This can be useful when generating code.
1649	*
1650	* @returns Read only name string.
1651	* @param enmVendor The CPU vendor value.
1652	*/
1653	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1654	{
1655	switch (enmVendor)
1656	{
1657	case CPUMCPUVENDOR_INTEL: return "INTEL";
1658	case CPUMCPUVENDOR_AMD: return "AMD";
1659	case CPUMCPUVENDOR_VIA: return "VIA";
1660	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1661	case CPUMCPUVENDOR_SHANGHAI: return "SHANGHAI";
1662	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1663
1664	case CPUMCPUVENDOR_INVALID:
1665	case CPUMCPUVENDOR_32BIT_HACK:
1666	break;
1667	}
1668	return "Invalid-cpu-vendor";
1669	}
1670
1671
1672	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1673	{
1674	/* Could do binary search, doing linear now because I'm lazy. */
1675	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1676	while (cLeaves-- > 0)
1677	{
1678	if (pLeaf->uLeaf == uLeaf)
1679	return pLeaf;
1680	pLeaf++;
1681	}
1682	return NULL;
1683	}
1684
1685
1686	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1687	{
1688	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1689	if ( !pLeaf
1690	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1691	return pLeaf;
1692
1693	/* Linear sub-leaf search. Lazy as usual. */
1694	cLeaves -= pLeaf - paLeaves;
1695	while ( cLeaves-- > 0
1696	&& pLeaf->uLeaf == uLeaf)
1697	{
1698	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1699	return pLeaf;
1700	pLeaf++;
1701	}
1702
1703	return NULL;
1704	}
1705
1706
1707	static void cpumR3ExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURES pFeatures)
1708	{
1709	Assert(pVmxMsrs);
1710	Assert(pFeatures);
1711	Assert(pFeatures->fVmx);
1712
1713	/* Basic information. */
1714	{
1715	uint64_t const u64Basic = pVmxMsrs->u64Basic;
1716	pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1717	}
1718
1719	/* Pin-based VM-execution controls. */
1720	{
1721	uint32_t const fPinCtls = pVmxMsrs->PinCtls.n.allowed1;
1722	pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1723	pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1724	pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1725	pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1726	pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1727	}
1728
1729	/* Processor-based VM-execution controls. */
1730	{
1731	uint32_t const fProcCtls = pVmxMsrs->ProcCtls.n.allowed1;
1732	pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1733	pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1734	pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1735	pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1736	pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1737	pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1738	pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1739	pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1740	pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1741	pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1742	pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1743	pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1744	pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1745	pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1746	pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1747	pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1748	pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1749	pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1750	pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1751	pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1752	pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1753	}
1754
1755	/* Secondary processor-based VM-execution controls. */
1756	{
1757	uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1758	pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1759	pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1760	pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1761	pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1762	pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1763	pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1764	pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1765	pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1766	pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1767	pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1768	pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1769	pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1770	pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1771	pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1772	pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1773	pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1774	pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1775	pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_VE);
1776	pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1777	pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1778	}
1779
1780	/* VM-exit controls. */
1781	{
1782	uint32_t const fExitCtls = pVmxMsrs->ExitCtls.n.allowed1;
1783	pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1784	pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1785	pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1786	pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1787	pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1788	pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1789	pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1790	pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1791	}
1792
1793	/* VM-entry controls. */
1794	{
1795	uint32_t const fEntryCtls = pVmxMsrs->EntryCtls.n.allowed1;
1796	pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1797	pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1798	pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1799	pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1800	}
1801
1802	/* Miscellaneous data. */
1803	{
1804	uint32_t const fMiscData = pVmxMsrs->u64Misc;
1805	pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1806	pFeatures->fVmxIntelPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1807	pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1808	pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1809	}
1810	}
1811
1812
1813	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures)
1814	{
1815	Assert(pMsrs);
1816	RT_ZERO(*pFeatures);
1817	if (cLeaves >= 2)
1818	{
1819	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1820	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1821	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1822	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1823	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1824	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1825
1826	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1827	pStd0Leaf->uEbx,
1828	pStd0Leaf->uEcx,
1829	pStd0Leaf->uEdx);
1830	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1831	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1832	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1833	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1834	pFeatures->uFamily,
1835	pFeatures->uModel,
1836	pFeatures->uStepping);
1837
1838	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1839	if (pExtLeaf8)
1840	{
1841	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1842	pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1843	}
1844	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1845	{
1846	pFeatures->cMaxPhysAddrWidth = 36;
1847	pFeatures->cMaxLinearAddrWidth = 36;
1848	}
1849	else
1850	{
1851	pFeatures->cMaxPhysAddrWidth = 32;
1852	pFeatures->cMaxLinearAddrWidth = 32;
1853	}
1854
1855	/* Standard features. */
1856	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1857	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1858	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1859	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1860	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1861	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1862	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1863	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1864	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1865	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1866	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1867	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1868	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1869	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1870	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1871	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1872	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1873	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1874	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1875	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1876	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1877	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1878	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1879	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1880	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1881	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1882	if (pFeatures->fVmx)
1883	cpumR3ExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1884
1885	/* Structured extended features. */
1886	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1887	if (pSxfLeaf0)
1888	{
1889	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1890	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1891	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1892	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1893	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1894
1895	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1896	pFeatures->fIbrs = pFeatures->fIbpb;
1897	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1898	pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
1899	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1900	pFeatures->fMdsClear = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
1901	}
1902
1903	/* MWAIT/MONITOR leaf. */
1904	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1905	if (pMWaitLeaf)
1906	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1907	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1908
1909	/* Extended features. */
1910	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1911	if (pExtLeaf)
1912	{
1913	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1914	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1915	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1916	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1917	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1918	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1919	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1920	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1921	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1922	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1923	}
1924
1925	/* VMX (VMXON, VMCS region and related data structures) physical address width (depends on long-mode). */
1926	pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
1927
1928	if ( pExtLeaf
1929	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1930	{
1931	/* AMD features. */
1932	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1933	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1934	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1935	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1936	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1937	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1938	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1939	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1940	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1941	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1942	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1943	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1944	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1945	if (pFeatures->fSvm)
1946	{
1947	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1948	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1949	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1950	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1951	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1952	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1953	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1954	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1955	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1956	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1957	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1958	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1959	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1960	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1961	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1962	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1963	}
1964	}
1965
1966	/*
1967	* Quirks.
1968	*/
1969	pFeatures->fLeakyFxSR = pExtLeaf
1970	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1971	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1972	&& pFeatures->uFamily >= 6 /* K7 and up */;
1973
1974	/*
1975	* Max extended (/FPU) state.
1976	*/
1977	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1978	if (pFeatures->fXSaveRstor)
1979	{
1980	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1981	if (pXStateLeaf0)
1982	{
1983	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1984	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1985	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1986	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1987	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1988	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1989	{
1990	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1991
1992	/* (paranoia:) */
1993	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1994	if ( pXStateLeaf1
1995	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1996	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1997	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1998	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1999	}
2000	else
2001	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
2002	pFeatures->fXSaveRstor = 0);
2003	}
2004	else
2005	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
2006	pFeatures->fXSaveRstor = 0);
2007	}
2008	}
2009	else
2010	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
2011	return VINF_SUCCESS;
2012	}
2013
2014
2015	/*
2016	*
2017	* Init related code.
2018	* Init related code.
2019	* Init related code.
2020	*
2021	*
2022	*/
2023	#ifdef VBOX_IN_VMM
2024
2025
2026	/**
2027	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
2028	*
2029	* This ignores the fSubLeafMask.
2030	*
2031	* @returns Pointer to the matching leaf, or NULL if not found.
2032	* @param paLeaves The CPUID leaves to search. This is sorted.
2033	* @param cLeaves The number of leaves in the array.
2034	* @param uLeaf The leaf to locate.
2035	* @param uSubLeaf The subleaf to locate.
2036	*/
2037	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
2038	{
2039	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
2040	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
2041	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
2042	if (iEnd)
2043	{
2044	uint32_t iBegin = 0;
2045	for (;;)
2046	{
2047	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
2048	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
2049	if (uNeedle < uCur)
2050	{
2051	if (i > iBegin)
2052	iEnd = i;
2053	else
2054	break;
2055	}
2056	else if (uNeedle > uCur)
2057	{
2058	if (i + 1 < iEnd)
2059	iBegin = i + 1;
2060	else
2061	break;
2062	}
2063	else
2064	return &paLeaves[i];
2065	}
2066	}
2067	return NULL;
2068	}
2069
2070
2071	/**
2072	* Loads MSR range overrides.
2073	*
2074	* This must be called before the MSR ranges are moved from the normal heap to
2075	* the hyper heap!
2076	*
2077	* @returns VBox status code (VMSetError called).
2078	* @param pVM The cross context VM structure.
2079	* @param pMsrNode The CFGM node with the MSR overrides.
2080	*/
2081	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
2082	{
2083	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2084	{
2085	/*
2086	* Assemble a valid MSR range.
2087	*/
2088	CPUMMSRRANGE MsrRange;
2089	MsrRange.offCpumCpu = 0;
2090	MsrRange.fReserved = 0;
2091
2092	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
2093	if (RT_FAILURE(rc))
2094	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
2095
2096	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
2097	if (RT_FAILURE(rc))
2098	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
2099	MsrRange.szName, rc);
2100
2101	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
2102	if (RT_FAILURE(rc))
2103	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
2104	MsrRange.szName, rc);
2105
2106	char szType[32];
2107	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
2108	if (RT_FAILURE(rc))
2109	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
2110	MsrRange.szName, rc);
2111	if (!RTStrICmp(szType, "FixedValue"))
2112	{
2113	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
2114	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
2115
2116	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
2117	if (RT_FAILURE(rc))
2118	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
2119	MsrRange.szName, rc);
2120
2121	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
2122	if (RT_FAILURE(rc))
2123	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
2124	MsrRange.szName, rc);
2125
2126	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
2127	if (RT_FAILURE(rc))
2128	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
2129	MsrRange.szName, rc);
2130	}
2131	else
2132	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
2133	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
2134
2135	/*
2136	* Insert the range into the table (replaces/splits/shrinks existing
2137	* MSR ranges).
2138	*/
2139	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
2140	&MsrRange);
2141	if (RT_FAILURE(rc))
2142	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
2143	}
2144
2145	return VINF_SUCCESS;
2146	}
2147
2148
2149	/**
2150	* Loads CPUID leaf overrides.
2151	*
2152	* This must be called before the CPUID leaves are moved from the normal
2153	* heap to the hyper heap!
2154	*
2155	* @returns VBox status code (VMSetError called).
2156	* @param pVM The cross context VM structure.
2157	* @param pParentNode The CFGM node with the CPUID leaves.
2158	* @param pszLabel How to label the overrides we're loading.
2159	*/
2160	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2161	{
2162	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2163	{
2164	/*
2165	* Get the leaf and subleaf numbers.
2166	*/
2167	char szName[128];
2168	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2169	if (RT_FAILURE(rc))
2170	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2171
2172	/* The leaf number is either specified directly or thru the node name. */
2173	uint32_t uLeaf;
2174	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2175	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2176	{
2177	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2178	if (rc != VINF_SUCCESS)
2179	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2180	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2181	}
2182	else if (RT_FAILURE(rc))
2183	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2184	pszLabel, szName, rc);
2185
2186	uint32_t uSubLeaf;
2187	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2188	if (RT_FAILURE(rc))
2189	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2190	pszLabel, szName, rc);
2191
2192	uint32_t fSubLeafMask;
2193	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2194	if (RT_FAILURE(rc))
2195	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2196	pszLabel, szName, rc);
2197
2198	/*
2199	* Look up the specified leaf, since the output register values
2200	* defaults to any existing values. This allows overriding a single
2201	* register, without needing to know the other values.
2202	*/
2203	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2204	CPUMCPUIDLEAF Leaf;
2205	if (pLeaf)
2206	Leaf = *pLeaf;
2207	else
2208	RT_ZERO(Leaf);
2209	Leaf.uLeaf = uLeaf;
2210	Leaf.uSubLeaf = uSubLeaf;
2211	Leaf.fSubLeafMask = fSubLeafMask;
2212
2213	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2214	if (RT_FAILURE(rc))
2215	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2216	pszLabel, szName, rc);
2217	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2218	if (RT_FAILURE(rc))
2219	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2220	pszLabel, szName, rc);
2221	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2222	if (RT_FAILURE(rc))
2223	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2224	pszLabel, szName, rc);
2225	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2226	if (RT_FAILURE(rc))
2227	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2228	pszLabel, szName, rc);
2229
2230	/*
2231	* Insert the leaf into the table (replaces existing ones).
2232	*/
2233	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2234	&Leaf);
2235	if (RT_FAILURE(rc))
2236	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2237	}
2238
2239	return VINF_SUCCESS;
2240	}
2241
2242
2243
2244	/**
2245	* Fetches overrides for a CPUID leaf.
2246	*
2247	* @returns VBox status code.
2248	* @param pLeaf The leaf to load the overrides into.
2249	* @param pCfgNode The CFGM node containing the overrides
2250	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2251	* @param iLeaf The CPUID leaf number.
2252	*/
2253	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2254	{
2255	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2256	if (pLeafNode)
2257	{
2258	uint32_t u32;
2259	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2260	if (RT_SUCCESS(rc))
2261	pLeaf->uEax = u32;
2262	else
2263	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2264
2265	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2266	if (RT_SUCCESS(rc))
2267	pLeaf->uEbx = u32;
2268	else
2269	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2270
2271	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2272	if (RT_SUCCESS(rc))
2273	pLeaf->uEcx = u32;
2274	else
2275	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2276
2277	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2278	if (RT_SUCCESS(rc))
2279	pLeaf->uEdx = u32;
2280	else
2281	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2282
2283	}
2284	return VINF_SUCCESS;
2285	}
2286
2287
2288	/**
2289	* Load the overrides for a set of CPUID leaves.
2290	*
2291	* @returns VBox status code.
2292	* @param paLeaves The leaf array.
2293	* @param cLeaves The number of leaves.
2294	* @param uStart The start leaf number.
2295	* @param pCfgNode The CFGM node containing the overrides
2296	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2297	*/
2298	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2299	{
2300	for (uint32_t i = 0; i < cLeaves; i++)
2301	{
2302	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2303	if (RT_FAILURE(rc))
2304	return rc;
2305	}
2306
2307	return VINF_SUCCESS;
2308	}
2309
2310
2311	/**
2312	* Installs the CPUID leaves and explods the data into structures like
2313	* GuestFeatures and CPUMCTX::aoffXState.
2314	*
2315	* @returns VBox status code.
2316	* @param pVM The cross context VM structure.
2317	* @param pCpum The CPUM part of @a VM.
2318	* @param paLeaves The leaves. These will be copied (but not freed).
2319	* @param cLeaves The number of leaves.
2320	* @param pMsrs The MSRs.
2321	*/
2322	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
2323	{
2324	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2325
2326	/*
2327	* Install the CPUID information.
2328	*/
2329	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2330	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2331
2332	AssertLogRelRCReturn(rc, rc);
2333	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2334	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2335	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2336
2337	/*
2338	* Update the default CPUID leaf if necessary.
2339	*/
2340	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2341	{
2342	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2343	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2344	{
2345	/* We don't use CPUID(0).eax here because of the NT hack that only
2346	changes that value without actually removing any leaves. */
2347	uint32_t i = 0;
2348	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2349	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2350	{
2351	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2352	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2353	i++;
2354	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2355	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2356	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2357	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2358	}
2359	break;
2360	}
2361	default:
2362	break;
2363	}
2364
2365	/*
2366	* Explode the guest CPU features.
2367	*/
2368	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
2369	&pCpum->GuestFeatures);
2370	AssertLogRelRCReturn(rc, rc);
2371
2372	/*
2373	* Adjust the scalable bus frequency according to the CPUID information
2374	* we're now using.
2375	*/
2376	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2377	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2378	? UINT64_C(100000000) /* 100MHz */
2379	: UINT64_C(133333333); /* 133MHz */
2380
2381	/*
2382	* Populate the legacy arrays. Currently used for everything, later only
2383	* for patch manager.
2384	*/
2385	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2386	{
2387	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2388	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2389	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2390	};
2391	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2392	{
2393	uint32_t cLeft = aOldRanges[i].cCpuIds;
2394	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2395	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2396	while (cLeft-- > 0)
2397	{
2398	uLeaf--;
2399	pLegacyLeaf--;
2400
2401	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2402	if (pLeaf)
2403	{
2404	pLegacyLeaf->uEax = pLeaf->uEax;
2405	pLegacyLeaf->uEbx = pLeaf->uEbx;
2406	pLegacyLeaf->uEcx = pLeaf->uEcx;
2407	pLegacyLeaf->uEdx = pLeaf->uEdx;
2408	}
2409	else
2410	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2411	}
2412	}
2413
2414	/*
2415	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2416	*/
2417	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2418	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2419	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2420	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2421	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2422	{
2423	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2424	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2425	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2426	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2427	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2428	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2429	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2430	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2431	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2432	pCpum->GuestFeatures.cbMaxExtendedState),
2433	VERR_CPUM_IPE_1);
2434	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2435	}
2436
2437	/* Copy the CPU #0 data to the other CPUs. */
2438	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2439	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2440	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2441
2442	return VINF_SUCCESS;
2443	}
2444
2445
2446	/** @name Instruction Set Extension Options
2447	* @{ */
2448	/** Configuration option type (extended boolean, really). */
2449	typedef uint8_t CPUMISAEXTCFG;
2450	/** Always disable the extension. */
2451	#define CPUMISAEXTCFG_DISABLED false
2452	/** Enable the extension if it's supported by the host CPU. */
2453	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2454	/** Enable the extension if it's supported by the host CPU, but don't let
2455	* the portable CPUID feature disable it. */
2456	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2457	/** Always enable the extension. */
2458	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2459	/** @} */
2460
2461	/**
2462	* CPUID Configuration (from CFGM).
2463	*
2464	* @remarks The members aren't document since we would only be duplicating the
2465	* \@cfgm entries in cpumR3CpuIdReadConfig.
2466	*/
2467	typedef struct CPUMCPUIDCONFIG
2468	{
2469	bool fNt4LeafLimit;
2470	bool fInvariantTsc;
2471	bool fForceVme;
2472	bool fNestedHWVirt;
2473
2474	CPUMISAEXTCFG enmCmpXchg16b;
2475	CPUMISAEXTCFG enmMonitor;
2476	CPUMISAEXTCFG enmMWaitExtensions;
2477	CPUMISAEXTCFG enmSse41;
2478	CPUMISAEXTCFG enmSse42;
2479	CPUMISAEXTCFG enmAvx;
2480	CPUMISAEXTCFG enmAvx2;
2481	CPUMISAEXTCFG enmXSave;
2482	CPUMISAEXTCFG enmAesNi;
2483	CPUMISAEXTCFG enmPClMul;
2484	CPUMISAEXTCFG enmPopCnt;
2485	CPUMISAEXTCFG enmMovBe;
2486	CPUMISAEXTCFG enmRdRand;
2487	CPUMISAEXTCFG enmRdSeed;
2488	CPUMISAEXTCFG enmCLFlushOpt;
2489	CPUMISAEXTCFG enmFsGsBase;
2490	CPUMISAEXTCFG enmPcid;
2491	CPUMISAEXTCFG enmInvpcid;
2492	CPUMISAEXTCFG enmFlushCmdMsr;
2493	CPUMISAEXTCFG enmMdsClear;
2494	CPUMISAEXTCFG enmArchCapMsr;
2495
2496	CPUMISAEXTCFG enmAbm;
2497	CPUMISAEXTCFG enmSse4A;
2498	CPUMISAEXTCFG enmMisAlnSse;
2499	CPUMISAEXTCFG enm3dNowPrf;
2500	CPUMISAEXTCFG enmAmdExtMmx;
2501
2502	uint32_t uMaxStdLeaf;
2503	uint32_t uMaxExtLeaf;
2504	uint32_t uMaxCentaurLeaf;
2505	uint32_t uMaxIntelFamilyModelStep;
2506	char szCpuName[128];
2507	} CPUMCPUIDCONFIG;
2508	/** Pointer to CPUID config (from CFGM). */
2509	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2510
2511
2512	/**
2513	* Mini CPU selection support for making Mac OS X happy.
2514	*
2515	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2516	*
2517	* @param pCpum The CPUM instance data.
2518	* @param pConfig The CPUID configuration we've read from CFGM.
2519	*/
2520	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2521	{
2522	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2523	{
2524	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2525	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2526	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2527	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2528	0);
2529	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2530	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2531	{
2532	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2533	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2534	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2535	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2536	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2537	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2538	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2539	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2540	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2541	pStdFeatureLeaf->uEax = uNew;
2542	}
2543	}
2544	}
2545
2546
2547
2548	/**
2549	* Limit it the number of entries, zapping the remainder.
2550	*
2551	* The limits are masking off stuff about power saving and similar, this
2552	* is perhaps a bit crudely done as there is probably some relatively harmless
2553	* info too in these leaves (like words about having a constant TSC).
2554	*
2555	* @param pCpum The CPUM instance data.
2556	* @param pConfig The CPUID configuration we've read from CFGM.
2557	*/
2558	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2559	{
2560	/*
2561	* Standard leaves.
2562	*/
2563	uint32_t uSubLeaf = 0;
2564	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2565	if (pCurLeaf)
2566	{
2567	uint32_t uLimit = pCurLeaf->uEax;
2568	if (uLimit <= UINT32_C(0x000fffff))
2569	{
2570	if (uLimit > pConfig->uMaxStdLeaf)
2571	{
2572	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2573	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2574	uLimit + 1, UINT32_C(0x000fffff));
2575	}
2576
2577	/* NT4 hack, no zapping of extra leaves here. */
2578	if (pConfig->fNt4LeafLimit && uLimit > 3)
2579	pCurLeaf->uEax = uLimit = 3;
2580
2581	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2582	pCurLeaf->uEax = uLimit;
2583	}
2584	else
2585	{
2586	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2587	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2588	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2589	}
2590	}
2591
2592	/*
2593	* Extended leaves.
2594	*/
2595	uSubLeaf = 0;
2596	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2597	if (pCurLeaf)
2598	{
2599	uint32_t uLimit = pCurLeaf->uEax;
2600	if ( uLimit >= UINT32_C(0x80000000)
2601	&& uLimit <= UINT32_C(0x800fffff))
2602	{
2603	if (uLimit > pConfig->uMaxExtLeaf)
2604	{
2605	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2606	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2607	uLimit + 1, UINT32_C(0x800fffff));
2608	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2609	pCurLeaf->uEax = uLimit;
2610	}
2611	}
2612	else
2613	{
2614	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2615	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2616	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2617	}
2618	}
2619
2620	/*
2621	* Centaur leaves (VIA).
2622	*/
2623	uSubLeaf = 0;
2624	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2625	if (pCurLeaf)
2626	{
2627	uint32_t uLimit = pCurLeaf->uEax;
2628	if ( uLimit >= UINT32_C(0xc0000000)
2629	&& uLimit <= UINT32_C(0xc00fffff))
2630	{
2631	if (uLimit > pConfig->uMaxCentaurLeaf)
2632	{
2633	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2634	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2635	uLimit + 1, UINT32_C(0xcfffffff));
2636	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2637	pCurLeaf->uEax = uLimit;
2638	}
2639	}
2640	else
2641	{
2642	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2643	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2644	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2645	}
2646	}
2647	}
2648
2649
2650	/**
2651	* Clears a CPUID leaf and all sub-leaves (to zero).
2652	*
2653	* @param pCpum The CPUM instance data.
2654	* @param uLeaf The leaf to clear.
2655	*/
2656	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2657	{
2658	uint32_t uSubLeaf = 0;
2659	PCPUMCPUIDLEAF pCurLeaf;
2660	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2661	{
2662	pCurLeaf->uEax = 0;
2663	pCurLeaf->uEbx = 0;
2664	pCurLeaf->uEcx = 0;
2665	pCurLeaf->uEdx = 0;
2666	uSubLeaf++;
2667	}
2668	}
2669
2670
2671	/**
2672	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2673	* the given leaf.
2674	*
2675	* @returns pLeaf.
2676	* @param pCpum The CPUM instance data.
2677	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2678	*/
2679	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2680	{
2681	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2682	if (pLeaf->fSubLeafMask != 0)
2683	{
2684	/*
2685	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2686	* Log everything while we're at it.
2687	*/
2688	LogRel(("CPUM:\n"
2689	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2690	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2691	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2692	for (;;)
2693	{
2694	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2695	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2696	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2697	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2698	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2699	break;
2700	pSubLeaf++;
2701	}
2702	LogRel(("CPUM:\n"));
2703
2704	/*
2705	* Remove the offending sub-leaves.
2706	*/
2707	if (pSubLeaf != pLeaf)
2708	{
2709	if (pSubLeaf != pLast)
2710	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2711	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2712	}
2713
2714	/*
2715	* Convert the first sub-leaf into a single leaf.
2716	*/
2717	pLeaf->uSubLeaf = 0;
2718	pLeaf->fSubLeafMask = 0;
2719	}
2720	return pLeaf;
2721	}
2722
2723
2724	/**
2725	* Sanitizes and adjust the CPUID leaves.
2726	*
2727	* Drop features that aren't virtualized (or virtualizable). Adjust information
2728	* and capabilities to fit the virtualized hardware. Remove information the
2729	* guest shouldn't have (because it's wrong in the virtual world or because it
2730	* gives away host details) or that we don't have documentation for and no idea
2731	* what means.
2732	*
2733	* @returns VBox status code.
2734	* @param pVM The cross context VM structure (for cCpus).
2735	* @param pCpum The CPUM instance data.
2736	* @param pConfig The CPUID configuration we've read from CFGM.
2737	*/
2738	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2739	{
2740	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2741	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2742	{ \
2743	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2744	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2745	}
2746	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2747	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2748	{ \
2749	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2750	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2751	}
2752	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2753	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2754	&& ((a_pLeafReg) & (fBitMask)) \
2755	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2756	{ \
2757	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2758	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2759	}
2760	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2761
2762	/* Cpuid 1:
2763	* EAX: CPU model, family and stepping.
2764	*
2765	* ECX + EDX: Supported features. Only report features we can support.
2766	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2767	* options may require adjusting (i.e. stripping what was enabled).
2768	*
2769	* EBX: Branding, CLFLUSH line size, logical processors per package and
2770	* initial APIC ID.
2771	*/
2772	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2773	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2774	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2775
2776	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2777	\| X86_CPUID_FEATURE_EDX_VME
2778	\| X86_CPUID_FEATURE_EDX_DE
2779	\| X86_CPUID_FEATURE_EDX_PSE
2780	\| X86_CPUID_FEATURE_EDX_TSC
2781	\| X86_CPUID_FEATURE_EDX_MSR
2782	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2783	\| X86_CPUID_FEATURE_EDX_MCE
2784	\| X86_CPUID_FEATURE_EDX_CX8
2785	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2786	//\| RT_BIT_32(10) - not defined
2787	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2788	//\| X86_CPUID_FEATURE_EDX_SEP
2789	\| X86_CPUID_FEATURE_EDX_MTRR
2790	\| X86_CPUID_FEATURE_EDX_PGE
2791	\| X86_CPUID_FEATURE_EDX_MCA
2792	\| X86_CPUID_FEATURE_EDX_CMOV
2793	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2794	\| X86_CPUID_FEATURE_EDX_PSE36
2795	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2796	\| X86_CPUID_FEATURE_EDX_CLFSH
2797	//\| RT_BIT_32(20) - not defined
2798	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2799	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2800	\| X86_CPUID_FEATURE_EDX_MMX
2801	\| X86_CPUID_FEATURE_EDX_FXSR
2802	\| X86_CPUID_FEATURE_EDX_SSE
2803	\| X86_CPUID_FEATURE_EDX_SSE2
2804	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2805	\| X86_CPUID_FEATURE_EDX_HTT
2806	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2807	//\| RT_BIT_32(30) - not defined
2808	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2809	;
2810	pStdFeatureLeaf->uEcx &= 0
2811	\| X86_CPUID_FEATURE_ECX_SSE3
2812	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2813	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2814	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2815	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2816	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2817	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2818	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2819	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2820	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2821	\| X86_CPUID_FEATURE_ECX_SSSE3
2822	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2823	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2824	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2825	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2826	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2827	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2828	\| (pConfig->enmPcid ? X86_CPUID_FEATURE_ECX_PCID : 0)
2829	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2830	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2831	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2832	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2833	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2834	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2835	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2836	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2837	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2838	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2839	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2840	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2841	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2842	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2843	;
2844
2845	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2846	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2847	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2848	{
2849	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2850	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2851	}
2852
2853	if (pCpum->u8PortableCpuIdLevel > 0)
2854	{
2855	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2856	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2857	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2858	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2859	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2860	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2861	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2862	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2863	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2864	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2865	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2866	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2867	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2868	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2869	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2870	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2871	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2872	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2873	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2874	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2875
2876	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2877	\| X86_CPUID_FEATURE_EDX_PSN
2878	\| X86_CPUID_FEATURE_EDX_DS
2879	\| X86_CPUID_FEATURE_EDX_ACPI
2880	\| X86_CPUID_FEATURE_EDX_SS
2881	\| X86_CPUID_FEATURE_EDX_TM
2882	\| X86_CPUID_FEATURE_EDX_PBE
2883	)));
2884	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2885	\| X86_CPUID_FEATURE_ECX_CPLDS
2886	\| X86_CPUID_FEATURE_ECX_AES
2887	\| X86_CPUID_FEATURE_ECX_VMX
2888	\| X86_CPUID_FEATURE_ECX_SMX
2889	\| X86_CPUID_FEATURE_ECX_EST
2890	\| X86_CPUID_FEATURE_ECX_TM2
2891	\| X86_CPUID_FEATURE_ECX_CNTXID
2892	\| X86_CPUID_FEATURE_ECX_FMA
2893	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2894	\| X86_CPUID_FEATURE_ECX_PDCM
2895	\| X86_CPUID_FEATURE_ECX_DCA
2896	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2897	)));
2898	}
2899
2900	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2901	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2902
2903	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2904	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2905	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2906	*/
2907	#ifdef VBOX_WITH_MULTI_CORE
2908	if (pVM->cCpus > 1)
2909	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2910	#endif
2911	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2912	{
2913	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2914	core times the number of CPU cores per processor */
2915	#ifdef VBOX_WITH_MULTI_CORE
2916	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2917	#else
2918	/* Single logical processor in a package. */
2919	pStdFeatureLeaf->uEbx \|= (1 << 16);
2920	#endif
2921	}
2922
2923	uint32_t uMicrocodeRev;
2924	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2925	if (RT_SUCCESS(rc))
2926	{
2927	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2928	}
2929	else
2930	{
2931	uMicrocodeRev = 0;
2932	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2933	}
2934
2935	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2936	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2937	*/
2938	if ( (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen)
2939	&& uMicrocodeRev < 0x8001126
2940	&& !pConfig->fForceVme)
2941	{
2942	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2943	LogRel(("CPUM: Zen VME workaround engaged\n"));
2944	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2945	}
2946
2947	/* Force standard feature bits. */
2948	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2949	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2950	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2951	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2952	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2953	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2954	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2955	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2956	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2957	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2958	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2959	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2960	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2961	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2962	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2963	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2964	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2965	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2966	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2967	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2968	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2969	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2970
2971	pStdFeatureLeaf = NULL; /* Must refetch! */
2972
2973	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2974	* AMD:
2975	* EAX: CPU model, family and stepping.
2976	*
2977	* ECX + EDX: Supported features. Only report features we can support.
2978	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2979	* options may require adjusting (i.e. stripping what was enabled).
2980	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2981	*
2982	* EBX: Branding ID and package type (or reserved).
2983	*
2984	* Intel and probably most others:
2985	* EAX: 0
2986	* EBX: 0
2987	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2988	*/
2989	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2990	if (pExtFeatureLeaf)
2991	{
2992	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2993
2994	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2995	\| X86_CPUID_AMD_FEATURE_EDX_VME
2996	\| X86_CPUID_AMD_FEATURE_EDX_DE
2997	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2998	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2999	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
3000	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
3001	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
3002	\| X86_CPUID_AMD_FEATURE_EDX_CX8
3003	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
3004	//\| RT_BIT_32(10) - reserved
3005	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
3006	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
3007	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3008	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
3009	\| X86_CPUID_AMD_FEATURE_EDX_PGE
3010	\| X86_CPUID_AMD_FEATURE_EDX_MCA
3011	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
3012	\| X86_CPUID_AMD_FEATURE_EDX_PAT
3013	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
3014	//\| RT_BIT_32(18) - reserved
3015	//\| RT_BIT_32(19) - reserved
3016	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
3017	//\| RT_BIT_32(21) - reserved
3018	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
3019	\| X86_CPUID_AMD_FEATURE_EDX_MMX
3020	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
3021	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
3022	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3023	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
3024	//\| RT_BIT_32(28) - reserved
3025	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
3026	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
3027	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
3028	;
3029	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
3030	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
3031	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
3032	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3033	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
3034	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
3035	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
3036	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
3037	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
3038	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
3039	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3040	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
3041	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
3042	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3043	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
3044	//\| RT_BIT_32(14) - reserved
3045	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
3046	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
3047	//\| RT_BIT_32(17) - reserved
3048	//\| RT_BIT_32(18) - reserved
3049	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
3050	//\| RT_BIT_32(20) - reserved
3051	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
3052	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
3053	//\| RT_BIT_32(23) - reserved
3054	//\| RT_BIT_32(24) - reserved
3055	//\| RT_BIT_32(25) - reserved
3056	//\| RT_BIT_32(26) - reserved
3057	//\| RT_BIT_32(27) - reserved
3058	//\| RT_BIT_32(28) - reserved
3059	//\| RT_BIT_32(29) - reserved
3060	//\| RT_BIT_32(30) - reserved
3061	//\| RT_BIT_32(31) - reserved
3062	;
3063	#ifdef VBOX_WITH_MULTI_CORE
3064	if ( pVM->cCpus > 1
3065	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3066	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
3067	#endif
3068
3069	if (pCpum->u8PortableCpuIdLevel > 0)
3070	{
3071	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
3072	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
3073	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
3074	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
3075	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
3076	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
3077	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
3078	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
3079	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
3080	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
3081	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
3082	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
3083	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
3084	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
3085	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
3086	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
3087
3088	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
3089	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3090	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3091	\| X86_CPUID_AMD_FEATURE_ECX_IBS
3092	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3093	\| X86_CPUID_AMD_FEATURE_ECX_WDT
3094	\| X86_CPUID_AMD_FEATURE_ECX_LWP
3095	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
3096	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
3097	\| UINT32_C(0xff964000)
3098	)));
3099	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
3100	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3101	\| RT_BIT(18)
3102	\| RT_BIT(19)
3103	\| RT_BIT(21)
3104	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
3105	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3106	\| RT_BIT(28)
3107	)));
3108	}
3109
3110	/* Force extended feature bits. */
3111	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
3112	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
3113	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
3114	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
3115	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
3116	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
3117	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
3118	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
3119	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3120	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
3121	}
3122	pExtFeatureLeaf = NULL; /* Must refetch! */
3123
3124
3125	/* Cpuid 2:
3126	* Intel: (Nondeterministic) Cache and TLB information
3127	* AMD: Reserved
3128	* VIA: Reserved
3129	* Safe to expose.
3130	*/
3131	uint32_t uSubLeaf = 0;
3132	PCPUMCPUIDLEAF pCurLeaf;
3133	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
3134	{
3135	if ((pCurLeaf->uEax & 0xff) > 1)
3136	{
3137	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
3138	pCurLeaf->uEax &= UINT32_C(0xffffff01);
3139	}
3140	uSubLeaf++;
3141	}
3142
3143	/* Cpuid 3:
3144	* Intel: EAX, EBX - reserved (transmeta uses these)
3145	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3146	* AMD: Reserved
3147	* VIA: Reserved
3148	* Safe to expose
3149	*/
3150	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3151	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3152	{
3153	uSubLeaf = 0;
3154	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3155	{
3156	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3157	if (pCpum->u8PortableCpuIdLevel > 0)
3158	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3159	uSubLeaf++;
3160	}
3161	}
3162
3163	/* Cpuid 4 + ECX:
3164	* Intel: Deterministic Cache Parameters Leaf.
3165	* AMD: Reserved
3166	* VIA: Reserved
3167	* Safe to expose, except for EAX:
3168	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3169	* Bits 31-26: Maximum number of processor cores in this physical package**
3170	* Note: These SMP values are constant regardless of ECX
3171	*/
3172	uSubLeaf = 0;
3173	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3174	{
3175	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3176	#ifdef VBOX_WITH_MULTI_CORE
3177	if ( pVM->cCpus > 1
3178	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3179	{
3180	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3181	/* One logical processor with possibly multiple cores. */
3182	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3183	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3184	}
3185	#endif
3186	uSubLeaf++;
3187	}
3188
3189	/* Cpuid 5: Monitor/mwait Leaf
3190	* Intel: ECX, EDX - reserved
3191	* EAX, EBX - Smallest and largest monitor line size
3192	* AMD: EDX - reserved
3193	* EAX, EBX - Smallest and largest monitor line size
3194	* ECX - extensions (ignored for now)
3195	* VIA: Reserved
3196	* Safe to expose
3197	*/
3198	uSubLeaf = 0;
3199	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3200	{
3201	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3202	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3203	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3204
3205	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3206	if (pConfig->enmMWaitExtensions)
3207	{
3208	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3209	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3210	it shall be part of our power management virtualization model */
3211	#if 0
3212	/* MWAIT sub C-states */
3213	pCurLeaf->uEdx =
3214	(0 << 0) /* 0 in C0 */ \|
3215	(2 << 4) /* 2 in C1 */ \|
3216	(2 << 8) /* 2 in C2 */ \|
3217	(2 << 12) /* 2 in C3 */ \|
3218	(0 << 16) /* 0 in C4 */
3219	;
3220	#endif
3221	}
3222	else
3223	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3224	uSubLeaf++;
3225	}
3226
3227	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3228	* Intel: Various stuff.
3229	* AMD: EAX, EBX, EDX - reserved.
3230	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3231	* present. Same as intel.
3232	* VIA: ??
3233	*
3234	* We clear everything here for now.
3235	*/
3236	cpumR3CpuIdZeroLeaf(pCpum, 6);
3237
3238	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3239	* EAX: Number of sub leaves.
3240	* EBX+ECX+EDX: Feature flags
3241	*
3242	* We only have documentation for one sub-leaf, so clear all other (no need
3243	* to remove them as such, just set them to zero).
3244	*
3245	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3246	* options may require adjusting (i.e. stripping what was enabled).
3247	*/
3248	uSubLeaf = 0;
3249	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3250	{
3251	switch (uSubLeaf)
3252	{
3253	case 0:
3254	{
3255	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3256	pCurLeaf->uEbx &= 0
3257	\| (pConfig->enmFsGsBase ? X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE : 0)
3258	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3259	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3260	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3261	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3262	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3263	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3264	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3265	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3266	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3267	\| (pConfig->enmInvpcid ? X86_CPUID_STEXT_FEATURE_EBX_INVPCID : 0)
3268	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3269	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3270	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3271	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3272	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3273	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3274	//\| RT_BIT(17) - reserved
3275	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3276	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3277	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3278	//\| RT_BIT(21) - reserved
3279	//\| RT_BIT(22) - reserved
3280	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3281	//\| RT_BIT(24) - reserved
3282	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3283	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3284	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3285	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3286	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3287	//\| RT_BIT(30) - reserved
3288	//\| RT_BIT(31) - reserved
3289	;
3290	pCurLeaf->uEcx &= 0
3291	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3292	;
3293	pCurLeaf->uEdx &= 0
3294	\| (pConfig->enmMdsClear ? X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR : 0)
3295	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3296	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3297	\| (pConfig->enmFlushCmdMsr ? X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD : 0)
3298	\| (pConfig->enmArchCapMsr ? X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP : 0)
3299	;
3300
3301	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3302	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3303	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3304	{
3305	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3306	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3307	}
3308
3309	if (pCpum->u8PortableCpuIdLevel > 0)
3310	{
3311	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3312	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3313	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3314	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3315	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3316	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3317	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3318	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3319	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3320	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3321	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3322	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3323	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3324	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3325	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3326	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
3327	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
3328	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
3329	}
3330
3331	/* Dependencies. */
3332	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
3333	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3334
3335	/* Force standard feature bits. */
3336	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3337	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3338	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3339	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3340	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3341	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3342	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3343	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3344	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3345	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3346	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3347	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
3348	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
3349	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3350	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3351	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
3352	break;
3353	}
3354
3355	default:
3356	/* Invalid index, all values are zero. */
3357	pCurLeaf->uEax = 0;
3358	pCurLeaf->uEbx = 0;
3359	pCurLeaf->uEcx = 0;
3360	pCurLeaf->uEdx = 0;
3361	break;
3362	}
3363	uSubLeaf++;
3364	}
3365
3366	/* Cpuid 8: Marked as reserved by Intel and AMD.
3367	* We zero this since we don't know what it may have been used for.
3368	*/
3369	cpumR3CpuIdZeroLeaf(pCpum, 8);
3370
3371	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3372	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3373	* EBX, ECX, EDX - reserved.
3374	* AMD: Reserved
3375	* VIA: ??
3376	*
3377	* We zero this.
3378	*/
3379	cpumR3CpuIdZeroLeaf(pCpum, 9);
3380
3381	/* Cpuid 0xa: Architectural Performance Monitor Features
3382	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3383	* EBX, ECX, EDX - reserved.
3384	* AMD: Reserved
3385	* VIA: ??
3386	*
3387	* We zero this, for now at least.
3388	*/
3389	cpumR3CpuIdZeroLeaf(pCpum, 10);
3390
3391	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3392	* Intel: EAX - APCI ID shift right for next level.
3393	* EBX - Factory configured cores/threads at this level.
3394	* ECX - Level number (same as input) and level type (1,2,0).
3395	* EDX - Extended initial APIC ID.
3396	* AMD: Reserved
3397	* VIA: ??
3398	*/
3399	uSubLeaf = 0;
3400	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3401	{
3402	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3403	{
3404	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3405	if (bLevelType == 1)
3406	{
3407	/* Thread level - we don't do threads at the moment. */
3408	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3409	pCurLeaf->uEbx = 1;
3410	}
3411	else if (bLevelType == 2)
3412	{
3413	/* Core level. */
3414	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3415	#ifdef VBOX_WITH_MULTI_CORE
3416	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3417	pCurLeaf->uEax++;
3418	#endif
3419	pCurLeaf->uEbx = pVM->cCpus;
3420	}
3421	else
3422	{
3423	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3424	pCurLeaf->uEax = 0;
3425	pCurLeaf->uEbx = 0;
3426	pCurLeaf->uEcx = 0;
3427	}
3428	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3429	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3430	}
3431	else
3432	{
3433	pCurLeaf->uEax = 0;
3434	pCurLeaf->uEbx = 0;
3435	pCurLeaf->uEcx = 0;
3436	pCurLeaf->uEdx = 0;
3437	}
3438	uSubLeaf++;
3439	}
3440
3441	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3442	* We zero this since we don't know what it may have been used for.
3443	*/
3444	cpumR3CpuIdZeroLeaf(pCpum, 12);
3445
3446	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3447	* ECX=0: EAX - Valid bits in XCR0[31:0].
3448	* EBX - Maximum state size as per current XCR0 value.
3449	* ECX - Maximum state size for all supported features.
3450	* EDX - Valid bits in XCR0[63:32].
3451	* ECX=1: EAX - Various X-features.
3452	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3453	* ECX - Valid bits in IA32_XSS[31:0].
3454	* EDX - Valid bits in IA32_XSS[63:32].
3455	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3456	* if the bit invalid all four registers are set to zero.
3457	* EAX - The state size for this feature.
3458	* EBX - The state byte offset of this feature.
3459	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3460	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3461	*
3462	* Clear them all as we don't currently implement extended CPU state.
3463	*/
3464	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3465	uint64_t fGuestXcr0Mask = 0;
3466	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3467	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3468	{
3469	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3470	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3471	fGuestXcr0Mask \|= XSAVE_C_YMM;
3472	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3473	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3474	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3475	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3476
3477	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3478	}
3479	pStdFeatureLeaf = NULL;
3480	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3481
3482	/* Work the sub-leaves. */
3483	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3484	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3485	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3486	{
3487	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3488	if (pCurLeaf)
3489	{
3490	if (fGuestXcr0Mask)
3491	{
3492	switch (uSubLeaf)
3493	{
3494	case 0:
3495	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3496	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3497	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3498	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3499	VERR_CPUM_IPE_1);
3500	cbXSaveMaxActual = pCurLeaf->uEcx;
3501	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3502	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3503	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3504	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3505	VERR_CPUM_IPE_2);
3506	continue;
3507	case 1:
3508	pCurLeaf->uEax &= 0;
3509	pCurLeaf->uEcx &= 0;
3510	pCurLeaf->uEdx &= 0;
3511	/** @todo what about checking ebx? */
3512	continue;
3513	default:
3514	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3515	{
3516	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3517	&& pCurLeaf->uEax > 0
3518	&& pCurLeaf->uEbx < cbXSaveMaxActual
3519	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3520	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3521	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3522	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3523	VERR_CPUM_IPE_2);
3524	AssertLogRel(!(pCurLeaf->uEcx & 1));
3525	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3526	pCurLeaf->uEdx = 0; /* it's reserved... */
3527	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3528	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3529	continue;
3530	}
3531	break;
3532	}
3533	}
3534
3535	/* Clear the leaf. */
3536	pCurLeaf->uEax = 0;
3537	pCurLeaf->uEbx = 0;
3538	pCurLeaf->uEcx = 0;
3539	pCurLeaf->uEdx = 0;
3540	}
3541	}
3542
3543	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3544	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3545	{
3546	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3547	if (pCurLeaf)
3548	{
3549	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3550	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3551	pCurLeaf->uEbx = cbXSaveMaxReport;
3552	pCurLeaf->uEcx = cbXSaveMaxReport;
3553	}
3554	}
3555
3556	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3557	* We zero this since we don't know what it may have been used for.
3558	*/
3559	cpumR3CpuIdZeroLeaf(pCpum, 14);
3560
3561	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3562	* also known as Intel Resource Director Technology (RDT) Monitoring
3563	* We zero this as we don't currently virtualize PQM.
3564	*/
3565	cpumR3CpuIdZeroLeaf(pCpum, 15);
3566
3567	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3568	* also known as Intel Resource Director Technology (RDT) Allocation
3569	* We zero this as we don't currently virtualize PQE.
3570	*/
3571	cpumR3CpuIdZeroLeaf(pCpum, 16);
3572
3573	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3574	* We zero this since we don't know what it may have been used for.
3575	*/
3576	cpumR3CpuIdZeroLeaf(pCpum, 17);
3577
3578	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3579	* We zero this as we don't currently virtualize this.
3580	*/
3581	cpumR3CpuIdZeroLeaf(pCpum, 18);
3582
3583	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3584	* We zero this since we don't know what it may have been used for.
3585	*/
3586	cpumR3CpuIdZeroLeaf(pCpum, 19);
3587
3588	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3589	* We zero this as we don't currently virtualize this.
3590	*/
3591	cpumR3CpuIdZeroLeaf(pCpum, 20);
3592
3593	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3594	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3595	* EAX - denominator (unsigned).
3596	* EBX - numerator (unsigned).
3597	* ECX, EDX - reserved.
3598	* AMD: Reserved / undefined / not implemented.
3599	* VIA: Reserved / undefined / not implemented.
3600	* We zero this as we don't currently virtualize this.
3601	*/
3602	cpumR3CpuIdZeroLeaf(pCpum, 21);
3603
3604	/* Cpuid 0x16: Processor frequency info
3605	* Intel: EAX - Core base frequency in MHz.
3606	* EBX - Core maximum frequency in MHz.
3607	* ECX - Bus (reference) frequency in MHz.
3608	* EDX - Reserved.
3609	* AMD: Reserved / undefined / not implemented.
3610	* VIA: Reserved / undefined / not implemented.
3611	* We zero this as we don't currently virtualize this.
3612	*/
3613	cpumR3CpuIdZeroLeaf(pCpum, 22);
3614
3615	/* Cpuid 0x17..0x10000000: Unknown.
3616	* We don't know these and what they mean, so remove them. */
3617	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3618	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3619
3620
3621	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3622	* We remove all these as we're a hypervisor and must provide our own.
3623	*/
3624	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3625	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3626
3627
3628	/* Cpuid 0x80000000 is harmless. */
3629
3630	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3631
3632	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3633
3634	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3635	* Safe to pass on to the guest.
3636	*
3637	* AMD: 0x800000005 L1 cache information
3638	* 0x800000006 L2/L3 cache information
3639	* Intel: 0x800000005 reserved
3640	* 0x800000006 L2 cache information
3641	* VIA: 0x800000005 TLB and L1 cache information
3642	* 0x800000006 L2 cache information
3643	*/
3644
3645	/* Cpuid 0x800000007: Advanced Power Management Information.
3646	* AMD: EAX: Processor feedback capabilities.
3647	* EBX: RAS capabilites.
3648	* ECX: Advanced power monitoring interface.
3649	* EDX: Enhanced power management capabilities.
3650	* Intel: EAX, EBX, ECX - reserved.
3651	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3652	* VIA: Reserved
3653	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3654	*/
3655	uSubLeaf = 0;
3656	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3657	{
3658	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3659	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3660	{
3661	/*
3662	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3663	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3664	* bit is now configurable.
3665	*/
3666	pCurLeaf->uEdx &= 0
3667	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3668	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3669	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3670	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3671	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3672	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3673	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3674	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3675	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3676	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3677	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3678	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3679	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3680	\| 0;
3681	}
3682	else
3683	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3684	if (!pConfig->fInvariantTsc)
3685	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3686	uSubLeaf++;
3687	}
3688
3689	/* Cpuid 0x80000008:
3690	* AMD: EBX, EDX - reserved
3691	* EAX: Virtual/Physical/Guest address Size
3692	* ECX: Number of cores + APICIdCoreIdSize
3693	* Intel: EAX: Virtual/Physical address Size
3694	* EBX, ECX, EDX - reserved
3695	* VIA: EAX: Virtual/Physical address Size
3696	* EBX, ECX, EDX - reserved
3697	*
3698	* We only expose the virtual+pysical address size to the guest atm.
3699	* On AMD we set the core count, but not the apic id stuff as we're
3700	* currently not doing the apic id assignments in a complatible manner.
3701	*/
3702	uSubLeaf = 0;
3703	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3704	{
3705	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3706	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3707	pCurLeaf->uEdx = 0; /* reserved */
3708
3709	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3710	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3711	pCurLeaf->uEcx = 0;
3712	#ifdef VBOX_WITH_MULTI_CORE
3713	if ( pVM->cCpus > 1
3714	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3715	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3716	#endif
3717	uSubLeaf++;
3718	}
3719
3720	/* Cpuid 0x80000009: Reserved
3721	* We zero this since we don't know what it may have been used for.
3722	*/
3723	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3724
3725	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
3726	* AMD: EAX - SVM revision.
3727	* EBX - Number of ASIDs.
3728	* ECX - Reserved.
3729	* EDX - SVM Feature identification.
3730	*/
3731	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3732	{
3733	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3734	if ( pExtFeatureLeaf
3735	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
3736	{
3737	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3738	if (pSvmFeatureLeaf)
3739	{
3740	pSvmFeatureLeaf->uEax = 0x1;
3741	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3742	pSvmFeatureLeaf->uEcx = 0;
3743	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3744	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3745	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3746	}
3747	else
3748	{
3749	/* Should never happen. */
3750	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
3751	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3752	}
3753	}
3754	else
3755	{
3756	/* If SVM is not supported, this is reserved, zero out. */
3757	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3758	}
3759	}
3760	else
3761	{
3762	/* Cpuid 0x8000000a: Reserved on Intel.
3763	* We zero this since we don't know what it may have been used for.
3764	*/
3765	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3766	}
3767
3768	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3769	* We clear these as we don't know what purpose they might have. */
3770	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3771	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3772
3773	/* Cpuid 0x80000019: TLB configuration
3774	* Seems to be harmless, pass them thru as is. */
3775
3776	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3777	* Strip anything we don't know what is or addresses feature we don't implement. */
3778	uSubLeaf = 0;
3779	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3780	{
3781	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3782	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3783	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3784	;
3785	pCurLeaf->uEbx = 0; /* reserved */
3786	pCurLeaf->uEcx = 0; /* reserved */
3787	pCurLeaf->uEdx = 0; /* reserved */
3788	uSubLeaf++;
3789	}
3790
3791	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3792	* Clear this as we don't currently virtualize this feature. */
3793	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3794
3795	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3796	* Clear this as we don't currently virtualize this feature. */
3797	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3798
3799	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3800	* We need to sanitize the cores per cache (EAX[25:14]).
3801	*
3802	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3803	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3804	* slightly different meaning.
3805	*/
3806	uSubLeaf = 0;
3807	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3808	{
3809	#ifdef VBOX_WITH_MULTI_CORE
3810	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3811	if (cCores > pVM->cCpus)
3812	cCores = pVM->cCpus;
3813	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3814	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3815	#else
3816	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3817	#endif
3818	uSubLeaf++;
3819	}
3820
3821	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3822	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3823	* setup, we have one compute unit with all the cores in it. Single node.
3824	*/
3825	uSubLeaf = 0;
3826	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3827	{
3828	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3829	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3830	{
3831	#ifdef VBOX_WITH_MULTI_CORE
3832	pCurLeaf->uEbx = pVM->cCpus < 0x100
3833	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3834	#else
3835	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3836	#endif
3837	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3838	}
3839	else
3840	{
3841	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3842	pCurLeaf->uEbx = 0; /* Reserved. */
3843	pCurLeaf->uEcx = 0; /* Reserved. */
3844	}
3845	pCurLeaf->uEdx = 0; /* Reserved. */
3846	uSubLeaf++;
3847	}
3848
3849	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3850	* We don't know these and what they mean, so remove them. */
3851	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3852	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3853
3854	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3855	* Just pass it thru for now. */
3856
3857	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3858	* Just pass it thru for now. */
3859
3860	/* Cpuid 0xc0000000: Centaur stuff.
3861	* Harmless, pass it thru. */
3862
3863	/* Cpuid 0xc0000001: Centaur features.
3864	* VIA: EAX - Family, model, stepping.
3865	* EDX - Centaur extended feature flags. Nothing interesting, except may
3866	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3867	* EBX, ECX - reserved.
3868	* We keep EAX but strips the rest.
3869	*/
3870	uSubLeaf = 0;
3871	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3872	{
3873	pCurLeaf->uEbx = 0;
3874	pCurLeaf->uEcx = 0;
3875	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3876	uSubLeaf++;
3877	}
3878
3879	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3880	* We only have fixed stale values, but should be harmless. */
3881
3882	/* Cpuid 0xc0000003: Reserved.
3883	* We zero this since we don't know what it may have been used for.
3884	*/
3885	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3886
3887	/* Cpuid 0xc0000004: Centaur Performance Info.
3888	* We only have fixed stale values, but should be harmless. */
3889
3890
3891	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3892	* We don't know these and what they mean, so remove them. */
3893	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3894	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3895
3896	return VINF_SUCCESS;
3897	#undef PORTABLE_DISABLE_FEATURE_BIT
3898	#undef PORTABLE_CLEAR_BITS_WHEN
3899	}
3900
3901
3902	/**
3903	* Reads a value in /CPUM/IsaExts/ node.
3904	*
3905	* @returns VBox status code (error message raised).
3906	* @param pVM The cross context VM structure. (For errors.)
3907	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3908	* @param pszValueName The value / extension name.
3909	* @param penmValue Where to return the choice.
3910	* @param enmDefault The default choice.
3911	*/
3912	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3913	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3914	{
3915	/*
3916	* Try integer encoding first.
3917	*/
3918	uint64_t uValue;
3919	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3920	if (RT_SUCCESS(rc))
3921	switch (uValue)
3922	{
3923	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3924	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3925	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3926	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3927	default:
3928	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3929	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3930	pszValueName, uValue);
3931	}
3932	/*
3933	* If missing, use default.
3934	*/
3935	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3936	*penmValue = enmDefault;
3937	else
3938	{
3939	if (rc == VERR_CFGM_NOT_INTEGER)
3940	{
3941	/*
3942	* Not an integer, try read it as a string.
3943	*/
3944	char szValue[32];
3945	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3946	if (RT_SUCCESS(rc))
3947	{
3948	RTStrToLower(szValue);
3949	size_t cchValue = strlen(szValue);
3950	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3951	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3952	*penmValue = CPUMISAEXTCFG_DISABLED;
3953	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3954	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3955	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3956	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3957	else if (EQ("portable"))
3958	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3959	else if (EQ("default") \|\| EQ("def"))
3960	*penmValue = enmDefault;
3961	else
3962	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3963	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3964	pszValueName, uValue);
3965	#undef EQ
3966	}
3967	}
3968	if (RT_FAILURE(rc))
3969	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3970	}
3971	return VINF_SUCCESS;
3972	}
3973
3974
3975	/**
3976	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3977	*
3978	* @returns VBox status code (error message raised).
3979	* @param pVM The cross context VM structure. (For errors.)
3980	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3981	* @param pszValueName The value / extension name.
3982	* @param penmValue Where to return the choice.
3983	* @param enmDefault The default choice.
3984	* @param fAllowed Allowed choice. Applied both to the result and to
3985	* the default value.
3986	*/
3987	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3988	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3989	{
3990	int rc;
3991	if (fAllowed)
3992	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3993	else
3994	{
3995	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3996	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3997	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3998	*penmValue = CPUMISAEXTCFG_DISABLED;
3999	}
4000	return rc;
4001	}
4002
4003
4004	/**
4005	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
4006	*
4007	* @returns VBox status code (error message raised).
4008	* @param pVM The cross context VM structure. (For errors.)
4009	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4010	* @param pCpumCfg The /CPUM node (can be NULL).
4011	* @param pszValueName The value / extension name.
4012	* @param penmValue Where to return the choice.
4013	* @param enmDefault The default choice.
4014	*/
4015	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
4016	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
4017	{
4018	if (CFGMR3Exists(pCpumCfg, pszValueName))
4019	{
4020	if (!CFGMR3Exists(pIsaExts, pszValueName))
4021	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
4022	else
4023	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
4024	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
4025	pszValueName, pszValueName);
4026
4027	bool fLegacy;
4028	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
4029	if (RT_SUCCESS(rc))
4030	{
4031	*penmValue = fLegacy;
4032	return VINF_SUCCESS;
4033	}
4034	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
4035	}
4036
4037	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4038	}
4039
4040
4041	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
4042	{
4043	int rc;
4044
4045	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
4046	* When non-zero CPUID features that could cause portability issues will be
4047	* stripped. The higher the value the more features gets stripped. Higher
4048	* values should only be used when older CPUs are involved since it may
4049	* harm performance and maybe also cause problems with specific guests. */
4050	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
4051	AssertLogRelRCReturn(rc, rc);
4052
4053	/** @cfgm{/CPUM/GuestCpuName, string}
4054	* The name of the CPU we're to emulate. The default is the host CPU.
4055	* Note! CPUs other than "host" one is currently unsupported. */
4056	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
4057	AssertLogRelRCReturn(rc, rc);
4058
4059	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
4060	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
4061	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
4062	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
4063	*/
4064	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
4065	AssertLogRelRCReturn(rc, rc);
4066
4067	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
4068	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
4069	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
4070	* 64-bit linux guests which assume the presence of AMD performance counters
4071	* that we do not virtualize.
4072	*/
4073	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
4074	AssertLogRelRCReturn(rc, rc);
4075
4076	/** @cfgm{/CPUM/ForceVme, boolean, false}
4077	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
4078	* By default the flag is passed thru as is from the host CPU, except
4079	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
4080	* guests and DOS boxes in general.
4081	*/
4082	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
4083	AssertLogRelRCReturn(rc, rc);
4084
4085	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
4086	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
4087	* probably going to be a temporary hack, so don't depend on this.
4088	* The 1st byte of the value is the stepping, the 2nd byte value is the model
4089	* number and the 3rd byte value is the family, and the 4th value must be zero.
4090	*/
4091	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
4092	AssertLogRelRCReturn(rc, rc);
4093
4094	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
4095	* The last standard leaf to keep. The actual last value that is stored in EAX
4096	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
4097	* removed. (This works independently of and differently from NT4LeafLimit.)
4098	* The default is usually set to what we're able to reasonably sanitize.
4099	*/
4100	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
4101	AssertLogRelRCReturn(rc, rc);
4102
4103	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
4104	* The last extended leaf to keep. The actual last value that is stored in EAX
4105	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
4106	* leaf are removed. The default is set to what we're able to sanitize.
4107	*/
4108	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
4109	AssertLogRelRCReturn(rc, rc);
4110
4111	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
4112	* The last extended leaf to keep. The actual last value that is stored in EAX
4113	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
4114	* leaf are removed. The default is set to what we're able to sanitize.
4115	*/
4116	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
4117	AssertLogRelRCReturn(rc, rc);
4118
4119	bool fQueryNestedHwvirt = false;
4120	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4121	fQueryNestedHwvirt \|= RT_BOOL(pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD);
4122	#endif
4123	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4124	fQueryNestedHwvirt \|= RT_BOOL( pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
4125	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA);
4126	#endif
4127	if (fQueryNestedHwvirt)
4128	{
4129	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
4130	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
4131	* The default is false, and when enabled requires a 64-bit CPU with support for
4132	* nested-paging and AMD-V or unrestricted guest mode.
4133	*/
4134	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
4135	AssertLogRelRCReturn(rc, rc);
4136	if ( pConfig->fNestedHWVirt
4137	&& !fNestedPagingAndFullGuestExec)
4138	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4139	"Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
4140
4141	/** @todo Think about enabling this later with NEM/KVM. */
4142	if ( pConfig->fNestedHWVirt
4143	&& VM_IS_NEM_ENABLED(pVM))
4144	{
4145	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
4146	pConfig->fNestedHWVirt = false;
4147	}
4148	}
4149
4150	/*
4151	* Instruction Set Architecture (ISA) Extensions.
4152	*/
4153	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
4154	if (pIsaExts)
4155	{
4156	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
4157	"CMPXCHG16B"
4158	"\|MONITOR"
4159	"\|MWaitExtensions"
4160	"\|SSE4.1"
4161	"\|SSE4.2"
4162	"\|XSAVE"
4163	"\|AVX"
4164	"\|AVX2"
4165	"\|AESNI"
4166	"\|PCLMUL"
4167	"\|POPCNT"
4168	"\|MOVBE"
4169	"\|RDRAND"
4170	"\|RDSEED"
4171	"\|CLFLUSHOPT"
4172	"\|FSGSBASE"
4173	"\|PCID"
4174	"\|INVPCID"
4175	"\|FlushCmdMsr"
4176	"\|ABM"
4177	"\|SSE4A"
4178	"\|MISALNSSE"
4179	"\|3DNOWPRF"
4180	"\|AXMMX"
4181	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
4182	if (RT_FAILURE(rc))
4183	return rc;
4184	}
4185
4186	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
4187	* Expose CMPXCHG16B to the guest if supported by the host. For the time
4188	* being the default is to only do this for VMs with nested paging and AMD-V or
4189	* unrestricted guest mode.
4190	*/
4191	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
4192	AssertLogRelRCReturn(rc, rc);
4193
4194	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4195	* Expose MONITOR/MWAIT instructions to the guest.
4196	*/
4197	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4198	AssertLogRelRCReturn(rc, rc);
4199
4200	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4201	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4202	* break on interrupt feature (bit 1).
4203	*/
4204	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4205	AssertLogRelRCReturn(rc, rc);
4206
4207	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4208	* Expose SSE4.1 to the guest if available.
4209	*/
4210	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4211	AssertLogRelRCReturn(rc, rc);
4212
4213	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4214	* Expose SSE4.2 to the guest if available.
4215	*/
4216	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4217	AssertLogRelRCReturn(rc, rc);
4218
4219	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4220	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4221	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor;
4222	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4223
4224	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4225	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4226	* default is to only expose this to VMs with nested paging and AMD-V or
4227	* unrestricted guest execution mode. Not possible to force this one without
4228	* host support at the moment.
4229	*/
4230	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4231	fMayHaveXSave /fAllowed/);
4232	AssertLogRelRCReturn(rc, rc);
4233
4234	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4235	* Expose the AVX instruction set extensions to the guest if available and
4236	* XSAVE is exposed too. For the time being the default is to only expose this
4237	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4238	*/
4239	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4240	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4241	AssertLogRelRCReturn(rc, rc);
4242
4243	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4244	* Expose the AVX2 instruction set extensions to the guest if available and
4245	* XSAVE is exposed too. For the time being the default is to only expose this
4246	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4247	*/
4248	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4249	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4250	AssertLogRelRCReturn(rc, rc);
4251
4252	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4253	* Whether to expose the AES instructions to the guest. For the time being the
4254	* default is to only do this for VMs with nested paging and AMD-V or
4255	* unrestricted guest mode.
4256	*/
4257	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4258	AssertLogRelRCReturn(rc, rc);
4259
4260	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4261	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4262	* being the default is to only do this for VMs with nested paging and AMD-V or
4263	* unrestricted guest mode.
4264	*/
4265	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4266	AssertLogRelRCReturn(rc, rc);
4267
4268	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4269	* Whether to expose the POPCNT instructions to the guest. For the time
4270	* being the default is to only do this for VMs with nested paging and AMD-V or
4271	* unrestricted guest mode.
4272	*/
4273	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4274	AssertLogRelRCReturn(rc, rc);
4275
4276	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4277	* Whether to expose the MOVBE instructions to the guest. For the time
4278	* being the default is to only do this for VMs with nested paging and AMD-V or
4279	* unrestricted guest mode.
4280	*/
4281	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4282	AssertLogRelRCReturn(rc, rc);
4283
4284	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4285	* Whether to expose the RDRAND instructions to the guest. For the time being
4286	* the default is to only do this for VMs with nested paging and AMD-V or
4287	* unrestricted guest mode.
4288	*/
4289	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4290	AssertLogRelRCReturn(rc, rc);
4291
4292	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4293	* Whether to expose the RDSEED instructions to the guest. For the time being
4294	* the default is to only do this for VMs with nested paging and AMD-V or
4295	* unrestricted guest mode.
4296	*/
4297	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4298	AssertLogRelRCReturn(rc, rc);
4299
4300	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4301	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4302	* being the default is to only do this for VMs with nested paging and AMD-V or
4303	* unrestricted guest mode.
4304	*/
4305	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4306	AssertLogRelRCReturn(rc, rc);
4307
4308	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4309	* Whether to expose the read/write FSGSBASE instructions to the guest.
4310	*/
4311	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4312	AssertLogRelRCReturn(rc, rc);
4313
4314	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4315	* Whether to expose the PCID feature to the guest.
4316	*/
4317	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4318	AssertLogRelRCReturn(rc, rc);
4319
4320	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4321	* Whether to expose the INVPCID instruction to the guest.
4322	*/
4323	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4324	AssertLogRelRCReturn(rc, rc);
4325
4326	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
4327	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
4328	*/
4329	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4330	AssertLogRelRCReturn(rc, rc);
4331
4332	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
4333	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
4334	* the guest. Requires FlushCmdMsr to be present too.
4335	*/
4336	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4337	AssertLogRelRCReturn(rc, rc);
4338
4339	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
4340	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
4341	*/
4342	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4343	AssertLogRelRCReturn(rc, rc);
4344
4345
4346	/* AMD: */
4347
4348	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4349	* Whether to expose the AMD ABM instructions to the guest. For the time
4350	* being the default is to only do this for VMs with nested paging and AMD-V or
4351	* unrestricted guest mode.
4352	*/
4353	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4354	AssertLogRelRCReturn(rc, rc);
4355
4356	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4357	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4358	* being the default is to only do this for VMs with nested paging and AMD-V or
4359	* unrestricted guest mode.
4360	*/
4361	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4362	AssertLogRelRCReturn(rc, rc);
4363
4364	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4365	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4366	* the time being the default is to only do this for VMs with nested paging and
4367	* AMD-V or unrestricted guest mode.
4368	*/
4369	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4370	AssertLogRelRCReturn(rc, rc);
4371
4372	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4373	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4374	* For the time being the default is to only do this for VMs with nested paging
4375	* and AMD-V or unrestricted guest mode.
4376	*/
4377	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4378	AssertLogRelRCReturn(rc, rc);
4379
4380	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4381	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4382	* the default is to only do this for VMs with nested paging and AMD-V or
4383	* unrestricted guest mode.
4384	*/
4385	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4386	AssertLogRelRCReturn(rc, rc);
4387
4388	return VINF_SUCCESS;
4389	}
4390
4391
4392	/**
4393	* Initializes the emulated CPU's CPUID & MSR information.
4394	*
4395	* @returns VBox status code.
4396	* @param pVM The cross context VM structure.
4397	* @param pHostMsrs Pointer to the host MSRs.
4398	*/
4399	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
4400	{
4401	Assert(pHostMsrs);
4402
4403	PCPUM pCpum = &pVM->cpum.s;
4404	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4405
4406	/*
4407	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4408	* on construction and manage everything from here on.
4409	*/
4410	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
4411	pVM->aCpus[iCpu].cpum.s.fCpuIdApicFeatureVisible = true;
4412
4413	/*
4414	* Read the configuration.
4415	*/
4416	CPUMCPUIDCONFIG Config;
4417	RT_ZERO(Config);
4418
4419	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4420	AssertRCReturn(rc, rc);
4421
4422	/*
4423	* Get the guest CPU data from the database and/or the host.
4424	*
4425	* The CPUID and MSRs are currently living on the regular heap to avoid
4426	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4427	* API for the hyper heap). This means special cleanup considerations.
4428	*/
4429	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4430	if (RT_FAILURE(rc))
4431	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4432	? VMSetError(pVM, rc, RT_SRC_POS,
4433	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4434	: rc;
4435
4436	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4437	{
4438	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4439	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4440	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4441	}
4442	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4443
4444	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4445	* Overrides the guest MSRs.
4446	*/
4447	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4448
4449	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4450	* Overrides the CPUID leaf values (from the host CPU usually) used for
4451	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4452	* values when moving a VM to a different machine. Another use is restricting
4453	* (or extending) the feature set exposed to the guest. */
4454	if (RT_SUCCESS(rc))
4455	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4456
4457	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4458	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4459	"Found unsupported configuration node '/CPUM/CPUID/'. "
4460	"Please use IMachine::setCPUIDLeaf() instead.");
4461
4462	CPUMMSRS GuestMsrs;
4463	RT_ZERO(GuestMsrs);
4464
4465	/*
4466	* Pre-explode the CPUID info.
4467	*/
4468	if (RT_SUCCESS(rc))
4469	{
4470	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
4471	&pCpum->GuestFeatures);
4472	}
4473
4474	/*
4475	* Sanitize the cpuid information passed on to the guest.
4476	*/
4477	if (RT_SUCCESS(rc))
4478	{
4479	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4480	if (RT_SUCCESS(rc))
4481	{
4482	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4483	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4484	}
4485	}
4486
4487	/*
4488	* Setup MSRs introduced in microcode updates or that are otherwise not in
4489	* the CPU profile, but are advertised in the CPUID info we just sanitized.
4490	*/
4491	if (RT_SUCCESS(rc))
4492	rc = cpumR3MsrReconcileWithCpuId(pVM);
4493	/*
4494	* MSR fudging.
4495	*/
4496	if (RT_SUCCESS(rc))
4497	{
4498	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4499	* Fudges some common MSRs if not present in the selected CPU database entry.
4500	* This is for trying to keep VMs running when moved between different hosts
4501	* and different CPU vendors. */
4502	bool fEnable;
4503	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4504	if (RT_SUCCESS(rc) && fEnable)
4505	{
4506	rc = cpumR3MsrApplyFudge(pVM);
4507	AssertLogRelRC(rc);
4508	}
4509	}
4510	if (RT_SUCCESS(rc))
4511	{
4512	/*
4513	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4514	* guest CPU features again.
4515	*/
4516	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4517	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4518	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
4519	RTMemFree(pvFree);
4520
4521	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4522	int rc2 = MMHyperDupMem(pVM, pvFree,
4523	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4524	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4525	RTMemFree(pvFree);
4526	AssertLogRelRCReturn(rc1, rc1);
4527	AssertLogRelRCReturn(rc2, rc2);
4528
4529	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4530
4531	/*
4532	* Finally, initialize guest VMX MSRs.
4533	*
4534	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
4535	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
4536	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
4537	*/
4538	if (pVM->cpum.s.GuestFeatures.fVmx)
4539	{
4540	Assert(Config.fNestedHWVirt);
4541	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
4542
4543	/* Copy MSRs to all VCPUs */
4544	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
4545	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4546	{
4547	PVMCPU pVCpu = &pVM->aCpus[idCpu];
4548	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
4549	}
4550	}
4551
4552	/*
4553	* Some more configuration that we're applying at the end of everything
4554	* via the CPUMR3SetGuestCpuIdFeature API.
4555	*/
4556
4557	/* Check if PAE was explicitely enabled by the user. */
4558	bool fEnable;
4559	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4560	AssertRCReturn(rc, rc);
4561	if (fEnable)
4562	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4563
4564	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4565	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4566	AssertRCReturn(rc, rc);
4567	if (fEnable)
4568	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4569
4570	/* Check if speculation control is enabled. */
4571	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4572	AssertRCReturn(rc, rc);
4573	if (fEnable)
4574	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4575
4576	return VINF_SUCCESS;
4577	}
4578
4579	/*
4580	* Failed before switching to hyper heap.
4581	*/
4582	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4583	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4584	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4585	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4586	return rc;
4587	}
4588
4589
4590	/**
4591	* Sets a CPUID feature bit during VM initialization.
4592	*
4593	* Since the CPUID feature bits are generally related to CPU features, other
4594	* CPUM configuration like MSRs can also be modified by calls to this API.
4595	*
4596	* @param pVM The cross context VM structure.
4597	* @param enmFeature The feature to set.
4598	*/
4599	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4600	{
4601	PCPUMCPUIDLEAF pLeaf;
4602	PCPUMMSRRANGE pMsrRange;
4603
4604	switch (enmFeature)
4605	{
4606	/*
4607	* Set the APIC bit in both feature masks.
4608	*/
4609	case CPUMCPUIDFEATURE_APIC:
4610	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4611	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4612	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4613
4614	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4615	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4616	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4617
4618	pVM->cpum.s.GuestFeatures.fApic = 1;
4619
4620	/* Make sure we've got the APICBASE MSR present. */
4621	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4622	if (!pMsrRange)
4623	{
4624	static CPUMMSRRANGE const s_ApicBase =
4625	{
4626	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4627	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4628	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4629	/.szName = / "IA32_APIC_BASE"
4630	};
4631	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4632	AssertLogRelRC(rc);
4633	}
4634
4635	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4636	break;
4637
4638	/*
4639	* Set the x2APIC bit in the standard feature mask.
4640	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4641	*/
4642	case CPUMCPUIDFEATURE_X2APIC:
4643	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4644	if (pLeaf)
4645	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4646	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4647
4648	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4649	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4650	if (pMsrRange)
4651	{
4652	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4653	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4654	}
4655
4656	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4657	break;
4658
4659	/*
4660	* Set the sysenter/sysexit bit in the standard feature mask.
4661	* Assumes the caller knows what it's doing! (host must support these)
4662	*/
4663	case CPUMCPUIDFEATURE_SEP:
4664	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4665	{
4666	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4667	return;
4668	}
4669
4670	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4671	if (pLeaf)
4672	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4673	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4674	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4675	break;
4676
4677	/*
4678	* Set the syscall/sysret bit in the extended feature mask.
4679	* Assumes the caller knows what it's doing! (host must support these)
4680	*/
4681	case CPUMCPUIDFEATURE_SYSCALL:
4682	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4683	if ( !pLeaf
4684	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4685	{
4686	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4687	return;
4688	}
4689
4690	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4691	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4692	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4693	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4694	break;
4695
4696	/*
4697	* Set the PAE bit in both feature masks.
4698	* Assumes the caller knows what it's doing! (host must support these)
4699	*/
4700	case CPUMCPUIDFEATURE_PAE:
4701	if (!pVM->cpum.s.HostFeatures.fPae)
4702	{
4703	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4704	return;
4705	}
4706
4707	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4708	if (pLeaf)
4709	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4710
4711	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4712	if ( pLeaf
4713	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4714	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4715
4716	pVM->cpum.s.GuestFeatures.fPae = 1;
4717	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4718	break;
4719
4720	/*
4721	* Set the LONG MODE bit in the extended feature mask.
4722	* Assumes the caller knows what it's doing! (host must support these)
4723	*/
4724	case CPUMCPUIDFEATURE_LONG_MODE:
4725	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4726	if ( !pLeaf
4727	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4728	{
4729	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4730	return;
4731	}
4732
4733	/* Valid for both Intel and AMD. */
4734	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4735	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4736	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
4737	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4738	break;
4739
4740	/*
4741	* Set the NX/XD bit in the extended feature mask.
4742	* Assumes the caller knows what it's doing! (host must support these)
4743	*/
4744	case CPUMCPUIDFEATURE_NX:
4745	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4746	if ( !pLeaf
4747	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4748	{
4749	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4750	return;
4751	}
4752
4753	/* Valid for both Intel and AMD. */
4754	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4755	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4756	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4757	break;
4758
4759
4760	/*
4761	* Set the LAHF/SAHF support in 64-bit mode.
4762	* Assumes the caller knows what it's doing! (host must support this)
4763	*/
4764	case CPUMCPUIDFEATURE_LAHF:
4765	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4766	if ( !pLeaf
4767	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4768	{
4769	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4770	return;
4771	}
4772
4773	/* Valid for both Intel and AMD. */
4774	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4775	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4776	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4777	break;
4778
4779	/*
4780	* Set the page attribute table bit. This is alternative page level
4781	* cache control that doesn't much matter when everything is
4782	* virtualized, though it may when passing thru device memory.
4783	*/
4784	case CPUMCPUIDFEATURE_PAT:
4785	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4786	if (pLeaf)
4787	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4788
4789	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4790	if ( pLeaf
4791	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4792	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4793
4794	pVM->cpum.s.GuestFeatures.fPat = 1;
4795	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4796	break;
4797
4798	/*
4799	* Set the RDTSCP support bit.
4800	* Assumes the caller knows what it's doing! (host must support this)
4801	*/
4802	case CPUMCPUIDFEATURE_RDTSCP:
4803	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4804	if ( !pLeaf
4805	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4806	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4807	{
4808	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4809	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4810	return;
4811	}
4812
4813	/* Valid for both Intel and AMD. */
4814	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4815	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4816	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4817	break;
4818
4819	/*
4820	* Set the Hypervisor Present bit in the standard feature mask.
4821	*/
4822	case CPUMCPUIDFEATURE_HVP:
4823	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4824	if (pLeaf)
4825	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4826	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4827	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4828	break;
4829
4830	/*
4831	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4832	* This currently includes the Present bit and MWAITBREAK bit as well.
4833	*/
4834	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4835	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4836	if ( !pLeaf
4837	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4838	{
4839	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4840	return;
4841	}
4842
4843	/* Valid for both Intel and AMD. */
4844	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4845	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4846	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4847	break;
4848
4849	/*
4850	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
4851	* on Intel CPUs, and different on AMDs.
4852	*/
4853	case CPUMCPUIDFEATURE_SPEC_CTRL:
4854	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4855	{
4856	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4857	if ( !pLeaf
4858	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
4859	{
4860	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4861	return;
4862	}
4863
4864	/* The feature can be enabled. Let's see what we can actually do. */
4865	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4866
4867	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4868	if (pVM->cpum.s.HostFeatures.fIbrs)
4869	{
4870	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4871	pVM->cpum.s.GuestFeatures.fIbrs = 1;
4872	if (pVM->cpum.s.HostFeatures.fStibp)
4873	{
4874	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4875	pVM->cpum.s.GuestFeatures.fStibp = 1;
4876	}
4877
4878	/* Make sure we have the speculation control MSR... */
4879	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4880	if (!pMsrRange)
4881	{
4882	static CPUMMSRRANGE const s_SpecCtrl =
4883	{
4884	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
4885	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
4886	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4887	/.szName = / "IA32_SPEC_CTRL"
4888	};
4889	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4890	AssertLogRelRC(rc);
4891	}
4892
4893	/* ... and the predictor command MSR. */
4894	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
4895	if (!pMsrRange)
4896	{
4897	/** @todo incorrect fWrGpMask. */
4898	static CPUMMSRRANGE const s_SpecCtrl =
4899	{
4900	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
4901	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
4902	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4903	/.szName = / "IA32_PRED_CMD"
4904	};
4905	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4906	AssertLogRelRC(rc);
4907	}
4908
4909	}
4910
4911	if (pVM->cpum.s.HostFeatures.fArchCap)
4912	{
4913	/* Install the architectural capabilities MSR. */
4914	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
4915	if (!pMsrRange)
4916	{
4917	static CPUMMSRRANGE const s_ArchCaps =
4918	{
4919	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
4920	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
4921	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
4922	/.szName = / "IA32_ARCH_CAPABILITIES"
4923	};
4924	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
4925	AssertLogRelRC(rc);
4926	}
4927	}
4928
4929	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
4930	}
4931	else if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4932	{
4933	/* The precise details of AMD's implementation are not yet clear. */
4934	}
4935	break;
4936
4937	default:
4938	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4939	break;
4940	}
4941
4942	/** @todo can probably kill this as this API is now init time only... */
4943	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4944	{
4945	PVMCPU pVCpu = &pVM->aCpus[i];
4946	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4947	}
4948	}
4949
4950
4951	/**
4952	* Queries a CPUID feature bit.
4953	*
4954	* @returns boolean for feature presence
4955	* @param pVM The cross context VM structure.
4956	* @param enmFeature The feature to query.
4957	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4958	*/
4959	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4960	{
4961	switch (enmFeature)
4962	{
4963	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4964	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4965	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4966	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4967	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4968	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4969	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4970	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4971	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4972	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4973	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4974	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4975	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
4976
4977	case CPUMCPUIDFEATURE_INVALID:
4978	case CPUMCPUIDFEATURE_32BIT_HACK:
4979	break;
4980	}
4981	AssertFailed();
4982	return false;
4983	}
4984
4985
4986	/**
4987	* Clears a CPUID feature bit.
4988	*
4989	* @param pVM The cross context VM structure.
4990	* @param enmFeature The feature to clear.
4991	*
4992	* @deprecated Probably better to default the feature to disabled and only allow
4993	* setting (enabling) it during construction.
4994	*/
4995	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4996	{
4997	PCPUMCPUIDLEAF pLeaf;
4998	switch (enmFeature)
4999	{
5000	case CPUMCPUIDFEATURE_APIC:
5001	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
5002	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5003	if (pLeaf)
5004	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
5005
5006	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5007	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
5008	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
5009
5010	pVM->cpum.s.GuestFeatures.fApic = 0;
5011	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
5012	break;
5013
5014	case CPUMCPUIDFEATURE_X2APIC:
5015	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
5016	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5017	if (pLeaf)
5018	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
5019	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
5020	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
5021	break;
5022
5023	case CPUMCPUIDFEATURE_PAE:
5024	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5025	if (pLeaf)
5026	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
5027
5028	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5029	if ( pLeaf
5030	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
5031	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
5032
5033	pVM->cpum.s.GuestFeatures.fPae = 0;
5034	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
5035	break;
5036
5037	case CPUMCPUIDFEATURE_PAT:
5038	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5039	if (pLeaf)
5040	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
5041
5042	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5043	if ( pLeaf
5044	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
5045	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
5046
5047	pVM->cpum.s.GuestFeatures.fPat = 0;
5048	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
5049	break;
5050
5051	case CPUMCPUIDFEATURE_LONG_MODE:
5052	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5053	if (pLeaf)
5054	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
5055	pVM->cpum.s.GuestFeatures.fLongMode = 0;
5056	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
5057	break;
5058
5059	case CPUMCPUIDFEATURE_LAHF:
5060	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5061	if (pLeaf)
5062	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
5063	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
5064	break;
5065
5066	case CPUMCPUIDFEATURE_RDTSCP:
5067	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5068	if (pLeaf)
5069	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
5070	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
5071	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
5072	break;
5073
5074	case CPUMCPUIDFEATURE_HVP:
5075	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5076	if (pLeaf)
5077	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
5078	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
5079	break;
5080
5081	case CPUMCPUIDFEATURE_MWAIT_EXTS:
5082	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
5083	if (pLeaf)
5084	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
5085	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
5086	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
5087	break;
5088
5089	case CPUMCPUIDFEATURE_SPEC_CTRL:
5090	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
5091	if (pLeaf)
5092	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
5093	pVM->cpum.s.GuestFeatures.fSpeculationControl = 0;
5094	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
5095	break;
5096
5097	default:
5098	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5099	break;
5100	}
5101
5102	for (VMCPUID i = 0; i < pVM->cCpus; i++)
5103	{
5104	PVMCPU pVCpu = &pVM->aCpus[i];
5105	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5106	}
5107	}
5108
5109
5110
5111	/*
5112	*
5113	*
5114	* Saved state related code.
5115	* Saved state related code.
5116	* Saved state related code.
5117	*
5118	*
5119	*/
5120
5121	/**
5122	* Called both in pass 0 and the final pass.
5123	*
5124	* @param pVM The cross context VM structure.
5125	* @param pSSM The saved state handle.
5126	*/
5127	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
5128	{
5129	/*
5130	* Save all the CPU ID leaves.
5131	*/
5132	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
5133	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5134	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
5135	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5136
5137	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5138
5139	/*
5140	* Save a good portion of the raw CPU IDs as well as they may come in
5141	* handy when validating features for raw mode.
5142	*/
5143	CPUMCPUID aRawStd[16];
5144	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
5145	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5146	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
5147	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
5148
5149	CPUMCPUID aRawExt[32];
5150	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
5151	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5152	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
5153	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
5154	}
5155
5156
5157	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5158	{
5159	uint32_t cCpuIds;
5160	int rc = SSMR3GetU32(pSSM, &cCpuIds);
5161	if (RT_SUCCESS(rc))
5162	{
5163	if (cCpuIds < 64)
5164	{
5165	for (uint32_t i = 0; i < cCpuIds; i++)
5166	{
5167	CPUMCPUID CpuId;
5168	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
5169	if (RT_FAILURE(rc))
5170	break;
5171
5172	CPUMCPUIDLEAF NewLeaf;
5173	NewLeaf.uLeaf = uBase + i;
5174	NewLeaf.uSubLeaf = 0;
5175	NewLeaf.fSubLeafMask = 0;
5176	NewLeaf.uEax = CpuId.uEax;
5177	NewLeaf.uEbx = CpuId.uEbx;
5178	NewLeaf.uEcx = CpuId.uEcx;
5179	NewLeaf.uEdx = CpuId.uEdx;
5180	NewLeaf.fFlags = 0;
5181	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
5182	}
5183	}
5184	else
5185	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5186	}
5187	if (RT_FAILURE(rc))
5188	{
5189	RTMemFree(*ppaLeaves);
5190	*ppaLeaves = NULL;
5191	*pcLeaves = 0;
5192	}
5193	return rc;
5194	}
5195
5196
5197	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5198	{
5199	*ppaLeaves = NULL;
5200	*pcLeaves = 0;
5201
5202	int rc;
5203	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
5204	{
5205	/*
5206	* The new format. Starts by declaring the leave size and count.
5207	*/
5208	uint32_t cbLeaf;
5209	SSMR3GetU32(pSSM, &cbLeaf);
5210	uint32_t cLeaves;
5211	rc = SSMR3GetU32(pSSM, &cLeaves);
5212	if (RT_SUCCESS(rc))
5213	{
5214	if (cbLeaf == sizeof(**ppaLeaves))
5215	{
5216	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
5217	{
5218	/*
5219	* Load the leaves one by one.
5220	*
5221	* The uPrev stuff is a kludge for working around a week worth of bad saved
5222	* states during the CPUID revamp in March 2015. We saved too many leaves
5223	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
5224	* garbage entires at the end of the array when restoring. We also had
5225	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
5226	* this kludge doesn't deal correctly with that, but who cares...
5227	*/
5228	uint32_t uPrev = 0;
5229	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
5230	{
5231	CPUMCPUIDLEAF Leaf;
5232	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5233	if (RT_SUCCESS(rc))
5234	{
5235	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5236	\|\| Leaf.uLeaf >= uPrev)
5237	{
5238	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5239	uPrev = Leaf.uLeaf;
5240	}
5241	else
5242	uPrev = UINT32_MAX;
5243	}
5244	}
5245	}
5246	else
5247	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5248	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5249	}
5250	else
5251	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5252	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5253	}
5254	}
5255	else
5256	{
5257	/*
5258	* The old format with its three inflexible arrays.
5259	*/
5260	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5261	if (RT_SUCCESS(rc))
5262	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5263	if (RT_SUCCESS(rc))
5264	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5265	if (RT_SUCCESS(rc))
5266	{
5267	/*
5268	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5269	*/
5270	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5271	if ( pLeaf
5272	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5273	{
5274	CPUMCPUIDLEAF Leaf;
5275	Leaf.uLeaf = 4;
5276	Leaf.fSubLeafMask = UINT32_MAX;
5277	Leaf.uSubLeaf = 0;
5278	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5279	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5280	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5281	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5282	\| UINT32_C(63); /* system coherency line size - 1 */
5283	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5284	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5285	\| (UINT32_C(1) << 5) /* cache level */
5286	\| UINT32_C(1); /* cache type (data) */
5287	Leaf.fFlags = 0;
5288	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5289	if (RT_SUCCESS(rc))
5290	{
5291	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5292	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5293	}
5294	if (RT_SUCCESS(rc))
5295	{
5296	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5297	Leaf.uEcx = 4095; /* sets - 1 */
5298	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5299	Leaf.uEbx \|= UINT32_C(23) << 22;
5300	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5301	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5302	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5303	Leaf.uEax \|= UINT32_C(2) << 5;
5304	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5305	}
5306	}
5307	}
5308	}
5309	return rc;
5310	}
5311
5312
5313	/**
5314	* Loads the CPU ID leaves saved by pass 0, inner worker.
5315	*
5316	* @returns VBox status code.
5317	* @param pVM The cross context VM structure.
5318	* @param pSSM The saved state handle.
5319	* @param uVersion The format version.
5320	* @param paLeaves Guest CPUID leaves loaded from the state.
5321	* @param cLeaves The number of leaves in @a paLeaves.
5322	* @param pMsrs The guest MSRs.
5323	*/
5324	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
5325	{
5326	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5327
5328	/*
5329	* Continue loading the state into stack buffers.
5330	*/
5331	CPUMCPUID GuestDefCpuId;
5332	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5333	AssertRCReturn(rc, rc);
5334
5335	CPUMCPUID aRawStd[16];
5336	uint32_t cRawStd;
5337	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5338	if (cRawStd > RT_ELEMENTS(aRawStd))
5339	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5340	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5341	AssertRCReturn(rc, rc);
5342	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5343	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5344
5345	CPUMCPUID aRawExt[32];
5346	uint32_t cRawExt;
5347	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5348	if (cRawExt > RT_ELEMENTS(aRawExt))
5349	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5350	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5351	AssertRCReturn(rc, rc);
5352	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5353	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5354
5355	/*
5356	* Get the raw CPU IDs for the current host.
5357	*/
5358	CPUMCPUID aHostRawStd[16];
5359	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5360	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5361
5362	CPUMCPUID aHostRawExt[32];
5363	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5364	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5365	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5366
5367	/*
5368	* Get the host and guest overrides so we don't reject the state because
5369	* some feature was enabled thru these interfaces.
5370	* Note! We currently only need the feature leaves, so skip rest.
5371	*/
5372	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5373	CPUMCPUID aHostOverrideStd[2];
5374	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5375	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5376
5377	CPUMCPUID aHostOverrideExt[2];
5378	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5379	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5380
5381	/*
5382	* This can be skipped.
5383	*/
5384	bool fStrictCpuIdChecks;
5385	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5386
5387	/*
5388	* Define a bunch of macros for simplifying the santizing/checking code below.
5389	*/
5390	/* Generic expression + failure message. */
5391	#define CPUID_CHECK_RET(expr, fmt) \
5392	do { \
5393	if (!(expr)) \
5394	{ \
5395	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5396	if (fStrictCpuIdChecks) \
5397	{ \
5398	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5399	RTStrFree(pszMsg); \
5400	return rcCpuid; \
5401	} \
5402	LogRel(("CPUM: %s\n", pszMsg)); \
5403	RTStrFree(pszMsg); \
5404	} \
5405	} while (0)
5406	#define CPUID_CHECK_WRN(expr, fmt) \
5407	do { \
5408	if (!(expr)) \
5409	LogRel(fmt); \
5410	} while (0)
5411
5412	/* For comparing two values and bitch if they differs. */
5413	#define CPUID_CHECK2_RET(what, host, saved) \
5414	do { \
5415	if ((host) != (saved)) \
5416	{ \
5417	if (fStrictCpuIdChecks) \
5418	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5419	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5420	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5421	} \
5422	} while (0)
5423	#define CPUID_CHECK2_WRN(what, host, saved) \
5424	do { \
5425	if ((host) != (saved)) \
5426	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5427	} while (0)
5428
5429	/* For checking raw cpu features (raw mode). */
5430	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5431	do { \
5432	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5433	{ \
5434	if (fStrictCpuIdChecks) \
5435	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5436	N_(#bit " mismatch: host=%d saved=%d"), \
5437	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5438	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5439	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5440	} \
5441	} while (0)
5442	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5443	do { \
5444	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5445	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5446	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5447	} while (0)
5448	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5449
5450	/* For checking guest features. */
5451	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5452	do { \
5453	if ( (aGuestCpuId##set [1].reg & bit) \
5454	&& !(aHostRaw##set [1].reg & bit) \
5455	&& !(aHostOverride##set [1].reg & bit) \
5456	) \
5457	{ \
5458	if (fStrictCpuIdChecks) \
5459	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5460	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5461	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5462	} \
5463	} while (0)
5464	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5465	do { \
5466	if ( (aGuestCpuId##set [1].reg & bit) \
5467	&& !(aHostRaw##set [1].reg & bit) \
5468	&& !(aHostOverride##set [1].reg & bit) \
5469	) \
5470	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5471	} while (0)
5472	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5473	do { \
5474	if ( (aGuestCpuId##set [1].reg & bit) \
5475	&& !(aHostRaw##set [1].reg & bit) \
5476	&& !(aHostOverride##set [1].reg & bit) \
5477	) \
5478	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5479	} while (0)
5480	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5481
5482	/* For checking guest features if AMD guest CPU. */
5483	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5484	do { \
5485	if ( (aGuestCpuId##set [1].reg & bit) \
5486	&& fGuestAmd \
5487	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5488	&& !(aHostOverride##set [1].reg & bit) \
5489	) \
5490	{ \
5491	if (fStrictCpuIdChecks) \
5492	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5493	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5494	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5495	} \
5496	} while (0)
5497	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5498	do { \
5499	if ( (aGuestCpuId##set [1].reg & bit) \
5500	&& fGuestAmd \
5501	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5502	&& !(aHostOverride##set [1].reg & bit) \
5503	) \
5504	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5505	} while (0)
5506	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5507	do { \
5508	if ( (aGuestCpuId##set [1].reg & bit) \
5509	&& fGuestAmd \
5510	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5511	&& !(aHostOverride##set [1].reg & bit) \
5512	) \
5513	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5514	} while (0)
5515	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5516
5517	/* For checking AMD features which have a corresponding bit in the standard
5518	range. (Intel defines very few bits in the extended feature sets.) */
5519	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5520	do { \
5521	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5522	&& !(fHostAmd \
5523	? aHostRawExt[1].reg & (ExtBit) \
5524	: aHostRawStd[1].reg & (StdBit)) \
5525	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5526	) \
5527	{ \
5528	if (fStrictCpuIdChecks) \
5529	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5530	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5531	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5532	} \
5533	} while (0)
5534	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5535	do { \
5536	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5537	&& !(fHostAmd \
5538	? aHostRawExt[1].reg & (ExtBit) \
5539	: aHostRawStd[1].reg & (StdBit)) \
5540	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5541	) \
5542	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5543	} while (0)
5544	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5545	do { \
5546	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5547	&& !(fHostAmd \
5548	? aHostRawExt[1].reg & (ExtBit) \
5549	: aHostRawStd[1].reg & (StdBit)) \
5550	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5551	) \
5552	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5553	} while (0)
5554	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5555
5556
5557	/*
5558	* Verify that we can support the features already exposed to the guest on
5559	* this host.
5560	*
5561	* Most of the features we're emulating requires intercepting instruction
5562	* and doing it the slow way, so there is no need to warn when they aren't
5563	* present in the host CPU. Thus we use IGN instead of EMU on these.
5564	*
5565	* Trailing comments:
5566	* "EMU" - Possible to emulate, could be lots of work and very slow.
5567	* "EMU?" - Can this be emulated?
5568	*/
5569	CPUMCPUID aGuestCpuIdStd[2];
5570	RT_ZERO(aGuestCpuIdStd);
5571	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5572
5573	/* CPUID(1).ecx */
5574	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5575	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5576	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5577	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5578	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5579	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5580	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5581	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5582	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5583	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5584	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5585	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5586	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5587	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5588	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5589	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5590	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5591	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5592	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5593	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5594	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5595	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5596	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5597	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5598	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5599	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5600	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5601	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5602	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5603	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5604	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5605	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5606
5607	/* CPUID(1).edx */
5608	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5609	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5610	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5611	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5612	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5613	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5614	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5615	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5616	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5617	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5618	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5619	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5620	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5621	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5622	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5623	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5624	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5625	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5626	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5627	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5628	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5629	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5630	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5631	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5632	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5633	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5634	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5635	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5636	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5637	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5638	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5639	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5640
5641	/* CPUID(0x80000000). */
5642	CPUMCPUID aGuestCpuIdExt[2];
5643	RT_ZERO(aGuestCpuIdExt);
5644	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5645	{
5646	/** @todo deal with no 0x80000001 on the host. */
5647	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5648	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5649
5650	/* CPUID(0x80000001).ecx */
5651	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5652	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5653	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5654	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5655	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5656	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5657	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5658	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5659	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5660	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5661	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5662	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5663	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5664	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5665	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5666	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5667	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5668	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5669	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5670	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5671	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5672	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5673	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5674	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5675	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5676	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5677	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5678	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5679	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5680	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5681	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5682	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5683
5684	/* CPUID(0x80000001).edx */
5685	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5686	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5687	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5688	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5689	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5690	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5691	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5692	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5693	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5694	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5695	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5696	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5697	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5698	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5699	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5700	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5701	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5702	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5703	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5704	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5705	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5706	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5707	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5708	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5709	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5710	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5711	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5712	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5713	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5714	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5715	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5716	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5717	}
5718
5719	/** @todo check leaf 7 */
5720
5721	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5722	* ECX=0: EAX - Valid bits in XCR0[31:0].
5723	* EBX - Maximum state size as per current XCR0 value.
5724	* ECX - Maximum state size for all supported features.
5725	* EDX - Valid bits in XCR0[63:32].
5726	* ECX=1: EAX - Various X-features.
5727	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5728	* ECX - Valid bits in IA32_XSS[31:0].
5729	* EDX - Valid bits in IA32_XSS[63:32].
5730	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5731	* if the bit invalid all four registers are set to zero.
5732	* EAX - The state size for this feature.
5733	* EBX - The state byte offset of this feature.
5734	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5735	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5736	*/
5737	uint64_t fGuestXcr0Mask = 0;
5738	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5739	if ( pCurLeaf
5740	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5741	&& ( pCurLeaf->uEax
5742	\|\| pCurLeaf->uEbx
5743	\|\| pCurLeaf->uEcx
5744	\|\| pCurLeaf->uEdx) )
5745	{
5746	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5747	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5748	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5749	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5750	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5751	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5752	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5753	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5754
5755	/* We don't support any additional features yet. */
5756	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5757	if (pCurLeaf && pCurLeaf->uEax)
5758	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5759	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5760	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5761	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5762	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5763	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5764
5765
5766	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5767	{
5768	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5769	if (pCurLeaf)
5770	{
5771	/* If advertised, the state component offset and size must match the one used by host. */
5772	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5773	{
5774	CPUMCPUID RawHost;
5775	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5776	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5777	if ( RawHost.uEbx != pCurLeaf->uEbx
5778	\|\| RawHost.uEax != pCurLeaf->uEax)
5779	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5780	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5781	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5782	}
5783	}
5784	}
5785	}
5786	/* Clear leaf 0xd just in case we're loading an old state... */
5787	else if (pCurLeaf)
5788	{
5789	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5790	{
5791	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5792	if (pCurLeaf)
5793	{
5794	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5795	\|\| ( pCurLeaf->uEax == 0
5796	&& pCurLeaf->uEbx == 0
5797	&& pCurLeaf->uEcx == 0
5798	&& pCurLeaf->uEdx == 0),
5799	("uVersion=%#x; %#x %#x %#x %#x\n",
5800	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5801	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5802	}
5803	}
5804	}
5805
5806	/* Update the fXStateGuestMask value for the VM. */
5807	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5808	{
5809	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5810	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5811	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5812	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5813	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5814	}
5815
5816	#undef CPUID_CHECK_RET
5817	#undef CPUID_CHECK_WRN
5818	#undef CPUID_CHECK2_RET
5819	#undef CPUID_CHECK2_WRN
5820	#undef CPUID_RAW_FEATURE_RET
5821	#undef CPUID_RAW_FEATURE_WRN
5822	#undef CPUID_RAW_FEATURE_IGN
5823	#undef CPUID_GST_FEATURE_RET
5824	#undef CPUID_GST_FEATURE_WRN
5825	#undef CPUID_GST_FEATURE_EMU
5826	#undef CPUID_GST_FEATURE_IGN
5827	#undef CPUID_GST_FEATURE2_RET
5828	#undef CPUID_GST_FEATURE2_WRN
5829	#undef CPUID_GST_FEATURE2_EMU
5830	#undef CPUID_GST_FEATURE2_IGN
5831	#undef CPUID_GST_AMD_FEATURE_RET
5832	#undef CPUID_GST_AMD_FEATURE_WRN
5833	#undef CPUID_GST_AMD_FEATURE_EMU
5834	#undef CPUID_GST_AMD_FEATURE_IGN
5835
5836	/*
5837	* We're good, commit the CPU ID leaves.
5838	*/
5839	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5840	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5841	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5842	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5843	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
5844	AssertLogRelRCReturn(rc, rc);
5845
5846	return VINF_SUCCESS;
5847	}
5848
5849
5850	/**
5851	* Loads the CPU ID leaves saved by pass 0.
5852	*
5853	* @returns VBox status code.
5854	* @param pVM The cross context VM structure.
5855	* @param pSSM The saved state handle.
5856	* @param uVersion The format version.
5857	* @param pMsrs The guest MSRs.
5858	*/
5859	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
5860	{
5861	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5862
5863	/*
5864	* Load the CPUID leaves array first and call worker to do the rest, just so
5865	* we can free the memory when we need to without ending up in column 1000.
5866	*/
5867	PCPUMCPUIDLEAF paLeaves;
5868	uint32_t cLeaves;
5869	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5870	AssertRC(rc);
5871	if (RT_SUCCESS(rc))
5872	{
5873	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
5874	RTMemFree(paLeaves);
5875	}
5876	return rc;
5877	}
5878
5879
5880
5881	/**
5882	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5883	*
5884	* @returns VBox status code.
5885	* @param pVM The cross context VM structure.
5886	* @param pSSM The saved state handle.
5887	* @param uVersion The format version.
5888	*/
5889	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5890	{
5891	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5892
5893	/*
5894	* Restore the CPUID leaves.
5895	*
5896	* Note that we support restoring less than the current amount of standard
5897	* leaves because we've been allowed more is newer version of VBox.
5898	*/
5899	uint32_t cElements;
5900	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5901	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5902	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5903	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5904
5905	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5906	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5907	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5908	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5909
5910	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5911	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5912	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5913	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5914
5915	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5916
5917	/*
5918	* Check that the basic cpuid id information is unchanged.
5919	*/
5920	/** @todo we should check the 64 bits capabilities too! */
5921	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5922	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5923	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5924	uint32_t au32CpuIdSaved[8];
5925	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5926	if (RT_SUCCESS(rc))
5927	{
5928	/* Ignore CPU stepping. */
5929	au32CpuId[4] &= 0xfffffff0;
5930	au32CpuIdSaved[4] &= 0xfffffff0;
5931
5932	/* Ignore APIC ID (AMD specs). */
5933	au32CpuId[5] &= ~0xff000000;
5934	au32CpuIdSaved[5] &= ~0xff000000;
5935
5936	/* Ignore the number of Logical CPUs (AMD specs). */
5937	au32CpuId[5] &= ~0x00ff0000;
5938	au32CpuIdSaved[5] &= ~0x00ff0000;
5939
5940	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5941	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5942	\| X86_CPUID_FEATURE_ECX_VMX
5943	\| X86_CPUID_FEATURE_ECX_SMX
5944	\| X86_CPUID_FEATURE_ECX_EST
5945	\| X86_CPUID_FEATURE_ECX_TM2
5946	\| X86_CPUID_FEATURE_ECX_CNTXID
5947	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5948	\| X86_CPUID_FEATURE_ECX_PDCM
5949	\| X86_CPUID_FEATURE_ECX_DCA
5950	\| X86_CPUID_FEATURE_ECX_X2APIC
5951	);
5952	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5953	\| X86_CPUID_FEATURE_ECX_VMX
5954	\| X86_CPUID_FEATURE_ECX_SMX
5955	\| X86_CPUID_FEATURE_ECX_EST
5956	\| X86_CPUID_FEATURE_ECX_TM2
5957	\| X86_CPUID_FEATURE_ECX_CNTXID
5958	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5959	\| X86_CPUID_FEATURE_ECX_PDCM
5960	\| X86_CPUID_FEATURE_ECX_DCA
5961	\| X86_CPUID_FEATURE_ECX_X2APIC
5962	);
5963
5964	/* Make sure we don't forget to update the masks when enabling
5965	* features in the future.
5966	*/
5967	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5968	( X86_CPUID_FEATURE_ECX_DTES64
5969	\| X86_CPUID_FEATURE_ECX_VMX
5970	\| X86_CPUID_FEATURE_ECX_SMX
5971	\| X86_CPUID_FEATURE_ECX_EST
5972	\| X86_CPUID_FEATURE_ECX_TM2
5973	\| X86_CPUID_FEATURE_ECX_CNTXID
5974	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5975	\| X86_CPUID_FEATURE_ECX_PDCM
5976	\| X86_CPUID_FEATURE_ECX_DCA
5977	\| X86_CPUID_FEATURE_ECX_X2APIC
5978	)));
5979	/* do the compare */
5980	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5981	{
5982	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5983	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5984	"Saved=%.*Rhxs\n"
5985	"Real =%.*Rhxs\n",
5986	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5987	sizeof(au32CpuId), au32CpuId));
5988	else
5989	{
5990	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5991	"Saved=%.*Rhxs\n"
5992	"Real =%.*Rhxs\n",
5993	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5994	sizeof(au32CpuId), au32CpuId));
5995	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5996	}
5997	}
5998	}
5999
6000	return rc;
6001	}
6002
6003
6004
6005	/*
6006	*
6007	*
6008	* CPUID Info Handler.
6009	* CPUID Info Handler.
6010	* CPUID Info Handler.
6011	*
6012	*
6013	*/
6014
6015
6016
6017	/**
6018	* Get L1 cache / TLS associativity.
6019	*/
6020	static const char getCacheAss(unsigned u, char pszBuf)
6021	{
6022	if (u == 0)
6023	return "res0 ";
6024	if (u == 1)
6025	return "direct";
6026	if (u == 255)
6027	return "fully";
6028	if (u >= 256)
6029	return "???";
6030
6031	RTStrPrintf(pszBuf, 16, "%d way", u);
6032	return pszBuf;
6033	}
6034
6035
6036	/**
6037	* Get L2 cache associativity.
6038	*/
6039	const char *getL2CacheAss(unsigned u)
6040	{
6041	switch (u)
6042	{
6043	case 0: return "off ";
6044	case 1: return "direct";
6045	case 2: return "2 way ";
6046	case 3: return "res3 ";
6047	case 4: return "4 way ";
6048	case 5: return "res5 ";
6049	case 6: return "8 way ";
6050	case 7: return "res7 ";
6051	case 8: return "16 way";
6052	case 9: return "res9 ";
6053	case 10: return "res10 ";
6054	case 11: return "res11 ";
6055	case 12: return "res12 ";
6056	case 13: return "res13 ";
6057	case 14: return "res14 ";
6058	case 15: return "fully ";
6059	default: return "????";
6060	}
6061	}
6062
6063
6064	/** CPUID(1).EDX field descriptions. */
6065	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6066	{
6067	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6068	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6069	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6070	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6071	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6072	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6073	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6074	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6075	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6076	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6077	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6078	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6079	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6080	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6081	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6082	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6083	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6084	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6085	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6086	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6087	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6088	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6089	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6090	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6091	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6092	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6093	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6094	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6095	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6096	DBGFREGSUBFIELD_TERMINATOR()
6097	};
6098
6099	/** CPUID(1).ECX field descriptions. */
6100	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6101	{
6102	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6103	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6104	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6105	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6106	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6107	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6108	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6109	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6110	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6111	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6112	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6113	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6114	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6115	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6116	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6117	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6118	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6119	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6120	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6121	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6122	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6123	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6124	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6125	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6126	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6127	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6128	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6129	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6130	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6131	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6132	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6133	DBGFREGSUBFIELD_TERMINATOR()
6134	};
6135
6136	/** CPUID(7,0).EBX field descriptions. */
6137	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6138	{
6139	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6140	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6141	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6142	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6143	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6144	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6145	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6146	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6147	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6148	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6149	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6150	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6151	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6152	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6153	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6154	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6155	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6156	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6157	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6158	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6159	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6160	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6161	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6162	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6163	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6164	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6165	DBGFREGSUBFIELD_TERMINATOR()
6166	};
6167
6168	/** CPUID(7,0).ECX field descriptions. */
6169	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6170	{
6171	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6172	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6173	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6174	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6175	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6176	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6177	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6178	DBGFREGSUBFIELD_TERMINATOR()
6179	};
6180
6181	/** CPUID(7,0).EDX field descriptions. */
6182	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6183	{
6184	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
6185	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6186	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6187	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
6188	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6189	DBGFREGSUBFIELD_TERMINATOR()
6190	};
6191
6192
6193	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6194	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6195	{
6196	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6197	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6198	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6199	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6200	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6201	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6202	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6203	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6204	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6205	DBGFREGSUBFIELD_TERMINATOR()
6206	};
6207
6208	/** CPUID(13,1).EAX field descriptions. */
6209	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6210	{
6211	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6212	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6213	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6214	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6215	DBGFREGSUBFIELD_TERMINATOR()
6216	};
6217
6218
6219	/** CPUID(0x80000001,0).EDX field descriptions. */
6220	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6221	{
6222	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6223	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6224	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6225	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6226	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6227	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6228	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6229	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6230	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6231	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6232	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6233	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6234	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6235	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6236	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6237	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6238	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6239	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6240	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6241	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6242	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6243	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6244	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6245	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6246	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6247	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6248	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6249	DBGFREGSUBFIELD_TERMINATOR()
6250	};
6251
6252	/** CPUID(0x80000001,0).ECX field descriptions. */
6253	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6254	{
6255	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6256	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6257	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6258	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6259	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6260	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6261	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6262	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6263	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6264	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6265	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6266	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6267	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6268	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6269	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6270	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6271	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6272	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6273	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6274	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6275	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6276	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6277	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6278	DBGFREGSUBFIELD_TERMINATOR()
6279	};
6280
6281	/** CPUID(0x8000000a,0).EDX field descriptions. */
6282	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6283	{
6284	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6285	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6286	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6287	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6288	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6289	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6290	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6291	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6292	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6293	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6294	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6295	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6296	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6297	DBGFREGSUBFIELD_TERMINATOR()
6298	};
6299
6300
6301	/** CPUID(0x80000007,0).EDX field descriptions. */
6302	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6303	{
6304	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6305	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6306	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6307	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6308	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6309	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6310	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6311	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6312	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6313	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6314	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6315	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6316	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6317	DBGFREGSUBFIELD_TERMINATOR()
6318	};
6319
6320	/** CPUID(0x80000008,0).EBX field descriptions. */
6321	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6322	{
6323	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6324	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6325	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6326	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6327	DBGFREGSUBFIELD_TERMINATOR()
6328	};
6329
6330
6331	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6332	const char *pszLeadIn, uint32_t cchWidth)
6333	{
6334	if (pszLeadIn)
6335	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6336
6337	for (uint32_t iBit = 0; iBit < 32; iBit++)
6338	if (RT_BIT_32(iBit) & uVal)
6339	{
6340	while ( pDesc->pszName != NULL
6341	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6342	pDesc++;
6343	if ( pDesc->pszName != NULL
6344	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6345	{
6346	if (pDesc->cBits == 1)
6347	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6348	else
6349	{
6350	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6351	if (pDesc->cBits < 32)
6352	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6353	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6354	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6355	}
6356	}
6357	else
6358	pHlp->pfnPrintf(pHlp, " %u", iBit);
6359	}
6360	if (pszLeadIn)
6361	pHlp->pfnPrintf(pHlp, "\n");
6362	}
6363
6364
6365	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6366	const char *pszLeadIn, uint32_t cchWidth)
6367	{
6368	if (pszLeadIn)
6369	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6370
6371	for (uint32_t iBit = 0; iBit < 64; iBit++)
6372	if (RT_BIT_64(iBit) & uVal)
6373	{
6374	while ( pDesc->pszName != NULL
6375	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6376	pDesc++;
6377	if ( pDesc->pszName != NULL
6378	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6379	{
6380	if (pDesc->cBits == 1)
6381	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6382	else
6383	{
6384	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6385	if (pDesc->cBits < 64)
6386	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6387	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6388	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6389	}
6390	}
6391	else
6392	pHlp->pfnPrintf(pHlp, " %u", iBit);
6393	}
6394	if (pszLeadIn)
6395	pHlp->pfnPrintf(pHlp, "\n");
6396	}
6397
6398
6399	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6400	const char *pszLeadIn, uint32_t cchWidth)
6401	{
6402	if (!uVal)
6403	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6404	else
6405	{
6406	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6407	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6408	pHlp->pfnPrintf(pHlp, " )\n");
6409	}
6410	}
6411
6412
6413	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6414	uint32_t cchWidth)
6415	{
6416	uint32_t uCombined = uVal1 \| uVal2;
6417	for (uint32_t iBit = 0; iBit < 32; iBit++)
6418	if ( (RT_BIT_32(iBit) & uCombined)
6419	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6420	{
6421	while ( pDesc->pszName != NULL
6422	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6423	pDesc++;
6424
6425	if ( pDesc->pszName != NULL
6426	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6427	{
6428	size_t cchMnemonic = strlen(pDesc->pszName);
6429	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6430	size_t cchDesc = strlen(pszDesc);
6431	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6432	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6433	if (pDesc->cBits < 32)
6434	{
6435	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6436	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6437	}
6438
6439	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6440	pDesc->pszName, pszDesc,
6441	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6442	uFieldValue1, uFieldValue2);
6443
6444	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6445	pDesc++;
6446	}
6447	else
6448	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6449	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6450	}
6451	}
6452
6453
6454	/**
6455	* Produces a detailed summary of standard leaf 0x00000001.
6456	*
6457	* @param pHlp The info helper functions.
6458	* @param pCurLeaf The 0x00000001 leaf.
6459	* @param fVerbose Whether to be very verbose or not.
6460	* @param fIntel Set if intel CPU.
6461	*/
6462	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6463	{
6464	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6465	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6466	uint32_t uEAX = pCurLeaf->uEax;
6467	uint32_t uEBX = pCurLeaf->uEbx;
6468
6469	pHlp->pfnPrintf(pHlp,
6470	"%36s %2d \tExtended: %d \tEffective: %d\n"
6471	"%36s %2d \tExtended: %d \tEffective: %d\n"
6472	"%36s %d\n"
6473	"%36s %d (%s)\n"
6474	"%36s %#04x\n"
6475	"%36s %d\n"
6476	"%36s %d\n"
6477	"%36s %#04x\n"
6478	,
6479	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6480	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6481	"Stepping:", ASMGetCpuStepping(uEAX),
6482	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6483	"APIC ID:", (uEBX >> 24) & 0xff,
6484	"Logical CPUs:",(uEBX >> 16) & 0xff,
6485	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6486	"Brand ID:", (uEBX >> 0) & 0xff);
6487	if (fVerbose)
6488	{
6489	CPUMCPUID Host;
6490	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6491	pHlp->pfnPrintf(pHlp, "Features\n");
6492	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6493	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6494	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6495	}
6496	else
6497	{
6498	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6499	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6500	}
6501	}
6502
6503
6504	/**
6505	* Produces a detailed summary of standard leaf 0x00000007.
6506	*
6507	* @param pHlp The info helper functions.
6508	* @param paLeaves The CPUID leaves array.
6509	* @param cLeaves The number of leaves in the array.
6510	* @param pCurLeaf The first 0x00000007 leaf.
6511	* @param fVerbose Whether to be very verbose or not.
6512	*/
6513	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6514	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6515	{
6516	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6517	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6518	for (;;)
6519	{
6520	CPUMCPUID Host;
6521	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6522
6523	switch (pCurLeaf->uSubLeaf)
6524	{
6525	case 0:
6526	if (fVerbose)
6527	{
6528	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6529	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6530	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6531	if (pCurLeaf->uEdx \|\| Host.uEdx)
6532	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6533	}
6534	else
6535	{
6536	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6537	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6538	if (pCurLeaf->uEdx)
6539	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6540	}
6541	break;
6542
6543	default:
6544	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6545	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6546	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6547	break;
6548
6549	}
6550
6551	/* advance. */
6552	pCurLeaf++;
6553	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6554	\|\| pCurLeaf->uLeaf != 0x7)
6555	break;
6556	}
6557	}
6558
6559
6560	/**
6561	* Produces a detailed summary of standard leaf 0x0000000d.
6562	*
6563	* @param pHlp The info helper functions.
6564	* @param paLeaves The CPUID leaves array.
6565	* @param cLeaves The number of leaves in the array.
6566	* @param pCurLeaf The first 0x00000007 leaf.
6567	* @param fVerbose Whether to be very verbose or not.
6568	*/
6569	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6570	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6571	{
6572	RT_NOREF_PV(fVerbose);
6573	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6574	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6575	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6576	{
6577	CPUMCPUID Host;
6578	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6579
6580	switch (uSubLeaf)
6581	{
6582	case 0:
6583	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6584	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6585	pCurLeaf->uEbx, pCurLeaf->uEcx);
6586	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6587
6588	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6589	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6590	"Valid XCR0 bits, guest:", 42);
6591	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6592	"Valid XCR0 bits, host:", 42);
6593	break;
6594
6595	case 1:
6596	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6597	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6598	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6599
6600	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6601	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6602	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6603
6604	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6605	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6606	" Valid IA32_XSS bits, guest:", 42);
6607	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6608	" Valid IA32_XSS bits, host:", 42);
6609	break;
6610
6611	default:
6612	if ( pCurLeaf
6613	&& pCurLeaf->uSubLeaf == uSubLeaf
6614	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6615	{
6616	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6617	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6618	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6619	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6620	if (pCurLeaf->uEdx)
6621	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6622	pHlp->pfnPrintf(pHlp, " --");
6623	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6624	pHlp->pfnPrintf(pHlp, "\n");
6625	}
6626	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6627	{
6628	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6629	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6630	if (Host.uEcx & ~RT_BIT_32(0))
6631	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6632	if (Host.uEdx)
6633	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6634	pHlp->pfnPrintf(pHlp, " --");
6635	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6636	pHlp->pfnPrintf(pHlp, "\n");
6637	}
6638	break;
6639
6640	}
6641
6642	/* advance. */
6643	if (pCurLeaf)
6644	{
6645	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6646	&& pCurLeaf->uSubLeaf <= uSubLeaf
6647	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6648	pCurLeaf++;
6649	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6650	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6651	pCurLeaf = NULL;
6652	}
6653	}
6654	}
6655
6656
6657	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6658	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6659	{
6660	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6661	&& pCurLeaf->uLeaf <= uUpToLeaf)
6662	{
6663	pHlp->pfnPrintf(pHlp,
6664	" %s\n"
6665	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6666	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6667	&& pCurLeaf->uLeaf <= uUpToLeaf)
6668	{
6669	CPUMCPUID Host;
6670	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6671	pHlp->pfnPrintf(pHlp,
6672	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6673	"Hst: %08x %08x %08x %08x\n",
6674	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6675	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6676	pCurLeaf++;
6677	}
6678	}
6679
6680	return pCurLeaf;
6681	}
6682
6683
6684	/**
6685	* Display the guest CpuId leaves.
6686	*
6687	* @param pVM The cross context VM structure.
6688	* @param pHlp The info helper functions.
6689	* @param pszArgs "terse", "default" or "verbose".
6690	*/
6691	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6692	{
6693	/*
6694	* Parse the argument.
6695	*/
6696	unsigned iVerbosity = 1;
6697	if (pszArgs)
6698	{
6699	pszArgs = RTStrStripL(pszArgs);
6700	if (!strcmp(pszArgs, "terse"))
6701	iVerbosity--;
6702	else if (!strcmp(pszArgs, "verbose"))
6703	iVerbosity++;
6704	}
6705
6706	uint32_t uLeaf;
6707	CPUMCPUID Host;
6708	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6709	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6710	PCCPUMCPUIDLEAF pCurLeaf;
6711	PCCPUMCPUIDLEAF pNextLeaf;
6712	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6713	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6714	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6715
6716	/*
6717	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6718	*/
6719	uint32_t cHstMax = ASMCpuId_EAX(0);
6720	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6721	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6722	pHlp->pfnPrintf(pHlp,
6723	" Raw Standard CPUID Leaves\n"
6724	" Leaf/sub-leaf eax ebx ecx edx\n");
6725	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6726	{
6727	uint32_t cMaxSubLeaves = 1;
6728	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6729	cMaxSubLeaves = 16;
6730	else if (uLeaf == 0xd)
6731	cMaxSubLeaves = 128;
6732
6733	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6734	{
6735	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6736	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6737	&& pCurLeaf->uLeaf == uLeaf
6738	&& pCurLeaf->uSubLeaf == uSubLeaf)
6739	{
6740	pHlp->pfnPrintf(pHlp,
6741	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6742	"Hst: %08x %08x %08x %08x\n",
6743	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6744	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6745	pCurLeaf++;
6746	}
6747	else if ( uLeaf != 0xd
6748	\|\| uSubLeaf <= 1
6749	\|\| Host.uEbx != 0 )
6750	pHlp->pfnPrintf(pHlp,
6751	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6752	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6753
6754	/* Done? */
6755	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6756	\|\| pCurLeaf->uLeaf != uLeaf)
6757	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6758	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6759	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6760	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6761	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6762	)
6763	)
6764	break;
6765	}
6766	}
6767	pNextLeaf = pCurLeaf;
6768
6769	/*
6770	* If verbose, decode it.
6771	*/
6772	if (iVerbosity && paLeaves[0].uLeaf == 0)
6773	pHlp->pfnPrintf(pHlp,
6774	"%36s %.04s%.04s%.04s\n"
6775	"%36s 0x00000000-%#010x\n"
6776	,
6777	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6778	"Supports:", paLeaves[0].uEax);
6779
6780	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6781	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6782
6783	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6784	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6785
6786	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6787	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6788
6789	pCurLeaf = pNextLeaf;
6790
6791	/*
6792	* Hypervisor leaves.
6793	*
6794	* Unlike most of the other leaves reported, the guest hypervisor leaves
6795	* aren't a subset of the host CPUID bits.
6796	*/
6797	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6798
6799	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6800	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6801	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6802	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6803	cMax = RT_MAX(cHstMax, cGstMax);
6804	if (cMax >= UINT32_C(0x40000000))
6805	{
6806	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6807
6808	/** @todo dump these in more detail. */
6809
6810	pCurLeaf = pNextLeaf;
6811	}
6812
6813
6814	/*
6815	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6816	* Implemented after AMD specs.
6817	*/
6818	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6819
6820	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6821	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6822	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6823	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6824	cMax = RT_MAX(cHstMax, cGstMax);
6825	if (cMax >= UINT32_C(0x80000000))
6826	{
6827
6828	pHlp->pfnPrintf(pHlp,
6829	" Raw Extended CPUID Leaves\n"
6830	" Leaf/sub-leaf eax ebx ecx edx\n");
6831	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6832	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6833	{
6834	uint32_t cMaxSubLeaves = 1;
6835	if (uLeaf == UINT32_C(0x8000001d))
6836	cMaxSubLeaves = 16;
6837
6838	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6839	{
6840	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6841	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6842	&& pCurLeaf->uLeaf == uLeaf
6843	&& pCurLeaf->uSubLeaf == uSubLeaf)
6844	{
6845	pHlp->pfnPrintf(pHlp,
6846	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6847	"Hst: %08x %08x %08x %08x\n",
6848	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6849	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6850	pCurLeaf++;
6851	}
6852	else if ( uLeaf != 0xd
6853	\|\| uSubLeaf <= 1
6854	\|\| Host.uEbx != 0 )
6855	pHlp->pfnPrintf(pHlp,
6856	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6857	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6858
6859	/* Done? */
6860	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6861	\|\| pCurLeaf->uLeaf != uLeaf)
6862	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6863	break;
6864	}
6865	}
6866	pNextLeaf = pCurLeaf;
6867
6868	/*
6869	* Understandable output
6870	*/
6871	if (iVerbosity)
6872	pHlp->pfnPrintf(pHlp,
6873	"Ext Name: %.4s%.4s%.4s\n"
6874	"Ext Supports: 0x80000000-%#010x\n",
6875	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6876
6877	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6878	if (iVerbosity && pCurLeaf)
6879	{
6880	uint32_t uEAX = pCurLeaf->uEax;
6881	pHlp->pfnPrintf(pHlp,
6882	"Family: %d \tExtended: %d \tEffective: %d\n"
6883	"Model: %d \tExtended: %d \tEffective: %d\n"
6884	"Stepping: %d\n"
6885	"Brand ID: %#05x\n",
6886	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6887	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6888	ASMGetCpuStepping(uEAX),
6889	pCurLeaf->uEbx & 0xfff);
6890
6891	if (iVerbosity == 1)
6892	{
6893	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6894	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6895	}
6896	else
6897	{
6898	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6899	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6900	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6901	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6902	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6903	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
6904	{
6905	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
6906	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6907	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
6908	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
6909	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
6910	}
6911	}
6912	}
6913
6914	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6915	{
6916	char szString[443+1] = {0};
6917	uint32_t pu32 = (uint32_t )szString;
6918	*pu32++ = pCurLeaf->uEax;
6919	*pu32++ = pCurLeaf->uEbx;
6920	*pu32++ = pCurLeaf->uEcx;
6921	*pu32++ = pCurLeaf->uEdx;
6922	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6923	if (pCurLeaf)
6924	{
6925	*pu32++ = pCurLeaf->uEax;
6926	*pu32++ = pCurLeaf->uEbx;
6927	*pu32++ = pCurLeaf->uEcx;
6928	*pu32++ = pCurLeaf->uEdx;
6929	}
6930	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6931	if (pCurLeaf)
6932	{
6933	*pu32++ = pCurLeaf->uEax;
6934	*pu32++ = pCurLeaf->uEbx;
6935	*pu32++ = pCurLeaf->uEcx;
6936	*pu32++ = pCurLeaf->uEdx;
6937	}
6938	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6939	}
6940
6941	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6942	{
6943	uint32_t uEAX = pCurLeaf->uEax;
6944	uint32_t uEBX = pCurLeaf->uEbx;
6945	uint32_t uECX = pCurLeaf->uEcx;
6946	uint32_t uEDX = pCurLeaf->uEdx;
6947	char sz1[32];
6948	char sz2[32];
6949
6950	pHlp->pfnPrintf(pHlp,
6951	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6952	"TLB 2/4M Data: %s %3d entries\n",
6953	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6954	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6955	pHlp->pfnPrintf(pHlp,
6956	"TLB 4K Instr/Uni: %s %3d entries\n"
6957	"TLB 4K Data: %s %3d entries\n",
6958	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6959	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6960	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6961	"L1 Instr Cache Lines Per Tag: %d\n"
6962	"L1 Instr Cache Associativity: %s\n"
6963	"L1 Instr Cache Size: %d KB\n",
6964	(uEDX >> 0) & 0xff,
6965	(uEDX >> 8) & 0xff,
6966	getCacheAss((uEDX >> 16) & 0xff, sz1),
6967	(uEDX >> 24) & 0xff);
6968	pHlp->pfnPrintf(pHlp,
6969	"L1 Data Cache Line Size: %d bytes\n"
6970	"L1 Data Cache Lines Per Tag: %d\n"
6971	"L1 Data Cache Associativity: %s\n"
6972	"L1 Data Cache Size: %d KB\n",
6973	(uECX >> 0) & 0xff,
6974	(uECX >> 8) & 0xff,
6975	getCacheAss((uECX >> 16) & 0xff, sz1),
6976	(uECX >> 24) & 0xff);
6977	}
6978
6979	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6980	{
6981	uint32_t uEAX = pCurLeaf->uEax;
6982	uint32_t uEBX = pCurLeaf->uEbx;
6983	uint32_t uEDX = pCurLeaf->uEdx;
6984
6985	pHlp->pfnPrintf(pHlp,
6986	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6987	"L2 TLB 2/4M Data: %s %4d entries\n",
6988	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6989	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6990	pHlp->pfnPrintf(pHlp,
6991	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6992	"L2 TLB 4K Data: %s %4d entries\n",
6993	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6994	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6995	pHlp->pfnPrintf(pHlp,
6996	"L2 Cache Line Size: %d bytes\n"
6997	"L2 Cache Lines Per Tag: %d\n"
6998	"L2 Cache Associativity: %s\n"
6999	"L2 Cache Size: %d KB\n",
7000	(uEDX >> 0) & 0xff,
7001	(uEDX >> 8) & 0xf,
7002	getL2CacheAss((uEDX >> 12) & 0xf),
7003	(uEDX >> 16) & 0xffff);
7004	}
7005
7006	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
7007	{
7008	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7009	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
7010	{
7011	if (iVerbosity < 1)
7012	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7013	else
7014	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7015	}
7016	}
7017
7018	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7019	if (pCurLeaf != NULL)
7020	{
7021	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7022	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7023	{
7024	if (iVerbosity < 1)
7025	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7026	else
7027	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7028	}
7029
7030	if (iVerbosity)
7031	{
7032	uint32_t uEAX = pCurLeaf->uEax;
7033	uint32_t uECX = pCurLeaf->uEcx;
7034
7035	pHlp->pfnPrintf(pHlp,
7036	"Physical Address Width: %d bits\n"
7037	"Virtual Address Width: %d bits\n"
7038	"Guest Physical Address Width: %d bits\n",
7039	(uEAX >> 0) & 0xff,
7040	(uEAX >> 8) & 0xff,
7041	(uEAX >> 16) & 0xff);
7042	pHlp->pfnPrintf(pHlp,
7043	"Physical Core Count: %d\n",
7044	((uECX >> 0) & 0xff) + 1);
7045	}
7046	}
7047
7048	pCurLeaf = pNextLeaf;
7049	}
7050
7051
7052
7053	/*
7054	* Centaur.
7055	*/
7056	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7057
7058	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7059	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7060	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7061	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7062	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7063	cMax = RT_MAX(cHstMax, cGstMax);
7064	if (cMax >= UINT32_C(0xc0000000))
7065	{
7066	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7067
7068	/*
7069	* Understandable output
7070	*/
7071	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7072	pHlp->pfnPrintf(pHlp,
7073	"Centaur Supports: 0xc0000000-%#010x\n",
7074	pCurLeaf->uEax);
7075
7076	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7077	{
7078	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7079	uint32_t uEdxGst = pCurLeaf->uEdx;
7080	uint32_t uEdxHst = Host.uEdx;
7081
7082	if (iVerbosity == 1)
7083	{
7084	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7085	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7086	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7087	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7088	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7089	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7090	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7091	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7092	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7093	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7094	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7095	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7096	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7097	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7098	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7099	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7100	for (unsigned iBit = 14; iBit < 32; iBit++)
7101	if (uEdxGst & RT_BIT(iBit))
7102	pHlp->pfnPrintf(pHlp, " %d", iBit);
7103	pHlp->pfnPrintf(pHlp, "\n");
7104	}
7105	else
7106	{
7107	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7108	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7109	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7110	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7111	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7112	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7113	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7114	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7115	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7116	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7117	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7118	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7119	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7120	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7121	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7122	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7123	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7124	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7125	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7126	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7127	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7128	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7129	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7130	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7131	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7132	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7133	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7134	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7135	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7136	for (unsigned iBit = 27; iBit < 32; iBit++)
7137	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7138	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7139	pHlp->pfnPrintf(pHlp, "\n");
7140	}
7141	}
7142
7143	pCurLeaf = pNextLeaf;
7144	}
7145
7146	/*
7147	* The remainder.
7148	*/
7149	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7150	}
7151
7152	#endif /* VBOX_IN_VMM */
7153

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 80074

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