CPUMR3CpuId.cpp@ 80239

Last change on this file since 80239 was 80191, checked in by vboxsync, 5 years ago
VMM/r3: Refactored VMCPU enumeration in preparation that aCpus will be replaced with a pointer array. Removed two raw-mode offset members from the CPUM and CPUMCPU sub-structures. bugref:9217 bugref:9517
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 332.5 KB

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1	/* $Id: CPUMR3CpuId.cpp 80191 2019-08-08 00:36:57Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define VBOX_BUGREF_9217_PART_I
23	#define LOG_GROUP LOG_GROUP_CPUM
24	#include <VBox/vmm/cpum.h>
25	#include <VBox/vmm/dbgf.h>
26	#include <VBox/vmm/hm.h>
27	#include <VBox/vmm/nem.h>
28	#include <VBox/vmm/ssm.h>
29	#include "CPUMInternal.h"
30	#include <VBox/vmm/vm.h>
31	#include <VBox/vmm/mm.h>
32	#include <VBox/sup.h>
33
34	#include <VBox/err.h>
35	#include <iprt/asm-amd64-x86.h>
36	#include <iprt/ctype.h>
37	#include <iprt/mem.h>
38	#include <iprt/string.h>
39
40
41	/*********************************************************************************************************************************
42	* Defined Constants And Macros *
43	*********************************************************************************************************************************/
44	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
45	#define CPUM_CPUID_MAX_LEAVES 2048
46	/* Max size we accept for the XSAVE area. */
47	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
48	/* Min size we accept for the XSAVE area. */
49	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
50
51
52	/*********************************************************************************************************************************
53	* Global Variables *
54	*********************************************************************************************************************************/
55	/**
56	* The intel pentium family.
57	*/
58	static const CPUMMICROARCH g_aenmIntelFamily06[] =
59	{
60	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
61	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
62	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
63	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
64	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
65	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
66	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
67	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
68	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
69	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
70	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
71	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
72	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
73	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
74	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
75	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
76	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
81	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
82	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
83	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
84	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
86	/* [26(0x1a)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Nehalem-EP */
87	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
88	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
89	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
90	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
91	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
92	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
97	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
98	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
99	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
100	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
102	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
103	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
104	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
105	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
106	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
107	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
108	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
113	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
114	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
115	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
116	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
118	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
119	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
120	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
121	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
122	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
123	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
124	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
129	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
130	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
131	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
132	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
134	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
135	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
136	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
137	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
138	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,
139	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Broadwell-E */
140	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
145	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu; skylake <= 4, cascade lake > 5 */
146	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
147	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
148	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
150	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
151	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
152	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
153	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
154	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
155	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
156	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
159	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
160	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
161	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
162	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
163	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
164	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
165	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
166	/[106(0x6a)] = / kCpumMicroarch_Intel_Unknown,
167	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
168	/[108(0x6c)] = / kCpumMicroarch_Intel_Unknown,
169	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
170	/[110(0x6e)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
171	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
172	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
173	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
174	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
175	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
176	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
177	/[117(0x75)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
178	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
179	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
180	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
181	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
182	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
183	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
184	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
185	/[125(0x7d)] = / kCpumMicroarch_Intel_Unknown,
186	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
187	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
188	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
189	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
190	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
191	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
192	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
193	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
194	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
195	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
196	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
197	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
198	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
199	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
200	/[140(0x8c)] = / kCpumMicroarch_Intel_Unknown,
201	/[141(0x8d)] = / kCpumMicroarch_Intel_Unknown,
202	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
203	/[143(0x8f)] = / kCpumMicroarch_Intel_Unknown,
204	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
205	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
206	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
207	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
208	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
209	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
210	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
211	/[151(0x97)] = / kCpumMicroarch_Intel_Unknown,
212	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
213	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
214	/[154(0x9a)] = / kCpumMicroarch_Intel_Unknown,
215	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
216	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
217	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
218	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
219	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
220	};
221	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0x9f+1);
222
223
224	/**
225	* Figures out the (sub-)micro architecture given a bit of CPUID info.
226	*
227	* @returns Micro architecture.
228	* @param enmVendor The CPU vendor .
229	* @param bFamily The CPU family.
230	* @param bModel The CPU model.
231	* @param bStepping The CPU stepping.
232	*/
233	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
234	uint8_t bModel, uint8_t bStepping)
235	{
236	if (enmVendor == CPUMCPUVENDOR_AMD)
237	{
238	switch (bFamily)
239	{
240	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
241	case 0x03: return kCpumMicroarch_AMD_Am386;
242	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
243	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
244	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
245	case 0x06:
246	switch (bModel)
247	{
248	case 0: return kCpumMicroarch_AMD_K7_Palomino;
249	case 1: return kCpumMicroarch_AMD_K7_Palomino;
250	case 2: return kCpumMicroarch_AMD_K7_Palomino;
251	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
252	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
253	case 6: return kCpumMicroarch_AMD_K7_Palomino;
254	case 7: return kCpumMicroarch_AMD_K7_Morgan;
255	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
256	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
257	}
258	return kCpumMicroarch_AMD_K7_Unknown;
259	case 0x0f:
260	/*
261	* This family is a friggin mess. Trying my best to make some
262	* sense out of it. Too much happened in the 0x0f family to
263	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
264	*
265	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
266	* cpu-world.com, and other places:
267	* - 130nm:
268	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
269	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
270	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
271	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
272	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
273	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
274	* - 90nm:
275	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
276	* - Oakville: 10FC0/DH-D0.
277	* - Georgetown: 10FC0/DH-D0.
278	* - Sonora: 10FC0/DH-D0.
279	* - Venus: 20F71/SH-E4
280	* - Troy: 20F51/SH-E4
281	* - Athens: 20F51/SH-E4
282	* - San Diego: 20F71/SH-E4.
283	* - Lancaster: 20F42/SH-E5
284	* - Newark: 20F42/SH-E5.
285	* - Albany: 20FC2/DH-E6.
286	* - Roma: 20FC2/DH-E6.
287	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
288	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
289	* - 90nm introducing Dual core:
290	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
291	* - Italy: 20F10/JH-E1, 20F12/JH-E6
292	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
293	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
294	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
295	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
296	* - Santa Ana: 40F32/JH-F2, /-F3
297	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
298	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
299	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
300	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
301	* - Keene: 40FC2/DH-F2.
302	* - Richmond: 40FC2/DH-F2
303	* - Taylor: 40F82/BH-F2
304	* - Trinidad: 40F82/BH-F2
305	*
306	* - 65nm:
307	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
308	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
309	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
310	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
311	* - Sherman: /-G1, 70FC2/DH-G2.
312	* - Huron: 70FF2/DH-G2.
313	*/
314	if (bModel < 0x10)
315	return kCpumMicroarch_AMD_K8_130nm;
316	if (bModel >= 0x60 && bModel < 0x80)
317	return kCpumMicroarch_AMD_K8_65nm;
318	if (bModel >= 0x40)
319	return kCpumMicroarch_AMD_K8_90nm_AMDV;
320	switch (bModel)
321	{
322	case 0x21:
323	case 0x23:
324	case 0x2b:
325	case 0x2f:
326	case 0x37:
327	case 0x3f:
328	return kCpumMicroarch_AMD_K8_90nm_DualCore;
329	}
330	return kCpumMicroarch_AMD_K8_90nm;
331	case 0x10:
332	return kCpumMicroarch_AMD_K10;
333	case 0x11:
334	return kCpumMicroarch_AMD_K10_Lion;
335	case 0x12:
336	return kCpumMicroarch_AMD_K10_Llano;
337	case 0x14:
338	return kCpumMicroarch_AMD_Bobcat;
339	case 0x15:
340	switch (bModel)
341	{
342	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
343	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
344	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
345	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
346	case 0x11: /* ?? */
347	case 0x12: /* ?? */
348	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
349	}
350	return kCpumMicroarch_AMD_15h_Unknown;
351	case 0x16:
352	return kCpumMicroarch_AMD_Jaguar;
353	case 0x17:
354	return kCpumMicroarch_AMD_Zen_Ryzen;
355	}
356	return kCpumMicroarch_AMD_Unknown;
357	}
358
359	if (enmVendor == CPUMCPUVENDOR_INTEL)
360	{
361	switch (bFamily)
362	{
363	case 3:
364	return kCpumMicroarch_Intel_80386;
365	case 4:
366	return kCpumMicroarch_Intel_80486;
367	case 5:
368	return kCpumMicroarch_Intel_P5;
369	case 6:
370	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
371	{
372	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
373	if (enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake)
374	{
375	if (bStepping >= 0xa && bStepping <= 0xc)
376	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
377	else if (bStepping >= 0xc)
378	enmMicroArch = kCpumMicroarch_Intel_Core7_WhiskeyLake;
379	}
380	else if ( enmMicroArch == kCpumMicroarch_Intel_Core7_Skylake
381	&& bModel == 0x55
382	&& bStepping >= 5)
383	enmMicroArch = kCpumMicroarch_Intel_Core7_CascadeLake;
384	return enmMicroArch;
385	}
386	return kCpumMicroarch_Intel_Atom_Unknown;
387	case 15:
388	switch (bModel)
389	{
390	case 0: return kCpumMicroarch_Intel_NB_Willamette;
391	case 1: return kCpumMicroarch_Intel_NB_Willamette;
392	case 2: return kCpumMicroarch_Intel_NB_Northwood;
393	case 3: return kCpumMicroarch_Intel_NB_Prescott;
394	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
395	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
396	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
397	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
398	default: return kCpumMicroarch_Intel_NB_Unknown;
399	}
400	break;
401	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
402	case 0:
403	return kCpumMicroarch_Intel_8086;
404	case 1:
405	return kCpumMicroarch_Intel_80186;
406	case 2:
407	return kCpumMicroarch_Intel_80286;
408	}
409	return kCpumMicroarch_Intel_Unknown;
410	}
411
412	if (enmVendor == CPUMCPUVENDOR_VIA)
413	{
414	switch (bFamily)
415	{
416	case 5:
417	switch (bModel)
418	{
419	case 1: return kCpumMicroarch_Centaur_C6;
420	case 4: return kCpumMicroarch_Centaur_C6;
421	case 8: return kCpumMicroarch_Centaur_C2;
422	case 9: return kCpumMicroarch_Centaur_C3;
423	}
424	break;
425
426	case 6:
427	switch (bModel)
428	{
429	case 5: return kCpumMicroarch_VIA_C3_M2;
430	case 6: return kCpumMicroarch_VIA_C3_C5A;
431	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
432	case 8: return kCpumMicroarch_VIA_C3_C5N;
433	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
434	case 10: return kCpumMicroarch_VIA_C7_C5J;
435	case 15: return kCpumMicroarch_VIA_Isaiah;
436	}
437	break;
438	}
439	return kCpumMicroarch_VIA_Unknown;
440	}
441
442	if (enmVendor == CPUMCPUVENDOR_SHANGHAI)
443	{
444	switch (bFamily)
445	{
446	case 6:
447	case 7:
448	return kCpumMicroarch_Shanghai_Wudaokou;
449	default:
450	break;
451	}
452	return kCpumMicroarch_Shanghai_Unknown;
453	}
454
455	if (enmVendor == CPUMCPUVENDOR_CYRIX)
456	{
457	switch (bFamily)
458	{
459	case 4:
460	switch (bModel)
461	{
462	case 9: return kCpumMicroarch_Cyrix_5x86;
463	}
464	break;
465
466	case 5:
467	switch (bModel)
468	{
469	case 2: return kCpumMicroarch_Cyrix_M1;
470	case 4: return kCpumMicroarch_Cyrix_MediaGX;
471	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
472	}
473	break;
474
475	case 6:
476	switch (bModel)
477	{
478	case 0: return kCpumMicroarch_Cyrix_M2;
479	}
480	break;
481
482	}
483	return kCpumMicroarch_Cyrix_Unknown;
484	}
485
486	return kCpumMicroarch_Unknown;
487	}
488
489
490	/**
491	* Translates a microarchitecture enum value to the corresponding string
492	* constant.
493	*
494	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
495	* NULL if the value is invalid.
496	*
497	* @param enmMicroarch The enum value to convert.
498	*/
499	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
500	{
501	switch (enmMicroarch)
502	{
503	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
504	CASE_RET_STR(kCpumMicroarch_Intel_8086);
505	CASE_RET_STR(kCpumMicroarch_Intel_80186);
506	CASE_RET_STR(kCpumMicroarch_Intel_80286);
507	CASE_RET_STR(kCpumMicroarch_Intel_80386);
508	CASE_RET_STR(kCpumMicroarch_Intel_80486);
509	CASE_RET_STR(kCpumMicroarch_Intel_P5);
510
511	CASE_RET_STR(kCpumMicroarch_Intel_P6);
512	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
513	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
514
515	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
516	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
517	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
518
519	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
520	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
521
522	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
523	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
524	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
525	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
526	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
527	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
528	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
529	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
530	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
531	CASE_RET_STR(kCpumMicroarch_Intel_Core7_WhiskeyLake);
532	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CascadeLake);
533	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
534	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
535	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
536
537	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
538	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
539	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
540	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
541	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
542	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
543	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
544	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
545
546	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
547	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
548	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
549	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
550	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
551
552	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
553	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
554	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
555	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
556	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
557	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
558	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
559
560	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
561
562	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
563	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
564	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
565	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
566	CASE_RET_STR(kCpumMicroarch_AMD_K5);
567	CASE_RET_STR(kCpumMicroarch_AMD_K6);
568
569	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
570	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
571	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
572	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
573	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
574	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
575	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
576
577	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
578	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
579	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
580	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
581	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
582
583	CASE_RET_STR(kCpumMicroarch_AMD_K10);
584	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
585	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
586	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
587	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
588
589	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
590	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
591	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
592	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
593	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
594
595	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
596
597	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
598
599	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
600
601	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
602	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
603	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
604	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
605	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
606	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
607	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
608	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
609	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
610	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
611	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
612	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
613	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
614
615	CASE_RET_STR(kCpumMicroarch_Shanghai_Wudaokou);
616	CASE_RET_STR(kCpumMicroarch_Shanghai_Unknown);
617
618	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
619	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
620	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
621	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
622	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
623	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
624
625	CASE_RET_STR(kCpumMicroarch_NEC_V20);
626	CASE_RET_STR(kCpumMicroarch_NEC_V30);
627
628	CASE_RET_STR(kCpumMicroarch_Unknown);
629
630	#undef CASE_RET_STR
631	case kCpumMicroarch_Invalid:
632	case kCpumMicroarch_Intel_End:
633	case kCpumMicroarch_Intel_Core2_End:
634	case kCpumMicroarch_Intel_Core7_End:
635	case kCpumMicroarch_Intel_Atom_End:
636	case kCpumMicroarch_Intel_P6_Core_Atom_End:
637	case kCpumMicroarch_Intel_Phi_End:
638	case kCpumMicroarch_Intel_NB_End:
639	case kCpumMicroarch_AMD_K7_End:
640	case kCpumMicroarch_AMD_K8_End:
641	case kCpumMicroarch_AMD_15h_End:
642	case kCpumMicroarch_AMD_16h_End:
643	case kCpumMicroarch_AMD_Zen_End:
644	case kCpumMicroarch_AMD_End:
645	case kCpumMicroarch_VIA_End:
646	case kCpumMicroarch_Cyrix_End:
647	case kCpumMicroarch_NEC_End:
648	case kCpumMicroarch_Shanghai_End:
649	case kCpumMicroarch_32BitHack:
650	break;
651	/* no default! */
652	}
653
654	return NULL;
655	}
656
657
658	/**
659	* Determins the host CPU MXCSR mask.
660	*
661	* @returns MXCSR mask.
662	*/
663	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
664	{
665	if ( ASMHasCpuId()
666	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
667	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
668	{
669	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
670	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
671	RT_ZERO(*pState);
672	ASMFxSave(pState);
673	if (pState->MXCSR_MASK == 0)
674	return 0xffbf;
675	return pState->MXCSR_MASK;
676	}
677	return 0;
678	}
679
680
681	/**
682	* Gets a matching leaf in the CPUID leaf array.
683	*
684	* @returns Pointer to the matching leaf, or NULL if not found.
685	* @param paLeaves The CPUID leaves to search. This is sorted.
686	* @param cLeaves The number of leaves in the array.
687	* @param uLeaf The leaf to locate.
688	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
689	*/
690	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
691	{
692	/* Lazy bird does linear lookup here since this is only used for the
693	occational CPUID overrides. */
694	for (uint32_t i = 0; i < cLeaves; i++)
695	if ( paLeaves[i].uLeaf == uLeaf
696	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
697	return &paLeaves[i];
698	return NULL;
699	}
700
701
702	#ifndef IN_VBOX_CPU_REPORT
703	/**
704	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
705	*
706	* @returns true if found, false it not.
707	* @param paLeaves The CPUID leaves to search. This is sorted.
708	* @param cLeaves The number of leaves in the array.
709	* @param uLeaf The leaf to locate.
710	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
711	* @param pLegacy The legacy output leaf.
712	*/
713	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
714	PCPUMCPUID pLegacy)
715	{
716	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
717	if (pLeaf)
718	{
719	pLegacy->uEax = pLeaf->uEax;
720	pLegacy->uEbx = pLeaf->uEbx;
721	pLegacy->uEcx = pLeaf->uEcx;
722	pLegacy->uEdx = pLeaf->uEdx;
723	return true;
724	}
725	return false;
726	}
727	#endif /* IN_VBOX_CPU_REPORT */
728
729
730	/**
731	* Ensures that the CPUID leaf array can hold one more leaf.
732	*
733	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
734	* failure.
735	* @param pVM The cross context VM structure. If NULL, use
736	* the process heap, otherwise the VM's hyper heap.
737	* @param ppaLeaves Pointer to the variable holding the array pointer
738	* (input/output).
739	* @param cLeaves The current array size.
740	*
741	* @remarks This function will automatically update the R0 and RC pointers when
742	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
743	* be the corresponding VM's CPUID arrays (which is asserted).
744	*/
745	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
746	{
747	/*
748	* If pVM is not specified, we're on the regular heap and can waste a
749	* little space to speed things up.
750	*/
751	uint32_t cAllocated;
752	if (!pVM)
753	{
754	cAllocated = RT_ALIGN(cLeaves, 16);
755	if (cLeaves + 1 > cAllocated)
756	{
757	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
758	if (pvNew)
759	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
760	else
761	{
762	RTMemFree(*ppaLeaves);
763	*ppaLeaves = NULL;
764	}
765	}
766	}
767	/*
768	* Otherwise, we're on the hyper heap and are probably just inserting
769	* one or two leaves and should conserve space.
770	*/
771	else
772	{
773	#ifdef IN_VBOX_CPU_REPORT
774	AssertReleaseFailed();
775	#else
776	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
777	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
778
779	size_t cb = cLeaves * sizeof(**ppaLeaves);
780	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
781	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
782	if (RT_SUCCESS(rc))
783	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
784	else
785	{
786	*ppaLeaves = NULL;
787	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
788	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
789	}
790	#endif
791	}
792	return *ppaLeaves;
793	}
794
795
796	/**
797	* Append a CPUID leaf or sub-leaf.
798	*
799	* ASSUMES linear insertion order, so we'll won't need to do any searching or
800	* replace anything. Use cpumR3CpuIdInsert() for those cases.
801	*
802	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
803	* the caller need do no more work.
804	* @param ppaLeaves Pointer to the pointer to the array of sorted
805	* CPUID leaves and sub-leaves.
806	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
807	* @param uLeaf The leaf we're adding.
808	* @param uSubLeaf The sub-leaf number.
809	* @param fSubLeafMask The sub-leaf mask.
810	* @param uEax The EAX value.
811	* @param uEbx The EBX value.
812	* @param uEcx The ECX value.
813	* @param uEdx The EDX value.
814	* @param fFlags The flags.
815	*/
816	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
817	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
818	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
819	{
820	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
821	return VERR_NO_MEMORY;
822
823	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
824	Assert( *pcLeaves == 0
825	\|\| pNew[-1].uLeaf < uLeaf
826	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
827
828	pNew->uLeaf = uLeaf;
829	pNew->uSubLeaf = uSubLeaf;
830	pNew->fSubLeafMask = fSubLeafMask;
831	pNew->uEax = uEax;
832	pNew->uEbx = uEbx;
833	pNew->uEcx = uEcx;
834	pNew->uEdx = uEdx;
835	pNew->fFlags = fFlags;
836
837	*pcLeaves += 1;
838	return VINF_SUCCESS;
839	}
840
841
842	/**
843	* Checks that we've updated the CPUID leaves array correctly.
844	*
845	* This is a no-op in non-strict builds.
846	*
847	* @param paLeaves The leaves array.
848	* @param cLeaves The number of leaves.
849	*/
850	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
851	{
852	#ifdef VBOX_STRICT
853	for (uint32_t i = 1; i < cLeaves; i++)
854	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
855	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
856	else
857	{
858	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
859	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
860	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
861	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
862	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
863	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
864	}
865	#else
866	NOREF(paLeaves);
867	NOREF(cLeaves);
868	#endif
869	}
870
871
872	/**
873	* Inserts a CPU ID leaf, replacing any existing ones.
874	*
875	* When inserting a simple leaf where we already got a series of sub-leaves with
876	* the same leaf number (eax), the simple leaf will replace the whole series.
877	*
878	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
879	* host-context heap and has only been allocated/reallocated by the
880	* cpumR3CpuIdEnsureSpace function.
881	*
882	* @returns VBox status code.
883	* @param pVM The cross context VM structure. If NULL, use
884	* the process heap, otherwise the VM's hyper heap.
885	* @param ppaLeaves Pointer to the pointer to the array of sorted
886	* CPUID leaves and sub-leaves. Must be NULL if using
887	* the hyper heap.
888	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
889	* be NULL if using the hyper heap.
890	* @param pNewLeaf Pointer to the data of the new leaf we're about to
891	* insert.
892	*/
893	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
894	{
895	/*
896	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
897	*/
898	if (pVM)
899	{
900	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
901	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
902
903	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
904	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
905	}
906
907	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
908	uint32_t cLeaves = *pcLeaves;
909
910	/*
911	* Validate the new leaf a little.
912	*/
913	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
914	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
915	VERR_INVALID_FLAGS);
916	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
917	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
918	VERR_INVALID_PARAMETER);
919	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
920	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
921	VERR_INVALID_PARAMETER);
922	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
923	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
924	VERR_INVALID_PARAMETER);
925
926	/*
927	* Find insertion point. The lazy bird uses the same excuse as in
928	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
929	*/
930	uint32_t i;
931	if ( cLeaves > 0
932	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
933	{
934	/* Add at end. */
935	i = cLeaves;
936	}
937	else if ( cLeaves > 0
938	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
939	{
940	/* Either replacing the last leaf or dealing with sub-leaves. Spool
941	back to the first sub-leaf to pretend we did the linear search. */
942	i = cLeaves - 1;
943	while ( i > 0
944	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
945	i--;
946	}
947	else
948	{
949	/* Linear search from the start. */
950	i = 0;
951	while ( i < cLeaves
952	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
953	i++;
954	}
955	if ( i < cLeaves
956	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
957	{
958	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
959	{
960	/*
961	* The sub-leaf mask differs, replace all existing leaves with the
962	* same leaf number.
963	*/
964	uint32_t c = 1;
965	while ( i + c < cLeaves
966	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
967	c++;
968	if (c > 1 && i + c < cLeaves)
969	{
970	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
971	*pcLeaves = cLeaves -= c - 1;
972	}
973
974	paLeaves[i] = *pNewLeaf;
975	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
976	return VINF_SUCCESS;
977	}
978
979	/* Find sub-leaf insertion point. */
980	while ( i < cLeaves
981	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
982	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
983	i++;
984
985	/*
986	* If we've got an exactly matching leaf, replace it.
987	*/
988	if ( i < cLeaves
989	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
990	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
991	{
992	paLeaves[i] = *pNewLeaf;
993	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
994	return VINF_SUCCESS;
995	}
996	}
997
998	/*
999	* Adding a new leaf at 'i'.
1000	*/
1001	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
1002	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
1003	if (!paLeaves)
1004	return VERR_NO_MEMORY;
1005
1006	if (i < cLeaves)
1007	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
1008	*pcLeaves += 1;
1009	paLeaves[i] = *pNewLeaf;
1010
1011	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1012	return VINF_SUCCESS;
1013	}
1014
1015
1016	#ifndef IN_VBOX_CPU_REPORT
1017	/**
1018	* Removes a range of CPUID leaves.
1019	*
1020	* This will not reallocate the array.
1021	*
1022	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1023	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1024	* @param uFirst The first leaf.
1025	* @param uLast The last leaf.
1026	*/
1027	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1028	{
1029	uint32_t cLeaves = *pcLeaves;
1030
1031	Assert(uFirst <= uLast);
1032
1033	/*
1034	* Find the first one.
1035	*/
1036	uint32_t iFirst = 0;
1037	while ( iFirst < cLeaves
1038	&& paLeaves[iFirst].uLeaf < uFirst)
1039	iFirst++;
1040
1041	/*
1042	* Find the end (last + 1).
1043	*/
1044	uint32_t iEnd = iFirst;
1045	while ( iEnd < cLeaves
1046	&& paLeaves[iEnd].uLeaf <= uLast)
1047	iEnd++;
1048
1049	/*
1050	* Adjust the array if anything needs removing.
1051	*/
1052	if (iFirst < iEnd)
1053	{
1054	if (iEnd < cLeaves)
1055	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1056	*pcLeaves = cLeaves -= (iEnd - iFirst);
1057	}
1058
1059	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1060	}
1061	#endif /* IN_VBOX_CPU_REPORT */
1062
1063
1064	/**
1065	* Checks if ECX make a difference when reading a given CPUID leaf.
1066	*
1067	* @returns @c true if it does, @c false if it doesn't.
1068	* @param uLeaf The leaf we're reading.
1069	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1070	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1071	* final sub-leaf (for leaf 0xb only).
1072	*/
1073	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1074	{
1075	*pfFinalEcxUnchanged = false;
1076
1077	uint32_t auCur[4];
1078	uint32_t auPrev[4];
1079	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1080
1081	/* Look for sub-leaves. */
1082	uint32_t uSubLeaf = 1;
1083	for (;;)
1084	{
1085	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1086	if (memcmp(auCur, auPrev, sizeof(auCur)))
1087	break;
1088
1089	/* Advance / give up. */
1090	uSubLeaf++;
1091	if (uSubLeaf >= 64)
1092	{
1093	*pcSubLeaves = 1;
1094	return false;
1095	}
1096	}
1097
1098	/* Count sub-leaves. */
1099	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1100	uint32_t cRepeats = 0;
1101	uSubLeaf = 0;
1102	for (;;)
1103	{
1104	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1105
1106	/* Figuring out when to stop isn't entirely straight forward as we need
1107	to cover undocumented behavior up to a point and implementation shortcuts. */
1108
1109	/* 1. Look for more than 4 repeating value sets. */
1110	if ( auCur[0] == auPrev[0]
1111	&& auCur[1] == auPrev[1]
1112	&& ( auCur[2] == auPrev[2]
1113	\|\| ( auCur[2] == uSubLeaf
1114	&& auPrev[2] == uSubLeaf - 1) )
1115	&& auCur[3] == auPrev[3])
1116	{
1117	if ( uLeaf != 0xd
1118	\|\| uSubLeaf >= 64
1119	\|\| ( auCur[0] == 0
1120	&& auCur[1] == 0
1121	&& auCur[2] == 0
1122	&& auCur[3] == 0
1123	&& auPrev[2] == 0) )
1124	cRepeats++;
1125	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1126	break;
1127	}
1128	else
1129	cRepeats = 0;
1130
1131	/* 2. Look for zero values. */
1132	if ( auCur[0] == 0
1133	&& auCur[1] == 0
1134	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1135	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1136	&& uSubLeaf >= cMinLeaves)
1137	{
1138	cRepeats = 0;
1139	break;
1140	}
1141
1142	/* 3. Leaf 0xb level type 0 check. */
1143	if ( uLeaf == 0xb
1144	&& (auCur[2] & 0xff00) == 0
1145	&& (auPrev[2] & 0xff00) == 0)
1146	{
1147	cRepeats = 0;
1148	break;
1149	}
1150
1151	/* 99. Give up. */
1152	if (uSubLeaf >= 128)
1153	{
1154	#ifndef IN_VBOX_CPU_REPORT
1155	/* Ok, limit it according to the documentation if possible just to
1156	avoid annoying users with these detection issues. */
1157	uint32_t cDocLimit = UINT32_MAX;
1158	if (uLeaf == 0x4)
1159	cDocLimit = 4;
1160	else if (uLeaf == 0x7)
1161	cDocLimit = 1;
1162	else if (uLeaf == 0xd)
1163	cDocLimit = 63;
1164	else if (uLeaf == 0xf)
1165	cDocLimit = 2;
1166	if (cDocLimit != UINT32_MAX)
1167	{
1168	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1169	*pcSubLeaves = cDocLimit + 3;
1170	return true;
1171	}
1172	#endif
1173	*pcSubLeaves = UINT32_MAX;
1174	return true;
1175	}
1176
1177	/* Advance. */
1178	uSubLeaf++;
1179	memcpy(auPrev, auCur, sizeof(auCur));
1180	}
1181
1182	/* Standard exit. */
1183	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1184	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1185	if (*pcSubLeaves == 0)
1186	*pcSubLeaves = 1;
1187	return true;
1188	}
1189
1190
1191	/**
1192	* Gets a CPU ID leaf.
1193	*
1194	* @returns VBox status code.
1195	* @param pVM The cross context VM structure.
1196	* @param pLeaf Where to store the found leaf.
1197	* @param uLeaf The leaf to locate.
1198	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1199	*/
1200	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1201	{
1202	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1203	uLeaf, uSubLeaf);
1204	if (pcLeaf)
1205	{
1206	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1207	return VINF_SUCCESS;
1208	}
1209
1210	return VERR_NOT_FOUND;
1211	}
1212
1213
1214	/**
1215	* Inserts a CPU ID leaf, replacing any existing ones.
1216	*
1217	* @returns VBox status code.
1218	* @param pVM The cross context VM structure.
1219	* @param pNewLeaf Pointer to the leaf being inserted.
1220	*/
1221	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1222	{
1223	/*
1224	* Validate parameters.
1225	*/
1226	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1227	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1228
1229	/*
1230	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1231	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1232	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1233	*/
1234	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1235	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1236	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1237	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1238	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1239	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1240	{
1241	return VERR_NOT_SUPPORTED;
1242	}
1243
1244	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1245	}
1246
1247	/**
1248	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1249	*
1250	* @returns VBox status code.
1251	* @param ppaLeaves Where to return the array pointer on success.
1252	* Use RTMemFree to release.
1253	* @param pcLeaves Where to return the size of the array on
1254	* success.
1255	*/
1256	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1257	{
1258	*ppaLeaves = NULL;
1259	*pcLeaves = 0;
1260
1261	/*
1262	* Try out various candidates. This must be sorted!
1263	*/
1264	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1265	{
1266	{ UINT32_C(0x00000000), false },
1267	{ UINT32_C(0x10000000), false },
1268	{ UINT32_C(0x20000000), false },
1269	{ UINT32_C(0x30000000), false },
1270	{ UINT32_C(0x40000000), false },
1271	{ UINT32_C(0x50000000), false },
1272	{ UINT32_C(0x60000000), false },
1273	{ UINT32_C(0x70000000), false },
1274	{ UINT32_C(0x80000000), false },
1275	{ UINT32_C(0x80860000), false },
1276	{ UINT32_C(0x8ffffffe), true },
1277	{ UINT32_C(0x8fffffff), true },
1278	{ UINT32_C(0x90000000), false },
1279	{ UINT32_C(0xa0000000), false },
1280	{ UINT32_C(0xb0000000), false },
1281	{ UINT32_C(0xc0000000), false },
1282	{ UINT32_C(0xd0000000), false },
1283	{ UINT32_C(0xe0000000), false },
1284	{ UINT32_C(0xf0000000), false },
1285	};
1286
1287	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1288	{
1289	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1290	uint32_t uEax, uEbx, uEcx, uEdx;
1291	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1292
1293	/*
1294	* Does EAX look like a typical leaf count value?
1295	*/
1296	if ( uEax > uLeaf
1297	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1298	{
1299	/* Yes, dump them. */
1300	uint32_t cLeaves = uEax - uLeaf + 1;
1301	while (cLeaves-- > 0)
1302	{
1303	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1304
1305	uint32_t fFlags = 0;
1306
1307	/* There are currently three known leaves containing an APIC ID
1308	that needs EMT specific attention */
1309	if (uLeaf == 1)
1310	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1311	else if (uLeaf == 0xb && uEcx != 0)
1312	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1313	else if ( uLeaf == UINT32_C(0x8000001e)
1314	&& ( uEax
1315	\|\| uEbx
1316	\|\| uEdx
1317	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1318	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1319
1320	/* The APIC bit is per-VCpu and needs flagging. */
1321	if (uLeaf == 1)
1322	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1323	else if ( uLeaf == UINT32_C(0x80000001)
1324	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1325	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1326	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1327
1328	/* Check three times here to reduce the chance of CPU migration
1329	resulting in false positives with things like the APIC ID. */
1330	uint32_t cSubLeaves;
1331	bool fFinalEcxUnchanged;
1332	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1333	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1334	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1335	{
1336	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1337	{
1338	/* This shouldn't happen. But in case it does, file all
1339	relevant details in the release log. */
1340	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1341	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1342	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1343	{
1344	uint32_t auTmp[4];
1345	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1346	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1347	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1348	}
1349	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1350	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1351	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1352	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1353	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1354	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1355	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1356	}
1357
1358	if (fFinalEcxUnchanged)
1359	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1360
1361	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1362	{
1363	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1364	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1365	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1366	if (RT_FAILURE(rc))
1367	return rc;
1368	}
1369	}
1370	else
1371	{
1372	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1373	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1374	if (RT_FAILURE(rc))
1375	return rc;
1376	}
1377
1378	/* next */
1379	uLeaf++;
1380	}
1381	}
1382	/*
1383	* Special CPUIDs needs special handling as they don't follow the
1384	* leaf count principle used above.
1385	*/
1386	else if (s_aCandidates[iOuter].fSpecial)
1387	{
1388	bool fKeep = false;
1389	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1390	fKeep = true;
1391	else if ( uLeaf == 0x8fffffff
1392	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1393	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1394	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1395	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1396	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1397	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1398	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1399	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1400	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1401	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1402	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1403	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1404	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1405	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1406	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1407	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1408	fKeep = true;
1409	if (fKeep)
1410	{
1411	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1412	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1413	if (RT_FAILURE(rc))
1414	return rc;
1415	}
1416	}
1417	}
1418
1419	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1420	return VINF_SUCCESS;
1421	}
1422
1423
1424	/**
1425	* Determines the method the CPU uses to handle unknown CPUID leaves.
1426	*
1427	* @returns VBox status code.
1428	* @param penmUnknownMethod Where to return the method.
1429	* @param pDefUnknown Where to return default unknown values. This
1430	* will be set, even if the resulting method
1431	* doesn't actually needs it.
1432	*/
1433	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1434	{
1435	uint32_t uLastStd = ASMCpuId_EAX(0);
1436	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1437	if (!ASMIsValidExtRange(uLastExt))
1438	uLastExt = 0x80000000;
1439
1440	uint32_t auChecks[] =
1441	{
1442	uLastStd + 1,
1443	uLastStd + 5,
1444	uLastStd + 8,
1445	uLastStd + 32,
1446	uLastStd + 251,
1447	uLastExt + 1,
1448	uLastExt + 8,
1449	uLastExt + 15,
1450	uLastExt + 63,
1451	uLastExt + 255,
1452	0x7fbbffcc,
1453	0x833f7872,
1454	0xefff2353,
1455	0x35779456,
1456	0x1ef6d33e,
1457	};
1458
1459	static const uint32_t s_auValues[] =
1460	{
1461	0xa95d2156,
1462	0x00000001,
1463	0x00000002,
1464	0x00000008,
1465	0x00000000,
1466	0x55773399,
1467	0x93401769,
1468	0x12039587,
1469	};
1470
1471	/*
1472	* Simple method, all zeros.
1473	*/
1474	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1475	pDefUnknown->uEax = 0;
1476	pDefUnknown->uEbx = 0;
1477	pDefUnknown->uEcx = 0;
1478	pDefUnknown->uEdx = 0;
1479
1480	/*
1481	* Intel has been observed returning the last standard leaf.
1482	*/
1483	uint32_t auLast[4];
1484	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1485
1486	uint32_t cChecks = RT_ELEMENTS(auChecks);
1487	while (cChecks > 0)
1488	{
1489	uint32_t auCur[4];
1490	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1491	if (memcmp(auCur, auLast, sizeof(auCur)))
1492	break;
1493	cChecks--;
1494	}
1495	if (cChecks == 0)
1496	{
1497	/* Now, what happens when the input changes? Esp. ECX. */
1498	uint32_t cTotal = 0;
1499	uint32_t cSame = 0;
1500	uint32_t cLastWithEcx = 0;
1501	uint32_t cNeither = 0;
1502	uint32_t cValues = RT_ELEMENTS(s_auValues);
1503	while (cValues > 0)
1504	{
1505	uint32_t uValue = s_auValues[cValues - 1];
1506	uint32_t auLastWithEcx[4];
1507	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1508	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1509
1510	cChecks = RT_ELEMENTS(auChecks);
1511	while (cChecks > 0)
1512	{
1513	uint32_t auCur[4];
1514	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1515	if (!memcmp(auCur, auLast, sizeof(auCur)))
1516	{
1517	cSame++;
1518	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1519	cLastWithEcx++;
1520	}
1521	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1522	cLastWithEcx++;
1523	else
1524	cNeither++;
1525	cTotal++;
1526	cChecks--;
1527	}
1528	cValues--;
1529	}
1530
1531	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1532	if (cSame == cTotal)
1533	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1534	else if (cLastWithEcx == cTotal)
1535	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1536	else
1537	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1538	pDefUnknown->uEax = auLast[0];
1539	pDefUnknown->uEbx = auLast[1];
1540	pDefUnknown->uEcx = auLast[2];
1541	pDefUnknown->uEdx = auLast[3];
1542	return VINF_SUCCESS;
1543	}
1544
1545	/*
1546	* Unchanged register values?
1547	*/
1548	cChecks = RT_ELEMENTS(auChecks);
1549	while (cChecks > 0)
1550	{
1551	uint32_t const uLeaf = auChecks[cChecks - 1];
1552	uint32_t cValues = RT_ELEMENTS(s_auValues);
1553	while (cValues > 0)
1554	{
1555	uint32_t uValue = s_auValues[cValues - 1];
1556	uint32_t auCur[4];
1557	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1558	if ( auCur[0] != uLeaf
1559	\|\| auCur[1] != uValue
1560	\|\| auCur[2] != uValue
1561	\|\| auCur[3] != uValue)
1562	break;
1563	cValues--;
1564	}
1565	if (cValues != 0)
1566	break;
1567	cChecks--;
1568	}
1569	if (cChecks == 0)
1570	{
1571	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1572	return VINF_SUCCESS;
1573	}
1574
1575	/*
1576	* Just go with the simple method.
1577	*/
1578	return VINF_SUCCESS;
1579	}
1580
1581
1582	/**
1583	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1584	*
1585	* @returns Read only name string.
1586	* @param enmUnknownMethod The method to translate.
1587	*/
1588	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1589	{
1590	switch (enmUnknownMethod)
1591	{
1592	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1593	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1594	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1595	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1596
1597	case CPUMUNKNOWNCPUID_INVALID:
1598	case CPUMUNKNOWNCPUID_END:
1599	case CPUMUNKNOWNCPUID_32BIT_HACK:
1600	break;
1601	}
1602	return "Invalid-unknown-CPUID-method";
1603	}
1604
1605
1606	/**
1607	* Detect the CPU vendor give n the
1608	*
1609	* @returns The vendor.
1610	* @param uEAX EAX from CPUID(0).
1611	* @param uEBX EBX from CPUID(0).
1612	* @param uECX ECX from CPUID(0).
1613	* @param uEDX EDX from CPUID(0).
1614	*/
1615	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1616	{
1617	if (ASMIsValidStdRange(uEAX))
1618	{
1619	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1620	return CPUMCPUVENDOR_AMD;
1621
1622	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1623	return CPUMCPUVENDOR_INTEL;
1624
1625	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1626	return CPUMCPUVENDOR_VIA;
1627
1628	if (ASMIsShanghaiCpuEx(uEBX, uECX, uEDX))
1629	return CPUMCPUVENDOR_SHANGHAI;
1630
1631	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1632	&& uECX == UINT32_C(0x64616574)
1633	&& uEDX == UINT32_C(0x736E4978))
1634	return CPUMCPUVENDOR_CYRIX;
1635
1636	/* "Geode by NSC", example: family 5, model 9. */
1637
1638	/** @todo detect the other buggers... */
1639	}
1640
1641	return CPUMCPUVENDOR_UNKNOWN;
1642	}
1643
1644
1645	/**
1646	* Translates a CPU vendor enum value into the corresponding string constant.
1647	*
1648	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1649	* value name. This can be useful when generating code.
1650	*
1651	* @returns Read only name string.
1652	* @param enmVendor The CPU vendor value.
1653	*/
1654	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1655	{
1656	switch (enmVendor)
1657	{
1658	case CPUMCPUVENDOR_INTEL: return "INTEL";
1659	case CPUMCPUVENDOR_AMD: return "AMD";
1660	case CPUMCPUVENDOR_VIA: return "VIA";
1661	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1662	case CPUMCPUVENDOR_SHANGHAI: return "SHANGHAI";
1663	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1664
1665	case CPUMCPUVENDOR_INVALID:
1666	case CPUMCPUVENDOR_32BIT_HACK:
1667	break;
1668	}
1669	return "Invalid-cpu-vendor";
1670	}
1671
1672
1673	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1674	{
1675	/* Could do binary search, doing linear now because I'm lazy. */
1676	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1677	while (cLeaves-- > 0)
1678	{
1679	if (pLeaf->uLeaf == uLeaf)
1680	return pLeaf;
1681	pLeaf++;
1682	}
1683	return NULL;
1684	}
1685
1686
1687	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1688	{
1689	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1690	if ( !pLeaf
1691	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1692	return pLeaf;
1693
1694	/* Linear sub-leaf search. Lazy as usual. */
1695	cLeaves -= pLeaf - paLeaves;
1696	while ( cLeaves-- > 0
1697	&& pLeaf->uLeaf == uLeaf)
1698	{
1699	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1700	return pLeaf;
1701	pLeaf++;
1702	}
1703
1704	return NULL;
1705	}
1706
1707
1708	static void cpumR3ExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURES pFeatures)
1709	{
1710	Assert(pVmxMsrs);
1711	Assert(pFeatures);
1712	Assert(pFeatures->fVmx);
1713
1714	/* Basic information. */
1715	{
1716	uint64_t const u64Basic = pVmxMsrs->u64Basic;
1717	pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1718	}
1719
1720	/* Pin-based VM-execution controls. */
1721	{
1722	uint32_t const fPinCtls = pVmxMsrs->PinCtls.n.allowed1;
1723	pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1724	pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1725	pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1726	pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1727	pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1728	}
1729
1730	/* Processor-based VM-execution controls. */
1731	{
1732	uint32_t const fProcCtls = pVmxMsrs->ProcCtls.n.allowed1;
1733	pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1734	pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1735	pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1736	pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1737	pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1738	pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1739	pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1740	pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1741	pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1742	pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1743	pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1744	pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1745	pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1746	pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1747	pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1748	pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1749	pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1750	pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1751	pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1752	pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1753	pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1754	}
1755
1756	/* Secondary processor-based VM-execution controls. */
1757	{
1758	uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1759	pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1760	pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1761	pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1762	pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1763	pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1764	pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1765	pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1766	pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1767	pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1768	pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1769	pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1770	pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1771	pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1772	pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1773	pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1774	pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1775	pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1776	pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_VE);
1777	pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1778	pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1779	}
1780
1781	/* VM-exit controls. */
1782	{
1783	uint32_t const fExitCtls = pVmxMsrs->ExitCtls.n.allowed1;
1784	pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1785	pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1786	pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1787	pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1788	pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1789	pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1790	pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1791	pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1792	}
1793
1794	/* VM-entry controls. */
1795	{
1796	uint32_t const fEntryCtls = pVmxMsrs->EntryCtls.n.allowed1;
1797	pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1798	pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1799	pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1800	pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1801	}
1802
1803	/* Miscellaneous data. */
1804	{
1805	uint32_t const fMiscData = pVmxMsrs->u64Misc;
1806	pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1807	pFeatures->fVmxIntelPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1808	pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1809	pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1810	}
1811	}
1812
1813
1814	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures)
1815	{
1816	Assert(pMsrs);
1817	RT_ZERO(*pFeatures);
1818	if (cLeaves >= 2)
1819	{
1820	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1821	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1822	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1823	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1824	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1825	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1826
1827	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1828	pStd0Leaf->uEbx,
1829	pStd0Leaf->uEcx,
1830	pStd0Leaf->uEdx);
1831	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1832	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1833	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1834	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1835	pFeatures->uFamily,
1836	pFeatures->uModel,
1837	pFeatures->uStepping);
1838
1839	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1840	if (pExtLeaf8)
1841	{
1842	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1843	pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1844	}
1845	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1846	{
1847	pFeatures->cMaxPhysAddrWidth = 36;
1848	pFeatures->cMaxLinearAddrWidth = 36;
1849	}
1850	else
1851	{
1852	pFeatures->cMaxPhysAddrWidth = 32;
1853	pFeatures->cMaxLinearAddrWidth = 32;
1854	}
1855
1856	/* Standard features. */
1857	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1858	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1859	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1860	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1861	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1862	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1863	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1864	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1865	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1866	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1867	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1868	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1869	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1870	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1871	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1872	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1873	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1874	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1875	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1876	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1877	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1878	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1879	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1880	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1881	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1882	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1883	if (pFeatures->fVmx)
1884	cpumR3ExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1885
1886	/* Structured extended features. */
1887	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1888	if (pSxfLeaf0)
1889	{
1890	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1891	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1892	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1893	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1894	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1895
1896	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1897	pFeatures->fIbrs = pFeatures->fIbpb;
1898	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1899	pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
1900	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1901	pFeatures->fMdsClear = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
1902	}
1903
1904	/* MWAIT/MONITOR leaf. */
1905	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1906	if (pMWaitLeaf)
1907	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1908	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1909
1910	/* Extended features. */
1911	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1912	if (pExtLeaf)
1913	{
1914	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1915	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1916	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1917	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1918	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1919	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1920	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1921	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1922	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1923	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1924	}
1925
1926	/* VMX (VMXON, VMCS region and related data structures) physical address width (depends on long-mode). */
1927	pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
1928
1929	if ( pExtLeaf
1930	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1931	{
1932	/* AMD features. */
1933	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1934	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1935	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1936	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1937	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1938	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1939	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1940	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1941	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1942	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1943	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1944	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1945	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1946	if (pFeatures->fSvm)
1947	{
1948	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1949	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1950	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1951	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1952	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1953	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1954	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1955	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1956	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1957	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1958	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1959	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1960	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1961	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1962	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1963	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1964	}
1965	}
1966
1967	/*
1968	* Quirks.
1969	*/
1970	pFeatures->fLeakyFxSR = pExtLeaf
1971	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1972	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1973	&& pFeatures->uFamily >= 6 /* K7 and up */;
1974
1975	/*
1976	* Max extended (/FPU) state.
1977	*/
1978	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1979	if (pFeatures->fXSaveRstor)
1980	{
1981	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1982	if (pXStateLeaf0)
1983	{
1984	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1985	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1986	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1987	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1988	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1989	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1990	{
1991	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1992
1993	/* (paranoia:) */
1994	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1995	if ( pXStateLeaf1
1996	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1997	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1998	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1999	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
2000	}
2001	else
2002	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
2003	pFeatures->fXSaveRstor = 0);
2004	}
2005	else
2006	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
2007	pFeatures->fXSaveRstor = 0);
2008	}
2009	}
2010	else
2011	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
2012	return VINF_SUCCESS;
2013	}
2014
2015
2016	/*
2017	*
2018	* Init related code.
2019	* Init related code.
2020	* Init related code.
2021	*
2022	*
2023	*/
2024	#ifdef VBOX_IN_VMM
2025
2026
2027	/**
2028	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
2029	*
2030	* This ignores the fSubLeafMask.
2031	*
2032	* @returns Pointer to the matching leaf, or NULL if not found.
2033	* @param paLeaves The CPUID leaves to search. This is sorted.
2034	* @param cLeaves The number of leaves in the array.
2035	* @param uLeaf The leaf to locate.
2036	* @param uSubLeaf The subleaf to locate.
2037	*/
2038	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
2039	{
2040	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
2041	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
2042	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
2043	if (iEnd)
2044	{
2045	uint32_t iBegin = 0;
2046	for (;;)
2047	{
2048	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
2049	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
2050	if (uNeedle < uCur)
2051	{
2052	if (i > iBegin)
2053	iEnd = i;
2054	else
2055	break;
2056	}
2057	else if (uNeedle > uCur)
2058	{
2059	if (i + 1 < iEnd)
2060	iBegin = i + 1;
2061	else
2062	break;
2063	}
2064	else
2065	return &paLeaves[i];
2066	}
2067	}
2068	return NULL;
2069	}
2070
2071
2072	/**
2073	* Loads MSR range overrides.
2074	*
2075	* This must be called before the MSR ranges are moved from the normal heap to
2076	* the hyper heap!
2077	*
2078	* @returns VBox status code (VMSetError called).
2079	* @param pVM The cross context VM structure.
2080	* @param pMsrNode The CFGM node with the MSR overrides.
2081	*/
2082	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
2083	{
2084	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2085	{
2086	/*
2087	* Assemble a valid MSR range.
2088	*/
2089	CPUMMSRRANGE MsrRange;
2090	MsrRange.offCpumCpu = 0;
2091	MsrRange.fReserved = 0;
2092
2093	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
2094	if (RT_FAILURE(rc))
2095	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
2096
2097	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
2098	if (RT_FAILURE(rc))
2099	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
2100	MsrRange.szName, rc);
2101
2102	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
2103	if (RT_FAILURE(rc))
2104	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
2105	MsrRange.szName, rc);
2106
2107	char szType[32];
2108	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
2109	if (RT_FAILURE(rc))
2110	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
2111	MsrRange.szName, rc);
2112	if (!RTStrICmp(szType, "FixedValue"))
2113	{
2114	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
2115	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
2116
2117	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
2118	if (RT_FAILURE(rc))
2119	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
2120	MsrRange.szName, rc);
2121
2122	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
2123	if (RT_FAILURE(rc))
2124	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
2125	MsrRange.szName, rc);
2126
2127	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
2128	if (RT_FAILURE(rc))
2129	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
2130	MsrRange.szName, rc);
2131	}
2132	else
2133	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
2134	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
2135
2136	/*
2137	* Insert the range into the table (replaces/splits/shrinks existing
2138	* MSR ranges).
2139	*/
2140	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
2141	&MsrRange);
2142	if (RT_FAILURE(rc))
2143	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
2144	}
2145
2146	return VINF_SUCCESS;
2147	}
2148
2149
2150	/**
2151	* Loads CPUID leaf overrides.
2152	*
2153	* This must be called before the CPUID leaves are moved from the normal
2154	* heap to the hyper heap!
2155	*
2156	* @returns VBox status code (VMSetError called).
2157	* @param pVM The cross context VM structure.
2158	* @param pParentNode The CFGM node with the CPUID leaves.
2159	* @param pszLabel How to label the overrides we're loading.
2160	*/
2161	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2162	{
2163	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2164	{
2165	/*
2166	* Get the leaf and subleaf numbers.
2167	*/
2168	char szName[128];
2169	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2170	if (RT_FAILURE(rc))
2171	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2172
2173	/* The leaf number is either specified directly or thru the node name. */
2174	uint32_t uLeaf;
2175	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2176	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2177	{
2178	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2179	if (rc != VINF_SUCCESS)
2180	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2181	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2182	}
2183	else if (RT_FAILURE(rc))
2184	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2185	pszLabel, szName, rc);
2186
2187	uint32_t uSubLeaf;
2188	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2189	if (RT_FAILURE(rc))
2190	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2191	pszLabel, szName, rc);
2192
2193	uint32_t fSubLeafMask;
2194	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2195	if (RT_FAILURE(rc))
2196	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2197	pszLabel, szName, rc);
2198
2199	/*
2200	* Look up the specified leaf, since the output register values
2201	* defaults to any existing values. This allows overriding a single
2202	* register, without needing to know the other values.
2203	*/
2204	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2205	CPUMCPUIDLEAF Leaf;
2206	if (pLeaf)
2207	Leaf = *pLeaf;
2208	else
2209	RT_ZERO(Leaf);
2210	Leaf.uLeaf = uLeaf;
2211	Leaf.uSubLeaf = uSubLeaf;
2212	Leaf.fSubLeafMask = fSubLeafMask;
2213
2214	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2215	if (RT_FAILURE(rc))
2216	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2217	pszLabel, szName, rc);
2218	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2219	if (RT_FAILURE(rc))
2220	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2221	pszLabel, szName, rc);
2222	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2223	if (RT_FAILURE(rc))
2224	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2225	pszLabel, szName, rc);
2226	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2227	if (RT_FAILURE(rc))
2228	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2229	pszLabel, szName, rc);
2230
2231	/*
2232	* Insert the leaf into the table (replaces existing ones).
2233	*/
2234	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2235	&Leaf);
2236	if (RT_FAILURE(rc))
2237	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2238	}
2239
2240	return VINF_SUCCESS;
2241	}
2242
2243
2244
2245	/**
2246	* Fetches overrides for a CPUID leaf.
2247	*
2248	* @returns VBox status code.
2249	* @param pLeaf The leaf to load the overrides into.
2250	* @param pCfgNode The CFGM node containing the overrides
2251	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2252	* @param iLeaf The CPUID leaf number.
2253	*/
2254	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2255	{
2256	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2257	if (pLeafNode)
2258	{
2259	uint32_t u32;
2260	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2261	if (RT_SUCCESS(rc))
2262	pLeaf->uEax = u32;
2263	else
2264	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2265
2266	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2267	if (RT_SUCCESS(rc))
2268	pLeaf->uEbx = u32;
2269	else
2270	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2271
2272	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2273	if (RT_SUCCESS(rc))
2274	pLeaf->uEcx = u32;
2275	else
2276	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2277
2278	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2279	if (RT_SUCCESS(rc))
2280	pLeaf->uEdx = u32;
2281	else
2282	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2283
2284	}
2285	return VINF_SUCCESS;
2286	}
2287
2288
2289	/**
2290	* Load the overrides for a set of CPUID leaves.
2291	*
2292	* @returns VBox status code.
2293	* @param paLeaves The leaf array.
2294	* @param cLeaves The number of leaves.
2295	* @param uStart The start leaf number.
2296	* @param pCfgNode The CFGM node containing the overrides
2297	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2298	*/
2299	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2300	{
2301	for (uint32_t i = 0; i < cLeaves; i++)
2302	{
2303	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2304	if (RT_FAILURE(rc))
2305	return rc;
2306	}
2307
2308	return VINF_SUCCESS;
2309	}
2310
2311
2312	/**
2313	* Installs the CPUID leaves and explods the data into structures like
2314	* GuestFeatures and CPUMCTX::aoffXState.
2315	*
2316	* @returns VBox status code.
2317	* @param pVM The cross context VM structure.
2318	* @param pCpum The CPUM part of @a VM.
2319	* @param paLeaves The leaves. These will be copied (but not freed).
2320	* @param cLeaves The number of leaves.
2321	* @param pMsrs The MSRs.
2322	*/
2323	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
2324	{
2325	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2326
2327	/*
2328	* Install the CPUID information.
2329	*/
2330	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2331	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2332
2333	AssertLogRelRCReturn(rc, rc);
2334	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2335	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2336	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2337
2338	/*
2339	* Update the default CPUID leaf if necessary.
2340	*/
2341	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2342	{
2343	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2344	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2345	{
2346	/* We don't use CPUID(0).eax here because of the NT hack that only
2347	changes that value without actually removing any leaves. */
2348	uint32_t i = 0;
2349	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2350	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2351	{
2352	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2353	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2354	i++;
2355	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2356	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2357	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2358	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2359	}
2360	break;
2361	}
2362	default:
2363	break;
2364	}
2365
2366	/*
2367	* Explode the guest CPU features.
2368	*/
2369	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
2370	&pCpum->GuestFeatures);
2371	AssertLogRelRCReturn(rc, rc);
2372
2373	/*
2374	* Adjust the scalable bus frequency according to the CPUID information
2375	* we're now using.
2376	*/
2377	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2378	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2379	? UINT64_C(100000000) /* 100MHz */
2380	: UINT64_C(133333333); /* 133MHz */
2381
2382	/*
2383	* Populate the legacy arrays. Currently used for everything, later only
2384	* for patch manager.
2385	*/
2386	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2387	{
2388	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2389	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2390	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2391	};
2392	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2393	{
2394	uint32_t cLeft = aOldRanges[i].cCpuIds;
2395	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2396	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2397	while (cLeft-- > 0)
2398	{
2399	uLeaf--;
2400	pLegacyLeaf--;
2401
2402	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2403	if (pLeaf)
2404	{
2405	pLegacyLeaf->uEax = pLeaf->uEax;
2406	pLegacyLeaf->uEbx = pLeaf->uEbx;
2407	pLegacyLeaf->uEcx = pLeaf->uEcx;
2408	pLegacyLeaf->uEdx = pLeaf->uEdx;
2409	}
2410	else
2411	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2412	}
2413	}
2414
2415	/*
2416	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2417	*/
2418	PVMCPU pVCpu0 = pVM->apCpusR3[0];
2419	memset(&pVCpu0->cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2420	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2421	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2422	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2423	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2424	{
2425	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2426	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2427	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2428	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2429	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2430	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2431	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2432	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2433	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2434	pCpum->GuestFeatures.cbMaxExtendedState),
2435	VERR_CPUM_IPE_1);
2436	pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2437	}
2438
2439	/* Copy the CPU #0 data to the other CPUs. */
2440	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
2441	{
2442	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2443	memcpy(&pVCpu->cpum.s.Guest.aoffXState[0], &pVCpu0->cpum.s.Guest.aoffXState[0], sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2444	}
2445
2446	return VINF_SUCCESS;
2447	}
2448
2449
2450	/** @name Instruction Set Extension Options
2451	* @{ */
2452	/** Configuration option type (extended boolean, really). */
2453	typedef uint8_t CPUMISAEXTCFG;
2454	/** Always disable the extension. */
2455	#define CPUMISAEXTCFG_DISABLED false
2456	/** Enable the extension if it's supported by the host CPU. */
2457	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2458	/** Enable the extension if it's supported by the host CPU, but don't let
2459	* the portable CPUID feature disable it. */
2460	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2461	/** Always enable the extension. */
2462	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2463	/** @} */
2464
2465	/**
2466	* CPUID Configuration (from CFGM).
2467	*
2468	* @remarks The members aren't document since we would only be duplicating the
2469	* \@cfgm entries in cpumR3CpuIdReadConfig.
2470	*/
2471	typedef struct CPUMCPUIDCONFIG
2472	{
2473	bool fNt4LeafLimit;
2474	bool fInvariantTsc;
2475	bool fForceVme;
2476	bool fNestedHWVirt;
2477
2478	CPUMISAEXTCFG enmCmpXchg16b;
2479	CPUMISAEXTCFG enmMonitor;
2480	CPUMISAEXTCFG enmMWaitExtensions;
2481	CPUMISAEXTCFG enmSse41;
2482	CPUMISAEXTCFG enmSse42;
2483	CPUMISAEXTCFG enmAvx;
2484	CPUMISAEXTCFG enmAvx2;
2485	CPUMISAEXTCFG enmXSave;
2486	CPUMISAEXTCFG enmAesNi;
2487	CPUMISAEXTCFG enmPClMul;
2488	CPUMISAEXTCFG enmPopCnt;
2489	CPUMISAEXTCFG enmMovBe;
2490	CPUMISAEXTCFG enmRdRand;
2491	CPUMISAEXTCFG enmRdSeed;
2492	CPUMISAEXTCFG enmCLFlushOpt;
2493	CPUMISAEXTCFG enmFsGsBase;
2494	CPUMISAEXTCFG enmPcid;
2495	CPUMISAEXTCFG enmInvpcid;
2496	CPUMISAEXTCFG enmFlushCmdMsr;
2497	CPUMISAEXTCFG enmMdsClear;
2498	CPUMISAEXTCFG enmArchCapMsr;
2499
2500	CPUMISAEXTCFG enmAbm;
2501	CPUMISAEXTCFG enmSse4A;
2502	CPUMISAEXTCFG enmMisAlnSse;
2503	CPUMISAEXTCFG enm3dNowPrf;
2504	CPUMISAEXTCFG enmAmdExtMmx;
2505
2506	uint32_t uMaxStdLeaf;
2507	uint32_t uMaxExtLeaf;
2508	uint32_t uMaxCentaurLeaf;
2509	uint32_t uMaxIntelFamilyModelStep;
2510	char szCpuName[128];
2511	} CPUMCPUIDCONFIG;
2512	/** Pointer to CPUID config (from CFGM). */
2513	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2514
2515
2516	/**
2517	* Mini CPU selection support for making Mac OS X happy.
2518	*
2519	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2520	*
2521	* @param pCpum The CPUM instance data.
2522	* @param pConfig The CPUID configuration we've read from CFGM.
2523	*/
2524	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2525	{
2526	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2527	{
2528	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2529	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2530	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2531	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2532	0);
2533	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2534	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2535	{
2536	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2537	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2538	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2539	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2540	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2541	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2542	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2543	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2544	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2545	pStdFeatureLeaf->uEax = uNew;
2546	}
2547	}
2548	}
2549
2550
2551
2552	/**
2553	* Limit it the number of entries, zapping the remainder.
2554	*
2555	* The limits are masking off stuff about power saving and similar, this
2556	* is perhaps a bit crudely done as there is probably some relatively harmless
2557	* info too in these leaves (like words about having a constant TSC).
2558	*
2559	* @param pCpum The CPUM instance data.
2560	* @param pConfig The CPUID configuration we've read from CFGM.
2561	*/
2562	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2563	{
2564	/*
2565	* Standard leaves.
2566	*/
2567	uint32_t uSubLeaf = 0;
2568	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2569	if (pCurLeaf)
2570	{
2571	uint32_t uLimit = pCurLeaf->uEax;
2572	if (uLimit <= UINT32_C(0x000fffff))
2573	{
2574	if (uLimit > pConfig->uMaxStdLeaf)
2575	{
2576	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2577	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2578	uLimit + 1, UINT32_C(0x000fffff));
2579	}
2580
2581	/* NT4 hack, no zapping of extra leaves here. */
2582	if (pConfig->fNt4LeafLimit && uLimit > 3)
2583	pCurLeaf->uEax = uLimit = 3;
2584
2585	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2586	pCurLeaf->uEax = uLimit;
2587	}
2588	else
2589	{
2590	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2591	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2592	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2593	}
2594	}
2595
2596	/*
2597	* Extended leaves.
2598	*/
2599	uSubLeaf = 0;
2600	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2601	if (pCurLeaf)
2602	{
2603	uint32_t uLimit = pCurLeaf->uEax;
2604	if ( uLimit >= UINT32_C(0x80000000)
2605	&& uLimit <= UINT32_C(0x800fffff))
2606	{
2607	if (uLimit > pConfig->uMaxExtLeaf)
2608	{
2609	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2610	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2611	uLimit + 1, UINT32_C(0x800fffff));
2612	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2613	pCurLeaf->uEax = uLimit;
2614	}
2615	}
2616	else
2617	{
2618	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2619	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2620	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2621	}
2622	}
2623
2624	/*
2625	* Centaur leaves (VIA).
2626	*/
2627	uSubLeaf = 0;
2628	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2629	if (pCurLeaf)
2630	{
2631	uint32_t uLimit = pCurLeaf->uEax;
2632	if ( uLimit >= UINT32_C(0xc0000000)
2633	&& uLimit <= UINT32_C(0xc00fffff))
2634	{
2635	if (uLimit > pConfig->uMaxCentaurLeaf)
2636	{
2637	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2638	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2639	uLimit + 1, UINT32_C(0xcfffffff));
2640	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2641	pCurLeaf->uEax = uLimit;
2642	}
2643	}
2644	else
2645	{
2646	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2647	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2648	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2649	}
2650	}
2651	}
2652
2653
2654	/**
2655	* Clears a CPUID leaf and all sub-leaves (to zero).
2656	*
2657	* @param pCpum The CPUM instance data.
2658	* @param uLeaf The leaf to clear.
2659	*/
2660	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2661	{
2662	uint32_t uSubLeaf = 0;
2663	PCPUMCPUIDLEAF pCurLeaf;
2664	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2665	{
2666	pCurLeaf->uEax = 0;
2667	pCurLeaf->uEbx = 0;
2668	pCurLeaf->uEcx = 0;
2669	pCurLeaf->uEdx = 0;
2670	uSubLeaf++;
2671	}
2672	}
2673
2674
2675	/**
2676	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2677	* the given leaf.
2678	*
2679	* @returns pLeaf.
2680	* @param pCpum The CPUM instance data.
2681	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2682	*/
2683	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2684	{
2685	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2686	if (pLeaf->fSubLeafMask != 0)
2687	{
2688	/*
2689	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2690	* Log everything while we're at it.
2691	*/
2692	LogRel(("CPUM:\n"
2693	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2694	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2695	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2696	for (;;)
2697	{
2698	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2699	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2700	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2701	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2702	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2703	break;
2704	pSubLeaf++;
2705	}
2706	LogRel(("CPUM:\n"));
2707
2708	/*
2709	* Remove the offending sub-leaves.
2710	*/
2711	if (pSubLeaf != pLeaf)
2712	{
2713	if (pSubLeaf != pLast)
2714	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2715	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2716	}
2717
2718	/*
2719	* Convert the first sub-leaf into a single leaf.
2720	*/
2721	pLeaf->uSubLeaf = 0;
2722	pLeaf->fSubLeafMask = 0;
2723	}
2724	return pLeaf;
2725	}
2726
2727
2728	/**
2729	* Sanitizes and adjust the CPUID leaves.
2730	*
2731	* Drop features that aren't virtualized (or virtualizable). Adjust information
2732	* and capabilities to fit the virtualized hardware. Remove information the
2733	* guest shouldn't have (because it's wrong in the virtual world or because it
2734	* gives away host details) or that we don't have documentation for and no idea
2735	* what means.
2736	*
2737	* @returns VBox status code.
2738	* @param pVM The cross context VM structure (for cCpus).
2739	* @param pCpum The CPUM instance data.
2740	* @param pConfig The CPUID configuration we've read from CFGM.
2741	*/
2742	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2743	{
2744	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2745	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2746	{ \
2747	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2748	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2749	}
2750	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2751	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2752	{ \
2753	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2754	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2755	}
2756	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2757	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2758	&& ((a_pLeafReg) & (fBitMask)) \
2759	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2760	{ \
2761	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2762	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2763	}
2764	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2765
2766	/* Cpuid 1:
2767	* EAX: CPU model, family and stepping.
2768	*
2769	* ECX + EDX: Supported features. Only report features we can support.
2770	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2771	* options may require adjusting (i.e. stripping what was enabled).
2772	*
2773	* EBX: Branding, CLFLUSH line size, logical processors per package and
2774	* initial APIC ID.
2775	*/
2776	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2777	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2778	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2779
2780	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2781	\| X86_CPUID_FEATURE_EDX_VME
2782	\| X86_CPUID_FEATURE_EDX_DE
2783	\| X86_CPUID_FEATURE_EDX_PSE
2784	\| X86_CPUID_FEATURE_EDX_TSC
2785	\| X86_CPUID_FEATURE_EDX_MSR
2786	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2787	\| X86_CPUID_FEATURE_EDX_MCE
2788	\| X86_CPUID_FEATURE_EDX_CX8
2789	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2790	//\| RT_BIT_32(10) - not defined
2791	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2792	//\| X86_CPUID_FEATURE_EDX_SEP
2793	\| X86_CPUID_FEATURE_EDX_MTRR
2794	\| X86_CPUID_FEATURE_EDX_PGE
2795	\| X86_CPUID_FEATURE_EDX_MCA
2796	\| X86_CPUID_FEATURE_EDX_CMOV
2797	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2798	\| X86_CPUID_FEATURE_EDX_PSE36
2799	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2800	\| X86_CPUID_FEATURE_EDX_CLFSH
2801	//\| RT_BIT_32(20) - not defined
2802	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2803	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2804	\| X86_CPUID_FEATURE_EDX_MMX
2805	\| X86_CPUID_FEATURE_EDX_FXSR
2806	\| X86_CPUID_FEATURE_EDX_SSE
2807	\| X86_CPUID_FEATURE_EDX_SSE2
2808	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2809	\| X86_CPUID_FEATURE_EDX_HTT
2810	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2811	//\| RT_BIT_32(30) - not defined
2812	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2813	;
2814	pStdFeatureLeaf->uEcx &= 0
2815	\| X86_CPUID_FEATURE_ECX_SSE3
2816	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2817	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2818	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2819	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2820	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2821	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2822	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2823	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2824	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2825	\| X86_CPUID_FEATURE_ECX_SSSE3
2826	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2827	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2828	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2829	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2830	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2831	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2832	\| (pConfig->enmPcid ? X86_CPUID_FEATURE_ECX_PCID : 0)
2833	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2834	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2835	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2836	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2837	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2838	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2839	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2840	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2841	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2842	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2843	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2844	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2845	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2846	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2847	;
2848
2849	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2850	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2851	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2852	{
2853	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2854	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2855	}
2856
2857	if (pCpum->u8PortableCpuIdLevel > 0)
2858	{
2859	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2860	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2861	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2862	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2863	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2864	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2865	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2866	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2867	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2868	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2869	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2870	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2871	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2872	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2873	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2874	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2875	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2876	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2877	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2878	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2879
2880	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2881	\| X86_CPUID_FEATURE_EDX_PSN
2882	\| X86_CPUID_FEATURE_EDX_DS
2883	\| X86_CPUID_FEATURE_EDX_ACPI
2884	\| X86_CPUID_FEATURE_EDX_SS
2885	\| X86_CPUID_FEATURE_EDX_TM
2886	\| X86_CPUID_FEATURE_EDX_PBE
2887	)));
2888	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2889	\| X86_CPUID_FEATURE_ECX_CPLDS
2890	\| X86_CPUID_FEATURE_ECX_AES
2891	\| X86_CPUID_FEATURE_ECX_VMX
2892	\| X86_CPUID_FEATURE_ECX_SMX
2893	\| X86_CPUID_FEATURE_ECX_EST
2894	\| X86_CPUID_FEATURE_ECX_TM2
2895	\| X86_CPUID_FEATURE_ECX_CNTXID
2896	\| X86_CPUID_FEATURE_ECX_FMA
2897	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2898	\| X86_CPUID_FEATURE_ECX_PDCM
2899	\| X86_CPUID_FEATURE_ECX_DCA
2900	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2901	)));
2902	}
2903
2904	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2905	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2906
2907	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2908	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2909	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2910	*/
2911	#ifdef VBOX_WITH_MULTI_CORE
2912	if (pVM->cCpus > 1)
2913	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2914	#endif
2915	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2916	{
2917	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2918	core times the number of CPU cores per processor */
2919	#ifdef VBOX_WITH_MULTI_CORE
2920	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2921	#else
2922	/* Single logical processor in a package. */
2923	pStdFeatureLeaf->uEbx \|= (1 << 16);
2924	#endif
2925	}
2926
2927	uint32_t uMicrocodeRev;
2928	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2929	if (RT_SUCCESS(rc))
2930	{
2931	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2932	}
2933	else
2934	{
2935	uMicrocodeRev = 0;
2936	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2937	}
2938
2939	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2940	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2941	*/
2942	if ( (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen)
2943	&& uMicrocodeRev < 0x8001126
2944	&& !pConfig->fForceVme)
2945	{
2946	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2947	LogRel(("CPUM: Zen VME workaround engaged\n"));
2948	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2949	}
2950
2951	/* Force standard feature bits. */
2952	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2953	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2954	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2955	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2956	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2957	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2958	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2959	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2960	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2961	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2962	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2963	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2964	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2965	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2966	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2967	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2968	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2969	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2970	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2971	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2972	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2973	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2974
2975	pStdFeatureLeaf = NULL; /* Must refetch! */
2976
2977	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2978	* AMD:
2979	* EAX: CPU model, family and stepping.
2980	*
2981	* ECX + EDX: Supported features. Only report features we can support.
2982	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2983	* options may require adjusting (i.e. stripping what was enabled).
2984	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2985	*
2986	* EBX: Branding ID and package type (or reserved).
2987	*
2988	* Intel and probably most others:
2989	* EAX: 0
2990	* EBX: 0
2991	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2992	*/
2993	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2994	if (pExtFeatureLeaf)
2995	{
2996	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2997
2998	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2999	\| X86_CPUID_AMD_FEATURE_EDX_VME
3000	\| X86_CPUID_AMD_FEATURE_EDX_DE
3001	\| X86_CPUID_AMD_FEATURE_EDX_PSE
3002	\| X86_CPUID_AMD_FEATURE_EDX_TSC
3003	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
3004	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
3005	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
3006	\| X86_CPUID_AMD_FEATURE_EDX_CX8
3007	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
3008	//\| RT_BIT_32(10) - reserved
3009	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
3010	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
3011	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3012	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
3013	\| X86_CPUID_AMD_FEATURE_EDX_PGE
3014	\| X86_CPUID_AMD_FEATURE_EDX_MCA
3015	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
3016	\| X86_CPUID_AMD_FEATURE_EDX_PAT
3017	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
3018	//\| RT_BIT_32(18) - reserved
3019	//\| RT_BIT_32(19) - reserved
3020	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
3021	//\| RT_BIT_32(21) - reserved
3022	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
3023	\| X86_CPUID_AMD_FEATURE_EDX_MMX
3024	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
3025	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
3026	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3027	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
3028	//\| RT_BIT_32(28) - reserved
3029	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
3030	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
3031	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
3032	;
3033	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
3034	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
3035	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
3036	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3037	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
3038	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
3039	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
3040	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
3041	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
3042	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
3043	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3044	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
3045	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
3046	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3047	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
3048	//\| RT_BIT_32(14) - reserved
3049	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
3050	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
3051	//\| RT_BIT_32(17) - reserved
3052	//\| RT_BIT_32(18) - reserved
3053	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
3054	//\| RT_BIT_32(20) - reserved
3055	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
3056	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
3057	//\| RT_BIT_32(23) - reserved
3058	//\| RT_BIT_32(24) - reserved
3059	//\| RT_BIT_32(25) - reserved
3060	//\| RT_BIT_32(26) - reserved
3061	//\| RT_BIT_32(27) - reserved
3062	//\| RT_BIT_32(28) - reserved
3063	//\| RT_BIT_32(29) - reserved
3064	//\| RT_BIT_32(30) - reserved
3065	//\| RT_BIT_32(31) - reserved
3066	;
3067	#ifdef VBOX_WITH_MULTI_CORE
3068	if ( pVM->cCpus > 1
3069	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3070	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
3071	#endif
3072
3073	if (pCpum->u8PortableCpuIdLevel > 0)
3074	{
3075	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
3076	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
3077	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
3078	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
3079	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
3080	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
3081	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
3082	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
3083	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
3084	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
3085	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
3086	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
3087	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
3088	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
3089	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
3090	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
3091
3092	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
3093	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3094	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3095	\| X86_CPUID_AMD_FEATURE_ECX_IBS
3096	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3097	\| X86_CPUID_AMD_FEATURE_ECX_WDT
3098	\| X86_CPUID_AMD_FEATURE_ECX_LWP
3099	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
3100	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
3101	\| UINT32_C(0xff964000)
3102	)));
3103	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
3104	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3105	\| RT_BIT(18)
3106	\| RT_BIT(19)
3107	\| RT_BIT(21)
3108	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
3109	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3110	\| RT_BIT(28)
3111	)));
3112	}
3113
3114	/* Force extended feature bits. */
3115	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
3116	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
3117	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
3118	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
3119	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
3120	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
3121	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
3122	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
3123	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3124	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
3125	}
3126	pExtFeatureLeaf = NULL; /* Must refetch! */
3127
3128
3129	/* Cpuid 2:
3130	* Intel: (Nondeterministic) Cache and TLB information
3131	* AMD: Reserved
3132	* VIA: Reserved
3133	* Safe to expose.
3134	*/
3135	uint32_t uSubLeaf = 0;
3136	PCPUMCPUIDLEAF pCurLeaf;
3137	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
3138	{
3139	if ((pCurLeaf->uEax & 0xff) > 1)
3140	{
3141	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
3142	pCurLeaf->uEax &= UINT32_C(0xffffff01);
3143	}
3144	uSubLeaf++;
3145	}
3146
3147	/* Cpuid 3:
3148	* Intel: EAX, EBX - reserved (transmeta uses these)
3149	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3150	* AMD: Reserved
3151	* VIA: Reserved
3152	* Safe to expose
3153	*/
3154	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3155	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3156	{
3157	uSubLeaf = 0;
3158	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3159	{
3160	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3161	if (pCpum->u8PortableCpuIdLevel > 0)
3162	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3163	uSubLeaf++;
3164	}
3165	}
3166
3167	/* Cpuid 4 + ECX:
3168	* Intel: Deterministic Cache Parameters Leaf.
3169	* AMD: Reserved
3170	* VIA: Reserved
3171	* Safe to expose, except for EAX:
3172	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3173	* Bits 31-26: Maximum number of processor cores in this physical package**
3174	* Note: These SMP values are constant regardless of ECX
3175	*/
3176	uSubLeaf = 0;
3177	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3178	{
3179	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3180	#ifdef VBOX_WITH_MULTI_CORE
3181	if ( pVM->cCpus > 1
3182	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3183	{
3184	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3185	/* One logical processor with possibly multiple cores. */
3186	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3187	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3188	}
3189	#endif
3190	uSubLeaf++;
3191	}
3192
3193	/* Cpuid 5: Monitor/mwait Leaf
3194	* Intel: ECX, EDX - reserved
3195	* EAX, EBX - Smallest and largest monitor line size
3196	* AMD: EDX - reserved
3197	* EAX, EBX - Smallest and largest monitor line size
3198	* ECX - extensions (ignored for now)
3199	* VIA: Reserved
3200	* Safe to expose
3201	*/
3202	uSubLeaf = 0;
3203	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3204	{
3205	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3206	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3207	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3208
3209	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3210	if (pConfig->enmMWaitExtensions)
3211	{
3212	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3213	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3214	it shall be part of our power management virtualization model */
3215	#if 0
3216	/* MWAIT sub C-states */
3217	pCurLeaf->uEdx =
3218	(0 << 0) /* 0 in C0 */ \|
3219	(2 << 4) /* 2 in C1 */ \|
3220	(2 << 8) /* 2 in C2 */ \|
3221	(2 << 12) /* 2 in C3 */ \|
3222	(0 << 16) /* 0 in C4 */
3223	;
3224	#endif
3225	}
3226	else
3227	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3228	uSubLeaf++;
3229	}
3230
3231	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3232	* Intel: Various stuff.
3233	* AMD: EAX, EBX, EDX - reserved.
3234	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3235	* present. Same as intel.
3236	* VIA: ??
3237	*
3238	* We clear everything here for now.
3239	*/
3240	cpumR3CpuIdZeroLeaf(pCpum, 6);
3241
3242	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3243	* EAX: Number of sub leaves.
3244	* EBX+ECX+EDX: Feature flags
3245	*
3246	* We only have documentation for one sub-leaf, so clear all other (no need
3247	* to remove them as such, just set them to zero).
3248	*
3249	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3250	* options may require adjusting (i.e. stripping what was enabled).
3251	*/
3252	uSubLeaf = 0;
3253	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3254	{
3255	switch (uSubLeaf)
3256	{
3257	case 0:
3258	{
3259	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3260	pCurLeaf->uEbx &= 0
3261	\| (pConfig->enmFsGsBase ? X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE : 0)
3262	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3263	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3264	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3265	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3266	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3267	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3268	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3269	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3270	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3271	\| (pConfig->enmInvpcid ? X86_CPUID_STEXT_FEATURE_EBX_INVPCID : 0)
3272	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3273	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3274	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3275	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3276	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3277	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3278	//\| RT_BIT(17) - reserved
3279	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3280	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3281	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3282	//\| RT_BIT(21) - reserved
3283	//\| RT_BIT(22) - reserved
3284	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3285	//\| RT_BIT(24) - reserved
3286	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3287	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3288	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3289	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3290	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3291	//\| RT_BIT(30) - reserved
3292	//\| RT_BIT(31) - reserved
3293	;
3294	pCurLeaf->uEcx &= 0
3295	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3296	;
3297	pCurLeaf->uEdx &= 0
3298	\| (pConfig->enmMdsClear ? X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR : 0)
3299	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3300	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3301	\| (pConfig->enmFlushCmdMsr ? X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD : 0)
3302	\| (pConfig->enmArchCapMsr ? X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP : 0)
3303	;
3304
3305	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3306	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3307	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3308	{
3309	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3310	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3311	}
3312
3313	if (pCpum->u8PortableCpuIdLevel > 0)
3314	{
3315	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3316	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3317	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3318	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3319	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3320	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3321	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3322	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3323	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3324	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3325	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3326	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3327	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3328	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3329	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3330	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
3331	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
3332	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
3333	}
3334
3335	/* Dependencies. */
3336	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
3337	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3338
3339	/* Force standard feature bits. */
3340	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3341	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3342	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3343	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3344	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3345	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3346	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3347	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3348	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3349	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3350	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3351	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
3352	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
3353	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3354	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3355	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
3356	break;
3357	}
3358
3359	default:
3360	/* Invalid index, all values are zero. */
3361	pCurLeaf->uEax = 0;
3362	pCurLeaf->uEbx = 0;
3363	pCurLeaf->uEcx = 0;
3364	pCurLeaf->uEdx = 0;
3365	break;
3366	}
3367	uSubLeaf++;
3368	}
3369
3370	/* Cpuid 8: Marked as reserved by Intel and AMD.
3371	* We zero this since we don't know what it may have been used for.
3372	*/
3373	cpumR3CpuIdZeroLeaf(pCpum, 8);
3374
3375	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3376	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3377	* EBX, ECX, EDX - reserved.
3378	* AMD: Reserved
3379	* VIA: ??
3380	*
3381	* We zero this.
3382	*/
3383	cpumR3CpuIdZeroLeaf(pCpum, 9);
3384
3385	/* Cpuid 0xa: Architectural Performance Monitor Features
3386	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3387	* EBX, ECX, EDX - reserved.
3388	* AMD: Reserved
3389	* VIA: ??
3390	*
3391	* We zero this, for now at least.
3392	*/
3393	cpumR3CpuIdZeroLeaf(pCpum, 10);
3394
3395	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3396	* Intel: EAX - APCI ID shift right for next level.
3397	* EBX - Factory configured cores/threads at this level.
3398	* ECX - Level number (same as input) and level type (1,2,0).
3399	* EDX - Extended initial APIC ID.
3400	* AMD: Reserved
3401	* VIA: ??
3402	*/
3403	uSubLeaf = 0;
3404	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3405	{
3406	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3407	{
3408	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3409	if (bLevelType == 1)
3410	{
3411	/* Thread level - we don't do threads at the moment. */
3412	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3413	pCurLeaf->uEbx = 1;
3414	}
3415	else if (bLevelType == 2)
3416	{
3417	/* Core level. */
3418	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3419	#ifdef VBOX_WITH_MULTI_CORE
3420	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3421	pCurLeaf->uEax++;
3422	#endif
3423	pCurLeaf->uEbx = pVM->cCpus;
3424	}
3425	else
3426	{
3427	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3428	pCurLeaf->uEax = 0;
3429	pCurLeaf->uEbx = 0;
3430	pCurLeaf->uEcx = 0;
3431	}
3432	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3433	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3434	}
3435	else
3436	{
3437	pCurLeaf->uEax = 0;
3438	pCurLeaf->uEbx = 0;
3439	pCurLeaf->uEcx = 0;
3440	pCurLeaf->uEdx = 0;
3441	}
3442	uSubLeaf++;
3443	}
3444
3445	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3446	* We zero this since we don't know what it may have been used for.
3447	*/
3448	cpumR3CpuIdZeroLeaf(pCpum, 12);
3449
3450	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3451	* ECX=0: EAX - Valid bits in XCR0[31:0].
3452	* EBX - Maximum state size as per current XCR0 value.
3453	* ECX - Maximum state size for all supported features.
3454	* EDX - Valid bits in XCR0[63:32].
3455	* ECX=1: EAX - Various X-features.
3456	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3457	* ECX - Valid bits in IA32_XSS[31:0].
3458	* EDX - Valid bits in IA32_XSS[63:32].
3459	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3460	* if the bit invalid all four registers are set to zero.
3461	* EAX - The state size for this feature.
3462	* EBX - The state byte offset of this feature.
3463	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3464	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3465	*
3466	* Clear them all as we don't currently implement extended CPU state.
3467	*/
3468	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3469	uint64_t fGuestXcr0Mask = 0;
3470	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3471	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3472	{
3473	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3474	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3475	fGuestXcr0Mask \|= XSAVE_C_YMM;
3476	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3477	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3478	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3479	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3480
3481	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3482	}
3483	pStdFeatureLeaf = NULL;
3484	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3485
3486	/* Work the sub-leaves. */
3487	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3488	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3489	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3490	{
3491	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3492	if (pCurLeaf)
3493	{
3494	if (fGuestXcr0Mask)
3495	{
3496	switch (uSubLeaf)
3497	{
3498	case 0:
3499	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3500	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3501	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3502	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3503	VERR_CPUM_IPE_1);
3504	cbXSaveMaxActual = pCurLeaf->uEcx;
3505	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3506	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3507	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3508	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3509	VERR_CPUM_IPE_2);
3510	continue;
3511	case 1:
3512	pCurLeaf->uEax &= 0;
3513	pCurLeaf->uEcx &= 0;
3514	pCurLeaf->uEdx &= 0;
3515	/** @todo what about checking ebx? */
3516	continue;
3517	default:
3518	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3519	{
3520	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3521	&& pCurLeaf->uEax > 0
3522	&& pCurLeaf->uEbx < cbXSaveMaxActual
3523	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3524	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3525	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3526	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3527	VERR_CPUM_IPE_2);
3528	AssertLogRel(!(pCurLeaf->uEcx & 1));
3529	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3530	pCurLeaf->uEdx = 0; /* it's reserved... */
3531	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3532	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3533	continue;
3534	}
3535	break;
3536	}
3537	}
3538
3539	/* Clear the leaf. */
3540	pCurLeaf->uEax = 0;
3541	pCurLeaf->uEbx = 0;
3542	pCurLeaf->uEcx = 0;
3543	pCurLeaf->uEdx = 0;
3544	}
3545	}
3546
3547	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3548	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3549	{
3550	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3551	if (pCurLeaf)
3552	{
3553	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3554	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3555	pCurLeaf->uEbx = cbXSaveMaxReport;
3556	pCurLeaf->uEcx = cbXSaveMaxReport;
3557	}
3558	}
3559
3560	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3561	* We zero this since we don't know what it may have been used for.
3562	*/
3563	cpumR3CpuIdZeroLeaf(pCpum, 14);
3564
3565	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3566	* also known as Intel Resource Director Technology (RDT) Monitoring
3567	* We zero this as we don't currently virtualize PQM.
3568	*/
3569	cpumR3CpuIdZeroLeaf(pCpum, 15);
3570
3571	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3572	* also known as Intel Resource Director Technology (RDT) Allocation
3573	* We zero this as we don't currently virtualize PQE.
3574	*/
3575	cpumR3CpuIdZeroLeaf(pCpum, 16);
3576
3577	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3578	* We zero this since we don't know what it may have been used for.
3579	*/
3580	cpumR3CpuIdZeroLeaf(pCpum, 17);
3581
3582	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3583	* We zero this as we don't currently virtualize this.
3584	*/
3585	cpumR3CpuIdZeroLeaf(pCpum, 18);
3586
3587	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3588	* We zero this since we don't know what it may have been used for.
3589	*/
3590	cpumR3CpuIdZeroLeaf(pCpum, 19);
3591
3592	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3593	* We zero this as we don't currently virtualize this.
3594	*/
3595	cpumR3CpuIdZeroLeaf(pCpum, 20);
3596
3597	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3598	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3599	* EAX - denominator (unsigned).
3600	* EBX - numerator (unsigned).
3601	* ECX, EDX - reserved.
3602	* AMD: Reserved / undefined / not implemented.
3603	* VIA: Reserved / undefined / not implemented.
3604	* We zero this as we don't currently virtualize this.
3605	*/
3606	cpumR3CpuIdZeroLeaf(pCpum, 21);
3607
3608	/* Cpuid 0x16: Processor frequency info
3609	* Intel: EAX - Core base frequency in MHz.
3610	* EBX - Core maximum frequency in MHz.
3611	* ECX - Bus (reference) frequency in MHz.
3612	* EDX - Reserved.
3613	* AMD: Reserved / undefined / not implemented.
3614	* VIA: Reserved / undefined / not implemented.
3615	* We zero this as we don't currently virtualize this.
3616	*/
3617	cpumR3CpuIdZeroLeaf(pCpum, 22);
3618
3619	/* Cpuid 0x17..0x10000000: Unknown.
3620	* We don't know these and what they mean, so remove them. */
3621	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3622	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3623
3624
3625	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3626	* We remove all these as we're a hypervisor and must provide our own.
3627	*/
3628	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3629	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3630
3631
3632	/* Cpuid 0x80000000 is harmless. */
3633
3634	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3635
3636	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3637
3638	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3639	* Safe to pass on to the guest.
3640	*
3641	* AMD: 0x800000005 L1 cache information
3642	* 0x800000006 L2/L3 cache information
3643	* Intel: 0x800000005 reserved
3644	* 0x800000006 L2 cache information
3645	* VIA: 0x800000005 TLB and L1 cache information
3646	* 0x800000006 L2 cache information
3647	*/
3648
3649	/* Cpuid 0x800000007: Advanced Power Management Information.
3650	* AMD: EAX: Processor feedback capabilities.
3651	* EBX: RAS capabilites.
3652	* ECX: Advanced power monitoring interface.
3653	* EDX: Enhanced power management capabilities.
3654	* Intel: EAX, EBX, ECX - reserved.
3655	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3656	* VIA: Reserved
3657	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3658	*/
3659	uSubLeaf = 0;
3660	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3661	{
3662	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3663	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3664	{
3665	/*
3666	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3667	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3668	* bit is now configurable.
3669	*/
3670	pCurLeaf->uEdx &= 0
3671	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3672	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3673	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3674	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3675	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3676	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3677	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3678	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3679	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3680	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3681	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3682	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3683	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3684	\| 0;
3685	}
3686	else
3687	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3688	if (!pConfig->fInvariantTsc)
3689	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3690	uSubLeaf++;
3691	}
3692
3693	/* Cpuid 0x80000008:
3694	* AMD: EBX, EDX - reserved
3695	* EAX: Virtual/Physical/Guest address Size
3696	* ECX: Number of cores + APICIdCoreIdSize
3697	* Intel: EAX: Virtual/Physical address Size
3698	* EBX, ECX, EDX - reserved
3699	* VIA: EAX: Virtual/Physical address Size
3700	* EBX, ECX, EDX - reserved
3701	*
3702	* We only expose the virtual+pysical address size to the guest atm.
3703	* On AMD we set the core count, but not the apic id stuff as we're
3704	* currently not doing the apic id assignments in a complatible manner.
3705	*/
3706	uSubLeaf = 0;
3707	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3708	{
3709	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3710	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3711	pCurLeaf->uEdx = 0; /* reserved */
3712
3713	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3714	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3715	pCurLeaf->uEcx = 0;
3716	#ifdef VBOX_WITH_MULTI_CORE
3717	if ( pVM->cCpus > 1
3718	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3719	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3720	#endif
3721	uSubLeaf++;
3722	}
3723
3724	/* Cpuid 0x80000009: Reserved
3725	* We zero this since we don't know what it may have been used for.
3726	*/
3727	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3728
3729	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
3730	* AMD: EAX - SVM revision.
3731	* EBX - Number of ASIDs.
3732	* ECX - Reserved.
3733	* EDX - SVM Feature identification.
3734	*/
3735	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3736	{
3737	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3738	if ( pExtFeatureLeaf
3739	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
3740	{
3741	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3742	if (pSvmFeatureLeaf)
3743	{
3744	pSvmFeatureLeaf->uEax = 0x1;
3745	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3746	pSvmFeatureLeaf->uEcx = 0;
3747	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3748	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3749	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3750	}
3751	else
3752	{
3753	/* Should never happen. */
3754	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
3755	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3756	}
3757	}
3758	else
3759	{
3760	/* If SVM is not supported, this is reserved, zero out. */
3761	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3762	}
3763	}
3764	else
3765	{
3766	/* Cpuid 0x8000000a: Reserved on Intel.
3767	* We zero this since we don't know what it may have been used for.
3768	*/
3769	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3770	}
3771
3772	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3773	* We clear these as we don't know what purpose they might have. */
3774	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3775	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3776
3777	/* Cpuid 0x80000019: TLB configuration
3778	* Seems to be harmless, pass them thru as is. */
3779
3780	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3781	* Strip anything we don't know what is or addresses feature we don't implement. */
3782	uSubLeaf = 0;
3783	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3784	{
3785	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3786	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3787	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3788	;
3789	pCurLeaf->uEbx = 0; /* reserved */
3790	pCurLeaf->uEcx = 0; /* reserved */
3791	pCurLeaf->uEdx = 0; /* reserved */
3792	uSubLeaf++;
3793	}
3794
3795	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3796	* Clear this as we don't currently virtualize this feature. */
3797	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3798
3799	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3800	* Clear this as we don't currently virtualize this feature. */
3801	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3802
3803	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3804	* We need to sanitize the cores per cache (EAX[25:14]).
3805	*
3806	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3807	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3808	* slightly different meaning.
3809	*/
3810	uSubLeaf = 0;
3811	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3812	{
3813	#ifdef VBOX_WITH_MULTI_CORE
3814	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3815	if (cCores > pVM->cCpus)
3816	cCores = pVM->cCpus;
3817	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3818	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3819	#else
3820	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3821	#endif
3822	uSubLeaf++;
3823	}
3824
3825	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3826	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3827	* setup, we have one compute unit with all the cores in it. Single node.
3828	*/
3829	uSubLeaf = 0;
3830	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3831	{
3832	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3833	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3834	{
3835	#ifdef VBOX_WITH_MULTI_CORE
3836	pCurLeaf->uEbx = pVM->cCpus < 0x100
3837	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3838	#else
3839	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3840	#endif
3841	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3842	}
3843	else
3844	{
3845	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3846	pCurLeaf->uEbx = 0; /* Reserved. */
3847	pCurLeaf->uEcx = 0; /* Reserved. */
3848	}
3849	pCurLeaf->uEdx = 0; /* Reserved. */
3850	uSubLeaf++;
3851	}
3852
3853	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3854	* We don't know these and what they mean, so remove them. */
3855	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3856	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3857
3858	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3859	* Just pass it thru for now. */
3860
3861	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3862	* Just pass it thru for now. */
3863
3864	/* Cpuid 0xc0000000: Centaur stuff.
3865	* Harmless, pass it thru. */
3866
3867	/* Cpuid 0xc0000001: Centaur features.
3868	* VIA: EAX - Family, model, stepping.
3869	* EDX - Centaur extended feature flags. Nothing interesting, except may
3870	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3871	* EBX, ECX - reserved.
3872	* We keep EAX but strips the rest.
3873	*/
3874	uSubLeaf = 0;
3875	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3876	{
3877	pCurLeaf->uEbx = 0;
3878	pCurLeaf->uEcx = 0;
3879	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3880	uSubLeaf++;
3881	}
3882
3883	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3884	* We only have fixed stale values, but should be harmless. */
3885
3886	/* Cpuid 0xc0000003: Reserved.
3887	* We zero this since we don't know what it may have been used for.
3888	*/
3889	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3890
3891	/* Cpuid 0xc0000004: Centaur Performance Info.
3892	* We only have fixed stale values, but should be harmless. */
3893
3894
3895	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3896	* We don't know these and what they mean, so remove them. */
3897	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3898	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3899
3900	return VINF_SUCCESS;
3901	#undef PORTABLE_DISABLE_FEATURE_BIT
3902	#undef PORTABLE_CLEAR_BITS_WHEN
3903	}
3904
3905
3906	/**
3907	* Reads a value in /CPUM/IsaExts/ node.
3908	*
3909	* @returns VBox status code (error message raised).
3910	* @param pVM The cross context VM structure. (For errors.)
3911	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3912	* @param pszValueName The value / extension name.
3913	* @param penmValue Where to return the choice.
3914	* @param enmDefault The default choice.
3915	*/
3916	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3917	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3918	{
3919	/*
3920	* Try integer encoding first.
3921	*/
3922	uint64_t uValue;
3923	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3924	if (RT_SUCCESS(rc))
3925	switch (uValue)
3926	{
3927	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3928	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3929	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3930	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3931	default:
3932	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3933	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3934	pszValueName, uValue);
3935	}
3936	/*
3937	* If missing, use default.
3938	*/
3939	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3940	*penmValue = enmDefault;
3941	else
3942	{
3943	if (rc == VERR_CFGM_NOT_INTEGER)
3944	{
3945	/*
3946	* Not an integer, try read it as a string.
3947	*/
3948	char szValue[32];
3949	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3950	if (RT_SUCCESS(rc))
3951	{
3952	RTStrToLower(szValue);
3953	size_t cchValue = strlen(szValue);
3954	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3955	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3956	*penmValue = CPUMISAEXTCFG_DISABLED;
3957	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3958	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3959	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3960	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3961	else if (EQ("portable"))
3962	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3963	else if (EQ("default") \|\| EQ("def"))
3964	*penmValue = enmDefault;
3965	else
3966	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3967	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3968	pszValueName, uValue);
3969	#undef EQ
3970	}
3971	}
3972	if (RT_FAILURE(rc))
3973	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3974	}
3975	return VINF_SUCCESS;
3976	}
3977
3978
3979	/**
3980	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3981	*
3982	* @returns VBox status code (error message raised).
3983	* @param pVM The cross context VM structure. (For errors.)
3984	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3985	* @param pszValueName The value / extension name.
3986	* @param penmValue Where to return the choice.
3987	* @param enmDefault The default choice.
3988	* @param fAllowed Allowed choice. Applied both to the result and to
3989	* the default value.
3990	*/
3991	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3992	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3993	{
3994	int rc;
3995	if (fAllowed)
3996	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3997	else
3998	{
3999	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
4000	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
4001	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
4002	*penmValue = CPUMISAEXTCFG_DISABLED;
4003	}
4004	return rc;
4005	}
4006
4007
4008	/**
4009	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
4010	*
4011	* @returns VBox status code (error message raised).
4012	* @param pVM The cross context VM structure. (For errors.)
4013	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4014	* @param pCpumCfg The /CPUM node (can be NULL).
4015	* @param pszValueName The value / extension name.
4016	* @param penmValue Where to return the choice.
4017	* @param enmDefault The default choice.
4018	*/
4019	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
4020	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
4021	{
4022	if (CFGMR3Exists(pCpumCfg, pszValueName))
4023	{
4024	if (!CFGMR3Exists(pIsaExts, pszValueName))
4025	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
4026	else
4027	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
4028	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
4029	pszValueName, pszValueName);
4030
4031	bool fLegacy;
4032	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
4033	if (RT_SUCCESS(rc))
4034	{
4035	*penmValue = fLegacy;
4036	return VINF_SUCCESS;
4037	}
4038	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
4039	}
4040
4041	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4042	}
4043
4044
4045	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
4046	{
4047	int rc;
4048
4049	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
4050	* When non-zero CPUID features that could cause portability issues will be
4051	* stripped. The higher the value the more features gets stripped. Higher
4052	* values should only be used when older CPUs are involved since it may
4053	* harm performance and maybe also cause problems with specific guests. */
4054	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
4055	AssertLogRelRCReturn(rc, rc);
4056
4057	/** @cfgm{/CPUM/GuestCpuName, string}
4058	* The name of the CPU we're to emulate. The default is the host CPU.
4059	* Note! CPUs other than "host" one is currently unsupported. */
4060	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
4061	AssertLogRelRCReturn(rc, rc);
4062
4063	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
4064	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
4065	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
4066	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
4067	*/
4068	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
4069	AssertLogRelRCReturn(rc, rc);
4070
4071	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
4072	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
4073	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
4074	* 64-bit linux guests which assume the presence of AMD performance counters
4075	* that we do not virtualize.
4076	*/
4077	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
4078	AssertLogRelRCReturn(rc, rc);
4079
4080	/** @cfgm{/CPUM/ForceVme, boolean, false}
4081	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
4082	* By default the flag is passed thru as is from the host CPU, except
4083	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
4084	* guests and DOS boxes in general.
4085	*/
4086	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
4087	AssertLogRelRCReturn(rc, rc);
4088
4089	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
4090	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
4091	* probably going to be a temporary hack, so don't depend on this.
4092	* The 1st byte of the value is the stepping, the 2nd byte value is the model
4093	* number and the 3rd byte value is the family, and the 4th value must be zero.
4094	*/
4095	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
4096	AssertLogRelRCReturn(rc, rc);
4097
4098	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
4099	* The last standard leaf to keep. The actual last value that is stored in EAX
4100	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
4101	* removed. (This works independently of and differently from NT4LeafLimit.)
4102	* The default is usually set to what we're able to reasonably sanitize.
4103	*/
4104	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
4105	AssertLogRelRCReturn(rc, rc);
4106
4107	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
4108	* The last extended leaf to keep. The actual last value that is stored in EAX
4109	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
4110	* leaf are removed. The default is set to what we're able to sanitize.
4111	*/
4112	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
4113	AssertLogRelRCReturn(rc, rc);
4114
4115	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
4116	* The last extended leaf to keep. The actual last value that is stored in EAX
4117	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
4118	* leaf are removed. The default is set to what we're able to sanitize.
4119	*/
4120	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
4121	AssertLogRelRCReturn(rc, rc);
4122
4123	bool fQueryNestedHwvirt = false;
4124	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4125	fQueryNestedHwvirt \|= RT_BOOL(pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD);
4126	#endif
4127	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4128	fQueryNestedHwvirt \|= RT_BOOL( pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
4129	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA);
4130	#endif
4131	if (fQueryNestedHwvirt)
4132	{
4133	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
4134	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
4135	* The default is false, and when enabled requires a 64-bit CPU with support for
4136	* nested-paging and AMD-V or unrestricted guest mode.
4137	*/
4138	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
4139	AssertLogRelRCReturn(rc, rc);
4140	if ( pConfig->fNestedHWVirt
4141	&& !fNestedPagingAndFullGuestExec)
4142	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4143	"Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
4144
4145	/** @todo Think about enabling this later with NEM/KVM. */
4146	if ( pConfig->fNestedHWVirt
4147	&& VM_IS_NEM_ENABLED(pVM))
4148	{
4149	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
4150	pConfig->fNestedHWVirt = false;
4151	}
4152	}
4153
4154	/*
4155	* Instruction Set Architecture (ISA) Extensions.
4156	*/
4157	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
4158	if (pIsaExts)
4159	{
4160	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
4161	"CMPXCHG16B"
4162	"\|MONITOR"
4163	"\|MWaitExtensions"
4164	"\|SSE4.1"
4165	"\|SSE4.2"
4166	"\|XSAVE"
4167	"\|AVX"
4168	"\|AVX2"
4169	"\|AESNI"
4170	"\|PCLMUL"
4171	"\|POPCNT"
4172	"\|MOVBE"
4173	"\|RDRAND"
4174	"\|RDSEED"
4175	"\|CLFLUSHOPT"
4176	"\|FSGSBASE"
4177	"\|PCID"
4178	"\|INVPCID"
4179	"\|FlushCmdMsr"
4180	"\|ABM"
4181	"\|SSE4A"
4182	"\|MISALNSSE"
4183	"\|3DNOWPRF"
4184	"\|AXMMX"
4185	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
4186	if (RT_FAILURE(rc))
4187	return rc;
4188	}
4189
4190	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
4191	* Expose CMPXCHG16B to the guest if supported by the host. For the time
4192	* being the default is to only do this for VMs with nested paging and AMD-V or
4193	* unrestricted guest mode.
4194	*/
4195	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
4196	AssertLogRelRCReturn(rc, rc);
4197
4198	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4199	* Expose MONITOR/MWAIT instructions to the guest.
4200	*/
4201	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4202	AssertLogRelRCReturn(rc, rc);
4203
4204	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4205	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4206	* break on interrupt feature (bit 1).
4207	*/
4208	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4209	AssertLogRelRCReturn(rc, rc);
4210
4211	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4212	* Expose SSE4.1 to the guest if available.
4213	*/
4214	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4215	AssertLogRelRCReturn(rc, rc);
4216
4217	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4218	* Expose SSE4.2 to the guest if available.
4219	*/
4220	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4221	AssertLogRelRCReturn(rc, rc);
4222
4223	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4224	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4225	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor;
4226	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4227
4228	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4229	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4230	* default is to only expose this to VMs with nested paging and AMD-V or
4231	* unrestricted guest execution mode. Not possible to force this one without
4232	* host support at the moment.
4233	*/
4234	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4235	fMayHaveXSave /fAllowed/);
4236	AssertLogRelRCReturn(rc, rc);
4237
4238	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4239	* Expose the AVX instruction set extensions to the guest if available and
4240	* XSAVE is exposed too. For the time being the default is to only expose this
4241	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4242	*/
4243	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4244	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4245	AssertLogRelRCReturn(rc, rc);
4246
4247	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4248	* Expose the AVX2 instruction set extensions to the guest if available and
4249	* XSAVE is exposed too. For the time being the default is to only expose this
4250	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4251	*/
4252	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4253	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4254	AssertLogRelRCReturn(rc, rc);
4255
4256	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4257	* Whether to expose the AES instructions to the guest. For the time being the
4258	* default is to only do this for VMs with nested paging and AMD-V or
4259	* unrestricted guest mode.
4260	*/
4261	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4262	AssertLogRelRCReturn(rc, rc);
4263
4264	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4265	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4266	* being the default is to only do this for VMs with nested paging and AMD-V or
4267	* unrestricted guest mode.
4268	*/
4269	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4270	AssertLogRelRCReturn(rc, rc);
4271
4272	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4273	* Whether to expose the POPCNT instructions to the guest. For the time
4274	* being the default is to only do this for VMs with nested paging and AMD-V or
4275	* unrestricted guest mode.
4276	*/
4277	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4278	AssertLogRelRCReturn(rc, rc);
4279
4280	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4281	* Whether to expose the MOVBE instructions to the guest. For the time
4282	* being the default is to only do this for VMs with nested paging and AMD-V or
4283	* unrestricted guest mode.
4284	*/
4285	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4286	AssertLogRelRCReturn(rc, rc);
4287
4288	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4289	* Whether to expose the RDRAND instructions to the guest. For the time being
4290	* the default is to only do this for VMs with nested paging and AMD-V or
4291	* unrestricted guest mode.
4292	*/
4293	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4294	AssertLogRelRCReturn(rc, rc);
4295
4296	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4297	* Whether to expose the RDSEED instructions to the guest. For the time being
4298	* the default is to only do this for VMs with nested paging and AMD-V or
4299	* unrestricted guest mode.
4300	*/
4301	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4302	AssertLogRelRCReturn(rc, rc);
4303
4304	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4305	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4306	* being the default is to only do this for VMs with nested paging and AMD-V or
4307	* unrestricted guest mode.
4308	*/
4309	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4310	AssertLogRelRCReturn(rc, rc);
4311
4312	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4313	* Whether to expose the read/write FSGSBASE instructions to the guest.
4314	*/
4315	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4316	AssertLogRelRCReturn(rc, rc);
4317
4318	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4319	* Whether to expose the PCID feature to the guest.
4320	*/
4321	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4322	AssertLogRelRCReturn(rc, rc);
4323
4324	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4325	* Whether to expose the INVPCID instruction to the guest.
4326	*/
4327	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4328	AssertLogRelRCReturn(rc, rc);
4329
4330	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
4331	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
4332	*/
4333	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4334	AssertLogRelRCReturn(rc, rc);
4335
4336	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
4337	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
4338	* the guest. Requires FlushCmdMsr to be present too.
4339	*/
4340	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4341	AssertLogRelRCReturn(rc, rc);
4342
4343	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
4344	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
4345	*/
4346	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4347	AssertLogRelRCReturn(rc, rc);
4348
4349
4350	/* AMD: */
4351
4352	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4353	* Whether to expose the AMD ABM instructions to the guest. For the time
4354	* being the default is to only do this for VMs with nested paging and AMD-V or
4355	* unrestricted guest mode.
4356	*/
4357	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4358	AssertLogRelRCReturn(rc, rc);
4359
4360	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4361	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4362	* being the default is to only do this for VMs with nested paging and AMD-V or
4363	* unrestricted guest mode.
4364	*/
4365	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4366	AssertLogRelRCReturn(rc, rc);
4367
4368	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4369	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4370	* the time being the default is to only do this for VMs with nested paging and
4371	* AMD-V or unrestricted guest mode.
4372	*/
4373	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4374	AssertLogRelRCReturn(rc, rc);
4375
4376	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4377	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4378	* For the time being the default is to only do this for VMs with nested paging
4379	* and AMD-V or unrestricted guest mode.
4380	*/
4381	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4382	AssertLogRelRCReturn(rc, rc);
4383
4384	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4385	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4386	* the default is to only do this for VMs with nested paging and AMD-V or
4387	* unrestricted guest mode.
4388	*/
4389	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4390	AssertLogRelRCReturn(rc, rc);
4391
4392	return VINF_SUCCESS;
4393	}
4394
4395
4396	/**
4397	* Initializes the emulated CPU's CPUID & MSR information.
4398	*
4399	* @returns VBox status code.
4400	* @param pVM The cross context VM structure.
4401	* @param pHostMsrs Pointer to the host MSRs.
4402	*/
4403	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
4404	{
4405	Assert(pHostMsrs);
4406
4407	PCPUM pCpum = &pVM->cpum.s;
4408	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4409
4410	/*
4411	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4412	* on construction and manage everything from here on.
4413	*/
4414	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4415	{
4416	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4417	pVCpu->cpum.s.fCpuIdApicFeatureVisible = true;
4418	}
4419
4420	/*
4421	* Read the configuration.
4422	*/
4423	CPUMCPUIDCONFIG Config;
4424	RT_ZERO(Config);
4425
4426	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4427	AssertRCReturn(rc, rc);
4428
4429	/*
4430	* Get the guest CPU data from the database and/or the host.
4431	*
4432	* The CPUID and MSRs are currently living on the regular heap to avoid
4433	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4434	* API for the hyper heap). This means special cleanup considerations.
4435	*/
4436	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4437	if (RT_FAILURE(rc))
4438	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4439	? VMSetError(pVM, rc, RT_SRC_POS,
4440	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4441	: rc;
4442
4443	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4444	{
4445	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4446	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4447	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4448	}
4449	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4450
4451	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4452	* Overrides the guest MSRs.
4453	*/
4454	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4455
4456	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4457	* Overrides the CPUID leaf values (from the host CPU usually) used for
4458	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4459	* values when moving a VM to a different machine. Another use is restricting
4460	* (or extending) the feature set exposed to the guest. */
4461	if (RT_SUCCESS(rc))
4462	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4463
4464	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4465	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4466	"Found unsupported configuration node '/CPUM/CPUID/'. "
4467	"Please use IMachine::setCPUIDLeaf() instead.");
4468
4469	CPUMMSRS GuestMsrs;
4470	RT_ZERO(GuestMsrs);
4471
4472	/*
4473	* Pre-explode the CPUID info.
4474	*/
4475	if (RT_SUCCESS(rc))
4476	{
4477	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
4478	&pCpum->GuestFeatures);
4479	}
4480
4481	/*
4482	* Sanitize the cpuid information passed on to the guest.
4483	*/
4484	if (RT_SUCCESS(rc))
4485	{
4486	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4487	if (RT_SUCCESS(rc))
4488	{
4489	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4490	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4491	}
4492	}
4493
4494	/*
4495	* Setup MSRs introduced in microcode updates or that are otherwise not in
4496	* the CPU profile, but are advertised in the CPUID info we just sanitized.
4497	*/
4498	if (RT_SUCCESS(rc))
4499	rc = cpumR3MsrReconcileWithCpuId(pVM);
4500	/*
4501	* MSR fudging.
4502	*/
4503	if (RT_SUCCESS(rc))
4504	{
4505	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4506	* Fudges some common MSRs if not present in the selected CPU database entry.
4507	* This is for trying to keep VMs running when moved between different hosts
4508	* and different CPU vendors. */
4509	bool fEnable;
4510	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4511	if (RT_SUCCESS(rc) && fEnable)
4512	{
4513	rc = cpumR3MsrApplyFudge(pVM);
4514	AssertLogRelRC(rc);
4515	}
4516	}
4517	if (RT_SUCCESS(rc))
4518	{
4519	/*
4520	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4521	* guest CPU features again.
4522	*/
4523	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4524	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4525	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
4526	RTMemFree(pvFree);
4527
4528	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4529	int rc2 = MMHyperDupMem(pVM, pvFree,
4530	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4531	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4532	RTMemFree(pvFree);
4533	AssertLogRelRCReturn(rc1, rc1);
4534	AssertLogRelRCReturn(rc2, rc2);
4535
4536	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4537
4538	/*
4539	* Finally, initialize guest VMX MSRs.
4540	*
4541	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
4542	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
4543	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
4544	*/
4545	if (pVM->cpum.s.GuestFeatures.fVmx)
4546	{
4547	Assert(Config.fNestedHWVirt);
4548	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
4549
4550	/* Copy MSRs to all VCPUs */
4551	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
4552	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4553	{
4554	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4555	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
4556	}
4557	}
4558
4559	/*
4560	* Some more configuration that we're applying at the end of everything
4561	* via the CPUMR3SetGuestCpuIdFeature API.
4562	*/
4563
4564	/* Check if PAE was explicitely enabled by the user. */
4565	bool fEnable;
4566	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4567	AssertRCReturn(rc, rc);
4568	if (fEnable)
4569	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4570
4571	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4572	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4573	AssertRCReturn(rc, rc);
4574	if (fEnable)
4575	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4576
4577	/* Check if speculation control is enabled. */
4578	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4579	AssertRCReturn(rc, rc);
4580	if (fEnable)
4581	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4582
4583	return VINF_SUCCESS;
4584	}
4585
4586	/*
4587	* Failed before switching to hyper heap.
4588	*/
4589	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4590	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4591	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4592	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4593	return rc;
4594	}
4595
4596
4597	/**
4598	* Sets a CPUID feature bit during VM initialization.
4599	*
4600	* Since the CPUID feature bits are generally related to CPU features, other
4601	* CPUM configuration like MSRs can also be modified by calls to this API.
4602	*
4603	* @param pVM The cross context VM structure.
4604	* @param enmFeature The feature to set.
4605	*/
4606	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4607	{
4608	PCPUMCPUIDLEAF pLeaf;
4609	PCPUMMSRRANGE pMsrRange;
4610
4611	switch (enmFeature)
4612	{
4613	/*
4614	* Set the APIC bit in both feature masks.
4615	*/
4616	case CPUMCPUIDFEATURE_APIC:
4617	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4618	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4619	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4620
4621	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4622	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4623	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4624
4625	pVM->cpum.s.GuestFeatures.fApic = 1;
4626
4627	/* Make sure we've got the APICBASE MSR present. */
4628	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4629	if (!pMsrRange)
4630	{
4631	static CPUMMSRRANGE const s_ApicBase =
4632	{
4633	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4634	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4635	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4636	/.szName = / "IA32_APIC_BASE"
4637	};
4638	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4639	AssertLogRelRC(rc);
4640	}
4641
4642	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4643	break;
4644
4645	/*
4646	* Set the x2APIC bit in the standard feature mask.
4647	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4648	*/
4649	case CPUMCPUIDFEATURE_X2APIC:
4650	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4651	if (pLeaf)
4652	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4653	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4654
4655	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4656	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4657	if (pMsrRange)
4658	{
4659	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4660	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4661	}
4662
4663	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4664	break;
4665
4666	/*
4667	* Set the sysenter/sysexit bit in the standard feature mask.
4668	* Assumes the caller knows what it's doing! (host must support these)
4669	*/
4670	case CPUMCPUIDFEATURE_SEP:
4671	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4672	{
4673	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4674	return;
4675	}
4676
4677	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4678	if (pLeaf)
4679	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4680	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4681	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4682	break;
4683
4684	/*
4685	* Set the syscall/sysret bit in the extended feature mask.
4686	* Assumes the caller knows what it's doing! (host must support these)
4687	*/
4688	case CPUMCPUIDFEATURE_SYSCALL:
4689	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4690	if ( !pLeaf
4691	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4692	{
4693	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4694	return;
4695	}
4696
4697	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4698	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4699	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4700	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4701	break;
4702
4703	/*
4704	* Set the PAE bit in both feature masks.
4705	* Assumes the caller knows what it's doing! (host must support these)
4706	*/
4707	case CPUMCPUIDFEATURE_PAE:
4708	if (!pVM->cpum.s.HostFeatures.fPae)
4709	{
4710	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4711	return;
4712	}
4713
4714	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4715	if (pLeaf)
4716	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4717
4718	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4719	if ( pLeaf
4720	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4721	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4722
4723	pVM->cpum.s.GuestFeatures.fPae = 1;
4724	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4725	break;
4726
4727	/*
4728	* Set the LONG MODE bit in the extended feature mask.
4729	* Assumes the caller knows what it's doing! (host must support these)
4730	*/
4731	case CPUMCPUIDFEATURE_LONG_MODE:
4732	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4733	if ( !pLeaf
4734	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4735	{
4736	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4737	return;
4738	}
4739
4740	/* Valid for both Intel and AMD. */
4741	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4742	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4743	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
4744	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4745	break;
4746
4747	/*
4748	* Set the NX/XD bit in the extended feature mask.
4749	* Assumes the caller knows what it's doing! (host must support these)
4750	*/
4751	case CPUMCPUIDFEATURE_NX:
4752	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4753	if ( !pLeaf
4754	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4755	{
4756	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4757	return;
4758	}
4759
4760	/* Valid for both Intel and AMD. */
4761	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4762	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4763	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4764	break;
4765
4766
4767	/*
4768	* Set the LAHF/SAHF support in 64-bit mode.
4769	* Assumes the caller knows what it's doing! (host must support this)
4770	*/
4771	case CPUMCPUIDFEATURE_LAHF:
4772	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4773	if ( !pLeaf
4774	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4775	{
4776	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4777	return;
4778	}
4779
4780	/* Valid for both Intel and AMD. */
4781	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4782	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4783	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4784	break;
4785
4786	/*
4787	* Set the page attribute table bit. This is alternative page level
4788	* cache control that doesn't much matter when everything is
4789	* virtualized, though it may when passing thru device memory.
4790	*/
4791	case CPUMCPUIDFEATURE_PAT:
4792	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4793	if (pLeaf)
4794	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4795
4796	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4797	if ( pLeaf
4798	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4799	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4800
4801	pVM->cpum.s.GuestFeatures.fPat = 1;
4802	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4803	break;
4804
4805	/*
4806	* Set the RDTSCP support bit.
4807	* Assumes the caller knows what it's doing! (host must support this)
4808	*/
4809	case CPUMCPUIDFEATURE_RDTSCP:
4810	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4811	if ( !pLeaf
4812	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4813	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4814	{
4815	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4816	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4817	return;
4818	}
4819
4820	/* Valid for both Intel and AMD. */
4821	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4822	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4823	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4824	break;
4825
4826	/*
4827	* Set the Hypervisor Present bit in the standard feature mask.
4828	*/
4829	case CPUMCPUIDFEATURE_HVP:
4830	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4831	if (pLeaf)
4832	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4833	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4834	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4835	break;
4836
4837	/*
4838	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4839	* This currently includes the Present bit and MWAITBREAK bit as well.
4840	*/
4841	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4842	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4843	if ( !pLeaf
4844	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4845	{
4846	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4847	return;
4848	}
4849
4850	/* Valid for both Intel and AMD. */
4851	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4852	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4853	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4854	break;
4855
4856	/*
4857	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
4858	* on Intel CPUs, and different on AMDs.
4859	*/
4860	case CPUMCPUIDFEATURE_SPEC_CTRL:
4861	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4862	{
4863	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4864	if ( !pLeaf
4865	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
4866	{
4867	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4868	return;
4869	}
4870
4871	/* The feature can be enabled. Let's see what we can actually do. */
4872	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4873
4874	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4875	if (pVM->cpum.s.HostFeatures.fIbrs)
4876	{
4877	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4878	pVM->cpum.s.GuestFeatures.fIbrs = 1;
4879	if (pVM->cpum.s.HostFeatures.fStibp)
4880	{
4881	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4882	pVM->cpum.s.GuestFeatures.fStibp = 1;
4883	}
4884
4885	/* Make sure we have the speculation control MSR... */
4886	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4887	if (!pMsrRange)
4888	{
4889	static CPUMMSRRANGE const s_SpecCtrl =
4890	{
4891	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
4892	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
4893	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4894	/.szName = / "IA32_SPEC_CTRL"
4895	};
4896	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4897	AssertLogRelRC(rc);
4898	}
4899
4900	/* ... and the predictor command MSR. */
4901	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
4902	if (!pMsrRange)
4903	{
4904	/** @todo incorrect fWrGpMask. */
4905	static CPUMMSRRANGE const s_SpecCtrl =
4906	{
4907	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
4908	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
4909	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4910	/.szName = / "IA32_PRED_CMD"
4911	};
4912	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4913	AssertLogRelRC(rc);
4914	}
4915
4916	}
4917
4918	if (pVM->cpum.s.HostFeatures.fArchCap)
4919	{
4920	/* Install the architectural capabilities MSR. */
4921	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
4922	if (!pMsrRange)
4923	{
4924	static CPUMMSRRANGE const s_ArchCaps =
4925	{
4926	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
4927	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
4928	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
4929	/.szName = / "IA32_ARCH_CAPABILITIES"
4930	};
4931	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
4932	AssertLogRelRC(rc);
4933	}
4934	}
4935
4936	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
4937	}
4938	else if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4939	{
4940	/* The precise details of AMD's implementation are not yet clear. */
4941	}
4942	break;
4943
4944	default:
4945	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4946	break;
4947	}
4948
4949	/** @todo can probably kill this as this API is now init time only... */
4950	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4951	{
4952	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4953	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4954	}
4955	}
4956
4957
4958	/**
4959	* Queries a CPUID feature bit.
4960	*
4961	* @returns boolean for feature presence
4962	* @param pVM The cross context VM structure.
4963	* @param enmFeature The feature to query.
4964	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4965	*/
4966	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4967	{
4968	switch (enmFeature)
4969	{
4970	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4971	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4972	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4973	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4974	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4975	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4976	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4977	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4978	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4979	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4980	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4981	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4982	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
4983
4984	case CPUMCPUIDFEATURE_INVALID:
4985	case CPUMCPUIDFEATURE_32BIT_HACK:
4986	break;
4987	}
4988	AssertFailed();
4989	return false;
4990	}
4991
4992
4993	/**
4994	* Clears a CPUID feature bit.
4995	*
4996	* @param pVM The cross context VM structure.
4997	* @param enmFeature The feature to clear.
4998	*
4999	* @deprecated Probably better to default the feature to disabled and only allow
5000	* setting (enabling) it during construction.
5001	*/
5002	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5003	{
5004	PCPUMCPUIDLEAF pLeaf;
5005	switch (enmFeature)
5006	{
5007	case CPUMCPUIDFEATURE_APIC:
5008	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
5009	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5010	if (pLeaf)
5011	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
5012
5013	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5014	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
5015	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
5016
5017	pVM->cpum.s.GuestFeatures.fApic = 0;
5018	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
5019	break;
5020
5021	case CPUMCPUIDFEATURE_X2APIC:
5022	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
5023	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5024	if (pLeaf)
5025	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
5026	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
5027	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
5028	break;
5029
5030	case CPUMCPUIDFEATURE_PAE:
5031	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5032	if (pLeaf)
5033	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
5034
5035	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5036	if ( pLeaf
5037	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
5038	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
5039
5040	pVM->cpum.s.GuestFeatures.fPae = 0;
5041	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
5042	break;
5043
5044	case CPUMCPUIDFEATURE_PAT:
5045	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5046	if (pLeaf)
5047	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
5048
5049	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5050	if ( pLeaf
5051	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
5052	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
5053
5054	pVM->cpum.s.GuestFeatures.fPat = 0;
5055	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
5056	break;
5057
5058	case CPUMCPUIDFEATURE_LONG_MODE:
5059	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5060	if (pLeaf)
5061	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
5062	pVM->cpum.s.GuestFeatures.fLongMode = 0;
5063	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
5064	break;
5065
5066	case CPUMCPUIDFEATURE_LAHF:
5067	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5068	if (pLeaf)
5069	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
5070	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
5071	break;
5072
5073	case CPUMCPUIDFEATURE_RDTSCP:
5074	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5075	if (pLeaf)
5076	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
5077	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
5078	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
5079	break;
5080
5081	case CPUMCPUIDFEATURE_HVP:
5082	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5083	if (pLeaf)
5084	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
5085	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
5086	break;
5087
5088	case CPUMCPUIDFEATURE_MWAIT_EXTS:
5089	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
5090	if (pLeaf)
5091	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
5092	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
5093	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
5094	break;
5095
5096	case CPUMCPUIDFEATURE_SPEC_CTRL:
5097	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
5098	if (pLeaf)
5099	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
5100	pVM->cpum.s.GuestFeatures.fSpeculationControl = 0;
5101	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
5102	break;
5103
5104	default:
5105	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5106	break;
5107	}
5108
5109	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5110	{
5111	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5112	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5113	}
5114	}
5115
5116
5117
5118	/*
5119	*
5120	*
5121	* Saved state related code.
5122	* Saved state related code.
5123	* Saved state related code.
5124	*
5125	*
5126	*/
5127
5128	/**
5129	* Called both in pass 0 and the final pass.
5130	*
5131	* @param pVM The cross context VM structure.
5132	* @param pSSM The saved state handle.
5133	*/
5134	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
5135	{
5136	/*
5137	* Save all the CPU ID leaves.
5138	*/
5139	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
5140	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5141	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
5142	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5143
5144	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5145
5146	/*
5147	* Save a good portion of the raw CPU IDs as well as they may come in
5148	* handy when validating features for raw mode.
5149	*/
5150	CPUMCPUID aRawStd[16];
5151	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
5152	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5153	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
5154	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
5155
5156	CPUMCPUID aRawExt[32];
5157	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
5158	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5159	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
5160	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
5161	}
5162
5163
5164	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5165	{
5166	uint32_t cCpuIds;
5167	int rc = SSMR3GetU32(pSSM, &cCpuIds);
5168	if (RT_SUCCESS(rc))
5169	{
5170	if (cCpuIds < 64)
5171	{
5172	for (uint32_t i = 0; i < cCpuIds; i++)
5173	{
5174	CPUMCPUID CpuId;
5175	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
5176	if (RT_FAILURE(rc))
5177	break;
5178
5179	CPUMCPUIDLEAF NewLeaf;
5180	NewLeaf.uLeaf = uBase + i;
5181	NewLeaf.uSubLeaf = 0;
5182	NewLeaf.fSubLeafMask = 0;
5183	NewLeaf.uEax = CpuId.uEax;
5184	NewLeaf.uEbx = CpuId.uEbx;
5185	NewLeaf.uEcx = CpuId.uEcx;
5186	NewLeaf.uEdx = CpuId.uEdx;
5187	NewLeaf.fFlags = 0;
5188	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
5189	}
5190	}
5191	else
5192	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5193	}
5194	if (RT_FAILURE(rc))
5195	{
5196	RTMemFree(*ppaLeaves);
5197	*ppaLeaves = NULL;
5198	*pcLeaves = 0;
5199	}
5200	return rc;
5201	}
5202
5203
5204	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5205	{
5206	*ppaLeaves = NULL;
5207	*pcLeaves = 0;
5208
5209	int rc;
5210	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
5211	{
5212	/*
5213	* The new format. Starts by declaring the leave size and count.
5214	*/
5215	uint32_t cbLeaf;
5216	SSMR3GetU32(pSSM, &cbLeaf);
5217	uint32_t cLeaves;
5218	rc = SSMR3GetU32(pSSM, &cLeaves);
5219	if (RT_SUCCESS(rc))
5220	{
5221	if (cbLeaf == sizeof(**ppaLeaves))
5222	{
5223	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
5224	{
5225	/*
5226	* Load the leaves one by one.
5227	*
5228	* The uPrev stuff is a kludge for working around a week worth of bad saved
5229	* states during the CPUID revamp in March 2015. We saved too many leaves
5230	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
5231	* garbage entires at the end of the array when restoring. We also had
5232	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
5233	* this kludge doesn't deal correctly with that, but who cares...
5234	*/
5235	uint32_t uPrev = 0;
5236	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
5237	{
5238	CPUMCPUIDLEAF Leaf;
5239	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5240	if (RT_SUCCESS(rc))
5241	{
5242	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5243	\|\| Leaf.uLeaf >= uPrev)
5244	{
5245	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5246	uPrev = Leaf.uLeaf;
5247	}
5248	else
5249	uPrev = UINT32_MAX;
5250	}
5251	}
5252	}
5253	else
5254	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5255	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5256	}
5257	else
5258	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5259	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5260	}
5261	}
5262	else
5263	{
5264	/*
5265	* The old format with its three inflexible arrays.
5266	*/
5267	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5268	if (RT_SUCCESS(rc))
5269	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5270	if (RT_SUCCESS(rc))
5271	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5272	if (RT_SUCCESS(rc))
5273	{
5274	/*
5275	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5276	*/
5277	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5278	if ( pLeaf
5279	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5280	{
5281	CPUMCPUIDLEAF Leaf;
5282	Leaf.uLeaf = 4;
5283	Leaf.fSubLeafMask = UINT32_MAX;
5284	Leaf.uSubLeaf = 0;
5285	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5286	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5287	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5288	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5289	\| UINT32_C(63); /* system coherency line size - 1 */
5290	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5291	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5292	\| (UINT32_C(1) << 5) /* cache level */
5293	\| UINT32_C(1); /* cache type (data) */
5294	Leaf.fFlags = 0;
5295	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5296	if (RT_SUCCESS(rc))
5297	{
5298	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5299	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5300	}
5301	if (RT_SUCCESS(rc))
5302	{
5303	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5304	Leaf.uEcx = 4095; /* sets - 1 */
5305	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5306	Leaf.uEbx \|= UINT32_C(23) << 22;
5307	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5308	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5309	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5310	Leaf.uEax \|= UINT32_C(2) << 5;
5311	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5312	}
5313	}
5314	}
5315	}
5316	return rc;
5317	}
5318
5319
5320	/**
5321	* Loads the CPU ID leaves saved by pass 0, inner worker.
5322	*
5323	* @returns VBox status code.
5324	* @param pVM The cross context VM structure.
5325	* @param pSSM The saved state handle.
5326	* @param uVersion The format version.
5327	* @param paLeaves Guest CPUID leaves loaded from the state.
5328	* @param cLeaves The number of leaves in @a paLeaves.
5329	* @param pMsrs The guest MSRs.
5330	*/
5331	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
5332	{
5333	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5334
5335	/*
5336	* Continue loading the state into stack buffers.
5337	*/
5338	CPUMCPUID GuestDefCpuId;
5339	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5340	AssertRCReturn(rc, rc);
5341
5342	CPUMCPUID aRawStd[16];
5343	uint32_t cRawStd;
5344	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5345	if (cRawStd > RT_ELEMENTS(aRawStd))
5346	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5347	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5348	AssertRCReturn(rc, rc);
5349	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5350	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5351
5352	CPUMCPUID aRawExt[32];
5353	uint32_t cRawExt;
5354	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5355	if (cRawExt > RT_ELEMENTS(aRawExt))
5356	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5357	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5358	AssertRCReturn(rc, rc);
5359	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5360	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5361
5362	/*
5363	* Get the raw CPU IDs for the current host.
5364	*/
5365	CPUMCPUID aHostRawStd[16];
5366	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5367	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5368
5369	CPUMCPUID aHostRawExt[32];
5370	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5371	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5372	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5373
5374	/*
5375	* Get the host and guest overrides so we don't reject the state because
5376	* some feature was enabled thru these interfaces.
5377	* Note! We currently only need the feature leaves, so skip rest.
5378	*/
5379	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5380	CPUMCPUID aHostOverrideStd[2];
5381	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5382	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5383
5384	CPUMCPUID aHostOverrideExt[2];
5385	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5386	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5387
5388	/*
5389	* This can be skipped.
5390	*/
5391	bool fStrictCpuIdChecks;
5392	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5393
5394	/*
5395	* Define a bunch of macros for simplifying the santizing/checking code below.
5396	*/
5397	/* Generic expression + failure message. */
5398	#define CPUID_CHECK_RET(expr, fmt) \
5399	do { \
5400	if (!(expr)) \
5401	{ \
5402	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5403	if (fStrictCpuIdChecks) \
5404	{ \
5405	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5406	RTStrFree(pszMsg); \
5407	return rcCpuid; \
5408	} \
5409	LogRel(("CPUM: %s\n", pszMsg)); \
5410	RTStrFree(pszMsg); \
5411	} \
5412	} while (0)
5413	#define CPUID_CHECK_WRN(expr, fmt) \
5414	do { \
5415	if (!(expr)) \
5416	LogRel(fmt); \
5417	} while (0)
5418
5419	/* For comparing two values and bitch if they differs. */
5420	#define CPUID_CHECK2_RET(what, host, saved) \
5421	do { \
5422	if ((host) != (saved)) \
5423	{ \
5424	if (fStrictCpuIdChecks) \
5425	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5426	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5427	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5428	} \
5429	} while (0)
5430	#define CPUID_CHECK2_WRN(what, host, saved) \
5431	do { \
5432	if ((host) != (saved)) \
5433	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5434	} while (0)
5435
5436	/* For checking raw cpu features (raw mode). */
5437	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5438	do { \
5439	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5440	{ \
5441	if (fStrictCpuIdChecks) \
5442	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5443	N_(#bit " mismatch: host=%d saved=%d"), \
5444	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5445	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5446	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5447	} \
5448	} while (0)
5449	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5450	do { \
5451	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5452	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5453	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5454	} while (0)
5455	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5456
5457	/* For checking guest features. */
5458	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5459	do { \
5460	if ( (aGuestCpuId##set [1].reg & bit) \
5461	&& !(aHostRaw##set [1].reg & bit) \
5462	&& !(aHostOverride##set [1].reg & bit) \
5463	) \
5464	{ \
5465	if (fStrictCpuIdChecks) \
5466	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5467	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5468	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5469	} \
5470	} while (0)
5471	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5472	do { \
5473	if ( (aGuestCpuId##set [1].reg & bit) \
5474	&& !(aHostRaw##set [1].reg & bit) \
5475	&& !(aHostOverride##set [1].reg & bit) \
5476	) \
5477	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5478	} while (0)
5479	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5480	do { \
5481	if ( (aGuestCpuId##set [1].reg & bit) \
5482	&& !(aHostRaw##set [1].reg & bit) \
5483	&& !(aHostOverride##set [1].reg & bit) \
5484	) \
5485	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5486	} while (0)
5487	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5488
5489	/* For checking guest features if AMD guest CPU. */
5490	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5491	do { \
5492	if ( (aGuestCpuId##set [1].reg & bit) \
5493	&& fGuestAmd \
5494	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5495	&& !(aHostOverride##set [1].reg & bit) \
5496	) \
5497	{ \
5498	if (fStrictCpuIdChecks) \
5499	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5500	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5501	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5502	} \
5503	} while (0)
5504	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5505	do { \
5506	if ( (aGuestCpuId##set [1].reg & bit) \
5507	&& fGuestAmd \
5508	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5509	&& !(aHostOverride##set [1].reg & bit) \
5510	) \
5511	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5512	} while (0)
5513	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5514	do { \
5515	if ( (aGuestCpuId##set [1].reg & bit) \
5516	&& fGuestAmd \
5517	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5518	&& !(aHostOverride##set [1].reg & bit) \
5519	) \
5520	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5521	} while (0)
5522	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5523
5524	/* For checking AMD features which have a corresponding bit in the standard
5525	range. (Intel defines very few bits in the extended feature sets.) */
5526	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5527	do { \
5528	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5529	&& !(fHostAmd \
5530	? aHostRawExt[1].reg & (ExtBit) \
5531	: aHostRawStd[1].reg & (StdBit)) \
5532	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5533	) \
5534	{ \
5535	if (fStrictCpuIdChecks) \
5536	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5537	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5538	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5539	} \
5540	} while (0)
5541	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5542	do { \
5543	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5544	&& !(fHostAmd \
5545	? aHostRawExt[1].reg & (ExtBit) \
5546	: aHostRawStd[1].reg & (StdBit)) \
5547	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5548	) \
5549	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5550	} while (0)
5551	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5552	do { \
5553	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5554	&& !(fHostAmd \
5555	? aHostRawExt[1].reg & (ExtBit) \
5556	: aHostRawStd[1].reg & (StdBit)) \
5557	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5558	) \
5559	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5560	} while (0)
5561	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5562
5563
5564	/*
5565	* Verify that we can support the features already exposed to the guest on
5566	* this host.
5567	*
5568	* Most of the features we're emulating requires intercepting instruction
5569	* and doing it the slow way, so there is no need to warn when they aren't
5570	* present in the host CPU. Thus we use IGN instead of EMU on these.
5571	*
5572	* Trailing comments:
5573	* "EMU" - Possible to emulate, could be lots of work and very slow.
5574	* "EMU?" - Can this be emulated?
5575	*/
5576	CPUMCPUID aGuestCpuIdStd[2];
5577	RT_ZERO(aGuestCpuIdStd);
5578	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5579
5580	/* CPUID(1).ecx */
5581	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5582	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5583	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5584	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5585	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5586	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5587	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5588	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5589	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5590	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5591	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5592	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5593	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5594	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5595	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5596	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5597	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5598	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5599	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5600	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5601	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5602	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5603	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5604	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5605	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5606	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5607	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5608	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5609	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5610	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5611	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5612	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5613
5614	/* CPUID(1).edx */
5615	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5616	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5617	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5618	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5619	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5620	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5621	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5622	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5623	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5624	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5625	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5626	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5627	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5628	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5629	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5630	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5631	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5632	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5633	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5634	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5635	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5636	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5637	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5638	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5639	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5640	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5641	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5642	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5643	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5644	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5645	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5646	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5647
5648	/* CPUID(0x80000000). */
5649	CPUMCPUID aGuestCpuIdExt[2];
5650	RT_ZERO(aGuestCpuIdExt);
5651	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5652	{
5653	/** @todo deal with no 0x80000001 on the host. */
5654	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5655	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5656
5657	/* CPUID(0x80000001).ecx */
5658	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5659	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5660	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5661	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5662	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5663	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5664	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5665	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5666	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5667	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5668	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5669	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5670	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5671	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5672	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5673	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5674	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5675	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5676	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5677	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5678	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5679	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5680	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5681	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5682	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5683	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5684	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5685	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5686	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5687	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5688	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5689	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5690
5691	/* CPUID(0x80000001).edx */
5692	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5693	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5694	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5695	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5696	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5697	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5698	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5699	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5700	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5701	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5702	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5703	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5704	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5705	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5706	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5707	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5708	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5709	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5710	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5711	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5712	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5713	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5714	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5715	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5716	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5717	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5718	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5719	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5720	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5721	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5722	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5723	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5724	}
5725
5726	/** @todo check leaf 7 */
5727
5728	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5729	* ECX=0: EAX - Valid bits in XCR0[31:0].
5730	* EBX - Maximum state size as per current XCR0 value.
5731	* ECX - Maximum state size for all supported features.
5732	* EDX - Valid bits in XCR0[63:32].
5733	* ECX=1: EAX - Various X-features.
5734	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5735	* ECX - Valid bits in IA32_XSS[31:0].
5736	* EDX - Valid bits in IA32_XSS[63:32].
5737	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5738	* if the bit invalid all four registers are set to zero.
5739	* EAX - The state size for this feature.
5740	* EBX - The state byte offset of this feature.
5741	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5742	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5743	*/
5744	uint64_t fGuestXcr0Mask = 0;
5745	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5746	if ( pCurLeaf
5747	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5748	&& ( pCurLeaf->uEax
5749	\|\| pCurLeaf->uEbx
5750	\|\| pCurLeaf->uEcx
5751	\|\| pCurLeaf->uEdx) )
5752	{
5753	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5754	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5755	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5756	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5757	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5758	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5759	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5760	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5761
5762	/* We don't support any additional features yet. */
5763	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5764	if (pCurLeaf && pCurLeaf->uEax)
5765	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5766	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5767	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5768	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5769	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5770	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5771
5772
5773	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5774	{
5775	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5776	if (pCurLeaf)
5777	{
5778	/* If advertised, the state component offset and size must match the one used by host. */
5779	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5780	{
5781	CPUMCPUID RawHost;
5782	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5783	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5784	if ( RawHost.uEbx != pCurLeaf->uEbx
5785	\|\| RawHost.uEax != pCurLeaf->uEax)
5786	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5787	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5788	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5789	}
5790	}
5791	}
5792	}
5793	/* Clear leaf 0xd just in case we're loading an old state... */
5794	else if (pCurLeaf)
5795	{
5796	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5797	{
5798	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5799	if (pCurLeaf)
5800	{
5801	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5802	\|\| ( pCurLeaf->uEax == 0
5803	&& pCurLeaf->uEbx == 0
5804	&& pCurLeaf->uEcx == 0
5805	&& pCurLeaf->uEdx == 0),
5806	("uVersion=%#x; %#x %#x %#x %#x\n",
5807	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5808	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5809	}
5810	}
5811	}
5812
5813	/* Update the fXStateGuestMask value for the VM. */
5814	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5815	{
5816	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5817	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5818	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5819	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5820	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5821	}
5822
5823	#undef CPUID_CHECK_RET
5824	#undef CPUID_CHECK_WRN
5825	#undef CPUID_CHECK2_RET
5826	#undef CPUID_CHECK2_WRN
5827	#undef CPUID_RAW_FEATURE_RET
5828	#undef CPUID_RAW_FEATURE_WRN
5829	#undef CPUID_RAW_FEATURE_IGN
5830	#undef CPUID_GST_FEATURE_RET
5831	#undef CPUID_GST_FEATURE_WRN
5832	#undef CPUID_GST_FEATURE_EMU
5833	#undef CPUID_GST_FEATURE_IGN
5834	#undef CPUID_GST_FEATURE2_RET
5835	#undef CPUID_GST_FEATURE2_WRN
5836	#undef CPUID_GST_FEATURE2_EMU
5837	#undef CPUID_GST_FEATURE2_IGN
5838	#undef CPUID_GST_AMD_FEATURE_RET
5839	#undef CPUID_GST_AMD_FEATURE_WRN
5840	#undef CPUID_GST_AMD_FEATURE_EMU
5841	#undef CPUID_GST_AMD_FEATURE_IGN
5842
5843	/*
5844	* We're good, commit the CPU ID leaves.
5845	*/
5846	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5847	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5848	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5849	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5850	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
5851	AssertLogRelRCReturn(rc, rc);
5852
5853	return VINF_SUCCESS;
5854	}
5855
5856
5857	/**
5858	* Loads the CPU ID leaves saved by pass 0.
5859	*
5860	* @returns VBox status code.
5861	* @param pVM The cross context VM structure.
5862	* @param pSSM The saved state handle.
5863	* @param uVersion The format version.
5864	* @param pMsrs The guest MSRs.
5865	*/
5866	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
5867	{
5868	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5869
5870	/*
5871	* Load the CPUID leaves array first and call worker to do the rest, just so
5872	* we can free the memory when we need to without ending up in column 1000.
5873	*/
5874	PCPUMCPUIDLEAF paLeaves;
5875	uint32_t cLeaves;
5876	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5877	AssertRC(rc);
5878	if (RT_SUCCESS(rc))
5879	{
5880	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
5881	RTMemFree(paLeaves);
5882	}
5883	return rc;
5884	}
5885
5886
5887
5888	/**
5889	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5890	*
5891	* @returns VBox status code.
5892	* @param pVM The cross context VM structure.
5893	* @param pSSM The saved state handle.
5894	* @param uVersion The format version.
5895	*/
5896	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5897	{
5898	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5899
5900	/*
5901	* Restore the CPUID leaves.
5902	*
5903	* Note that we support restoring less than the current amount of standard
5904	* leaves because we've been allowed more is newer version of VBox.
5905	*/
5906	uint32_t cElements;
5907	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5908	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5909	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5910	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5911
5912	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5913	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5914	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5915	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5916
5917	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5918	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5919	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5920	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5921
5922	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5923
5924	/*
5925	* Check that the basic cpuid id information is unchanged.
5926	*/
5927	/** @todo we should check the 64 bits capabilities too! */
5928	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5929	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5930	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5931	uint32_t au32CpuIdSaved[8];
5932	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5933	if (RT_SUCCESS(rc))
5934	{
5935	/* Ignore CPU stepping. */
5936	au32CpuId[4] &= 0xfffffff0;
5937	au32CpuIdSaved[4] &= 0xfffffff0;
5938
5939	/* Ignore APIC ID (AMD specs). */
5940	au32CpuId[5] &= ~0xff000000;
5941	au32CpuIdSaved[5] &= ~0xff000000;
5942
5943	/* Ignore the number of Logical CPUs (AMD specs). */
5944	au32CpuId[5] &= ~0x00ff0000;
5945	au32CpuIdSaved[5] &= ~0x00ff0000;
5946
5947	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5948	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5949	\| X86_CPUID_FEATURE_ECX_VMX
5950	\| X86_CPUID_FEATURE_ECX_SMX
5951	\| X86_CPUID_FEATURE_ECX_EST
5952	\| X86_CPUID_FEATURE_ECX_TM2
5953	\| X86_CPUID_FEATURE_ECX_CNTXID
5954	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5955	\| X86_CPUID_FEATURE_ECX_PDCM
5956	\| X86_CPUID_FEATURE_ECX_DCA
5957	\| X86_CPUID_FEATURE_ECX_X2APIC
5958	);
5959	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5960	\| X86_CPUID_FEATURE_ECX_VMX
5961	\| X86_CPUID_FEATURE_ECX_SMX
5962	\| X86_CPUID_FEATURE_ECX_EST
5963	\| X86_CPUID_FEATURE_ECX_TM2
5964	\| X86_CPUID_FEATURE_ECX_CNTXID
5965	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5966	\| X86_CPUID_FEATURE_ECX_PDCM
5967	\| X86_CPUID_FEATURE_ECX_DCA
5968	\| X86_CPUID_FEATURE_ECX_X2APIC
5969	);
5970
5971	/* Make sure we don't forget to update the masks when enabling
5972	* features in the future.
5973	*/
5974	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5975	( X86_CPUID_FEATURE_ECX_DTES64
5976	\| X86_CPUID_FEATURE_ECX_VMX
5977	\| X86_CPUID_FEATURE_ECX_SMX
5978	\| X86_CPUID_FEATURE_ECX_EST
5979	\| X86_CPUID_FEATURE_ECX_TM2
5980	\| X86_CPUID_FEATURE_ECX_CNTXID
5981	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5982	\| X86_CPUID_FEATURE_ECX_PDCM
5983	\| X86_CPUID_FEATURE_ECX_DCA
5984	\| X86_CPUID_FEATURE_ECX_X2APIC
5985	)));
5986	/* do the compare */
5987	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5988	{
5989	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5990	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5991	"Saved=%.*Rhxs\n"
5992	"Real =%.*Rhxs\n",
5993	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5994	sizeof(au32CpuId), au32CpuId));
5995	else
5996	{
5997	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5998	"Saved=%.*Rhxs\n"
5999	"Real =%.*Rhxs\n",
6000	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6001	sizeof(au32CpuId), au32CpuId));
6002	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
6003	}
6004	}
6005	}
6006
6007	return rc;
6008	}
6009
6010
6011
6012	/*
6013	*
6014	*
6015	* CPUID Info Handler.
6016	* CPUID Info Handler.
6017	* CPUID Info Handler.
6018	*
6019	*
6020	*/
6021
6022
6023
6024	/**
6025	* Get L1 cache / TLS associativity.
6026	*/
6027	static const char getCacheAss(unsigned u, char pszBuf)
6028	{
6029	if (u == 0)
6030	return "res0 ";
6031	if (u == 1)
6032	return "direct";
6033	if (u == 255)
6034	return "fully";
6035	if (u >= 256)
6036	return "???";
6037
6038	RTStrPrintf(pszBuf, 16, "%d way", u);
6039	return pszBuf;
6040	}
6041
6042
6043	/**
6044	* Get L2 cache associativity.
6045	*/
6046	const char *getL2CacheAss(unsigned u)
6047	{
6048	switch (u)
6049	{
6050	case 0: return "off ";
6051	case 1: return "direct";
6052	case 2: return "2 way ";
6053	case 3: return "res3 ";
6054	case 4: return "4 way ";
6055	case 5: return "res5 ";
6056	case 6: return "8 way ";
6057	case 7: return "res7 ";
6058	case 8: return "16 way";
6059	case 9: return "res9 ";
6060	case 10: return "res10 ";
6061	case 11: return "res11 ";
6062	case 12: return "res12 ";
6063	case 13: return "res13 ";
6064	case 14: return "res14 ";
6065	case 15: return "fully ";
6066	default: return "????";
6067	}
6068	}
6069
6070
6071	/** CPUID(1).EDX field descriptions. */
6072	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6073	{
6074	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6075	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6076	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6077	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6078	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6079	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6080	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6081	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6082	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6083	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6084	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6085	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6086	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6087	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6088	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6089	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6090	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6091	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6092	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6093	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6094	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6095	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6096	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6097	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6098	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6099	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6100	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6101	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6102	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6103	DBGFREGSUBFIELD_TERMINATOR()
6104	};
6105
6106	/** CPUID(1).ECX field descriptions. */
6107	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6108	{
6109	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6110	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6111	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6112	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6113	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6114	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6115	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6116	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6117	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6118	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6119	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6120	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6121	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6122	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6123	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6124	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6125	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6126	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6127	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6128	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6129	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6130	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6131	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6132	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6133	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6134	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6135	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6136	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6137	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6138	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6139	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6140	DBGFREGSUBFIELD_TERMINATOR()
6141	};
6142
6143	/** CPUID(7,0).EBX field descriptions. */
6144	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6145	{
6146	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6147	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6148	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6149	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6150	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6151	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6152	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6153	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6154	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6155	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6156	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6157	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6158	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6159	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6160	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6161	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6162	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6163	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6164	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6165	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6166	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6167	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6168	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6169	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6170	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6171	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6172	DBGFREGSUBFIELD_TERMINATOR()
6173	};
6174
6175	/** CPUID(7,0).ECX field descriptions. */
6176	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6177	{
6178	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6179	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6180	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6181	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6182	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6183	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6184	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6185	DBGFREGSUBFIELD_TERMINATOR()
6186	};
6187
6188	/** CPUID(7,0).EDX field descriptions. */
6189	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6190	{
6191	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
6192	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6193	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6194	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
6195	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6196	DBGFREGSUBFIELD_TERMINATOR()
6197	};
6198
6199
6200	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6201	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6202	{
6203	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6204	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6205	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6206	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6207	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6208	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6209	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6210	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6211	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6212	DBGFREGSUBFIELD_TERMINATOR()
6213	};
6214
6215	/** CPUID(13,1).EAX field descriptions. */
6216	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6217	{
6218	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6219	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6220	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6221	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6222	DBGFREGSUBFIELD_TERMINATOR()
6223	};
6224
6225
6226	/** CPUID(0x80000001,0).EDX field descriptions. */
6227	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6228	{
6229	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6230	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6231	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6232	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6233	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6234	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6235	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6236	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6237	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6238	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6239	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6240	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6241	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6242	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6243	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6244	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6245	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6246	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6247	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6248	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6249	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6250	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6251	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6252	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6253	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6254	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6255	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6256	DBGFREGSUBFIELD_TERMINATOR()
6257	};
6258
6259	/** CPUID(0x80000001,0).ECX field descriptions. */
6260	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6261	{
6262	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6263	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6264	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6265	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6266	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6267	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6268	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6269	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6270	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6271	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6272	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6273	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6274	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6275	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6276	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6277	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6278	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6279	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6280	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6281	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6282	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6283	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6284	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6285	DBGFREGSUBFIELD_TERMINATOR()
6286	};
6287
6288	/** CPUID(0x8000000a,0).EDX field descriptions. */
6289	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6290	{
6291	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6292	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6293	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6294	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6295	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6296	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6297	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6298	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6299	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6300	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6301	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6302	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6303	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6304	DBGFREGSUBFIELD_TERMINATOR()
6305	};
6306
6307
6308	/** CPUID(0x80000007,0).EDX field descriptions. */
6309	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6310	{
6311	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6312	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6313	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6314	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6315	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6316	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6317	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6318	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6319	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6320	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6321	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6322	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6323	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6324	DBGFREGSUBFIELD_TERMINATOR()
6325	};
6326
6327	/** CPUID(0x80000008,0).EBX field descriptions. */
6328	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6329	{
6330	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6331	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6332	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6333	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6334	DBGFREGSUBFIELD_TERMINATOR()
6335	};
6336
6337
6338	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6339	const char *pszLeadIn, uint32_t cchWidth)
6340	{
6341	if (pszLeadIn)
6342	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6343
6344	for (uint32_t iBit = 0; iBit < 32; iBit++)
6345	if (RT_BIT_32(iBit) & uVal)
6346	{
6347	while ( pDesc->pszName != NULL
6348	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6349	pDesc++;
6350	if ( pDesc->pszName != NULL
6351	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6352	{
6353	if (pDesc->cBits == 1)
6354	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6355	else
6356	{
6357	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6358	if (pDesc->cBits < 32)
6359	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6360	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6361	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6362	}
6363	}
6364	else
6365	pHlp->pfnPrintf(pHlp, " %u", iBit);
6366	}
6367	if (pszLeadIn)
6368	pHlp->pfnPrintf(pHlp, "\n");
6369	}
6370
6371
6372	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6373	const char *pszLeadIn, uint32_t cchWidth)
6374	{
6375	if (pszLeadIn)
6376	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6377
6378	for (uint32_t iBit = 0; iBit < 64; iBit++)
6379	if (RT_BIT_64(iBit) & uVal)
6380	{
6381	while ( pDesc->pszName != NULL
6382	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6383	pDesc++;
6384	if ( pDesc->pszName != NULL
6385	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6386	{
6387	if (pDesc->cBits == 1)
6388	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6389	else
6390	{
6391	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6392	if (pDesc->cBits < 64)
6393	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6394	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6395	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6396	}
6397	}
6398	else
6399	pHlp->pfnPrintf(pHlp, " %u", iBit);
6400	}
6401	if (pszLeadIn)
6402	pHlp->pfnPrintf(pHlp, "\n");
6403	}
6404
6405
6406	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6407	const char *pszLeadIn, uint32_t cchWidth)
6408	{
6409	if (!uVal)
6410	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6411	else
6412	{
6413	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6414	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6415	pHlp->pfnPrintf(pHlp, " )\n");
6416	}
6417	}
6418
6419
6420	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6421	uint32_t cchWidth)
6422	{
6423	uint32_t uCombined = uVal1 \| uVal2;
6424	for (uint32_t iBit = 0; iBit < 32; iBit++)
6425	if ( (RT_BIT_32(iBit) & uCombined)
6426	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6427	{
6428	while ( pDesc->pszName != NULL
6429	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6430	pDesc++;
6431
6432	if ( pDesc->pszName != NULL
6433	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6434	{
6435	size_t cchMnemonic = strlen(pDesc->pszName);
6436	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6437	size_t cchDesc = strlen(pszDesc);
6438	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6439	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6440	if (pDesc->cBits < 32)
6441	{
6442	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6443	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6444	}
6445
6446	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6447	pDesc->pszName, pszDesc,
6448	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6449	uFieldValue1, uFieldValue2);
6450
6451	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6452	pDesc++;
6453	}
6454	else
6455	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6456	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6457	}
6458	}
6459
6460
6461	/**
6462	* Produces a detailed summary of standard leaf 0x00000001.
6463	*
6464	* @param pHlp The info helper functions.
6465	* @param pCurLeaf The 0x00000001 leaf.
6466	* @param fVerbose Whether to be very verbose or not.
6467	* @param fIntel Set if intel CPU.
6468	*/
6469	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6470	{
6471	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6472	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6473	uint32_t uEAX = pCurLeaf->uEax;
6474	uint32_t uEBX = pCurLeaf->uEbx;
6475
6476	pHlp->pfnPrintf(pHlp,
6477	"%36s %2d \tExtended: %d \tEffective: %d\n"
6478	"%36s %2d \tExtended: %d \tEffective: %d\n"
6479	"%36s %d\n"
6480	"%36s %d (%s)\n"
6481	"%36s %#04x\n"
6482	"%36s %d\n"
6483	"%36s %d\n"
6484	"%36s %#04x\n"
6485	,
6486	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6487	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6488	"Stepping:", ASMGetCpuStepping(uEAX),
6489	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6490	"APIC ID:", (uEBX >> 24) & 0xff,
6491	"Logical CPUs:",(uEBX >> 16) & 0xff,
6492	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6493	"Brand ID:", (uEBX >> 0) & 0xff);
6494	if (fVerbose)
6495	{
6496	CPUMCPUID Host;
6497	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6498	pHlp->pfnPrintf(pHlp, "Features\n");
6499	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6500	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6501	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6502	}
6503	else
6504	{
6505	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6506	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6507	}
6508	}
6509
6510
6511	/**
6512	* Produces a detailed summary of standard leaf 0x00000007.
6513	*
6514	* @param pHlp The info helper functions.
6515	* @param paLeaves The CPUID leaves array.
6516	* @param cLeaves The number of leaves in the array.
6517	* @param pCurLeaf The first 0x00000007 leaf.
6518	* @param fVerbose Whether to be very verbose or not.
6519	*/
6520	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6521	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6522	{
6523	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6524	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6525	for (;;)
6526	{
6527	CPUMCPUID Host;
6528	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6529
6530	switch (pCurLeaf->uSubLeaf)
6531	{
6532	case 0:
6533	if (fVerbose)
6534	{
6535	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6536	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6537	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6538	if (pCurLeaf->uEdx \|\| Host.uEdx)
6539	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6540	}
6541	else
6542	{
6543	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6544	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6545	if (pCurLeaf->uEdx)
6546	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6547	}
6548	break;
6549
6550	default:
6551	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6552	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6553	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6554	break;
6555
6556	}
6557
6558	/* advance. */
6559	pCurLeaf++;
6560	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6561	\|\| pCurLeaf->uLeaf != 0x7)
6562	break;
6563	}
6564	}
6565
6566
6567	/**
6568	* Produces a detailed summary of standard leaf 0x0000000d.
6569	*
6570	* @param pHlp The info helper functions.
6571	* @param paLeaves The CPUID leaves array.
6572	* @param cLeaves The number of leaves in the array.
6573	* @param pCurLeaf The first 0x00000007 leaf.
6574	* @param fVerbose Whether to be very verbose or not.
6575	*/
6576	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6577	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6578	{
6579	RT_NOREF_PV(fVerbose);
6580	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6581	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6582	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6583	{
6584	CPUMCPUID Host;
6585	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6586
6587	switch (uSubLeaf)
6588	{
6589	case 0:
6590	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6591	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6592	pCurLeaf->uEbx, pCurLeaf->uEcx);
6593	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6594
6595	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6596	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6597	"Valid XCR0 bits, guest:", 42);
6598	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6599	"Valid XCR0 bits, host:", 42);
6600	break;
6601
6602	case 1:
6603	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6604	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6605	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6606
6607	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6608	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6609	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6610
6611	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6612	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6613	" Valid IA32_XSS bits, guest:", 42);
6614	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6615	" Valid IA32_XSS bits, host:", 42);
6616	break;
6617
6618	default:
6619	if ( pCurLeaf
6620	&& pCurLeaf->uSubLeaf == uSubLeaf
6621	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6622	{
6623	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6624	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6625	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6626	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6627	if (pCurLeaf->uEdx)
6628	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6629	pHlp->pfnPrintf(pHlp, " --");
6630	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6631	pHlp->pfnPrintf(pHlp, "\n");
6632	}
6633	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6634	{
6635	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6636	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6637	if (Host.uEcx & ~RT_BIT_32(0))
6638	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6639	if (Host.uEdx)
6640	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6641	pHlp->pfnPrintf(pHlp, " --");
6642	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6643	pHlp->pfnPrintf(pHlp, "\n");
6644	}
6645	break;
6646
6647	}
6648
6649	/* advance. */
6650	if (pCurLeaf)
6651	{
6652	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6653	&& pCurLeaf->uSubLeaf <= uSubLeaf
6654	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6655	pCurLeaf++;
6656	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6657	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6658	pCurLeaf = NULL;
6659	}
6660	}
6661	}
6662
6663
6664	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6665	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6666	{
6667	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6668	&& pCurLeaf->uLeaf <= uUpToLeaf)
6669	{
6670	pHlp->pfnPrintf(pHlp,
6671	" %s\n"
6672	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6673	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6674	&& pCurLeaf->uLeaf <= uUpToLeaf)
6675	{
6676	CPUMCPUID Host;
6677	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6678	pHlp->pfnPrintf(pHlp,
6679	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6680	"Hst: %08x %08x %08x %08x\n",
6681	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6682	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6683	pCurLeaf++;
6684	}
6685	}
6686
6687	return pCurLeaf;
6688	}
6689
6690
6691	/**
6692	* Display the guest CpuId leaves.
6693	*
6694	* @param pVM The cross context VM structure.
6695	* @param pHlp The info helper functions.
6696	* @param pszArgs "terse", "default" or "verbose".
6697	*/
6698	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6699	{
6700	/*
6701	* Parse the argument.
6702	*/
6703	unsigned iVerbosity = 1;
6704	if (pszArgs)
6705	{
6706	pszArgs = RTStrStripL(pszArgs);
6707	if (!strcmp(pszArgs, "terse"))
6708	iVerbosity--;
6709	else if (!strcmp(pszArgs, "verbose"))
6710	iVerbosity++;
6711	}
6712
6713	uint32_t uLeaf;
6714	CPUMCPUID Host;
6715	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6716	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6717	PCCPUMCPUIDLEAF pCurLeaf;
6718	PCCPUMCPUIDLEAF pNextLeaf;
6719	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6720	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6721	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6722
6723	/*
6724	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6725	*/
6726	uint32_t cHstMax = ASMCpuId_EAX(0);
6727	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6728	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6729	pHlp->pfnPrintf(pHlp,
6730	" Raw Standard CPUID Leaves\n"
6731	" Leaf/sub-leaf eax ebx ecx edx\n");
6732	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6733	{
6734	uint32_t cMaxSubLeaves = 1;
6735	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6736	cMaxSubLeaves = 16;
6737	else if (uLeaf == 0xd)
6738	cMaxSubLeaves = 128;
6739
6740	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6741	{
6742	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6743	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6744	&& pCurLeaf->uLeaf == uLeaf
6745	&& pCurLeaf->uSubLeaf == uSubLeaf)
6746	{
6747	pHlp->pfnPrintf(pHlp,
6748	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6749	"Hst: %08x %08x %08x %08x\n",
6750	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6751	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6752	pCurLeaf++;
6753	}
6754	else if ( uLeaf != 0xd
6755	\|\| uSubLeaf <= 1
6756	\|\| Host.uEbx != 0 )
6757	pHlp->pfnPrintf(pHlp,
6758	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6759	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6760
6761	/* Done? */
6762	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6763	\|\| pCurLeaf->uLeaf != uLeaf)
6764	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6765	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6766	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6767	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6768	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6769	)
6770	)
6771	break;
6772	}
6773	}
6774	pNextLeaf = pCurLeaf;
6775
6776	/*
6777	* If verbose, decode it.
6778	*/
6779	if (iVerbosity && paLeaves[0].uLeaf == 0)
6780	pHlp->pfnPrintf(pHlp,
6781	"%36s %.04s%.04s%.04s\n"
6782	"%36s 0x00000000-%#010x\n"
6783	,
6784	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6785	"Supports:", paLeaves[0].uEax);
6786
6787	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6788	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6789
6790	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6791	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6792
6793	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6794	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6795
6796	pCurLeaf = pNextLeaf;
6797
6798	/*
6799	* Hypervisor leaves.
6800	*
6801	* Unlike most of the other leaves reported, the guest hypervisor leaves
6802	* aren't a subset of the host CPUID bits.
6803	*/
6804	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6805
6806	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6807	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6808	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6809	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6810	cMax = RT_MAX(cHstMax, cGstMax);
6811	if (cMax >= UINT32_C(0x40000000))
6812	{
6813	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6814
6815	/** @todo dump these in more detail. */
6816
6817	pCurLeaf = pNextLeaf;
6818	}
6819
6820
6821	/*
6822	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6823	* Implemented after AMD specs.
6824	*/
6825	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6826
6827	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6828	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6829	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6830	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6831	cMax = RT_MAX(cHstMax, cGstMax);
6832	if (cMax >= UINT32_C(0x80000000))
6833	{
6834
6835	pHlp->pfnPrintf(pHlp,
6836	" Raw Extended CPUID Leaves\n"
6837	" Leaf/sub-leaf eax ebx ecx edx\n");
6838	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6839	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6840	{
6841	uint32_t cMaxSubLeaves = 1;
6842	if (uLeaf == UINT32_C(0x8000001d))
6843	cMaxSubLeaves = 16;
6844
6845	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6846	{
6847	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6848	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6849	&& pCurLeaf->uLeaf == uLeaf
6850	&& pCurLeaf->uSubLeaf == uSubLeaf)
6851	{
6852	pHlp->pfnPrintf(pHlp,
6853	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6854	"Hst: %08x %08x %08x %08x\n",
6855	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6856	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6857	pCurLeaf++;
6858	}
6859	else if ( uLeaf != 0xd
6860	\|\| uSubLeaf <= 1
6861	\|\| Host.uEbx != 0 )
6862	pHlp->pfnPrintf(pHlp,
6863	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6864	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6865
6866	/* Done? */
6867	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6868	\|\| pCurLeaf->uLeaf != uLeaf)
6869	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6870	break;
6871	}
6872	}
6873	pNextLeaf = pCurLeaf;
6874
6875	/*
6876	* Understandable output
6877	*/
6878	if (iVerbosity)
6879	pHlp->pfnPrintf(pHlp,
6880	"Ext Name: %.4s%.4s%.4s\n"
6881	"Ext Supports: 0x80000000-%#010x\n",
6882	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6883
6884	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6885	if (iVerbosity && pCurLeaf)
6886	{
6887	uint32_t uEAX = pCurLeaf->uEax;
6888	pHlp->pfnPrintf(pHlp,
6889	"Family: %d \tExtended: %d \tEffective: %d\n"
6890	"Model: %d \tExtended: %d \tEffective: %d\n"
6891	"Stepping: %d\n"
6892	"Brand ID: %#05x\n",
6893	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6894	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6895	ASMGetCpuStepping(uEAX),
6896	pCurLeaf->uEbx & 0xfff);
6897
6898	if (iVerbosity == 1)
6899	{
6900	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6901	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6902	}
6903	else
6904	{
6905	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6906	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6907	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6908	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6909	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6910	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
6911	{
6912	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
6913	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6914	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
6915	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
6916	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
6917	}
6918	}
6919	}
6920
6921	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6922	{
6923	char szString[443+1] = {0};
6924	uint32_t pu32 = (uint32_t )szString;
6925	*pu32++ = pCurLeaf->uEax;
6926	*pu32++ = pCurLeaf->uEbx;
6927	*pu32++ = pCurLeaf->uEcx;
6928	*pu32++ = pCurLeaf->uEdx;
6929	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6930	if (pCurLeaf)
6931	{
6932	*pu32++ = pCurLeaf->uEax;
6933	*pu32++ = pCurLeaf->uEbx;
6934	*pu32++ = pCurLeaf->uEcx;
6935	*pu32++ = pCurLeaf->uEdx;
6936	}
6937	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6938	if (pCurLeaf)
6939	{
6940	*pu32++ = pCurLeaf->uEax;
6941	*pu32++ = pCurLeaf->uEbx;
6942	*pu32++ = pCurLeaf->uEcx;
6943	*pu32++ = pCurLeaf->uEdx;
6944	}
6945	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6946	}
6947
6948	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6949	{
6950	uint32_t uEAX = pCurLeaf->uEax;
6951	uint32_t uEBX = pCurLeaf->uEbx;
6952	uint32_t uECX = pCurLeaf->uEcx;
6953	uint32_t uEDX = pCurLeaf->uEdx;
6954	char sz1[32];
6955	char sz2[32];
6956
6957	pHlp->pfnPrintf(pHlp,
6958	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6959	"TLB 2/4M Data: %s %3d entries\n",
6960	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6961	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6962	pHlp->pfnPrintf(pHlp,
6963	"TLB 4K Instr/Uni: %s %3d entries\n"
6964	"TLB 4K Data: %s %3d entries\n",
6965	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6966	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6967	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6968	"L1 Instr Cache Lines Per Tag: %d\n"
6969	"L1 Instr Cache Associativity: %s\n"
6970	"L1 Instr Cache Size: %d KB\n",
6971	(uEDX >> 0) & 0xff,
6972	(uEDX >> 8) & 0xff,
6973	getCacheAss((uEDX >> 16) & 0xff, sz1),
6974	(uEDX >> 24) & 0xff);
6975	pHlp->pfnPrintf(pHlp,
6976	"L1 Data Cache Line Size: %d bytes\n"
6977	"L1 Data Cache Lines Per Tag: %d\n"
6978	"L1 Data Cache Associativity: %s\n"
6979	"L1 Data Cache Size: %d KB\n",
6980	(uECX >> 0) & 0xff,
6981	(uECX >> 8) & 0xff,
6982	getCacheAss((uECX >> 16) & 0xff, sz1),
6983	(uECX >> 24) & 0xff);
6984	}
6985
6986	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6987	{
6988	uint32_t uEAX = pCurLeaf->uEax;
6989	uint32_t uEBX = pCurLeaf->uEbx;
6990	uint32_t uEDX = pCurLeaf->uEdx;
6991
6992	pHlp->pfnPrintf(pHlp,
6993	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6994	"L2 TLB 2/4M Data: %s %4d entries\n",
6995	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6996	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6997	pHlp->pfnPrintf(pHlp,
6998	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6999	"L2 TLB 4K Data: %s %4d entries\n",
7000	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
7001	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
7002	pHlp->pfnPrintf(pHlp,
7003	"L2 Cache Line Size: %d bytes\n"
7004	"L2 Cache Lines Per Tag: %d\n"
7005	"L2 Cache Associativity: %s\n"
7006	"L2 Cache Size: %d KB\n",
7007	(uEDX >> 0) & 0xff,
7008	(uEDX >> 8) & 0xf,
7009	getL2CacheAss((uEDX >> 12) & 0xf),
7010	(uEDX >> 16) & 0xffff);
7011	}
7012
7013	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
7014	{
7015	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7016	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
7017	{
7018	if (iVerbosity < 1)
7019	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7020	else
7021	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7022	}
7023	}
7024
7025	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7026	if (pCurLeaf != NULL)
7027	{
7028	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7029	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7030	{
7031	if (iVerbosity < 1)
7032	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7033	else
7034	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7035	}
7036
7037	if (iVerbosity)
7038	{
7039	uint32_t uEAX = pCurLeaf->uEax;
7040	uint32_t uECX = pCurLeaf->uEcx;
7041
7042	pHlp->pfnPrintf(pHlp,
7043	"Physical Address Width: %d bits\n"
7044	"Virtual Address Width: %d bits\n"
7045	"Guest Physical Address Width: %d bits\n",
7046	(uEAX >> 0) & 0xff,
7047	(uEAX >> 8) & 0xff,
7048	(uEAX >> 16) & 0xff);
7049	pHlp->pfnPrintf(pHlp,
7050	"Physical Core Count: %d\n",
7051	((uECX >> 0) & 0xff) + 1);
7052	}
7053	}
7054
7055	pCurLeaf = pNextLeaf;
7056	}
7057
7058
7059
7060	/*
7061	* Centaur.
7062	*/
7063	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7064
7065	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7066	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7067	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7068	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7069	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7070	cMax = RT_MAX(cHstMax, cGstMax);
7071	if (cMax >= UINT32_C(0xc0000000))
7072	{
7073	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7074
7075	/*
7076	* Understandable output
7077	*/
7078	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7079	pHlp->pfnPrintf(pHlp,
7080	"Centaur Supports: 0xc0000000-%#010x\n",
7081	pCurLeaf->uEax);
7082
7083	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7084	{
7085	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7086	uint32_t uEdxGst = pCurLeaf->uEdx;
7087	uint32_t uEdxHst = Host.uEdx;
7088
7089	if (iVerbosity == 1)
7090	{
7091	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7092	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7093	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7094	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7095	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7096	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7097	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7098	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7099	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7100	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7101	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7102	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7103	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7104	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7105	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7106	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7107	for (unsigned iBit = 14; iBit < 32; iBit++)
7108	if (uEdxGst & RT_BIT(iBit))
7109	pHlp->pfnPrintf(pHlp, " %d", iBit);
7110	pHlp->pfnPrintf(pHlp, "\n");
7111	}
7112	else
7113	{
7114	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7115	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7116	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7117	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7118	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7119	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7120	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7121	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7122	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7123	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7124	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7125	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7126	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7127	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7128	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7129	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7130	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7131	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7132	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7133	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7134	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7135	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7136	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7137	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7138	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7139	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7140	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7141	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7142	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7143	for (unsigned iBit = 27; iBit < 32; iBit++)
7144	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7145	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7146	pHlp->pfnPrintf(pHlp, "\n");
7147	}
7148	}
7149
7150	pCurLeaf = pNextLeaf;
7151	}
7152
7153	/*
7154	* The remainder.
7155	*/
7156	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7157	}
7158
7159	#endif /* VBOX_IN_VMM */
7160

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 80239

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