CPUMR3CpuId.cpp@ 81240

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1	/* $Id: CPUMR3CpuId.cpp 81240 2019-10-14 08:22:59Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/mm.h>
31	#include <VBox/sup.h>
32
33	#include <VBox/err.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/ctype.h>
36	#include <iprt/mem.h>
37	#include <iprt/string.h>
38
39
40	/*********************************************************************************************************************************
41	* Defined Constants And Macros *
42	*********************************************************************************************************************************/
43	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
44	#define CPUM_CPUID_MAX_LEAVES 2048
45	/* Max size we accept for the XSAVE area. */
46	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
47	/* Min size we accept for the XSAVE area. */
48	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
49
50
51	/*********************************************************************************************************************************
52	* Global Variables *
53	*********************************************************************************************************************************/
54	/**
55	* The intel pentium family.
56	*/
57	static const CPUMMICROARCH g_aenmIntelFamily06[] =
58	{
59	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
60	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
61	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
63	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
64	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
65	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
66	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
67	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
68	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
69	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
70	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
71	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
72	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
73	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
74	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
75	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
81	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
82	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
83	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [26(0x1a)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Nehalem-EP */
86	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
88	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
89	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
90	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
91	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
97	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
98	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
99	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
102	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
104	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
105	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
106	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
107	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
113	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
114	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
115	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
118	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
121	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
122	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
130	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
131	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
136	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,
138	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Broadwell-E */
139	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu; skylake <= 4, cascade lake > 5 */
145	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
146	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
147	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
150	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
152	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
153	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
154	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
155	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
159	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
160	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
161	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
162	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
163	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
164	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
165	/[106(0x6a)] = / kCpumMicroarch_Intel_Unknown,
166	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
167	/[108(0x6c)] = / kCpumMicroarch_Intel_Unknown,
168	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
169	/[110(0x6e)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
170	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
171	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
172	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
173	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
174	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
175	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
176	/[117(0x75)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
177	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
178	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
179	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
180	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
181	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
182	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
183	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
184	/[125(0x7d)] = / kCpumMicroarch_Intel_Unknown,
185	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
186	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
187	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
188	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
189	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
190	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
191	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
192	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
193	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
194	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
195	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
196	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
197	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
198	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
199	/[140(0x8c)] = / kCpumMicroarch_Intel_Unknown,
200	/[141(0x8d)] = / kCpumMicroarch_Intel_Unknown,
201	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
202	/[143(0x8f)] = / kCpumMicroarch_Intel_Unknown,
203	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
204	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
205	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
206	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
207	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
208	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
209	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
210	/[151(0x97)] = / kCpumMicroarch_Intel_Unknown,
211	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
212	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
213	/[154(0x9a)] = / kCpumMicroarch_Intel_Unknown,
214	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
215	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
216	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
217	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
218	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
219	};
220	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0x9f+1);
221
222
223	/**
224	* Figures out the (sub-)micro architecture given a bit of CPUID info.
225	*
226	* @returns Micro architecture.
227	* @param enmVendor The CPU vendor .
228	* @param bFamily The CPU family.
229	* @param bModel The CPU model.
230	* @param bStepping The CPU stepping.
231	*/
232	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
233	uint8_t bModel, uint8_t bStepping)
234	{
235	if (enmVendor == CPUMCPUVENDOR_AMD)
236	{
237	switch (bFamily)
238	{
239	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
240	case 0x03: return kCpumMicroarch_AMD_Am386;
241	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
242	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
243	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
244	case 0x06:
245	switch (bModel)
246	{
247	case 0: return kCpumMicroarch_AMD_K7_Palomino;
248	case 1: return kCpumMicroarch_AMD_K7_Palomino;
249	case 2: return kCpumMicroarch_AMD_K7_Palomino;
250	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
251	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
252	case 6: return kCpumMicroarch_AMD_K7_Palomino;
253	case 7: return kCpumMicroarch_AMD_K7_Morgan;
254	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
255	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
256	}
257	return kCpumMicroarch_AMD_K7_Unknown;
258	case 0x0f:
259	/*
260	* This family is a friggin mess. Trying my best to make some
261	* sense out of it. Too much happened in the 0x0f family to
262	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
263	*
264	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
265	* cpu-world.com, and other places:
266	* - 130nm:
267	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
268	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
269	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
270	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
271	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
272	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
273	* - 90nm:
274	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
275	* - Oakville: 10FC0/DH-D0.
276	* - Georgetown: 10FC0/DH-D0.
277	* - Sonora: 10FC0/DH-D0.
278	* - Venus: 20F71/SH-E4
279	* - Troy: 20F51/SH-E4
280	* - Athens: 20F51/SH-E4
281	* - San Diego: 20F71/SH-E4.
282	* - Lancaster: 20F42/SH-E5
283	* - Newark: 20F42/SH-E5.
284	* - Albany: 20FC2/DH-E6.
285	* - Roma: 20FC2/DH-E6.
286	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
287	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
288	* - 90nm introducing Dual core:
289	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
290	* - Italy: 20F10/JH-E1, 20F12/JH-E6
291	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
292	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
293	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
294	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
295	* - Santa Ana: 40F32/JH-F2, /-F3
296	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
297	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
298	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
299	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
300	* - Keene: 40FC2/DH-F2.
301	* - Richmond: 40FC2/DH-F2
302	* - Taylor: 40F82/BH-F2
303	* - Trinidad: 40F82/BH-F2
304	*
305	* - 65nm:
306	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
307	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
308	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
309	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
310	* - Sherman: /-G1, 70FC2/DH-G2.
311	* - Huron: 70FF2/DH-G2.
312	*/
313	if (bModel < 0x10)
314	return kCpumMicroarch_AMD_K8_130nm;
315	if (bModel >= 0x60 && bModel < 0x80)
316	return kCpumMicroarch_AMD_K8_65nm;
317	if (bModel >= 0x40)
318	return kCpumMicroarch_AMD_K8_90nm_AMDV;
319	switch (bModel)
320	{
321	case 0x21:
322	case 0x23:
323	case 0x2b:
324	case 0x2f:
325	case 0x37:
326	case 0x3f:
327	return kCpumMicroarch_AMD_K8_90nm_DualCore;
328	}
329	return kCpumMicroarch_AMD_K8_90nm;
330	case 0x10:
331	return kCpumMicroarch_AMD_K10;
332	case 0x11:
333	return kCpumMicroarch_AMD_K10_Lion;
334	case 0x12:
335	return kCpumMicroarch_AMD_K10_Llano;
336	case 0x14:
337	return kCpumMicroarch_AMD_Bobcat;
338	case 0x15:
339	switch (bModel)
340	{
341	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
342	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
343	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
344	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
345	case 0x11: /* ?? */
346	case 0x12: /* ?? */
347	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
348	}
349	return kCpumMicroarch_AMD_15h_Unknown;
350	case 0x16:
351	return kCpumMicroarch_AMD_Jaguar;
352	case 0x17:
353	return kCpumMicroarch_AMD_Zen_Ryzen;
354	}
355	return kCpumMicroarch_AMD_Unknown;
356	}
357
358	if (enmVendor == CPUMCPUVENDOR_INTEL)
359	{
360	switch (bFamily)
361	{
362	case 3:
363	return kCpumMicroarch_Intel_80386;
364	case 4:
365	return kCpumMicroarch_Intel_80486;
366	case 5:
367	return kCpumMicroarch_Intel_P5;
368	case 6:
369	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
370	{
371	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
372	if (enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake)
373	{
374	if (bStepping >= 0xa && bStepping <= 0xc)
375	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
376	else if (bStepping >= 0xc)
377	enmMicroArch = kCpumMicroarch_Intel_Core7_WhiskeyLake;
378	}
379	else if ( enmMicroArch == kCpumMicroarch_Intel_Core7_Skylake
380	&& bModel == 0x55
381	&& bStepping >= 5)
382	enmMicroArch = kCpumMicroarch_Intel_Core7_CascadeLake;
383	return enmMicroArch;
384	}
385	return kCpumMicroarch_Intel_Atom_Unknown;
386	case 15:
387	switch (bModel)
388	{
389	case 0: return kCpumMicroarch_Intel_NB_Willamette;
390	case 1: return kCpumMicroarch_Intel_NB_Willamette;
391	case 2: return kCpumMicroarch_Intel_NB_Northwood;
392	case 3: return kCpumMicroarch_Intel_NB_Prescott;
393	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
394	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
395	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
396	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
397	default: return kCpumMicroarch_Intel_NB_Unknown;
398	}
399	break;
400	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
401	case 0:
402	return kCpumMicroarch_Intel_8086;
403	case 1:
404	return kCpumMicroarch_Intel_80186;
405	case 2:
406	return kCpumMicroarch_Intel_80286;
407	}
408	return kCpumMicroarch_Intel_Unknown;
409	}
410
411	if (enmVendor == CPUMCPUVENDOR_VIA)
412	{
413	switch (bFamily)
414	{
415	case 5:
416	switch (bModel)
417	{
418	case 1: return kCpumMicroarch_Centaur_C6;
419	case 4: return kCpumMicroarch_Centaur_C6;
420	case 8: return kCpumMicroarch_Centaur_C2;
421	case 9: return kCpumMicroarch_Centaur_C3;
422	}
423	break;
424
425	case 6:
426	switch (bModel)
427	{
428	case 5: return kCpumMicroarch_VIA_C3_M2;
429	case 6: return kCpumMicroarch_VIA_C3_C5A;
430	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
431	case 8: return kCpumMicroarch_VIA_C3_C5N;
432	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
433	case 10: return kCpumMicroarch_VIA_C7_C5J;
434	case 15: return kCpumMicroarch_VIA_Isaiah;
435	}
436	break;
437	}
438	return kCpumMicroarch_VIA_Unknown;
439	}
440
441	if (enmVendor == CPUMCPUVENDOR_SHANGHAI)
442	{
443	switch (bFamily)
444	{
445	case 6:
446	case 7:
447	return kCpumMicroarch_Shanghai_Wudaokou;
448	default:
449	break;
450	}
451	return kCpumMicroarch_Shanghai_Unknown;
452	}
453
454	if (enmVendor == CPUMCPUVENDOR_CYRIX)
455	{
456	switch (bFamily)
457	{
458	case 4:
459	switch (bModel)
460	{
461	case 9: return kCpumMicroarch_Cyrix_5x86;
462	}
463	break;
464
465	case 5:
466	switch (bModel)
467	{
468	case 2: return kCpumMicroarch_Cyrix_M1;
469	case 4: return kCpumMicroarch_Cyrix_MediaGX;
470	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
471	}
472	break;
473
474	case 6:
475	switch (bModel)
476	{
477	case 0: return kCpumMicroarch_Cyrix_M2;
478	}
479	break;
480
481	}
482	return kCpumMicroarch_Cyrix_Unknown;
483	}
484
485	return kCpumMicroarch_Unknown;
486	}
487
488
489	/**
490	* Translates a microarchitecture enum value to the corresponding string
491	* constant.
492	*
493	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
494	* NULL if the value is invalid.
495	*
496	* @param enmMicroarch The enum value to convert.
497	*/
498	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
499	{
500	switch (enmMicroarch)
501	{
502	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
503	CASE_RET_STR(kCpumMicroarch_Intel_8086);
504	CASE_RET_STR(kCpumMicroarch_Intel_80186);
505	CASE_RET_STR(kCpumMicroarch_Intel_80286);
506	CASE_RET_STR(kCpumMicroarch_Intel_80386);
507	CASE_RET_STR(kCpumMicroarch_Intel_80486);
508	CASE_RET_STR(kCpumMicroarch_Intel_P5);
509
510	CASE_RET_STR(kCpumMicroarch_Intel_P6);
511	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
512	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
513
514	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
515	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
516	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
517
518	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
519	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
520
521	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
522	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
523	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
524	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
525	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
526	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
527	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
528	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
529	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
530	CASE_RET_STR(kCpumMicroarch_Intel_Core7_WhiskeyLake);
531	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CascadeLake);
532	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
533	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
534	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
535
536	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
537	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
538	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
539	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
540	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
541	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
542	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
543	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
544
545	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
546	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
547	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
548	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
549	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
550
551	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
552	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
553	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
554	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
555	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
556	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
557	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
558
559	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
560
561	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
562	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
563	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
564	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
565	CASE_RET_STR(kCpumMicroarch_AMD_K5);
566	CASE_RET_STR(kCpumMicroarch_AMD_K6);
567
568	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
569	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
570	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
571	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
572	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
573	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
574	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
575
576	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
577	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
578	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
579	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
580	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
581
582	CASE_RET_STR(kCpumMicroarch_AMD_K10);
583	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
584	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
585	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
586	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
587
588	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
589	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
590	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
591	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
592	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
593
594	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
595
596	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
597
598	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
599
600	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
601	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
602	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
603	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
604	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
605	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
606	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
607	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
608	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
609	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
610	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
611	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
612	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
613
614	CASE_RET_STR(kCpumMicroarch_Shanghai_Wudaokou);
615	CASE_RET_STR(kCpumMicroarch_Shanghai_Unknown);
616
617	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
618	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
619	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
620	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
621	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
622	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
623
624	CASE_RET_STR(kCpumMicroarch_NEC_V20);
625	CASE_RET_STR(kCpumMicroarch_NEC_V30);
626
627	CASE_RET_STR(kCpumMicroarch_Unknown);
628
629	#undef CASE_RET_STR
630	case kCpumMicroarch_Invalid:
631	case kCpumMicroarch_Intel_End:
632	case kCpumMicroarch_Intel_Core2_End:
633	case kCpumMicroarch_Intel_Core7_End:
634	case kCpumMicroarch_Intel_Atom_End:
635	case kCpumMicroarch_Intel_P6_Core_Atom_End:
636	case kCpumMicroarch_Intel_Phi_End:
637	case kCpumMicroarch_Intel_NB_End:
638	case kCpumMicroarch_AMD_K7_End:
639	case kCpumMicroarch_AMD_K8_End:
640	case kCpumMicroarch_AMD_15h_End:
641	case kCpumMicroarch_AMD_16h_End:
642	case kCpumMicroarch_AMD_Zen_End:
643	case kCpumMicroarch_AMD_End:
644	case kCpumMicroarch_VIA_End:
645	case kCpumMicroarch_Cyrix_End:
646	case kCpumMicroarch_NEC_End:
647	case kCpumMicroarch_Shanghai_End:
648	case kCpumMicroarch_32BitHack:
649	break;
650	/* no default! */
651	}
652
653	return NULL;
654	}
655
656
657	/**
658	* Determins the host CPU MXCSR mask.
659	*
660	* @returns MXCSR mask.
661	*/
662	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
663	{
664	if ( ASMHasCpuId()
665	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
666	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
667	{
668	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
669	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
670	RT_ZERO(*pState);
671	ASMFxSave(pState);
672	if (pState->MXCSR_MASK == 0)
673	return 0xffbf;
674	return pState->MXCSR_MASK;
675	}
676	return 0;
677	}
678
679
680	/**
681	* Gets a matching leaf in the CPUID leaf array.
682	*
683	* @returns Pointer to the matching leaf, or NULL if not found.
684	* @param paLeaves The CPUID leaves to search. This is sorted.
685	* @param cLeaves The number of leaves in the array.
686	* @param uLeaf The leaf to locate.
687	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
688	*/
689	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
690	{
691	/* Lazy bird does linear lookup here since this is only used for the
692	occational CPUID overrides. */
693	for (uint32_t i = 0; i < cLeaves; i++)
694	if ( paLeaves[i].uLeaf == uLeaf
695	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
696	return &paLeaves[i];
697	return NULL;
698	}
699
700
701	#ifndef IN_VBOX_CPU_REPORT
702	/**
703	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
704	*
705	* @returns true if found, false it not.
706	* @param paLeaves The CPUID leaves to search. This is sorted.
707	* @param cLeaves The number of leaves in the array.
708	* @param uLeaf The leaf to locate.
709	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
710	* @param pLegacy The legacy output leaf.
711	*/
712	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
713	PCPUMCPUID pLegacy)
714	{
715	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
716	if (pLeaf)
717	{
718	pLegacy->uEax = pLeaf->uEax;
719	pLegacy->uEbx = pLeaf->uEbx;
720	pLegacy->uEcx = pLeaf->uEcx;
721	pLegacy->uEdx = pLeaf->uEdx;
722	return true;
723	}
724	return false;
725	}
726	#endif /* IN_VBOX_CPU_REPORT */
727
728
729	/**
730	* Ensures that the CPUID leaf array can hold one more leaf.
731	*
732	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
733	* failure.
734	* @param pVM The cross context VM structure. If NULL, use
735	* the process heap, otherwise the VM's hyper heap.
736	* @param ppaLeaves Pointer to the variable holding the array pointer
737	* (input/output).
738	* @param cLeaves The current array size.
739	*
740	* @remarks This function will automatically update the R0 and RC pointers when
741	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
742	* be the corresponding VM's CPUID arrays (which is asserted).
743	*/
744	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
745	{
746	/*
747	* If pVM is not specified, we're on the regular heap and can waste a
748	* little space to speed things up.
749	*/
750	uint32_t cAllocated;
751	if (!pVM)
752	{
753	cAllocated = RT_ALIGN(cLeaves, 16);
754	if (cLeaves + 1 > cAllocated)
755	{
756	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
757	if (pvNew)
758	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
759	else
760	{
761	RTMemFree(*ppaLeaves);
762	*ppaLeaves = NULL;
763	}
764	}
765	}
766	/*
767	* Otherwise, we're on the hyper heap and are probably just inserting
768	* one or two leaves and should conserve space.
769	*/
770	else
771	{
772	#ifdef IN_VBOX_CPU_REPORT
773	AssertReleaseFailed();
774	#else
775	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
776	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
777
778	size_t cb = cLeaves * sizeof(**ppaLeaves);
779	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
780	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
781	if (RT_SUCCESS(rc))
782	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
783	else
784	{
785	*ppaLeaves = NULL;
786	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
787	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
788	}
789	#endif
790	}
791	return *ppaLeaves;
792	}
793
794
795	/**
796	* Append a CPUID leaf or sub-leaf.
797	*
798	* ASSUMES linear insertion order, so we'll won't need to do any searching or
799	* replace anything. Use cpumR3CpuIdInsert() for those cases.
800	*
801	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
802	* the caller need do no more work.
803	* @param ppaLeaves Pointer to the pointer to the array of sorted
804	* CPUID leaves and sub-leaves.
805	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
806	* @param uLeaf The leaf we're adding.
807	* @param uSubLeaf The sub-leaf number.
808	* @param fSubLeafMask The sub-leaf mask.
809	* @param uEax The EAX value.
810	* @param uEbx The EBX value.
811	* @param uEcx The ECX value.
812	* @param uEdx The EDX value.
813	* @param fFlags The flags.
814	*/
815	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
816	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
817	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
818	{
819	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
820	return VERR_NO_MEMORY;
821
822	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
823	Assert( *pcLeaves == 0
824	\|\| pNew[-1].uLeaf < uLeaf
825	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
826
827	pNew->uLeaf = uLeaf;
828	pNew->uSubLeaf = uSubLeaf;
829	pNew->fSubLeafMask = fSubLeafMask;
830	pNew->uEax = uEax;
831	pNew->uEbx = uEbx;
832	pNew->uEcx = uEcx;
833	pNew->uEdx = uEdx;
834	pNew->fFlags = fFlags;
835
836	*pcLeaves += 1;
837	return VINF_SUCCESS;
838	}
839
840
841	/**
842	* Checks that we've updated the CPUID leaves array correctly.
843	*
844	* This is a no-op in non-strict builds.
845	*
846	* @param paLeaves The leaves array.
847	* @param cLeaves The number of leaves.
848	*/
849	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
850	{
851	#ifdef VBOX_STRICT
852	for (uint32_t i = 1; i < cLeaves; i++)
853	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
854	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
855	else
856	{
857	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
858	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
859	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
860	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
861	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
862	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
863	}
864	#else
865	NOREF(paLeaves);
866	NOREF(cLeaves);
867	#endif
868	}
869
870
871	/**
872	* Inserts a CPU ID leaf, replacing any existing ones.
873	*
874	* When inserting a simple leaf where we already got a series of sub-leaves with
875	* the same leaf number (eax), the simple leaf will replace the whole series.
876	*
877	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
878	* host-context heap and has only been allocated/reallocated by the
879	* cpumR3CpuIdEnsureSpace function.
880	*
881	* @returns VBox status code.
882	* @param pVM The cross context VM structure. If NULL, use
883	* the process heap, otherwise the VM's hyper heap.
884	* @param ppaLeaves Pointer to the pointer to the array of sorted
885	* CPUID leaves and sub-leaves. Must be NULL if using
886	* the hyper heap.
887	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
888	* be NULL if using the hyper heap.
889	* @param pNewLeaf Pointer to the data of the new leaf we're about to
890	* insert.
891	*/
892	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
893	{
894	/*
895	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
896	*/
897	if (pVM)
898	{
899	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
900	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
901
902	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
903	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
904	}
905
906	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
907	uint32_t cLeaves = *pcLeaves;
908
909	/*
910	* Validate the new leaf a little.
911	*/
912	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
913	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
914	VERR_INVALID_FLAGS);
915	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
916	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
917	VERR_INVALID_PARAMETER);
918	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
919	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
920	VERR_INVALID_PARAMETER);
921	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
922	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
923	VERR_INVALID_PARAMETER);
924
925	/*
926	* Find insertion point. The lazy bird uses the same excuse as in
927	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
928	*/
929	uint32_t i;
930	if ( cLeaves > 0
931	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
932	{
933	/* Add at end. */
934	i = cLeaves;
935	}
936	else if ( cLeaves > 0
937	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
938	{
939	/* Either replacing the last leaf or dealing with sub-leaves. Spool
940	back to the first sub-leaf to pretend we did the linear search. */
941	i = cLeaves - 1;
942	while ( i > 0
943	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
944	i--;
945	}
946	else
947	{
948	/* Linear search from the start. */
949	i = 0;
950	while ( i < cLeaves
951	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
952	i++;
953	}
954	if ( i < cLeaves
955	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
956	{
957	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
958	{
959	/*
960	* The sub-leaf mask differs, replace all existing leaves with the
961	* same leaf number.
962	*/
963	uint32_t c = 1;
964	while ( i + c < cLeaves
965	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
966	c++;
967	if (c > 1 && i + c < cLeaves)
968	{
969	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
970	*pcLeaves = cLeaves -= c - 1;
971	}
972
973	paLeaves[i] = *pNewLeaf;
974	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
975	return VINF_SUCCESS;
976	}
977
978	/* Find sub-leaf insertion point. */
979	while ( i < cLeaves
980	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
981	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
982	i++;
983
984	/*
985	* If we've got an exactly matching leaf, replace it.
986	*/
987	if ( i < cLeaves
988	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
989	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
990	{
991	paLeaves[i] = *pNewLeaf;
992	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
993	return VINF_SUCCESS;
994	}
995	}
996
997	/*
998	* Adding a new leaf at 'i'.
999	*/
1000	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
1001	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
1002	if (!paLeaves)
1003	return VERR_NO_MEMORY;
1004
1005	if (i < cLeaves)
1006	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
1007	*pcLeaves += 1;
1008	paLeaves[i] = *pNewLeaf;
1009
1010	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1011	return VINF_SUCCESS;
1012	}
1013
1014
1015	#ifndef IN_VBOX_CPU_REPORT
1016	/**
1017	* Removes a range of CPUID leaves.
1018	*
1019	* This will not reallocate the array.
1020	*
1021	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1022	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1023	* @param uFirst The first leaf.
1024	* @param uLast The last leaf.
1025	*/
1026	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1027	{
1028	uint32_t cLeaves = *pcLeaves;
1029
1030	Assert(uFirst <= uLast);
1031
1032	/*
1033	* Find the first one.
1034	*/
1035	uint32_t iFirst = 0;
1036	while ( iFirst < cLeaves
1037	&& paLeaves[iFirst].uLeaf < uFirst)
1038	iFirst++;
1039
1040	/*
1041	* Find the end (last + 1).
1042	*/
1043	uint32_t iEnd = iFirst;
1044	while ( iEnd < cLeaves
1045	&& paLeaves[iEnd].uLeaf <= uLast)
1046	iEnd++;
1047
1048	/*
1049	* Adjust the array if anything needs removing.
1050	*/
1051	if (iFirst < iEnd)
1052	{
1053	if (iEnd < cLeaves)
1054	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1055	*pcLeaves = cLeaves -= (iEnd - iFirst);
1056	}
1057
1058	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1059	}
1060	#endif /* IN_VBOX_CPU_REPORT */
1061
1062
1063	/**
1064	* Checks if ECX make a difference when reading a given CPUID leaf.
1065	*
1066	* @returns @c true if it does, @c false if it doesn't.
1067	* @param uLeaf The leaf we're reading.
1068	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1069	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1070	* final sub-leaf (for leaf 0xb only).
1071	*/
1072	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1073	{
1074	*pfFinalEcxUnchanged = false;
1075
1076	uint32_t auCur[4];
1077	uint32_t auPrev[4];
1078	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1079
1080	/* Look for sub-leaves. */
1081	uint32_t uSubLeaf = 1;
1082	for (;;)
1083	{
1084	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1085	if (memcmp(auCur, auPrev, sizeof(auCur)))
1086	break;
1087
1088	/* Advance / give up. */
1089	uSubLeaf++;
1090	if (uSubLeaf >= 64)
1091	{
1092	*pcSubLeaves = 1;
1093	return false;
1094	}
1095	}
1096
1097	/* Count sub-leaves. */
1098	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1099	uint32_t cRepeats = 0;
1100	uSubLeaf = 0;
1101	for (;;)
1102	{
1103	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1104
1105	/* Figuring out when to stop isn't entirely straight forward as we need
1106	to cover undocumented behavior up to a point and implementation shortcuts. */
1107
1108	/* 1. Look for more than 4 repeating value sets. */
1109	if ( auCur[0] == auPrev[0]
1110	&& auCur[1] == auPrev[1]
1111	&& ( auCur[2] == auPrev[2]
1112	\|\| ( auCur[2] == uSubLeaf
1113	&& auPrev[2] == uSubLeaf - 1) )
1114	&& auCur[3] == auPrev[3])
1115	{
1116	if ( uLeaf != 0xd
1117	\|\| uSubLeaf >= 64
1118	\|\| ( auCur[0] == 0
1119	&& auCur[1] == 0
1120	&& auCur[2] == 0
1121	&& auCur[3] == 0
1122	&& auPrev[2] == 0) )
1123	cRepeats++;
1124	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1125	break;
1126	}
1127	else
1128	cRepeats = 0;
1129
1130	/* 2. Look for zero values. */
1131	if ( auCur[0] == 0
1132	&& auCur[1] == 0
1133	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1134	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1135	&& uSubLeaf >= cMinLeaves)
1136	{
1137	cRepeats = 0;
1138	break;
1139	}
1140
1141	/* 3. Leaf 0xb level type 0 check. */
1142	if ( uLeaf == 0xb
1143	&& (auCur[2] & 0xff00) == 0
1144	&& (auPrev[2] & 0xff00) == 0)
1145	{
1146	cRepeats = 0;
1147	break;
1148	}
1149
1150	/* 99. Give up. */
1151	if (uSubLeaf >= 128)
1152	{
1153	#ifndef IN_VBOX_CPU_REPORT
1154	/* Ok, limit it according to the documentation if possible just to
1155	avoid annoying users with these detection issues. */
1156	uint32_t cDocLimit = UINT32_MAX;
1157	if (uLeaf == 0x4)
1158	cDocLimit = 4;
1159	else if (uLeaf == 0x7)
1160	cDocLimit = 1;
1161	else if (uLeaf == 0xd)
1162	cDocLimit = 63;
1163	else if (uLeaf == 0xf)
1164	cDocLimit = 2;
1165	if (cDocLimit != UINT32_MAX)
1166	{
1167	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1168	*pcSubLeaves = cDocLimit + 3;
1169	return true;
1170	}
1171	#endif
1172	*pcSubLeaves = UINT32_MAX;
1173	return true;
1174	}
1175
1176	/* Advance. */
1177	uSubLeaf++;
1178	memcpy(auPrev, auCur, sizeof(auCur));
1179	}
1180
1181	/* Standard exit. */
1182	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1183	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1184	if (*pcSubLeaves == 0)
1185	*pcSubLeaves = 1;
1186	return true;
1187	}
1188
1189
1190	/**
1191	* Gets a CPU ID leaf.
1192	*
1193	* @returns VBox status code.
1194	* @param pVM The cross context VM structure.
1195	* @param pLeaf Where to store the found leaf.
1196	* @param uLeaf The leaf to locate.
1197	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1198	*/
1199	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1200	{
1201	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1202	uLeaf, uSubLeaf);
1203	if (pcLeaf)
1204	{
1205	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1206	return VINF_SUCCESS;
1207	}
1208
1209	return VERR_NOT_FOUND;
1210	}
1211
1212
1213	/**
1214	* Inserts a CPU ID leaf, replacing any existing ones.
1215	*
1216	* @returns VBox status code.
1217	* @param pVM The cross context VM structure.
1218	* @param pNewLeaf Pointer to the leaf being inserted.
1219	*/
1220	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1221	{
1222	/*
1223	* Validate parameters.
1224	*/
1225	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1226	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1227
1228	/*
1229	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1230	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1231	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1232	*/
1233	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1234	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1235	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1236	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1237	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1238	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1239	{
1240	return VERR_NOT_SUPPORTED;
1241	}
1242
1243	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1244	}
1245
1246	/**
1247	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1248	*
1249	* @returns VBox status code.
1250	* @param ppaLeaves Where to return the array pointer on success.
1251	* Use RTMemFree to release.
1252	* @param pcLeaves Where to return the size of the array on
1253	* success.
1254	*/
1255	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1256	{
1257	*ppaLeaves = NULL;
1258	*pcLeaves = 0;
1259
1260	/*
1261	* Try out various candidates. This must be sorted!
1262	*/
1263	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1264	{
1265	{ UINT32_C(0x00000000), false },
1266	{ UINT32_C(0x10000000), false },
1267	{ UINT32_C(0x20000000), false },
1268	{ UINT32_C(0x30000000), false },
1269	{ UINT32_C(0x40000000), false },
1270	{ UINT32_C(0x50000000), false },
1271	{ UINT32_C(0x60000000), false },
1272	{ UINT32_C(0x70000000), false },
1273	{ UINT32_C(0x80000000), false },
1274	{ UINT32_C(0x80860000), false },
1275	{ UINT32_C(0x8ffffffe), true },
1276	{ UINT32_C(0x8fffffff), true },
1277	{ UINT32_C(0x90000000), false },
1278	{ UINT32_C(0xa0000000), false },
1279	{ UINT32_C(0xb0000000), false },
1280	{ UINT32_C(0xc0000000), false },
1281	{ UINT32_C(0xd0000000), false },
1282	{ UINT32_C(0xe0000000), false },
1283	{ UINT32_C(0xf0000000), false },
1284	};
1285
1286	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1287	{
1288	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1289	uint32_t uEax, uEbx, uEcx, uEdx;
1290	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1291
1292	/*
1293	* Does EAX look like a typical leaf count value?
1294	*/
1295	if ( uEax > uLeaf
1296	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1297	{
1298	/* Yes, dump them. */
1299	uint32_t cLeaves = uEax - uLeaf + 1;
1300	while (cLeaves-- > 0)
1301	{
1302	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1303
1304	uint32_t fFlags = 0;
1305
1306	/* There are currently three known leaves containing an APIC ID
1307	that needs EMT specific attention */
1308	if (uLeaf == 1)
1309	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1310	else if (uLeaf == 0xb && uEcx != 0)
1311	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1312	else if ( uLeaf == UINT32_C(0x8000001e)
1313	&& ( uEax
1314	\|\| uEbx
1315	\|\| uEdx
1316	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1317	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1318
1319	/* The APIC bit is per-VCpu and needs flagging. */
1320	if (uLeaf == 1)
1321	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1322	else if ( uLeaf == UINT32_C(0x80000001)
1323	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1324	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1325	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1326
1327	/* Check three times here to reduce the chance of CPU migration
1328	resulting in false positives with things like the APIC ID. */
1329	uint32_t cSubLeaves;
1330	bool fFinalEcxUnchanged;
1331	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1332	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1333	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1334	{
1335	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1336	{
1337	/* This shouldn't happen. But in case it does, file all
1338	relevant details in the release log. */
1339	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1340	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1341	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1342	{
1343	uint32_t auTmp[4];
1344	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1345	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1346	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1347	}
1348	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1349	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1350	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1351	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1352	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1353	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1354	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1355	}
1356
1357	if (fFinalEcxUnchanged)
1358	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1359
1360	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1361	{
1362	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1363	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1364	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1365	if (RT_FAILURE(rc))
1366	return rc;
1367	}
1368	}
1369	else
1370	{
1371	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1372	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1373	if (RT_FAILURE(rc))
1374	return rc;
1375	}
1376
1377	/* next */
1378	uLeaf++;
1379	}
1380	}
1381	/*
1382	* Special CPUIDs needs special handling as they don't follow the
1383	* leaf count principle used above.
1384	*/
1385	else if (s_aCandidates[iOuter].fSpecial)
1386	{
1387	bool fKeep = false;
1388	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1389	fKeep = true;
1390	else if ( uLeaf == 0x8fffffff
1391	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1392	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1393	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1394	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1395	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1396	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1397	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1398	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1399	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1400	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1401	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1402	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1403	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1404	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1405	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1406	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1407	fKeep = true;
1408	if (fKeep)
1409	{
1410	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1411	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1412	if (RT_FAILURE(rc))
1413	return rc;
1414	}
1415	}
1416	}
1417
1418	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1419	return VINF_SUCCESS;
1420	}
1421
1422
1423	/**
1424	* Determines the method the CPU uses to handle unknown CPUID leaves.
1425	*
1426	* @returns VBox status code.
1427	* @param penmUnknownMethod Where to return the method.
1428	* @param pDefUnknown Where to return default unknown values. This
1429	* will be set, even if the resulting method
1430	* doesn't actually needs it.
1431	*/
1432	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1433	{
1434	uint32_t uLastStd = ASMCpuId_EAX(0);
1435	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1436	if (!ASMIsValidExtRange(uLastExt))
1437	uLastExt = 0x80000000;
1438
1439	uint32_t auChecks[] =
1440	{
1441	uLastStd + 1,
1442	uLastStd + 5,
1443	uLastStd + 8,
1444	uLastStd + 32,
1445	uLastStd + 251,
1446	uLastExt + 1,
1447	uLastExt + 8,
1448	uLastExt + 15,
1449	uLastExt + 63,
1450	uLastExt + 255,
1451	0x7fbbffcc,
1452	0x833f7872,
1453	0xefff2353,
1454	0x35779456,
1455	0x1ef6d33e,
1456	};
1457
1458	static const uint32_t s_auValues[] =
1459	{
1460	0xa95d2156,
1461	0x00000001,
1462	0x00000002,
1463	0x00000008,
1464	0x00000000,
1465	0x55773399,
1466	0x93401769,
1467	0x12039587,
1468	};
1469
1470	/*
1471	* Simple method, all zeros.
1472	*/
1473	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1474	pDefUnknown->uEax = 0;
1475	pDefUnknown->uEbx = 0;
1476	pDefUnknown->uEcx = 0;
1477	pDefUnknown->uEdx = 0;
1478
1479	/*
1480	* Intel has been observed returning the last standard leaf.
1481	*/
1482	uint32_t auLast[4];
1483	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1484
1485	uint32_t cChecks = RT_ELEMENTS(auChecks);
1486	while (cChecks > 0)
1487	{
1488	uint32_t auCur[4];
1489	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1490	if (memcmp(auCur, auLast, sizeof(auCur)))
1491	break;
1492	cChecks--;
1493	}
1494	if (cChecks == 0)
1495	{
1496	/* Now, what happens when the input changes? Esp. ECX. */
1497	uint32_t cTotal = 0;
1498	uint32_t cSame = 0;
1499	uint32_t cLastWithEcx = 0;
1500	uint32_t cNeither = 0;
1501	uint32_t cValues = RT_ELEMENTS(s_auValues);
1502	while (cValues > 0)
1503	{
1504	uint32_t uValue = s_auValues[cValues - 1];
1505	uint32_t auLastWithEcx[4];
1506	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1507	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1508
1509	cChecks = RT_ELEMENTS(auChecks);
1510	while (cChecks > 0)
1511	{
1512	uint32_t auCur[4];
1513	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1514	if (!memcmp(auCur, auLast, sizeof(auCur)))
1515	{
1516	cSame++;
1517	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1518	cLastWithEcx++;
1519	}
1520	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1521	cLastWithEcx++;
1522	else
1523	cNeither++;
1524	cTotal++;
1525	cChecks--;
1526	}
1527	cValues--;
1528	}
1529
1530	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1531	if (cSame == cTotal)
1532	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1533	else if (cLastWithEcx == cTotal)
1534	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1535	else
1536	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1537	pDefUnknown->uEax = auLast[0];
1538	pDefUnknown->uEbx = auLast[1];
1539	pDefUnknown->uEcx = auLast[2];
1540	pDefUnknown->uEdx = auLast[3];
1541	return VINF_SUCCESS;
1542	}
1543
1544	/*
1545	* Unchanged register values?
1546	*/
1547	cChecks = RT_ELEMENTS(auChecks);
1548	while (cChecks > 0)
1549	{
1550	uint32_t const uLeaf = auChecks[cChecks - 1];
1551	uint32_t cValues = RT_ELEMENTS(s_auValues);
1552	while (cValues > 0)
1553	{
1554	uint32_t uValue = s_auValues[cValues - 1];
1555	uint32_t auCur[4];
1556	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1557	if ( auCur[0] != uLeaf
1558	\|\| auCur[1] != uValue
1559	\|\| auCur[2] != uValue
1560	\|\| auCur[3] != uValue)
1561	break;
1562	cValues--;
1563	}
1564	if (cValues != 0)
1565	break;
1566	cChecks--;
1567	}
1568	if (cChecks == 0)
1569	{
1570	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1571	return VINF_SUCCESS;
1572	}
1573
1574	/*
1575	* Just go with the simple method.
1576	*/
1577	return VINF_SUCCESS;
1578	}
1579
1580
1581	/**
1582	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1583	*
1584	* @returns Read only name string.
1585	* @param enmUnknownMethod The method to translate.
1586	*/
1587	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1588	{
1589	switch (enmUnknownMethod)
1590	{
1591	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1592	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1593	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1594	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1595
1596	case CPUMUNKNOWNCPUID_INVALID:
1597	case CPUMUNKNOWNCPUID_END:
1598	case CPUMUNKNOWNCPUID_32BIT_HACK:
1599	break;
1600	}
1601	return "Invalid-unknown-CPUID-method";
1602	}
1603
1604
1605	/**
1606	* Detect the CPU vendor give n the
1607	*
1608	* @returns The vendor.
1609	* @param uEAX EAX from CPUID(0).
1610	* @param uEBX EBX from CPUID(0).
1611	* @param uECX ECX from CPUID(0).
1612	* @param uEDX EDX from CPUID(0).
1613	*/
1614	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1615	{
1616	if (ASMIsValidStdRange(uEAX))
1617	{
1618	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1619	return CPUMCPUVENDOR_AMD;
1620
1621	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1622	return CPUMCPUVENDOR_INTEL;
1623
1624	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1625	return CPUMCPUVENDOR_VIA;
1626
1627	if (ASMIsShanghaiCpuEx(uEBX, uECX, uEDX))
1628	return CPUMCPUVENDOR_SHANGHAI;
1629
1630	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1631	&& uECX == UINT32_C(0x64616574)
1632	&& uEDX == UINT32_C(0x736E4978))
1633	return CPUMCPUVENDOR_CYRIX;
1634
1635	/* "Geode by NSC", example: family 5, model 9. */
1636
1637	/** @todo detect the other buggers... */
1638	}
1639
1640	return CPUMCPUVENDOR_UNKNOWN;
1641	}
1642
1643
1644	/**
1645	* Translates a CPU vendor enum value into the corresponding string constant.
1646	*
1647	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1648	* value name. This can be useful when generating code.
1649	*
1650	* @returns Read only name string.
1651	* @param enmVendor The CPU vendor value.
1652	*/
1653	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1654	{
1655	switch (enmVendor)
1656	{
1657	case CPUMCPUVENDOR_INTEL: return "INTEL";
1658	case CPUMCPUVENDOR_AMD: return "AMD";
1659	case CPUMCPUVENDOR_VIA: return "VIA";
1660	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1661	case CPUMCPUVENDOR_SHANGHAI: return "SHANGHAI";
1662	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1663
1664	case CPUMCPUVENDOR_INVALID:
1665	case CPUMCPUVENDOR_32BIT_HACK:
1666	break;
1667	}
1668	return "Invalid-cpu-vendor";
1669	}
1670
1671
1672	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1673	{
1674	/* Could do binary search, doing linear now because I'm lazy. */
1675	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1676	while (cLeaves-- > 0)
1677	{
1678	if (pLeaf->uLeaf == uLeaf)
1679	return pLeaf;
1680	pLeaf++;
1681	}
1682	return NULL;
1683	}
1684
1685
1686	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1687	{
1688	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1689	if ( !pLeaf
1690	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1691	return pLeaf;
1692
1693	/* Linear sub-leaf search. Lazy as usual. */
1694	cLeaves -= pLeaf - paLeaves;
1695	while ( cLeaves-- > 0
1696	&& pLeaf->uLeaf == uLeaf)
1697	{
1698	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1699	return pLeaf;
1700	pLeaf++;
1701	}
1702
1703	return NULL;
1704	}
1705
1706
1707	static void cpumR3ExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURES pFeatures)
1708	{
1709	Assert(pVmxMsrs);
1710	Assert(pFeatures);
1711	Assert(pFeatures->fVmx);
1712
1713	/* Basic information. */
1714	{
1715	uint64_t const u64Basic = pVmxMsrs->u64Basic;
1716	pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1717	}
1718
1719	/* Pin-based VM-execution controls. */
1720	{
1721	uint32_t const fPinCtls = pVmxMsrs->PinCtls.n.allowed1;
1722	pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1723	pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1724	pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1725	pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1726	pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1727	}
1728
1729	/* Processor-based VM-execution controls. */
1730	{
1731	uint32_t const fProcCtls = pVmxMsrs->ProcCtls.n.allowed1;
1732	pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1733	pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1734	pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1735	pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1736	pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1737	pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1738	pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1739	pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1740	pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1741	pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1742	pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1743	pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1744	pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1745	pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1746	pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1747	pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1748	pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1749	pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1750	pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1751	pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1752	pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1753	}
1754
1755	/* Secondary processor-based VM-execution controls. */
1756	{
1757	uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1758	pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1759	pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1760	pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1761	pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1762	pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1763	pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1764	pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1765	pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1766	pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1767	pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1768	pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1769	pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1770	pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1771	pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1772	pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1773	pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1774	pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1775	pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_VE);
1776	pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1777	pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1778	}
1779
1780	/* VM-exit controls. */
1781	{
1782	uint32_t const fExitCtls = pVmxMsrs->ExitCtls.n.allowed1;
1783	pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1784	pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1785	pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1786	pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1787	pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1788	pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1789	pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1790	pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1791	}
1792
1793	/* VM-entry controls. */
1794	{
1795	uint32_t const fEntryCtls = pVmxMsrs->EntryCtls.n.allowed1;
1796	pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1797	pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1798	pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1799	pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1800	}
1801
1802	/* Miscellaneous data. */
1803	{
1804	uint32_t const fMiscData = pVmxMsrs->u64Misc;
1805	pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1806	pFeatures->fVmxIntelPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1807	pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1808	pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1809	}
1810	}
1811
1812
1813	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures)
1814	{
1815	Assert(pMsrs);
1816	RT_ZERO(*pFeatures);
1817	if (cLeaves >= 2)
1818	{
1819	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1820	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1821	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1822	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1823	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1824	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1825
1826	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1827	pStd0Leaf->uEbx,
1828	pStd0Leaf->uEcx,
1829	pStd0Leaf->uEdx);
1830	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1831	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1832	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1833	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1834	pFeatures->uFamily,
1835	pFeatures->uModel,
1836	pFeatures->uStepping);
1837
1838	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1839	if (pExtLeaf8)
1840	{
1841	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1842	pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1843	}
1844	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1845	{
1846	pFeatures->cMaxPhysAddrWidth = 36;
1847	pFeatures->cMaxLinearAddrWidth = 36;
1848	}
1849	else
1850	{
1851	pFeatures->cMaxPhysAddrWidth = 32;
1852	pFeatures->cMaxLinearAddrWidth = 32;
1853	}
1854
1855	/* Standard features. */
1856	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1857	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1858	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1859	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1860	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1861	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1862	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1863	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1864	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1865	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1866	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1867	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1868	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1869	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1870	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1871	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1872	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1873	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1874	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1875	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1876	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1877	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1878	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1879	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1880	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1881	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1882	if (pFeatures->fVmx)
1883	cpumR3ExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1884
1885	/* Structured extended features. */
1886	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1887	if (pSxfLeaf0)
1888	{
1889	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1890	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1891	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1892	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1893	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1894
1895	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1896	pFeatures->fIbrs = pFeatures->fIbpb;
1897	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1898	pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
1899	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1900	pFeatures->fMdsClear = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
1901	}
1902
1903	/* MWAIT/MONITOR leaf. */
1904	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1905	if (pMWaitLeaf)
1906	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1907	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1908
1909	/* Extended features. */
1910	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1911	if (pExtLeaf)
1912	{
1913	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1914	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1915	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1916	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1917	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1918	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1919	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1920	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1921	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1922	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1923	}
1924
1925	/* VMX (VMXON, VMCS region and related data structures) physical address width (depends on long-mode). */
1926	pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
1927
1928	if ( pExtLeaf
1929	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1930	{
1931	/* AMD features. */
1932	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1933	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1934	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1935	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1936	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1937	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1938	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1939	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1940	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1941	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1942	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1943	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1944	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1945	if (pFeatures->fSvm)
1946	{
1947	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1948	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1949	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1950	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1951	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1952	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1953	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1954	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1955	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1956	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1957	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1958	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1959	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1960	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1961	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1962	pFeatures->fSvmGmet = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_GMET);
1963	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1964	}
1965	}
1966
1967	/*
1968	* Quirks.
1969	*/
1970	pFeatures->fLeakyFxSR = pExtLeaf
1971	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1972	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1973	&& pFeatures->uFamily >= 6 /* K7 and up */;
1974
1975	/*
1976	* Max extended (/FPU) state.
1977	*/
1978	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1979	if (pFeatures->fXSaveRstor)
1980	{
1981	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1982	if (pXStateLeaf0)
1983	{
1984	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1985	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1986	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1987	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1988	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1989	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1990	{
1991	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1992
1993	/* (paranoia:) */
1994	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1995	if ( pXStateLeaf1
1996	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1997	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1998	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1999	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
2000	}
2001	else
2002	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
2003	pFeatures->fXSaveRstor = 0);
2004	}
2005	else
2006	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
2007	pFeatures->fXSaveRstor = 0);
2008	}
2009	}
2010	else
2011	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
2012	return VINF_SUCCESS;
2013	}
2014
2015
2016	/*
2017	*
2018	* Init related code.
2019	* Init related code.
2020	* Init related code.
2021	*
2022	*
2023	*/
2024	#ifndef IN_VBOX_CPU_REPORT
2025
2026
2027	/**
2028	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
2029	*
2030	* This ignores the fSubLeafMask.
2031	*
2032	* @returns Pointer to the matching leaf, or NULL if not found.
2033	* @param pCpum The CPUM instance data.
2034	* @param uLeaf The leaf to locate.
2035	* @param uSubLeaf The subleaf to locate.
2036	*/
2037	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
2038	{
2039	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
2040	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
2041	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
2042	if (iEnd)
2043	{
2044	uint32_t iBegin = 0;
2045	for (;;)
2046	{
2047	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
2048	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
2049	if (uNeedle < uCur)
2050	{
2051	if (i > iBegin)
2052	iEnd = i;
2053	else
2054	break;
2055	}
2056	else if (uNeedle > uCur)
2057	{
2058	if (i + 1 < iEnd)
2059	iBegin = i + 1;
2060	else
2061	break;
2062	}
2063	else
2064	return &paLeaves[i];
2065	}
2066	}
2067	return NULL;
2068	}
2069
2070
2071	/**
2072	* Loads MSR range overrides.
2073	*
2074	* This must be called before the MSR ranges are moved from the normal heap to
2075	* the hyper heap!
2076	*
2077	* @returns VBox status code (VMSetError called).
2078	* @param pVM The cross context VM structure.
2079	* @param pMsrNode The CFGM node with the MSR overrides.
2080	*/
2081	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
2082	{
2083	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2084	{
2085	/*
2086	* Assemble a valid MSR range.
2087	*/
2088	CPUMMSRRANGE MsrRange;
2089	MsrRange.offCpumCpu = 0;
2090	MsrRange.fReserved = 0;
2091
2092	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
2093	if (RT_FAILURE(rc))
2094	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
2095
2096	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
2097	if (RT_FAILURE(rc))
2098	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
2099	MsrRange.szName, rc);
2100
2101	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
2102	if (RT_FAILURE(rc))
2103	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
2104	MsrRange.szName, rc);
2105
2106	char szType[32];
2107	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
2108	if (RT_FAILURE(rc))
2109	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
2110	MsrRange.szName, rc);
2111	if (!RTStrICmp(szType, "FixedValue"))
2112	{
2113	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
2114	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
2115
2116	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
2117	if (RT_FAILURE(rc))
2118	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
2119	MsrRange.szName, rc);
2120
2121	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
2122	if (RT_FAILURE(rc))
2123	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
2124	MsrRange.szName, rc);
2125
2126	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
2127	if (RT_FAILURE(rc))
2128	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
2129	MsrRange.szName, rc);
2130	}
2131	else
2132	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
2133	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
2134
2135	/*
2136	* Insert the range into the table (replaces/splits/shrinks existing
2137	* MSR ranges).
2138	*/
2139	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
2140	&MsrRange);
2141	if (RT_FAILURE(rc))
2142	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
2143	}
2144
2145	return VINF_SUCCESS;
2146	}
2147
2148
2149	/**
2150	* Loads CPUID leaf overrides.
2151	*
2152	* This must be called before the CPUID leaves are moved from the normal
2153	* heap to the hyper heap!
2154	*
2155	* @returns VBox status code (VMSetError called).
2156	* @param pVM The cross context VM structure.
2157	* @param pParentNode The CFGM node with the CPUID leaves.
2158	* @param pszLabel How to label the overrides we're loading.
2159	*/
2160	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2161	{
2162	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2163	{
2164	/*
2165	* Get the leaf and subleaf numbers.
2166	*/
2167	char szName[128];
2168	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2169	if (RT_FAILURE(rc))
2170	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2171
2172	/* The leaf number is either specified directly or thru the node name. */
2173	uint32_t uLeaf;
2174	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2175	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2176	{
2177	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2178	if (rc != VINF_SUCCESS)
2179	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2180	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2181	}
2182	else if (RT_FAILURE(rc))
2183	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2184	pszLabel, szName, rc);
2185
2186	uint32_t uSubLeaf;
2187	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2188	if (RT_FAILURE(rc))
2189	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2190	pszLabel, szName, rc);
2191
2192	uint32_t fSubLeafMask;
2193	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2194	if (RT_FAILURE(rc))
2195	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2196	pszLabel, szName, rc);
2197
2198	/*
2199	* Look up the specified leaf, since the output register values
2200	* defaults to any existing values. This allows overriding a single
2201	* register, without needing to know the other values.
2202	*/
2203	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2204	CPUMCPUIDLEAF Leaf;
2205	if (pLeaf)
2206	Leaf = *pLeaf;
2207	else
2208	RT_ZERO(Leaf);
2209	Leaf.uLeaf = uLeaf;
2210	Leaf.uSubLeaf = uSubLeaf;
2211	Leaf.fSubLeafMask = fSubLeafMask;
2212
2213	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2214	if (RT_FAILURE(rc))
2215	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2216	pszLabel, szName, rc);
2217	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2218	if (RT_FAILURE(rc))
2219	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2220	pszLabel, szName, rc);
2221	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2222	if (RT_FAILURE(rc))
2223	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2224	pszLabel, szName, rc);
2225	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2226	if (RT_FAILURE(rc))
2227	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2228	pszLabel, szName, rc);
2229
2230	/*
2231	* Insert the leaf into the table (replaces existing ones).
2232	*/
2233	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2234	&Leaf);
2235	if (RT_FAILURE(rc))
2236	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2237	}
2238
2239	return VINF_SUCCESS;
2240	}
2241
2242
2243
2244	/**
2245	* Fetches overrides for a CPUID leaf.
2246	*
2247	* @returns VBox status code.
2248	* @param pLeaf The leaf to load the overrides into.
2249	* @param pCfgNode The CFGM node containing the overrides
2250	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2251	* @param iLeaf The CPUID leaf number.
2252	*/
2253	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2254	{
2255	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2256	if (pLeafNode)
2257	{
2258	uint32_t u32;
2259	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2260	if (RT_SUCCESS(rc))
2261	pLeaf->uEax = u32;
2262	else
2263	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2264
2265	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2266	if (RT_SUCCESS(rc))
2267	pLeaf->uEbx = u32;
2268	else
2269	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2270
2271	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2272	if (RT_SUCCESS(rc))
2273	pLeaf->uEcx = u32;
2274	else
2275	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2276
2277	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2278	if (RT_SUCCESS(rc))
2279	pLeaf->uEdx = u32;
2280	else
2281	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2282
2283	}
2284	return VINF_SUCCESS;
2285	}
2286
2287
2288	/**
2289	* Load the overrides for a set of CPUID leaves.
2290	*
2291	* @returns VBox status code.
2292	* @param paLeaves The leaf array.
2293	* @param cLeaves The number of leaves.
2294	* @param uStart The start leaf number.
2295	* @param pCfgNode The CFGM node containing the overrides
2296	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2297	*/
2298	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2299	{
2300	for (uint32_t i = 0; i < cLeaves; i++)
2301	{
2302	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2303	if (RT_FAILURE(rc))
2304	return rc;
2305	}
2306
2307	return VINF_SUCCESS;
2308	}
2309
2310
2311	/**
2312	* Installs the CPUID leaves and explods the data into structures like
2313	* GuestFeatures and CPUMCTX::aoffXState.
2314	*
2315	* @returns VBox status code.
2316	* @param pVM The cross context VM structure.
2317	* @param pCpum The CPUM part of @a VM.
2318	* @param paLeaves The leaves. These will be copied (but not freed).
2319	* @param cLeaves The number of leaves.
2320	* @param pMsrs The MSRs.
2321	*/
2322	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
2323	{
2324	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2325
2326	/*
2327	* Install the CPUID information.
2328	*/
2329	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2330	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2331
2332	AssertLogRelRCReturn(rc, rc);
2333	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2334	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2335	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2336
2337	/*
2338	* Update the default CPUID leaf if necessary.
2339	*/
2340	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2341	{
2342	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2343	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2344	{
2345	/* We don't use CPUID(0).eax here because of the NT hack that only
2346	changes that value without actually removing any leaves. */
2347	uint32_t i = 0;
2348	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2349	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2350	{
2351	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2352	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2353	i++;
2354	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2355	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2356	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2357	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2358	}
2359	break;
2360	}
2361	default:
2362	break;
2363	}
2364
2365	/*
2366	* Explode the guest CPU features.
2367	*/
2368	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
2369	&pCpum->GuestFeatures);
2370	AssertLogRelRCReturn(rc, rc);
2371
2372	/*
2373	* Adjust the scalable bus frequency according to the CPUID information
2374	* we're now using.
2375	*/
2376	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2377	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2378	? UINT64_C(100000000) /* 100MHz */
2379	: UINT64_C(133333333); /* 133MHz */
2380
2381	/*
2382	* Populate the legacy arrays. Currently used for everything, later only
2383	* for patch manager.
2384	*/
2385	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2386	{
2387	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2388	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2389	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2390	};
2391	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2392	{
2393	uint32_t cLeft = aOldRanges[i].cCpuIds;
2394	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2395	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2396	while (cLeft-- > 0)
2397	{
2398	uLeaf--;
2399	pLegacyLeaf--;
2400
2401	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2402	if (pLeaf)
2403	{
2404	pLegacyLeaf->uEax = pLeaf->uEax;
2405	pLegacyLeaf->uEbx = pLeaf->uEbx;
2406	pLegacyLeaf->uEcx = pLeaf->uEcx;
2407	pLegacyLeaf->uEdx = pLeaf->uEdx;
2408	}
2409	else
2410	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2411	}
2412	}
2413
2414	/*
2415	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2416	*/
2417	PVMCPU pVCpu0 = pVM->apCpusR3[0];
2418	memset(&pVCpu0->cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2419	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2420	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2421	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2422	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2423	{
2424	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2425	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2426	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2427	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2428	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2429	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2430	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2431	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2432	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2433	pCpum->GuestFeatures.cbMaxExtendedState),
2434	VERR_CPUM_IPE_1);
2435	pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2436	}
2437
2438	/* Copy the CPU #0 data to the other CPUs. */
2439	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
2440	{
2441	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2442	memcpy(&pVCpu->cpum.s.Guest.aoffXState[0], &pVCpu0->cpum.s.Guest.aoffXState[0], sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2443	}
2444
2445	return VINF_SUCCESS;
2446	}
2447
2448
2449	/** @name Instruction Set Extension Options
2450	* @{ */
2451	/** Configuration option type (extended boolean, really). */
2452	typedef uint8_t CPUMISAEXTCFG;
2453	/** Always disable the extension. */
2454	#define CPUMISAEXTCFG_DISABLED false
2455	/** Enable the extension if it's supported by the host CPU. */
2456	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2457	/** Enable the extension if it's supported by the host CPU, but don't let
2458	* the portable CPUID feature disable it. */
2459	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2460	/** Always enable the extension. */
2461	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2462	/** @} */
2463
2464	/**
2465	* CPUID Configuration (from CFGM).
2466	*
2467	* @remarks The members aren't document since we would only be duplicating the
2468	* \@cfgm entries in cpumR3CpuIdReadConfig.
2469	*/
2470	typedef struct CPUMCPUIDCONFIG
2471	{
2472	bool fNt4LeafLimit;
2473	bool fInvariantTsc;
2474	bool fForceVme;
2475	bool fNestedHWVirt;
2476
2477	CPUMISAEXTCFG enmCmpXchg16b;
2478	CPUMISAEXTCFG enmMonitor;
2479	CPUMISAEXTCFG enmMWaitExtensions;
2480	CPUMISAEXTCFG enmSse41;
2481	CPUMISAEXTCFG enmSse42;
2482	CPUMISAEXTCFG enmAvx;
2483	CPUMISAEXTCFG enmAvx2;
2484	CPUMISAEXTCFG enmXSave;
2485	CPUMISAEXTCFG enmAesNi;
2486	CPUMISAEXTCFG enmPClMul;
2487	CPUMISAEXTCFG enmPopCnt;
2488	CPUMISAEXTCFG enmMovBe;
2489	CPUMISAEXTCFG enmRdRand;
2490	CPUMISAEXTCFG enmRdSeed;
2491	CPUMISAEXTCFG enmCLFlushOpt;
2492	CPUMISAEXTCFG enmFsGsBase;
2493	CPUMISAEXTCFG enmPcid;
2494	CPUMISAEXTCFG enmInvpcid;
2495	CPUMISAEXTCFG enmFlushCmdMsr;
2496	CPUMISAEXTCFG enmMdsClear;
2497	CPUMISAEXTCFG enmArchCapMsr;
2498
2499	CPUMISAEXTCFG enmAbm;
2500	CPUMISAEXTCFG enmSse4A;
2501	CPUMISAEXTCFG enmMisAlnSse;
2502	CPUMISAEXTCFG enm3dNowPrf;
2503	CPUMISAEXTCFG enmAmdExtMmx;
2504
2505	uint32_t uMaxStdLeaf;
2506	uint32_t uMaxExtLeaf;
2507	uint32_t uMaxCentaurLeaf;
2508	uint32_t uMaxIntelFamilyModelStep;
2509	char szCpuName[128];
2510	} CPUMCPUIDCONFIG;
2511	/** Pointer to CPUID config (from CFGM). */
2512	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2513
2514
2515	/**
2516	* Mini CPU selection support for making Mac OS X happy.
2517	*
2518	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2519	*
2520	* @param pCpum The CPUM instance data.
2521	* @param pConfig The CPUID configuration we've read from CFGM.
2522	*/
2523	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2524	{
2525	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2526	{
2527	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2528	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2529	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2530	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2531	0);
2532	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2533	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2534	{
2535	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2536	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2537	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2538	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2539	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2540	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2541	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2542	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2543	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2544	pStdFeatureLeaf->uEax = uNew;
2545	}
2546	}
2547	}
2548
2549
2550
2551	/**
2552	* Limit it the number of entries, zapping the remainder.
2553	*
2554	* The limits are masking off stuff about power saving and similar, this
2555	* is perhaps a bit crudely done as there is probably some relatively harmless
2556	* info too in these leaves (like words about having a constant TSC).
2557	*
2558	* @param pCpum The CPUM instance data.
2559	* @param pConfig The CPUID configuration we've read from CFGM.
2560	*/
2561	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2562	{
2563	/*
2564	* Standard leaves.
2565	*/
2566	uint32_t uSubLeaf = 0;
2567	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2568	if (pCurLeaf)
2569	{
2570	uint32_t uLimit = pCurLeaf->uEax;
2571	if (uLimit <= UINT32_C(0x000fffff))
2572	{
2573	if (uLimit > pConfig->uMaxStdLeaf)
2574	{
2575	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2576	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2577	uLimit + 1, UINT32_C(0x000fffff));
2578	}
2579
2580	/* NT4 hack, no zapping of extra leaves here. */
2581	if (pConfig->fNt4LeafLimit && uLimit > 3)
2582	pCurLeaf->uEax = uLimit = 3;
2583
2584	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2585	pCurLeaf->uEax = uLimit;
2586	}
2587	else
2588	{
2589	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2590	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2591	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2592	}
2593	}
2594
2595	/*
2596	* Extended leaves.
2597	*/
2598	uSubLeaf = 0;
2599	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2600	if (pCurLeaf)
2601	{
2602	uint32_t uLimit = pCurLeaf->uEax;
2603	if ( uLimit >= UINT32_C(0x80000000)
2604	&& uLimit <= UINT32_C(0x800fffff))
2605	{
2606	if (uLimit > pConfig->uMaxExtLeaf)
2607	{
2608	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2609	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2610	uLimit + 1, UINT32_C(0x800fffff));
2611	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2612	pCurLeaf->uEax = uLimit;
2613	}
2614	}
2615	else
2616	{
2617	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2618	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2619	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2620	}
2621	}
2622
2623	/*
2624	* Centaur leaves (VIA).
2625	*/
2626	uSubLeaf = 0;
2627	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2628	if (pCurLeaf)
2629	{
2630	uint32_t uLimit = pCurLeaf->uEax;
2631	if ( uLimit >= UINT32_C(0xc0000000)
2632	&& uLimit <= UINT32_C(0xc00fffff))
2633	{
2634	if (uLimit > pConfig->uMaxCentaurLeaf)
2635	{
2636	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2637	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2638	uLimit + 1, UINT32_C(0xcfffffff));
2639	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2640	pCurLeaf->uEax = uLimit;
2641	}
2642	}
2643	else
2644	{
2645	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2646	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2647	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2648	}
2649	}
2650	}
2651
2652
2653	/**
2654	* Clears a CPUID leaf and all sub-leaves (to zero).
2655	*
2656	* @param pCpum The CPUM instance data.
2657	* @param uLeaf The leaf to clear.
2658	*/
2659	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2660	{
2661	uint32_t uSubLeaf = 0;
2662	PCPUMCPUIDLEAF pCurLeaf;
2663	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2664	{
2665	pCurLeaf->uEax = 0;
2666	pCurLeaf->uEbx = 0;
2667	pCurLeaf->uEcx = 0;
2668	pCurLeaf->uEdx = 0;
2669	uSubLeaf++;
2670	}
2671	}
2672
2673
2674	/**
2675	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2676	* the given leaf.
2677	*
2678	* @returns pLeaf.
2679	* @param pCpum The CPUM instance data.
2680	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2681	*/
2682	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2683	{
2684	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2685	if (pLeaf->fSubLeafMask != 0)
2686	{
2687	/*
2688	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2689	* Log everything while we're at it.
2690	*/
2691	LogRel(("CPUM:\n"
2692	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2693	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2694	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2695	for (;;)
2696	{
2697	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2698	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2699	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2700	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2701	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2702	break;
2703	pSubLeaf++;
2704	}
2705	LogRel(("CPUM:\n"));
2706
2707	/*
2708	* Remove the offending sub-leaves.
2709	*/
2710	if (pSubLeaf != pLeaf)
2711	{
2712	if (pSubLeaf != pLast)
2713	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2714	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2715	}
2716
2717	/*
2718	* Convert the first sub-leaf into a single leaf.
2719	*/
2720	pLeaf->uSubLeaf = 0;
2721	pLeaf->fSubLeafMask = 0;
2722	}
2723	return pLeaf;
2724	}
2725
2726
2727	/**
2728	* Sanitizes and adjust the CPUID leaves.
2729	*
2730	* Drop features that aren't virtualized (or virtualizable). Adjust information
2731	* and capabilities to fit the virtualized hardware. Remove information the
2732	* guest shouldn't have (because it's wrong in the virtual world or because it
2733	* gives away host details) or that we don't have documentation for and no idea
2734	* what means.
2735	*
2736	* @returns VBox status code.
2737	* @param pVM The cross context VM structure (for cCpus).
2738	* @param pCpum The CPUM instance data.
2739	* @param pConfig The CPUID configuration we've read from CFGM.
2740	*/
2741	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2742	{
2743	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2744	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2745	{ \
2746	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2747	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2748	}
2749	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2750	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2751	{ \
2752	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2753	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2754	}
2755	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2756	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2757	&& ((a_pLeafReg) & (fBitMask)) \
2758	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2759	{ \
2760	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2761	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2762	}
2763	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2764
2765	/* Cpuid 1:
2766	* EAX: CPU model, family and stepping.
2767	*
2768	* ECX + EDX: Supported features. Only report features we can support.
2769	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2770	* options may require adjusting (i.e. stripping what was enabled).
2771	*
2772	* EBX: Branding, CLFLUSH line size, logical processors per package and
2773	* initial APIC ID.
2774	*/
2775	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2776	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2777	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2778
2779	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2780	\| X86_CPUID_FEATURE_EDX_VME
2781	\| X86_CPUID_FEATURE_EDX_DE
2782	\| X86_CPUID_FEATURE_EDX_PSE
2783	\| X86_CPUID_FEATURE_EDX_TSC
2784	\| X86_CPUID_FEATURE_EDX_MSR
2785	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2786	\| X86_CPUID_FEATURE_EDX_MCE
2787	\| X86_CPUID_FEATURE_EDX_CX8
2788	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2789	//\| RT_BIT_32(10) - not defined
2790	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2791	//\| X86_CPUID_FEATURE_EDX_SEP
2792	\| X86_CPUID_FEATURE_EDX_MTRR
2793	\| X86_CPUID_FEATURE_EDX_PGE
2794	\| X86_CPUID_FEATURE_EDX_MCA
2795	\| X86_CPUID_FEATURE_EDX_CMOV
2796	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2797	\| X86_CPUID_FEATURE_EDX_PSE36
2798	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2799	\| X86_CPUID_FEATURE_EDX_CLFSH
2800	//\| RT_BIT_32(20) - not defined
2801	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2802	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2803	\| X86_CPUID_FEATURE_EDX_MMX
2804	\| X86_CPUID_FEATURE_EDX_FXSR
2805	\| X86_CPUID_FEATURE_EDX_SSE
2806	\| X86_CPUID_FEATURE_EDX_SSE2
2807	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2808	\| X86_CPUID_FEATURE_EDX_HTT
2809	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2810	//\| RT_BIT_32(30) - not defined
2811	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2812	;
2813	pStdFeatureLeaf->uEcx &= 0
2814	\| X86_CPUID_FEATURE_ECX_SSE3
2815	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2816	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2817	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2818	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2819	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2820	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2821	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2822	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2823	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2824	\| X86_CPUID_FEATURE_ECX_SSSE3
2825	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2826	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2827	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2828	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2829	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2830	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2831	\| (pConfig->enmPcid ? X86_CPUID_FEATURE_ECX_PCID : 0)
2832	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2833	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2834	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2835	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2836	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2837	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2838	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2839	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2840	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2841	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2842	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2843	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2844	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2845	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2846	;
2847
2848	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2849	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2850	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2851	{
2852	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2853	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2854	}
2855
2856	if (pCpum->u8PortableCpuIdLevel > 0)
2857	{
2858	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2859	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2860	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2861	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2862	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2863	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2864	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2865	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2866	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2867	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2868	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2869	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2870	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2871	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2872	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2873	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2874	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2875	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2876	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2877	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2878
2879	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2880	\| X86_CPUID_FEATURE_EDX_PSN
2881	\| X86_CPUID_FEATURE_EDX_DS
2882	\| X86_CPUID_FEATURE_EDX_ACPI
2883	\| X86_CPUID_FEATURE_EDX_SS
2884	\| X86_CPUID_FEATURE_EDX_TM
2885	\| X86_CPUID_FEATURE_EDX_PBE
2886	)));
2887	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2888	\| X86_CPUID_FEATURE_ECX_CPLDS
2889	\| X86_CPUID_FEATURE_ECX_AES
2890	\| X86_CPUID_FEATURE_ECX_VMX
2891	\| X86_CPUID_FEATURE_ECX_SMX
2892	\| X86_CPUID_FEATURE_ECX_EST
2893	\| X86_CPUID_FEATURE_ECX_TM2
2894	\| X86_CPUID_FEATURE_ECX_CNTXID
2895	\| X86_CPUID_FEATURE_ECX_FMA
2896	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2897	\| X86_CPUID_FEATURE_ECX_PDCM
2898	\| X86_CPUID_FEATURE_ECX_DCA
2899	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2900	)));
2901	}
2902
2903	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2904	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2905
2906	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2907	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2908	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2909	*/
2910	#ifdef VBOX_WITH_MULTI_CORE
2911	if (pVM->cCpus > 1)
2912	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2913	#endif
2914	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2915	{
2916	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2917	core times the number of CPU cores per processor */
2918	#ifdef VBOX_WITH_MULTI_CORE
2919	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2920	#else
2921	/* Single logical processor in a package. */
2922	pStdFeatureLeaf->uEbx \|= (1 << 16);
2923	#endif
2924	}
2925
2926	uint32_t uMicrocodeRev;
2927	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2928	if (RT_SUCCESS(rc))
2929	{
2930	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2931	}
2932	else
2933	{
2934	uMicrocodeRev = 0;
2935	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2936	}
2937
2938	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2939	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2940	*/
2941	if ( (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen)
2942	&& uMicrocodeRev < 0x8001126
2943	&& !pConfig->fForceVme)
2944	{
2945	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2946	LogRel(("CPUM: Zen VME workaround engaged\n"));
2947	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2948	}
2949
2950	/* Force standard feature bits. */
2951	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2952	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2953	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2954	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2955	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2956	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2957	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2958	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2959	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2960	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2961	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2962	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2963	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2964	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2965	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2966	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2967	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2968	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2969	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2970	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2971	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2972	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2973
2974	pStdFeatureLeaf = NULL; /* Must refetch! */
2975
2976	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2977	* AMD:
2978	* EAX: CPU model, family and stepping.
2979	*
2980	* ECX + EDX: Supported features. Only report features we can support.
2981	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2982	* options may require adjusting (i.e. stripping what was enabled).
2983	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2984	*
2985	* EBX: Branding ID and package type (or reserved).
2986	*
2987	* Intel and probably most others:
2988	* EAX: 0
2989	* EBX: 0
2990	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2991	*/
2992	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2993	if (pExtFeatureLeaf)
2994	{
2995	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2996
2997	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2998	\| X86_CPUID_AMD_FEATURE_EDX_VME
2999	\| X86_CPUID_AMD_FEATURE_EDX_DE
3000	\| X86_CPUID_AMD_FEATURE_EDX_PSE
3001	\| X86_CPUID_AMD_FEATURE_EDX_TSC
3002	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
3003	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
3004	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
3005	\| X86_CPUID_AMD_FEATURE_EDX_CX8
3006	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
3007	//\| RT_BIT_32(10) - reserved
3008	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
3009	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
3010	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3011	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
3012	\| X86_CPUID_AMD_FEATURE_EDX_PGE
3013	\| X86_CPUID_AMD_FEATURE_EDX_MCA
3014	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
3015	\| X86_CPUID_AMD_FEATURE_EDX_PAT
3016	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
3017	//\| RT_BIT_32(18) - reserved
3018	//\| RT_BIT_32(19) - reserved
3019	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
3020	//\| RT_BIT_32(21) - reserved
3021	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
3022	\| X86_CPUID_AMD_FEATURE_EDX_MMX
3023	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
3024	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
3025	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3026	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
3027	//\| RT_BIT_32(28) - reserved
3028	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
3029	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
3030	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
3031	;
3032	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
3033	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
3034	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
3035	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3036	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
3037	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
3038	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
3039	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
3040	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
3041	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
3042	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3043	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
3044	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
3045	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3046	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
3047	//\| RT_BIT_32(14) - reserved
3048	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
3049	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
3050	//\| RT_BIT_32(17) - reserved
3051	//\| RT_BIT_32(18) - reserved
3052	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
3053	//\| RT_BIT_32(20) - reserved
3054	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
3055	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
3056	//\| RT_BIT_32(23) - reserved
3057	//\| RT_BIT_32(24) - reserved
3058	//\| RT_BIT_32(25) - reserved
3059	//\| RT_BIT_32(26) - reserved
3060	//\| RT_BIT_32(27) - reserved
3061	//\| RT_BIT_32(28) - reserved
3062	//\| RT_BIT_32(29) - reserved
3063	//\| RT_BIT_32(30) - reserved
3064	//\| RT_BIT_32(31) - reserved
3065	;
3066	#ifdef VBOX_WITH_MULTI_CORE
3067	if ( pVM->cCpus > 1
3068	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3069	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
3070	#endif
3071
3072	if (pCpum->u8PortableCpuIdLevel > 0)
3073	{
3074	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
3075	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
3076	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
3077	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
3078	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
3079	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
3080	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
3081	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
3082	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
3083	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
3084	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
3085	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
3086	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
3087	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
3088	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
3089	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
3090
3091	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
3092	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3093	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3094	\| X86_CPUID_AMD_FEATURE_ECX_IBS
3095	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3096	\| X86_CPUID_AMD_FEATURE_ECX_WDT
3097	\| X86_CPUID_AMD_FEATURE_ECX_LWP
3098	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
3099	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
3100	\| UINT32_C(0xff964000)
3101	)));
3102	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
3103	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3104	\| RT_BIT(18)
3105	\| RT_BIT(19)
3106	\| RT_BIT(21)
3107	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
3108	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3109	\| RT_BIT(28)
3110	)));
3111	}
3112
3113	/* Force extended feature bits. */
3114	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
3115	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
3116	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
3117	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
3118	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
3119	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
3120	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
3121	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
3122	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3123	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
3124	}
3125	pExtFeatureLeaf = NULL; /* Must refetch! */
3126
3127
3128	/* Cpuid 2:
3129	* Intel: (Nondeterministic) Cache and TLB information
3130	* AMD: Reserved
3131	* VIA: Reserved
3132	* Safe to expose.
3133	*/
3134	uint32_t uSubLeaf = 0;
3135	PCPUMCPUIDLEAF pCurLeaf;
3136	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
3137	{
3138	if ((pCurLeaf->uEax & 0xff) > 1)
3139	{
3140	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
3141	pCurLeaf->uEax &= UINT32_C(0xffffff01);
3142	}
3143	uSubLeaf++;
3144	}
3145
3146	/* Cpuid 3:
3147	* Intel: EAX, EBX - reserved (transmeta uses these)
3148	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3149	* AMD: Reserved
3150	* VIA: Reserved
3151	* Safe to expose
3152	*/
3153	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3154	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3155	{
3156	uSubLeaf = 0;
3157	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3158	{
3159	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3160	if (pCpum->u8PortableCpuIdLevel > 0)
3161	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3162	uSubLeaf++;
3163	}
3164	}
3165
3166	/* Cpuid 4 + ECX:
3167	* Intel: Deterministic Cache Parameters Leaf.
3168	* AMD: Reserved
3169	* VIA: Reserved
3170	* Safe to expose, except for EAX:
3171	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3172	* Bits 31-26: Maximum number of processor cores in this physical package**
3173	* Note: These SMP values are constant regardless of ECX
3174	*/
3175	uSubLeaf = 0;
3176	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3177	{
3178	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3179	#ifdef VBOX_WITH_MULTI_CORE
3180	if ( pVM->cCpus > 1
3181	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3182	{
3183	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3184	/* One logical processor with possibly multiple cores. */
3185	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3186	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3187	}
3188	#endif
3189	uSubLeaf++;
3190	}
3191
3192	/* Cpuid 5: Monitor/mwait Leaf
3193	* Intel: ECX, EDX - reserved
3194	* EAX, EBX - Smallest and largest monitor line size
3195	* AMD: EDX - reserved
3196	* EAX, EBX - Smallest and largest monitor line size
3197	* ECX - extensions (ignored for now)
3198	* VIA: Reserved
3199	* Safe to expose
3200	*/
3201	uSubLeaf = 0;
3202	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3203	{
3204	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3205	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3206	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3207
3208	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3209	if (pConfig->enmMWaitExtensions)
3210	{
3211	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3212	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3213	it shall be part of our power management virtualization model */
3214	#if 0
3215	/* MWAIT sub C-states */
3216	pCurLeaf->uEdx =
3217	(0 << 0) /* 0 in C0 */ \|
3218	(2 << 4) /* 2 in C1 */ \|
3219	(2 << 8) /* 2 in C2 */ \|
3220	(2 << 12) /* 2 in C3 */ \|
3221	(0 << 16) /* 0 in C4 */
3222	;
3223	#endif
3224	}
3225	else
3226	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3227	uSubLeaf++;
3228	}
3229
3230	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3231	* Intel: Various stuff.
3232	* AMD: EAX, EBX, EDX - reserved.
3233	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3234	* present. Same as intel.
3235	* VIA: ??
3236	*
3237	* We clear everything here for now.
3238	*/
3239	cpumR3CpuIdZeroLeaf(pCpum, 6);
3240
3241	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3242	* EAX: Number of sub leaves.
3243	* EBX+ECX+EDX: Feature flags
3244	*
3245	* We only have documentation for one sub-leaf, so clear all other (no need
3246	* to remove them as such, just set them to zero).
3247	*
3248	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3249	* options may require adjusting (i.e. stripping what was enabled).
3250	*/
3251	uSubLeaf = 0;
3252	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3253	{
3254	switch (uSubLeaf)
3255	{
3256	case 0:
3257	{
3258	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3259	pCurLeaf->uEbx &= 0
3260	\| (pConfig->enmFsGsBase ? X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE : 0)
3261	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3262	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3263	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3264	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3265	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3266	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3267	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3268	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3269	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3270	\| (pConfig->enmInvpcid ? X86_CPUID_STEXT_FEATURE_EBX_INVPCID : 0)
3271	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3272	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3273	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3274	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3275	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3276	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3277	//\| RT_BIT(17) - reserved
3278	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3279	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3280	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3281	//\| RT_BIT(21) - reserved
3282	//\| RT_BIT(22) - reserved
3283	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3284	//\| RT_BIT(24) - reserved
3285	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3286	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3287	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3288	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3289	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3290	//\| RT_BIT(30) - reserved
3291	//\| RT_BIT(31) - reserved
3292	;
3293	pCurLeaf->uEcx &= 0
3294	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3295	;
3296	pCurLeaf->uEdx &= 0
3297	\| (pConfig->enmMdsClear ? X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR : 0)
3298	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3299	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3300	\| (pConfig->enmFlushCmdMsr ? X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD : 0)
3301	\| (pConfig->enmArchCapMsr ? X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP : 0)
3302	;
3303
3304	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3305	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3306	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3307	{
3308	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3309	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3310	}
3311
3312	if (pCpum->u8PortableCpuIdLevel > 0)
3313	{
3314	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3315	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3316	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3317	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3318	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3319	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3320	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3321	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3322	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3323	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3324	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3325	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3326	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3327	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3328	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3329	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
3330	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
3331	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
3332	}
3333
3334	/* Dependencies. */
3335	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
3336	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3337
3338	/* Force standard feature bits. */
3339	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3340	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3341	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3342	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3343	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3344	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3345	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3346	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3347	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3348	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3349	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3350	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
3351	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
3352	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3353	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3354	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
3355	break;
3356	}
3357
3358	default:
3359	/* Invalid index, all values are zero. */
3360	pCurLeaf->uEax = 0;
3361	pCurLeaf->uEbx = 0;
3362	pCurLeaf->uEcx = 0;
3363	pCurLeaf->uEdx = 0;
3364	break;
3365	}
3366	uSubLeaf++;
3367	}
3368
3369	/* Cpuid 8: Marked as reserved by Intel and AMD.
3370	* We zero this since we don't know what it may have been used for.
3371	*/
3372	cpumR3CpuIdZeroLeaf(pCpum, 8);
3373
3374	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3375	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3376	* EBX, ECX, EDX - reserved.
3377	* AMD: Reserved
3378	* VIA: ??
3379	*
3380	* We zero this.
3381	*/
3382	cpumR3CpuIdZeroLeaf(pCpum, 9);
3383
3384	/* Cpuid 0xa: Architectural Performance Monitor Features
3385	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3386	* EBX, ECX, EDX - reserved.
3387	* AMD: Reserved
3388	* VIA: ??
3389	*
3390	* We zero this, for now at least.
3391	*/
3392	cpumR3CpuIdZeroLeaf(pCpum, 10);
3393
3394	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3395	* Intel: EAX - APCI ID shift right for next level.
3396	* EBX - Factory configured cores/threads at this level.
3397	* ECX - Level number (same as input) and level type (1,2,0).
3398	* EDX - Extended initial APIC ID.
3399	* AMD: Reserved
3400	* VIA: ??
3401	*/
3402	uSubLeaf = 0;
3403	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3404	{
3405	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3406	{
3407	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3408	if (bLevelType == 1)
3409	{
3410	/* Thread level - we don't do threads at the moment. */
3411	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3412	pCurLeaf->uEbx = 1;
3413	}
3414	else if (bLevelType == 2)
3415	{
3416	/* Core level. */
3417	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3418	#ifdef VBOX_WITH_MULTI_CORE
3419	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3420	pCurLeaf->uEax++;
3421	#endif
3422	pCurLeaf->uEbx = pVM->cCpus;
3423	}
3424	else
3425	{
3426	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3427	pCurLeaf->uEax = 0;
3428	pCurLeaf->uEbx = 0;
3429	pCurLeaf->uEcx = 0;
3430	}
3431	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3432	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3433	}
3434	else
3435	{
3436	pCurLeaf->uEax = 0;
3437	pCurLeaf->uEbx = 0;
3438	pCurLeaf->uEcx = 0;
3439	pCurLeaf->uEdx = 0;
3440	}
3441	uSubLeaf++;
3442	}
3443
3444	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3445	* We zero this since we don't know what it may have been used for.
3446	*/
3447	cpumR3CpuIdZeroLeaf(pCpum, 12);
3448
3449	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3450	* ECX=0: EAX - Valid bits in XCR0[31:0].
3451	* EBX - Maximum state size as per current XCR0 value.
3452	* ECX - Maximum state size for all supported features.
3453	* EDX - Valid bits in XCR0[63:32].
3454	* ECX=1: EAX - Various X-features.
3455	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3456	* ECX - Valid bits in IA32_XSS[31:0].
3457	* EDX - Valid bits in IA32_XSS[63:32].
3458	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3459	* if the bit invalid all four registers are set to zero.
3460	* EAX - The state size for this feature.
3461	* EBX - The state byte offset of this feature.
3462	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3463	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3464	*
3465	* Clear them all as we don't currently implement extended CPU state.
3466	*/
3467	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3468	uint64_t fGuestXcr0Mask = 0;
3469	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3470	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3471	{
3472	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3473	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3474	fGuestXcr0Mask \|= XSAVE_C_YMM;
3475	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3476	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3477	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3478	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3479
3480	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3481	}
3482	pStdFeatureLeaf = NULL;
3483	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3484
3485	/* Work the sub-leaves. */
3486	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3487	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3488	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3489	{
3490	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3491	if (pCurLeaf)
3492	{
3493	if (fGuestXcr0Mask)
3494	{
3495	switch (uSubLeaf)
3496	{
3497	case 0:
3498	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3499	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3500	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3501	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3502	VERR_CPUM_IPE_1);
3503	cbXSaveMaxActual = pCurLeaf->uEcx;
3504	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3505	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3506	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3507	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3508	VERR_CPUM_IPE_2);
3509	continue;
3510	case 1:
3511	pCurLeaf->uEax &= 0;
3512	pCurLeaf->uEcx &= 0;
3513	pCurLeaf->uEdx &= 0;
3514	/** @todo what about checking ebx? */
3515	continue;
3516	default:
3517	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3518	{
3519	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3520	&& pCurLeaf->uEax > 0
3521	&& pCurLeaf->uEbx < cbXSaveMaxActual
3522	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3523	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3524	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3525	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3526	VERR_CPUM_IPE_2);
3527	AssertLogRel(!(pCurLeaf->uEcx & 1));
3528	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3529	pCurLeaf->uEdx = 0; /* it's reserved... */
3530	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3531	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3532	continue;
3533	}
3534	break;
3535	}
3536	}
3537
3538	/* Clear the leaf. */
3539	pCurLeaf->uEax = 0;
3540	pCurLeaf->uEbx = 0;
3541	pCurLeaf->uEcx = 0;
3542	pCurLeaf->uEdx = 0;
3543	}
3544	}
3545
3546	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3547	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3548	{
3549	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3550	if (pCurLeaf)
3551	{
3552	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3553	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3554	pCurLeaf->uEbx = cbXSaveMaxReport;
3555	pCurLeaf->uEcx = cbXSaveMaxReport;
3556	}
3557	}
3558
3559	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3560	* We zero this since we don't know what it may have been used for.
3561	*/
3562	cpumR3CpuIdZeroLeaf(pCpum, 14);
3563
3564	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3565	* also known as Intel Resource Director Technology (RDT) Monitoring
3566	* We zero this as we don't currently virtualize PQM.
3567	*/
3568	cpumR3CpuIdZeroLeaf(pCpum, 15);
3569
3570	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3571	* also known as Intel Resource Director Technology (RDT) Allocation
3572	* We zero this as we don't currently virtualize PQE.
3573	*/
3574	cpumR3CpuIdZeroLeaf(pCpum, 16);
3575
3576	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3577	* We zero this since we don't know what it may have been used for.
3578	*/
3579	cpumR3CpuIdZeroLeaf(pCpum, 17);
3580
3581	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3582	* We zero this as we don't currently virtualize this.
3583	*/
3584	cpumR3CpuIdZeroLeaf(pCpum, 18);
3585
3586	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3587	* We zero this since we don't know what it may have been used for.
3588	*/
3589	cpumR3CpuIdZeroLeaf(pCpum, 19);
3590
3591	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3592	* We zero this as we don't currently virtualize this.
3593	*/
3594	cpumR3CpuIdZeroLeaf(pCpum, 20);
3595
3596	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3597	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3598	* EAX - denominator (unsigned).
3599	* EBX - numerator (unsigned).
3600	* ECX, EDX - reserved.
3601	* AMD: Reserved / undefined / not implemented.
3602	* VIA: Reserved / undefined / not implemented.
3603	* We zero this as we don't currently virtualize this.
3604	*/
3605	cpumR3CpuIdZeroLeaf(pCpum, 21);
3606
3607	/* Cpuid 0x16: Processor frequency info
3608	* Intel: EAX - Core base frequency in MHz.
3609	* EBX - Core maximum frequency in MHz.
3610	* ECX - Bus (reference) frequency in MHz.
3611	* EDX - Reserved.
3612	* AMD: Reserved / undefined / not implemented.
3613	* VIA: Reserved / undefined / not implemented.
3614	* We zero this as we don't currently virtualize this.
3615	*/
3616	cpumR3CpuIdZeroLeaf(pCpum, 22);
3617
3618	/* Cpuid 0x17..0x10000000: Unknown.
3619	* We don't know these and what they mean, so remove them. */
3620	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3621	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3622
3623
3624	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3625	* We remove all these as we're a hypervisor and must provide our own.
3626	*/
3627	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3628	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3629
3630
3631	/* Cpuid 0x80000000 is harmless. */
3632
3633	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3634
3635	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3636
3637	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3638	* Safe to pass on to the guest.
3639	*
3640	* AMD: 0x800000005 L1 cache information
3641	* 0x800000006 L2/L3 cache information
3642	* Intel: 0x800000005 reserved
3643	* 0x800000006 L2 cache information
3644	* VIA: 0x800000005 TLB and L1 cache information
3645	* 0x800000006 L2 cache information
3646	*/
3647
3648	/* Cpuid 0x800000007: Advanced Power Management Information.
3649	* AMD: EAX: Processor feedback capabilities.
3650	* EBX: RAS capabilites.
3651	* ECX: Advanced power monitoring interface.
3652	* EDX: Enhanced power management capabilities.
3653	* Intel: EAX, EBX, ECX - reserved.
3654	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3655	* VIA: Reserved
3656	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3657	*/
3658	uSubLeaf = 0;
3659	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3660	{
3661	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3662	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3663	{
3664	/*
3665	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3666	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3667	* bit is now configurable.
3668	*/
3669	pCurLeaf->uEdx &= 0
3670	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3671	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3672	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3673	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3674	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3675	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3676	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3677	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3678	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3679	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3680	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3681	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3682	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3683	\| 0;
3684	}
3685	else
3686	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3687	if (!pConfig->fInvariantTsc)
3688	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3689	uSubLeaf++;
3690	}
3691
3692	/* Cpuid 0x80000008:
3693	* AMD: EBX, EDX - reserved
3694	* EAX: Virtual/Physical/Guest address Size
3695	* ECX: Number of cores + APICIdCoreIdSize
3696	* Intel: EAX: Virtual/Physical address Size
3697	* EBX, ECX, EDX - reserved
3698	* VIA: EAX: Virtual/Physical address Size
3699	* EBX, ECX, EDX - reserved
3700	*
3701	* We only expose the virtual+pysical address size to the guest atm.
3702	* On AMD we set the core count, but not the apic id stuff as we're
3703	* currently not doing the apic id assignments in a complatible manner.
3704	*/
3705	uSubLeaf = 0;
3706	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3707	{
3708	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3709	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3710	pCurLeaf->uEdx = 0; /* reserved */
3711
3712	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3713	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3714	pCurLeaf->uEcx = 0;
3715	#ifdef VBOX_WITH_MULTI_CORE
3716	if ( pVM->cCpus > 1
3717	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3718	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3719	#endif
3720	uSubLeaf++;
3721	}
3722
3723	/* Cpuid 0x80000009: Reserved
3724	* We zero this since we don't know what it may have been used for.
3725	*/
3726	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3727
3728	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
3729	* AMD: EAX - SVM revision.
3730	* EBX - Number of ASIDs.
3731	* ECX - Reserved.
3732	* EDX - SVM Feature identification.
3733	*/
3734	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3735	{
3736	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3737	if ( pExtFeatureLeaf
3738	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
3739	{
3740	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3741	if (pSvmFeatureLeaf)
3742	{
3743	pSvmFeatureLeaf->uEax = 0x1;
3744	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3745	pSvmFeatureLeaf->uEcx = 0;
3746	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3747	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3748	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3749	}
3750	else
3751	{
3752	/* Should never happen. */
3753	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
3754	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3755	}
3756	}
3757	else
3758	{
3759	/* If SVM is not supported, this is reserved, zero out. */
3760	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3761	}
3762	}
3763	else
3764	{
3765	/* Cpuid 0x8000000a: Reserved on Intel.
3766	* We zero this since we don't know what it may have been used for.
3767	*/
3768	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3769	}
3770
3771	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3772	* We clear these as we don't know what purpose they might have. */
3773	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3774	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3775
3776	/* Cpuid 0x80000019: TLB configuration
3777	* Seems to be harmless, pass them thru as is. */
3778
3779	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3780	* Strip anything we don't know what is or addresses feature we don't implement. */
3781	uSubLeaf = 0;
3782	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3783	{
3784	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3785	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3786	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3787	;
3788	pCurLeaf->uEbx = 0; /* reserved */
3789	pCurLeaf->uEcx = 0; /* reserved */
3790	pCurLeaf->uEdx = 0; /* reserved */
3791	uSubLeaf++;
3792	}
3793
3794	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3795	* Clear this as we don't currently virtualize this feature. */
3796	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3797
3798	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3799	* Clear this as we don't currently virtualize this feature. */
3800	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3801
3802	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3803	* We need to sanitize the cores per cache (EAX[25:14]).
3804	*
3805	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3806	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3807	* slightly different meaning.
3808	*/
3809	uSubLeaf = 0;
3810	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3811	{
3812	#ifdef VBOX_WITH_MULTI_CORE
3813	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3814	if (cCores > pVM->cCpus)
3815	cCores = pVM->cCpus;
3816	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3817	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3818	#else
3819	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3820	#endif
3821	uSubLeaf++;
3822	}
3823
3824	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3825	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3826	* setup, we have one compute unit with all the cores in it. Single node.
3827	*/
3828	uSubLeaf = 0;
3829	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3830	{
3831	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3832	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3833	{
3834	#ifdef VBOX_WITH_MULTI_CORE
3835	pCurLeaf->uEbx = pVM->cCpus < 0x100
3836	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3837	#else
3838	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3839	#endif
3840	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3841	}
3842	else
3843	{
3844	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3845	pCurLeaf->uEbx = 0; /* Reserved. */
3846	pCurLeaf->uEcx = 0; /* Reserved. */
3847	}
3848	pCurLeaf->uEdx = 0; /* Reserved. */
3849	uSubLeaf++;
3850	}
3851
3852	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3853	* We don't know these and what they mean, so remove them. */
3854	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3855	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3856
3857	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3858	* Just pass it thru for now. */
3859
3860	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3861	* Just pass it thru for now. */
3862
3863	/* Cpuid 0xc0000000: Centaur stuff.
3864	* Harmless, pass it thru. */
3865
3866	/* Cpuid 0xc0000001: Centaur features.
3867	* VIA: EAX - Family, model, stepping.
3868	* EDX - Centaur extended feature flags. Nothing interesting, except may
3869	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3870	* EBX, ECX - reserved.
3871	* We keep EAX but strips the rest.
3872	*/
3873	uSubLeaf = 0;
3874	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3875	{
3876	pCurLeaf->uEbx = 0;
3877	pCurLeaf->uEcx = 0;
3878	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3879	uSubLeaf++;
3880	}
3881
3882	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3883	* We only have fixed stale values, but should be harmless. */
3884
3885	/* Cpuid 0xc0000003: Reserved.
3886	* We zero this since we don't know what it may have been used for.
3887	*/
3888	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3889
3890	/* Cpuid 0xc0000004: Centaur Performance Info.
3891	* We only have fixed stale values, but should be harmless. */
3892
3893
3894	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3895	* We don't know these and what they mean, so remove them. */
3896	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3897	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3898
3899	return VINF_SUCCESS;
3900	#undef PORTABLE_DISABLE_FEATURE_BIT
3901	#undef PORTABLE_CLEAR_BITS_WHEN
3902	}
3903
3904
3905	/**
3906	* Reads a value in /CPUM/IsaExts/ node.
3907	*
3908	* @returns VBox status code (error message raised).
3909	* @param pVM The cross context VM structure. (For errors.)
3910	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3911	* @param pszValueName The value / extension name.
3912	* @param penmValue Where to return the choice.
3913	* @param enmDefault The default choice.
3914	*/
3915	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3916	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3917	{
3918	/*
3919	* Try integer encoding first.
3920	*/
3921	uint64_t uValue;
3922	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3923	if (RT_SUCCESS(rc))
3924	switch (uValue)
3925	{
3926	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3927	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3928	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3929	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3930	default:
3931	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3932	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3933	pszValueName, uValue);
3934	}
3935	/*
3936	* If missing, use default.
3937	*/
3938	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3939	*penmValue = enmDefault;
3940	else
3941	{
3942	if (rc == VERR_CFGM_NOT_INTEGER)
3943	{
3944	/*
3945	* Not an integer, try read it as a string.
3946	*/
3947	char szValue[32];
3948	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3949	if (RT_SUCCESS(rc))
3950	{
3951	RTStrToLower(szValue);
3952	size_t cchValue = strlen(szValue);
3953	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3954	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3955	*penmValue = CPUMISAEXTCFG_DISABLED;
3956	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3957	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3958	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3959	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3960	else if (EQ("portable"))
3961	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3962	else if (EQ("default") \|\| EQ("def"))
3963	*penmValue = enmDefault;
3964	else
3965	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3966	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3967	pszValueName, uValue);
3968	#undef EQ
3969	}
3970	}
3971	if (RT_FAILURE(rc))
3972	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3973	}
3974	return VINF_SUCCESS;
3975	}
3976
3977
3978	/**
3979	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3980	*
3981	* @returns VBox status code (error message raised).
3982	* @param pVM The cross context VM structure. (For errors.)
3983	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3984	* @param pszValueName The value / extension name.
3985	* @param penmValue Where to return the choice.
3986	* @param enmDefault The default choice.
3987	* @param fAllowed Allowed choice. Applied both to the result and to
3988	* the default value.
3989	*/
3990	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3991	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3992	{
3993	int rc;
3994	if (fAllowed)
3995	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3996	else
3997	{
3998	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3999	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
4000	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
4001	*penmValue = CPUMISAEXTCFG_DISABLED;
4002	}
4003	return rc;
4004	}
4005
4006
4007	/**
4008	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
4009	*
4010	* @returns VBox status code (error message raised).
4011	* @param pVM The cross context VM structure. (For errors.)
4012	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4013	* @param pCpumCfg The /CPUM node (can be NULL).
4014	* @param pszValueName The value / extension name.
4015	* @param penmValue Where to return the choice.
4016	* @param enmDefault The default choice.
4017	*/
4018	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
4019	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
4020	{
4021	if (CFGMR3Exists(pCpumCfg, pszValueName))
4022	{
4023	if (!CFGMR3Exists(pIsaExts, pszValueName))
4024	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
4025	else
4026	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
4027	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
4028	pszValueName, pszValueName);
4029
4030	bool fLegacy;
4031	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
4032	if (RT_SUCCESS(rc))
4033	{
4034	*penmValue = fLegacy;
4035	return VINF_SUCCESS;
4036	}
4037	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
4038	}
4039
4040	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4041	}
4042
4043
4044	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
4045	{
4046	int rc;
4047
4048	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
4049	* When non-zero CPUID features that could cause portability issues will be
4050	* stripped. The higher the value the more features gets stripped. Higher
4051	* values should only be used when older CPUs are involved since it may
4052	* harm performance and maybe also cause problems with specific guests. */
4053	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
4054	AssertLogRelRCReturn(rc, rc);
4055
4056	/** @cfgm{/CPUM/GuestCpuName, string}
4057	* The name of the CPU we're to emulate. The default is the host CPU.
4058	* Note! CPUs other than "host" one is currently unsupported. */
4059	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
4060	AssertLogRelRCReturn(rc, rc);
4061
4062	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
4063	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
4064	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
4065	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
4066	*/
4067	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
4068	AssertLogRelRCReturn(rc, rc);
4069
4070	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
4071	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
4072	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
4073	* 64-bit linux guests which assume the presence of AMD performance counters
4074	* that we do not virtualize.
4075	*/
4076	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
4077	AssertLogRelRCReturn(rc, rc);
4078
4079	/** @cfgm{/CPUM/ForceVme, boolean, false}
4080	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
4081	* By default the flag is passed thru as is from the host CPU, except
4082	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
4083	* guests and DOS boxes in general.
4084	*/
4085	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
4086	AssertLogRelRCReturn(rc, rc);
4087
4088	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
4089	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
4090	* probably going to be a temporary hack, so don't depend on this.
4091	* The 1st byte of the value is the stepping, the 2nd byte value is the model
4092	* number and the 3rd byte value is the family, and the 4th value must be zero.
4093	*/
4094	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
4095	AssertLogRelRCReturn(rc, rc);
4096
4097	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
4098	* The last standard leaf to keep. The actual last value that is stored in EAX
4099	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
4100	* removed. (This works independently of and differently from NT4LeafLimit.)
4101	* The default is usually set to what we're able to reasonably sanitize.
4102	*/
4103	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
4104	AssertLogRelRCReturn(rc, rc);
4105
4106	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
4107	* The last extended leaf to keep. The actual last value that is stored in EAX
4108	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
4109	* leaf are removed. The default is set to what we're able to sanitize.
4110	*/
4111	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
4112	AssertLogRelRCReturn(rc, rc);
4113
4114	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
4115	* The last extended leaf to keep. The actual last value that is stored in EAX
4116	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
4117	* leaf are removed. The default is set to what we're able to sanitize.
4118	*/
4119	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
4120	AssertLogRelRCReturn(rc, rc);
4121
4122	bool fQueryNestedHwvirt = false;
4123	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4124	fQueryNestedHwvirt \|= RT_BOOL(pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD);
4125	#endif
4126	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4127	fQueryNestedHwvirt \|= RT_BOOL( pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
4128	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA);
4129	#endif
4130	if (fQueryNestedHwvirt)
4131	{
4132	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
4133	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
4134	* The default is false, and when enabled requires a 64-bit CPU with support for
4135	* nested-paging and AMD-V or unrestricted guest mode.
4136	*/
4137	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
4138	AssertLogRelRCReturn(rc, rc);
4139	if ( pConfig->fNestedHWVirt
4140	&& !fNestedPagingAndFullGuestExec)
4141	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4142	"Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
4143
4144	/** @todo Think about enabling this later with NEM/KVM. */
4145	if ( pConfig->fNestedHWVirt
4146	&& VM_IS_NEM_ENABLED(pVM))
4147	{
4148	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
4149	pConfig->fNestedHWVirt = false;
4150	}
4151	}
4152
4153	/*
4154	* Instruction Set Architecture (ISA) Extensions.
4155	*/
4156	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
4157	if (pIsaExts)
4158	{
4159	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
4160	"CMPXCHG16B"
4161	"\|MONITOR"
4162	"\|MWaitExtensions"
4163	"\|SSE4.1"
4164	"\|SSE4.2"
4165	"\|XSAVE"
4166	"\|AVX"
4167	"\|AVX2"
4168	"\|AESNI"
4169	"\|PCLMUL"
4170	"\|POPCNT"
4171	"\|MOVBE"
4172	"\|RDRAND"
4173	"\|RDSEED"
4174	"\|CLFLUSHOPT"
4175	"\|FSGSBASE"
4176	"\|PCID"
4177	"\|INVPCID"
4178	"\|FlushCmdMsr"
4179	"\|ABM"
4180	"\|SSE4A"
4181	"\|MISALNSSE"
4182	"\|3DNOWPRF"
4183	"\|AXMMX"
4184	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
4185	if (RT_FAILURE(rc))
4186	return rc;
4187	}
4188
4189	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
4190	* Expose CMPXCHG16B to the guest if supported by the host. For the time
4191	* being the default is to only do this for VMs with nested paging and AMD-V or
4192	* unrestricted guest mode.
4193	*/
4194	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
4195	AssertLogRelRCReturn(rc, rc);
4196
4197	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4198	* Expose MONITOR/MWAIT instructions to the guest.
4199	*/
4200	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4201	AssertLogRelRCReturn(rc, rc);
4202
4203	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4204	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4205	* break on interrupt feature (bit 1).
4206	*/
4207	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4208	AssertLogRelRCReturn(rc, rc);
4209
4210	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4211	* Expose SSE4.1 to the guest if available.
4212	*/
4213	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4214	AssertLogRelRCReturn(rc, rc);
4215
4216	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4217	* Expose SSE4.2 to the guest if available.
4218	*/
4219	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4220	AssertLogRelRCReturn(rc, rc);
4221
4222	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4223	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4224	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor;
4225	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4226
4227	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4228	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4229	* default is to only expose this to VMs with nested paging and AMD-V or
4230	* unrestricted guest execution mode. Not possible to force this one without
4231	* host support at the moment.
4232	*/
4233	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4234	fMayHaveXSave /fAllowed/);
4235	AssertLogRelRCReturn(rc, rc);
4236
4237	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4238	* Expose the AVX instruction set extensions to the guest if available and
4239	* XSAVE is exposed too. For the time being the default is to only expose this
4240	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4241	*/
4242	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4243	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4244	AssertLogRelRCReturn(rc, rc);
4245
4246	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4247	* Expose the AVX2 instruction set extensions to the guest if available and
4248	* XSAVE is exposed too. For the time being the default is to only expose this
4249	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4250	*/
4251	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4252	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4253	AssertLogRelRCReturn(rc, rc);
4254
4255	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4256	* Whether to expose the AES instructions to the guest. For the time being the
4257	* default is to only do this for VMs with nested paging and AMD-V or
4258	* unrestricted guest mode.
4259	*/
4260	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4261	AssertLogRelRCReturn(rc, rc);
4262
4263	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4264	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4265	* being the default is to only do this for VMs with nested paging and AMD-V or
4266	* unrestricted guest mode.
4267	*/
4268	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4269	AssertLogRelRCReturn(rc, rc);
4270
4271	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4272	* Whether to expose the POPCNT instructions to the guest. For the time
4273	* being the default is to only do this for VMs with nested paging and AMD-V or
4274	* unrestricted guest mode.
4275	*/
4276	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4277	AssertLogRelRCReturn(rc, rc);
4278
4279	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4280	* Whether to expose the MOVBE instructions to the guest. For the time
4281	* being the default is to only do this for VMs with nested paging and AMD-V or
4282	* unrestricted guest mode.
4283	*/
4284	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4285	AssertLogRelRCReturn(rc, rc);
4286
4287	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4288	* Whether to expose the RDRAND instructions to the guest. For the time being
4289	* the default is to only do this for VMs with nested paging and AMD-V or
4290	* unrestricted guest mode.
4291	*/
4292	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4293	AssertLogRelRCReturn(rc, rc);
4294
4295	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4296	* Whether to expose the RDSEED instructions to the guest. For the time being
4297	* the default is to only do this for VMs with nested paging and AMD-V or
4298	* unrestricted guest mode.
4299	*/
4300	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4301	AssertLogRelRCReturn(rc, rc);
4302
4303	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4304	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4305	* being the default is to only do this for VMs with nested paging and AMD-V or
4306	* unrestricted guest mode.
4307	*/
4308	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4309	AssertLogRelRCReturn(rc, rc);
4310
4311	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4312	* Whether to expose the read/write FSGSBASE instructions to the guest.
4313	*/
4314	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4315	AssertLogRelRCReturn(rc, rc);
4316
4317	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4318	* Whether to expose the PCID feature to the guest.
4319	*/
4320	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4321	AssertLogRelRCReturn(rc, rc);
4322
4323	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4324	* Whether to expose the INVPCID instruction to the guest.
4325	*/
4326	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4327	AssertLogRelRCReturn(rc, rc);
4328
4329	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
4330	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
4331	*/
4332	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4333	AssertLogRelRCReturn(rc, rc);
4334
4335	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
4336	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
4337	* the guest. Requires FlushCmdMsr to be present too.
4338	*/
4339	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4340	AssertLogRelRCReturn(rc, rc);
4341
4342	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
4343	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
4344	*/
4345	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4346	AssertLogRelRCReturn(rc, rc);
4347
4348
4349	/* AMD: */
4350
4351	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4352	* Whether to expose the AMD ABM instructions to the guest. For the time
4353	* being the default is to only do this for VMs with nested paging and AMD-V or
4354	* unrestricted guest mode.
4355	*/
4356	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4357	AssertLogRelRCReturn(rc, rc);
4358
4359	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4360	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4361	* being the default is to only do this for VMs with nested paging and AMD-V or
4362	* unrestricted guest mode.
4363	*/
4364	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4365	AssertLogRelRCReturn(rc, rc);
4366
4367	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4368	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4369	* the time being the default is to only do this for VMs with nested paging and
4370	* AMD-V or unrestricted guest mode.
4371	*/
4372	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4373	AssertLogRelRCReturn(rc, rc);
4374
4375	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4376	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4377	* For the time being the default is to only do this for VMs with nested paging
4378	* and AMD-V or unrestricted guest mode.
4379	*/
4380	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4381	AssertLogRelRCReturn(rc, rc);
4382
4383	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4384	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4385	* the default is to only do this for VMs with nested paging and AMD-V or
4386	* unrestricted guest mode.
4387	*/
4388	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4389	AssertLogRelRCReturn(rc, rc);
4390
4391	return VINF_SUCCESS;
4392	}
4393
4394
4395	/**
4396	* Initializes the emulated CPU's CPUID & MSR information.
4397	*
4398	* @returns VBox status code.
4399	* @param pVM The cross context VM structure.
4400	* @param pHostMsrs Pointer to the host MSRs.
4401	*/
4402	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
4403	{
4404	Assert(pHostMsrs);
4405
4406	PCPUM pCpum = &pVM->cpum.s;
4407	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4408
4409	/*
4410	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4411	* on construction and manage everything from here on.
4412	*/
4413	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4414	{
4415	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4416	pVCpu->cpum.s.fCpuIdApicFeatureVisible = true;
4417	}
4418
4419	/*
4420	* Read the configuration.
4421	*/
4422	CPUMCPUIDCONFIG Config;
4423	RT_ZERO(Config);
4424
4425	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4426	AssertRCReturn(rc, rc);
4427
4428	/*
4429	* Get the guest CPU data from the database and/or the host.
4430	*
4431	* The CPUID and MSRs are currently living on the regular heap to avoid
4432	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4433	* API for the hyper heap). This means special cleanup considerations.
4434	*/
4435	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4436	if (RT_FAILURE(rc))
4437	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4438	? VMSetError(pVM, rc, RT_SRC_POS,
4439	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4440	: rc;
4441
4442	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4443	{
4444	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4445	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4446	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4447	}
4448	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4449
4450	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4451	* Overrides the guest MSRs.
4452	*/
4453	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4454
4455	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4456	* Overrides the CPUID leaf values (from the host CPU usually) used for
4457	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4458	* values when moving a VM to a different machine. Another use is restricting
4459	* (or extending) the feature set exposed to the guest. */
4460	if (RT_SUCCESS(rc))
4461	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4462
4463	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4464	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4465	"Found unsupported configuration node '/CPUM/CPUID/'. "
4466	"Please use IMachine::setCPUIDLeaf() instead.");
4467
4468	CPUMMSRS GuestMsrs;
4469	RT_ZERO(GuestMsrs);
4470
4471	/*
4472	* Pre-explode the CPUID info.
4473	*/
4474	if (RT_SUCCESS(rc))
4475	{
4476	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
4477	&pCpum->GuestFeatures);
4478	}
4479
4480	/*
4481	* Sanitize the cpuid information passed on to the guest.
4482	*/
4483	if (RT_SUCCESS(rc))
4484	{
4485	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4486	if (RT_SUCCESS(rc))
4487	{
4488	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4489	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4490	}
4491	}
4492
4493	/*
4494	* Setup MSRs introduced in microcode updates or that are otherwise not in
4495	* the CPU profile, but are advertised in the CPUID info we just sanitized.
4496	*/
4497	if (RT_SUCCESS(rc))
4498	rc = cpumR3MsrReconcileWithCpuId(pVM);
4499	/*
4500	* MSR fudging.
4501	*/
4502	if (RT_SUCCESS(rc))
4503	{
4504	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4505	* Fudges some common MSRs if not present in the selected CPU database entry.
4506	* This is for trying to keep VMs running when moved between different hosts
4507	* and different CPU vendors. */
4508	bool fEnable;
4509	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4510	if (RT_SUCCESS(rc) && fEnable)
4511	{
4512	rc = cpumR3MsrApplyFudge(pVM);
4513	AssertLogRelRC(rc);
4514	}
4515	}
4516	if (RT_SUCCESS(rc))
4517	{
4518	/*
4519	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4520	* guest CPU features again.
4521	*/
4522	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4523	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4524	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
4525	RTMemFree(pvFree);
4526
4527	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4528	int rc2 = MMHyperDupMem(pVM, pvFree,
4529	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4530	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4531	RTMemFree(pvFree);
4532	AssertLogRelRCReturn(rc1, rc1);
4533	AssertLogRelRCReturn(rc2, rc2);
4534
4535	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4536
4537	/*
4538	* Finally, initialize guest VMX MSRs.
4539	*
4540	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
4541	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
4542	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
4543	*/
4544	if (pVM->cpum.s.GuestFeatures.fVmx)
4545	{
4546	Assert(Config.fNestedHWVirt);
4547	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
4548
4549	/* Copy MSRs to all VCPUs */
4550	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
4551	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4552	{
4553	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4554	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
4555	}
4556	}
4557
4558	/*
4559	* Some more configuration that we're applying at the end of everything
4560	* via the CPUMR3SetGuestCpuIdFeature API.
4561	*/
4562
4563	/* Check if PAE was explicitely enabled by the user. */
4564	bool fEnable;
4565	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4566	AssertRCReturn(rc, rc);
4567	if (fEnable)
4568	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4569
4570	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4571	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4572	AssertRCReturn(rc, rc);
4573	if (fEnable)
4574	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4575
4576	/* Check if speculation control is enabled. */
4577	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4578	AssertRCReturn(rc, rc);
4579	if (fEnable)
4580	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4581
4582	return VINF_SUCCESS;
4583	}
4584
4585	/*
4586	* Failed before switching to hyper heap.
4587	*/
4588	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4589	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4590	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4591	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4592	return rc;
4593	}
4594
4595
4596	/**
4597	* Sets a CPUID feature bit during VM initialization.
4598	*
4599	* Since the CPUID feature bits are generally related to CPU features, other
4600	* CPUM configuration like MSRs can also be modified by calls to this API.
4601	*
4602	* @param pVM The cross context VM structure.
4603	* @param enmFeature The feature to set.
4604	*/
4605	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4606	{
4607	PCPUMCPUIDLEAF pLeaf;
4608	PCPUMMSRRANGE pMsrRange;
4609
4610	switch (enmFeature)
4611	{
4612	/*
4613	* Set the APIC bit in both feature masks.
4614	*/
4615	case CPUMCPUIDFEATURE_APIC:
4616	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4617	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4618	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4619
4620	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4621	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4622	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4623
4624	pVM->cpum.s.GuestFeatures.fApic = 1;
4625
4626	/* Make sure we've got the APICBASE MSR present. */
4627	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4628	if (!pMsrRange)
4629	{
4630	static CPUMMSRRANGE const s_ApicBase =
4631	{
4632	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4633	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4634	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4635	/.szName = / "IA32_APIC_BASE"
4636	};
4637	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4638	AssertLogRelRC(rc);
4639	}
4640
4641	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4642	break;
4643
4644	/*
4645	* Set the x2APIC bit in the standard feature mask.
4646	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4647	*/
4648	case CPUMCPUIDFEATURE_X2APIC:
4649	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4650	if (pLeaf)
4651	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4652	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4653
4654	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4655	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4656	if (pMsrRange)
4657	{
4658	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4659	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4660	}
4661
4662	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4663	break;
4664
4665	/*
4666	* Set the sysenter/sysexit bit in the standard feature mask.
4667	* Assumes the caller knows what it's doing! (host must support these)
4668	*/
4669	case CPUMCPUIDFEATURE_SEP:
4670	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4671	{
4672	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4673	return;
4674	}
4675
4676	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4677	if (pLeaf)
4678	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4679	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4680	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4681	break;
4682
4683	/*
4684	* Set the syscall/sysret bit in the extended feature mask.
4685	* Assumes the caller knows what it's doing! (host must support these)
4686	*/
4687	case CPUMCPUIDFEATURE_SYSCALL:
4688	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4689	if ( !pLeaf
4690	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4691	{
4692	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4693	return;
4694	}
4695
4696	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4697	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4698	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4699	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4700	break;
4701
4702	/*
4703	* Set the PAE bit in both feature masks.
4704	* Assumes the caller knows what it's doing! (host must support these)
4705	*/
4706	case CPUMCPUIDFEATURE_PAE:
4707	if (!pVM->cpum.s.HostFeatures.fPae)
4708	{
4709	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4710	return;
4711	}
4712
4713	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4714	if (pLeaf)
4715	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4716
4717	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4718	if ( pLeaf
4719	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4720	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4721
4722	pVM->cpum.s.GuestFeatures.fPae = 1;
4723	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4724	break;
4725
4726	/*
4727	* Set the LONG MODE bit in the extended feature mask.
4728	* Assumes the caller knows what it's doing! (host must support these)
4729	*/
4730	case CPUMCPUIDFEATURE_LONG_MODE:
4731	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4732	if ( !pLeaf
4733	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4734	{
4735	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4736	return;
4737	}
4738
4739	/* Valid for both Intel and AMD. */
4740	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4741	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4742	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
4743	if (pVM->cpum.s.GuestFeatures.fVmx)
4744	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4745	{
4746	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4747	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic &= ~VMX_BASIC_PHYSADDR_WIDTH_32BIT;
4748	}
4749	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4750	break;
4751
4752	/*
4753	* Set the NX/XD bit in the extended feature mask.
4754	* Assumes the caller knows what it's doing! (host must support these)
4755	*/
4756	case CPUMCPUIDFEATURE_NX:
4757	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4758	if ( !pLeaf
4759	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4760	{
4761	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4762	return;
4763	}
4764
4765	/* Valid for both Intel and AMD. */
4766	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4767	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4768	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4769	break;
4770
4771
4772	/*
4773	* Set the LAHF/SAHF support in 64-bit mode.
4774	* Assumes the caller knows what it's doing! (host must support this)
4775	*/
4776	case CPUMCPUIDFEATURE_LAHF:
4777	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4778	if ( !pLeaf
4779	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4780	{
4781	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4782	return;
4783	}
4784
4785	/* Valid for both Intel and AMD. */
4786	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4787	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4788	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4789	break;
4790
4791	/*
4792	* Set the page attribute table bit. This is alternative page level
4793	* cache control that doesn't much matter when everything is
4794	* virtualized, though it may when passing thru device memory.
4795	*/
4796	case CPUMCPUIDFEATURE_PAT:
4797	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4798	if (pLeaf)
4799	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4800
4801	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4802	if ( pLeaf
4803	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4804	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4805
4806	pVM->cpum.s.GuestFeatures.fPat = 1;
4807	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4808	break;
4809
4810	/*
4811	* Set the RDTSCP support bit.
4812	* Assumes the caller knows what it's doing! (host must support this)
4813	*/
4814	case CPUMCPUIDFEATURE_RDTSCP:
4815	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4816	if ( !pLeaf
4817	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4818	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4819	{
4820	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4821	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4822	return;
4823	}
4824
4825	/* Valid for both Intel and AMD. */
4826	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4827	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4828	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4829	break;
4830
4831	/*
4832	* Set the Hypervisor Present bit in the standard feature mask.
4833	*/
4834	case CPUMCPUIDFEATURE_HVP:
4835	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4836	if (pLeaf)
4837	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4838	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4839	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4840	break;
4841
4842	/*
4843	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4844	* This currently includes the Present bit and MWAITBREAK bit as well.
4845	*/
4846	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4847	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4848	if ( !pLeaf
4849	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4850	{
4851	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4852	return;
4853	}
4854
4855	/* Valid for both Intel and AMD. */
4856	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4857	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4858	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4859	break;
4860
4861	/*
4862	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
4863	* on Intel CPUs, and different on AMDs.
4864	*/
4865	case CPUMCPUIDFEATURE_SPEC_CTRL:
4866	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4867	{
4868	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4869	if ( !pLeaf
4870	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
4871	{
4872	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4873	return;
4874	}
4875
4876	/* The feature can be enabled. Let's see what we can actually do. */
4877	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4878
4879	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4880	if (pVM->cpum.s.HostFeatures.fIbrs)
4881	{
4882	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4883	pVM->cpum.s.GuestFeatures.fIbrs = 1;
4884	if (pVM->cpum.s.HostFeatures.fStibp)
4885	{
4886	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4887	pVM->cpum.s.GuestFeatures.fStibp = 1;
4888	}
4889
4890	/* Make sure we have the speculation control MSR... */
4891	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4892	if (!pMsrRange)
4893	{
4894	static CPUMMSRRANGE const s_SpecCtrl =
4895	{
4896	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
4897	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
4898	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4899	/.szName = / "IA32_SPEC_CTRL"
4900	};
4901	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4902	AssertLogRelRC(rc);
4903	}
4904
4905	/* ... and the predictor command MSR. */
4906	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
4907	if (!pMsrRange)
4908	{
4909	/** @todo incorrect fWrGpMask. */
4910	static CPUMMSRRANGE const s_SpecCtrl =
4911	{
4912	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
4913	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
4914	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4915	/.szName = / "IA32_PRED_CMD"
4916	};
4917	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4918	AssertLogRelRC(rc);
4919	}
4920
4921	}
4922
4923	if (pVM->cpum.s.HostFeatures.fArchCap)
4924	{
4925	/* Install the architectural capabilities MSR. */
4926	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
4927	if (!pMsrRange)
4928	{
4929	static CPUMMSRRANGE const s_ArchCaps =
4930	{
4931	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
4932	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
4933	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
4934	/.szName = / "IA32_ARCH_CAPABILITIES"
4935	};
4936	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
4937	AssertLogRelRC(rc);
4938	}
4939	}
4940
4941	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
4942	}
4943	else if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4944	{
4945	/* The precise details of AMD's implementation are not yet clear. */
4946	}
4947	break;
4948
4949	default:
4950	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4951	break;
4952	}
4953
4954	/** @todo can probably kill this as this API is now init time only... */
4955	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4956	{
4957	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4958	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4959	}
4960	}
4961
4962
4963	/**
4964	* Queries a CPUID feature bit.
4965	*
4966	* @returns boolean for feature presence
4967	* @param pVM The cross context VM structure.
4968	* @param enmFeature The feature to query.
4969	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4970	*/
4971	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4972	{
4973	switch (enmFeature)
4974	{
4975	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4976	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4977	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4978	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4979	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4980	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4981	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4982	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4983	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4984	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4985	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4986	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4987	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
4988
4989	case CPUMCPUIDFEATURE_INVALID:
4990	case CPUMCPUIDFEATURE_32BIT_HACK:
4991	break;
4992	}
4993	AssertFailed();
4994	return false;
4995	}
4996
4997
4998	/**
4999	* Clears a CPUID feature bit.
5000	*
5001	* @param pVM The cross context VM structure.
5002	* @param enmFeature The feature to clear.
5003	*
5004	* @deprecated Probably better to default the feature to disabled and only allow
5005	* setting (enabling) it during construction.
5006	*/
5007	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5008	{
5009	PCPUMCPUIDLEAF pLeaf;
5010	switch (enmFeature)
5011	{
5012	case CPUMCPUIDFEATURE_APIC:
5013	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
5014	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5015	if (pLeaf)
5016	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
5017
5018	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5019	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
5020	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
5021
5022	pVM->cpum.s.GuestFeatures.fApic = 0;
5023	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
5024	break;
5025
5026	case CPUMCPUIDFEATURE_X2APIC:
5027	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
5028	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5029	if (pLeaf)
5030	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
5031	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
5032	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
5033	break;
5034
5035	case CPUMCPUIDFEATURE_PAE:
5036	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5037	if (pLeaf)
5038	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
5039
5040	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5041	if ( pLeaf
5042	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
5043	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
5044
5045	pVM->cpum.s.GuestFeatures.fPae = 0;
5046	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
5047	break;
5048
5049	case CPUMCPUIDFEATURE_PAT:
5050	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5051	if (pLeaf)
5052	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
5053
5054	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5055	if ( pLeaf
5056	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
5057	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
5058
5059	pVM->cpum.s.GuestFeatures.fPat = 0;
5060	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
5061	break;
5062
5063	case CPUMCPUIDFEATURE_LONG_MODE:
5064	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5065	if (pLeaf)
5066	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
5067	pVM->cpum.s.GuestFeatures.fLongMode = 0;
5068	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
5069	if (pVM->cpum.s.GuestFeatures.fVmx)
5070	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5071	{
5072	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5073	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic \|= VMX_BASIC_PHYSADDR_WIDTH_32BIT;
5074	}
5075	break;
5076
5077	case CPUMCPUIDFEATURE_LAHF:
5078	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5079	if (pLeaf)
5080	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
5081	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
5082	break;
5083
5084	case CPUMCPUIDFEATURE_RDTSCP:
5085	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5086	if (pLeaf)
5087	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
5088	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
5089	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
5090	break;
5091
5092	case CPUMCPUIDFEATURE_HVP:
5093	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5094	if (pLeaf)
5095	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
5096	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
5097	break;
5098
5099	case CPUMCPUIDFEATURE_MWAIT_EXTS:
5100	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
5101	if (pLeaf)
5102	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
5103	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
5104	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
5105	break;
5106
5107	case CPUMCPUIDFEATURE_SPEC_CTRL:
5108	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
5109	if (pLeaf)
5110	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
5111	pVM->cpum.s.GuestFeatures.fSpeculationControl = 0;
5112	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
5113	break;
5114
5115	default:
5116	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5117	break;
5118	}
5119
5120	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5121	{
5122	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5123	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5124	}
5125	}
5126
5127
5128
5129	/*
5130	*
5131	*
5132	* Saved state related code.
5133	* Saved state related code.
5134	* Saved state related code.
5135	*
5136	*
5137	*/
5138
5139	/**
5140	* Called both in pass 0 and the final pass.
5141	*
5142	* @param pVM The cross context VM structure.
5143	* @param pSSM The saved state handle.
5144	*/
5145	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
5146	{
5147	/*
5148	* Save all the CPU ID leaves.
5149	*/
5150	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
5151	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5152	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
5153	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5154
5155	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5156
5157	/*
5158	* Save a good portion of the raw CPU IDs as well as they may come in
5159	* handy when validating features for raw mode.
5160	*/
5161	CPUMCPUID aRawStd[16];
5162	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
5163	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5164	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
5165	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
5166
5167	CPUMCPUID aRawExt[32];
5168	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
5169	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5170	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
5171	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
5172	}
5173
5174
5175	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5176	{
5177	uint32_t cCpuIds;
5178	int rc = SSMR3GetU32(pSSM, &cCpuIds);
5179	if (RT_SUCCESS(rc))
5180	{
5181	if (cCpuIds < 64)
5182	{
5183	for (uint32_t i = 0; i < cCpuIds; i++)
5184	{
5185	CPUMCPUID CpuId;
5186	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
5187	if (RT_FAILURE(rc))
5188	break;
5189
5190	CPUMCPUIDLEAF NewLeaf;
5191	NewLeaf.uLeaf = uBase + i;
5192	NewLeaf.uSubLeaf = 0;
5193	NewLeaf.fSubLeafMask = 0;
5194	NewLeaf.uEax = CpuId.uEax;
5195	NewLeaf.uEbx = CpuId.uEbx;
5196	NewLeaf.uEcx = CpuId.uEcx;
5197	NewLeaf.uEdx = CpuId.uEdx;
5198	NewLeaf.fFlags = 0;
5199	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
5200	}
5201	}
5202	else
5203	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5204	}
5205	if (RT_FAILURE(rc))
5206	{
5207	RTMemFree(*ppaLeaves);
5208	*ppaLeaves = NULL;
5209	*pcLeaves = 0;
5210	}
5211	return rc;
5212	}
5213
5214
5215	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5216	{
5217	*ppaLeaves = NULL;
5218	*pcLeaves = 0;
5219
5220	int rc;
5221	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
5222	{
5223	/*
5224	* The new format. Starts by declaring the leave size and count.
5225	*/
5226	uint32_t cbLeaf;
5227	SSMR3GetU32(pSSM, &cbLeaf);
5228	uint32_t cLeaves;
5229	rc = SSMR3GetU32(pSSM, &cLeaves);
5230	if (RT_SUCCESS(rc))
5231	{
5232	if (cbLeaf == sizeof(**ppaLeaves))
5233	{
5234	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
5235	{
5236	/*
5237	* Load the leaves one by one.
5238	*
5239	* The uPrev stuff is a kludge for working around a week worth of bad saved
5240	* states during the CPUID revamp in March 2015. We saved too many leaves
5241	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
5242	* garbage entires at the end of the array when restoring. We also had
5243	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
5244	* this kludge doesn't deal correctly with that, but who cares...
5245	*/
5246	uint32_t uPrev = 0;
5247	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
5248	{
5249	CPUMCPUIDLEAF Leaf;
5250	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5251	if (RT_SUCCESS(rc))
5252	{
5253	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5254	\|\| Leaf.uLeaf >= uPrev)
5255	{
5256	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5257	uPrev = Leaf.uLeaf;
5258	}
5259	else
5260	uPrev = UINT32_MAX;
5261	}
5262	}
5263	}
5264	else
5265	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5266	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5267	}
5268	else
5269	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5270	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5271	}
5272	}
5273	else
5274	{
5275	/*
5276	* The old format with its three inflexible arrays.
5277	*/
5278	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5279	if (RT_SUCCESS(rc))
5280	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5281	if (RT_SUCCESS(rc))
5282	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5283	if (RT_SUCCESS(rc))
5284	{
5285	/*
5286	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5287	*/
5288	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5289	if ( pLeaf
5290	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5291	{
5292	CPUMCPUIDLEAF Leaf;
5293	Leaf.uLeaf = 4;
5294	Leaf.fSubLeafMask = UINT32_MAX;
5295	Leaf.uSubLeaf = 0;
5296	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5297	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5298	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5299	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5300	\| UINT32_C(63); /* system coherency line size - 1 */
5301	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5302	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5303	\| (UINT32_C(1) << 5) /* cache level */
5304	\| UINT32_C(1); /* cache type (data) */
5305	Leaf.fFlags = 0;
5306	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5307	if (RT_SUCCESS(rc))
5308	{
5309	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5310	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5311	}
5312	if (RT_SUCCESS(rc))
5313	{
5314	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5315	Leaf.uEcx = 4095; /* sets - 1 */
5316	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5317	Leaf.uEbx \|= UINT32_C(23) << 22;
5318	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5319	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5320	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5321	Leaf.uEax \|= UINT32_C(2) << 5;
5322	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5323	}
5324	}
5325	}
5326	}
5327	return rc;
5328	}
5329
5330
5331	/**
5332	* Loads the CPU ID leaves saved by pass 0, inner worker.
5333	*
5334	* @returns VBox status code.
5335	* @param pVM The cross context VM structure.
5336	* @param pSSM The saved state handle.
5337	* @param uVersion The format version.
5338	* @param paLeaves Guest CPUID leaves loaded from the state.
5339	* @param cLeaves The number of leaves in @a paLeaves.
5340	* @param pMsrs The guest MSRs.
5341	*/
5342	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
5343	{
5344	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5345
5346	/*
5347	* Continue loading the state into stack buffers.
5348	*/
5349	CPUMCPUID GuestDefCpuId;
5350	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5351	AssertRCReturn(rc, rc);
5352
5353	CPUMCPUID aRawStd[16];
5354	uint32_t cRawStd;
5355	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5356	if (cRawStd > RT_ELEMENTS(aRawStd))
5357	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5358	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5359	AssertRCReturn(rc, rc);
5360	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5361	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5362
5363	CPUMCPUID aRawExt[32];
5364	uint32_t cRawExt;
5365	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5366	if (cRawExt > RT_ELEMENTS(aRawExt))
5367	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5368	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5369	AssertRCReturn(rc, rc);
5370	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5371	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5372
5373	/*
5374	* Get the raw CPU IDs for the current host.
5375	*/
5376	CPUMCPUID aHostRawStd[16];
5377	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5378	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5379
5380	CPUMCPUID aHostRawExt[32];
5381	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5382	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5383	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5384
5385	/*
5386	* Get the host and guest overrides so we don't reject the state because
5387	* some feature was enabled thru these interfaces.
5388	* Note! We currently only need the feature leaves, so skip rest.
5389	*/
5390	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5391	CPUMCPUID aHostOverrideStd[2];
5392	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5393	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5394
5395	CPUMCPUID aHostOverrideExt[2];
5396	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5397	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5398
5399	/*
5400	* This can be skipped.
5401	*/
5402	bool fStrictCpuIdChecks;
5403	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5404
5405	/*
5406	* Define a bunch of macros for simplifying the santizing/checking code below.
5407	*/
5408	/* Generic expression + failure message. */
5409	#define CPUID_CHECK_RET(expr, fmt) \
5410	do { \
5411	if (!(expr)) \
5412	{ \
5413	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5414	if (fStrictCpuIdChecks) \
5415	{ \
5416	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5417	RTStrFree(pszMsg); \
5418	return rcCpuid; \
5419	} \
5420	LogRel(("CPUM: %s\n", pszMsg)); \
5421	RTStrFree(pszMsg); \
5422	} \
5423	} while (0)
5424	#define CPUID_CHECK_WRN(expr, fmt) \
5425	do { \
5426	if (!(expr)) \
5427	LogRel(fmt); \
5428	} while (0)
5429
5430	/* For comparing two values and bitch if they differs. */
5431	#define CPUID_CHECK2_RET(what, host, saved) \
5432	do { \
5433	if ((host) != (saved)) \
5434	{ \
5435	if (fStrictCpuIdChecks) \
5436	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5437	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5438	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5439	} \
5440	} while (0)
5441	#define CPUID_CHECK2_WRN(what, host, saved) \
5442	do { \
5443	if ((host) != (saved)) \
5444	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5445	} while (0)
5446
5447	/* For checking raw cpu features (raw mode). */
5448	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5449	do { \
5450	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5451	{ \
5452	if (fStrictCpuIdChecks) \
5453	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5454	N_(#bit " mismatch: host=%d saved=%d"), \
5455	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5456	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5457	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5458	} \
5459	} while (0)
5460	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5461	do { \
5462	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5463	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5464	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5465	} while (0)
5466	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5467
5468	/* For checking guest features. */
5469	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5470	do { \
5471	if ( (aGuestCpuId##set [1].reg & bit) \
5472	&& !(aHostRaw##set [1].reg & bit) \
5473	&& !(aHostOverride##set [1].reg & bit) \
5474	) \
5475	{ \
5476	if (fStrictCpuIdChecks) \
5477	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5478	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5479	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5480	} \
5481	} while (0)
5482	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5483	do { \
5484	if ( (aGuestCpuId##set [1].reg & bit) \
5485	&& !(aHostRaw##set [1].reg & bit) \
5486	&& !(aHostOverride##set [1].reg & bit) \
5487	) \
5488	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5489	} while (0)
5490	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5491	do { \
5492	if ( (aGuestCpuId##set [1].reg & bit) \
5493	&& !(aHostRaw##set [1].reg & bit) \
5494	&& !(aHostOverride##set [1].reg & bit) \
5495	) \
5496	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5497	} while (0)
5498	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5499
5500	/* For checking guest features if AMD guest CPU. */
5501	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5502	do { \
5503	if ( (aGuestCpuId##set [1].reg & bit) \
5504	&& fGuestAmd \
5505	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5506	&& !(aHostOverride##set [1].reg & bit) \
5507	) \
5508	{ \
5509	if (fStrictCpuIdChecks) \
5510	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5511	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5512	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5513	} \
5514	} while (0)
5515	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5516	do { \
5517	if ( (aGuestCpuId##set [1].reg & bit) \
5518	&& fGuestAmd \
5519	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5520	&& !(aHostOverride##set [1].reg & bit) \
5521	) \
5522	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5523	} while (0)
5524	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5525	do { \
5526	if ( (aGuestCpuId##set [1].reg & bit) \
5527	&& fGuestAmd \
5528	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5529	&& !(aHostOverride##set [1].reg & bit) \
5530	) \
5531	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5532	} while (0)
5533	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5534
5535	/* For checking AMD features which have a corresponding bit in the standard
5536	range. (Intel defines very few bits in the extended feature sets.) */
5537	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5538	do { \
5539	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5540	&& !(fHostAmd \
5541	? aHostRawExt[1].reg & (ExtBit) \
5542	: aHostRawStd[1].reg & (StdBit)) \
5543	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5544	) \
5545	{ \
5546	if (fStrictCpuIdChecks) \
5547	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5548	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5549	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5550	} \
5551	} while (0)
5552	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5553	do { \
5554	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5555	&& !(fHostAmd \
5556	? aHostRawExt[1].reg & (ExtBit) \
5557	: aHostRawStd[1].reg & (StdBit)) \
5558	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5559	) \
5560	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5561	} while (0)
5562	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5563	do { \
5564	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5565	&& !(fHostAmd \
5566	? aHostRawExt[1].reg & (ExtBit) \
5567	: aHostRawStd[1].reg & (StdBit)) \
5568	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5569	) \
5570	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5571	} while (0)
5572	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5573
5574
5575	/*
5576	* Verify that we can support the features already exposed to the guest on
5577	* this host.
5578	*
5579	* Most of the features we're emulating requires intercepting instruction
5580	* and doing it the slow way, so there is no need to warn when they aren't
5581	* present in the host CPU. Thus we use IGN instead of EMU on these.
5582	*
5583	* Trailing comments:
5584	* "EMU" - Possible to emulate, could be lots of work and very slow.
5585	* "EMU?" - Can this be emulated?
5586	*/
5587	CPUMCPUID aGuestCpuIdStd[2];
5588	RT_ZERO(aGuestCpuIdStd);
5589	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5590
5591	/* CPUID(1).ecx */
5592	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5593	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5594	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5595	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5596	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5597	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5598	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5599	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5600	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5601	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5602	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5603	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5604	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5605	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5606	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5607	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5608	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5609	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5610	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5611	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5612	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5613	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5614	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5615	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5616	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5617	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5618	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5619	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5620	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5621	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5622	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5623	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5624
5625	/* CPUID(1).edx */
5626	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5627	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5628	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5629	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5630	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5631	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5632	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5633	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5634	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5635	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5636	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5637	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5638	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5639	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5640	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5641	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5642	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5643	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5644	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5645	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5646	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5647	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5648	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5649	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5650	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5651	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5652	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5653	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5654	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5655	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5656	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5657	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5658
5659	/* CPUID(0x80000000). */
5660	CPUMCPUID aGuestCpuIdExt[2];
5661	RT_ZERO(aGuestCpuIdExt);
5662	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5663	{
5664	/** @todo deal with no 0x80000001 on the host. */
5665	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5666	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5667
5668	/* CPUID(0x80000001).ecx */
5669	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5670	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5671	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5672	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5673	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5674	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5675	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5676	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5677	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5678	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5679	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5680	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5681	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5682	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5683	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5684	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5685	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5686	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5687	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5688	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5689	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5690	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5691	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5692	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5693	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5694	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5695	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5696	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5697	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5698	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5699	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5700	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5701
5702	/* CPUID(0x80000001).edx */
5703	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5704	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5705	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5706	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5707	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5708	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5709	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5710	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5711	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5712	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5713	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5714	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5715	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5716	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5717	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5718	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5719	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5720	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5721	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5722	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5723	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5724	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5725	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5726	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5727	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5728	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5729	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5730	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5731	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5732	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5733	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5734	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5735	}
5736
5737	/** @todo check leaf 7 */
5738
5739	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5740	* ECX=0: EAX - Valid bits in XCR0[31:0].
5741	* EBX - Maximum state size as per current XCR0 value.
5742	* ECX - Maximum state size for all supported features.
5743	* EDX - Valid bits in XCR0[63:32].
5744	* ECX=1: EAX - Various X-features.
5745	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5746	* ECX - Valid bits in IA32_XSS[31:0].
5747	* EDX - Valid bits in IA32_XSS[63:32].
5748	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5749	* if the bit invalid all four registers are set to zero.
5750	* EAX - The state size for this feature.
5751	* EBX - The state byte offset of this feature.
5752	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5753	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5754	*/
5755	uint64_t fGuestXcr0Mask = 0;
5756	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5757	if ( pCurLeaf
5758	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5759	&& ( pCurLeaf->uEax
5760	\|\| pCurLeaf->uEbx
5761	\|\| pCurLeaf->uEcx
5762	\|\| pCurLeaf->uEdx) )
5763	{
5764	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5765	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5766	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5767	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5768	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5769	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5770	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5771	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5772
5773	/* We don't support any additional features yet. */
5774	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5775	if (pCurLeaf && pCurLeaf->uEax)
5776	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5777	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5778	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5779	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5780	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5781	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5782
5783
5784	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5785	{
5786	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5787	if (pCurLeaf)
5788	{
5789	/* If advertised, the state component offset and size must match the one used by host. */
5790	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5791	{
5792	CPUMCPUID RawHost;
5793	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5794	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5795	if ( RawHost.uEbx != pCurLeaf->uEbx
5796	\|\| RawHost.uEax != pCurLeaf->uEax)
5797	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5798	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5799	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5800	}
5801	}
5802	}
5803	}
5804	/* Clear leaf 0xd just in case we're loading an old state... */
5805	else if (pCurLeaf)
5806	{
5807	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5808	{
5809	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5810	if (pCurLeaf)
5811	{
5812	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5813	\|\| ( pCurLeaf->uEax == 0
5814	&& pCurLeaf->uEbx == 0
5815	&& pCurLeaf->uEcx == 0
5816	&& pCurLeaf->uEdx == 0),
5817	("uVersion=%#x; %#x %#x %#x %#x\n",
5818	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5819	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5820	}
5821	}
5822	}
5823
5824	/* Update the fXStateGuestMask value for the VM. */
5825	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5826	{
5827	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5828	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5829	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5830	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5831	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5832	}
5833
5834	#undef CPUID_CHECK_RET
5835	#undef CPUID_CHECK_WRN
5836	#undef CPUID_CHECK2_RET
5837	#undef CPUID_CHECK2_WRN
5838	#undef CPUID_RAW_FEATURE_RET
5839	#undef CPUID_RAW_FEATURE_WRN
5840	#undef CPUID_RAW_FEATURE_IGN
5841	#undef CPUID_GST_FEATURE_RET
5842	#undef CPUID_GST_FEATURE_WRN
5843	#undef CPUID_GST_FEATURE_EMU
5844	#undef CPUID_GST_FEATURE_IGN
5845	#undef CPUID_GST_FEATURE2_RET
5846	#undef CPUID_GST_FEATURE2_WRN
5847	#undef CPUID_GST_FEATURE2_EMU
5848	#undef CPUID_GST_FEATURE2_IGN
5849	#undef CPUID_GST_AMD_FEATURE_RET
5850	#undef CPUID_GST_AMD_FEATURE_WRN
5851	#undef CPUID_GST_AMD_FEATURE_EMU
5852	#undef CPUID_GST_AMD_FEATURE_IGN
5853
5854	/*
5855	* We're good, commit the CPU ID leaves.
5856	*/
5857	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5858	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5859	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5860	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5861	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
5862	AssertLogRelRCReturn(rc, rc);
5863
5864	return VINF_SUCCESS;
5865	}
5866
5867
5868	/**
5869	* Loads the CPU ID leaves saved by pass 0.
5870	*
5871	* @returns VBox status code.
5872	* @param pVM The cross context VM structure.
5873	* @param pSSM The saved state handle.
5874	* @param uVersion The format version.
5875	* @param pMsrs The guest MSRs.
5876	*/
5877	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
5878	{
5879	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5880
5881	/*
5882	* Load the CPUID leaves array first and call worker to do the rest, just so
5883	* we can free the memory when we need to without ending up in column 1000.
5884	*/
5885	PCPUMCPUIDLEAF paLeaves;
5886	uint32_t cLeaves;
5887	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5888	AssertRC(rc);
5889	if (RT_SUCCESS(rc))
5890	{
5891	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
5892	RTMemFree(paLeaves);
5893	}
5894	return rc;
5895	}
5896
5897
5898
5899	/**
5900	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5901	*
5902	* @returns VBox status code.
5903	* @param pVM The cross context VM structure.
5904	* @param pSSM The saved state handle.
5905	* @param uVersion The format version.
5906	*/
5907	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5908	{
5909	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5910
5911	/*
5912	* Restore the CPUID leaves.
5913	*
5914	* Note that we support restoring less than the current amount of standard
5915	* leaves because we've been allowed more is newer version of VBox.
5916	*/
5917	uint32_t cElements;
5918	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5919	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5920	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5921	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5922
5923	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5924	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5925	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5926	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5927
5928	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5929	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5930	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5931	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5932
5933	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5934
5935	/*
5936	* Check that the basic cpuid id information is unchanged.
5937	*/
5938	/** @todo we should check the 64 bits capabilities too! */
5939	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5940	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5941	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5942	uint32_t au32CpuIdSaved[8];
5943	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5944	if (RT_SUCCESS(rc))
5945	{
5946	/* Ignore CPU stepping. */
5947	au32CpuId[4] &= 0xfffffff0;
5948	au32CpuIdSaved[4] &= 0xfffffff0;
5949
5950	/* Ignore APIC ID (AMD specs). */
5951	au32CpuId[5] &= ~0xff000000;
5952	au32CpuIdSaved[5] &= ~0xff000000;
5953
5954	/* Ignore the number of Logical CPUs (AMD specs). */
5955	au32CpuId[5] &= ~0x00ff0000;
5956	au32CpuIdSaved[5] &= ~0x00ff0000;
5957
5958	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5959	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5960	\| X86_CPUID_FEATURE_ECX_VMX
5961	\| X86_CPUID_FEATURE_ECX_SMX
5962	\| X86_CPUID_FEATURE_ECX_EST
5963	\| X86_CPUID_FEATURE_ECX_TM2
5964	\| X86_CPUID_FEATURE_ECX_CNTXID
5965	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5966	\| X86_CPUID_FEATURE_ECX_PDCM
5967	\| X86_CPUID_FEATURE_ECX_DCA
5968	\| X86_CPUID_FEATURE_ECX_X2APIC
5969	);
5970	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5971	\| X86_CPUID_FEATURE_ECX_VMX
5972	\| X86_CPUID_FEATURE_ECX_SMX
5973	\| X86_CPUID_FEATURE_ECX_EST
5974	\| X86_CPUID_FEATURE_ECX_TM2
5975	\| X86_CPUID_FEATURE_ECX_CNTXID
5976	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5977	\| X86_CPUID_FEATURE_ECX_PDCM
5978	\| X86_CPUID_FEATURE_ECX_DCA
5979	\| X86_CPUID_FEATURE_ECX_X2APIC
5980	);
5981
5982	/* Make sure we don't forget to update the masks when enabling
5983	* features in the future.
5984	*/
5985	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5986	( X86_CPUID_FEATURE_ECX_DTES64
5987	\| X86_CPUID_FEATURE_ECX_VMX
5988	\| X86_CPUID_FEATURE_ECX_SMX
5989	\| X86_CPUID_FEATURE_ECX_EST
5990	\| X86_CPUID_FEATURE_ECX_TM2
5991	\| X86_CPUID_FEATURE_ECX_CNTXID
5992	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5993	\| X86_CPUID_FEATURE_ECX_PDCM
5994	\| X86_CPUID_FEATURE_ECX_DCA
5995	\| X86_CPUID_FEATURE_ECX_X2APIC
5996	)));
5997	/* do the compare */
5998	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5999	{
6000	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
6001	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
6002	"Saved=%.*Rhxs\n"
6003	"Real =%.*Rhxs\n",
6004	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6005	sizeof(au32CpuId), au32CpuId));
6006	else
6007	{
6008	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
6009	"Saved=%.*Rhxs\n"
6010	"Real =%.*Rhxs\n",
6011	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6012	sizeof(au32CpuId), au32CpuId));
6013	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
6014	}
6015	}
6016	}
6017
6018	return rc;
6019	}
6020
6021
6022
6023	/*
6024	*
6025	*
6026	* CPUID Info Handler.
6027	* CPUID Info Handler.
6028	* CPUID Info Handler.
6029	*
6030	*
6031	*/
6032
6033
6034
6035	/**
6036	* Get L1 cache / TLS associativity.
6037	*/
6038	static const char getCacheAss(unsigned u, char pszBuf)
6039	{
6040	if (u == 0)
6041	return "res0 ";
6042	if (u == 1)
6043	return "direct";
6044	if (u == 255)
6045	return "fully";
6046	if (u >= 256)
6047	return "???";
6048
6049	RTStrPrintf(pszBuf, 16, "%d way", u);
6050	return pszBuf;
6051	}
6052
6053
6054	/**
6055	* Get L2 cache associativity.
6056	*/
6057	const char *getL2CacheAss(unsigned u)
6058	{
6059	switch (u)
6060	{
6061	case 0: return "off ";
6062	case 1: return "direct";
6063	case 2: return "2 way ";
6064	case 3: return "res3 ";
6065	case 4: return "4 way ";
6066	case 5: return "res5 ";
6067	case 6: return "8 way ";
6068	case 7: return "res7 ";
6069	case 8: return "16 way";
6070	case 9: return "res9 ";
6071	case 10: return "res10 ";
6072	case 11: return "res11 ";
6073	case 12: return "res12 ";
6074	case 13: return "res13 ";
6075	case 14: return "res14 ";
6076	case 15: return "fully ";
6077	default: return "????";
6078	}
6079	}
6080
6081
6082	/** CPUID(1).EDX field descriptions. */
6083	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6084	{
6085	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6086	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6087	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6088	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6089	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6090	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6091	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6092	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6093	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6094	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6095	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6096	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6097	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6098	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6099	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6100	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6101	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6102	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6103	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6104	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6105	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6106	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6107	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6108	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6109	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6110	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6111	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6112	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6113	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6114	DBGFREGSUBFIELD_TERMINATOR()
6115	};
6116
6117	/** CPUID(1).ECX field descriptions. */
6118	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6119	{
6120	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6121	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6122	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6123	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6124	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6125	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6126	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6127	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6128	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6129	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6130	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6131	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6132	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6133	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6134	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6135	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6136	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6137	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6138	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6139	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6140	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6141	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6142	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6143	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6144	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6145	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6146	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6147	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6148	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6149	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6150	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6151	DBGFREGSUBFIELD_TERMINATOR()
6152	};
6153
6154	/** CPUID(7,0).EBX field descriptions. */
6155	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6156	{
6157	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6158	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6159	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6160	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6161	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6162	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6163	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6164	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6165	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6166	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6167	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6168	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6169	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6170	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6171	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6172	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6173	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6174	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6175	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6176	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6177	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6178	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6179	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6180	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6181	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6182	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6183	DBGFREGSUBFIELD_TERMINATOR()
6184	};
6185
6186	/** CPUID(7,0).ECX field descriptions. */
6187	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6188	{
6189	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6190	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6191	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6192	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6193	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6194	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6195	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6196	DBGFREGSUBFIELD_TERMINATOR()
6197	};
6198
6199	/** CPUID(7,0).EDX field descriptions. */
6200	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6201	{
6202	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
6203	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6204	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6205	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
6206	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6207	DBGFREGSUBFIELD_RO("CORECAP\0" "Supports IA32_CORE_CAP", 30, 1, 0),
6208	DBGFREGSUBFIELD_RO("SSBD\0" "Supports IA32_SPEC_CTRL.SSBD", 31, 1, 0),
6209	DBGFREGSUBFIELD_TERMINATOR()
6210	};
6211
6212
6213	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6214	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6215	{
6216	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6217	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6218	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6219	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6220	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6221	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6222	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6223	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6224	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6225	DBGFREGSUBFIELD_TERMINATOR()
6226	};
6227
6228	/** CPUID(13,1).EAX field descriptions. */
6229	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6230	{
6231	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6232	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6233	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6234	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6235	DBGFREGSUBFIELD_TERMINATOR()
6236	};
6237
6238
6239	/** CPUID(0x80000001,0).EDX field descriptions. */
6240	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6241	{
6242	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6243	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6244	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6245	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6246	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6247	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6248	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6249	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6250	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6251	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6252	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6253	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6254	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6255	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6256	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6257	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6258	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6259	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6260	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6261	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6262	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6263	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6264	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6265	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6266	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6267	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6268	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6269	DBGFREGSUBFIELD_TERMINATOR()
6270	};
6271
6272	/** CPUID(0x80000001,0).ECX field descriptions. */
6273	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6274	{
6275	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6276	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6277	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6278	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6279	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6280	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6281	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6282	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6283	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6284	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6285	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6286	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6287	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6288	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6289	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6290	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6291	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6292	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6293	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6294	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6295	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6296	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6297	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6298	DBGFREGSUBFIELD_TERMINATOR()
6299	};
6300
6301	/** CPUID(0x8000000a,0).EDX field descriptions. */
6302	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6303	{
6304	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6305	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6306	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6307	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6308	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6309	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6310	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6311	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6312	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6313	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6314	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6315	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6316	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6317	DBGFREGSUBFIELD_RO("GMET\0" "Guest Mode Execute Trap Extension", 17, 1, 0),
6318	DBGFREGSUBFIELD_TERMINATOR()
6319	};
6320
6321
6322	/** CPUID(0x80000007,0).EDX field descriptions. */
6323	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6324	{
6325	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6326	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6327	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6328	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6329	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6330	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6331	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6332	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6333	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6334	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6335	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6336	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6337	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6338	DBGFREGSUBFIELD_TERMINATOR()
6339	};
6340
6341	/** CPUID(0x80000008,0).EBX field descriptions. */
6342	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6343	{
6344	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6345	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6346	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6347	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6348	DBGFREGSUBFIELD_TERMINATOR()
6349	};
6350
6351
6352	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6353	const char *pszLeadIn, uint32_t cchWidth)
6354	{
6355	if (pszLeadIn)
6356	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6357
6358	for (uint32_t iBit = 0; iBit < 32; iBit++)
6359	if (RT_BIT_32(iBit) & uVal)
6360	{
6361	while ( pDesc->pszName != NULL
6362	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6363	pDesc++;
6364	if ( pDesc->pszName != NULL
6365	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6366	{
6367	if (pDesc->cBits == 1)
6368	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6369	else
6370	{
6371	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6372	if (pDesc->cBits < 32)
6373	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6374	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6375	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6376	}
6377	}
6378	else
6379	pHlp->pfnPrintf(pHlp, " %u", iBit);
6380	}
6381	if (pszLeadIn)
6382	pHlp->pfnPrintf(pHlp, "\n");
6383	}
6384
6385
6386	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6387	const char *pszLeadIn, uint32_t cchWidth)
6388	{
6389	if (pszLeadIn)
6390	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6391
6392	for (uint32_t iBit = 0; iBit < 64; iBit++)
6393	if (RT_BIT_64(iBit) & uVal)
6394	{
6395	while ( pDesc->pszName != NULL
6396	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6397	pDesc++;
6398	if ( pDesc->pszName != NULL
6399	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6400	{
6401	if (pDesc->cBits == 1)
6402	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6403	else
6404	{
6405	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6406	if (pDesc->cBits < 64)
6407	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6408	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6409	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6410	}
6411	}
6412	else
6413	pHlp->pfnPrintf(pHlp, " %u", iBit);
6414	}
6415	if (pszLeadIn)
6416	pHlp->pfnPrintf(pHlp, "\n");
6417	}
6418
6419
6420	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6421	const char *pszLeadIn, uint32_t cchWidth)
6422	{
6423	if (!uVal)
6424	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6425	else
6426	{
6427	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6428	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6429	pHlp->pfnPrintf(pHlp, " )\n");
6430	}
6431	}
6432
6433
6434	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6435	uint32_t cchWidth)
6436	{
6437	uint32_t uCombined = uVal1 \| uVal2;
6438	for (uint32_t iBit = 0; iBit < 32; iBit++)
6439	if ( (RT_BIT_32(iBit) & uCombined)
6440	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6441	{
6442	while ( pDesc->pszName != NULL
6443	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6444	pDesc++;
6445
6446	if ( pDesc->pszName != NULL
6447	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6448	{
6449	size_t cchMnemonic = strlen(pDesc->pszName);
6450	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6451	size_t cchDesc = strlen(pszDesc);
6452	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6453	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6454	if (pDesc->cBits < 32)
6455	{
6456	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6457	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6458	}
6459
6460	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6461	pDesc->pszName, pszDesc,
6462	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6463	uFieldValue1, uFieldValue2);
6464
6465	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6466	pDesc++;
6467	}
6468	else
6469	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6470	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6471	}
6472	}
6473
6474
6475	/**
6476	* Produces a detailed summary of standard leaf 0x00000001.
6477	*
6478	* @param pHlp The info helper functions.
6479	* @param pCurLeaf The 0x00000001 leaf.
6480	* @param fVerbose Whether to be very verbose or not.
6481	* @param fIntel Set if intel CPU.
6482	*/
6483	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6484	{
6485	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6486	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6487	uint32_t uEAX = pCurLeaf->uEax;
6488	uint32_t uEBX = pCurLeaf->uEbx;
6489
6490	pHlp->pfnPrintf(pHlp,
6491	"%36s %2d \tExtended: %d \tEffective: %d\n"
6492	"%36s %2d \tExtended: %d \tEffective: %d\n"
6493	"%36s %d\n"
6494	"%36s %d (%s)\n"
6495	"%36s %#04x\n"
6496	"%36s %d\n"
6497	"%36s %d\n"
6498	"%36s %#04x\n"
6499	,
6500	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6501	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6502	"Stepping:", ASMGetCpuStepping(uEAX),
6503	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6504	"APIC ID:", (uEBX >> 24) & 0xff,
6505	"Logical CPUs:",(uEBX >> 16) & 0xff,
6506	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6507	"Brand ID:", (uEBX >> 0) & 0xff);
6508	if (fVerbose)
6509	{
6510	CPUMCPUID Host;
6511	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6512	pHlp->pfnPrintf(pHlp, "Features\n");
6513	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6514	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6515	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6516	}
6517	else
6518	{
6519	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6520	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6521	}
6522	}
6523
6524
6525	/**
6526	* Produces a detailed summary of standard leaf 0x00000007.
6527	*
6528	* @param pHlp The info helper functions.
6529	* @param paLeaves The CPUID leaves array.
6530	* @param cLeaves The number of leaves in the array.
6531	* @param pCurLeaf The first 0x00000007 leaf.
6532	* @param fVerbose Whether to be very verbose or not.
6533	*/
6534	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6535	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6536	{
6537	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6538	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6539	for (;;)
6540	{
6541	CPUMCPUID Host;
6542	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6543
6544	switch (pCurLeaf->uSubLeaf)
6545	{
6546	case 0:
6547	if (fVerbose)
6548	{
6549	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6550	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6551	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6552	if (pCurLeaf->uEdx \|\| Host.uEdx)
6553	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6554	}
6555	else
6556	{
6557	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6558	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6559	if (pCurLeaf->uEdx)
6560	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6561	}
6562	break;
6563
6564	default:
6565	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6566	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6567	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6568	break;
6569
6570	}
6571
6572	/* advance. */
6573	pCurLeaf++;
6574	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6575	\|\| pCurLeaf->uLeaf != 0x7)
6576	break;
6577	}
6578	}
6579
6580
6581	/**
6582	* Produces a detailed summary of standard leaf 0x0000000d.
6583	*
6584	* @param pHlp The info helper functions.
6585	* @param paLeaves The CPUID leaves array.
6586	* @param cLeaves The number of leaves in the array.
6587	* @param pCurLeaf The first 0x00000007 leaf.
6588	* @param fVerbose Whether to be very verbose or not.
6589	*/
6590	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6591	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6592	{
6593	RT_NOREF_PV(fVerbose);
6594	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6595	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6596	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6597	{
6598	CPUMCPUID Host;
6599	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6600
6601	switch (uSubLeaf)
6602	{
6603	case 0:
6604	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6605	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6606	pCurLeaf->uEbx, pCurLeaf->uEcx);
6607	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6608
6609	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6610	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6611	"Valid XCR0 bits, guest:", 42);
6612	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6613	"Valid XCR0 bits, host:", 42);
6614	break;
6615
6616	case 1:
6617	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6618	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6619	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6620
6621	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6622	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6623	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6624
6625	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6626	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6627	" Valid IA32_XSS bits, guest:", 42);
6628	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6629	" Valid IA32_XSS bits, host:", 42);
6630	break;
6631
6632	default:
6633	if ( pCurLeaf
6634	&& pCurLeaf->uSubLeaf == uSubLeaf
6635	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6636	{
6637	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6638	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6639	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6640	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6641	if (pCurLeaf->uEdx)
6642	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6643	pHlp->pfnPrintf(pHlp, " --");
6644	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6645	pHlp->pfnPrintf(pHlp, "\n");
6646	}
6647	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6648	{
6649	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6650	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6651	if (Host.uEcx & ~RT_BIT_32(0))
6652	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6653	if (Host.uEdx)
6654	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6655	pHlp->pfnPrintf(pHlp, " --");
6656	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6657	pHlp->pfnPrintf(pHlp, "\n");
6658	}
6659	break;
6660
6661	}
6662
6663	/* advance. */
6664	if (pCurLeaf)
6665	{
6666	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6667	&& pCurLeaf->uSubLeaf <= uSubLeaf
6668	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6669	pCurLeaf++;
6670	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6671	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6672	pCurLeaf = NULL;
6673	}
6674	}
6675	}
6676
6677
6678	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6679	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6680	{
6681	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6682	&& pCurLeaf->uLeaf <= uUpToLeaf)
6683	{
6684	pHlp->pfnPrintf(pHlp,
6685	" %s\n"
6686	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6687	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6688	&& pCurLeaf->uLeaf <= uUpToLeaf)
6689	{
6690	CPUMCPUID Host;
6691	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6692	pHlp->pfnPrintf(pHlp,
6693	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6694	"Hst: %08x %08x %08x %08x\n",
6695	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6696	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6697	pCurLeaf++;
6698	}
6699	}
6700
6701	return pCurLeaf;
6702	}
6703
6704
6705	/**
6706	* Display the guest CpuId leaves.
6707	*
6708	* @param pVM The cross context VM structure.
6709	* @param pHlp The info helper functions.
6710	* @param pszArgs "terse", "default" or "verbose".
6711	*/
6712	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6713	{
6714	/*
6715	* Parse the argument.
6716	*/
6717	unsigned iVerbosity = 1;
6718	if (pszArgs)
6719	{
6720	pszArgs = RTStrStripL(pszArgs);
6721	if (!strcmp(pszArgs, "terse"))
6722	iVerbosity--;
6723	else if (!strcmp(pszArgs, "verbose"))
6724	iVerbosity++;
6725	}
6726
6727	uint32_t uLeaf;
6728	CPUMCPUID Host;
6729	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6730	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6731	PCCPUMCPUIDLEAF pCurLeaf;
6732	PCCPUMCPUIDLEAF pNextLeaf;
6733	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6734	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6735	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6736
6737	/*
6738	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6739	*/
6740	uint32_t cHstMax = ASMCpuId_EAX(0);
6741	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6742	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6743	pHlp->pfnPrintf(pHlp,
6744	" Raw Standard CPUID Leaves\n"
6745	" Leaf/sub-leaf eax ebx ecx edx\n");
6746	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6747	{
6748	uint32_t cMaxSubLeaves = 1;
6749	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6750	cMaxSubLeaves = 16;
6751	else if (uLeaf == 0xd)
6752	cMaxSubLeaves = 128;
6753
6754	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6755	{
6756	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6757	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6758	&& pCurLeaf->uLeaf == uLeaf
6759	&& pCurLeaf->uSubLeaf == uSubLeaf)
6760	{
6761	pHlp->pfnPrintf(pHlp,
6762	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6763	"Hst: %08x %08x %08x %08x\n",
6764	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6765	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6766	pCurLeaf++;
6767	}
6768	else if ( uLeaf != 0xd
6769	\|\| uSubLeaf <= 1
6770	\|\| Host.uEbx != 0 )
6771	pHlp->pfnPrintf(pHlp,
6772	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6773	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6774
6775	/* Done? */
6776	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6777	\|\| pCurLeaf->uLeaf != uLeaf)
6778	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6779	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6780	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6781	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6782	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6783	)
6784	)
6785	break;
6786	}
6787	}
6788	pNextLeaf = pCurLeaf;
6789
6790	/*
6791	* If verbose, decode it.
6792	*/
6793	if (iVerbosity && paLeaves[0].uLeaf == 0)
6794	pHlp->pfnPrintf(pHlp,
6795	"%36s %.04s%.04s%.04s\n"
6796	"%36s 0x00000000-%#010x\n"
6797	,
6798	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6799	"Supports:", paLeaves[0].uEax);
6800
6801	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6802	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6803
6804	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6805	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6806
6807	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6808	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6809
6810	pCurLeaf = pNextLeaf;
6811
6812	/*
6813	* Hypervisor leaves.
6814	*
6815	* Unlike most of the other leaves reported, the guest hypervisor leaves
6816	* aren't a subset of the host CPUID bits.
6817	*/
6818	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6819
6820	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6821	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6822	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6823	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6824	cMax = RT_MAX(cHstMax, cGstMax);
6825	if (cMax >= UINT32_C(0x40000000))
6826	{
6827	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6828
6829	/** @todo dump these in more detail. */
6830
6831	pCurLeaf = pNextLeaf;
6832	}
6833
6834
6835	/*
6836	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6837	* Implemented after AMD specs.
6838	*/
6839	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6840
6841	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6842	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6843	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6844	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6845	cMax = RT_MAX(cHstMax, cGstMax);
6846	if (cMax >= UINT32_C(0x80000000))
6847	{
6848
6849	pHlp->pfnPrintf(pHlp,
6850	" Raw Extended CPUID Leaves\n"
6851	" Leaf/sub-leaf eax ebx ecx edx\n");
6852	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6853	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6854	{
6855	uint32_t cMaxSubLeaves = 1;
6856	if (uLeaf == UINT32_C(0x8000001d))
6857	cMaxSubLeaves = 16;
6858
6859	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6860	{
6861	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6862	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6863	&& pCurLeaf->uLeaf == uLeaf
6864	&& pCurLeaf->uSubLeaf == uSubLeaf)
6865	{
6866	pHlp->pfnPrintf(pHlp,
6867	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6868	"Hst: %08x %08x %08x %08x\n",
6869	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6870	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6871	pCurLeaf++;
6872	}
6873	else if ( uLeaf != 0xd
6874	\|\| uSubLeaf <= 1
6875	\|\| Host.uEbx != 0 )
6876	pHlp->pfnPrintf(pHlp,
6877	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6878	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6879
6880	/* Done? */
6881	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6882	\|\| pCurLeaf->uLeaf != uLeaf)
6883	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6884	break;
6885	}
6886	}
6887	pNextLeaf = pCurLeaf;
6888
6889	/*
6890	* Understandable output
6891	*/
6892	if (iVerbosity)
6893	pHlp->pfnPrintf(pHlp,
6894	"Ext Name: %.4s%.4s%.4s\n"
6895	"Ext Supports: 0x80000000-%#010x\n",
6896	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6897
6898	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6899	if (iVerbosity && pCurLeaf)
6900	{
6901	uint32_t uEAX = pCurLeaf->uEax;
6902	pHlp->pfnPrintf(pHlp,
6903	"Family: %d \tExtended: %d \tEffective: %d\n"
6904	"Model: %d \tExtended: %d \tEffective: %d\n"
6905	"Stepping: %d\n"
6906	"Brand ID: %#05x\n",
6907	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6908	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6909	ASMGetCpuStepping(uEAX),
6910	pCurLeaf->uEbx & 0xfff);
6911
6912	if (iVerbosity == 1)
6913	{
6914	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6915	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6916	}
6917	else
6918	{
6919	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6920	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6921	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6922	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6923	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6924	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
6925	{
6926	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
6927	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6928	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
6929	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
6930	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
6931	}
6932	}
6933	}
6934
6935	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6936	{
6937	char szString[443+1] = {0};
6938	uint32_t pu32 = (uint32_t )szString;
6939	*pu32++ = pCurLeaf->uEax;
6940	*pu32++ = pCurLeaf->uEbx;
6941	*pu32++ = pCurLeaf->uEcx;
6942	*pu32++ = pCurLeaf->uEdx;
6943	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6944	if (pCurLeaf)
6945	{
6946	*pu32++ = pCurLeaf->uEax;
6947	*pu32++ = pCurLeaf->uEbx;
6948	*pu32++ = pCurLeaf->uEcx;
6949	*pu32++ = pCurLeaf->uEdx;
6950	}
6951	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6952	if (pCurLeaf)
6953	{
6954	*pu32++ = pCurLeaf->uEax;
6955	*pu32++ = pCurLeaf->uEbx;
6956	*pu32++ = pCurLeaf->uEcx;
6957	*pu32++ = pCurLeaf->uEdx;
6958	}
6959	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6960	}
6961
6962	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6963	{
6964	uint32_t uEAX = pCurLeaf->uEax;
6965	uint32_t uEBX = pCurLeaf->uEbx;
6966	uint32_t uECX = pCurLeaf->uEcx;
6967	uint32_t uEDX = pCurLeaf->uEdx;
6968	char sz1[32];
6969	char sz2[32];
6970
6971	pHlp->pfnPrintf(pHlp,
6972	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6973	"TLB 2/4M Data: %s %3d entries\n",
6974	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6975	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6976	pHlp->pfnPrintf(pHlp,
6977	"TLB 4K Instr/Uni: %s %3d entries\n"
6978	"TLB 4K Data: %s %3d entries\n",
6979	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6980	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6981	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6982	"L1 Instr Cache Lines Per Tag: %d\n"
6983	"L1 Instr Cache Associativity: %s\n"
6984	"L1 Instr Cache Size: %d KB\n",
6985	(uEDX >> 0) & 0xff,
6986	(uEDX >> 8) & 0xff,
6987	getCacheAss((uEDX >> 16) & 0xff, sz1),
6988	(uEDX >> 24) & 0xff);
6989	pHlp->pfnPrintf(pHlp,
6990	"L1 Data Cache Line Size: %d bytes\n"
6991	"L1 Data Cache Lines Per Tag: %d\n"
6992	"L1 Data Cache Associativity: %s\n"
6993	"L1 Data Cache Size: %d KB\n",
6994	(uECX >> 0) & 0xff,
6995	(uECX >> 8) & 0xff,
6996	getCacheAss((uECX >> 16) & 0xff, sz1),
6997	(uECX >> 24) & 0xff);
6998	}
6999
7000	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
7001	{
7002	uint32_t uEAX = pCurLeaf->uEax;
7003	uint32_t uEBX = pCurLeaf->uEbx;
7004	uint32_t uEDX = pCurLeaf->uEdx;
7005
7006	pHlp->pfnPrintf(pHlp,
7007	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
7008	"L2 TLB 2/4M Data: %s %4d entries\n",
7009	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
7010	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
7011	pHlp->pfnPrintf(pHlp,
7012	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
7013	"L2 TLB 4K Data: %s %4d entries\n",
7014	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
7015	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
7016	pHlp->pfnPrintf(pHlp,
7017	"L2 Cache Line Size: %d bytes\n"
7018	"L2 Cache Lines Per Tag: %d\n"
7019	"L2 Cache Associativity: %s\n"
7020	"L2 Cache Size: %d KB\n",
7021	(uEDX >> 0) & 0xff,
7022	(uEDX >> 8) & 0xf,
7023	getL2CacheAss((uEDX >> 12) & 0xf),
7024	(uEDX >> 16) & 0xffff);
7025	}
7026
7027	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
7028	{
7029	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7030	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
7031	{
7032	if (iVerbosity < 1)
7033	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7034	else
7035	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7036	}
7037	}
7038
7039	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7040	if (pCurLeaf != NULL)
7041	{
7042	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7043	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7044	{
7045	if (iVerbosity < 1)
7046	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7047	else
7048	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7049	}
7050
7051	if (iVerbosity)
7052	{
7053	uint32_t uEAX = pCurLeaf->uEax;
7054	uint32_t uECX = pCurLeaf->uEcx;
7055
7056	pHlp->pfnPrintf(pHlp,
7057	"Physical Address Width: %d bits\n"
7058	"Virtual Address Width: %d bits\n"
7059	"Guest Physical Address Width: %d bits\n",
7060	(uEAX >> 0) & 0xff,
7061	(uEAX >> 8) & 0xff,
7062	(uEAX >> 16) & 0xff);
7063	pHlp->pfnPrintf(pHlp,
7064	"Physical Core Count: %d\n",
7065	((uECX >> 0) & 0xff) + 1);
7066	}
7067	}
7068
7069	pCurLeaf = pNextLeaf;
7070	}
7071
7072
7073
7074	/*
7075	* Centaur.
7076	*/
7077	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7078
7079	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7080	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7081	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7082	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7083	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7084	cMax = RT_MAX(cHstMax, cGstMax);
7085	if (cMax >= UINT32_C(0xc0000000))
7086	{
7087	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7088
7089	/*
7090	* Understandable output
7091	*/
7092	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7093	pHlp->pfnPrintf(pHlp,
7094	"Centaur Supports: 0xc0000000-%#010x\n",
7095	pCurLeaf->uEax);
7096
7097	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7098	{
7099	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7100	uint32_t uEdxGst = pCurLeaf->uEdx;
7101	uint32_t uEdxHst = Host.uEdx;
7102
7103	if (iVerbosity == 1)
7104	{
7105	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7106	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7107	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7108	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7109	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7110	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7111	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7112	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7113	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7114	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7115	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7116	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7117	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7118	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7119	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7120	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7121	for (unsigned iBit = 14; iBit < 32; iBit++)
7122	if (uEdxGst & RT_BIT(iBit))
7123	pHlp->pfnPrintf(pHlp, " %d", iBit);
7124	pHlp->pfnPrintf(pHlp, "\n");
7125	}
7126	else
7127	{
7128	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7129	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7130	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7131	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7132	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7133	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7134	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7135	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7136	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7137	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7138	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7139	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7140	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7141	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7142	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7143	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7144	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7145	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7146	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7147	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7148	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7149	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7150	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7151	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7152	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7153	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7154	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7155	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7156	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7157	for (unsigned iBit = 27; iBit < 32; iBit++)
7158	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7159	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7160	pHlp->pfnPrintf(pHlp, "\n");
7161	}
7162	}
7163
7164	pCurLeaf = pNextLeaf;
7165	}
7166
7167	/*
7168	* The remainder.
7169	*/
7170	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7171	}
7172
7173	#endif /* !IN_VBOX_CPU_REPORT */
7174

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 81240

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