CPUMR3CpuId.cpp@ 90703

Last change on this file since 90703 was 90204, checked in by vboxsync, 4 years ago
VMM/CPUM: Todo/comment to clarify 'Guest physical address width' being reported as 0.
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File size: 341.8 KB

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1	/* $Id: CPUMR3CpuId.cpp 90204 2021-07-15 05:02:11Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vmcc.h>
30	#include <VBox/vmm/mm.h>
31	#include <VBox/sup.h>
32
33	#include <VBox/err.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/ctype.h>
36	#include <iprt/mem.h>
37	#include <iprt/string.h>
38
39
40	/*********************************************************************************************************************************
41	* Defined Constants And Macros *
42	*********************************************************************************************************************************/
43	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
44	#define CPUM_CPUID_MAX_LEAVES 2048
45	/* Max size we accept for the XSAVE area. */
46	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
47	/* Min size we accept for the XSAVE area. */
48	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
49
50
51	/*********************************************************************************************************************************
52	* Global Variables *
53	*********************************************************************************************************************************/
54	/**
55	* The intel pentium family.
56	*/
57	static const CPUMMICROARCH g_aenmIntelFamily06[] =
58	{
59	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
60	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
61	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
63	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
64	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
65	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
66	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
67	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
68	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
69	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
70	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
71	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
72	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
73	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
74	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
75	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
81	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
82	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
83	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [26(0x1a)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Nehalem-EP */
86	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
88	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
89	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
90	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
91	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
97	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
98	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
99	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
102	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
104	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
105	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
106	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
107	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
113	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
114	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
115	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
118	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
121	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
122	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
130	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
131	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
136	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,
138	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Broadwell-E */
139	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu; skylake <= 4, cascade lake > 5 */
145	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
146	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
147	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
150	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
152	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
153	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
154	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
155	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
159	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
160	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
161	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
162	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
163	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
164	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
165	/[106(0x6a)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
166	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
167	/[108(0x6c)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
168	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
169	/[110(0x6e)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
170	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
171	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
172	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
173	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
174	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
175	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
176	/[117(0x75)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
177	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
178	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
179	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
180	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
181	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
182	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
183	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
184	/[125(0x7d)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
185	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
186	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
187	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
188	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
189	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
190	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
191	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
192	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
193	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
194	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
195	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
196	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
197	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
198	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
199	/[140(0x8c)] = / kCpumMicroarch_Intel_Core7_TigerLake, /* 11th Gen Intel(R) Core(TM) i7-1185G7 @ 3.00GHz (bird) */
200	/[141(0x8d)] = / kCpumMicroarch_Intel_Core7_TigerLake, /* unconfirmed */
201	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
202	/[143(0x8f)] = / kCpumMicroarch_Intel_Core7_SapphireRapids,
203	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
204	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
205	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
206	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
207	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
208	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
209	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
210	/[151(0x97)] = / kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
211	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
212	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
213	/[154(0x9a)] = / kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
214	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
215	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
216	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
217	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
218	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
219	/[160(0xa0)] = / kCpumMicroarch_Intel_Unknown,
220	/[161(0xa1)] = / kCpumMicroarch_Intel_Unknown,
221	/[162(0xa2)] = / kCpumMicroarch_Intel_Unknown,
222	/[163(0xa3)] = / kCpumMicroarch_Intel_Unknown,
223	/[164(0xa4)] = / kCpumMicroarch_Intel_Unknown,
224	/[165(0xa5)] = / kCpumMicroarch_Intel_Core7_CometLake, /* unconfirmed */
225	/[166(0xa6)] = / kCpumMicroarch_Intel_Unknown,
226	/[167(0xa7)] = / kCpumMicroarch_Intel_Core7_CypressCove, /* 14nm backport, unconfirmed */
227	};
228	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0xa7+1);
229
230
231	/**
232	* Figures out the (sub-)micro architecture given a bit of CPUID info.
233	*
234	* @returns Micro architecture.
235	* @param enmVendor The CPU vendor.
236	* @param bFamily The CPU family.
237	* @param bModel The CPU model.
238	* @param bStepping The CPU stepping.
239	*/
240	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
241	uint8_t bModel, uint8_t bStepping)
242	{
243	if (enmVendor == CPUMCPUVENDOR_AMD)
244	{
245	switch (bFamily)
246	{
247	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
248	case 0x03: return kCpumMicroarch_AMD_Am386;
249	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
250	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
251	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
252	case 0x06:
253	switch (bModel)
254	{
255	case 0: return kCpumMicroarch_AMD_K7_Palomino;
256	case 1: return kCpumMicroarch_AMD_K7_Palomino;
257	case 2: return kCpumMicroarch_AMD_K7_Palomino;
258	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
259	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
260	case 6: return kCpumMicroarch_AMD_K7_Palomino;
261	case 7: return kCpumMicroarch_AMD_K7_Morgan;
262	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
263	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
264	}
265	return kCpumMicroarch_AMD_K7_Unknown;
266	case 0x0f:
267	/*
268	* This family is a friggin mess. Trying my best to make some
269	* sense out of it. Too much happened in the 0x0f family to
270	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
271	*
272	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
273	* cpu-world.com, and other places:
274	* - 130nm:
275	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
276	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
277	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
278	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
279	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
280	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
281	* - 90nm:
282	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
283	* - Oakville: 10FC0/DH-D0.
284	* - Georgetown: 10FC0/DH-D0.
285	* - Sonora: 10FC0/DH-D0.
286	* - Venus: 20F71/SH-E4
287	* - Troy: 20F51/SH-E4
288	* - Athens: 20F51/SH-E4
289	* - San Diego: 20F71/SH-E4.
290	* - Lancaster: 20F42/SH-E5
291	* - Newark: 20F42/SH-E5.
292	* - Albany: 20FC2/DH-E6.
293	* - Roma: 20FC2/DH-E6.
294	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
295	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
296	* - 90nm introducing Dual core:
297	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
298	* - Italy: 20F10/JH-E1, 20F12/JH-E6
299	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
300	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
301	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
302	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
303	* - Santa Ana: 40F32/JH-F2, /-F3
304	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
305	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
306	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
307	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
308	* - Keene: 40FC2/DH-F2.
309	* - Richmond: 40FC2/DH-F2
310	* - Taylor: 40F82/BH-F2
311	* - Trinidad: 40F82/BH-F2
312	*
313	* - 65nm:
314	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
315	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
316	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
317	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
318	* - Sherman: /-G1, 70FC2/DH-G2.
319	* - Huron: 70FF2/DH-G2.
320	*/
321	if (bModel < 0x10)
322	return kCpumMicroarch_AMD_K8_130nm;
323	if (bModel >= 0x60 && bModel < 0x80)
324	return kCpumMicroarch_AMD_K8_65nm;
325	if (bModel >= 0x40)
326	return kCpumMicroarch_AMD_K8_90nm_AMDV;
327	switch (bModel)
328	{
329	case 0x21:
330	case 0x23:
331	case 0x2b:
332	case 0x2f:
333	case 0x37:
334	case 0x3f:
335	return kCpumMicroarch_AMD_K8_90nm_DualCore;
336	}
337	return kCpumMicroarch_AMD_K8_90nm;
338	case 0x10:
339	return kCpumMicroarch_AMD_K10;
340	case 0x11:
341	return kCpumMicroarch_AMD_K10_Lion;
342	case 0x12:
343	return kCpumMicroarch_AMD_K10_Llano;
344	case 0x14:
345	return kCpumMicroarch_AMD_Bobcat;
346	case 0x15:
347	switch (bModel)
348	{
349	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
350	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
351	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
352	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
353	case 0x11: /* ?? */
354	case 0x12: /* ?? */
355	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
356	}
357	return kCpumMicroarch_AMD_15h_Unknown;
358	case 0x16:
359	return kCpumMicroarch_AMD_Jaguar;
360	case 0x17:
361	return kCpumMicroarch_AMD_Zen_Ryzen;
362	}
363	return kCpumMicroarch_AMD_Unknown;
364	}
365
366	if (enmVendor == CPUMCPUVENDOR_INTEL)
367	{
368	switch (bFamily)
369	{
370	case 3:
371	return kCpumMicroarch_Intel_80386;
372	case 4:
373	return kCpumMicroarch_Intel_80486;
374	case 5:
375	return kCpumMicroarch_Intel_P5;
376	case 6:
377	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
378	{
379	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
380	if (enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake)
381	{
382	if (bStepping >= 0xa && bStepping <= 0xc)
383	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
384	else if (bStepping >= 0xc)
385	enmMicroArch = kCpumMicroarch_Intel_Core7_WhiskeyLake;
386	}
387	else if ( enmMicroArch == kCpumMicroarch_Intel_Core7_Skylake
388	&& bModel == 0x55
389	&& bStepping >= 5)
390	enmMicroArch = kCpumMicroarch_Intel_Core7_CascadeLake;
391	return enmMicroArch;
392	}
393	return kCpumMicroarch_Intel_Atom_Unknown;
394	case 15:
395	switch (bModel)
396	{
397	case 0: return kCpumMicroarch_Intel_NB_Willamette;
398	case 1: return kCpumMicroarch_Intel_NB_Willamette;
399	case 2: return kCpumMicroarch_Intel_NB_Northwood;
400	case 3: return kCpumMicroarch_Intel_NB_Prescott;
401	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
402	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
403	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
404	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
405	default: return kCpumMicroarch_Intel_NB_Unknown;
406	}
407	break;
408	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
409	case 0:
410	return kCpumMicroarch_Intel_8086;
411	case 1:
412	return kCpumMicroarch_Intel_80186;
413	case 2:
414	return kCpumMicroarch_Intel_80286;
415	}
416	return kCpumMicroarch_Intel_Unknown;
417	}
418
419	if (enmVendor == CPUMCPUVENDOR_VIA)
420	{
421	switch (bFamily)
422	{
423	case 5:
424	switch (bModel)
425	{
426	case 1: return kCpumMicroarch_Centaur_C6;
427	case 4: return kCpumMicroarch_Centaur_C6;
428	case 8: return kCpumMicroarch_Centaur_C2;
429	case 9: return kCpumMicroarch_Centaur_C3;
430	}
431	break;
432
433	case 6:
434	switch (bModel)
435	{
436	case 5: return kCpumMicroarch_VIA_C3_M2;
437	case 6: return kCpumMicroarch_VIA_C3_C5A;
438	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
439	case 8: return kCpumMicroarch_VIA_C3_C5N;
440	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
441	case 10: return kCpumMicroarch_VIA_C7_C5J;
442	case 15: return kCpumMicroarch_VIA_Isaiah;
443	}
444	break;
445	}
446	return kCpumMicroarch_VIA_Unknown;
447	}
448
449	if (enmVendor == CPUMCPUVENDOR_SHANGHAI)
450	{
451	switch (bFamily)
452	{
453	case 6:
454	case 7:
455	return kCpumMicroarch_Shanghai_Wudaokou;
456	default:
457	break;
458	}
459	return kCpumMicroarch_Shanghai_Unknown;
460	}
461
462	if (enmVendor == CPUMCPUVENDOR_CYRIX)
463	{
464	switch (bFamily)
465	{
466	case 4:
467	switch (bModel)
468	{
469	case 9: return kCpumMicroarch_Cyrix_5x86;
470	}
471	break;
472
473	case 5:
474	switch (bModel)
475	{
476	case 2: return kCpumMicroarch_Cyrix_M1;
477	case 4: return kCpumMicroarch_Cyrix_MediaGX;
478	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
479	}
480	break;
481
482	case 6:
483	switch (bModel)
484	{
485	case 0: return kCpumMicroarch_Cyrix_M2;
486	}
487	break;
488
489	}
490	return kCpumMicroarch_Cyrix_Unknown;
491	}
492
493	if (enmVendor == CPUMCPUVENDOR_HYGON)
494	{
495	switch (bFamily)
496	{
497	case 0x18:
498	return kCpumMicroarch_Hygon_Dhyana;
499	default:
500	break;
501	}
502	return kCpumMicroarch_Hygon_Unknown;
503	}
504
505	return kCpumMicroarch_Unknown;
506	}
507
508
509	/**
510	* Translates a microarchitecture enum value to the corresponding string
511	* constant.
512	*
513	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
514	* NULL if the value is invalid.
515	*
516	* @param enmMicroarch The enum value to convert.
517	*/
518	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
519	{
520	switch (enmMicroarch)
521	{
522	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
523	CASE_RET_STR(kCpumMicroarch_Intel_8086);
524	CASE_RET_STR(kCpumMicroarch_Intel_80186);
525	CASE_RET_STR(kCpumMicroarch_Intel_80286);
526	CASE_RET_STR(kCpumMicroarch_Intel_80386);
527	CASE_RET_STR(kCpumMicroarch_Intel_80486);
528	CASE_RET_STR(kCpumMicroarch_Intel_P5);
529
530	CASE_RET_STR(kCpumMicroarch_Intel_P6);
531	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
532	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
533
534	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
535	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
536	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
537
538	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
539	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
540
541	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
542	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
543	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
544	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
545	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
546	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
547	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
548	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
549	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
550	CASE_RET_STR(kCpumMicroarch_Intel_Core7_WhiskeyLake);
551	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CascadeLake);
552	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
553	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CometLake);
554	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
555	CASE_RET_STR(kCpumMicroarch_Intel_Core7_RocketLake);
556	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
557	CASE_RET_STR(kCpumMicroarch_Intel_Core7_AlderLake);
558	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SapphireRapids);
559
560	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
561	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
562	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
563	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
564	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
565	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
566	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
567	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
568
569	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
570	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
571	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
572	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
573	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
574
575	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
576	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
577	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
578	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
579	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
580	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
581	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
582
583	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
584
585	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
586	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
587	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
588	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
589	CASE_RET_STR(kCpumMicroarch_AMD_K5);
590	CASE_RET_STR(kCpumMicroarch_AMD_K6);
591
592	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
593	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
594	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
595	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
596	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
597	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
598	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
599
600	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
601	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
602	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
603	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
604	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
605
606	CASE_RET_STR(kCpumMicroarch_AMD_K10);
607	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
608	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
609	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
610	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
611
612	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
613	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
614	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
615	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
616	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
617
618	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
619
620	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
621
622	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
623
624	CASE_RET_STR(kCpumMicroarch_Hygon_Dhyana);
625	CASE_RET_STR(kCpumMicroarch_Hygon_Unknown);
626
627	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
628	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
629	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
630	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
631	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
632	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
633	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
634	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
635	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
636	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
637	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
638	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
639	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
640
641	CASE_RET_STR(kCpumMicroarch_Shanghai_Wudaokou);
642	CASE_RET_STR(kCpumMicroarch_Shanghai_Unknown);
643
644	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
645	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
646	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
647	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
648	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
649	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
650
651	CASE_RET_STR(kCpumMicroarch_NEC_V20);
652	CASE_RET_STR(kCpumMicroarch_NEC_V30);
653
654	CASE_RET_STR(kCpumMicroarch_Unknown);
655
656	#undef CASE_RET_STR
657	case kCpumMicroarch_Invalid:
658	case kCpumMicroarch_Intel_End:
659	case kCpumMicroarch_Intel_Core2_End:
660	case kCpumMicroarch_Intel_Core7_End:
661	case kCpumMicroarch_Intel_Atom_End:
662	case kCpumMicroarch_Intel_P6_Core_Atom_End:
663	case kCpumMicroarch_Intel_Phi_End:
664	case kCpumMicroarch_Intel_NB_End:
665	case kCpumMicroarch_AMD_K7_End:
666	case kCpumMicroarch_AMD_K8_End:
667	case kCpumMicroarch_AMD_15h_End:
668	case kCpumMicroarch_AMD_16h_End:
669	case kCpumMicroarch_AMD_Zen_End:
670	case kCpumMicroarch_AMD_End:
671	case kCpumMicroarch_Hygon_End:
672	case kCpumMicroarch_VIA_End:
673	case kCpumMicroarch_Shanghai_End:
674	case kCpumMicroarch_Cyrix_End:
675	case kCpumMicroarch_NEC_End:
676	case kCpumMicroarch_32BitHack:
677	break;
678	/* no default! */
679	}
680
681	return NULL;
682	}
683
684
685	/**
686	* Determins the host CPU MXCSR mask.
687	*
688	* @returns MXCSR mask.
689	*/
690	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
691	{
692	if ( ASMHasCpuId()
693	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
694	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
695	{
696	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
697	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
698	RT_ZERO(*pState);
699	ASMFxSave(pState);
700	if (pState->MXCSR_MASK == 0)
701	return 0xffbf;
702	return pState->MXCSR_MASK;
703	}
704	return 0;
705	}
706
707
708	/**
709	* Gets a matching leaf in the CPUID leaf array.
710	*
711	* @returns Pointer to the matching leaf, or NULL if not found.
712	* @param paLeaves The CPUID leaves to search. This is sorted.
713	* @param cLeaves The number of leaves in the array.
714	* @param uLeaf The leaf to locate.
715	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
716	*/
717	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
718	{
719	/* Lazy bird does linear lookup here since this is only used for the
720	occational CPUID overrides. */
721	for (uint32_t i = 0; i < cLeaves; i++)
722	if ( paLeaves[i].uLeaf == uLeaf
723	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
724	return &paLeaves[i];
725	return NULL;
726	}
727
728
729	#ifndef IN_VBOX_CPU_REPORT
730	/**
731	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
732	*
733	* @returns true if found, false it not.
734	* @param paLeaves The CPUID leaves to search. This is sorted.
735	* @param cLeaves The number of leaves in the array.
736	* @param uLeaf The leaf to locate.
737	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
738	* @param pLegacy The legacy output leaf.
739	*/
740	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
741	PCPUMCPUID pLegacy)
742	{
743	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
744	if (pLeaf)
745	{
746	pLegacy->uEax = pLeaf->uEax;
747	pLegacy->uEbx = pLeaf->uEbx;
748	pLegacy->uEcx = pLeaf->uEcx;
749	pLegacy->uEdx = pLeaf->uEdx;
750	return true;
751	}
752	return false;
753	}
754	#endif /* IN_VBOX_CPU_REPORT */
755
756
757	/**
758	* Ensures that the CPUID leaf array can hold one more leaf.
759	*
760	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
761	* failure.
762	* @param pVM The cross context VM structure. If NULL, use
763	* the process heap, otherwise the VM's hyper heap.
764	* @param ppaLeaves Pointer to the variable holding the array pointer
765	* (input/output).
766	* @param cLeaves The current array size.
767	*
768	* @remarks This function will automatically update the R0 and RC pointers when
769	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
770	* be the corresponding VM's CPUID arrays (which is asserted).
771	*/
772	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
773	{
774	/*
775	* If pVM is not specified, we're on the regular heap and can waste a
776	* little space to speed things up.
777	*/
778	uint32_t cAllocated;
779	if (!pVM)
780	{
781	cAllocated = RT_ALIGN(cLeaves, 16);
782	if (cLeaves + 1 > cAllocated)
783	{
784	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
785	if (pvNew)
786	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
787	else
788	{
789	RTMemFree(*ppaLeaves);
790	*ppaLeaves = NULL;
791	}
792	}
793	}
794	/*
795	* Otherwise, we're on the hyper heap and are probably just inserting
796	* one or two leaves and should conserve space.
797	*/
798	else
799	{
800	#ifdef IN_VBOX_CPU_REPORT
801	AssertReleaseFailed();
802	#else
803	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
804	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
805
806	size_t cb = cLeaves * sizeof(**ppaLeaves);
807	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
808	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
809	if (RT_SUCCESS(rc))
810	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
811	else
812	{
813	*ppaLeaves = NULL;
814	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
815	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
816	}
817	#endif
818	}
819	return *ppaLeaves;
820	}
821
822
823	/**
824	* Append a CPUID leaf or sub-leaf.
825	*
826	* ASSUMES linear insertion order, so we'll won't need to do any searching or
827	* replace anything. Use cpumR3CpuIdInsert() for those cases.
828	*
829	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
830	* the caller need do no more work.
831	* @param ppaLeaves Pointer to the pointer to the array of sorted
832	* CPUID leaves and sub-leaves.
833	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
834	* @param uLeaf The leaf we're adding.
835	* @param uSubLeaf The sub-leaf number.
836	* @param fSubLeafMask The sub-leaf mask.
837	* @param uEax The EAX value.
838	* @param uEbx The EBX value.
839	* @param uEcx The ECX value.
840	* @param uEdx The EDX value.
841	* @param fFlags The flags.
842	*/
843	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
844	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
845	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
846	{
847	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
848	return VERR_NO_MEMORY;
849
850	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
851	Assert( *pcLeaves == 0
852	\|\| pNew[-1].uLeaf < uLeaf
853	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
854
855	pNew->uLeaf = uLeaf;
856	pNew->uSubLeaf = uSubLeaf;
857	pNew->fSubLeafMask = fSubLeafMask;
858	pNew->uEax = uEax;
859	pNew->uEbx = uEbx;
860	pNew->uEcx = uEcx;
861	pNew->uEdx = uEdx;
862	pNew->fFlags = fFlags;
863
864	*pcLeaves += 1;
865	return VINF_SUCCESS;
866	}
867
868
869	/**
870	* Checks that we've updated the CPUID leaves array correctly.
871	*
872	* This is a no-op in non-strict builds.
873	*
874	* @param paLeaves The leaves array.
875	* @param cLeaves The number of leaves.
876	*/
877	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
878	{
879	#ifdef VBOX_STRICT
880	for (uint32_t i = 1; i < cLeaves; i++)
881	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
882	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
883	else
884	{
885	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
886	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
887	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
888	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
889	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
890	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
891	}
892	#else
893	NOREF(paLeaves);
894	NOREF(cLeaves);
895	#endif
896	}
897
898
899	/**
900	* Inserts a CPU ID leaf, replacing any existing ones.
901	*
902	* When inserting a simple leaf where we already got a series of sub-leaves with
903	* the same leaf number (eax), the simple leaf will replace the whole series.
904	*
905	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
906	* host-context heap and has only been allocated/reallocated by the
907	* cpumR3CpuIdEnsureSpace function.
908	*
909	* @returns VBox status code.
910	* @param pVM The cross context VM structure. If NULL, use
911	* the process heap, otherwise the VM's hyper heap.
912	* @param ppaLeaves Pointer to the pointer to the array of sorted
913	* CPUID leaves and sub-leaves. Must be NULL if using
914	* the hyper heap.
915	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
916	* be NULL if using the hyper heap.
917	* @param pNewLeaf Pointer to the data of the new leaf we're about to
918	* insert.
919	*/
920	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
921	{
922	/*
923	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
924	*/
925	if (pVM)
926	{
927	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
928	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
929
930	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
931	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
932	}
933
934	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
935	uint32_t cLeaves = *pcLeaves;
936
937	/*
938	* Validate the new leaf a little.
939	*/
940	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
941	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
942	VERR_INVALID_FLAGS);
943	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
944	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
945	VERR_INVALID_PARAMETER);
946	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
947	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
948	VERR_INVALID_PARAMETER);
949	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
950	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
951	VERR_INVALID_PARAMETER);
952
953	/*
954	* Find insertion point. The lazy bird uses the same excuse as in
955	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
956	*/
957	uint32_t i;
958	if ( cLeaves > 0
959	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
960	{
961	/* Add at end. */
962	i = cLeaves;
963	}
964	else if ( cLeaves > 0
965	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
966	{
967	/* Either replacing the last leaf or dealing with sub-leaves. Spool
968	back to the first sub-leaf to pretend we did the linear search. */
969	i = cLeaves - 1;
970	while ( i > 0
971	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
972	i--;
973	}
974	else
975	{
976	/* Linear search from the start. */
977	i = 0;
978	while ( i < cLeaves
979	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
980	i++;
981	}
982	if ( i < cLeaves
983	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
984	{
985	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
986	{
987	/*
988	* The sub-leaf mask differs, replace all existing leaves with the
989	* same leaf number.
990	*/
991	uint32_t c = 1;
992	while ( i + c < cLeaves
993	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
994	c++;
995	if (c > 1 && i + c < cLeaves)
996	{
997	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
998	*pcLeaves = cLeaves -= c - 1;
999	}
1000
1001	paLeaves[i] = *pNewLeaf;
1002	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1003	return VINF_SUCCESS;
1004	}
1005
1006	/* Find sub-leaf insertion point. */
1007	while ( i < cLeaves
1008	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
1009	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
1010	i++;
1011
1012	/*
1013	* If we've got an exactly matching leaf, replace it.
1014	*/
1015	if ( i < cLeaves
1016	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
1017	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
1018	{
1019	paLeaves[i] = *pNewLeaf;
1020	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1021	return VINF_SUCCESS;
1022	}
1023	}
1024
1025	/*
1026	* Adding a new leaf at 'i'.
1027	*/
1028	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
1029	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
1030	if (!paLeaves)
1031	return VERR_NO_MEMORY;
1032
1033	if (i < cLeaves)
1034	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
1035	*pcLeaves += 1;
1036	paLeaves[i] = *pNewLeaf;
1037
1038	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1039	return VINF_SUCCESS;
1040	}
1041
1042
1043	#ifndef IN_VBOX_CPU_REPORT
1044	/**
1045	* Removes a range of CPUID leaves.
1046	*
1047	* This will not reallocate the array.
1048	*
1049	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1050	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1051	* @param uFirst The first leaf.
1052	* @param uLast The last leaf.
1053	*/
1054	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1055	{
1056	uint32_t cLeaves = *pcLeaves;
1057
1058	Assert(uFirst <= uLast);
1059
1060	/*
1061	* Find the first one.
1062	*/
1063	uint32_t iFirst = 0;
1064	while ( iFirst < cLeaves
1065	&& paLeaves[iFirst].uLeaf < uFirst)
1066	iFirst++;
1067
1068	/*
1069	* Find the end (last + 1).
1070	*/
1071	uint32_t iEnd = iFirst;
1072	while ( iEnd < cLeaves
1073	&& paLeaves[iEnd].uLeaf <= uLast)
1074	iEnd++;
1075
1076	/*
1077	* Adjust the array if anything needs removing.
1078	*/
1079	if (iFirst < iEnd)
1080	{
1081	if (iEnd < cLeaves)
1082	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1083	*pcLeaves = cLeaves -= (iEnd - iFirst);
1084	}
1085
1086	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1087	}
1088	#endif /* IN_VBOX_CPU_REPORT */
1089
1090
1091	/**
1092	* Checks if ECX make a difference when reading a given CPUID leaf.
1093	*
1094	* @returns @c true if it does, @c false if it doesn't.
1095	* @param uLeaf The leaf we're reading.
1096	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1097	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1098	* final sub-leaf (for leaf 0xb only).
1099	*/
1100	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1101	{
1102	*pfFinalEcxUnchanged = false;
1103
1104	uint32_t auCur[4];
1105	uint32_t auPrev[4];
1106	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1107
1108	/* Look for sub-leaves. */
1109	uint32_t uSubLeaf = 1;
1110	for (;;)
1111	{
1112	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1113	if (memcmp(auCur, auPrev, sizeof(auCur)))
1114	break;
1115
1116	/* Advance / give up. */
1117	uSubLeaf++;
1118	if (uSubLeaf >= 64)
1119	{
1120	*pcSubLeaves = 1;
1121	return false;
1122	}
1123	}
1124
1125	/* Count sub-leaves. */
1126	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1127	uint32_t cRepeats = 0;
1128	uSubLeaf = 0;
1129	for (;;)
1130	{
1131	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1132
1133	/* Figuring out when to stop isn't entirely straight forward as we need
1134	to cover undocumented behavior up to a point and implementation shortcuts. */
1135
1136	/* 1. Look for more than 4 repeating value sets. */
1137	if ( auCur[0] == auPrev[0]
1138	&& auCur[1] == auPrev[1]
1139	&& ( auCur[2] == auPrev[2]
1140	\|\| ( auCur[2] == uSubLeaf
1141	&& auPrev[2] == uSubLeaf - 1) )
1142	&& auCur[3] == auPrev[3])
1143	{
1144	if ( uLeaf != 0xd
1145	\|\| uSubLeaf >= 64
1146	\|\| ( auCur[0] == 0
1147	&& auCur[1] == 0
1148	&& auCur[2] == 0
1149	&& auCur[3] == 0
1150	&& auPrev[2] == 0) )
1151	cRepeats++;
1152	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1153	break;
1154	}
1155	else
1156	cRepeats = 0;
1157
1158	/* 2. Look for zero values. */
1159	if ( auCur[0] == 0
1160	&& auCur[1] == 0
1161	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1162	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1163	&& uSubLeaf >= cMinLeaves)
1164	{
1165	cRepeats = 0;
1166	break;
1167	}
1168
1169	/* 3. Leaf 0xb level type 0 check. */
1170	if ( uLeaf == 0xb
1171	&& (auCur[2] & 0xff00) == 0
1172	&& (auPrev[2] & 0xff00) == 0)
1173	{
1174	cRepeats = 0;
1175	break;
1176	}
1177
1178	/* 99. Give up. */
1179	if (uSubLeaf >= 128)
1180	{
1181	#ifndef IN_VBOX_CPU_REPORT
1182	/* Ok, limit it according to the documentation if possible just to
1183	avoid annoying users with these detection issues. */
1184	uint32_t cDocLimit = UINT32_MAX;
1185	if (uLeaf == 0x4)
1186	cDocLimit = 4;
1187	else if (uLeaf == 0x7)
1188	cDocLimit = 1;
1189	else if (uLeaf == 0xd)
1190	cDocLimit = 63;
1191	else if (uLeaf == 0xf)
1192	cDocLimit = 2;
1193	if (cDocLimit != UINT32_MAX)
1194	{
1195	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1196	*pcSubLeaves = cDocLimit + 3;
1197	return true;
1198	}
1199	#endif
1200	*pcSubLeaves = UINT32_MAX;
1201	return true;
1202	}
1203
1204	/* Advance. */
1205	uSubLeaf++;
1206	memcpy(auPrev, auCur, sizeof(auCur));
1207	}
1208
1209	/* Standard exit. */
1210	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1211	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1212	if (*pcSubLeaves == 0)
1213	*pcSubLeaves = 1;
1214	return true;
1215	}
1216
1217
1218	/**
1219	* Gets a CPU ID leaf.
1220	*
1221	* @returns VBox status code.
1222	* @param pVM The cross context VM structure.
1223	* @param pLeaf Where to store the found leaf.
1224	* @param uLeaf The leaf to locate.
1225	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1226	*/
1227	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1228	{
1229	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1230	uLeaf, uSubLeaf);
1231	if (pcLeaf)
1232	{
1233	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1234	return VINF_SUCCESS;
1235	}
1236
1237	return VERR_NOT_FOUND;
1238	}
1239
1240
1241	/**
1242	* Inserts a CPU ID leaf, replacing any existing ones.
1243	*
1244	* @returns VBox status code.
1245	* @param pVM The cross context VM structure.
1246	* @param pNewLeaf Pointer to the leaf being inserted.
1247	*/
1248	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1249	{
1250	/*
1251	* Validate parameters.
1252	*/
1253	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1254	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1255
1256	/*
1257	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1258	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1259	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1260	*/
1261	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1262	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1263	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1264	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1265	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1266	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1267	{
1268	return VERR_NOT_SUPPORTED;
1269	}
1270
1271	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1272	}
1273
1274	/**
1275	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1276	*
1277	* @returns VBox status code.
1278	* @param ppaLeaves Where to return the array pointer on success.
1279	* Use RTMemFree to release.
1280	* @param pcLeaves Where to return the size of the array on
1281	* success.
1282	*/
1283	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1284	{
1285	*ppaLeaves = NULL;
1286	*pcLeaves = 0;
1287
1288	/*
1289	* Try out various candidates. This must be sorted!
1290	*/
1291	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1292	{
1293	{ UINT32_C(0x00000000), false },
1294	{ UINT32_C(0x10000000), false },
1295	{ UINT32_C(0x20000000), false },
1296	{ UINT32_C(0x30000000), false },
1297	{ UINT32_C(0x40000000), false },
1298	{ UINT32_C(0x50000000), false },
1299	{ UINT32_C(0x60000000), false },
1300	{ UINT32_C(0x70000000), false },
1301	{ UINT32_C(0x80000000), false },
1302	{ UINT32_C(0x80860000), false },
1303	{ UINT32_C(0x8ffffffe), true },
1304	{ UINT32_C(0x8fffffff), true },
1305	{ UINT32_C(0x90000000), false },
1306	{ UINT32_C(0xa0000000), false },
1307	{ UINT32_C(0xb0000000), false },
1308	{ UINT32_C(0xc0000000), false },
1309	{ UINT32_C(0xd0000000), false },
1310	{ UINT32_C(0xe0000000), false },
1311	{ UINT32_C(0xf0000000), false },
1312	};
1313
1314	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1315	{
1316	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1317	uint32_t uEax, uEbx, uEcx, uEdx;
1318	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1319
1320	/*
1321	* Does EAX look like a typical leaf count value?
1322	*/
1323	if ( uEax > uLeaf
1324	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1325	{
1326	/* Yes, dump them. */
1327	uint32_t cLeaves = uEax - uLeaf + 1;
1328	while (cLeaves-- > 0)
1329	{
1330	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1331
1332	uint32_t fFlags = 0;
1333
1334	/* There are currently three known leaves containing an APIC ID
1335	that needs EMT specific attention */
1336	if (uLeaf == 1)
1337	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1338	else if (uLeaf == 0xb && uEcx != 0)
1339	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1340	else if ( uLeaf == UINT32_C(0x8000001e)
1341	&& ( uEax
1342	\|\| uEbx
1343	\|\| uEdx
1344	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1345	\|\| ASMIsHygonCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1346	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1347
1348	/* The APIC bit is per-VCpu and needs flagging. */
1349	if (uLeaf == 1)
1350	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1351	else if ( uLeaf == UINT32_C(0x80000001)
1352	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1353	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1354	\|\| ASMIsHygonCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1355	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1356
1357	/* Check three times here to reduce the chance of CPU migration
1358	resulting in false positives with things like the APIC ID. */
1359	uint32_t cSubLeaves;
1360	bool fFinalEcxUnchanged;
1361	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1362	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1363	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1364	{
1365	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1366	{
1367	/* This shouldn't happen. But in case it does, file all
1368	relevant details in the release log. */
1369	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1370	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1371	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1372	{
1373	uint32_t auTmp[4];
1374	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1375	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1376	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1377	}
1378	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1379	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1380	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1381	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1382	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1383	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1384	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1385	}
1386
1387	if (fFinalEcxUnchanged)
1388	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1389
1390	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1391	{
1392	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1393	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1394	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1395	if (RT_FAILURE(rc))
1396	return rc;
1397	}
1398	}
1399	else
1400	{
1401	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1402	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1403	if (RT_FAILURE(rc))
1404	return rc;
1405	}
1406
1407	/* next */
1408	uLeaf++;
1409	}
1410	}
1411	/*
1412	* Special CPUIDs needs special handling as they don't follow the
1413	* leaf count principle used above.
1414	*/
1415	else if (s_aCandidates[iOuter].fSpecial)
1416	{
1417	bool fKeep = false;
1418	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1419	fKeep = true;
1420	else if ( uLeaf == 0x8fffffff
1421	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1422	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1423	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1424	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1425	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1426	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1427	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1428	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1429	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1430	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1431	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1432	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1433	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1434	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1435	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1436	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1437	fKeep = true;
1438	if (fKeep)
1439	{
1440	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1441	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1442	if (RT_FAILURE(rc))
1443	return rc;
1444	}
1445	}
1446	}
1447
1448	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1449	return VINF_SUCCESS;
1450	}
1451
1452
1453	/**
1454	* Determines the method the CPU uses to handle unknown CPUID leaves.
1455	*
1456	* @returns VBox status code.
1457	* @param penmUnknownMethod Where to return the method.
1458	* @param pDefUnknown Where to return default unknown values. This
1459	* will be set, even if the resulting method
1460	* doesn't actually needs it.
1461	*/
1462	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1463	{
1464	uint32_t uLastStd = ASMCpuId_EAX(0);
1465	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1466	if (!ASMIsValidExtRange(uLastExt))
1467	uLastExt = 0x80000000;
1468
1469	uint32_t auChecks[] =
1470	{
1471	uLastStd + 1,
1472	uLastStd + 5,
1473	uLastStd + 8,
1474	uLastStd + 32,
1475	uLastStd + 251,
1476	uLastExt + 1,
1477	uLastExt + 8,
1478	uLastExt + 15,
1479	uLastExt + 63,
1480	uLastExt + 255,
1481	0x7fbbffcc,
1482	0x833f7872,
1483	0xefff2353,
1484	0x35779456,
1485	0x1ef6d33e,
1486	};
1487
1488	static const uint32_t s_auValues[] =
1489	{
1490	0xa95d2156,
1491	0x00000001,
1492	0x00000002,
1493	0x00000008,
1494	0x00000000,
1495	0x55773399,
1496	0x93401769,
1497	0x12039587,
1498	};
1499
1500	/*
1501	* Simple method, all zeros.
1502	*/
1503	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1504	pDefUnknown->uEax = 0;
1505	pDefUnknown->uEbx = 0;
1506	pDefUnknown->uEcx = 0;
1507	pDefUnknown->uEdx = 0;
1508
1509	/*
1510	* Intel has been observed returning the last standard leaf.
1511	*/
1512	uint32_t auLast[4];
1513	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1514
1515	uint32_t cChecks = RT_ELEMENTS(auChecks);
1516	while (cChecks > 0)
1517	{
1518	uint32_t auCur[4];
1519	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1520	if (memcmp(auCur, auLast, sizeof(auCur)))
1521	break;
1522	cChecks--;
1523	}
1524	if (cChecks == 0)
1525	{
1526	/* Now, what happens when the input changes? Esp. ECX. */
1527	uint32_t cTotal = 0;
1528	uint32_t cSame = 0;
1529	uint32_t cLastWithEcx = 0;
1530	uint32_t cNeither = 0;
1531	uint32_t cValues = RT_ELEMENTS(s_auValues);
1532	while (cValues > 0)
1533	{
1534	uint32_t uValue = s_auValues[cValues - 1];
1535	uint32_t auLastWithEcx[4];
1536	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1537	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1538
1539	cChecks = RT_ELEMENTS(auChecks);
1540	while (cChecks > 0)
1541	{
1542	uint32_t auCur[4];
1543	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1544	if (!memcmp(auCur, auLast, sizeof(auCur)))
1545	{
1546	cSame++;
1547	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1548	cLastWithEcx++;
1549	}
1550	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1551	cLastWithEcx++;
1552	else
1553	cNeither++;
1554	cTotal++;
1555	cChecks--;
1556	}
1557	cValues--;
1558	}
1559
1560	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1561	if (cSame == cTotal)
1562	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1563	else if (cLastWithEcx == cTotal)
1564	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1565	else
1566	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1567	pDefUnknown->uEax = auLast[0];
1568	pDefUnknown->uEbx = auLast[1];
1569	pDefUnknown->uEcx = auLast[2];
1570	pDefUnknown->uEdx = auLast[3];
1571	return VINF_SUCCESS;
1572	}
1573
1574	/*
1575	* Unchanged register values?
1576	*/
1577	cChecks = RT_ELEMENTS(auChecks);
1578	while (cChecks > 0)
1579	{
1580	uint32_t const uLeaf = auChecks[cChecks - 1];
1581	uint32_t cValues = RT_ELEMENTS(s_auValues);
1582	while (cValues > 0)
1583	{
1584	uint32_t uValue = s_auValues[cValues - 1];
1585	uint32_t auCur[4];
1586	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1587	if ( auCur[0] != uLeaf
1588	\|\| auCur[1] != uValue
1589	\|\| auCur[2] != uValue
1590	\|\| auCur[3] != uValue)
1591	break;
1592	cValues--;
1593	}
1594	if (cValues != 0)
1595	break;
1596	cChecks--;
1597	}
1598	if (cChecks == 0)
1599	{
1600	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1601	return VINF_SUCCESS;
1602	}
1603
1604	/*
1605	* Just go with the simple method.
1606	*/
1607	return VINF_SUCCESS;
1608	}
1609
1610
1611	/**
1612	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1613	*
1614	* @returns Read only name string.
1615	* @param enmUnknownMethod The method to translate.
1616	*/
1617	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1618	{
1619	switch (enmUnknownMethod)
1620	{
1621	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1622	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1623	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1624	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1625
1626	case CPUMUNKNOWNCPUID_INVALID:
1627	case CPUMUNKNOWNCPUID_END:
1628	case CPUMUNKNOWNCPUID_32BIT_HACK:
1629	break;
1630	}
1631	return "Invalid-unknown-CPUID-method";
1632	}
1633
1634
1635	/**
1636	* Detect the CPU vendor give n the
1637	*
1638	* @returns The vendor.
1639	* @param uEAX EAX from CPUID(0).
1640	* @param uEBX EBX from CPUID(0).
1641	* @param uECX ECX from CPUID(0).
1642	* @param uEDX EDX from CPUID(0).
1643	*/
1644	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1645	{
1646	if (ASMIsValidStdRange(uEAX))
1647	{
1648	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1649	return CPUMCPUVENDOR_AMD;
1650
1651	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1652	return CPUMCPUVENDOR_INTEL;
1653
1654	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1655	return CPUMCPUVENDOR_VIA;
1656
1657	if (ASMIsShanghaiCpuEx(uEBX, uECX, uEDX))
1658	return CPUMCPUVENDOR_SHANGHAI;
1659
1660	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1661	&& uECX == UINT32_C(0x64616574)
1662	&& uEDX == UINT32_C(0x736E4978))
1663	return CPUMCPUVENDOR_CYRIX;
1664
1665	if (ASMIsHygonCpuEx(uEBX, uECX, uEDX))
1666	return CPUMCPUVENDOR_HYGON;
1667
1668	/* "Geode by NSC", example: family 5, model 9. */
1669
1670	/** @todo detect the other buggers... */
1671	}
1672
1673	return CPUMCPUVENDOR_UNKNOWN;
1674	}
1675
1676
1677	/**
1678	* Translates a CPU vendor enum value into the corresponding string constant.
1679	*
1680	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1681	* value name. This can be useful when generating code.
1682	*
1683	* @returns Read only name string.
1684	* @param enmVendor The CPU vendor value.
1685	*/
1686	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1687	{
1688	switch (enmVendor)
1689	{
1690	case CPUMCPUVENDOR_INTEL: return "INTEL";
1691	case CPUMCPUVENDOR_AMD: return "AMD";
1692	case CPUMCPUVENDOR_VIA: return "VIA";
1693	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1694	case CPUMCPUVENDOR_SHANGHAI: return "SHANGHAI";
1695	case CPUMCPUVENDOR_HYGON: return "HYGON";
1696	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1697
1698	case CPUMCPUVENDOR_INVALID:
1699	case CPUMCPUVENDOR_32BIT_HACK:
1700	break;
1701	}
1702	return "Invalid-cpu-vendor";
1703	}
1704
1705
1706	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1707	{
1708	/* Could do binary search, doing linear now because I'm lazy. */
1709	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1710	while (cLeaves-- > 0)
1711	{
1712	if (pLeaf->uLeaf == uLeaf)
1713	return pLeaf;
1714	pLeaf++;
1715	}
1716	return NULL;
1717	}
1718
1719
1720	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1721	{
1722	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1723	if ( !pLeaf
1724	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1725	return pLeaf;
1726
1727	/* Linear sub-leaf search. Lazy as usual. */
1728	cLeaves -= pLeaf - paLeaves;
1729	while ( cLeaves-- > 0
1730	&& pLeaf->uLeaf == uLeaf)
1731	{
1732	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1733	return pLeaf;
1734	pLeaf++;
1735	}
1736
1737	return NULL;
1738	}
1739
1740
1741	static void cpumR3ExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURES pFeatures)
1742	{
1743	Assert(pVmxMsrs);
1744	Assert(pFeatures);
1745	Assert(pFeatures->fVmx);
1746
1747	/* Basic information. */
1748	{
1749	uint64_t const u64Basic = pVmxMsrs->u64Basic;
1750	pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1751	}
1752
1753	/* Pin-based VM-execution controls. */
1754	{
1755	uint32_t const fPinCtls = pVmxMsrs->PinCtls.n.allowed1;
1756	pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1757	pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1758	pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1759	pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1760	pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1761	}
1762
1763	/* Processor-based VM-execution controls. */
1764	{
1765	uint32_t const fProcCtls = pVmxMsrs->ProcCtls.n.allowed1;
1766	pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1767	pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1768	pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1769	pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1770	pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1771	pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1772	pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1773	pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1774	pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1775	pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1776	pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1777	pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1778	pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1779	pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1780	pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1781	pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1782	pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1783	pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1784	pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1785	pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1786	pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1787	}
1788
1789	/* Secondary processor-based VM-execution controls. */
1790	{
1791	uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1792	pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1793	pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1794	pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1795	pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1796	pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1797	pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1798	pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1799	pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1800	pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1801	pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1802	pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1803	pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1804	pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1805	pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1806	pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1807	pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1808	pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1809	pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_VE);
1810	pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1811	pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1812	}
1813
1814	/* VM-exit controls. */
1815	{
1816	uint32_t const fExitCtls = pVmxMsrs->ExitCtls.n.allowed1;
1817	pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1818	pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1819	pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1820	pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1821	pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1822	pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1823	pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1824	pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1825	}
1826
1827	/* VM-entry controls. */
1828	{
1829	uint32_t const fEntryCtls = pVmxMsrs->EntryCtls.n.allowed1;
1830	pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1831	pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1832	pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1833	pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1834	}
1835
1836	/* Miscellaneous data. */
1837	{
1838	uint32_t const fMiscData = pVmxMsrs->u64Misc;
1839	pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1840	pFeatures->fVmxIntelPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1841	pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1842	pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1843	}
1844	}
1845
1846
1847	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures)
1848	{
1849	Assert(pMsrs);
1850	RT_ZERO(*pFeatures);
1851	if (cLeaves >= 2)
1852	{
1853	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1854	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1855	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1856	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1857	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1858	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1859
1860	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1861	pStd0Leaf->uEbx,
1862	pStd0Leaf->uEcx,
1863	pStd0Leaf->uEdx);
1864	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1865	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1866	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1867	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1868	pFeatures->uFamily,
1869	pFeatures->uModel,
1870	pFeatures->uStepping);
1871
1872	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1873	if (pExtLeaf8)
1874	{
1875	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1876	pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1877	}
1878	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1879	{
1880	pFeatures->cMaxPhysAddrWidth = 36;
1881	pFeatures->cMaxLinearAddrWidth = 36;
1882	}
1883	else
1884	{
1885	pFeatures->cMaxPhysAddrWidth = 32;
1886	pFeatures->cMaxLinearAddrWidth = 32;
1887	}
1888
1889	/* Standard features. */
1890	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1891	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1892	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1893	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1894	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1895	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1896	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1897	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1898	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1899	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1900	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1901	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1902	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1903	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1904	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1905	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1906	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1907	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1908	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1909	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1910	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1911	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1912	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1913	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1914	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1915	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1916	if (pFeatures->fVmx)
1917	cpumR3ExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1918
1919	/* Structured extended features. */
1920	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1921	if (pSxfLeaf0)
1922	{
1923	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1924	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1925	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1926	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1927	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1928
1929	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1930	pFeatures->fIbrs = pFeatures->fIbpb;
1931	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1932	pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
1933	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1934	pFeatures->fMdsClear = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
1935	}
1936
1937	/* MWAIT/MONITOR leaf. */
1938	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1939	if (pMWaitLeaf)
1940	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1941	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1942
1943	/* Extended features. */
1944	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1945	if (pExtLeaf)
1946	{
1947	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1948	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1949	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1950	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1951	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1952	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1953	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1954	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1955	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1956	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1957	}
1958
1959	/* VMX (VMXON, VMCS region and related data structures) physical address width (depends on long-mode). */
1960	pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
1961
1962	if ( pExtLeaf
1963	&& ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1964	\|\| pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON))
1965	{
1966	/* AMD features. */
1967	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1968	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1969	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1970	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1971	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1972	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1973	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1974	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1975	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1976	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1977	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1978	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1979	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1980	if (pFeatures->fSvm)
1981	{
1982	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1983	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1984	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1985	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1986	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1987	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1988	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1989	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1990	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1991	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1992	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1993	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1994	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1995	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1996	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1997	pFeatures->fSvmGmet = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_GMET);
1998	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1999	}
2000	}
2001
2002	/*
2003	* Quirks.
2004	*/
2005	pFeatures->fLeakyFxSR = pExtLeaf
2006	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2007	&& ( ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
2008	&& pFeatures->uFamily >= 6 /* K7 and up */)
2009	\|\| pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON);
2010
2011	/*
2012	* Max extended (/FPU) state.
2013	*/
2014	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
2015	if (pFeatures->fXSaveRstor)
2016	{
2017	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
2018	if (pXStateLeaf0)
2019	{
2020	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
2021	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
2022	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
2023	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
2024	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
2025	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
2026	{
2027	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
2028
2029	/* (paranoia:) */
2030	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
2031	if ( pXStateLeaf1
2032	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
2033	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
2034	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
2035	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
2036	}
2037	else
2038	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
2039	pFeatures->fXSaveRstor = 0);
2040	}
2041	else
2042	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
2043	pFeatures->fXSaveRstor = 0);
2044	}
2045	}
2046	else
2047	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
2048	return VINF_SUCCESS;
2049	}
2050
2051
2052	/*
2053	*
2054	* Init related code.
2055	* Init related code.
2056	* Init related code.
2057	*
2058	*
2059	*/
2060	#ifndef IN_VBOX_CPU_REPORT
2061
2062
2063	/**
2064	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
2065	*
2066	* This ignores the fSubLeafMask.
2067	*
2068	* @returns Pointer to the matching leaf, or NULL if not found.
2069	* @param pCpum The CPUM instance data.
2070	* @param uLeaf The leaf to locate.
2071	* @param uSubLeaf The subleaf to locate.
2072	*/
2073	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
2074	{
2075	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
2076	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
2077	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
2078	if (iEnd)
2079	{
2080	uint32_t iBegin = 0;
2081	for (;;)
2082	{
2083	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
2084	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
2085	if (uNeedle < uCur)
2086	{
2087	if (i > iBegin)
2088	iEnd = i;
2089	else
2090	break;
2091	}
2092	else if (uNeedle > uCur)
2093	{
2094	if (i + 1 < iEnd)
2095	iBegin = i + 1;
2096	else
2097	break;
2098	}
2099	else
2100	return &paLeaves[i];
2101	}
2102	}
2103	return NULL;
2104	}
2105
2106
2107	/**
2108	* Loads MSR range overrides.
2109	*
2110	* This must be called before the MSR ranges are moved from the normal heap to
2111	* the hyper heap!
2112	*
2113	* @returns VBox status code (VMSetError called).
2114	* @param pVM The cross context VM structure.
2115	* @param pMsrNode The CFGM node with the MSR overrides.
2116	*/
2117	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
2118	{
2119	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2120	{
2121	/*
2122	* Assemble a valid MSR range.
2123	*/
2124	CPUMMSRRANGE MsrRange;
2125	MsrRange.offCpumCpu = 0;
2126	MsrRange.fReserved = 0;
2127
2128	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
2129	if (RT_FAILURE(rc))
2130	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
2131
2132	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
2133	if (RT_FAILURE(rc))
2134	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
2135	MsrRange.szName, rc);
2136
2137	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
2138	if (RT_FAILURE(rc))
2139	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
2140	MsrRange.szName, rc);
2141
2142	char szType[32];
2143	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
2144	if (RT_FAILURE(rc))
2145	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
2146	MsrRange.szName, rc);
2147	if (!RTStrICmp(szType, "FixedValue"))
2148	{
2149	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
2150	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
2151
2152	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
2153	if (RT_FAILURE(rc))
2154	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
2155	MsrRange.szName, rc);
2156
2157	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
2158	if (RT_FAILURE(rc))
2159	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
2160	MsrRange.szName, rc);
2161
2162	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
2163	if (RT_FAILURE(rc))
2164	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
2165	MsrRange.szName, rc);
2166	}
2167	else
2168	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
2169	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
2170
2171	/*
2172	* Insert the range into the table (replaces/splits/shrinks existing
2173	* MSR ranges).
2174	*/
2175	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
2176	&MsrRange);
2177	if (RT_FAILURE(rc))
2178	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
2179	}
2180
2181	return VINF_SUCCESS;
2182	}
2183
2184
2185	/**
2186	* Loads CPUID leaf overrides.
2187	*
2188	* This must be called before the CPUID leaves are moved from the normal
2189	* heap to the hyper heap!
2190	*
2191	* @returns VBox status code (VMSetError called).
2192	* @param pVM The cross context VM structure.
2193	* @param pParentNode The CFGM node with the CPUID leaves.
2194	* @param pszLabel How to label the overrides we're loading.
2195	*/
2196	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2197	{
2198	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2199	{
2200	/*
2201	* Get the leaf and subleaf numbers.
2202	*/
2203	char szName[128];
2204	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2205	if (RT_FAILURE(rc))
2206	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2207
2208	/* The leaf number is either specified directly or thru the node name. */
2209	uint32_t uLeaf;
2210	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2211	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2212	{
2213	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2214	if (rc != VINF_SUCCESS)
2215	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2216	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2217	}
2218	else if (RT_FAILURE(rc))
2219	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2220	pszLabel, szName, rc);
2221
2222	uint32_t uSubLeaf;
2223	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2224	if (RT_FAILURE(rc))
2225	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2226	pszLabel, szName, rc);
2227
2228	uint32_t fSubLeafMask;
2229	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2230	if (RT_FAILURE(rc))
2231	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2232	pszLabel, szName, rc);
2233
2234	/*
2235	* Look up the specified leaf, since the output register values
2236	* defaults to any existing values. This allows overriding a single
2237	* register, without needing to know the other values.
2238	*/
2239	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2240	CPUMCPUIDLEAF Leaf;
2241	if (pLeaf)
2242	Leaf = *pLeaf;
2243	else
2244	RT_ZERO(Leaf);
2245	Leaf.uLeaf = uLeaf;
2246	Leaf.uSubLeaf = uSubLeaf;
2247	Leaf.fSubLeafMask = fSubLeafMask;
2248
2249	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2250	if (RT_FAILURE(rc))
2251	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2252	pszLabel, szName, rc);
2253	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2254	if (RT_FAILURE(rc))
2255	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2256	pszLabel, szName, rc);
2257	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2258	if (RT_FAILURE(rc))
2259	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2260	pszLabel, szName, rc);
2261	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2262	if (RT_FAILURE(rc))
2263	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2264	pszLabel, szName, rc);
2265
2266	/*
2267	* Insert the leaf into the table (replaces existing ones).
2268	*/
2269	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2270	&Leaf);
2271	if (RT_FAILURE(rc))
2272	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2273	}
2274
2275	return VINF_SUCCESS;
2276	}
2277
2278
2279
2280	/**
2281	* Fetches overrides for a CPUID leaf.
2282	*
2283	* @returns VBox status code.
2284	* @param pLeaf The leaf to load the overrides into.
2285	* @param pCfgNode The CFGM node containing the overrides
2286	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2287	* @param iLeaf The CPUID leaf number.
2288	*/
2289	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2290	{
2291	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2292	if (pLeafNode)
2293	{
2294	uint32_t u32;
2295	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2296	if (RT_SUCCESS(rc))
2297	pLeaf->uEax = u32;
2298	else
2299	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2300
2301	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2302	if (RT_SUCCESS(rc))
2303	pLeaf->uEbx = u32;
2304	else
2305	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2306
2307	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2308	if (RT_SUCCESS(rc))
2309	pLeaf->uEcx = u32;
2310	else
2311	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2312
2313	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2314	if (RT_SUCCESS(rc))
2315	pLeaf->uEdx = u32;
2316	else
2317	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2318
2319	}
2320	return VINF_SUCCESS;
2321	}
2322
2323
2324	/**
2325	* Load the overrides for a set of CPUID leaves.
2326	*
2327	* @returns VBox status code.
2328	* @param paLeaves The leaf array.
2329	* @param cLeaves The number of leaves.
2330	* @param uStart The start leaf number.
2331	* @param pCfgNode The CFGM node containing the overrides
2332	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2333	*/
2334	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2335	{
2336	for (uint32_t i = 0; i < cLeaves; i++)
2337	{
2338	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2339	if (RT_FAILURE(rc))
2340	return rc;
2341	}
2342
2343	return VINF_SUCCESS;
2344	}
2345
2346
2347	/**
2348	* Installs the CPUID leaves and explods the data into structures like
2349	* GuestFeatures and CPUMCTX::aoffXState.
2350	*
2351	* @returns VBox status code.
2352	* @param pVM The cross context VM structure.
2353	* @param pCpum The CPUM part of @a VM.
2354	* @param paLeaves The leaves. These will be copied (but not freed).
2355	* @param cLeaves The number of leaves.
2356	* @param pMsrs The MSRs.
2357	*/
2358	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
2359	{
2360	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2361
2362	/*
2363	* Install the CPUID information.
2364	*/
2365	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2366	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2367
2368	AssertLogRelRCReturn(rc, rc);
2369	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2370	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2371	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2372
2373	/*
2374	* Update the default CPUID leaf if necessary.
2375	*/
2376	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2377	{
2378	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2379	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2380	{
2381	/* We don't use CPUID(0).eax here because of the NT hack that only
2382	changes that value without actually removing any leaves. */
2383	uint32_t i = 0;
2384	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2385	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2386	{
2387	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2388	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2389	i++;
2390	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2391	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2392	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2393	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2394	}
2395	break;
2396	}
2397	default:
2398	break;
2399	}
2400
2401	/*
2402	* Explode the guest CPU features.
2403	*/
2404	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
2405	&pCpum->GuestFeatures);
2406	AssertLogRelRCReturn(rc, rc);
2407
2408	/*
2409	* Adjust the scalable bus frequency according to the CPUID information
2410	* we're now using.
2411	*/
2412	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2413	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2414	? UINT64_C(100000000) /* 100MHz */
2415	: UINT64_C(133333333); /* 133MHz */
2416
2417	/*
2418	* Populate the legacy arrays. Currently used for everything, later only
2419	* for patch manager.
2420	*/
2421	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2422	{
2423	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2424	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2425	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2426	};
2427	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2428	{
2429	uint32_t cLeft = aOldRanges[i].cCpuIds;
2430	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2431	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2432	while (cLeft-- > 0)
2433	{
2434	uLeaf--;
2435	pLegacyLeaf--;
2436
2437	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2438	if (pLeaf)
2439	{
2440	pLegacyLeaf->uEax = pLeaf->uEax;
2441	pLegacyLeaf->uEbx = pLeaf->uEbx;
2442	pLegacyLeaf->uEcx = pLeaf->uEcx;
2443	pLegacyLeaf->uEdx = pLeaf->uEdx;
2444	}
2445	else
2446	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2447	}
2448	}
2449
2450	/*
2451	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2452	*/
2453	PVMCPU pVCpu0 = pVM->apCpusR3[0];
2454	memset(&pVCpu0->cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2455	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2456	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2457	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2458	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2459	{
2460	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2461	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2462	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2463	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2464	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2465	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2466	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2467	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2468	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2469	pCpum->GuestFeatures.cbMaxExtendedState),
2470	VERR_CPUM_IPE_1);
2471	pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2472	}
2473
2474	/* Copy the CPU #0 data to the other CPUs. */
2475	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
2476	{
2477	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2478	memcpy(&pVCpu->cpum.s.Guest.aoffXState[0], &pVCpu0->cpum.s.Guest.aoffXState[0], sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2479	}
2480
2481	return VINF_SUCCESS;
2482	}
2483
2484
2485	/** @name Instruction Set Extension Options
2486	* @{ */
2487	/** Configuration option type (extended boolean, really). */
2488	typedef uint8_t CPUMISAEXTCFG;
2489	/** Always disable the extension. */
2490	#define CPUMISAEXTCFG_DISABLED false
2491	/** Enable the extension if it's supported by the host CPU. */
2492	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2493	/** Enable the extension if it's supported by the host CPU, but don't let
2494	* the portable CPUID feature disable it. */
2495	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2496	/** Always enable the extension. */
2497	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2498	/** @} */
2499
2500	/**
2501	* CPUID Configuration (from CFGM).
2502	*
2503	* @remarks The members aren't document since we would only be duplicating the
2504	* \@cfgm entries in cpumR3CpuIdReadConfig.
2505	*/
2506	typedef struct CPUMCPUIDCONFIG
2507	{
2508	bool fNt4LeafLimit;
2509	bool fInvariantTsc;
2510	bool fForceVme;
2511	bool fNestedHWVirt;
2512
2513	CPUMISAEXTCFG enmCmpXchg16b;
2514	CPUMISAEXTCFG enmMonitor;
2515	CPUMISAEXTCFG enmMWaitExtensions;
2516	CPUMISAEXTCFG enmSse41;
2517	CPUMISAEXTCFG enmSse42;
2518	CPUMISAEXTCFG enmAvx;
2519	CPUMISAEXTCFG enmAvx2;
2520	CPUMISAEXTCFG enmXSave;
2521	CPUMISAEXTCFG enmAesNi;
2522	CPUMISAEXTCFG enmPClMul;
2523	CPUMISAEXTCFG enmPopCnt;
2524	CPUMISAEXTCFG enmMovBe;
2525	CPUMISAEXTCFG enmRdRand;
2526	CPUMISAEXTCFG enmRdSeed;
2527	CPUMISAEXTCFG enmCLFlushOpt;
2528	CPUMISAEXTCFG enmFsGsBase;
2529	CPUMISAEXTCFG enmPcid;
2530	CPUMISAEXTCFG enmInvpcid;
2531	CPUMISAEXTCFG enmFlushCmdMsr;
2532	CPUMISAEXTCFG enmMdsClear;
2533	CPUMISAEXTCFG enmArchCapMsr;
2534
2535	CPUMISAEXTCFG enmAbm;
2536	CPUMISAEXTCFG enmSse4A;
2537	CPUMISAEXTCFG enmMisAlnSse;
2538	CPUMISAEXTCFG enm3dNowPrf;
2539	CPUMISAEXTCFG enmAmdExtMmx;
2540
2541	uint32_t uMaxStdLeaf;
2542	uint32_t uMaxExtLeaf;
2543	uint32_t uMaxCentaurLeaf;
2544	uint32_t uMaxIntelFamilyModelStep;
2545	char szCpuName[128];
2546	} CPUMCPUIDCONFIG;
2547	/** Pointer to CPUID config (from CFGM). */
2548	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2549
2550
2551	/**
2552	* Mini CPU selection support for making Mac OS X happy.
2553	*
2554	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2555	*
2556	* @param pCpum The CPUM instance data.
2557	* @param pConfig The CPUID configuration we've read from CFGM.
2558	*/
2559	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2560	{
2561	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2562	{
2563	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2564	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2565	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2566	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2567	0);
2568	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2569	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2570	{
2571	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2572	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2573	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2574	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2575	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2576	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2577	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2578	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2579	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2580	pStdFeatureLeaf->uEax = uNew;
2581	}
2582	}
2583	}
2584
2585
2586
2587	/**
2588	* Limit it the number of entries, zapping the remainder.
2589	*
2590	* The limits are masking off stuff about power saving and similar, this
2591	* is perhaps a bit crudely done as there is probably some relatively harmless
2592	* info too in these leaves (like words about having a constant TSC).
2593	*
2594	* @param pCpum The CPUM instance data.
2595	* @param pConfig The CPUID configuration we've read from CFGM.
2596	*/
2597	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2598	{
2599	/*
2600	* Standard leaves.
2601	*/
2602	uint32_t uSubLeaf = 0;
2603	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2604	if (pCurLeaf)
2605	{
2606	uint32_t uLimit = pCurLeaf->uEax;
2607	if (uLimit <= UINT32_C(0x000fffff))
2608	{
2609	if (uLimit > pConfig->uMaxStdLeaf)
2610	{
2611	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2612	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2613	uLimit + 1, UINT32_C(0x000fffff));
2614	}
2615
2616	/* NT4 hack, no zapping of extra leaves here. */
2617	if (pConfig->fNt4LeafLimit && uLimit > 3)
2618	pCurLeaf->uEax = uLimit = 3;
2619
2620	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2621	pCurLeaf->uEax = uLimit;
2622	}
2623	else
2624	{
2625	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2626	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2627	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2628	}
2629	}
2630
2631	/*
2632	* Extended leaves.
2633	*/
2634	uSubLeaf = 0;
2635	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2636	if (pCurLeaf)
2637	{
2638	uint32_t uLimit = pCurLeaf->uEax;
2639	if ( uLimit >= UINT32_C(0x80000000)
2640	&& uLimit <= UINT32_C(0x800fffff))
2641	{
2642	if (uLimit > pConfig->uMaxExtLeaf)
2643	{
2644	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2645	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2646	uLimit + 1, UINT32_C(0x800fffff));
2647	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2648	pCurLeaf->uEax = uLimit;
2649	}
2650	}
2651	else
2652	{
2653	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2654	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2655	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2656	}
2657	}
2658
2659	/*
2660	* Centaur leaves (VIA).
2661	*/
2662	uSubLeaf = 0;
2663	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2664	if (pCurLeaf)
2665	{
2666	uint32_t uLimit = pCurLeaf->uEax;
2667	if ( uLimit >= UINT32_C(0xc0000000)
2668	&& uLimit <= UINT32_C(0xc00fffff))
2669	{
2670	if (uLimit > pConfig->uMaxCentaurLeaf)
2671	{
2672	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2673	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2674	uLimit + 1, UINT32_C(0xcfffffff));
2675	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2676	pCurLeaf->uEax = uLimit;
2677	}
2678	}
2679	else
2680	{
2681	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2682	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2683	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2684	}
2685	}
2686	}
2687
2688
2689	/**
2690	* Clears a CPUID leaf and all sub-leaves (to zero).
2691	*
2692	* @param pCpum The CPUM instance data.
2693	* @param uLeaf The leaf to clear.
2694	*/
2695	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2696	{
2697	uint32_t uSubLeaf = 0;
2698	PCPUMCPUIDLEAF pCurLeaf;
2699	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2700	{
2701	pCurLeaf->uEax = 0;
2702	pCurLeaf->uEbx = 0;
2703	pCurLeaf->uEcx = 0;
2704	pCurLeaf->uEdx = 0;
2705	uSubLeaf++;
2706	}
2707	}
2708
2709
2710	/**
2711	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2712	* the given leaf.
2713	*
2714	* @returns pLeaf.
2715	* @param pCpum The CPUM instance data.
2716	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2717	*/
2718	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2719	{
2720	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2721	if (pLeaf->fSubLeafMask != 0)
2722	{
2723	/*
2724	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2725	* Log everything while we're at it.
2726	*/
2727	LogRel(("CPUM:\n"
2728	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2729	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2730	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2731	for (;;)
2732	{
2733	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2734	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2735	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2736	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2737	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2738	break;
2739	pSubLeaf++;
2740	}
2741	LogRel(("CPUM:\n"));
2742
2743	/*
2744	* Remove the offending sub-leaves.
2745	*/
2746	if (pSubLeaf != pLeaf)
2747	{
2748	if (pSubLeaf != pLast)
2749	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2750	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2751	}
2752
2753	/*
2754	* Convert the first sub-leaf into a single leaf.
2755	*/
2756	pLeaf->uSubLeaf = 0;
2757	pLeaf->fSubLeafMask = 0;
2758	}
2759	return pLeaf;
2760	}
2761
2762
2763	/**
2764	* Sanitizes and adjust the CPUID leaves.
2765	*
2766	* Drop features that aren't virtualized (or virtualizable). Adjust information
2767	* and capabilities to fit the virtualized hardware. Remove information the
2768	* guest shouldn't have (because it's wrong in the virtual world or because it
2769	* gives away host details) or that we don't have documentation for and no idea
2770	* what means.
2771	*
2772	* @returns VBox status code.
2773	* @param pVM The cross context VM structure (for cCpus).
2774	* @param pCpum The CPUM instance data.
2775	* @param pConfig The CPUID configuration we've read from CFGM.
2776	*/
2777	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2778	{
2779	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2780	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2781	{ \
2782	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2783	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2784	}
2785	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2786	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2787	{ \
2788	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2789	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2790	}
2791	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2792	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2793	&& ((a_pLeafReg) & (fBitMask)) \
2794	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2795	{ \
2796	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2797	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2798	}
2799	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2800
2801	/* The CPUID entries we start with here isn't necessarily the ones of the host, so we
2802	must consult HostFeatures when processing CPUMISAEXTCFG variables. */
2803	PCCPUMFEATURES pHstFeat = &pCpum->HostFeatures;
2804	#define PASSTHRU_FEATURE(enmConfig, fHostFeature, fConst) \
2805	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) ? (fConst) : 0)
2806	#define PASSTHRU_FEATURE_EX(enmConfig, fHostFeature, fAndExpr, fConst) \
2807	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) && (fAndExpr) ? (fConst) : 0)
2808	#define PASSTHRU_FEATURE_TODO(enmConfig, fConst) ((enmConfig) ? (fConst) : 0)
2809
2810	/* Cpuid 1:
2811	* EAX: CPU model, family and stepping.
2812	*
2813	* ECX + EDX: Supported features. Only report features we can support.
2814	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2815	* options may require adjusting (i.e. stripping what was enabled).
2816	*
2817	* EBX: Branding, CLFLUSH line size, logical processors per package and
2818	* initial APIC ID.
2819	*/
2820	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2821	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2822	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2823
2824	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2825	\| X86_CPUID_FEATURE_EDX_VME
2826	\| X86_CPUID_FEATURE_EDX_DE
2827	\| X86_CPUID_FEATURE_EDX_PSE
2828	\| X86_CPUID_FEATURE_EDX_TSC
2829	\| X86_CPUID_FEATURE_EDX_MSR
2830	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2831	\| X86_CPUID_FEATURE_EDX_MCE
2832	\| X86_CPUID_FEATURE_EDX_CX8
2833	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2834	//\| RT_BIT_32(10) - not defined
2835	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2836	//\| X86_CPUID_FEATURE_EDX_SEP
2837	\| X86_CPUID_FEATURE_EDX_MTRR
2838	\| X86_CPUID_FEATURE_EDX_PGE
2839	\| X86_CPUID_FEATURE_EDX_MCA
2840	\| X86_CPUID_FEATURE_EDX_CMOV
2841	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2842	\| X86_CPUID_FEATURE_EDX_PSE36
2843	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2844	\| X86_CPUID_FEATURE_EDX_CLFSH
2845	//\| RT_BIT_32(20) - not defined
2846	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2847	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2848	\| X86_CPUID_FEATURE_EDX_MMX
2849	\| X86_CPUID_FEATURE_EDX_FXSR
2850	\| X86_CPUID_FEATURE_EDX_SSE
2851	\| X86_CPUID_FEATURE_EDX_SSE2
2852	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2853	\| X86_CPUID_FEATURE_EDX_HTT
2854	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2855	//\| RT_BIT_32(30) - not defined
2856	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2857	;
2858	pStdFeatureLeaf->uEcx &= X86_CPUID_FEATURE_ECX_SSE3
2859	\| PASSTHRU_FEATURE_TODO(pConfig->enmPClMul, X86_CPUID_FEATURE_ECX_PCLMUL)
2860	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2861	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2862	\| PASSTHRU_FEATURE_EX(pConfig->enmMonitor, pHstFeat->fMonitorMWait, pVM->cCpus == 1, X86_CPUID_FEATURE_ECX_MONITOR)
2863	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2864	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2865	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2866	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2867	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2868	\| X86_CPUID_FEATURE_ECX_SSSE3
2869	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2870	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2871	\| PASSTHRU_FEATURE(pConfig->enmCmpXchg16b, pHstFeat->fMovCmpXchg16b, X86_CPUID_FEATURE_ECX_CX16)
2872	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2873	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2874	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2875	\| PASSTHRU_FEATURE(pConfig->enmPcid, pHstFeat->fPcid, X86_CPUID_FEATURE_ECX_PCID)
2876	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2877	\| PASSTHRU_FEATURE(pConfig->enmSse41, pHstFeat->fSse41, X86_CPUID_FEATURE_ECX_SSE4_1)
2878	\| PASSTHRU_FEATURE(pConfig->enmSse42, pHstFeat->fSse42, X86_CPUID_FEATURE_ECX_SSE4_2)
2879	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2880	\| PASSTHRU_FEATURE_TODO(pConfig->enmMovBe, X86_CPUID_FEATURE_ECX_MOVBE)
2881	\| PASSTHRU_FEATURE_TODO(pConfig->enmPopCnt, X86_CPUID_FEATURE_ECX_POPCNT)
2882	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2883	\| PASSTHRU_FEATURE_TODO(pConfig->enmAesNi, X86_CPUID_FEATURE_ECX_AES)
2884	\| PASSTHRU_FEATURE(pConfig->enmXSave, pHstFeat->fXSaveRstor, X86_CPUID_FEATURE_ECX_XSAVE)
2885	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2886	\| PASSTHRU_FEATURE(pConfig->enmAvx, pHstFeat->fAvx, X86_CPUID_FEATURE_ECX_AVX)
2887	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2888	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdRand, X86_CPUID_FEATURE_ECX_RDRAND)
2889	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2890	;
2891
2892	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2893	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2894	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2895	{
2896	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2897	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2898	}
2899
2900	if (pCpum->u8PortableCpuIdLevel > 0)
2901	{
2902	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2903	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2904	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2905	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2906	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2907	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2908	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2909	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2910	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2911	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2912	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2913	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2914	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2915	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2916	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2917	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2918	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2919	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2920	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2921	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2922
2923	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2924	\| X86_CPUID_FEATURE_EDX_PSN
2925	\| X86_CPUID_FEATURE_EDX_DS
2926	\| X86_CPUID_FEATURE_EDX_ACPI
2927	\| X86_CPUID_FEATURE_EDX_SS
2928	\| X86_CPUID_FEATURE_EDX_TM
2929	\| X86_CPUID_FEATURE_EDX_PBE
2930	)));
2931	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2932	\| X86_CPUID_FEATURE_ECX_CPLDS
2933	\| X86_CPUID_FEATURE_ECX_AES
2934	\| X86_CPUID_FEATURE_ECX_VMX
2935	\| X86_CPUID_FEATURE_ECX_SMX
2936	\| X86_CPUID_FEATURE_ECX_EST
2937	\| X86_CPUID_FEATURE_ECX_TM2
2938	\| X86_CPUID_FEATURE_ECX_CNTXID
2939	\| X86_CPUID_FEATURE_ECX_FMA
2940	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2941	\| X86_CPUID_FEATURE_ECX_PDCM
2942	\| X86_CPUID_FEATURE_ECX_DCA
2943	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2944	)));
2945	}
2946
2947	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2948	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2949
2950	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2951	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2952	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2953	*/
2954	#ifdef VBOX_WITH_MULTI_CORE
2955	if (pVM->cCpus > 1)
2956	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2957	#endif
2958	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2959	{
2960	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2961	core times the number of CPU cores per processor */
2962	#ifdef VBOX_WITH_MULTI_CORE
2963	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2964	#else
2965	/* Single logical processor in a package. */
2966	pStdFeatureLeaf->uEbx \|= (1 << 16);
2967	#endif
2968	}
2969
2970	uint32_t uMicrocodeRev;
2971	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2972	if (RT_SUCCESS(rc))
2973	{
2974	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2975	}
2976	else
2977	{
2978	uMicrocodeRev = 0;
2979	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2980	}
2981
2982	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2983	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2984	*/
2985	if ( ( pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen
2986	/** @todo The following ASSUMES that Hygon uses the same version numbering
2987	* as AMD and that they shipped buggy firmware. */
2988	\|\| pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Hygon_Dhyana)
2989	&& uMicrocodeRev < 0x8001126
2990	&& !pConfig->fForceVme)
2991	{
2992	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2993	LogRel(("CPUM: Zen VME workaround engaged\n"));
2994	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2995	}
2996
2997	/* Force standard feature bits. */
2998	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2999	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
3000	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
3001	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
3002	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
3003	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
3004	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3005	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
3006	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3007	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
3008	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
3009	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
3010	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3011	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
3012	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
3013	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
3014	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
3015	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
3016	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3017	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
3018	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
3019	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
3020
3021	pStdFeatureLeaf = NULL; /* Must refetch! */
3022
3023	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
3024	* AMD:
3025	* EAX: CPU model, family and stepping.
3026	*
3027	* ECX + EDX: Supported features. Only report features we can support.
3028	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3029	* options may require adjusting (i.e. stripping what was enabled).
3030	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
3031	*
3032	* EBX: Branding ID and package type (or reserved).
3033	*
3034	* Intel and probably most others:
3035	* EAX: 0
3036	* EBX: 0
3037	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
3038	*/
3039	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3040	if (pExtFeatureLeaf)
3041	{
3042	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
3043
3044	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
3045	\| X86_CPUID_AMD_FEATURE_EDX_VME
3046	\| X86_CPUID_AMD_FEATURE_EDX_DE
3047	\| X86_CPUID_AMD_FEATURE_EDX_PSE
3048	\| X86_CPUID_AMD_FEATURE_EDX_TSC
3049	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
3050	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
3051	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
3052	\| X86_CPUID_AMD_FEATURE_EDX_CX8
3053	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
3054	//\| RT_BIT_32(10) - reserved
3055	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
3056	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
3057	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3058	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
3059	\| X86_CPUID_AMD_FEATURE_EDX_PGE
3060	\| X86_CPUID_AMD_FEATURE_EDX_MCA
3061	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
3062	\| X86_CPUID_AMD_FEATURE_EDX_PAT
3063	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
3064	//\| RT_BIT_32(18) - reserved
3065	//\| RT_BIT_32(19) - reserved
3066	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
3067	//\| RT_BIT_32(21) - reserved
3068	\| PASSTHRU_FEATURE(pConfig->enmAmdExtMmx, pHstFeat->fAmdMmxExts, X86_CPUID_AMD_FEATURE_EDX_AXMMX)
3069	\| X86_CPUID_AMD_FEATURE_EDX_MMX
3070	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
3071	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
3072	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3073	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
3074	//\| RT_BIT_32(28) - reserved
3075	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
3076	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
3077	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
3078	;
3079	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
3080	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
3081	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
3082	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3083	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
3084	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
3085	\| PASSTHRU_FEATURE_TODO(pConfig->enmAbm, X86_CPUID_AMD_FEATURE_ECX_ABM)
3086	\| PASSTHRU_FEATURE_TODO(pConfig->enmSse4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A)
3087	\| PASSTHRU_FEATURE_TODO(pConfig->enmMisAlnSse, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE)
3088	\| PASSTHRU_FEATURE(pConfig->enm3dNowPrf, pHstFeat->f3DNowPrefetch, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
3089	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3090	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
3091	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
3092	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3093	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
3094	//\| RT_BIT_32(14) - reserved
3095	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
3096	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
3097	//\| RT_BIT_32(17) - reserved
3098	//\| RT_BIT_32(18) - reserved
3099	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
3100	//\| RT_BIT_32(20) - reserved
3101	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
3102	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
3103	//\| RT_BIT_32(23) - reserved
3104	//\| RT_BIT_32(24) - reserved
3105	//\| RT_BIT_32(25) - reserved
3106	//\| RT_BIT_32(26) - reserved
3107	//\| RT_BIT_32(27) - reserved
3108	//\| RT_BIT_32(28) - reserved
3109	//\| RT_BIT_32(29) - reserved
3110	//\| RT_BIT_32(30) - reserved
3111	//\| RT_BIT_32(31) - reserved
3112	;
3113	#ifdef VBOX_WITH_MULTI_CORE
3114	if ( pVM->cCpus > 1
3115	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3116	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3117	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
3118	#endif
3119
3120	if (pCpum->u8PortableCpuIdLevel > 0)
3121	{
3122	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
3123	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
3124	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
3125	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
3126	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
3127	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
3128	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
3129	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
3130	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
3131	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
3132	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
3133	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
3134	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
3135	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
3136	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
3137	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
3138
3139	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
3140	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3141	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3142	\| X86_CPUID_AMD_FEATURE_ECX_IBS
3143	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3144	\| X86_CPUID_AMD_FEATURE_ECX_WDT
3145	\| X86_CPUID_AMD_FEATURE_ECX_LWP
3146	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
3147	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
3148	\| UINT32_C(0xff964000)
3149	)));
3150	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
3151	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3152	\| RT_BIT(18)
3153	\| RT_BIT(19)
3154	\| RT_BIT(21)
3155	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
3156	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3157	\| RT_BIT(28)
3158	)));
3159	}
3160
3161	/* Force extended feature bits. */
3162	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
3163	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
3164	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
3165	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
3166	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
3167	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
3168	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
3169	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
3170	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3171	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
3172	}
3173	pExtFeatureLeaf = NULL; /* Must refetch! */
3174
3175
3176	/* Cpuid 2:
3177	* Intel: (Nondeterministic) Cache and TLB information
3178	* AMD: Reserved
3179	* VIA: Reserved
3180	* Safe to expose.
3181	*/
3182	uint32_t uSubLeaf = 0;
3183	PCPUMCPUIDLEAF pCurLeaf;
3184	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
3185	{
3186	if ((pCurLeaf->uEax & 0xff) > 1)
3187	{
3188	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
3189	pCurLeaf->uEax &= UINT32_C(0xffffff01);
3190	}
3191	uSubLeaf++;
3192	}
3193
3194	/* Cpuid 3:
3195	* Intel: EAX, EBX - reserved (transmeta uses these)
3196	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3197	* AMD: Reserved
3198	* VIA: Reserved
3199	* Safe to expose
3200	*/
3201	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3202	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3203	{
3204	uSubLeaf = 0;
3205	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3206	{
3207	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3208	if (pCpum->u8PortableCpuIdLevel > 0)
3209	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3210	uSubLeaf++;
3211	}
3212	}
3213
3214	/* Cpuid 4 + ECX:
3215	* Intel: Deterministic Cache Parameters Leaf.
3216	* AMD: Reserved
3217	* VIA: Reserved
3218	* Safe to expose, except for EAX:
3219	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3220	* Bits 31-26: Maximum number of processor cores in this physical package**
3221	* Note: These SMP values are constant regardless of ECX
3222	*/
3223	uSubLeaf = 0;
3224	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3225	{
3226	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3227	#ifdef VBOX_WITH_MULTI_CORE
3228	if ( pVM->cCpus > 1
3229	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3230	{
3231	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3232	/* One logical processor with possibly multiple cores. */
3233	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3234	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3235	}
3236	#endif
3237	uSubLeaf++;
3238	}
3239
3240	/* Cpuid 5: Monitor/mwait Leaf
3241	* Intel: ECX, EDX - reserved
3242	* EAX, EBX - Smallest and largest monitor line size
3243	* AMD: EDX - reserved
3244	* EAX, EBX - Smallest and largest monitor line size
3245	* ECX - extensions (ignored for now)
3246	* VIA: Reserved
3247	* Safe to expose
3248	*/
3249	uSubLeaf = 0;
3250	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3251	{
3252	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3253	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3254	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3255
3256	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3257	if (pConfig->enmMWaitExtensions)
3258	{
3259	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3260	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3261	it shall be part of our power management virtualization model */
3262	#if 0
3263	/* MWAIT sub C-states */
3264	pCurLeaf->uEdx =
3265	(0 << 0) /* 0 in C0 */ \|
3266	(2 << 4) /* 2 in C1 */ \|
3267	(2 << 8) /* 2 in C2 */ \|
3268	(2 << 12) /* 2 in C3 */ \|
3269	(0 << 16) /* 0 in C4 */
3270	;
3271	#endif
3272	}
3273	else
3274	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3275	uSubLeaf++;
3276	}
3277
3278	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3279	* Intel: Various stuff.
3280	* AMD: EAX, EBX, EDX - reserved.
3281	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3282	* present. Same as intel.
3283	* VIA: ??
3284	*
3285	* We clear everything here for now.
3286	*/
3287	cpumR3CpuIdZeroLeaf(pCpum, 6);
3288
3289	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3290	* EAX: Number of sub leaves.
3291	* EBX+ECX+EDX: Feature flags
3292	*
3293	* We only have documentation for one sub-leaf, so clear all other (no need
3294	* to remove them as such, just set them to zero).
3295	*
3296	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3297	* options may require adjusting (i.e. stripping what was enabled).
3298	*/
3299	uSubLeaf = 0;
3300	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3301	{
3302	switch (uSubLeaf)
3303	{
3304	case 0:
3305	{
3306	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3307	pCurLeaf->uEbx &= 0
3308	\| PASSTHRU_FEATURE(pConfig->enmFsGsBase, pHstFeat->fFsGsBase, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE)
3309	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3310	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3311	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3312	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3313	\| PASSTHRU_FEATURE(pConfig->enmAvx2, pHstFeat->fAvx2, X86_CPUID_STEXT_FEATURE_EBX_AVX2)
3314	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3315	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3316	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3317	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3318	\| PASSTHRU_FEATURE(pConfig->enmInvpcid, pHstFeat->fInvpcid, X86_CPUID_STEXT_FEATURE_EBX_INVPCID)
3319	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3320	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3321	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3322	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3323	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3324	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3325	//\| RT_BIT(17) - reserved
3326	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdSeed, X86_CPUID_STEXT_FEATURE_EBX_RDSEED)
3327	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3328	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3329	//\| RT_BIT(21) - reserved
3330	//\| RT_BIT(22) - reserved
3331	\| PASSTHRU_FEATURE(pConfig->enmCLFlushOpt, pHstFeat->fClFlushOpt, X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT)
3332	//\| RT_BIT(24) - reserved
3333	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3334	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3335	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3336	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3337	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3338	//\| RT_BIT(30) - reserved
3339	//\| RT_BIT(31) - reserved
3340	;
3341	pCurLeaf->uEcx &= 0
3342	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3343	;
3344	pCurLeaf->uEdx &= 0
3345	\| PASSTHRU_FEATURE(pConfig->enmMdsClear, pHstFeat->fMdsClear, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR)
3346	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3347	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3348	\| PASSTHRU_FEATURE(pConfig->enmFlushCmdMsr, pHstFeat->fFlushCmd, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD)
3349	\| PASSTHRU_FEATURE(pConfig->enmArchCapMsr, pHstFeat->fArchCap, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
3350	;
3351
3352	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3353	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3354	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3355	{
3356	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3357	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3358	}
3359
3360	if (pCpum->u8PortableCpuIdLevel > 0)
3361	{
3362	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3363	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3364	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3365	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3366	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3367	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3368	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3369	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3370	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3371	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3372	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3373	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3374	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3375	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3376	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3377	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
3378	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
3379	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
3380	}
3381
3382	/* Dependencies. */
3383	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
3384	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3385
3386	/* Force standard feature bits. */
3387	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3388	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3389	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3390	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3391	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3392	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3393	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3394	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3395	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3396	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3397	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3398	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
3399	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
3400	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3401	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3402	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
3403	break;
3404	}
3405
3406	default:
3407	/* Invalid index, all values are zero. */
3408	pCurLeaf->uEax = 0;
3409	pCurLeaf->uEbx = 0;
3410	pCurLeaf->uEcx = 0;
3411	pCurLeaf->uEdx = 0;
3412	break;
3413	}
3414	uSubLeaf++;
3415	}
3416
3417	/* Cpuid 8: Marked as reserved by Intel and AMD.
3418	* We zero this since we don't know what it may have been used for.
3419	*/
3420	cpumR3CpuIdZeroLeaf(pCpum, 8);
3421
3422	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3423	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3424	* EBX, ECX, EDX - reserved.
3425	* AMD: Reserved
3426	* VIA: ??
3427	*
3428	* We zero this.
3429	*/
3430	cpumR3CpuIdZeroLeaf(pCpum, 9);
3431
3432	/* Cpuid 0xa: Architectural Performance Monitor Features
3433	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3434	* EBX, ECX, EDX - reserved.
3435	* AMD: Reserved
3436	* VIA: ??
3437	*
3438	* We zero this, for now at least.
3439	*/
3440	cpumR3CpuIdZeroLeaf(pCpum, 10);
3441
3442	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3443	* Intel: EAX - APCI ID shift right for next level.
3444	* EBX - Factory configured cores/threads at this level.
3445	* ECX - Level number (same as input) and level type (1,2,0).
3446	* EDX - Extended initial APIC ID.
3447	* AMD: Reserved
3448	* VIA: ??
3449	*/
3450	uSubLeaf = 0;
3451	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3452	{
3453	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3454	{
3455	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3456	if (bLevelType == 1)
3457	{
3458	/* Thread level - we don't do threads at the moment. */
3459	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3460	pCurLeaf->uEbx = 1;
3461	}
3462	else if (bLevelType == 2)
3463	{
3464	/* Core level. */
3465	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3466	#ifdef VBOX_WITH_MULTI_CORE
3467	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3468	pCurLeaf->uEax++;
3469	#endif
3470	pCurLeaf->uEbx = pVM->cCpus;
3471	}
3472	else
3473	{
3474	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3475	pCurLeaf->uEax = 0;
3476	pCurLeaf->uEbx = 0;
3477	pCurLeaf->uEcx = 0;
3478	}
3479	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3480	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3481	}
3482	else
3483	{
3484	pCurLeaf->uEax = 0;
3485	pCurLeaf->uEbx = 0;
3486	pCurLeaf->uEcx = 0;
3487	pCurLeaf->uEdx = 0;
3488	}
3489	uSubLeaf++;
3490	}
3491
3492	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3493	* We zero this since we don't know what it may have been used for.
3494	*/
3495	cpumR3CpuIdZeroLeaf(pCpum, 12);
3496
3497	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3498	* ECX=0: EAX - Valid bits in XCR0[31:0].
3499	* EBX - Maximum state size as per current XCR0 value.
3500	* ECX - Maximum state size for all supported features.
3501	* EDX - Valid bits in XCR0[63:32].
3502	* ECX=1: EAX - Various X-features.
3503	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3504	* ECX - Valid bits in IA32_XSS[31:0].
3505	* EDX - Valid bits in IA32_XSS[63:32].
3506	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3507	* if the bit invalid all four registers are set to zero.
3508	* EAX - The state size for this feature.
3509	* EBX - The state byte offset of this feature.
3510	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3511	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3512	*
3513	* Clear them all as we don't currently implement extended CPU state.
3514	*/
3515	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3516	uint64_t fGuestXcr0Mask = 0;
3517	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3518	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3519	{
3520	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3521	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3522	fGuestXcr0Mask \|= XSAVE_C_YMM;
3523	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3524	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3525	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3526	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3527
3528	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3529	}
3530	pStdFeatureLeaf = NULL;
3531	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3532
3533	/* Work the sub-leaves. */
3534	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3535	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3536	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3537	{
3538	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3539	if (pCurLeaf)
3540	{
3541	if (fGuestXcr0Mask)
3542	{
3543	switch (uSubLeaf)
3544	{
3545	case 0:
3546	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3547	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3548	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3549	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3550	VERR_CPUM_IPE_1);
3551	cbXSaveMaxActual = pCurLeaf->uEcx;
3552	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3553	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3554	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3555	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3556	VERR_CPUM_IPE_2);
3557	continue;
3558	case 1:
3559	pCurLeaf->uEax &= 0;
3560	pCurLeaf->uEcx &= 0;
3561	pCurLeaf->uEdx &= 0;
3562	/** @todo what about checking ebx? */
3563	continue;
3564	default:
3565	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3566	{
3567	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3568	&& pCurLeaf->uEax > 0
3569	&& pCurLeaf->uEbx < cbXSaveMaxActual
3570	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3571	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3572	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3573	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3574	VERR_CPUM_IPE_2);
3575	AssertLogRel(!(pCurLeaf->uEcx & 1));
3576	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3577	pCurLeaf->uEdx = 0; /* it's reserved... */
3578	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3579	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3580	continue;
3581	}
3582	break;
3583	}
3584	}
3585
3586	/* Clear the leaf. */
3587	pCurLeaf->uEax = 0;
3588	pCurLeaf->uEbx = 0;
3589	pCurLeaf->uEcx = 0;
3590	pCurLeaf->uEdx = 0;
3591	}
3592	}
3593
3594	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3595	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3596	{
3597	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3598	if (pCurLeaf)
3599	{
3600	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3601	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3602	pCurLeaf->uEbx = cbXSaveMaxReport;
3603	pCurLeaf->uEcx = cbXSaveMaxReport;
3604	}
3605	}
3606
3607	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3608	* We zero this since we don't know what it may have been used for.
3609	*/
3610	cpumR3CpuIdZeroLeaf(pCpum, 14);
3611
3612	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3613	* also known as Intel Resource Director Technology (RDT) Monitoring
3614	* We zero this as we don't currently virtualize PQM.
3615	*/
3616	cpumR3CpuIdZeroLeaf(pCpum, 15);
3617
3618	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3619	* also known as Intel Resource Director Technology (RDT) Allocation
3620	* We zero this as we don't currently virtualize PQE.
3621	*/
3622	cpumR3CpuIdZeroLeaf(pCpum, 16);
3623
3624	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3625	* We zero this since we don't know what it may have been used for.
3626	*/
3627	cpumR3CpuIdZeroLeaf(pCpum, 17);
3628
3629	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3630	* We zero this as we don't currently virtualize this.
3631	*/
3632	cpumR3CpuIdZeroLeaf(pCpum, 18);
3633
3634	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3635	* We zero this since we don't know what it may have been used for.
3636	*/
3637	cpumR3CpuIdZeroLeaf(pCpum, 19);
3638
3639	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3640	* We zero this as we don't currently virtualize this.
3641	*/
3642	cpumR3CpuIdZeroLeaf(pCpum, 20);
3643
3644	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3645	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3646	* EAX - denominator (unsigned).
3647	* EBX - numerator (unsigned).
3648	* ECX, EDX - reserved.
3649	* AMD: Reserved / undefined / not implemented.
3650	* VIA: Reserved / undefined / not implemented.
3651	* We zero this as we don't currently virtualize this.
3652	*/
3653	cpumR3CpuIdZeroLeaf(pCpum, 21);
3654
3655	/* Cpuid 0x16: Processor frequency info
3656	* Intel: EAX - Core base frequency in MHz.
3657	* EBX - Core maximum frequency in MHz.
3658	* ECX - Bus (reference) frequency in MHz.
3659	* EDX - Reserved.
3660	* AMD: Reserved / undefined / not implemented.
3661	* VIA: Reserved / undefined / not implemented.
3662	* We zero this as we don't currently virtualize this.
3663	*/
3664	cpumR3CpuIdZeroLeaf(pCpum, 22);
3665
3666	/* Cpuid 0x17..0x10000000: Unknown.
3667	* We don't know these and what they mean, so remove them. */
3668	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3669	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3670
3671
3672	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3673	* We remove all these as we're a hypervisor and must provide our own.
3674	*/
3675	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3676	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3677
3678
3679	/* Cpuid 0x80000000 is harmless. */
3680
3681	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3682
3683	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3684
3685	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3686	* Safe to pass on to the guest.
3687	*
3688	* AMD: 0x800000005 L1 cache information
3689	* 0x800000006 L2/L3 cache information
3690	* Intel: 0x800000005 reserved
3691	* 0x800000006 L2 cache information
3692	* VIA: 0x800000005 TLB and L1 cache information
3693	* 0x800000006 L2 cache information
3694	*/
3695
3696	/* Cpuid 0x800000007: Advanced Power Management Information.
3697	* AMD: EAX: Processor feedback capabilities.
3698	* EBX: RAS capabilites.
3699	* ECX: Advanced power monitoring interface.
3700	* EDX: Enhanced power management capabilities.
3701	* Intel: EAX, EBX, ECX - reserved.
3702	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3703	* VIA: Reserved
3704	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3705	*/
3706	uSubLeaf = 0;
3707	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3708	{
3709	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3710	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3711	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3712	{
3713	/*
3714	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3715	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3716	* bit is now configurable.
3717	*/
3718	pCurLeaf->uEdx &= 0
3719	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3720	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3721	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3722	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3723	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3724	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3725	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3726	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3727	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3728	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3729	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3730	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3731	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3732	\| 0;
3733	}
3734	else
3735	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3736	if (!pConfig->fInvariantTsc)
3737	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3738	uSubLeaf++;
3739	}
3740
3741	/* Cpuid 0x80000008:
3742	* AMD: EBX, EDX - reserved
3743	* EAX: Virtual/Physical/Guest address Size
3744	* ECX: Number of cores + APICIdCoreIdSize
3745	* Intel: EAX: Virtual/Physical address Size
3746	* EBX, ECX, EDX - reserved
3747	* VIA: EAX: Virtual/Physical address Size
3748	* EBX, ECX, EDX - reserved
3749	*
3750	* We only expose the virtual+pysical address size to the guest atm.
3751	* On AMD we set the core count, but not the apic id stuff as we're
3752	* currently not doing the apic id assignments in a complatible manner.
3753	*/
3754	uSubLeaf = 0;
3755	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3756	{
3757	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3758	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3759	pCurLeaf->uEdx = 0; /* reserved */
3760
3761	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3762	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3763	pCurLeaf->uEcx = 0;
3764	#ifdef VBOX_WITH_MULTI_CORE
3765	if ( pVM->cCpus > 1
3766	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3767	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3768	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3769	#endif
3770	uSubLeaf++;
3771	}
3772
3773	/* Cpuid 0x80000009: Reserved
3774	* We zero this since we don't know what it may have been used for.
3775	*/
3776	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3777
3778	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
3779	* AMD: EAX - SVM revision.
3780	* EBX - Number of ASIDs.
3781	* ECX - Reserved.
3782	* EDX - SVM Feature identification.
3783	*/
3784	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3785	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3786	{
3787	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3788	if ( pExtFeatureLeaf
3789	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
3790	{
3791	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3792	if (pSvmFeatureLeaf)
3793	{
3794	pSvmFeatureLeaf->uEax = 0x1;
3795	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3796	pSvmFeatureLeaf->uEcx = 0;
3797	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3798	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3799	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3800	}
3801	else
3802	{
3803	/* Should never happen. */
3804	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
3805	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3806	}
3807	}
3808	else
3809	{
3810	/* If SVM is not supported, this is reserved, zero out. */
3811	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3812	}
3813	}
3814	else
3815	{
3816	/* Cpuid 0x8000000a: Reserved on Intel.
3817	* We zero this since we don't know what it may have been used for.
3818	*/
3819	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3820	}
3821
3822	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3823	* We clear these as we don't know what purpose they might have. */
3824	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3825	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3826
3827	/* Cpuid 0x80000019: TLB configuration
3828	* Seems to be harmless, pass them thru as is. */
3829
3830	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3831	* Strip anything we don't know what is or addresses feature we don't implement. */
3832	uSubLeaf = 0;
3833	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3834	{
3835	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3836	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3837	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3838	;
3839	pCurLeaf->uEbx = 0; /* reserved */
3840	pCurLeaf->uEcx = 0; /* reserved */
3841	pCurLeaf->uEdx = 0; /* reserved */
3842	uSubLeaf++;
3843	}
3844
3845	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3846	* Clear this as we don't currently virtualize this feature. */
3847	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3848
3849	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3850	* Clear this as we don't currently virtualize this feature. */
3851	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3852
3853	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3854	* We need to sanitize the cores per cache (EAX[25:14]).
3855	*
3856	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3857	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3858	* slightly different meaning.
3859	*/
3860	uSubLeaf = 0;
3861	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3862	{
3863	#ifdef VBOX_WITH_MULTI_CORE
3864	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3865	if (cCores > pVM->cCpus)
3866	cCores = pVM->cCpus;
3867	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3868	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3869	#else
3870	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3871	#endif
3872	uSubLeaf++;
3873	}
3874
3875	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3876	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3877	* setup, we have one compute unit with all the cores in it. Single node.
3878	*/
3879	uSubLeaf = 0;
3880	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3881	{
3882	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3883	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3884	{
3885	#ifdef VBOX_WITH_MULTI_CORE
3886	pCurLeaf->uEbx = pVM->cCpus < 0x100
3887	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3888	#else
3889	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3890	#endif
3891	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3892	}
3893	else
3894	{
3895	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3896	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_HYGON);
3897	pCurLeaf->uEbx = 0; /* Reserved. */
3898	pCurLeaf->uEcx = 0; /* Reserved. */
3899	}
3900	pCurLeaf->uEdx = 0; /* Reserved. */
3901	uSubLeaf++;
3902	}
3903
3904	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3905	* We don't know these and what they mean, so remove them. */
3906	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3907	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3908
3909	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3910	* Just pass it thru for now. */
3911
3912	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3913	* Just pass it thru for now. */
3914
3915	/* Cpuid 0xc0000000: Centaur stuff.
3916	* Harmless, pass it thru. */
3917
3918	/* Cpuid 0xc0000001: Centaur features.
3919	* VIA: EAX - Family, model, stepping.
3920	* EDX - Centaur extended feature flags. Nothing interesting, except may
3921	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3922	* EBX, ECX - reserved.
3923	* We keep EAX but strips the rest.
3924	*/
3925	uSubLeaf = 0;
3926	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3927	{
3928	pCurLeaf->uEbx = 0;
3929	pCurLeaf->uEcx = 0;
3930	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3931	uSubLeaf++;
3932	}
3933
3934	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3935	* We only have fixed stale values, but should be harmless. */
3936
3937	/* Cpuid 0xc0000003: Reserved.
3938	* We zero this since we don't know what it may have been used for.
3939	*/
3940	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3941
3942	/* Cpuid 0xc0000004: Centaur Performance Info.
3943	* We only have fixed stale values, but should be harmless. */
3944
3945
3946	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3947	* We don't know these and what they mean, so remove them. */
3948	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3949	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3950
3951	return VINF_SUCCESS;
3952	#undef PORTABLE_DISABLE_FEATURE_BIT
3953	#undef PORTABLE_CLEAR_BITS_WHEN
3954	}
3955
3956
3957	/**
3958	* Reads a value in /CPUM/IsaExts/ node.
3959	*
3960	* @returns VBox status code (error message raised).
3961	* @param pVM The cross context VM structure. (For errors.)
3962	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3963	* @param pszValueName The value / extension name.
3964	* @param penmValue Where to return the choice.
3965	* @param enmDefault The default choice.
3966	*/
3967	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3968	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3969	{
3970	/*
3971	* Try integer encoding first.
3972	*/
3973	uint64_t uValue;
3974	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3975	if (RT_SUCCESS(rc))
3976	switch (uValue)
3977	{
3978	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3979	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3980	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3981	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3982	default:
3983	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3984	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3985	pszValueName, uValue);
3986	}
3987	/*
3988	* If missing, use default.
3989	*/
3990	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3991	*penmValue = enmDefault;
3992	else
3993	{
3994	if (rc == VERR_CFGM_NOT_INTEGER)
3995	{
3996	/*
3997	* Not an integer, try read it as a string.
3998	*/
3999	char szValue[32];
4000	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
4001	if (RT_SUCCESS(rc))
4002	{
4003	RTStrToLower(szValue);
4004	size_t cchValue = strlen(szValue);
4005	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
4006	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
4007	*penmValue = CPUMISAEXTCFG_DISABLED;
4008	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
4009	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
4010	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
4011	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
4012	else if (EQ("portable"))
4013	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
4014	else if (EQ("default") \|\| EQ("def"))
4015	*penmValue = enmDefault;
4016	else
4017	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
4018	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
4019	pszValueName, uValue);
4020	#undef EQ
4021	}
4022	}
4023	if (RT_FAILURE(rc))
4024	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
4025	}
4026	return VINF_SUCCESS;
4027	}
4028
4029
4030	/**
4031	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
4032	*
4033	* @returns VBox status code (error message raised).
4034	* @param pVM The cross context VM structure. (For errors.)
4035	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4036	* @param pszValueName The value / extension name.
4037	* @param penmValue Where to return the choice.
4038	* @param enmDefault The default choice.
4039	* @param fAllowed Allowed choice. Applied both to the result and to
4040	* the default value.
4041	*/
4042	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
4043	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
4044	{
4045	int rc;
4046	if (fAllowed)
4047	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4048	else
4049	{
4050	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
4051	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
4052	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
4053	*penmValue = CPUMISAEXTCFG_DISABLED;
4054	}
4055	return rc;
4056	}
4057
4058
4059	/**
4060	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
4061	*
4062	* @returns VBox status code (error message raised).
4063	* @param pVM The cross context VM structure. (For errors.)
4064	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4065	* @param pCpumCfg The /CPUM node (can be NULL).
4066	* @param pszValueName The value / extension name.
4067	* @param penmValue Where to return the choice.
4068	* @param enmDefault The default choice.
4069	*/
4070	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
4071	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
4072	{
4073	if (CFGMR3Exists(pCpumCfg, pszValueName))
4074	{
4075	if (!CFGMR3Exists(pIsaExts, pszValueName))
4076	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
4077	else
4078	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
4079	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
4080	pszValueName, pszValueName);
4081
4082	bool fLegacy;
4083	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
4084	if (RT_SUCCESS(rc))
4085	{
4086	*penmValue = fLegacy;
4087	return VINF_SUCCESS;
4088	}
4089	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
4090	}
4091
4092	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4093	}
4094
4095
4096	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
4097	{
4098	int rc;
4099
4100	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
4101	* When non-zero CPUID features that could cause portability issues will be
4102	* stripped. The higher the value the more features gets stripped. Higher
4103	* values should only be used when older CPUs are involved since it may
4104	* harm performance and maybe also cause problems with specific guests. */
4105	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
4106	AssertLogRelRCReturn(rc, rc);
4107
4108	/** @cfgm{/CPUM/GuestCpuName, string}
4109	* The name of the CPU we're to emulate. The default is the host CPU.
4110	* Note! CPUs other than "host" one is currently unsupported. */
4111	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
4112	AssertLogRelRCReturn(rc, rc);
4113
4114	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
4115	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
4116	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
4117	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
4118	*/
4119	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
4120	AssertLogRelRCReturn(rc, rc);
4121
4122	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
4123	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
4124	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
4125	* 64-bit linux guests which assume the presence of AMD performance counters
4126	* that we do not virtualize.
4127	*/
4128	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
4129	AssertLogRelRCReturn(rc, rc);
4130
4131	/** @cfgm{/CPUM/ForceVme, boolean, false}
4132	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
4133	* By default the flag is passed thru as is from the host CPU, except
4134	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
4135	* guests and DOS boxes in general.
4136	*/
4137	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
4138	AssertLogRelRCReturn(rc, rc);
4139
4140	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
4141	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
4142	* probably going to be a temporary hack, so don't depend on this.
4143	* The 1st byte of the value is the stepping, the 2nd byte value is the model
4144	* number and the 3rd byte value is the family, and the 4th value must be zero.
4145	*/
4146	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
4147	AssertLogRelRCReturn(rc, rc);
4148
4149	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
4150	* The last standard leaf to keep. The actual last value that is stored in EAX
4151	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
4152	* removed. (This works independently of and differently from NT4LeafLimit.)
4153	* The default is usually set to what we're able to reasonably sanitize.
4154	*/
4155	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
4156	AssertLogRelRCReturn(rc, rc);
4157
4158	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
4159	* The last extended leaf to keep. The actual last value that is stored in EAX
4160	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
4161	* leaf are removed. The default is set to what we're able to sanitize.
4162	*/
4163	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
4164	AssertLogRelRCReturn(rc, rc);
4165
4166	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
4167	* The last extended leaf to keep. The actual last value that is stored in EAX
4168	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
4169	* leaf are removed. The default is set to what we're able to sanitize.
4170	*/
4171	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
4172	AssertLogRelRCReturn(rc, rc);
4173
4174	bool fQueryNestedHwvirt = false
4175	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4176	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4177	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON
4178	#endif
4179	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4180	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
4181	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA
4182	#endif
4183	;
4184	if (fQueryNestedHwvirt)
4185	{
4186	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
4187	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
4188	* The default is false, and when enabled requires a 64-bit CPU with support for
4189	* nested-paging and AMD-V or unrestricted guest mode.
4190	*/
4191	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
4192	AssertLogRelRCReturn(rc, rc);
4193	if ( pConfig->fNestedHWVirt
4194	&& !fNestedPagingAndFullGuestExec)
4195	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4196	"Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
4197
4198	/** @todo Think about enabling this later with NEM/KVM. */
4199	if ( pConfig->fNestedHWVirt
4200	&& VM_IS_NEM_ENABLED(pVM))
4201	{
4202	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
4203	pConfig->fNestedHWVirt = false;
4204	}
4205
4206	/** @cfgm{/CPUM/NestedVmxPreemptTimer, bool, true}
4207	* Whether to expose the VMX-preemption timer feature to the guest (if also
4208	* supported by the host hardware). The default is true, and when disabled will
4209	* prevent exposing the VMX-preemption timer feature to the guest even if the host
4210	* supports it.
4211	*/
4212	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxPreemptTimer", &pVM->cpum.s.fNestedVmxPreemptTimer, true);
4213	AssertLogRelRCReturn(rc, rc);
4214	}
4215
4216	/*
4217	* Instruction Set Architecture (ISA) Extensions.
4218	*/
4219	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
4220	if (pIsaExts)
4221	{
4222	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
4223	"CMPXCHG16B"
4224	"\|MONITOR"
4225	"\|MWaitExtensions"
4226	"\|SSE4.1"
4227	"\|SSE4.2"
4228	"\|XSAVE"
4229	"\|AVX"
4230	"\|AVX2"
4231	"\|AESNI"
4232	"\|PCLMUL"
4233	"\|POPCNT"
4234	"\|MOVBE"
4235	"\|RDRAND"
4236	"\|RDSEED"
4237	"\|CLFLUSHOPT"
4238	"\|FSGSBASE"
4239	"\|PCID"
4240	"\|INVPCID"
4241	"\|FlushCmdMsr"
4242	"\|ABM"
4243	"\|SSE4A"
4244	"\|MISALNSSE"
4245	"\|3DNOWPRF"
4246	"\|AXMMX"
4247	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
4248	if (RT_FAILURE(rc))
4249	return rc;
4250	}
4251
4252	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, true}
4253	* Expose CMPXCHG16B to the guest if available. All host CPUs which support
4254	* hardware virtualization have it.
4255	*/
4256	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, true);
4257	AssertLogRelRCReturn(rc, rc);
4258
4259	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4260	* Expose MONITOR/MWAIT instructions to the guest.
4261	*/
4262	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4263	AssertLogRelRCReturn(rc, rc);
4264
4265	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4266	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4267	* break on interrupt feature (bit 1).
4268	*/
4269	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4270	AssertLogRelRCReturn(rc, rc);
4271
4272	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4273	* Expose SSE4.1 to the guest if available.
4274	*/
4275	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4276	AssertLogRelRCReturn(rc, rc);
4277
4278	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4279	* Expose SSE4.2 to the guest if available.
4280	*/
4281	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4282	AssertLogRelRCReturn(rc, rc);
4283
4284	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4285	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4286	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor;
4287	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4288
4289	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4290	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4291	* default is to only expose this to VMs with nested paging and AMD-V or
4292	* unrestricted guest execution mode. Not possible to force this one without
4293	* host support at the moment.
4294	*/
4295	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4296	fMayHaveXSave /fAllowed/);
4297	AssertLogRelRCReturn(rc, rc);
4298
4299	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4300	* Expose the AVX instruction set extensions to the guest if available and
4301	* XSAVE is exposed too. For the time being the default is to only expose this
4302	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4303	*/
4304	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4305	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4306	AssertLogRelRCReturn(rc, rc);
4307
4308	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4309	* Expose the AVX2 instruction set extensions to the guest if available and
4310	* XSAVE is exposed too. For the time being the default is to only expose this
4311	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4312	*/
4313	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4314	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4315	AssertLogRelRCReturn(rc, rc);
4316
4317	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4318	* Whether to expose the AES instructions to the guest. For the time being the
4319	* default is to only do this for VMs with nested paging and AMD-V or
4320	* unrestricted guest mode.
4321	*/
4322	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4323	AssertLogRelRCReturn(rc, rc);
4324
4325	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4326	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4327	* being the default is to only do this for VMs with nested paging and AMD-V or
4328	* unrestricted guest mode.
4329	*/
4330	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4331	AssertLogRelRCReturn(rc, rc);
4332
4333	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4334	* Whether to expose the POPCNT instructions to the guest. For the time
4335	* being the default is to only do this for VMs with nested paging and AMD-V or
4336	* unrestricted guest mode.
4337	*/
4338	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4339	AssertLogRelRCReturn(rc, rc);
4340
4341	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4342	* Whether to expose the MOVBE instructions to the guest. For the time
4343	* being the default is to only do this for VMs with nested paging and AMD-V or
4344	* unrestricted guest mode.
4345	*/
4346	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4347	AssertLogRelRCReturn(rc, rc);
4348
4349	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4350	* Whether to expose the RDRAND instructions to the guest. For the time being
4351	* the default is to only do this for VMs with nested paging and AMD-V or
4352	* unrestricted guest mode.
4353	*/
4354	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4355	AssertLogRelRCReturn(rc, rc);
4356
4357	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4358	* Whether to expose the RDSEED instructions to the guest. For the time being
4359	* the default is to only do this for VMs with nested paging and AMD-V or
4360	* unrestricted guest mode.
4361	*/
4362	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4363	AssertLogRelRCReturn(rc, rc);
4364
4365	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4366	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4367	* being the default is to only do this for VMs with nested paging and AMD-V or
4368	* unrestricted guest mode.
4369	*/
4370	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4371	AssertLogRelRCReturn(rc, rc);
4372
4373	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4374	* Whether to expose the read/write FSGSBASE instructions to the guest.
4375	*/
4376	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4377	AssertLogRelRCReturn(rc, rc);
4378
4379	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4380	* Whether to expose the PCID feature to the guest.
4381	*/
4382	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4383	AssertLogRelRCReturn(rc, rc);
4384
4385	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4386	* Whether to expose the INVPCID instruction to the guest.
4387	*/
4388	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4389	AssertLogRelRCReturn(rc, rc);
4390
4391	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
4392	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
4393	*/
4394	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4395	AssertLogRelRCReturn(rc, rc);
4396
4397	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
4398	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
4399	* the guest. Requires FlushCmdMsr to be present too.
4400	*/
4401	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4402	AssertLogRelRCReturn(rc, rc);
4403
4404	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
4405	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
4406	*/
4407	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4408	AssertLogRelRCReturn(rc, rc);
4409
4410
4411	/* AMD: */
4412
4413	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4414	* Whether to expose the AMD ABM instructions to the guest. For the time
4415	* being the default is to only do this for VMs with nested paging and AMD-V or
4416	* unrestricted guest mode.
4417	*/
4418	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4419	AssertLogRelRCReturn(rc, rc);
4420
4421	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4422	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4423	* being the default is to only do this for VMs with nested paging and AMD-V or
4424	* unrestricted guest mode.
4425	*/
4426	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4427	AssertLogRelRCReturn(rc, rc);
4428
4429	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4430	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4431	* the time being the default is to only do this for VMs with nested paging and
4432	* AMD-V or unrestricted guest mode.
4433	*/
4434	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4435	AssertLogRelRCReturn(rc, rc);
4436
4437	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4438	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4439	* For the time being the default is to only do this for VMs with nested paging
4440	* and AMD-V or unrestricted guest mode.
4441	*/
4442	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4443	AssertLogRelRCReturn(rc, rc);
4444
4445	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4446	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4447	* the default is to only do this for VMs with nested paging and AMD-V or
4448	* unrestricted guest mode.
4449	*/
4450	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4451	AssertLogRelRCReturn(rc, rc);
4452
4453	return VINF_SUCCESS;
4454	}
4455
4456
4457	/**
4458	* Initializes the emulated CPU's CPUID & MSR information.
4459	*
4460	* @returns VBox status code.
4461	* @param pVM The cross context VM structure.
4462	* @param pHostMsrs Pointer to the host MSRs.
4463	*/
4464	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
4465	{
4466	Assert(pHostMsrs);
4467
4468	PCPUM pCpum = &pVM->cpum.s;
4469	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4470
4471	/*
4472	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4473	* on construction and manage everything from here on.
4474	*/
4475	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4476	{
4477	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4478	pVCpu->cpum.s.fCpuIdApicFeatureVisible = true;
4479	}
4480
4481	/*
4482	* Read the configuration.
4483	*/
4484	CPUMCPUIDCONFIG Config;
4485	RT_ZERO(Config);
4486
4487	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4488	AssertRCReturn(rc, rc);
4489
4490	/*
4491	* Get the guest CPU data from the database and/or the host.
4492	*
4493	* The CPUID and MSRs are currently living on the regular heap to avoid
4494	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4495	* API for the hyper heap). This means special cleanup considerations.
4496	*/
4497	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4498	if (RT_FAILURE(rc))
4499	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4500	? VMSetError(pVM, rc, RT_SRC_POS,
4501	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4502	: rc;
4503
4504	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4505	{
4506	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4507	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4508	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4509	}
4510	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4511
4512	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4513	* Overrides the guest MSRs.
4514	*/
4515	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4516
4517	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4518	* Overrides the CPUID leaf values (from the host CPU usually) used for
4519	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4520	* values when moving a VM to a different machine. Another use is restricting
4521	* (or extending) the feature set exposed to the guest. */
4522	if (RT_SUCCESS(rc))
4523	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4524
4525	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4526	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4527	"Found unsupported configuration node '/CPUM/CPUID/'. "
4528	"Please use IMachine::setCPUIDLeaf() instead.");
4529
4530	CPUMMSRS GuestMsrs;
4531	RT_ZERO(GuestMsrs);
4532
4533	/*
4534	* Pre-explode the CPUID info.
4535	*/
4536	if (RT_SUCCESS(rc))
4537	{
4538	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
4539	&pCpum->GuestFeatures);
4540	}
4541
4542	/*
4543	* Sanitize the cpuid information passed on to the guest.
4544	*/
4545	if (RT_SUCCESS(rc))
4546	{
4547	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4548	if (RT_SUCCESS(rc))
4549	{
4550	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4551	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4552	}
4553	}
4554
4555	/*
4556	* Setup MSRs introduced in microcode updates or that are otherwise not in
4557	* the CPU profile, but are advertised in the CPUID info we just sanitized.
4558	*/
4559	if (RT_SUCCESS(rc))
4560	rc = cpumR3MsrReconcileWithCpuId(pVM);
4561	/*
4562	* MSR fudging.
4563	*/
4564	if (RT_SUCCESS(rc))
4565	{
4566	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4567	* Fudges some common MSRs if not present in the selected CPU database entry.
4568	* This is for trying to keep VMs running when moved between different hosts
4569	* and different CPU vendors. */
4570	bool fEnable;
4571	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4572	if (RT_SUCCESS(rc) && fEnable)
4573	{
4574	rc = cpumR3MsrApplyFudge(pVM);
4575	AssertLogRelRC(rc);
4576	}
4577	}
4578	if (RT_SUCCESS(rc))
4579	{
4580	/*
4581	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4582	* guest CPU features again.
4583	*/
4584	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4585	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4586	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
4587	RTMemFree(pvFree);
4588
4589	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4590	int rc2 = MMHyperDupMem(pVM, pvFree,
4591	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4592	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4593	RTMemFree(pvFree);
4594	AssertLogRelRCReturn(rc1, rc1);
4595	AssertLogRelRCReturn(rc2, rc2);
4596
4597	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4598
4599	/*
4600	* Finally, initialize guest VMX MSRs.
4601	*
4602	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
4603	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
4604	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
4605	*/
4606	if (pVM->cpum.s.GuestFeatures.fVmx)
4607	{
4608	Assert(Config.fNestedHWVirt);
4609	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
4610
4611	/* Copy MSRs to all VCPUs */
4612	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
4613	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4614	{
4615	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4616	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
4617	}
4618	}
4619
4620	/*
4621	* Some more configuration that we're applying at the end of everything
4622	* via the CPUMR3SetGuestCpuIdFeature API.
4623	*/
4624
4625	/* Check if PAE was explicitely enabled by the user. */
4626	bool fEnable;
4627	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4628	AssertRCReturn(rc, rc);
4629	if (fEnable)
4630	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4631
4632	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4633	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4634	AssertRCReturn(rc, rc);
4635	if (fEnable)
4636	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4637
4638	/* Check if speculation control is enabled. */
4639	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4640	AssertRCReturn(rc, rc);
4641	if (fEnable)
4642	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4643	else
4644	{
4645	/*
4646	* Set the "SSBD-not-needed" flag to work around a bug in some Linux kernels when the VIRT_SPEC_CTL
4647	* feature is not exposed on AMD CPUs and there is only 1 vCPU configured.
4648	* This was observed with kernel "4.15.0-29-generic #31~16.04.1-Ubuntu" but more versions are likely affected.
4649	*
4650	* The kernel doesn't initialize a lock and causes a NULL pointer exception later on when configuring SSBD:
4651	* EIP: _raw_spin_lock+0x14/0x30
4652	* EFLAGS: 00010046 CPU: 0
4653	* EAX: 00000000 EBX: 00000001 ECX: 00000004 EDX: 00000000
4654	* ESI: 00000000 EDI: 00000000 EBP: ee023f1c ESP: ee023f18
4655	* DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
4656	* CR0: 80050033 CR2: 00000004 CR3: 3671c180 CR4: 000006f0
4657	* Call Trace:
4658	* speculative_store_bypass_update+0x8e/0x180
4659	* ssb_prctl_set+0xc0/0xe0
4660	* arch_seccomp_spec_mitigate+0x1d/0x20
4661	* do_seccomp+0x3cb/0x610
4662	* SyS_seccomp+0x16/0x20
4663	* do_fast_syscall_32+0x7f/0x1d0
4664	* entry_SYSENTER_32+0x4e/0x7c
4665	*
4666	* The lock would've been initialized in process.c:speculative_store_bypass_ht_init() called from two places in smpboot.c.
4667	* First when a secondary CPU is started and second in native_smp_prepare_cpus() which is not called in a single vCPU environment.
4668	*
4669	* As spectre control features are completely disabled anyway when we arrived here there is no harm done in informing the
4670	* guest to not even try.
4671	*/
4672	if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4673	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
4674	{
4675	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x80000008), 0);
4676	if (pLeaf)
4677	{
4678	pLeaf->uEbx \|= X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED;
4679	LogRel(("CPUM: Set SSBD not required flag for AMD to work around some buggy Linux kernels!\n"));
4680	}
4681	}
4682	}
4683
4684	return VINF_SUCCESS;
4685	}
4686
4687	/*
4688	* Failed before switching to hyper heap.
4689	*/
4690	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4691	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4692	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4693	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4694	return rc;
4695	}
4696
4697
4698	/**
4699	* Sets a CPUID feature bit during VM initialization.
4700	*
4701	* Since the CPUID feature bits are generally related to CPU features, other
4702	* CPUM configuration like MSRs can also be modified by calls to this API.
4703	*
4704	* @param pVM The cross context VM structure.
4705	* @param enmFeature The feature to set.
4706	*/
4707	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4708	{
4709	PCPUMCPUIDLEAF pLeaf;
4710	PCPUMMSRRANGE pMsrRange;
4711
4712	switch (enmFeature)
4713	{
4714	/*
4715	* Set the APIC bit in both feature masks.
4716	*/
4717	case CPUMCPUIDFEATURE_APIC:
4718	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4719	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4720	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4721
4722	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4723	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4724	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4725
4726	pVM->cpum.s.GuestFeatures.fApic = 1;
4727
4728	/* Make sure we've got the APICBASE MSR present. */
4729	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4730	if (!pMsrRange)
4731	{
4732	static CPUMMSRRANGE const s_ApicBase =
4733	{
4734	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4735	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4736	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4737	/.szName = / "IA32_APIC_BASE"
4738	};
4739	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4740	AssertLogRelRC(rc);
4741	}
4742
4743	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4744	break;
4745
4746	/*
4747	* Set the x2APIC bit in the standard feature mask.
4748	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4749	*/
4750	case CPUMCPUIDFEATURE_X2APIC:
4751	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4752	if (pLeaf)
4753	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4754	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4755
4756	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4757	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4758	if (pMsrRange)
4759	{
4760	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4761	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4762	}
4763
4764	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4765	break;
4766
4767	/*
4768	* Set the sysenter/sysexit bit in the standard feature mask.
4769	* Assumes the caller knows what it's doing! (host must support these)
4770	*/
4771	case CPUMCPUIDFEATURE_SEP:
4772	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4773	{
4774	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4775	return;
4776	}
4777
4778	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4779	if (pLeaf)
4780	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4781	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4782	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4783	break;
4784
4785	/*
4786	* Set the syscall/sysret bit in the extended feature mask.
4787	* Assumes the caller knows what it's doing! (host must support these)
4788	*/
4789	case CPUMCPUIDFEATURE_SYSCALL:
4790	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4791	if ( !pLeaf
4792	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4793	{
4794	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4795	return;
4796	}
4797
4798	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4799	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4800	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4801	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4802	break;
4803
4804	/*
4805	* Set the PAE bit in both feature masks.
4806	* Assumes the caller knows what it's doing! (host must support these)
4807	*/
4808	case CPUMCPUIDFEATURE_PAE:
4809	if (!pVM->cpum.s.HostFeatures.fPae)
4810	{
4811	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4812	return;
4813	}
4814
4815	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4816	if (pLeaf)
4817	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4818
4819	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4820	if ( pLeaf
4821	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4822	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
4823	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4824
4825	pVM->cpum.s.GuestFeatures.fPae = 1;
4826	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4827	break;
4828
4829	/*
4830	* Set the LONG MODE bit in the extended feature mask.
4831	* Assumes the caller knows what it's doing! (host must support these)
4832	*/
4833	case CPUMCPUIDFEATURE_LONG_MODE:
4834	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4835	if ( !pLeaf
4836	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4837	{
4838	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4839	return;
4840	}
4841
4842	/* Valid for both Intel and AMD. */
4843	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4844	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4845	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
4846	if (pVM->cpum.s.GuestFeatures.fVmx)
4847	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4848	{
4849	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4850	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic &= ~VMX_BASIC_PHYSADDR_WIDTH_32BIT;
4851	}
4852	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4853	break;
4854
4855	/*
4856	* Set the NX/XD bit in the extended feature mask.
4857	* Assumes the caller knows what it's doing! (host must support these)
4858	*/
4859	case CPUMCPUIDFEATURE_NX:
4860	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4861	if ( !pLeaf
4862	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4863	{
4864	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4865	return;
4866	}
4867
4868	/* Valid for both Intel and AMD. */
4869	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4870	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4871	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4872	break;
4873
4874
4875	/*
4876	* Set the LAHF/SAHF support in 64-bit mode.
4877	* Assumes the caller knows what it's doing! (host must support this)
4878	*/
4879	case CPUMCPUIDFEATURE_LAHF:
4880	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4881	if ( !pLeaf
4882	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4883	{
4884	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4885	return;
4886	}
4887
4888	/* Valid for both Intel and AMD. */
4889	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4890	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4891	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4892	break;
4893
4894	/*
4895	* Set the page attribute table bit. This is alternative page level
4896	* cache control that doesn't much matter when everything is
4897	* virtualized, though it may when passing thru device memory.
4898	*/
4899	case CPUMCPUIDFEATURE_PAT:
4900	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4901	if (pLeaf)
4902	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4903
4904	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4905	if ( pLeaf
4906	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4907	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
4908	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4909
4910	pVM->cpum.s.GuestFeatures.fPat = 1;
4911	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4912	break;
4913
4914	/*
4915	* Set the RDTSCP support bit.
4916	* Assumes the caller knows what it's doing! (host must support this)
4917	*/
4918	case CPUMCPUIDFEATURE_RDTSCP:
4919	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4920	if ( !pLeaf
4921	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4922	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4923	{
4924	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4925	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4926	return;
4927	}
4928
4929	/* Valid for both Intel and AMD. */
4930	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4931	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4932	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4933	break;
4934
4935	/*
4936	* Set the Hypervisor Present bit in the standard feature mask.
4937	*/
4938	case CPUMCPUIDFEATURE_HVP:
4939	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4940	if (pLeaf)
4941	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4942	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4943	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4944	break;
4945
4946	/*
4947	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4948	* This currently includes the Present bit and MWAITBREAK bit as well.
4949	*/
4950	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4951	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4952	if ( !pLeaf
4953	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4954	{
4955	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4956	return;
4957	}
4958
4959	/* Valid for both Intel and AMD. */
4960	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4961	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4962	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4963	break;
4964
4965	/*
4966	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
4967	* on Intel CPUs, and different on AMDs.
4968	*/
4969	case CPUMCPUIDFEATURE_SPEC_CTRL:
4970	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4971	{
4972	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4973	if ( !pLeaf
4974	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
4975	{
4976	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4977	return;
4978	}
4979
4980	/* The feature can be enabled. Let's see what we can actually do. */
4981	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4982
4983	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4984	if (pVM->cpum.s.HostFeatures.fIbrs)
4985	{
4986	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4987	pVM->cpum.s.GuestFeatures.fIbrs = 1;
4988	if (pVM->cpum.s.HostFeatures.fStibp)
4989	{
4990	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4991	pVM->cpum.s.GuestFeatures.fStibp = 1;
4992	}
4993
4994	/* Make sure we have the speculation control MSR... */
4995	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4996	if (!pMsrRange)
4997	{
4998	static CPUMMSRRANGE const s_SpecCtrl =
4999	{
5000	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
5001	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
5002	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
5003	/.szName = / "IA32_SPEC_CTRL"
5004	};
5005	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
5006	AssertLogRelRC(rc);
5007	}
5008
5009	/* ... and the predictor command MSR. */
5010	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
5011	if (!pMsrRange)
5012	{
5013	/** @todo incorrect fWrGpMask. */
5014	static CPUMMSRRANGE const s_SpecCtrl =
5015	{
5016	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
5017	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
5018	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
5019	/.szName = / "IA32_PRED_CMD"
5020	};
5021	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
5022	AssertLogRelRC(rc);
5023	}
5024
5025	}
5026
5027	if (pVM->cpum.s.HostFeatures.fArchCap)
5028	{
5029	/* Install the architectural capabilities MSR. */
5030	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
5031	if (!pMsrRange)
5032	{
5033	static CPUMMSRRANGE const s_ArchCaps =
5034	{
5035	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
5036	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
5037	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
5038	/.szName = / "IA32_ARCH_CAPABILITIES"
5039	};
5040	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
5041	AssertLogRelRC(rc);
5042	}
5043
5044	/* Advertise IBRS_ALL if present at this point... */
5045	if (pVM->cpum.s.HostFeatures.fArchCap & MSR_IA32_ARCH_CAP_F_IBRS_ALL)
5046	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps \|= MSR_IA32_ARCH_CAP_F_IBRS_ALL);
5047	}
5048
5049	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
5050	}
5051	else if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
5052	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
5053	{
5054	/* The precise details of AMD's implementation are not yet clear. */
5055	}
5056	break;
5057
5058	default:
5059	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5060	break;
5061	}
5062
5063	/** @todo can probably kill this as this API is now init time only... */
5064	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5065	{
5066	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5067	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5068	}
5069	}
5070
5071
5072	/**
5073	* Queries a CPUID feature bit.
5074	*
5075	* @returns boolean for feature presence
5076	* @param pVM The cross context VM structure.
5077	* @param enmFeature The feature to query.
5078	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
5079	*/
5080	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5081	{
5082	switch (enmFeature)
5083	{
5084	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
5085	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
5086	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
5087	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
5088	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
5089	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
5090	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
5091	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
5092	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
5093	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
5094	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
5095	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
5096	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
5097
5098	case CPUMCPUIDFEATURE_INVALID:
5099	case CPUMCPUIDFEATURE_32BIT_HACK:
5100	break;
5101	}
5102	AssertFailed();
5103	return false;
5104	}
5105
5106
5107	/**
5108	* Clears a CPUID feature bit.
5109	*
5110	* @param pVM The cross context VM structure.
5111	* @param enmFeature The feature to clear.
5112	*
5113	* @deprecated Probably better to default the feature to disabled and only allow
5114	* setting (enabling) it during construction.
5115	*/
5116	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5117	{
5118	PCPUMCPUIDLEAF pLeaf;
5119	switch (enmFeature)
5120	{
5121	case CPUMCPUIDFEATURE_APIC:
5122	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
5123	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5124	if (pLeaf)
5125	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
5126
5127	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5128	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
5129	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
5130
5131	pVM->cpum.s.GuestFeatures.fApic = 0;
5132	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
5133	break;
5134
5135	case CPUMCPUIDFEATURE_X2APIC:
5136	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
5137	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5138	if (pLeaf)
5139	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
5140	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
5141	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
5142	break;
5143
5144	case CPUMCPUIDFEATURE_PAE:
5145	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5146	if (pLeaf)
5147	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
5148
5149	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5150	if ( pLeaf
5151	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
5152	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
5153	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
5154
5155	pVM->cpum.s.GuestFeatures.fPae = 0;
5156	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
5157	break;
5158
5159	case CPUMCPUIDFEATURE_PAT:
5160	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5161	if (pLeaf)
5162	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
5163
5164	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5165	if ( pLeaf
5166	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
5167	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
5168	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
5169
5170	pVM->cpum.s.GuestFeatures.fPat = 0;
5171	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
5172	break;
5173
5174	case CPUMCPUIDFEATURE_LONG_MODE:
5175	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5176	if (pLeaf)
5177	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
5178	pVM->cpum.s.GuestFeatures.fLongMode = 0;
5179	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
5180	if (pVM->cpum.s.GuestFeatures.fVmx)
5181	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5182	{
5183	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5184	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic \|= VMX_BASIC_PHYSADDR_WIDTH_32BIT;
5185	}
5186	break;
5187
5188	case CPUMCPUIDFEATURE_LAHF:
5189	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5190	if (pLeaf)
5191	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
5192	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
5193	break;
5194
5195	case CPUMCPUIDFEATURE_RDTSCP:
5196	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5197	if (pLeaf)
5198	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
5199	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
5200	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
5201	break;
5202
5203	case CPUMCPUIDFEATURE_HVP:
5204	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5205	if (pLeaf)
5206	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
5207	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
5208	break;
5209
5210	case CPUMCPUIDFEATURE_MWAIT_EXTS:
5211	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
5212	if (pLeaf)
5213	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
5214	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
5215	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
5216	break;
5217
5218	case CPUMCPUIDFEATURE_SPEC_CTRL:
5219	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
5220	if (pLeaf)
5221	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
5222	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL);
5223	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
5224	break;
5225
5226	default:
5227	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5228	break;
5229	}
5230
5231	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5232	{
5233	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5234	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5235	}
5236	}
5237
5238
5239
5240	/*
5241	*
5242	*
5243	* Saved state related code.
5244	* Saved state related code.
5245	* Saved state related code.
5246	*
5247	*
5248	*/
5249
5250	/**
5251	* Called both in pass 0 and the final pass.
5252	*
5253	* @param pVM The cross context VM structure.
5254	* @param pSSM The saved state handle.
5255	*/
5256	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
5257	{
5258	/*
5259	* Save all the CPU ID leaves.
5260	*/
5261	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
5262	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5263	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
5264	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5265
5266	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5267
5268	/*
5269	* Save a good portion of the raw CPU IDs as well as they may come in
5270	* handy when validating features for raw mode.
5271	*/
5272	CPUMCPUID aRawStd[16];
5273	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
5274	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5275	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
5276	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
5277
5278	CPUMCPUID aRawExt[32];
5279	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
5280	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5281	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
5282	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
5283	}
5284
5285
5286	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5287	{
5288	uint32_t cCpuIds;
5289	int rc = SSMR3GetU32(pSSM, &cCpuIds);
5290	if (RT_SUCCESS(rc))
5291	{
5292	if (cCpuIds < 64)
5293	{
5294	for (uint32_t i = 0; i < cCpuIds; i++)
5295	{
5296	CPUMCPUID CpuId;
5297	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
5298	if (RT_FAILURE(rc))
5299	break;
5300
5301	CPUMCPUIDLEAF NewLeaf;
5302	NewLeaf.uLeaf = uBase + i;
5303	NewLeaf.uSubLeaf = 0;
5304	NewLeaf.fSubLeafMask = 0;
5305	NewLeaf.uEax = CpuId.uEax;
5306	NewLeaf.uEbx = CpuId.uEbx;
5307	NewLeaf.uEcx = CpuId.uEcx;
5308	NewLeaf.uEdx = CpuId.uEdx;
5309	NewLeaf.fFlags = 0;
5310	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
5311	}
5312	}
5313	else
5314	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5315	}
5316	if (RT_FAILURE(rc))
5317	{
5318	RTMemFree(*ppaLeaves);
5319	*ppaLeaves = NULL;
5320	*pcLeaves = 0;
5321	}
5322	return rc;
5323	}
5324
5325
5326	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5327	{
5328	*ppaLeaves = NULL;
5329	*pcLeaves = 0;
5330
5331	int rc;
5332	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
5333	{
5334	/*
5335	* The new format. Starts by declaring the leave size and count.
5336	*/
5337	uint32_t cbLeaf;
5338	SSMR3GetU32(pSSM, &cbLeaf);
5339	uint32_t cLeaves;
5340	rc = SSMR3GetU32(pSSM, &cLeaves);
5341	if (RT_SUCCESS(rc))
5342	{
5343	if (cbLeaf == sizeof(**ppaLeaves))
5344	{
5345	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
5346	{
5347	/*
5348	* Load the leaves one by one.
5349	*
5350	* The uPrev stuff is a kludge for working around a week worth of bad saved
5351	* states during the CPUID revamp in March 2015. We saved too many leaves
5352	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
5353	* garbage entires at the end of the array when restoring. We also had
5354	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
5355	* this kludge doesn't deal correctly with that, but who cares...
5356	*/
5357	uint32_t uPrev = 0;
5358	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
5359	{
5360	CPUMCPUIDLEAF Leaf;
5361	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5362	if (RT_SUCCESS(rc))
5363	{
5364	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5365	\|\| Leaf.uLeaf >= uPrev)
5366	{
5367	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5368	uPrev = Leaf.uLeaf;
5369	}
5370	else
5371	uPrev = UINT32_MAX;
5372	}
5373	}
5374	}
5375	else
5376	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5377	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5378	}
5379	else
5380	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5381	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5382	}
5383	}
5384	else
5385	{
5386	/*
5387	* The old format with its three inflexible arrays.
5388	*/
5389	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5390	if (RT_SUCCESS(rc))
5391	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5392	if (RT_SUCCESS(rc))
5393	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5394	if (RT_SUCCESS(rc))
5395	{
5396	/*
5397	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5398	*/
5399	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5400	if ( pLeaf
5401	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5402	{
5403	CPUMCPUIDLEAF Leaf;
5404	Leaf.uLeaf = 4;
5405	Leaf.fSubLeafMask = UINT32_MAX;
5406	Leaf.uSubLeaf = 0;
5407	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5408	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5409	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5410	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5411	\| UINT32_C(63); /* system coherency line size - 1 */
5412	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5413	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5414	\| (UINT32_C(1) << 5) /* cache level */
5415	\| UINT32_C(1); /* cache type (data) */
5416	Leaf.fFlags = 0;
5417	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5418	if (RT_SUCCESS(rc))
5419	{
5420	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5421	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5422	}
5423	if (RT_SUCCESS(rc))
5424	{
5425	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5426	Leaf.uEcx = 4095; /* sets - 1 */
5427	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5428	Leaf.uEbx \|= UINT32_C(23) << 22;
5429	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5430	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5431	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5432	Leaf.uEax \|= UINT32_C(2) << 5;
5433	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5434	}
5435	}
5436	}
5437	}
5438	return rc;
5439	}
5440
5441
5442	/**
5443	* Loads the CPU ID leaves saved by pass 0, inner worker.
5444	*
5445	* @returns VBox status code.
5446	* @param pVM The cross context VM structure.
5447	* @param pSSM The saved state handle.
5448	* @param uVersion The format version.
5449	* @param paLeaves Guest CPUID leaves loaded from the state.
5450	* @param cLeaves The number of leaves in @a paLeaves.
5451	* @param pMsrs The guest MSRs.
5452	*/
5453	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
5454	{
5455	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5456
5457	/*
5458	* Continue loading the state into stack buffers.
5459	*/
5460	CPUMCPUID GuestDefCpuId;
5461	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5462	AssertRCReturn(rc, rc);
5463
5464	CPUMCPUID aRawStd[16];
5465	uint32_t cRawStd;
5466	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5467	if (cRawStd > RT_ELEMENTS(aRawStd))
5468	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5469	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5470	AssertRCReturn(rc, rc);
5471	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5472	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5473
5474	CPUMCPUID aRawExt[32];
5475	uint32_t cRawExt;
5476	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5477	if (cRawExt > RT_ELEMENTS(aRawExt))
5478	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5479	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5480	AssertRCReturn(rc, rc);
5481	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5482	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5483
5484	/*
5485	* Get the raw CPU IDs for the current host.
5486	*/
5487	CPUMCPUID aHostRawStd[16];
5488	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5489	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5490
5491	CPUMCPUID aHostRawExt[32];
5492	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5493	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5494	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5495
5496	/*
5497	* Get the host and guest overrides so we don't reject the state because
5498	* some feature was enabled thru these interfaces.
5499	* Note! We currently only need the feature leaves, so skip rest.
5500	*/
5501	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5502	CPUMCPUID aHostOverrideStd[2];
5503	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5504	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5505
5506	CPUMCPUID aHostOverrideExt[2];
5507	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5508	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5509
5510	/*
5511	* This can be skipped.
5512	*/
5513	bool fStrictCpuIdChecks;
5514	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5515
5516	/*
5517	* Define a bunch of macros for simplifying the santizing/checking code below.
5518	*/
5519	/* Generic expression + failure message. */
5520	#define CPUID_CHECK_RET(expr, fmt) \
5521	do { \
5522	if (!(expr)) \
5523	{ \
5524	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5525	if (fStrictCpuIdChecks) \
5526	{ \
5527	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5528	RTStrFree(pszMsg); \
5529	return rcCpuid; \
5530	} \
5531	LogRel(("CPUM: %s\n", pszMsg)); \
5532	RTStrFree(pszMsg); \
5533	} \
5534	} while (0)
5535	#define CPUID_CHECK_WRN(expr, fmt) \
5536	do { \
5537	if (!(expr)) \
5538	LogRel(fmt); \
5539	} while (0)
5540
5541	/* For comparing two values and bitch if they differs. */
5542	#define CPUID_CHECK2_RET(what, host, saved) \
5543	do { \
5544	if ((host) != (saved)) \
5545	{ \
5546	if (fStrictCpuIdChecks) \
5547	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5548	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5549	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5550	} \
5551	} while (0)
5552	#define CPUID_CHECK2_WRN(what, host, saved) \
5553	do { \
5554	if ((host) != (saved)) \
5555	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5556	} while (0)
5557
5558	/* For checking raw cpu features (raw mode). */
5559	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5560	do { \
5561	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5562	{ \
5563	if (fStrictCpuIdChecks) \
5564	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5565	N_(#bit " mismatch: host=%d saved=%d"), \
5566	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5567	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5568	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5569	} \
5570	} while (0)
5571	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5572	do { \
5573	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5574	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5575	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5576	} while (0)
5577	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5578
5579	/* For checking guest features. */
5580	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5581	do { \
5582	if ( (aGuestCpuId##set [1].reg & bit) \
5583	&& !(aHostRaw##set [1].reg & bit) \
5584	&& !(aHostOverride##set [1].reg & bit) \
5585	) \
5586	{ \
5587	if (fStrictCpuIdChecks) \
5588	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5589	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5590	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5591	} \
5592	} while (0)
5593	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5594	do { \
5595	if ( (aGuestCpuId##set [1].reg & bit) \
5596	&& !(aHostRaw##set [1].reg & bit) \
5597	&& !(aHostOverride##set [1].reg & bit) \
5598	) \
5599	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5600	} while (0)
5601	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5602	do { \
5603	if ( (aGuestCpuId##set [1].reg & bit) \
5604	&& !(aHostRaw##set [1].reg & bit) \
5605	&& !(aHostOverride##set [1].reg & bit) \
5606	) \
5607	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5608	} while (0)
5609	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5610
5611	/* For checking guest features if AMD guest CPU. */
5612	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5613	do { \
5614	if ( (aGuestCpuId##set [1].reg & bit) \
5615	&& fGuestAmd \
5616	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5617	&& !(aHostOverride##set [1].reg & bit) \
5618	) \
5619	{ \
5620	if (fStrictCpuIdChecks) \
5621	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5622	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5623	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5624	} \
5625	} while (0)
5626	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5627	do { \
5628	if ( (aGuestCpuId##set [1].reg & bit) \
5629	&& fGuestAmd \
5630	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5631	&& !(aHostOverride##set [1].reg & bit) \
5632	) \
5633	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5634	} while (0)
5635	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5636	do { \
5637	if ( (aGuestCpuId##set [1].reg & bit) \
5638	&& fGuestAmd \
5639	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5640	&& !(aHostOverride##set [1].reg & bit) \
5641	) \
5642	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5643	} while (0)
5644	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5645
5646	/* For checking AMD features which have a corresponding bit in the standard
5647	range. (Intel defines very few bits in the extended feature sets.) */
5648	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5649	do { \
5650	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5651	&& !(fHostAmd \
5652	? aHostRawExt[1].reg & (ExtBit) \
5653	: aHostRawStd[1].reg & (StdBit)) \
5654	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5655	) \
5656	{ \
5657	if (fStrictCpuIdChecks) \
5658	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5659	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5660	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5661	} \
5662	} while (0)
5663	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5664	do { \
5665	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5666	&& !(fHostAmd \
5667	? aHostRawExt[1].reg & (ExtBit) \
5668	: aHostRawStd[1].reg & (StdBit)) \
5669	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5670	) \
5671	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5672	} while (0)
5673	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5674	do { \
5675	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5676	&& !(fHostAmd \
5677	? aHostRawExt[1].reg & (ExtBit) \
5678	: aHostRawStd[1].reg & (StdBit)) \
5679	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5680	) \
5681	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5682	} while (0)
5683	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5684
5685
5686	/*
5687	* Verify that we can support the features already exposed to the guest on
5688	* this host.
5689	*
5690	* Most of the features we're emulating requires intercepting instruction
5691	* and doing it the slow way, so there is no need to warn when they aren't
5692	* present in the host CPU. Thus we use IGN instead of EMU on these.
5693	*
5694	* Trailing comments:
5695	* "EMU" - Possible to emulate, could be lots of work and very slow.
5696	* "EMU?" - Can this be emulated?
5697	*/
5698	CPUMCPUID aGuestCpuIdStd[2];
5699	RT_ZERO(aGuestCpuIdStd);
5700	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5701
5702	/* CPUID(1).ecx */
5703	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5704	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5705	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5706	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5707	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5708	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5709	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5710	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5711	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5712	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5713	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5714	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5715	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5716	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5717	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5718	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5719	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5720	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5721	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5722	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5723	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5724	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5725	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5726	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5727	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5728	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5729	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5730	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5731	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5732	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5733	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5734	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5735
5736	/* CPUID(1).edx */
5737	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5738	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5739	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5740	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5741	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5742	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5743	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5744	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5745	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5746	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5747	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5748	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5749	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5750	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5751	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5752	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5753	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5754	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5755	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5756	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5757	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5758	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5759	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5760	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5761	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5762	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5763	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5764	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5765	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5766	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5767	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5768	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5769
5770	/* CPUID(0x80000000). */
5771	CPUMCPUID aGuestCpuIdExt[2];
5772	RT_ZERO(aGuestCpuIdExt);
5773	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5774	{
5775	/** @todo deal with no 0x80000001 on the host. */
5776	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx)
5777	\|\| ASMIsHygonCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5778	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx)
5779	\|\| ASMIsHygonCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5780
5781	/* CPUID(0x80000001).ecx */
5782	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5783	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5784	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5785	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5786	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5787	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5788	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5789	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5790	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5791	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5792	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5793	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5794	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5795	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5796	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5797	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5798	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5799	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5800	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5801	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5802	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5803	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5804	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5805	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5806	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5807	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5808	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5809	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5810	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5811	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5812	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5813	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5814
5815	/* CPUID(0x80000001).edx */
5816	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5817	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5818	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5819	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5820	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5821	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5822	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5823	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5824	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5825	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5826	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5827	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5828	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5829	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5830	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5831	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5832	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5833	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5834	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5835	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5836	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5837	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5838	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5839	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5840	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5841	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5842	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5843	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5844	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5845	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5846	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5847	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5848	}
5849
5850	/** @todo check leaf 7 */
5851
5852	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5853	* ECX=0: EAX - Valid bits in XCR0[31:0].
5854	* EBX - Maximum state size as per current XCR0 value.
5855	* ECX - Maximum state size for all supported features.
5856	* EDX - Valid bits in XCR0[63:32].
5857	* ECX=1: EAX - Various X-features.
5858	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5859	* ECX - Valid bits in IA32_XSS[31:0].
5860	* EDX - Valid bits in IA32_XSS[63:32].
5861	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5862	* if the bit invalid all four registers are set to zero.
5863	* EAX - The state size for this feature.
5864	* EBX - The state byte offset of this feature.
5865	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5866	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5867	*/
5868	uint64_t fGuestXcr0Mask = 0;
5869	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5870	if ( pCurLeaf
5871	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5872	&& ( pCurLeaf->uEax
5873	\|\| pCurLeaf->uEbx
5874	\|\| pCurLeaf->uEcx
5875	\|\| pCurLeaf->uEdx) )
5876	{
5877	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5878	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5879	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5880	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5881	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5882	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5883	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5884	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5885
5886	/* We don't support any additional features yet. */
5887	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5888	if (pCurLeaf && pCurLeaf->uEax)
5889	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5890	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5891	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5892	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5893	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5894	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5895
5896
5897	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5898	{
5899	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5900	if (pCurLeaf)
5901	{
5902	/* If advertised, the state component offset and size must match the one used by host. */
5903	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5904	{
5905	CPUMCPUID RawHost;
5906	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5907	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5908	if ( RawHost.uEbx != pCurLeaf->uEbx
5909	\|\| RawHost.uEax != pCurLeaf->uEax)
5910	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5911	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5912	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5913	}
5914	}
5915	}
5916	}
5917	/* Clear leaf 0xd just in case we're loading an old state... */
5918	else if (pCurLeaf)
5919	{
5920	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5921	{
5922	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5923	if (pCurLeaf)
5924	{
5925	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5926	\|\| ( pCurLeaf->uEax == 0
5927	&& pCurLeaf->uEbx == 0
5928	&& pCurLeaf->uEcx == 0
5929	&& pCurLeaf->uEdx == 0),
5930	("uVersion=%#x; %#x %#x %#x %#x\n",
5931	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5932	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5933	}
5934	}
5935	}
5936
5937	/* Update the fXStateGuestMask value for the VM. */
5938	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5939	{
5940	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5941	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5942	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5943	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5944	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5945	}
5946
5947	#undef CPUID_CHECK_RET
5948	#undef CPUID_CHECK_WRN
5949	#undef CPUID_CHECK2_RET
5950	#undef CPUID_CHECK2_WRN
5951	#undef CPUID_RAW_FEATURE_RET
5952	#undef CPUID_RAW_FEATURE_WRN
5953	#undef CPUID_RAW_FEATURE_IGN
5954	#undef CPUID_GST_FEATURE_RET
5955	#undef CPUID_GST_FEATURE_WRN
5956	#undef CPUID_GST_FEATURE_EMU
5957	#undef CPUID_GST_FEATURE_IGN
5958	#undef CPUID_GST_FEATURE2_RET
5959	#undef CPUID_GST_FEATURE2_WRN
5960	#undef CPUID_GST_FEATURE2_EMU
5961	#undef CPUID_GST_FEATURE2_IGN
5962	#undef CPUID_GST_AMD_FEATURE_RET
5963	#undef CPUID_GST_AMD_FEATURE_WRN
5964	#undef CPUID_GST_AMD_FEATURE_EMU
5965	#undef CPUID_GST_AMD_FEATURE_IGN
5966
5967	/*
5968	* We're good, commit the CPU ID leaves.
5969	*/
5970	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5971	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5972	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5973	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5974	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
5975	AssertLogRelRCReturn(rc, rc);
5976
5977	return VINF_SUCCESS;
5978	}
5979
5980
5981	/**
5982	* Loads the CPU ID leaves saved by pass 0.
5983	*
5984	* @returns VBox status code.
5985	* @param pVM The cross context VM structure.
5986	* @param pSSM The saved state handle.
5987	* @param uVersion The format version.
5988	* @param pMsrs The guest MSRs.
5989	*/
5990	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
5991	{
5992	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5993
5994	/*
5995	* Load the CPUID leaves array first and call worker to do the rest, just so
5996	* we can free the memory when we need to without ending up in column 1000.
5997	*/
5998	PCPUMCPUIDLEAF paLeaves;
5999	uint32_t cLeaves;
6000	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
6001	AssertRC(rc);
6002	if (RT_SUCCESS(rc))
6003	{
6004	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
6005	RTMemFree(paLeaves);
6006	}
6007	return rc;
6008	}
6009
6010
6011
6012	/**
6013	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
6014	*
6015	* @returns VBox status code.
6016	* @param pVM The cross context VM structure.
6017	* @param pSSM The saved state handle.
6018	* @param uVersion The format version.
6019	*/
6020	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
6021	{
6022	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
6023
6024	/*
6025	* Restore the CPUID leaves.
6026	*
6027	* Note that we support restoring less than the current amount of standard
6028	* leaves because we've been allowed more is newer version of VBox.
6029	*/
6030	uint32_t cElements;
6031	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6032	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
6033	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6034	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
6035
6036	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6037	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
6038	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6039	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
6040
6041	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6042	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
6043	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6044	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
6045
6046	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
6047
6048	/*
6049	* Check that the basic cpuid id information is unchanged.
6050	*/
6051	/** @todo we should check the 64 bits capabilities too! */
6052	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
6053	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
6054	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
6055	uint32_t au32CpuIdSaved[8];
6056	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
6057	if (RT_SUCCESS(rc))
6058	{
6059	/* Ignore CPU stepping. */
6060	au32CpuId[4] &= 0xfffffff0;
6061	au32CpuIdSaved[4] &= 0xfffffff0;
6062
6063	/* Ignore APIC ID (AMD specs). */
6064	au32CpuId[5] &= ~0xff000000;
6065	au32CpuIdSaved[5] &= ~0xff000000;
6066
6067	/* Ignore the number of Logical CPUs (AMD specs). */
6068	au32CpuId[5] &= ~0x00ff0000;
6069	au32CpuIdSaved[5] &= ~0x00ff0000;
6070
6071	/* Ignore some advanced capability bits, that we don't expose to the guest. */
6072	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6073	\| X86_CPUID_FEATURE_ECX_VMX
6074	\| X86_CPUID_FEATURE_ECX_SMX
6075	\| X86_CPUID_FEATURE_ECX_EST
6076	\| X86_CPUID_FEATURE_ECX_TM2
6077	\| X86_CPUID_FEATURE_ECX_CNTXID
6078	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6079	\| X86_CPUID_FEATURE_ECX_PDCM
6080	\| X86_CPUID_FEATURE_ECX_DCA
6081	\| X86_CPUID_FEATURE_ECX_X2APIC
6082	);
6083	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6084	\| X86_CPUID_FEATURE_ECX_VMX
6085	\| X86_CPUID_FEATURE_ECX_SMX
6086	\| X86_CPUID_FEATURE_ECX_EST
6087	\| X86_CPUID_FEATURE_ECX_TM2
6088	\| X86_CPUID_FEATURE_ECX_CNTXID
6089	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6090	\| X86_CPUID_FEATURE_ECX_PDCM
6091	\| X86_CPUID_FEATURE_ECX_DCA
6092	\| X86_CPUID_FEATURE_ECX_X2APIC
6093	);
6094
6095	/* Make sure we don't forget to update the masks when enabling
6096	* features in the future.
6097	*/
6098	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
6099	( X86_CPUID_FEATURE_ECX_DTES64
6100	\| X86_CPUID_FEATURE_ECX_VMX
6101	\| X86_CPUID_FEATURE_ECX_SMX
6102	\| X86_CPUID_FEATURE_ECX_EST
6103	\| X86_CPUID_FEATURE_ECX_TM2
6104	\| X86_CPUID_FEATURE_ECX_CNTXID
6105	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6106	\| X86_CPUID_FEATURE_ECX_PDCM
6107	\| X86_CPUID_FEATURE_ECX_DCA
6108	\| X86_CPUID_FEATURE_ECX_X2APIC
6109	)));
6110	/* do the compare */
6111	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
6112	{
6113	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
6114	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
6115	"Saved=%.*Rhxs\n"
6116	"Real =%.*Rhxs\n",
6117	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6118	sizeof(au32CpuId), au32CpuId));
6119	else
6120	{
6121	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
6122	"Saved=%.*Rhxs\n"
6123	"Real =%.*Rhxs\n",
6124	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6125	sizeof(au32CpuId), au32CpuId));
6126	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
6127	}
6128	}
6129	}
6130
6131	return rc;
6132	}
6133
6134
6135
6136	/*
6137	*
6138	*
6139	* CPUID Info Handler.
6140	* CPUID Info Handler.
6141	* CPUID Info Handler.
6142	*
6143	*
6144	*/
6145
6146
6147
6148	/**
6149	* Get L1 cache / TLS associativity.
6150	*/
6151	static const char getCacheAss(unsigned u, char pszBuf)
6152	{
6153	if (u == 0)
6154	return "res0 ";
6155	if (u == 1)
6156	return "direct";
6157	if (u == 255)
6158	return "fully";
6159	if (u >= 256)
6160	return "???";
6161
6162	RTStrPrintf(pszBuf, 16, "%d way", u);
6163	return pszBuf;
6164	}
6165
6166
6167	/**
6168	* Get L2 cache associativity.
6169	*/
6170	const char *getL2CacheAss(unsigned u)
6171	{
6172	switch (u)
6173	{
6174	case 0: return "off ";
6175	case 1: return "direct";
6176	case 2: return "2 way ";
6177	case 3: return "res3 ";
6178	case 4: return "4 way ";
6179	case 5: return "res5 ";
6180	case 6: return "8 way ";
6181	case 7: return "res7 ";
6182	case 8: return "16 way";
6183	case 9: return "res9 ";
6184	case 10: return "res10 ";
6185	case 11: return "res11 ";
6186	case 12: return "res12 ";
6187	case 13: return "res13 ";
6188	case 14: return "res14 ";
6189	case 15: return "fully ";
6190	default: return "????";
6191	}
6192	}
6193
6194
6195	/** CPUID(1).EDX field descriptions. */
6196	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6197	{
6198	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6199	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6200	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6201	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6202	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6203	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6204	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6205	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6206	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6207	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6208	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6209	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6210	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6211	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6212	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6213	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6214	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6215	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6216	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6217	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6218	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6219	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6220	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6221	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6222	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6223	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6224	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6225	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6226	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6227	DBGFREGSUBFIELD_TERMINATOR()
6228	};
6229
6230	/** CPUID(1).ECX field descriptions. */
6231	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6232	{
6233	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6234	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6235	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6236	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6237	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6238	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6239	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6240	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6241	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6242	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6243	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6244	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6245	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6246	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6247	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6248	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6249	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6250	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6251	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6252	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6253	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6254	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6255	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6256	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6257	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6258	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6259	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6260	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6261	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6262	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6263	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6264	DBGFREGSUBFIELD_TERMINATOR()
6265	};
6266
6267	/** CPUID(7,0).EBX field descriptions. */
6268	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6269	{
6270	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6271	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6272	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6273	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6274	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6275	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6276	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6277	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6278	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6279	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6280	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6281	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6282	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6283	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6284	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6285	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6286	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6287	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6288	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6289	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6290	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6291	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6292	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6293	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6294	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6295	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6296	DBGFREGSUBFIELD_TERMINATOR()
6297	};
6298
6299	/** CPUID(7,0).ECX field descriptions. */
6300	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6301	{
6302	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6303	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6304	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6305	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6306	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6307	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6308	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6309	DBGFREGSUBFIELD_TERMINATOR()
6310	};
6311
6312	/** CPUID(7,0).EDX field descriptions. */
6313	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6314	{
6315	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
6316	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6317	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6318	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
6319	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6320	DBGFREGSUBFIELD_RO("CORECAP\0" "Supports IA32_CORE_CAP", 30, 1, 0),
6321	DBGFREGSUBFIELD_RO("SSBD\0" "Supports IA32_SPEC_CTRL.SSBD", 31, 1, 0),
6322	DBGFREGSUBFIELD_TERMINATOR()
6323	};
6324
6325
6326	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6327	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6328	{
6329	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6330	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6331	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6332	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6333	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6334	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6335	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6336	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6337	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6338	DBGFREGSUBFIELD_TERMINATOR()
6339	};
6340
6341	/** CPUID(13,1).EAX field descriptions. */
6342	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6343	{
6344	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6345	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6346	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6347	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6348	DBGFREGSUBFIELD_TERMINATOR()
6349	};
6350
6351
6352	/** CPUID(0x80000001,0).EDX field descriptions. */
6353	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6354	{
6355	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6356	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6357	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6358	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6359	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6360	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6361	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6362	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6363	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6364	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6365	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6366	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6367	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6368	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6369	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6370	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6371	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6372	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6373	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6374	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6375	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6376	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6377	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6378	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6379	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6380	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6381	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6382	DBGFREGSUBFIELD_TERMINATOR()
6383	};
6384
6385	/** CPUID(0x80000001,0).ECX field descriptions. */
6386	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6387	{
6388	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6389	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6390	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6391	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6392	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6393	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6394	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6395	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6396	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6397	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6398	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6399	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6400	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6401	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6402	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6403	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6404	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6405	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6406	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6407	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6408	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6409	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6410	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6411	DBGFREGSUBFIELD_RO("PCX_L2I\0" "L2I/L3 Performance Counter Extensions", 28, 1, 0),
6412	DBGFREGSUBFIELD_RO("MWAITX\0" "MWAITX and MONITORX instructions", 29, 1, 0),
6413	DBGFREGSUBFIELD_TERMINATOR()
6414	};
6415
6416	/** CPUID(0x8000000a,0).EDX field descriptions. */
6417	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6418	{
6419	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6420	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6421	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6422	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6423	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6424	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6425	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6426	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6427	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6428	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6429	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6430	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6431	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6432	DBGFREGSUBFIELD_RO("GMET\0" "Guest Mode Execute Trap Extension", 17, 1, 0),
6433	DBGFREGSUBFIELD_TERMINATOR()
6434	};
6435
6436
6437	/** CPUID(0x80000007,0).EDX field descriptions. */
6438	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6439	{
6440	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6441	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6442	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6443	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6444	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6445	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6446	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6447	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6448	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6449	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6450	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6451	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6452	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6453	DBGFREGSUBFIELD_TERMINATOR()
6454	};
6455
6456	/** CPUID(0x80000008,0).EBX field descriptions. */
6457	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6458	{
6459	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6460	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6461	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6462	DBGFREGSUBFIELD_RO("RDPRU\0" "RDPRU instruction", 4, 1, 0),
6463	DBGFREGSUBFIELD_RO("MCOMMIT\0" "MCOMMIT instruction", 8, 1, 0),
6464	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6465	DBGFREGSUBFIELD_TERMINATOR()
6466	};
6467
6468
6469	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6470	const char *pszLeadIn, uint32_t cchWidth)
6471	{
6472	if (pszLeadIn)
6473	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6474
6475	for (uint32_t iBit = 0; iBit < 32; iBit++)
6476	if (RT_BIT_32(iBit) & uVal)
6477	{
6478	while ( pDesc->pszName != NULL
6479	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6480	pDesc++;
6481	if ( pDesc->pszName != NULL
6482	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6483	{
6484	if (pDesc->cBits == 1)
6485	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6486	else
6487	{
6488	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6489	if (pDesc->cBits < 32)
6490	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6491	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6492	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6493	}
6494	}
6495	else
6496	pHlp->pfnPrintf(pHlp, " %u", iBit);
6497	}
6498	if (pszLeadIn)
6499	pHlp->pfnPrintf(pHlp, "\n");
6500	}
6501
6502
6503	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6504	const char *pszLeadIn, uint32_t cchWidth)
6505	{
6506	if (pszLeadIn)
6507	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6508
6509	for (uint32_t iBit = 0; iBit < 64; iBit++)
6510	if (RT_BIT_64(iBit) & uVal)
6511	{
6512	while ( pDesc->pszName != NULL
6513	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6514	pDesc++;
6515	if ( pDesc->pszName != NULL
6516	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6517	{
6518	if (pDesc->cBits == 1)
6519	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6520	else
6521	{
6522	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6523	if (pDesc->cBits < 64)
6524	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6525	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6526	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6527	}
6528	}
6529	else
6530	pHlp->pfnPrintf(pHlp, " %u", iBit);
6531	}
6532	if (pszLeadIn)
6533	pHlp->pfnPrintf(pHlp, "\n");
6534	}
6535
6536
6537	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6538	const char *pszLeadIn, uint32_t cchWidth)
6539	{
6540	if (!uVal)
6541	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6542	else
6543	{
6544	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6545	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6546	pHlp->pfnPrintf(pHlp, " )\n");
6547	}
6548	}
6549
6550
6551	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6552	uint32_t cchWidth)
6553	{
6554	uint32_t uCombined = uVal1 \| uVal2;
6555	for (uint32_t iBit = 0; iBit < 32; iBit++)
6556	if ( (RT_BIT_32(iBit) & uCombined)
6557	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6558	{
6559	while ( pDesc->pszName != NULL
6560	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6561	pDesc++;
6562
6563	if ( pDesc->pszName != NULL
6564	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6565	{
6566	size_t cchMnemonic = strlen(pDesc->pszName);
6567	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6568	size_t cchDesc = strlen(pszDesc);
6569	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6570	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6571	if (pDesc->cBits < 32)
6572	{
6573	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6574	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6575	}
6576
6577	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6578	pDesc->pszName, pszDesc,
6579	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6580	uFieldValue1, uFieldValue2);
6581
6582	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6583	pDesc++;
6584	}
6585	else
6586	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6587	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6588	}
6589	}
6590
6591
6592	/**
6593	* Produces a detailed summary of standard leaf 0x00000001.
6594	*
6595	* @param pHlp The info helper functions.
6596	* @param pCurLeaf The 0x00000001 leaf.
6597	* @param fVerbose Whether to be very verbose or not.
6598	* @param fIntel Set if intel CPU.
6599	*/
6600	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6601	{
6602	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6603	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6604	uint32_t uEAX = pCurLeaf->uEax;
6605	uint32_t uEBX = pCurLeaf->uEbx;
6606
6607	pHlp->pfnPrintf(pHlp,
6608	"%36s %2d \tExtended: %d \tEffective: %d\n"
6609	"%36s %2d \tExtended: %d \tEffective: %d\n"
6610	"%36s %d\n"
6611	"%36s %d (%s)\n"
6612	"%36s %#04x\n"
6613	"%36s %d\n"
6614	"%36s %d\n"
6615	"%36s %#04x\n"
6616	,
6617	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6618	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6619	"Stepping:", ASMGetCpuStepping(uEAX),
6620	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6621	"APIC ID:", (uEBX >> 24) & 0xff,
6622	"Logical CPUs:",(uEBX >> 16) & 0xff,
6623	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6624	"Brand ID:", (uEBX >> 0) & 0xff);
6625	if (fVerbose)
6626	{
6627	CPUMCPUID Host;
6628	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6629	pHlp->pfnPrintf(pHlp, "Features\n");
6630	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6631	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6632	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6633	}
6634	else
6635	{
6636	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6637	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6638	}
6639	}
6640
6641
6642	/**
6643	* Produces a detailed summary of standard leaf 0x00000007.
6644	*
6645	* @param pHlp The info helper functions.
6646	* @param paLeaves The CPUID leaves array.
6647	* @param cLeaves The number of leaves in the array.
6648	* @param pCurLeaf The first 0x00000007 leaf.
6649	* @param fVerbose Whether to be very verbose or not.
6650	*/
6651	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6652	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6653	{
6654	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6655	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6656	for (;;)
6657	{
6658	CPUMCPUID Host;
6659	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6660
6661	switch (pCurLeaf->uSubLeaf)
6662	{
6663	case 0:
6664	if (fVerbose)
6665	{
6666	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6667	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6668	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6669	if (pCurLeaf->uEdx \|\| Host.uEdx)
6670	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6671	}
6672	else
6673	{
6674	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6675	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6676	if (pCurLeaf->uEdx)
6677	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6678	}
6679	break;
6680
6681	default:
6682	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6683	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6684	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6685	break;
6686
6687	}
6688
6689	/* advance. */
6690	pCurLeaf++;
6691	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6692	\|\| pCurLeaf->uLeaf != 0x7)
6693	break;
6694	}
6695	}
6696
6697
6698	/**
6699	* Produces a detailed summary of standard leaf 0x0000000d.
6700	*
6701	* @param pHlp The info helper functions.
6702	* @param paLeaves The CPUID leaves array.
6703	* @param cLeaves The number of leaves in the array.
6704	* @param pCurLeaf The first 0x00000007 leaf.
6705	* @param fVerbose Whether to be very verbose or not.
6706	*/
6707	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6708	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6709	{
6710	RT_NOREF_PV(fVerbose);
6711	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6712	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6713	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6714	{
6715	CPUMCPUID Host;
6716	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6717
6718	switch (uSubLeaf)
6719	{
6720	case 0:
6721	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6722	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6723	pCurLeaf->uEbx, pCurLeaf->uEcx);
6724	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6725
6726	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6727	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6728	"Valid XCR0 bits, guest:", 42);
6729	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6730	"Valid XCR0 bits, host:", 42);
6731	break;
6732
6733	case 1:
6734	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6735	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6736	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6737
6738	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6739	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6740	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6741
6742	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6743	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6744	" Valid IA32_XSS bits, guest:", 42);
6745	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6746	" Valid IA32_XSS bits, host:", 42);
6747	break;
6748
6749	default:
6750	if ( pCurLeaf
6751	&& pCurLeaf->uSubLeaf == uSubLeaf
6752	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6753	{
6754	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6755	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6756	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6757	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6758	if (pCurLeaf->uEdx)
6759	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6760	pHlp->pfnPrintf(pHlp, " --");
6761	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6762	pHlp->pfnPrintf(pHlp, "\n");
6763	}
6764	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6765	{
6766	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6767	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6768	if (Host.uEcx & ~RT_BIT_32(0))
6769	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6770	if (Host.uEdx)
6771	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6772	pHlp->pfnPrintf(pHlp, " --");
6773	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6774	pHlp->pfnPrintf(pHlp, "\n");
6775	}
6776	break;
6777
6778	}
6779
6780	/* advance. */
6781	if (pCurLeaf)
6782	{
6783	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6784	&& pCurLeaf->uSubLeaf <= uSubLeaf
6785	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6786	pCurLeaf++;
6787	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6788	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6789	pCurLeaf = NULL;
6790	}
6791	}
6792	}
6793
6794
6795	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6796	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6797	{
6798	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6799	&& pCurLeaf->uLeaf <= uUpToLeaf)
6800	{
6801	pHlp->pfnPrintf(pHlp,
6802	" %s\n"
6803	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6804	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6805	&& pCurLeaf->uLeaf <= uUpToLeaf)
6806	{
6807	CPUMCPUID Host;
6808	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6809	pHlp->pfnPrintf(pHlp,
6810	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6811	"Hst: %08x %08x %08x %08x\n",
6812	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6813	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6814	pCurLeaf++;
6815	}
6816	}
6817
6818	return pCurLeaf;
6819	}
6820
6821
6822	/**
6823	* Display the guest CpuId leaves.
6824	*
6825	* @param pVM The cross context VM structure.
6826	* @param pHlp The info helper functions.
6827	* @param pszArgs "terse", "default" or "verbose".
6828	*/
6829	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6830	{
6831	/*
6832	* Parse the argument.
6833	*/
6834	unsigned iVerbosity = 1;
6835	if (pszArgs)
6836	{
6837	pszArgs = RTStrStripL(pszArgs);
6838	if (!strcmp(pszArgs, "terse"))
6839	iVerbosity--;
6840	else if (!strcmp(pszArgs, "verbose"))
6841	iVerbosity++;
6842	}
6843
6844	uint32_t uLeaf;
6845	CPUMCPUID Host;
6846	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6847	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6848	PCCPUMCPUIDLEAF pCurLeaf;
6849	PCCPUMCPUIDLEAF pNextLeaf;
6850	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6851	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6852	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6853
6854	/*
6855	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6856	*/
6857	uint32_t cHstMax = ASMCpuId_EAX(0);
6858	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6859	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6860	pHlp->pfnPrintf(pHlp,
6861	" Raw Standard CPUID Leaves\n"
6862	" Leaf/sub-leaf eax ebx ecx edx\n");
6863	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6864	{
6865	uint32_t cMaxSubLeaves = 1;
6866	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6867	cMaxSubLeaves = 16;
6868	else if (uLeaf == 0xd)
6869	cMaxSubLeaves = 128;
6870
6871	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6872	{
6873	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6874	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6875	&& pCurLeaf->uLeaf == uLeaf
6876	&& pCurLeaf->uSubLeaf == uSubLeaf)
6877	{
6878	pHlp->pfnPrintf(pHlp,
6879	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6880	"Hst: %08x %08x %08x %08x\n",
6881	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6882	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6883	pCurLeaf++;
6884	}
6885	else if ( uLeaf != 0xd
6886	\|\| uSubLeaf <= 1
6887	\|\| Host.uEbx != 0 )
6888	pHlp->pfnPrintf(pHlp,
6889	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6890	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6891
6892	/* Done? */
6893	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6894	\|\| pCurLeaf->uLeaf != uLeaf)
6895	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6896	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6897	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6898	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6899	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6900	)
6901	)
6902	break;
6903	}
6904	}
6905	pNextLeaf = pCurLeaf;
6906
6907	/*
6908	* If verbose, decode it.
6909	*/
6910	if (iVerbosity && paLeaves[0].uLeaf == 0)
6911	pHlp->pfnPrintf(pHlp,
6912	"%36s %.04s%.04s%.04s\n"
6913	"%36s 0x00000000-%#010x\n"
6914	,
6915	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6916	"Supports:", paLeaves[0].uEax);
6917
6918	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6919	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6920
6921	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6922	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6923
6924	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6925	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6926
6927	pCurLeaf = pNextLeaf;
6928
6929	/*
6930	* Hypervisor leaves.
6931	*
6932	* Unlike most of the other leaves reported, the guest hypervisor leaves
6933	* aren't a subset of the host CPUID bits.
6934	*/
6935	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6936
6937	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6938	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6939	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6940	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6941	cMax = RT_MAX(cHstMax, cGstMax);
6942	if (cMax >= UINT32_C(0x40000000))
6943	{
6944	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6945
6946	/** @todo dump these in more detail. */
6947
6948	pCurLeaf = pNextLeaf;
6949	}
6950
6951
6952	/*
6953	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6954	* Implemented after AMD specs.
6955	*/
6956	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6957
6958	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6959	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6960	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6961	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6962	cMax = RT_MAX(cHstMax, cGstMax);
6963	if (cMax >= UINT32_C(0x80000000))
6964	{
6965
6966	pHlp->pfnPrintf(pHlp,
6967	" Raw Extended CPUID Leaves\n"
6968	" Leaf/sub-leaf eax ebx ecx edx\n");
6969	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6970	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6971	{
6972	uint32_t cMaxSubLeaves = 1;
6973	if (uLeaf == UINT32_C(0x8000001d))
6974	cMaxSubLeaves = 16;
6975
6976	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6977	{
6978	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6979	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6980	&& pCurLeaf->uLeaf == uLeaf
6981	&& pCurLeaf->uSubLeaf == uSubLeaf)
6982	{
6983	pHlp->pfnPrintf(pHlp,
6984	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6985	"Hst: %08x %08x %08x %08x\n",
6986	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6987	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6988	pCurLeaf++;
6989	}
6990	else if ( uLeaf != 0xd
6991	\|\| uSubLeaf <= 1
6992	\|\| Host.uEbx != 0 )
6993	pHlp->pfnPrintf(pHlp,
6994	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6995	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6996
6997	/* Done? */
6998	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6999	\|\| pCurLeaf->uLeaf != uLeaf)
7000	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
7001	break;
7002	}
7003	}
7004	pNextLeaf = pCurLeaf;
7005
7006	/*
7007	* Understandable output
7008	*/
7009	if (iVerbosity)
7010	pHlp->pfnPrintf(pHlp,
7011	"Ext Name: %.4s%.4s%.4s\n"
7012	"Ext Supports: 0x80000000-%#010x\n",
7013	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
7014
7015	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
7016	if (iVerbosity && pCurLeaf)
7017	{
7018	uint32_t uEAX = pCurLeaf->uEax;
7019	pHlp->pfnPrintf(pHlp,
7020	"Family: %d \tExtended: %d \tEffective: %d\n"
7021	"Model: %d \tExtended: %d \tEffective: %d\n"
7022	"Stepping: %d\n"
7023	"Brand ID: %#05x\n",
7024	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
7025	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
7026	ASMGetCpuStepping(uEAX),
7027	pCurLeaf->uEbx & 0xfff);
7028
7029	if (iVerbosity == 1)
7030	{
7031	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
7032	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
7033	}
7034	else
7035	{
7036	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7037	pHlp->pfnPrintf(pHlp, "Ext Features\n");
7038	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
7039	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
7040	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
7041	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
7042	{
7043	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
7044	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7045	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
7046	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
7047	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
7048	}
7049	}
7050	}
7051
7052	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
7053	{
7054	char szString[443+1] = {0};
7055	uint32_t pu32 = (uint32_t )szString;
7056	*pu32++ = pCurLeaf->uEax;
7057	*pu32++ = pCurLeaf->uEbx;
7058	*pu32++ = pCurLeaf->uEcx;
7059	*pu32++ = pCurLeaf->uEdx;
7060	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
7061	if (pCurLeaf)
7062	{
7063	*pu32++ = pCurLeaf->uEax;
7064	*pu32++ = pCurLeaf->uEbx;
7065	*pu32++ = pCurLeaf->uEcx;
7066	*pu32++ = pCurLeaf->uEdx;
7067	}
7068	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
7069	if (pCurLeaf)
7070	{
7071	*pu32++ = pCurLeaf->uEax;
7072	*pu32++ = pCurLeaf->uEbx;
7073	*pu32++ = pCurLeaf->uEcx;
7074	*pu32++ = pCurLeaf->uEdx;
7075	}
7076	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
7077	}
7078
7079	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
7080	{
7081	uint32_t uEAX = pCurLeaf->uEax;
7082	uint32_t uEBX = pCurLeaf->uEbx;
7083	uint32_t uECX = pCurLeaf->uEcx;
7084	uint32_t uEDX = pCurLeaf->uEdx;
7085	char sz1[32];
7086	char sz2[32];
7087
7088	pHlp->pfnPrintf(pHlp,
7089	"TLB 2/4M Instr/Uni: %s %3d entries\n"
7090	"TLB 2/4M Data: %s %3d entries\n",
7091	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
7092	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
7093	pHlp->pfnPrintf(pHlp,
7094	"TLB 4K Instr/Uni: %s %3d entries\n"
7095	"TLB 4K Data: %s %3d entries\n",
7096	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
7097	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
7098	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
7099	"L1 Instr Cache Lines Per Tag: %d\n"
7100	"L1 Instr Cache Associativity: %s\n"
7101	"L1 Instr Cache Size: %d KB\n",
7102	(uEDX >> 0) & 0xff,
7103	(uEDX >> 8) & 0xff,
7104	getCacheAss((uEDX >> 16) & 0xff, sz1),
7105	(uEDX >> 24) & 0xff);
7106	pHlp->pfnPrintf(pHlp,
7107	"L1 Data Cache Line Size: %d bytes\n"
7108	"L1 Data Cache Lines Per Tag: %d\n"
7109	"L1 Data Cache Associativity: %s\n"
7110	"L1 Data Cache Size: %d KB\n",
7111	(uECX >> 0) & 0xff,
7112	(uECX >> 8) & 0xff,
7113	getCacheAss((uECX >> 16) & 0xff, sz1),
7114	(uECX >> 24) & 0xff);
7115	}
7116
7117	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
7118	{
7119	uint32_t uEAX = pCurLeaf->uEax;
7120	uint32_t uEBX = pCurLeaf->uEbx;
7121	uint32_t uEDX = pCurLeaf->uEdx;
7122
7123	pHlp->pfnPrintf(pHlp,
7124	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
7125	"L2 TLB 2/4M Data: %s %4d entries\n",
7126	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
7127	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
7128	pHlp->pfnPrintf(pHlp,
7129	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
7130	"L2 TLB 4K Data: %s %4d entries\n",
7131	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
7132	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
7133	pHlp->pfnPrintf(pHlp,
7134	"L2 Cache Line Size: %d bytes\n"
7135	"L2 Cache Lines Per Tag: %d\n"
7136	"L2 Cache Associativity: %s\n"
7137	"L2 Cache Size: %d KB\n",
7138	(uEDX >> 0) & 0xff,
7139	(uEDX >> 8) & 0xf,
7140	getL2CacheAss((uEDX >> 12) & 0xf),
7141	(uEDX >> 16) & 0xffff);
7142	}
7143
7144	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
7145	{
7146	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7147	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
7148	{
7149	if (iVerbosity < 1)
7150	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7151	else
7152	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7153	}
7154	}
7155
7156	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7157	if (pCurLeaf != NULL)
7158	{
7159	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7160	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7161	{
7162	if (iVerbosity < 1)
7163	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7164	else
7165	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7166	}
7167
7168	if (iVerbosity)
7169	{
7170	uint32_t uEAX = pCurLeaf->uEax;
7171	uint32_t uECX = pCurLeaf->uEcx;
7172
7173	/** @todo 0x80000008:EAX[23:16] is only defined for AMD. We'll get 0 on Intel. On
7174	* AMD if we get 0, the guest physical address width should be taken from
7175	* 0x80000008:EAX[7:0] instead. Guest Physical address width is relevant
7176	* for guests using nested paging. */
7177	pHlp->pfnPrintf(pHlp,
7178	"Physical Address Width: %d bits\n"
7179	"Virtual Address Width: %d bits\n"
7180	"Guest Physical Address Width: %d bits\n",
7181	(uEAX >> 0) & 0xff,
7182	(uEAX >> 8) & 0xff,
7183	(uEAX >> 16) & 0xff);
7184
7185	/** @todo 0x80000008:ECX is reserved on Intel (we'll get incorrect physical core
7186	* count here). */
7187	pHlp->pfnPrintf(pHlp,
7188	"Physical Core Count: %d\n",
7189	((uECX >> 0) & 0xff) + 1);
7190	}
7191	}
7192
7193	pCurLeaf = pNextLeaf;
7194	}
7195
7196
7197
7198	/*
7199	* Centaur.
7200	*/
7201	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7202
7203	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7204	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7205	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7206	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7207	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7208	cMax = RT_MAX(cHstMax, cGstMax);
7209	if (cMax >= UINT32_C(0xc0000000))
7210	{
7211	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7212
7213	/*
7214	* Understandable output
7215	*/
7216	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7217	pHlp->pfnPrintf(pHlp,
7218	"Centaur Supports: 0xc0000000-%#010x\n",
7219	pCurLeaf->uEax);
7220
7221	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7222	{
7223	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7224	uint32_t uEdxGst = pCurLeaf->uEdx;
7225	uint32_t uEdxHst = Host.uEdx;
7226
7227	if (iVerbosity == 1)
7228	{
7229	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7230	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7231	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7232	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7233	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7234	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7235	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7236	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7237	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7238	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7239	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7240	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7241	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7242	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7243	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7244	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7245	for (unsigned iBit = 14; iBit < 32; iBit++)
7246	if (uEdxGst & RT_BIT(iBit))
7247	pHlp->pfnPrintf(pHlp, " %d", iBit);
7248	pHlp->pfnPrintf(pHlp, "\n");
7249	}
7250	else
7251	{
7252	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7253	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7254	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7255	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7256	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7257	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7258	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7259	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7260	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7261	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7262	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7263	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7264	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7265	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7266	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7267	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7268	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7269	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7270	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7271	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7272	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7273	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7274	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7275	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7276	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7277	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7278	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7279	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7280	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7281	for (unsigned iBit = 27; iBit < 32; iBit++)
7282	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7283	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7284	pHlp->pfnPrintf(pHlp, "\n");
7285	}
7286	}
7287
7288	pCurLeaf = pNextLeaf;
7289	}
7290
7291	/*
7292	* The remainder.
7293	*/
7294	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7295	}
7296
7297	#endif /* !IN_VBOX_CPU_REPORT */
7298

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 90703

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