CPUMR3CpuId.cpp@ 91535

Last change on this file since 91535 was 91354, checked in by vboxsync, 3 years ago
VMM: Nested VMX: bugref:10092 Fix VMX preemption timer's default.
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File size: 340.7 KB

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1	/* $Id: CPUMR3CpuId.cpp 91354 2021-09-24 06:43:55Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vmcc.h>
30	#include <VBox/sup.h>
31
32	#include <VBox/err.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/ctype.h>
35	#include <iprt/mem.h>
36	#include <iprt/string.h>
37
38
39	/*********************************************************************************************************************************
40	* Defined Constants And Macros *
41	*********************************************************************************************************************************/
42	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
43	#define CPUM_CPUID_MAX_LEAVES 2048
44	/** Max size we accept for the XSAVE area.
45	* @see CPUMCTX::abXSave */
46	#define CPUM_MAX_XSAVE_AREA_SIZE (0x4000 - 0x300)
47	/* Min size we accept for the XSAVE area. */
48	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
49
50
51	/*********************************************************************************************************************************
52	* Global Variables *
53	*********************************************************************************************************************************/
54	/**
55	* The intel pentium family.
56	*/
57	static const CPUMMICROARCH g_aenmIntelFamily06[] =
58	{
59	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
60	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
61	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
63	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
64	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
65	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
66	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
67	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
68	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
69	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
70	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
71	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
72	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
73	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
74	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
75	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
81	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
82	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
83	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [26(0x1a)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Nehalem-EP */
86	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
88	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
89	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
90	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
91	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
97	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
98	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
99	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
102	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
104	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
105	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
106	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
107	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
113	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
114	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
115	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
118	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
121	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
122	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
130	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
131	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
136	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,
138	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Broadwell-E */
139	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu; skylake <= 4, cascade lake > 5 */
145	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
146	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
147	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
150	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
152	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
153	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
154	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
155	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
159	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
160	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
161	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
162	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
163	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
164	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
165	/[106(0x6a)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
166	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
167	/[108(0x6c)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
168	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
169	/[110(0x6e)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
170	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
171	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
172	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
173	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
174	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
175	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
176	/[117(0x75)] = / kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
177	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
178	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
179	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
180	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
181	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
182	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
183	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
184	/[125(0x7d)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
185	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
186	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
187	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
188	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
189	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
190	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
191	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
192	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
193	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
194	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
195	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
196	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
197	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
198	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
199	/[140(0x8c)] = / kCpumMicroarch_Intel_Core7_TigerLake, /* 11th Gen Intel(R) Core(TM) i7-1185G7 @ 3.00GHz (bird) */
200	/[141(0x8d)] = / kCpumMicroarch_Intel_Core7_TigerLake, /* unconfirmed */
201	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
202	/[143(0x8f)] = / kCpumMicroarch_Intel_Core7_SapphireRapids,
203	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
204	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
205	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
206	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
207	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
208	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
209	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
210	/[151(0x97)] = / kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
211	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
212	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
213	/[154(0x9a)] = / kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
214	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
215	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
216	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
217	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
218	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
219	/[160(0xa0)] = / kCpumMicroarch_Intel_Unknown,
220	/[161(0xa1)] = / kCpumMicroarch_Intel_Unknown,
221	/[162(0xa2)] = / kCpumMicroarch_Intel_Unknown,
222	/[163(0xa3)] = / kCpumMicroarch_Intel_Unknown,
223	/[164(0xa4)] = / kCpumMicroarch_Intel_Unknown,
224	/[165(0xa5)] = / kCpumMicroarch_Intel_Core7_CometLake, /* unconfirmed */
225	/[166(0xa6)] = / kCpumMicroarch_Intel_Unknown,
226	/[167(0xa7)] = / kCpumMicroarch_Intel_Core7_CypressCove, /* 14nm backport, unconfirmed */
227	};
228	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0xa7+1);
229
230
231	/**
232	* Figures out the (sub-)micro architecture given a bit of CPUID info.
233	*
234	* @returns Micro architecture.
235	* @param enmVendor The CPU vendor.
236	* @param bFamily The CPU family.
237	* @param bModel The CPU model.
238	* @param bStepping The CPU stepping.
239	*/
240	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
241	uint8_t bModel, uint8_t bStepping)
242	{
243	if (enmVendor == CPUMCPUVENDOR_AMD)
244	{
245	switch (bFamily)
246	{
247	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
248	case 0x03: return kCpumMicroarch_AMD_Am386;
249	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
250	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
251	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
252	case 0x06:
253	switch (bModel)
254	{
255	case 0: return kCpumMicroarch_AMD_K7_Palomino;
256	case 1: return kCpumMicroarch_AMD_K7_Palomino;
257	case 2: return kCpumMicroarch_AMD_K7_Palomino;
258	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
259	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
260	case 6: return kCpumMicroarch_AMD_K7_Palomino;
261	case 7: return kCpumMicroarch_AMD_K7_Morgan;
262	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
263	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
264	}
265	return kCpumMicroarch_AMD_K7_Unknown;
266	case 0x0f:
267	/*
268	* This family is a friggin mess. Trying my best to make some
269	* sense out of it. Too much happened in the 0x0f family to
270	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
271	*
272	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
273	* cpu-world.com, and other places:
274	* - 130nm:
275	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
276	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
277	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
278	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
279	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
280	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
281	* - 90nm:
282	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
283	* - Oakville: 10FC0/DH-D0.
284	* - Georgetown: 10FC0/DH-D0.
285	* - Sonora: 10FC0/DH-D0.
286	* - Venus: 20F71/SH-E4
287	* - Troy: 20F51/SH-E4
288	* - Athens: 20F51/SH-E4
289	* - San Diego: 20F71/SH-E4.
290	* - Lancaster: 20F42/SH-E5
291	* - Newark: 20F42/SH-E5.
292	* - Albany: 20FC2/DH-E6.
293	* - Roma: 20FC2/DH-E6.
294	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
295	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
296	* - 90nm introducing Dual core:
297	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
298	* - Italy: 20F10/JH-E1, 20F12/JH-E6
299	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
300	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
301	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
302	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
303	* - Santa Ana: 40F32/JH-F2, /-F3
304	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
305	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
306	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
307	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
308	* - Keene: 40FC2/DH-F2.
309	* - Richmond: 40FC2/DH-F2
310	* - Taylor: 40F82/BH-F2
311	* - Trinidad: 40F82/BH-F2
312	*
313	* - 65nm:
314	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
315	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
316	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
317	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
318	* - Sherman: /-G1, 70FC2/DH-G2.
319	* - Huron: 70FF2/DH-G2.
320	*/
321	if (bModel < 0x10)
322	return kCpumMicroarch_AMD_K8_130nm;
323	if (bModel >= 0x60 && bModel < 0x80)
324	return kCpumMicroarch_AMD_K8_65nm;
325	if (bModel >= 0x40)
326	return kCpumMicroarch_AMD_K8_90nm_AMDV;
327	switch (bModel)
328	{
329	case 0x21:
330	case 0x23:
331	case 0x2b:
332	case 0x2f:
333	case 0x37:
334	case 0x3f:
335	return kCpumMicroarch_AMD_K8_90nm_DualCore;
336	}
337	return kCpumMicroarch_AMD_K8_90nm;
338	case 0x10:
339	return kCpumMicroarch_AMD_K10;
340	case 0x11:
341	return kCpumMicroarch_AMD_K10_Lion;
342	case 0x12:
343	return kCpumMicroarch_AMD_K10_Llano;
344	case 0x14:
345	return kCpumMicroarch_AMD_Bobcat;
346	case 0x15:
347	switch (bModel)
348	{
349	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
350	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
351	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
352	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
353	case 0x11: /* ?? */
354	case 0x12: /* ?? */
355	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
356	}
357	return kCpumMicroarch_AMD_15h_Unknown;
358	case 0x16:
359	return kCpumMicroarch_AMD_Jaguar;
360	case 0x17:
361	return kCpumMicroarch_AMD_Zen_Ryzen;
362	}
363	return kCpumMicroarch_AMD_Unknown;
364	}
365
366	if (enmVendor == CPUMCPUVENDOR_INTEL)
367	{
368	switch (bFamily)
369	{
370	case 3:
371	return kCpumMicroarch_Intel_80386;
372	case 4:
373	return kCpumMicroarch_Intel_80486;
374	case 5:
375	return kCpumMicroarch_Intel_P5;
376	case 6:
377	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
378	{
379	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
380	if (enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake)
381	{
382	if (bStepping >= 0xa && bStepping <= 0xc)
383	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
384	else if (bStepping >= 0xc)
385	enmMicroArch = kCpumMicroarch_Intel_Core7_WhiskeyLake;
386	}
387	else if ( enmMicroArch == kCpumMicroarch_Intel_Core7_Skylake
388	&& bModel == 0x55
389	&& bStepping >= 5)
390	enmMicroArch = kCpumMicroarch_Intel_Core7_CascadeLake;
391	return enmMicroArch;
392	}
393	return kCpumMicroarch_Intel_Atom_Unknown;
394	case 15:
395	switch (bModel)
396	{
397	case 0: return kCpumMicroarch_Intel_NB_Willamette;
398	case 1: return kCpumMicroarch_Intel_NB_Willamette;
399	case 2: return kCpumMicroarch_Intel_NB_Northwood;
400	case 3: return kCpumMicroarch_Intel_NB_Prescott;
401	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
402	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
403	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
404	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
405	default: return kCpumMicroarch_Intel_NB_Unknown;
406	}
407	break;
408	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
409	case 0:
410	return kCpumMicroarch_Intel_8086;
411	case 1:
412	return kCpumMicroarch_Intel_80186;
413	case 2:
414	return kCpumMicroarch_Intel_80286;
415	}
416	return kCpumMicroarch_Intel_Unknown;
417	}
418
419	if (enmVendor == CPUMCPUVENDOR_VIA)
420	{
421	switch (bFamily)
422	{
423	case 5:
424	switch (bModel)
425	{
426	case 1: return kCpumMicroarch_Centaur_C6;
427	case 4: return kCpumMicroarch_Centaur_C6;
428	case 8: return kCpumMicroarch_Centaur_C2;
429	case 9: return kCpumMicroarch_Centaur_C3;
430	}
431	break;
432
433	case 6:
434	switch (bModel)
435	{
436	case 5: return kCpumMicroarch_VIA_C3_M2;
437	case 6: return kCpumMicroarch_VIA_C3_C5A;
438	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
439	case 8: return kCpumMicroarch_VIA_C3_C5N;
440	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
441	case 10: return kCpumMicroarch_VIA_C7_C5J;
442	case 15: return kCpumMicroarch_VIA_Isaiah;
443	}
444	break;
445	}
446	return kCpumMicroarch_VIA_Unknown;
447	}
448
449	if (enmVendor == CPUMCPUVENDOR_SHANGHAI)
450	{
451	switch (bFamily)
452	{
453	case 6:
454	case 7:
455	return kCpumMicroarch_Shanghai_Wudaokou;
456	default:
457	break;
458	}
459	return kCpumMicroarch_Shanghai_Unknown;
460	}
461
462	if (enmVendor == CPUMCPUVENDOR_CYRIX)
463	{
464	switch (bFamily)
465	{
466	case 4:
467	switch (bModel)
468	{
469	case 9: return kCpumMicroarch_Cyrix_5x86;
470	}
471	break;
472
473	case 5:
474	switch (bModel)
475	{
476	case 2: return kCpumMicroarch_Cyrix_M1;
477	case 4: return kCpumMicroarch_Cyrix_MediaGX;
478	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
479	}
480	break;
481
482	case 6:
483	switch (bModel)
484	{
485	case 0: return kCpumMicroarch_Cyrix_M2;
486	}
487	break;
488
489	}
490	return kCpumMicroarch_Cyrix_Unknown;
491	}
492
493	if (enmVendor == CPUMCPUVENDOR_HYGON)
494	{
495	switch (bFamily)
496	{
497	case 0x18:
498	return kCpumMicroarch_Hygon_Dhyana;
499	default:
500	break;
501	}
502	return kCpumMicroarch_Hygon_Unknown;
503	}
504
505	return kCpumMicroarch_Unknown;
506	}
507
508
509	/**
510	* Translates a microarchitecture enum value to the corresponding string
511	* constant.
512	*
513	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
514	* NULL if the value is invalid.
515	*
516	* @param enmMicroarch The enum value to convert.
517	*/
518	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
519	{
520	switch (enmMicroarch)
521	{
522	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
523	CASE_RET_STR(kCpumMicroarch_Intel_8086);
524	CASE_RET_STR(kCpumMicroarch_Intel_80186);
525	CASE_RET_STR(kCpumMicroarch_Intel_80286);
526	CASE_RET_STR(kCpumMicroarch_Intel_80386);
527	CASE_RET_STR(kCpumMicroarch_Intel_80486);
528	CASE_RET_STR(kCpumMicroarch_Intel_P5);
529
530	CASE_RET_STR(kCpumMicroarch_Intel_P6);
531	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
532	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
533
534	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
535	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
536	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
537
538	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
539	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
540
541	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
542	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
543	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
544	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
545	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
546	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
547	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
548	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
549	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
550	CASE_RET_STR(kCpumMicroarch_Intel_Core7_WhiskeyLake);
551	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CascadeLake);
552	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
553	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CometLake);
554	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
555	CASE_RET_STR(kCpumMicroarch_Intel_Core7_RocketLake);
556	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
557	CASE_RET_STR(kCpumMicroarch_Intel_Core7_AlderLake);
558	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SapphireRapids);
559
560	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
561	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
562	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
563	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
564	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
565	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
566	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
567	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
568
569	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
570	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
571	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
572	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
573	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
574
575	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
576	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
577	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
578	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
579	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
580	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
581	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
582
583	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
584
585	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
586	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
587	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
588	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
589	CASE_RET_STR(kCpumMicroarch_AMD_K5);
590	CASE_RET_STR(kCpumMicroarch_AMD_K6);
591
592	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
593	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
594	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
595	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
596	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
597	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
598	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
599
600	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
601	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
602	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
603	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
604	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
605
606	CASE_RET_STR(kCpumMicroarch_AMD_K10);
607	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
608	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
609	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
610	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
611
612	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
613	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
614	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
615	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
616	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
617
618	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
619
620	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
621
622	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
623
624	CASE_RET_STR(kCpumMicroarch_Hygon_Dhyana);
625	CASE_RET_STR(kCpumMicroarch_Hygon_Unknown);
626
627	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
628	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
629	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
630	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
631	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
632	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
633	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
634	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
635	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
636	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
637	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
638	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
639	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
640
641	CASE_RET_STR(kCpumMicroarch_Shanghai_Wudaokou);
642	CASE_RET_STR(kCpumMicroarch_Shanghai_Unknown);
643
644	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
645	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
646	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
647	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
648	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
649	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
650
651	CASE_RET_STR(kCpumMicroarch_NEC_V20);
652	CASE_RET_STR(kCpumMicroarch_NEC_V30);
653
654	CASE_RET_STR(kCpumMicroarch_Unknown);
655
656	#undef CASE_RET_STR
657	case kCpumMicroarch_Invalid:
658	case kCpumMicroarch_Intel_End:
659	case kCpumMicroarch_Intel_Core2_End:
660	case kCpumMicroarch_Intel_Core7_End:
661	case kCpumMicroarch_Intel_Atom_End:
662	case kCpumMicroarch_Intel_P6_Core_Atom_End:
663	case kCpumMicroarch_Intel_Phi_End:
664	case kCpumMicroarch_Intel_NB_End:
665	case kCpumMicroarch_AMD_K7_End:
666	case kCpumMicroarch_AMD_K8_End:
667	case kCpumMicroarch_AMD_15h_End:
668	case kCpumMicroarch_AMD_16h_End:
669	case kCpumMicroarch_AMD_Zen_End:
670	case kCpumMicroarch_AMD_End:
671	case kCpumMicroarch_Hygon_End:
672	case kCpumMicroarch_VIA_End:
673	case kCpumMicroarch_Shanghai_End:
674	case kCpumMicroarch_Cyrix_End:
675	case kCpumMicroarch_NEC_End:
676	case kCpumMicroarch_32BitHack:
677	break;
678	/* no default! */
679	}
680
681	return NULL;
682	}
683
684
685	/**
686	* Determins the host CPU MXCSR mask.
687	*
688	* @returns MXCSR mask.
689	*/
690	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
691	{
692	if ( ASMHasCpuId()
693	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
694	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
695	{
696	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
697	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
698	RT_ZERO(*pState);
699	ASMFxSave(pState);
700	if (pState->MXCSR_MASK == 0)
701	return 0xffbf;
702	return pState->MXCSR_MASK;
703	}
704	return 0;
705	}
706
707
708	/**
709	* Gets a matching leaf in the CPUID leaf array.
710	*
711	* @returns Pointer to the matching leaf, or NULL if not found.
712	* @param paLeaves The CPUID leaves to search. This is sorted.
713	* @param cLeaves The number of leaves in the array.
714	* @param uLeaf The leaf to locate.
715	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
716	*/
717	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
718	{
719	/* Lazy bird does linear lookup here since this is only used for the
720	occational CPUID overrides. */
721	for (uint32_t i = 0; i < cLeaves; i++)
722	if ( paLeaves[i].uLeaf == uLeaf
723	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
724	return &paLeaves[i];
725	return NULL;
726	}
727
728
729	#ifndef IN_VBOX_CPU_REPORT
730	/**
731	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
732	*
733	* @returns true if found, false it not.
734	* @param paLeaves The CPUID leaves to search. This is sorted.
735	* @param cLeaves The number of leaves in the array.
736	* @param uLeaf The leaf to locate.
737	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
738	* @param pLegacy The legacy output leaf.
739	*/
740	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
741	PCPUMCPUID pLegacy)
742	{
743	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
744	if (pLeaf)
745	{
746	pLegacy->uEax = pLeaf->uEax;
747	pLegacy->uEbx = pLeaf->uEbx;
748	pLegacy->uEcx = pLeaf->uEcx;
749	pLegacy->uEdx = pLeaf->uEdx;
750	return true;
751	}
752	return false;
753	}
754	#endif /* IN_VBOX_CPU_REPORT */
755
756
757	/**
758	* Ensures that the CPUID leaf array can hold one more leaf.
759	*
760	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
761	* failure.
762	* @param pVM The cross context VM structure. If NULL, use
763	* the process heap, otherwise the VM's hyper heap.
764	* @param ppaLeaves Pointer to the variable holding the array pointer
765	* (input/output).
766	* @param cLeaves The current array size.
767	*
768	* @remarks This function will automatically update the R0 and RC pointers when
769	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
770	* be the corresponding VM's CPUID arrays (which is asserted).
771	*/
772	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
773	{
774	/*
775	* If pVM is not specified, we're on the regular heap and can waste a
776	* little space to speed things up.
777	*/
778	uint32_t cAllocated;
779	if (!pVM)
780	{
781	cAllocated = RT_ALIGN(cLeaves, 16);
782	if (cLeaves + 1 > cAllocated)
783	{
784	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
785	if (pvNew)
786	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
787	else
788	{
789	RTMemFree(*ppaLeaves);
790	*ppaLeaves = NULL;
791	}
792	}
793	}
794	/*
795	* Otherwise, we're on the hyper heap and are probably just inserting
796	* one or two leaves and should conserve space.
797	*/
798	else
799	{
800	#ifdef IN_VBOX_CPU_REPORT
801	AssertReleaseFailed();
802	#else
803	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
804	Assert(*ppaLeaves == pVM->cpum.s.GuestInfo.aCpuIdLeaves);
805	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
806
807	if (cLeaves + 1 <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves))
808	{ }
809	else
810	{
811	*ppaLeaves = NULL;
812	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: Out of CPUID space!\n"));
813	}
814	#endif
815	}
816	return *ppaLeaves;
817	}
818
819
820	/**
821	* Append a CPUID leaf or sub-leaf.
822	*
823	* ASSUMES linear insertion order, so we'll won't need to do any searching or
824	* replace anything. Use cpumR3CpuIdInsert() for those cases.
825	*
826	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
827	* the caller need do no more work.
828	* @param ppaLeaves Pointer to the pointer to the array of sorted
829	* CPUID leaves and sub-leaves.
830	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
831	* @param uLeaf The leaf we're adding.
832	* @param uSubLeaf The sub-leaf number.
833	* @param fSubLeafMask The sub-leaf mask.
834	* @param uEax The EAX value.
835	* @param uEbx The EBX value.
836	* @param uEcx The ECX value.
837	* @param uEdx The EDX value.
838	* @param fFlags The flags.
839	*/
840	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
841	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
842	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
843	{
844	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
845	return VERR_NO_MEMORY;
846
847	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
848	Assert( *pcLeaves == 0
849	\|\| pNew[-1].uLeaf < uLeaf
850	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
851
852	pNew->uLeaf = uLeaf;
853	pNew->uSubLeaf = uSubLeaf;
854	pNew->fSubLeafMask = fSubLeafMask;
855	pNew->uEax = uEax;
856	pNew->uEbx = uEbx;
857	pNew->uEcx = uEcx;
858	pNew->uEdx = uEdx;
859	pNew->fFlags = fFlags;
860
861	*pcLeaves += 1;
862	return VINF_SUCCESS;
863	}
864
865
866	/**
867	* Checks that we've updated the CPUID leaves array correctly.
868	*
869	* This is a no-op in non-strict builds.
870	*
871	* @param paLeaves The leaves array.
872	* @param cLeaves The number of leaves.
873	*/
874	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
875	{
876	#ifdef VBOX_STRICT
877	for (uint32_t i = 1; i < cLeaves; i++)
878	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
879	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
880	else
881	{
882	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
883	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
884	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
885	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
886	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
887	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
888	}
889	#else
890	NOREF(paLeaves);
891	NOREF(cLeaves);
892	#endif
893	}
894
895
896	/**
897	* Inserts a CPU ID leaf, replacing any existing ones.
898	*
899	* When inserting a simple leaf where we already got a series of sub-leaves with
900	* the same leaf number (eax), the simple leaf will replace the whole series.
901	*
902	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
903	* host-context heap and has only been allocated/reallocated by the
904	* cpumR3CpuIdEnsureSpace function.
905	*
906	* @returns VBox status code.
907	* @param pVM The cross context VM structure. If NULL, use
908	* the process heap, otherwise the VM's hyper heap.
909	* @param ppaLeaves Pointer to the pointer to the array of sorted
910	* CPUID leaves and sub-leaves. Must be NULL if using
911	* the hyper heap.
912	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
913	* be NULL if using the hyper heap.
914	* @param pNewLeaf Pointer to the data of the new leaf we're about to
915	* insert.
916	*/
917	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
918	{
919	/*
920	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
921	*/
922	if (pVM)
923	{
924	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
925	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
926	AssertReturn(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 == pVM->cpum.s.GuestInfo.aCpuIdLeaves, VERR_INVALID_PARAMETER);
927
928	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
929	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
930	}
931
932	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
933	uint32_t cLeaves = *pcLeaves;
934
935	/*
936	* Validate the new leaf a little.
937	*/
938	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
939	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
940	VERR_INVALID_FLAGS);
941	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
942	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
943	VERR_INVALID_PARAMETER);
944	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
945	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
946	VERR_INVALID_PARAMETER);
947	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
948	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
949	VERR_INVALID_PARAMETER);
950
951	/*
952	* Find insertion point. The lazy bird uses the same excuse as in
953	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
954	*/
955	uint32_t i;
956	if ( cLeaves > 0
957	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
958	{
959	/* Add at end. */
960	i = cLeaves;
961	}
962	else if ( cLeaves > 0
963	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
964	{
965	/* Either replacing the last leaf or dealing with sub-leaves. Spool
966	back to the first sub-leaf to pretend we did the linear search. */
967	i = cLeaves - 1;
968	while ( i > 0
969	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
970	i--;
971	}
972	else
973	{
974	/* Linear search from the start. */
975	i = 0;
976	while ( i < cLeaves
977	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
978	i++;
979	}
980	if ( i < cLeaves
981	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
982	{
983	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
984	{
985	/*
986	* The sub-leaf mask differs, replace all existing leaves with the
987	* same leaf number.
988	*/
989	uint32_t c = 1;
990	while ( i + c < cLeaves
991	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
992	c++;
993	if (c > 1 && i + c < cLeaves)
994	{
995	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
996	*pcLeaves = cLeaves -= c - 1;
997	}
998
999	paLeaves[i] = *pNewLeaf;
1000	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1001	return VINF_SUCCESS;
1002	}
1003
1004	/* Find sub-leaf insertion point. */
1005	while ( i < cLeaves
1006	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
1007	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
1008	i++;
1009
1010	/*
1011	* If we've got an exactly matching leaf, replace it.
1012	*/
1013	if ( i < cLeaves
1014	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
1015	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
1016	{
1017	paLeaves[i] = *pNewLeaf;
1018	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1019	return VINF_SUCCESS;
1020	}
1021	}
1022
1023	/*
1024	* Adding a new leaf at 'i'.
1025	*/
1026	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
1027	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
1028	if (!paLeaves)
1029	return VERR_NO_MEMORY;
1030
1031	if (i < cLeaves)
1032	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
1033	*pcLeaves += 1;
1034	paLeaves[i] = *pNewLeaf;
1035
1036	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1037	return VINF_SUCCESS;
1038	}
1039
1040
1041	#ifndef IN_VBOX_CPU_REPORT
1042	/**
1043	* Removes a range of CPUID leaves.
1044	*
1045	* This will not reallocate the array.
1046	*
1047	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1048	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1049	* @param uFirst The first leaf.
1050	* @param uLast The last leaf.
1051	*/
1052	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1053	{
1054	uint32_t cLeaves = *pcLeaves;
1055
1056	Assert(uFirst <= uLast);
1057
1058	/*
1059	* Find the first one.
1060	*/
1061	uint32_t iFirst = 0;
1062	while ( iFirst < cLeaves
1063	&& paLeaves[iFirst].uLeaf < uFirst)
1064	iFirst++;
1065
1066	/*
1067	* Find the end (last + 1).
1068	*/
1069	uint32_t iEnd = iFirst;
1070	while ( iEnd < cLeaves
1071	&& paLeaves[iEnd].uLeaf <= uLast)
1072	iEnd++;
1073
1074	/*
1075	* Adjust the array if anything needs removing.
1076	*/
1077	if (iFirst < iEnd)
1078	{
1079	if (iEnd < cLeaves)
1080	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1081	*pcLeaves = cLeaves -= (iEnd - iFirst);
1082	}
1083
1084	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1085	}
1086	#endif /* IN_VBOX_CPU_REPORT */
1087
1088
1089	/**
1090	* Checks if ECX make a difference when reading a given CPUID leaf.
1091	*
1092	* @returns @c true if it does, @c false if it doesn't.
1093	* @param uLeaf The leaf we're reading.
1094	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1095	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1096	* final sub-leaf (for leaf 0xb only).
1097	*/
1098	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1099	{
1100	*pfFinalEcxUnchanged = false;
1101
1102	uint32_t auCur[4];
1103	uint32_t auPrev[4];
1104	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1105
1106	/* Look for sub-leaves. */
1107	uint32_t uSubLeaf = 1;
1108	for (;;)
1109	{
1110	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1111	if (memcmp(auCur, auPrev, sizeof(auCur)))
1112	break;
1113
1114	/* Advance / give up. */
1115	uSubLeaf++;
1116	if (uSubLeaf >= 64)
1117	{
1118	*pcSubLeaves = 1;
1119	return false;
1120	}
1121	}
1122
1123	/* Count sub-leaves. */
1124	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1125	uint32_t cRepeats = 0;
1126	uSubLeaf = 0;
1127	for (;;)
1128	{
1129	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1130
1131	/* Figuring out when to stop isn't entirely straight forward as we need
1132	to cover undocumented behavior up to a point and implementation shortcuts. */
1133
1134	/* 1. Look for more than 4 repeating value sets. */
1135	if ( auCur[0] == auPrev[0]
1136	&& auCur[1] == auPrev[1]
1137	&& ( auCur[2] == auPrev[2]
1138	\|\| ( auCur[2] == uSubLeaf
1139	&& auPrev[2] == uSubLeaf - 1) )
1140	&& auCur[3] == auPrev[3])
1141	{
1142	if ( uLeaf != 0xd
1143	\|\| uSubLeaf >= 64
1144	\|\| ( auCur[0] == 0
1145	&& auCur[1] == 0
1146	&& auCur[2] == 0
1147	&& auCur[3] == 0
1148	&& auPrev[2] == 0) )
1149	cRepeats++;
1150	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1151	break;
1152	}
1153	else
1154	cRepeats = 0;
1155
1156	/* 2. Look for zero values. */
1157	if ( auCur[0] == 0
1158	&& auCur[1] == 0
1159	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1160	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1161	&& uSubLeaf >= cMinLeaves)
1162	{
1163	cRepeats = 0;
1164	break;
1165	}
1166
1167	/* 3. Leaf 0xb level type 0 check. */
1168	if ( uLeaf == 0xb
1169	&& (auCur[2] & 0xff00) == 0
1170	&& (auPrev[2] & 0xff00) == 0)
1171	{
1172	cRepeats = 0;
1173	break;
1174	}
1175
1176	/* 99. Give up. */
1177	if (uSubLeaf >= 128)
1178	{
1179	#ifndef IN_VBOX_CPU_REPORT
1180	/* Ok, limit it according to the documentation if possible just to
1181	avoid annoying users with these detection issues. */
1182	uint32_t cDocLimit = UINT32_MAX;
1183	if (uLeaf == 0x4)
1184	cDocLimit = 4;
1185	else if (uLeaf == 0x7)
1186	cDocLimit = 1;
1187	else if (uLeaf == 0xd)
1188	cDocLimit = 63;
1189	else if (uLeaf == 0xf)
1190	cDocLimit = 2;
1191	if (cDocLimit != UINT32_MAX)
1192	{
1193	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1194	*pcSubLeaves = cDocLimit + 3;
1195	return true;
1196	}
1197	#endif
1198	*pcSubLeaves = UINT32_MAX;
1199	return true;
1200	}
1201
1202	/* Advance. */
1203	uSubLeaf++;
1204	memcpy(auPrev, auCur, sizeof(auCur));
1205	}
1206
1207	/* Standard exit. */
1208	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1209	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1210	if (*pcSubLeaves == 0)
1211	*pcSubLeaves = 1;
1212	return true;
1213	}
1214
1215
1216	/**
1217	* Gets a CPU ID leaf.
1218	*
1219	* @returns VBox status code.
1220	* @param pVM The cross context VM structure.
1221	* @param pLeaf Where to store the found leaf.
1222	* @param uLeaf The leaf to locate.
1223	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1224	*/
1225	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1226	{
1227	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1228	uLeaf, uSubLeaf);
1229	if (pcLeaf)
1230	{
1231	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1232	return VINF_SUCCESS;
1233	}
1234
1235	return VERR_NOT_FOUND;
1236	}
1237
1238
1239	/**
1240	* Inserts a CPU ID leaf, replacing any existing ones.
1241	*
1242	* @returns VBox status code.
1243	* @param pVM The cross context VM structure.
1244	* @param pNewLeaf Pointer to the leaf being inserted.
1245	*/
1246	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1247	{
1248	/*
1249	* Validate parameters.
1250	*/
1251	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1252	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1253
1254	/*
1255	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1256	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1257	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1258	*/
1259	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1260	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1261	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1262	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1263	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1264	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1265	{
1266	return VERR_NOT_SUPPORTED;
1267	}
1268
1269	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1270	}
1271
1272	/**
1273	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1274	*
1275	* @returns VBox status code.
1276	* @param ppaLeaves Where to return the array pointer on success.
1277	* Use RTMemFree to release.
1278	* @param pcLeaves Where to return the size of the array on
1279	* success.
1280	*/
1281	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1282	{
1283	*ppaLeaves = NULL;
1284	*pcLeaves = 0;
1285
1286	/*
1287	* Try out various candidates. This must be sorted!
1288	*/
1289	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1290	{
1291	{ UINT32_C(0x00000000), false },
1292	{ UINT32_C(0x10000000), false },
1293	{ UINT32_C(0x20000000), false },
1294	{ UINT32_C(0x30000000), false },
1295	{ UINT32_C(0x40000000), false },
1296	{ UINT32_C(0x50000000), false },
1297	{ UINT32_C(0x60000000), false },
1298	{ UINT32_C(0x70000000), false },
1299	{ UINT32_C(0x80000000), false },
1300	{ UINT32_C(0x80860000), false },
1301	{ UINT32_C(0x8ffffffe), true },
1302	{ UINT32_C(0x8fffffff), true },
1303	{ UINT32_C(0x90000000), false },
1304	{ UINT32_C(0xa0000000), false },
1305	{ UINT32_C(0xb0000000), false },
1306	{ UINT32_C(0xc0000000), false },
1307	{ UINT32_C(0xd0000000), false },
1308	{ UINT32_C(0xe0000000), false },
1309	{ UINT32_C(0xf0000000), false },
1310	};
1311
1312	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1313	{
1314	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1315	uint32_t uEax, uEbx, uEcx, uEdx;
1316	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1317
1318	/*
1319	* Does EAX look like a typical leaf count value?
1320	*/
1321	if ( uEax > uLeaf
1322	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1323	{
1324	/* Yes, dump them. */
1325	uint32_t cLeaves = uEax - uLeaf + 1;
1326	while (cLeaves-- > 0)
1327	{
1328	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1329
1330	uint32_t fFlags = 0;
1331
1332	/* There are currently three known leaves containing an APIC ID
1333	that needs EMT specific attention */
1334	if (uLeaf == 1)
1335	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1336	else if (uLeaf == 0xb && uEcx != 0)
1337	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1338	else if ( uLeaf == UINT32_C(0x8000001e)
1339	&& ( uEax
1340	\|\| uEbx
1341	\|\| uEdx
1342	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1343	\|\| ASMIsHygonCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1344	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1345
1346	/* The APIC bit is per-VCpu and needs flagging. */
1347	if (uLeaf == 1)
1348	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1349	else if ( uLeaf == UINT32_C(0x80000001)
1350	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1351	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1352	\|\| ASMIsHygonCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1353	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1354
1355	/* Check three times here to reduce the chance of CPU migration
1356	resulting in false positives with things like the APIC ID. */
1357	uint32_t cSubLeaves;
1358	bool fFinalEcxUnchanged;
1359	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1360	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1361	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1362	{
1363	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1364	{
1365	/* This shouldn't happen. But in case it does, file all
1366	relevant details in the release log. */
1367	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1368	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1369	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1370	{
1371	uint32_t auTmp[4];
1372	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1373	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1374	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1375	}
1376	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1377	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1378	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1379	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1380	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1381	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1382	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1383	}
1384
1385	if (fFinalEcxUnchanged)
1386	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1387
1388	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1389	{
1390	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1391	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1392	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1393	if (RT_FAILURE(rc))
1394	return rc;
1395	}
1396	}
1397	else
1398	{
1399	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1400	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1401	if (RT_FAILURE(rc))
1402	return rc;
1403	}
1404
1405	/* next */
1406	uLeaf++;
1407	}
1408	}
1409	/*
1410	* Special CPUIDs needs special handling as they don't follow the
1411	* leaf count principle used above.
1412	*/
1413	else if (s_aCandidates[iOuter].fSpecial)
1414	{
1415	bool fKeep = false;
1416	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1417	fKeep = true;
1418	else if ( uLeaf == 0x8fffffff
1419	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1420	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1421	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1422	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1423	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1424	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1425	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1426	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1427	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1428	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1429	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1430	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1431	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1432	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1433	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1434	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1435	fKeep = true;
1436	if (fKeep)
1437	{
1438	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1439	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1440	if (RT_FAILURE(rc))
1441	return rc;
1442	}
1443	}
1444	}
1445
1446	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1447	return VINF_SUCCESS;
1448	}
1449
1450
1451	/**
1452	* Determines the method the CPU uses to handle unknown CPUID leaves.
1453	*
1454	* @returns VBox status code.
1455	* @param penmUnknownMethod Where to return the method.
1456	* @param pDefUnknown Where to return default unknown values. This
1457	* will be set, even if the resulting method
1458	* doesn't actually needs it.
1459	*/
1460	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1461	{
1462	uint32_t uLastStd = ASMCpuId_EAX(0);
1463	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1464	if (!ASMIsValidExtRange(uLastExt))
1465	uLastExt = 0x80000000;
1466
1467	uint32_t auChecks[] =
1468	{
1469	uLastStd + 1,
1470	uLastStd + 5,
1471	uLastStd + 8,
1472	uLastStd + 32,
1473	uLastStd + 251,
1474	uLastExt + 1,
1475	uLastExt + 8,
1476	uLastExt + 15,
1477	uLastExt + 63,
1478	uLastExt + 255,
1479	0x7fbbffcc,
1480	0x833f7872,
1481	0xefff2353,
1482	0x35779456,
1483	0x1ef6d33e,
1484	};
1485
1486	static const uint32_t s_auValues[] =
1487	{
1488	0xa95d2156,
1489	0x00000001,
1490	0x00000002,
1491	0x00000008,
1492	0x00000000,
1493	0x55773399,
1494	0x93401769,
1495	0x12039587,
1496	};
1497
1498	/*
1499	* Simple method, all zeros.
1500	*/
1501	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1502	pDefUnknown->uEax = 0;
1503	pDefUnknown->uEbx = 0;
1504	pDefUnknown->uEcx = 0;
1505	pDefUnknown->uEdx = 0;
1506
1507	/*
1508	* Intel has been observed returning the last standard leaf.
1509	*/
1510	uint32_t auLast[4];
1511	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1512
1513	uint32_t cChecks = RT_ELEMENTS(auChecks);
1514	while (cChecks > 0)
1515	{
1516	uint32_t auCur[4];
1517	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1518	if (memcmp(auCur, auLast, sizeof(auCur)))
1519	break;
1520	cChecks--;
1521	}
1522	if (cChecks == 0)
1523	{
1524	/* Now, what happens when the input changes? Esp. ECX. */
1525	uint32_t cTotal = 0;
1526	uint32_t cSame = 0;
1527	uint32_t cLastWithEcx = 0;
1528	uint32_t cNeither = 0;
1529	uint32_t cValues = RT_ELEMENTS(s_auValues);
1530	while (cValues > 0)
1531	{
1532	uint32_t uValue = s_auValues[cValues - 1];
1533	uint32_t auLastWithEcx[4];
1534	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1535	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1536
1537	cChecks = RT_ELEMENTS(auChecks);
1538	while (cChecks > 0)
1539	{
1540	uint32_t auCur[4];
1541	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1542	if (!memcmp(auCur, auLast, sizeof(auCur)))
1543	{
1544	cSame++;
1545	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1546	cLastWithEcx++;
1547	}
1548	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1549	cLastWithEcx++;
1550	else
1551	cNeither++;
1552	cTotal++;
1553	cChecks--;
1554	}
1555	cValues--;
1556	}
1557
1558	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1559	if (cSame == cTotal)
1560	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1561	else if (cLastWithEcx == cTotal)
1562	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1563	else
1564	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1565	pDefUnknown->uEax = auLast[0];
1566	pDefUnknown->uEbx = auLast[1];
1567	pDefUnknown->uEcx = auLast[2];
1568	pDefUnknown->uEdx = auLast[3];
1569	return VINF_SUCCESS;
1570	}
1571
1572	/*
1573	* Unchanged register values?
1574	*/
1575	cChecks = RT_ELEMENTS(auChecks);
1576	while (cChecks > 0)
1577	{
1578	uint32_t const uLeaf = auChecks[cChecks - 1];
1579	uint32_t cValues = RT_ELEMENTS(s_auValues);
1580	while (cValues > 0)
1581	{
1582	uint32_t uValue = s_auValues[cValues - 1];
1583	uint32_t auCur[4];
1584	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1585	if ( auCur[0] != uLeaf
1586	\|\| auCur[1] != uValue
1587	\|\| auCur[2] != uValue
1588	\|\| auCur[3] != uValue)
1589	break;
1590	cValues--;
1591	}
1592	if (cValues != 0)
1593	break;
1594	cChecks--;
1595	}
1596	if (cChecks == 0)
1597	{
1598	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1599	return VINF_SUCCESS;
1600	}
1601
1602	/*
1603	* Just go with the simple method.
1604	*/
1605	return VINF_SUCCESS;
1606	}
1607
1608
1609	/**
1610	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1611	*
1612	* @returns Read only name string.
1613	* @param enmUnknownMethod The method to translate.
1614	*/
1615	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1616	{
1617	switch (enmUnknownMethod)
1618	{
1619	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1620	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1621	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1622	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1623
1624	case CPUMUNKNOWNCPUID_INVALID:
1625	case CPUMUNKNOWNCPUID_END:
1626	case CPUMUNKNOWNCPUID_32BIT_HACK:
1627	break;
1628	}
1629	return "Invalid-unknown-CPUID-method";
1630	}
1631
1632
1633	/**
1634	* Detect the CPU vendor give n the
1635	*
1636	* @returns The vendor.
1637	* @param uEAX EAX from CPUID(0).
1638	* @param uEBX EBX from CPUID(0).
1639	* @param uECX ECX from CPUID(0).
1640	* @param uEDX EDX from CPUID(0).
1641	*/
1642	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1643	{
1644	if (ASMIsValidStdRange(uEAX))
1645	{
1646	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1647	return CPUMCPUVENDOR_AMD;
1648
1649	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1650	return CPUMCPUVENDOR_INTEL;
1651
1652	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1653	return CPUMCPUVENDOR_VIA;
1654
1655	if (ASMIsShanghaiCpuEx(uEBX, uECX, uEDX))
1656	return CPUMCPUVENDOR_SHANGHAI;
1657
1658	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1659	&& uECX == UINT32_C(0x64616574)
1660	&& uEDX == UINT32_C(0x736E4978))
1661	return CPUMCPUVENDOR_CYRIX;
1662
1663	if (ASMIsHygonCpuEx(uEBX, uECX, uEDX))
1664	return CPUMCPUVENDOR_HYGON;
1665
1666	/* "Geode by NSC", example: family 5, model 9. */
1667
1668	/** @todo detect the other buggers... */
1669	}
1670
1671	return CPUMCPUVENDOR_UNKNOWN;
1672	}
1673
1674
1675	/**
1676	* Translates a CPU vendor enum value into the corresponding string constant.
1677	*
1678	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1679	* value name. This can be useful when generating code.
1680	*
1681	* @returns Read only name string.
1682	* @param enmVendor The CPU vendor value.
1683	*/
1684	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1685	{
1686	switch (enmVendor)
1687	{
1688	case CPUMCPUVENDOR_INTEL: return "INTEL";
1689	case CPUMCPUVENDOR_AMD: return "AMD";
1690	case CPUMCPUVENDOR_VIA: return "VIA";
1691	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1692	case CPUMCPUVENDOR_SHANGHAI: return "SHANGHAI";
1693	case CPUMCPUVENDOR_HYGON: return "HYGON";
1694	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1695
1696	case CPUMCPUVENDOR_INVALID:
1697	case CPUMCPUVENDOR_32BIT_HACK:
1698	break;
1699	}
1700	return "Invalid-cpu-vendor";
1701	}
1702
1703
1704	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1705	{
1706	/* Could do binary search, doing linear now because I'm lazy. */
1707	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1708	while (cLeaves-- > 0)
1709	{
1710	if (pLeaf->uLeaf == uLeaf)
1711	return pLeaf;
1712	pLeaf++;
1713	}
1714	return NULL;
1715	}
1716
1717
1718	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1719	{
1720	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1721	if ( !pLeaf
1722	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1723	return pLeaf;
1724
1725	/* Linear sub-leaf search. Lazy as usual. */
1726	cLeaves -= pLeaf - paLeaves;
1727	while ( cLeaves-- > 0
1728	&& pLeaf->uLeaf == uLeaf)
1729	{
1730	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1731	return pLeaf;
1732	pLeaf++;
1733	}
1734
1735	return NULL;
1736	}
1737
1738
1739	static void cpumR3ExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURES pFeatures)
1740	{
1741	Assert(pVmxMsrs);
1742	Assert(pFeatures);
1743	Assert(pFeatures->fVmx);
1744
1745	/* Basic information. */
1746	{
1747	uint64_t const u64Basic = pVmxMsrs->u64Basic;
1748	pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1749	}
1750
1751	/* Pin-based VM-execution controls. */
1752	{
1753	uint32_t const fPinCtls = pVmxMsrs->PinCtls.n.allowed1;
1754	pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1755	pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1756	pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1757	pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1758	pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1759	}
1760
1761	/* Processor-based VM-execution controls. */
1762	{
1763	uint32_t const fProcCtls = pVmxMsrs->ProcCtls.n.allowed1;
1764	pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1765	pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1766	pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1767	pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1768	pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1769	pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1770	pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1771	pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1772	pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1773	pFeatures->fVmxTertiaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1774	pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1775	pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1776	pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1777	pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1778	pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1779	pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1780	pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1781	pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1782	pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1783	pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1784	pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1785	pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1786	}
1787
1788	/* Secondary processor-based VM-execution controls. */
1789	{
1790	uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1791	pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1792	pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1793	pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1794	pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1795	pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1796	pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1797	pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1798	pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1799	pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1800	pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1801	pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1802	pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1803	pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1804	pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1805	pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1806	pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1807	pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1808	pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE);
1809	pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1810	pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1811	}
1812
1813	/* Tertiary processor-based VM-execution controls. */
1814	{
1815	uint64_t const fProcCtls3 = pFeatures->fVmxTertiaryExecCtls ? pVmxMsrs->u64ProcCtls3 : 0;
1816	pFeatures->fVmxLoadIwKeyExit = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT);
1817	}
1818
1819	/* VM-exit controls. */
1820	{
1821	uint32_t const fExitCtls = pVmxMsrs->ExitCtls.n.allowed1;
1822	pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1823	pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1824	pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1825	pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1826	pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1827	pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1828	pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1829	pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1830	}
1831
1832	/* VM-entry controls. */
1833	{
1834	uint32_t const fEntryCtls = pVmxMsrs->EntryCtls.n.allowed1;
1835	pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1836	pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1837	pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1838	pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1839	}
1840
1841	/* Miscellaneous data. */
1842	{
1843	uint32_t const fMiscData = pVmxMsrs->u64Misc;
1844	pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1845	pFeatures->fVmxIntelPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1846	pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1847	pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1848	}
1849	}
1850
1851
1852	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures)
1853	{
1854	Assert(pMsrs);
1855	RT_ZERO(*pFeatures);
1856	if (cLeaves >= 2)
1857	{
1858	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1859	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1860	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1861	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1862	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1863	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1864
1865	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1866	pStd0Leaf->uEbx,
1867	pStd0Leaf->uEcx,
1868	pStd0Leaf->uEdx);
1869	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1870	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1871	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1872	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1873	pFeatures->uFamily,
1874	pFeatures->uModel,
1875	pFeatures->uStepping);
1876
1877	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1878	if (pExtLeaf8)
1879	{
1880	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1881	pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1882	}
1883	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1884	{
1885	pFeatures->cMaxPhysAddrWidth = 36;
1886	pFeatures->cMaxLinearAddrWidth = 36;
1887	}
1888	else
1889	{
1890	pFeatures->cMaxPhysAddrWidth = 32;
1891	pFeatures->cMaxLinearAddrWidth = 32;
1892	}
1893
1894	/* Standard features. */
1895	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1896	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1897	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1898	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1899	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1900	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1901	pFeatures->fPge = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PGE);
1902	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1903	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1904	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1905	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1906	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1907	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1908	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1909	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1910	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1911	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1912	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1913	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1914	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1915	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1916	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1917	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1918	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1919	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1920	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1921	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1922	if (pFeatures->fVmx)
1923	cpumR3ExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1924
1925	/* Structured extended features. */
1926	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1927	if (pSxfLeaf0)
1928	{
1929	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1930	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1931	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1932	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1933	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1934
1935	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1936	pFeatures->fIbrs = pFeatures->fIbpb;
1937	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1938	pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
1939	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1940	pFeatures->fMdsClear = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
1941	}
1942
1943	/* MWAIT/MONITOR leaf. */
1944	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1945	if (pMWaitLeaf)
1946	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1947	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1948
1949	/* Extended features. */
1950	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1951	if (pExtLeaf)
1952	{
1953	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1954	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1955	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1956	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1957	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1958	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1959	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1960	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1961	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1962	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1963	}
1964
1965	/* VMX (VMXON, VMCS region and related data structures) physical address width (depends on long-mode). */
1966	pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
1967
1968	if ( pExtLeaf
1969	&& ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1970	\|\| pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON))
1971	{
1972	/* AMD features. */
1973	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1974	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1975	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1976	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1977	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1978	pFeatures->fPge \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PGE);
1979	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1980	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1981	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1982	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1983	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1984	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1985	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1986	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1987	if (pFeatures->fSvm)
1988	{
1989	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1990	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1991	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1992	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1993	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1994	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1995	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1996	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1997	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1998	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1999	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
2000	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
2001	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
2002	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
2003	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
2004	pFeatures->fSvmGmet = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_GMET);
2005	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
2006	}
2007	}
2008
2009	/*
2010	* Quirks.
2011	*/
2012	pFeatures->fLeakyFxSR = pExtLeaf
2013	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2014	&& ( ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
2015	&& pFeatures->uFamily >= 6 /* K7 and up */)
2016	\|\| pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON);
2017
2018	/*
2019	* Max extended (/FPU) state.
2020	*/
2021	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
2022	if (pFeatures->fXSaveRstor)
2023	{
2024	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
2025	if (pXStateLeaf0)
2026	{
2027	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
2028	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
2029	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
2030	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
2031	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
2032	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
2033	{
2034	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
2035
2036	/* (paranoia:) */
2037	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
2038	if ( pXStateLeaf1
2039	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
2040	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
2041	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
2042	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
2043	}
2044	else
2045	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
2046	pFeatures->fXSaveRstor = 0);
2047	}
2048	else
2049	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
2050	pFeatures->fXSaveRstor = 0);
2051	}
2052	}
2053	else
2054	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
2055	return VINF_SUCCESS;
2056	}
2057
2058
2059	/*
2060	*
2061	* Init related code.
2062	* Init related code.
2063	* Init related code.
2064	*
2065	*
2066	*/
2067	#ifndef IN_VBOX_CPU_REPORT
2068
2069
2070	/**
2071	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
2072	*
2073	* This ignores the fSubLeafMask.
2074	*
2075	* @returns Pointer to the matching leaf, or NULL if not found.
2076	* @param pCpum The CPUM instance data.
2077	* @param uLeaf The leaf to locate.
2078	* @param uSubLeaf The subleaf to locate.
2079	*/
2080	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
2081	{
2082	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
2083	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
2084	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
2085	if (iEnd)
2086	{
2087	uint32_t iBegin = 0;
2088	for (;;)
2089	{
2090	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
2091	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
2092	if (uNeedle < uCur)
2093	{
2094	if (i > iBegin)
2095	iEnd = i;
2096	else
2097	break;
2098	}
2099	else if (uNeedle > uCur)
2100	{
2101	if (i + 1 < iEnd)
2102	iBegin = i + 1;
2103	else
2104	break;
2105	}
2106	else
2107	return &paLeaves[i];
2108	}
2109	}
2110	return NULL;
2111	}
2112
2113
2114	/**
2115	* Loads MSR range overrides.
2116	*
2117	* This must be called before the MSR ranges are moved from the normal heap to
2118	* the hyper heap!
2119	*
2120	* @returns VBox status code (VMSetError called).
2121	* @param pVM The cross context VM structure.
2122	* @param pMsrNode The CFGM node with the MSR overrides.
2123	*/
2124	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
2125	{
2126	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2127	{
2128	/*
2129	* Assemble a valid MSR range.
2130	*/
2131	CPUMMSRRANGE MsrRange;
2132	MsrRange.offCpumCpu = 0;
2133	MsrRange.fReserved = 0;
2134
2135	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
2136	if (RT_FAILURE(rc))
2137	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
2138
2139	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
2140	if (RT_FAILURE(rc))
2141	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
2142	MsrRange.szName, rc);
2143
2144	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
2145	if (RT_FAILURE(rc))
2146	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
2147	MsrRange.szName, rc);
2148
2149	char szType[32];
2150	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
2151	if (RT_FAILURE(rc))
2152	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
2153	MsrRange.szName, rc);
2154	if (!RTStrICmp(szType, "FixedValue"))
2155	{
2156	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
2157	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
2158
2159	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
2160	if (RT_FAILURE(rc))
2161	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
2162	MsrRange.szName, rc);
2163
2164	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
2165	if (RT_FAILURE(rc))
2166	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
2167	MsrRange.szName, rc);
2168
2169	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
2170	if (RT_FAILURE(rc))
2171	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
2172	MsrRange.szName, rc);
2173	}
2174	else
2175	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
2176	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
2177
2178	/*
2179	* Insert the range into the table (replaces/splits/shrinks existing
2180	* MSR ranges).
2181	*/
2182	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
2183	&MsrRange);
2184	if (RT_FAILURE(rc))
2185	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
2186	}
2187
2188	return VINF_SUCCESS;
2189	}
2190
2191
2192	/**
2193	* Loads CPUID leaf overrides.
2194	*
2195	* This must be called before the CPUID leaves are moved from the normal
2196	* heap to the hyper heap!
2197	*
2198	* @returns VBox status code (VMSetError called).
2199	* @param pVM The cross context VM structure.
2200	* @param pParentNode The CFGM node with the CPUID leaves.
2201	* @param pszLabel How to label the overrides we're loading.
2202	*/
2203	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2204	{
2205	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2206	{
2207	/*
2208	* Get the leaf and subleaf numbers.
2209	*/
2210	char szName[128];
2211	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2212	if (RT_FAILURE(rc))
2213	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2214
2215	/* The leaf number is either specified directly or thru the node name. */
2216	uint32_t uLeaf;
2217	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2218	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2219	{
2220	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2221	if (rc != VINF_SUCCESS)
2222	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2223	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2224	}
2225	else if (RT_FAILURE(rc))
2226	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2227	pszLabel, szName, rc);
2228
2229	uint32_t uSubLeaf;
2230	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2231	if (RT_FAILURE(rc))
2232	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2233	pszLabel, szName, rc);
2234
2235	uint32_t fSubLeafMask;
2236	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2237	if (RT_FAILURE(rc))
2238	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2239	pszLabel, szName, rc);
2240
2241	/*
2242	* Look up the specified leaf, since the output register values
2243	* defaults to any existing values. This allows overriding a single
2244	* register, without needing to know the other values.
2245	*/
2246	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2247	CPUMCPUIDLEAF Leaf;
2248	if (pLeaf)
2249	Leaf = *pLeaf;
2250	else
2251	RT_ZERO(Leaf);
2252	Leaf.uLeaf = uLeaf;
2253	Leaf.uSubLeaf = uSubLeaf;
2254	Leaf.fSubLeafMask = fSubLeafMask;
2255
2256	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2257	if (RT_FAILURE(rc))
2258	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2259	pszLabel, szName, rc);
2260	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2261	if (RT_FAILURE(rc))
2262	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2263	pszLabel, szName, rc);
2264	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2265	if (RT_FAILURE(rc))
2266	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2267	pszLabel, szName, rc);
2268	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2269	if (RT_FAILURE(rc))
2270	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2271	pszLabel, szName, rc);
2272
2273	/*
2274	* Insert the leaf into the table (replaces existing ones).
2275	*/
2276	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2277	&Leaf);
2278	if (RT_FAILURE(rc))
2279	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2280	}
2281
2282	return VINF_SUCCESS;
2283	}
2284
2285
2286
2287	/**
2288	* Fetches overrides for a CPUID leaf.
2289	*
2290	* @returns VBox status code.
2291	* @param pLeaf The leaf to load the overrides into.
2292	* @param pCfgNode The CFGM node containing the overrides
2293	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2294	* @param iLeaf The CPUID leaf number.
2295	*/
2296	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2297	{
2298	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2299	if (pLeafNode)
2300	{
2301	uint32_t u32;
2302	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2303	if (RT_SUCCESS(rc))
2304	pLeaf->uEax = u32;
2305	else
2306	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2307
2308	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2309	if (RT_SUCCESS(rc))
2310	pLeaf->uEbx = u32;
2311	else
2312	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2313
2314	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2315	if (RT_SUCCESS(rc))
2316	pLeaf->uEcx = u32;
2317	else
2318	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2319
2320	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2321	if (RT_SUCCESS(rc))
2322	pLeaf->uEdx = u32;
2323	else
2324	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2325
2326	}
2327	return VINF_SUCCESS;
2328	}
2329
2330
2331	/**
2332	* Load the overrides for a set of CPUID leaves.
2333	*
2334	* @returns VBox status code.
2335	* @param paLeaves The leaf array.
2336	* @param cLeaves The number of leaves.
2337	* @param uStart The start leaf number.
2338	* @param pCfgNode The CFGM node containing the overrides
2339	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2340	*/
2341	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2342	{
2343	for (uint32_t i = 0; i < cLeaves; i++)
2344	{
2345	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2346	if (RT_FAILURE(rc))
2347	return rc;
2348	}
2349
2350	return VINF_SUCCESS;
2351	}
2352
2353
2354	/**
2355	* Installs the CPUID leaves and explods the data into structures like
2356	* GuestFeatures and CPUMCTX::aoffXState.
2357	*
2358	* @returns VBox status code.
2359	* @param pVM The cross context VM structure.
2360	* @param pCpum The CPUM part of @a VM.
2361	* @param paLeaves The leaves. These will be copied (but not freed).
2362	* @param cLeaves The number of leaves.
2363	* @param pMsrs The MSRs.
2364	*/
2365	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
2366	{
2367	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2368
2369	/*
2370	* Install the CPUID information.
2371	*/
2372	AssertLogRelMsgReturn(cLeaves <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves),
2373	("cLeaves=%u - max %u\n", cLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves)),
2374	VERR_CPUM_IPE_1); /** @todo better status! */
2375	if (paLeaves != pCpum->GuestInfo.aCpuIdLeaves)
2376	memcpy(pCpum->GuestInfo.aCpuIdLeaves, paLeaves, cLeaves * sizeof(paLeaves[0]));
2377	pCpum->GuestInfo.paCpuIdLeavesR3 = pCpum->GuestInfo.aCpuIdLeaves;
2378	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2379
2380	/*
2381	* Update the default CPUID leaf if necessary.
2382	*/
2383	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2384	{
2385	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2386	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2387	{
2388	/* We don't use CPUID(0).eax here because of the NT hack that only
2389	changes that value without actually removing any leaves. */
2390	uint32_t i = 0;
2391	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2392	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2393	{
2394	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2395	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2396	i++;
2397	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2398	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2399	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2400	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2401	}
2402	break;
2403	}
2404	default:
2405	break;
2406	}
2407
2408	/*
2409	* Explode the guest CPU features.
2410	*/
2411	int rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
2412	&pCpum->GuestFeatures);
2413	AssertLogRelRCReturn(rc, rc);
2414
2415	/*
2416	* Adjust the scalable bus frequency according to the CPUID information
2417	* we're now using.
2418	*/
2419	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2420	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2421	? UINT64_C(100000000) /* 100MHz */
2422	: UINT64_C(133333333); /* 133MHz */
2423
2424	/*
2425	* Populate the legacy arrays. Currently used for everything, later only
2426	* for patch manager.
2427	*/
2428	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2429	{
2430	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2431	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2432	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2433	};
2434	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2435	{
2436	uint32_t cLeft = aOldRanges[i].cCpuIds;
2437	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2438	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2439	while (cLeft-- > 0)
2440	{
2441	uLeaf--;
2442	pLegacyLeaf--;
2443
2444	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2445	if (pLeaf)
2446	{
2447	pLegacyLeaf->uEax = pLeaf->uEax;
2448	pLegacyLeaf->uEbx = pLeaf->uEbx;
2449	pLegacyLeaf->uEcx = pLeaf->uEcx;
2450	pLegacyLeaf->uEdx = pLeaf->uEdx;
2451	}
2452	else
2453	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2454	}
2455	}
2456
2457	/*
2458	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2459	*/
2460	PVMCPU pVCpu0 = pVM->apCpusR3[0];
2461	AssertCompile(sizeof(pVCpu0->cpum.s.Guest.abXState) == CPUM_MAX_XSAVE_AREA_SIZE);
2462	memset(&pVCpu0->cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2463	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2464	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2465	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2466	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2467	{
2468	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2469	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2470	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2471	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2472	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2473	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2474	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2475	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2476	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2477	pCpum->GuestFeatures.cbMaxExtendedState),
2478	VERR_CPUM_IPE_1);
2479	pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2480	}
2481
2482	/* Copy the CPU #0 data to the other CPUs. */
2483	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
2484	{
2485	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2486	memcpy(&pVCpu->cpum.s.Guest.aoffXState[0], &pVCpu0->cpum.s.Guest.aoffXState[0], sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2487	}
2488
2489	return VINF_SUCCESS;
2490	}
2491
2492
2493	/** @name Instruction Set Extension Options
2494	* @{ */
2495	/** Configuration option type (extended boolean, really). */
2496	typedef uint8_t CPUMISAEXTCFG;
2497	/** Always disable the extension. */
2498	#define CPUMISAEXTCFG_DISABLED false
2499	/** Enable the extension if it's supported by the host CPU. */
2500	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2501	/** Enable the extension if it's supported by the host CPU, but don't let
2502	* the portable CPUID feature disable it. */
2503	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2504	/** Always enable the extension. */
2505	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2506	/** @} */
2507
2508	/**
2509	* CPUID Configuration (from CFGM).
2510	*
2511	* @remarks The members aren't document since we would only be duplicating the
2512	* \@cfgm entries in cpumR3CpuIdReadConfig.
2513	*/
2514	typedef struct CPUMCPUIDCONFIG
2515	{
2516	bool fNt4LeafLimit;
2517	bool fInvariantTsc;
2518	bool fForceVme;
2519	bool fNestedHWVirt;
2520
2521	CPUMISAEXTCFG enmCmpXchg16b;
2522	CPUMISAEXTCFG enmMonitor;
2523	CPUMISAEXTCFG enmMWaitExtensions;
2524	CPUMISAEXTCFG enmSse41;
2525	CPUMISAEXTCFG enmSse42;
2526	CPUMISAEXTCFG enmAvx;
2527	CPUMISAEXTCFG enmAvx2;
2528	CPUMISAEXTCFG enmXSave;
2529	CPUMISAEXTCFG enmAesNi;
2530	CPUMISAEXTCFG enmPClMul;
2531	CPUMISAEXTCFG enmPopCnt;
2532	CPUMISAEXTCFG enmMovBe;
2533	CPUMISAEXTCFG enmRdRand;
2534	CPUMISAEXTCFG enmRdSeed;
2535	CPUMISAEXTCFG enmCLFlushOpt;
2536	CPUMISAEXTCFG enmFsGsBase;
2537	CPUMISAEXTCFG enmPcid;
2538	CPUMISAEXTCFG enmInvpcid;
2539	CPUMISAEXTCFG enmFlushCmdMsr;
2540	CPUMISAEXTCFG enmMdsClear;
2541	CPUMISAEXTCFG enmArchCapMsr;
2542
2543	CPUMISAEXTCFG enmAbm;
2544	CPUMISAEXTCFG enmSse4A;
2545	CPUMISAEXTCFG enmMisAlnSse;
2546	CPUMISAEXTCFG enm3dNowPrf;
2547	CPUMISAEXTCFG enmAmdExtMmx;
2548
2549	uint32_t uMaxStdLeaf;
2550	uint32_t uMaxExtLeaf;
2551	uint32_t uMaxCentaurLeaf;
2552	uint32_t uMaxIntelFamilyModelStep;
2553	char szCpuName[128];
2554	} CPUMCPUIDCONFIG;
2555	/** Pointer to CPUID config (from CFGM). */
2556	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2557
2558
2559	/**
2560	* Mini CPU selection support for making Mac OS X happy.
2561	*
2562	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2563	*
2564	* @param pCpum The CPUM instance data.
2565	* @param pConfig The CPUID configuration we've read from CFGM.
2566	*/
2567	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2568	{
2569	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2570	{
2571	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2572	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2573	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2574	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2575	0);
2576	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2577	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2578	{
2579	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2580	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2581	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2582	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2583	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2584	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2585	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2586	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2587	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2588	pStdFeatureLeaf->uEax = uNew;
2589	}
2590	}
2591	}
2592
2593
2594
2595	/**
2596	* Limit it the number of entries, zapping the remainder.
2597	*
2598	* The limits are masking off stuff about power saving and similar, this
2599	* is perhaps a bit crudely done as there is probably some relatively harmless
2600	* info too in these leaves (like words about having a constant TSC).
2601	*
2602	* @param pCpum The CPUM instance data.
2603	* @param pConfig The CPUID configuration we've read from CFGM.
2604	*/
2605	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2606	{
2607	/*
2608	* Standard leaves.
2609	*/
2610	uint32_t uSubLeaf = 0;
2611	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2612	if (pCurLeaf)
2613	{
2614	uint32_t uLimit = pCurLeaf->uEax;
2615	if (uLimit <= UINT32_C(0x000fffff))
2616	{
2617	if (uLimit > pConfig->uMaxStdLeaf)
2618	{
2619	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2620	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2621	uLimit + 1, UINT32_C(0x000fffff));
2622	}
2623
2624	/* NT4 hack, no zapping of extra leaves here. */
2625	if (pConfig->fNt4LeafLimit && uLimit > 3)
2626	pCurLeaf->uEax = uLimit = 3;
2627
2628	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2629	pCurLeaf->uEax = uLimit;
2630	}
2631	else
2632	{
2633	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2634	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2635	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2636	}
2637	}
2638
2639	/*
2640	* Extended leaves.
2641	*/
2642	uSubLeaf = 0;
2643	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2644	if (pCurLeaf)
2645	{
2646	uint32_t uLimit = pCurLeaf->uEax;
2647	if ( uLimit >= UINT32_C(0x80000000)
2648	&& uLimit <= UINT32_C(0x800fffff))
2649	{
2650	if (uLimit > pConfig->uMaxExtLeaf)
2651	{
2652	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2653	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2654	uLimit + 1, UINT32_C(0x800fffff));
2655	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2656	pCurLeaf->uEax = uLimit;
2657	}
2658	}
2659	else
2660	{
2661	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2662	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2663	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2664	}
2665	}
2666
2667	/*
2668	* Centaur leaves (VIA).
2669	*/
2670	uSubLeaf = 0;
2671	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2672	if (pCurLeaf)
2673	{
2674	uint32_t uLimit = pCurLeaf->uEax;
2675	if ( uLimit >= UINT32_C(0xc0000000)
2676	&& uLimit <= UINT32_C(0xc00fffff))
2677	{
2678	if (uLimit > pConfig->uMaxCentaurLeaf)
2679	{
2680	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2681	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2682	uLimit + 1, UINT32_C(0xcfffffff));
2683	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2684	pCurLeaf->uEax = uLimit;
2685	}
2686	}
2687	else
2688	{
2689	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2690	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2691	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2692	}
2693	}
2694	}
2695
2696
2697	/**
2698	* Clears a CPUID leaf and all sub-leaves (to zero).
2699	*
2700	* @param pCpum The CPUM instance data.
2701	* @param uLeaf The leaf to clear.
2702	*/
2703	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2704	{
2705	uint32_t uSubLeaf = 0;
2706	PCPUMCPUIDLEAF pCurLeaf;
2707	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2708	{
2709	pCurLeaf->uEax = 0;
2710	pCurLeaf->uEbx = 0;
2711	pCurLeaf->uEcx = 0;
2712	pCurLeaf->uEdx = 0;
2713	uSubLeaf++;
2714	}
2715	}
2716
2717
2718	/**
2719	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2720	* the given leaf.
2721	*
2722	* @returns pLeaf.
2723	* @param pCpum The CPUM instance data.
2724	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2725	*/
2726	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2727	{
2728	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2729	if (pLeaf->fSubLeafMask != 0)
2730	{
2731	/*
2732	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2733	* Log everything while we're at it.
2734	*/
2735	LogRel(("CPUM:\n"
2736	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2737	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2738	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2739	for (;;)
2740	{
2741	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2742	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2743	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2744	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2745	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2746	break;
2747	pSubLeaf++;
2748	}
2749	LogRel(("CPUM:\n"));
2750
2751	/*
2752	* Remove the offending sub-leaves.
2753	*/
2754	if (pSubLeaf != pLeaf)
2755	{
2756	if (pSubLeaf != pLast)
2757	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2758	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2759	}
2760
2761	/*
2762	* Convert the first sub-leaf into a single leaf.
2763	*/
2764	pLeaf->uSubLeaf = 0;
2765	pLeaf->fSubLeafMask = 0;
2766	}
2767	return pLeaf;
2768	}
2769
2770
2771	/**
2772	* Sanitizes and adjust the CPUID leaves.
2773	*
2774	* Drop features that aren't virtualized (or virtualizable). Adjust information
2775	* and capabilities to fit the virtualized hardware. Remove information the
2776	* guest shouldn't have (because it's wrong in the virtual world or because it
2777	* gives away host details) or that we don't have documentation for and no idea
2778	* what means.
2779	*
2780	* @returns VBox status code.
2781	* @param pVM The cross context VM structure (for cCpus).
2782	* @param pCpum The CPUM instance data.
2783	* @param pConfig The CPUID configuration we've read from CFGM.
2784	*/
2785	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2786	{
2787	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2788	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2789	{ \
2790	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2791	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2792	}
2793	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2794	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2795	{ \
2796	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2797	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2798	}
2799	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2800	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2801	&& ((a_pLeafReg) & (fBitMask)) \
2802	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2803	{ \
2804	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2805	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2806	}
2807	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2808
2809	/* The CPUID entries we start with here isn't necessarily the ones of the host, so we
2810	must consult HostFeatures when processing CPUMISAEXTCFG variables. */
2811	PCCPUMFEATURES pHstFeat = &pCpum->HostFeatures;
2812	#define PASSTHRU_FEATURE(enmConfig, fHostFeature, fConst) \
2813	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) ? (fConst) : 0)
2814	#define PASSTHRU_FEATURE_EX(enmConfig, fHostFeature, fAndExpr, fConst) \
2815	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) && (fAndExpr) ? (fConst) : 0)
2816	#define PASSTHRU_FEATURE_TODO(enmConfig, fConst) ((enmConfig) ? (fConst) : 0)
2817
2818	/* Cpuid 1:
2819	* EAX: CPU model, family and stepping.
2820	*
2821	* ECX + EDX: Supported features. Only report features we can support.
2822	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2823	* options may require adjusting (i.e. stripping what was enabled).
2824	*
2825	* EBX: Branding, CLFLUSH line size, logical processors per package and
2826	* initial APIC ID.
2827	*/
2828	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2829	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2830	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2831
2832	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2833	\| X86_CPUID_FEATURE_EDX_VME
2834	\| X86_CPUID_FEATURE_EDX_DE
2835	\| X86_CPUID_FEATURE_EDX_PSE
2836	\| X86_CPUID_FEATURE_EDX_TSC
2837	\| X86_CPUID_FEATURE_EDX_MSR
2838	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2839	\| X86_CPUID_FEATURE_EDX_MCE
2840	\| X86_CPUID_FEATURE_EDX_CX8
2841	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2842	//\| RT_BIT_32(10) - not defined
2843	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2844	//\| X86_CPUID_FEATURE_EDX_SEP
2845	\| X86_CPUID_FEATURE_EDX_MTRR
2846	\| X86_CPUID_FEATURE_EDX_PGE
2847	\| X86_CPUID_FEATURE_EDX_MCA
2848	\| X86_CPUID_FEATURE_EDX_CMOV
2849	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2850	\| X86_CPUID_FEATURE_EDX_PSE36
2851	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2852	\| X86_CPUID_FEATURE_EDX_CLFSH
2853	//\| RT_BIT_32(20) - not defined
2854	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2855	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2856	\| X86_CPUID_FEATURE_EDX_MMX
2857	\| X86_CPUID_FEATURE_EDX_FXSR
2858	\| X86_CPUID_FEATURE_EDX_SSE
2859	\| X86_CPUID_FEATURE_EDX_SSE2
2860	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2861	\| X86_CPUID_FEATURE_EDX_HTT
2862	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2863	//\| RT_BIT_32(30) - not defined
2864	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2865	;
2866	pStdFeatureLeaf->uEcx &= X86_CPUID_FEATURE_ECX_SSE3
2867	\| PASSTHRU_FEATURE_TODO(pConfig->enmPClMul, X86_CPUID_FEATURE_ECX_PCLMUL)
2868	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2869	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2870	\| PASSTHRU_FEATURE_EX(pConfig->enmMonitor, pHstFeat->fMonitorMWait, pVM->cCpus == 1, X86_CPUID_FEATURE_ECX_MONITOR)
2871	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2872	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2873	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2874	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2875	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2876	\| X86_CPUID_FEATURE_ECX_SSSE3
2877	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2878	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2879	\| PASSTHRU_FEATURE(pConfig->enmCmpXchg16b, pHstFeat->fMovCmpXchg16b, X86_CPUID_FEATURE_ECX_CX16)
2880	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2881	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2882	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2883	\| PASSTHRU_FEATURE(pConfig->enmPcid, pHstFeat->fPcid, X86_CPUID_FEATURE_ECX_PCID)
2884	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2885	\| PASSTHRU_FEATURE(pConfig->enmSse41, pHstFeat->fSse41, X86_CPUID_FEATURE_ECX_SSE4_1)
2886	\| PASSTHRU_FEATURE(pConfig->enmSse42, pHstFeat->fSse42, X86_CPUID_FEATURE_ECX_SSE4_2)
2887	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2888	\| PASSTHRU_FEATURE_TODO(pConfig->enmMovBe, X86_CPUID_FEATURE_ECX_MOVBE)
2889	\| PASSTHRU_FEATURE_TODO(pConfig->enmPopCnt, X86_CPUID_FEATURE_ECX_POPCNT)
2890	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2891	\| PASSTHRU_FEATURE_TODO(pConfig->enmAesNi, X86_CPUID_FEATURE_ECX_AES)
2892	\| PASSTHRU_FEATURE(pConfig->enmXSave, pHstFeat->fXSaveRstor, X86_CPUID_FEATURE_ECX_XSAVE)
2893	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2894	\| PASSTHRU_FEATURE(pConfig->enmAvx, pHstFeat->fAvx, X86_CPUID_FEATURE_ECX_AVX)
2895	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2896	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdRand, X86_CPUID_FEATURE_ECX_RDRAND)
2897	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2898	;
2899
2900	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2901	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2902	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2903	{
2904	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2905	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2906	}
2907
2908	if (pCpum->u8PortableCpuIdLevel > 0)
2909	{
2910	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2911	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2912	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2913	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2914	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2915	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2916	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2917	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2918	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2919	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2920	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2921	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2922	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2923	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2924	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2925	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2926	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2927	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2928	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2929	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2930
2931	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2932	\| X86_CPUID_FEATURE_EDX_PSN
2933	\| X86_CPUID_FEATURE_EDX_DS
2934	\| X86_CPUID_FEATURE_EDX_ACPI
2935	\| X86_CPUID_FEATURE_EDX_SS
2936	\| X86_CPUID_FEATURE_EDX_TM
2937	\| X86_CPUID_FEATURE_EDX_PBE
2938	)));
2939	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2940	\| X86_CPUID_FEATURE_ECX_CPLDS
2941	\| X86_CPUID_FEATURE_ECX_AES
2942	\| X86_CPUID_FEATURE_ECX_VMX
2943	\| X86_CPUID_FEATURE_ECX_SMX
2944	\| X86_CPUID_FEATURE_ECX_EST
2945	\| X86_CPUID_FEATURE_ECX_TM2
2946	\| X86_CPUID_FEATURE_ECX_CNTXID
2947	\| X86_CPUID_FEATURE_ECX_FMA
2948	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2949	\| X86_CPUID_FEATURE_ECX_PDCM
2950	\| X86_CPUID_FEATURE_ECX_DCA
2951	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2952	)));
2953	}
2954
2955	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2956	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2957
2958	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2959	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2960	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2961	*/
2962	#ifdef VBOX_WITH_MULTI_CORE
2963	if (pVM->cCpus > 1)
2964	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2965	#endif
2966	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2967	{
2968	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2969	core times the number of CPU cores per processor */
2970	#ifdef VBOX_WITH_MULTI_CORE
2971	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2972	#else
2973	/* Single logical processor in a package. */
2974	pStdFeatureLeaf->uEbx \|= (1 << 16);
2975	#endif
2976	}
2977
2978	uint32_t uMicrocodeRev;
2979	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2980	if (RT_SUCCESS(rc))
2981	{
2982	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2983	}
2984	else
2985	{
2986	uMicrocodeRev = 0;
2987	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2988	}
2989
2990	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2991	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2992	*/
2993	if ( ( pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen
2994	/** @todo The following ASSUMES that Hygon uses the same version numbering
2995	* as AMD and that they shipped buggy firmware. */
2996	\|\| pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Hygon_Dhyana)
2997	&& uMicrocodeRev < 0x8001126
2998	&& !pConfig->fForceVme)
2999	{
3000	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
3001	LogRel(("CPUM: Zen VME workaround engaged\n"));
3002	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
3003	}
3004
3005	/* Force standard feature bits. */
3006	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
3007	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
3008	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
3009	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
3010	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
3011	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
3012	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3013	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
3014	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3015	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
3016	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
3017	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
3018	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3019	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
3020	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
3021	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
3022	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
3023	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
3024	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3025	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
3026	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
3027	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
3028
3029	pStdFeatureLeaf = NULL; /* Must refetch! */
3030
3031	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
3032	* AMD:
3033	* EAX: CPU model, family and stepping.
3034	*
3035	* ECX + EDX: Supported features. Only report features we can support.
3036	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3037	* options may require adjusting (i.e. stripping what was enabled).
3038	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
3039	*
3040	* EBX: Branding ID and package type (or reserved).
3041	*
3042	* Intel and probably most others:
3043	* EAX: 0
3044	* EBX: 0
3045	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
3046	*/
3047	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3048	if (pExtFeatureLeaf)
3049	{
3050	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
3051
3052	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
3053	\| X86_CPUID_AMD_FEATURE_EDX_VME
3054	\| X86_CPUID_AMD_FEATURE_EDX_DE
3055	\| X86_CPUID_AMD_FEATURE_EDX_PSE
3056	\| X86_CPUID_AMD_FEATURE_EDX_TSC
3057	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
3058	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
3059	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
3060	\| X86_CPUID_AMD_FEATURE_EDX_CX8
3061	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
3062	//\| RT_BIT_32(10) - reserved
3063	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
3064	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
3065	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3066	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
3067	\| X86_CPUID_AMD_FEATURE_EDX_PGE
3068	\| X86_CPUID_AMD_FEATURE_EDX_MCA
3069	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
3070	\| X86_CPUID_AMD_FEATURE_EDX_PAT
3071	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
3072	//\| RT_BIT_32(18) - reserved
3073	//\| RT_BIT_32(19) - reserved
3074	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
3075	//\| RT_BIT_32(21) - reserved
3076	\| PASSTHRU_FEATURE(pConfig->enmAmdExtMmx, pHstFeat->fAmdMmxExts, X86_CPUID_AMD_FEATURE_EDX_AXMMX)
3077	\| X86_CPUID_AMD_FEATURE_EDX_MMX
3078	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
3079	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
3080	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3081	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
3082	//\| RT_BIT_32(28) - reserved
3083	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
3084	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
3085	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
3086	;
3087	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
3088	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
3089	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
3090	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3091	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
3092	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
3093	\| PASSTHRU_FEATURE_TODO(pConfig->enmAbm, X86_CPUID_AMD_FEATURE_ECX_ABM)
3094	\| PASSTHRU_FEATURE_TODO(pConfig->enmSse4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A)
3095	\| PASSTHRU_FEATURE_TODO(pConfig->enmMisAlnSse, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE)
3096	\| PASSTHRU_FEATURE(pConfig->enm3dNowPrf, pHstFeat->f3DNowPrefetch, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
3097	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3098	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
3099	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
3100	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3101	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
3102	//\| RT_BIT_32(14) - reserved
3103	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
3104	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
3105	//\| RT_BIT_32(17) - reserved
3106	//\| RT_BIT_32(18) - reserved
3107	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
3108	//\| RT_BIT_32(20) - reserved
3109	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
3110	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
3111	//\| RT_BIT_32(23) - reserved
3112	//\| RT_BIT_32(24) - reserved
3113	//\| RT_BIT_32(25) - reserved
3114	//\| RT_BIT_32(26) - reserved
3115	//\| RT_BIT_32(27) - reserved
3116	//\| RT_BIT_32(28) - reserved
3117	//\| RT_BIT_32(29) - reserved
3118	//\| RT_BIT_32(30) - reserved
3119	//\| RT_BIT_32(31) - reserved
3120	;
3121	#ifdef VBOX_WITH_MULTI_CORE
3122	if ( pVM->cCpus > 1
3123	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3124	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3125	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
3126	#endif
3127
3128	if (pCpum->u8PortableCpuIdLevel > 0)
3129	{
3130	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
3131	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
3132	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
3133	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
3134	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
3135	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
3136	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
3137	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
3138	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
3139	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
3140	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
3141	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
3142	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
3143	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
3144	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
3145	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
3146
3147	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
3148	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3149	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
3150	\| X86_CPUID_AMD_FEATURE_ECX_IBS
3151	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3152	\| X86_CPUID_AMD_FEATURE_ECX_WDT
3153	\| X86_CPUID_AMD_FEATURE_ECX_LWP
3154	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
3155	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
3156	\| UINT32_C(0xff964000)
3157	)));
3158	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
3159	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3160	\| RT_BIT(18)
3161	\| RT_BIT(19)
3162	\| RT_BIT(21)
3163	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
3164	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3165	\| RT_BIT(28)
3166	)));
3167	}
3168
3169	/* Force extended feature bits. */
3170	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
3171	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
3172	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
3173	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
3174	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
3175	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
3176	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
3177	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
3178	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3179	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
3180	}
3181	pExtFeatureLeaf = NULL; /* Must refetch! */
3182
3183
3184	/* Cpuid 2:
3185	* Intel: (Nondeterministic) Cache and TLB information
3186	* AMD: Reserved
3187	* VIA: Reserved
3188	* Safe to expose.
3189	*/
3190	uint32_t uSubLeaf = 0;
3191	PCPUMCPUIDLEAF pCurLeaf;
3192	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
3193	{
3194	if ((pCurLeaf->uEax & 0xff) > 1)
3195	{
3196	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
3197	pCurLeaf->uEax &= UINT32_C(0xffffff01);
3198	}
3199	uSubLeaf++;
3200	}
3201
3202	/* Cpuid 3:
3203	* Intel: EAX, EBX - reserved (transmeta uses these)
3204	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3205	* AMD: Reserved
3206	* VIA: Reserved
3207	* Safe to expose
3208	*/
3209	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3210	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3211	{
3212	uSubLeaf = 0;
3213	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3214	{
3215	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3216	if (pCpum->u8PortableCpuIdLevel > 0)
3217	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3218	uSubLeaf++;
3219	}
3220	}
3221
3222	/* Cpuid 4 + ECX:
3223	* Intel: Deterministic Cache Parameters Leaf.
3224	* AMD: Reserved
3225	* VIA: Reserved
3226	* Safe to expose, except for EAX:
3227	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3228	* Bits 31-26: Maximum number of processor cores in this physical package**
3229	* Note: These SMP values are constant regardless of ECX
3230	*/
3231	uSubLeaf = 0;
3232	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3233	{
3234	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3235	#ifdef VBOX_WITH_MULTI_CORE
3236	if ( pVM->cCpus > 1
3237	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3238	{
3239	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3240	/* One logical processor with possibly multiple cores. */
3241	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3242	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3243	}
3244	#endif
3245	uSubLeaf++;
3246	}
3247
3248	/* Cpuid 5: Monitor/mwait Leaf
3249	* Intel: ECX, EDX - reserved
3250	* EAX, EBX - Smallest and largest monitor line size
3251	* AMD: EDX - reserved
3252	* EAX, EBX - Smallest and largest monitor line size
3253	* ECX - extensions (ignored for now)
3254	* VIA: Reserved
3255	* Safe to expose
3256	*/
3257	uSubLeaf = 0;
3258	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3259	{
3260	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3261	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3262	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3263
3264	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3265	if (pConfig->enmMWaitExtensions)
3266	{
3267	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3268	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3269	it shall be part of our power management virtualization model */
3270	#if 0
3271	/* MWAIT sub C-states */
3272	pCurLeaf->uEdx =
3273	(0 << 0) /* 0 in C0 */ \|
3274	(2 << 4) /* 2 in C1 */ \|
3275	(2 << 8) /* 2 in C2 */ \|
3276	(2 << 12) /* 2 in C3 */ \|
3277	(0 << 16) /* 0 in C4 */
3278	;
3279	#endif
3280	}
3281	else
3282	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3283	uSubLeaf++;
3284	}
3285
3286	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3287	* Intel: Various stuff.
3288	* AMD: EAX, EBX, EDX - reserved.
3289	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3290	* present. Same as intel.
3291	* VIA: ??
3292	*
3293	* We clear everything here for now.
3294	*/
3295	cpumR3CpuIdZeroLeaf(pCpum, 6);
3296
3297	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3298	* EAX: Number of sub leaves.
3299	* EBX+ECX+EDX: Feature flags
3300	*
3301	* We only have documentation for one sub-leaf, so clear all other (no need
3302	* to remove them as such, just set them to zero).
3303	*
3304	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3305	* options may require adjusting (i.e. stripping what was enabled).
3306	*/
3307	uSubLeaf = 0;
3308	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3309	{
3310	switch (uSubLeaf)
3311	{
3312	case 0:
3313	{
3314	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3315	pCurLeaf->uEbx &= 0
3316	\| PASSTHRU_FEATURE(pConfig->enmFsGsBase, pHstFeat->fFsGsBase, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE)
3317	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3318	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3319	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3320	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3321	\| PASSTHRU_FEATURE(pConfig->enmAvx2, pHstFeat->fAvx2, X86_CPUID_STEXT_FEATURE_EBX_AVX2)
3322	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3323	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3324	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3325	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3326	\| PASSTHRU_FEATURE(pConfig->enmInvpcid, pHstFeat->fInvpcid, X86_CPUID_STEXT_FEATURE_EBX_INVPCID)
3327	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3328	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3329	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3330	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3331	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3332	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3333	//\| RT_BIT(17) - reserved
3334	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdSeed, X86_CPUID_STEXT_FEATURE_EBX_RDSEED)
3335	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3336	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3337	//\| RT_BIT(21) - reserved
3338	//\| RT_BIT(22) - reserved
3339	\| PASSTHRU_FEATURE(pConfig->enmCLFlushOpt, pHstFeat->fClFlushOpt, X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT)
3340	//\| RT_BIT(24) - reserved
3341	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3342	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3343	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3344	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3345	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3346	//\| RT_BIT(30) - reserved
3347	//\| RT_BIT(31) - reserved
3348	;
3349	pCurLeaf->uEcx &= 0
3350	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3351	;
3352	pCurLeaf->uEdx &= 0
3353	\| PASSTHRU_FEATURE(pConfig->enmMdsClear, pHstFeat->fMdsClear, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR)
3354	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3355	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3356	\| PASSTHRU_FEATURE(pConfig->enmFlushCmdMsr, pHstFeat->fFlushCmd, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD)
3357	\| PASSTHRU_FEATURE(pConfig->enmArchCapMsr, pHstFeat->fArchCap, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
3358	;
3359
3360	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3361	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3362	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3363	{
3364	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3365	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3366	}
3367
3368	if (pCpum->u8PortableCpuIdLevel > 0)
3369	{
3370	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3371	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3372	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3373	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3374	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3375	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3376	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3377	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3378	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3379	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3380	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3381	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3382	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3383	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3384	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3385	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
3386	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
3387	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
3388	}
3389
3390	/* Dependencies. */
3391	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
3392	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3393
3394	/* Force standard feature bits. */
3395	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3396	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3397	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3398	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3399	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3400	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3401	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3402	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3403	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3404	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3405	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3406	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
3407	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
3408	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3409	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3410	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
3411	break;
3412	}
3413
3414	default:
3415	/* Invalid index, all values are zero. */
3416	pCurLeaf->uEax = 0;
3417	pCurLeaf->uEbx = 0;
3418	pCurLeaf->uEcx = 0;
3419	pCurLeaf->uEdx = 0;
3420	break;
3421	}
3422	uSubLeaf++;
3423	}
3424
3425	/* Cpuid 8: Marked as reserved by Intel and AMD.
3426	* We zero this since we don't know what it may have been used for.
3427	*/
3428	cpumR3CpuIdZeroLeaf(pCpum, 8);
3429
3430	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3431	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3432	* EBX, ECX, EDX - reserved.
3433	* AMD: Reserved
3434	* VIA: ??
3435	*
3436	* We zero this.
3437	*/
3438	cpumR3CpuIdZeroLeaf(pCpum, 9);
3439
3440	/* Cpuid 0xa: Architectural Performance Monitor Features
3441	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3442	* EBX, ECX, EDX - reserved.
3443	* AMD: Reserved
3444	* VIA: ??
3445	*
3446	* We zero this, for now at least.
3447	*/
3448	cpumR3CpuIdZeroLeaf(pCpum, 10);
3449
3450	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3451	* Intel: EAX - APCI ID shift right for next level.
3452	* EBX - Factory configured cores/threads at this level.
3453	* ECX - Level number (same as input) and level type (1,2,0).
3454	* EDX - Extended initial APIC ID.
3455	* AMD: Reserved
3456	* VIA: ??
3457	*/
3458	uSubLeaf = 0;
3459	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3460	{
3461	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3462	{
3463	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3464	if (bLevelType == 1)
3465	{
3466	/* Thread level - we don't do threads at the moment. */
3467	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3468	pCurLeaf->uEbx = 1;
3469	}
3470	else if (bLevelType == 2)
3471	{
3472	/* Core level. */
3473	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3474	#ifdef VBOX_WITH_MULTI_CORE
3475	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3476	pCurLeaf->uEax++;
3477	#endif
3478	pCurLeaf->uEbx = pVM->cCpus;
3479	}
3480	else
3481	{
3482	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3483	pCurLeaf->uEax = 0;
3484	pCurLeaf->uEbx = 0;
3485	pCurLeaf->uEcx = 0;
3486	}
3487	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3488	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3489	}
3490	else
3491	{
3492	pCurLeaf->uEax = 0;
3493	pCurLeaf->uEbx = 0;
3494	pCurLeaf->uEcx = 0;
3495	pCurLeaf->uEdx = 0;
3496	}
3497	uSubLeaf++;
3498	}
3499
3500	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3501	* We zero this since we don't know what it may have been used for.
3502	*/
3503	cpumR3CpuIdZeroLeaf(pCpum, 12);
3504
3505	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3506	* ECX=0: EAX - Valid bits in XCR0[31:0].
3507	* EBX - Maximum state size as per current XCR0 value.
3508	* ECX - Maximum state size for all supported features.
3509	* EDX - Valid bits in XCR0[63:32].
3510	* ECX=1: EAX - Various X-features.
3511	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3512	* ECX - Valid bits in IA32_XSS[31:0].
3513	* EDX - Valid bits in IA32_XSS[63:32].
3514	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3515	* if the bit invalid all four registers are set to zero.
3516	* EAX - The state size for this feature.
3517	* EBX - The state byte offset of this feature.
3518	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3519	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3520	*
3521	* Clear them all as we don't currently implement extended CPU state.
3522	*/
3523	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3524	uint64_t fGuestXcr0Mask = 0;
3525	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3526	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3527	{
3528	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3529	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3530	fGuestXcr0Mask \|= XSAVE_C_YMM;
3531	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3532	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3533	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3534	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3535
3536	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3537	}
3538	pStdFeatureLeaf = NULL;
3539	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3540
3541	/* Work the sub-leaves. */
3542	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3543	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3544	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3545	{
3546	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3547	if (pCurLeaf)
3548	{
3549	if (fGuestXcr0Mask)
3550	{
3551	switch (uSubLeaf)
3552	{
3553	case 0:
3554	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3555	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3556	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3557	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3558	VERR_CPUM_IPE_1);
3559	cbXSaveMaxActual = pCurLeaf->uEcx;
3560	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3561	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3562	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3563	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3564	VERR_CPUM_IPE_2);
3565	continue;
3566	case 1:
3567	pCurLeaf->uEax &= 0;
3568	pCurLeaf->uEcx &= 0;
3569	pCurLeaf->uEdx &= 0;
3570	/** @todo what about checking ebx? */
3571	continue;
3572	default:
3573	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3574	{
3575	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3576	&& pCurLeaf->uEax > 0
3577	&& pCurLeaf->uEbx < cbXSaveMaxActual
3578	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3579	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3580	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3581	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3582	VERR_CPUM_IPE_2);
3583	AssertLogRel(!(pCurLeaf->uEcx & 1));
3584	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3585	pCurLeaf->uEdx = 0; /* it's reserved... */
3586	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3587	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3588	continue;
3589	}
3590	break;
3591	}
3592	}
3593
3594	/* Clear the leaf. */
3595	pCurLeaf->uEax = 0;
3596	pCurLeaf->uEbx = 0;
3597	pCurLeaf->uEcx = 0;
3598	pCurLeaf->uEdx = 0;
3599	}
3600	}
3601
3602	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3603	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3604	{
3605	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3606	if (pCurLeaf)
3607	{
3608	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3609	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3610	pCurLeaf->uEbx = cbXSaveMaxReport;
3611	pCurLeaf->uEcx = cbXSaveMaxReport;
3612	}
3613	}
3614
3615	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3616	* We zero this since we don't know what it may have been used for.
3617	*/
3618	cpumR3CpuIdZeroLeaf(pCpum, 14);
3619
3620	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3621	* also known as Intel Resource Director Technology (RDT) Monitoring
3622	* We zero this as we don't currently virtualize PQM.
3623	*/
3624	cpumR3CpuIdZeroLeaf(pCpum, 15);
3625
3626	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3627	* also known as Intel Resource Director Technology (RDT) Allocation
3628	* We zero this as we don't currently virtualize PQE.
3629	*/
3630	cpumR3CpuIdZeroLeaf(pCpum, 16);
3631
3632	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3633	* We zero this since we don't know what it may have been used for.
3634	*/
3635	cpumR3CpuIdZeroLeaf(pCpum, 17);
3636
3637	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3638	* We zero this as we don't currently virtualize this.
3639	*/
3640	cpumR3CpuIdZeroLeaf(pCpum, 18);
3641
3642	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3643	* We zero this since we don't know what it may have been used for.
3644	*/
3645	cpumR3CpuIdZeroLeaf(pCpum, 19);
3646
3647	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3648	* We zero this as we don't currently virtualize this.
3649	*/
3650	cpumR3CpuIdZeroLeaf(pCpum, 20);
3651
3652	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3653	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3654	* EAX - denominator (unsigned).
3655	* EBX - numerator (unsigned).
3656	* ECX, EDX - reserved.
3657	* AMD: Reserved / undefined / not implemented.
3658	* VIA: Reserved / undefined / not implemented.
3659	* We zero this as we don't currently virtualize this.
3660	*/
3661	cpumR3CpuIdZeroLeaf(pCpum, 21);
3662
3663	/* Cpuid 0x16: Processor frequency info
3664	* Intel: EAX - Core base frequency in MHz.
3665	* EBX - Core maximum frequency in MHz.
3666	* ECX - Bus (reference) frequency in MHz.
3667	* EDX - Reserved.
3668	* AMD: Reserved / undefined / not implemented.
3669	* VIA: Reserved / undefined / not implemented.
3670	* We zero this as we don't currently virtualize this.
3671	*/
3672	cpumR3CpuIdZeroLeaf(pCpum, 22);
3673
3674	/* Cpuid 0x17..0x10000000: Unknown.
3675	* We don't know these and what they mean, so remove them. */
3676	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3677	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3678
3679
3680	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3681	* We remove all these as we're a hypervisor and must provide our own.
3682	*/
3683	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3684	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3685
3686
3687	/* Cpuid 0x80000000 is harmless. */
3688
3689	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3690
3691	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3692
3693	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3694	* Safe to pass on to the guest.
3695	*
3696	* AMD: 0x800000005 L1 cache information
3697	* 0x800000006 L2/L3 cache information
3698	* Intel: 0x800000005 reserved
3699	* 0x800000006 L2 cache information
3700	* VIA: 0x800000005 TLB and L1 cache information
3701	* 0x800000006 L2 cache information
3702	*/
3703
3704	/* Cpuid 0x800000007: Advanced Power Management Information.
3705	* AMD: EAX: Processor feedback capabilities.
3706	* EBX: RAS capabilites.
3707	* ECX: Advanced power monitoring interface.
3708	* EDX: Enhanced power management capabilities.
3709	* Intel: EAX, EBX, ECX - reserved.
3710	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3711	* VIA: Reserved
3712	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3713	*/
3714	uSubLeaf = 0;
3715	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3716	{
3717	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3718	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3719	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3720	{
3721	/*
3722	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3723	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3724	* bit is now configurable.
3725	*/
3726	pCurLeaf->uEdx &= 0
3727	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3728	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3729	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3730	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3731	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3732	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3733	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3734	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3735	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3736	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3737	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3738	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3739	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3740	\| 0;
3741	}
3742	else
3743	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3744	if (!pConfig->fInvariantTsc)
3745	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3746	uSubLeaf++;
3747	}
3748
3749	/* Cpuid 0x80000008:
3750	* AMD: EBX, EDX - reserved
3751	* EAX: Virtual/Physical/Guest address Size
3752	* ECX: Number of cores + APICIdCoreIdSize
3753	* Intel: EAX: Virtual/Physical address Size
3754	* EBX, ECX, EDX - reserved
3755	* VIA: EAX: Virtual/Physical address Size
3756	* EBX, ECX, EDX - reserved
3757	*
3758	* We only expose the virtual+pysical address size to the guest atm.
3759	* On AMD we set the core count, but not the apic id stuff as we're
3760	* currently not doing the apic id assignments in a complatible manner.
3761	*/
3762	uSubLeaf = 0;
3763	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3764	{
3765	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3766	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3767	pCurLeaf->uEdx = 0; /* reserved */
3768
3769	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3770	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3771	pCurLeaf->uEcx = 0;
3772	#ifdef VBOX_WITH_MULTI_CORE
3773	if ( pVM->cCpus > 1
3774	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3775	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3776	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3777	#endif
3778	uSubLeaf++;
3779	}
3780
3781	/* Cpuid 0x80000009: Reserved
3782	* We zero this since we don't know what it may have been used for.
3783	*/
3784	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3785
3786	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
3787	* AMD: EAX - SVM revision.
3788	* EBX - Number of ASIDs.
3789	* ECX - Reserved.
3790	* EDX - SVM Feature identification.
3791	*/
3792	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3793	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3794	{
3795	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3796	if ( pExtFeatureLeaf
3797	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
3798	{
3799	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3800	if (pSvmFeatureLeaf)
3801	{
3802	pSvmFeatureLeaf->uEax = 0x1;
3803	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3804	pSvmFeatureLeaf->uEcx = 0;
3805	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3806	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3807	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3808	}
3809	else
3810	{
3811	/* Should never happen. */
3812	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
3813	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3814	}
3815	}
3816	else
3817	{
3818	/* If SVM is not supported, this is reserved, zero out. */
3819	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3820	}
3821	}
3822	else
3823	{
3824	/* Cpuid 0x8000000a: Reserved on Intel.
3825	* We zero this since we don't know what it may have been used for.
3826	*/
3827	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3828	}
3829
3830	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3831	* We clear these as we don't know what purpose they might have. */
3832	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3833	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3834
3835	/* Cpuid 0x80000019: TLB configuration
3836	* Seems to be harmless, pass them thru as is. */
3837
3838	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3839	* Strip anything we don't know what is or addresses feature we don't implement. */
3840	uSubLeaf = 0;
3841	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3842	{
3843	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3844	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3845	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3846	;
3847	pCurLeaf->uEbx = 0; /* reserved */
3848	pCurLeaf->uEcx = 0; /* reserved */
3849	pCurLeaf->uEdx = 0; /* reserved */
3850	uSubLeaf++;
3851	}
3852
3853	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3854	* Clear this as we don't currently virtualize this feature. */
3855	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3856
3857	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3858	* Clear this as we don't currently virtualize this feature. */
3859	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3860
3861	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3862	* We need to sanitize the cores per cache (EAX[25:14]).
3863	*
3864	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3865	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3866	* slightly different meaning.
3867	*/
3868	uSubLeaf = 0;
3869	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3870	{
3871	#ifdef VBOX_WITH_MULTI_CORE
3872	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3873	if (cCores > pVM->cCpus)
3874	cCores = pVM->cCpus;
3875	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3876	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3877	#else
3878	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3879	#endif
3880	uSubLeaf++;
3881	}
3882
3883	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3884	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3885	* setup, we have one compute unit with all the cores in it. Single node.
3886	*/
3887	uSubLeaf = 0;
3888	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3889	{
3890	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3891	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3892	{
3893	#ifdef VBOX_WITH_MULTI_CORE
3894	pCurLeaf->uEbx = pVM->cCpus < 0x100
3895	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3896	#else
3897	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3898	#endif
3899	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3900	}
3901	else
3902	{
3903	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3904	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_HYGON);
3905	pCurLeaf->uEbx = 0; /* Reserved. */
3906	pCurLeaf->uEcx = 0; /* Reserved. */
3907	}
3908	pCurLeaf->uEdx = 0; /* Reserved. */
3909	uSubLeaf++;
3910	}
3911
3912	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3913	* We don't know these and what they mean, so remove them. */
3914	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3915	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3916
3917	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3918	* Just pass it thru for now. */
3919
3920	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3921	* Just pass it thru for now. */
3922
3923	/* Cpuid 0xc0000000: Centaur stuff.
3924	* Harmless, pass it thru. */
3925
3926	/* Cpuid 0xc0000001: Centaur features.
3927	* VIA: EAX - Family, model, stepping.
3928	* EDX - Centaur extended feature flags. Nothing interesting, except may
3929	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3930	* EBX, ECX - reserved.
3931	* We keep EAX but strips the rest.
3932	*/
3933	uSubLeaf = 0;
3934	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3935	{
3936	pCurLeaf->uEbx = 0;
3937	pCurLeaf->uEcx = 0;
3938	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3939	uSubLeaf++;
3940	}
3941
3942	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3943	* We only have fixed stale values, but should be harmless. */
3944
3945	/* Cpuid 0xc0000003: Reserved.
3946	* We zero this since we don't know what it may have been used for.
3947	*/
3948	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3949
3950	/* Cpuid 0xc0000004: Centaur Performance Info.
3951	* We only have fixed stale values, but should be harmless. */
3952
3953
3954	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3955	* We don't know these and what they mean, so remove them. */
3956	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3957	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3958
3959	return VINF_SUCCESS;
3960	#undef PORTABLE_DISABLE_FEATURE_BIT
3961	#undef PORTABLE_CLEAR_BITS_WHEN
3962	}
3963
3964
3965	/**
3966	* Reads a value in /CPUM/IsaExts/ node.
3967	*
3968	* @returns VBox status code (error message raised).
3969	* @param pVM The cross context VM structure. (For errors.)
3970	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3971	* @param pszValueName The value / extension name.
3972	* @param penmValue Where to return the choice.
3973	* @param enmDefault The default choice.
3974	*/
3975	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3976	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3977	{
3978	/*
3979	* Try integer encoding first.
3980	*/
3981	uint64_t uValue;
3982	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3983	if (RT_SUCCESS(rc))
3984	switch (uValue)
3985	{
3986	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3987	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3988	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3989	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3990	default:
3991	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3992	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3993	pszValueName, uValue);
3994	}
3995	/*
3996	* If missing, use default.
3997	*/
3998	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3999	*penmValue = enmDefault;
4000	else
4001	{
4002	if (rc == VERR_CFGM_NOT_INTEGER)
4003	{
4004	/*
4005	* Not an integer, try read it as a string.
4006	*/
4007	char szValue[32];
4008	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
4009	if (RT_SUCCESS(rc))
4010	{
4011	RTStrToLower(szValue);
4012	size_t cchValue = strlen(szValue);
4013	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
4014	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
4015	*penmValue = CPUMISAEXTCFG_DISABLED;
4016	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
4017	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
4018	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
4019	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
4020	else if (EQ("portable"))
4021	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
4022	else if (EQ("default") \|\| EQ("def"))
4023	*penmValue = enmDefault;
4024	else
4025	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
4026	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
4027	pszValueName, uValue);
4028	#undef EQ
4029	}
4030	}
4031	if (RT_FAILURE(rc))
4032	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
4033	}
4034	return VINF_SUCCESS;
4035	}
4036
4037
4038	/**
4039	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
4040	*
4041	* @returns VBox status code (error message raised).
4042	* @param pVM The cross context VM structure. (For errors.)
4043	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4044	* @param pszValueName The value / extension name.
4045	* @param penmValue Where to return the choice.
4046	* @param enmDefault The default choice.
4047	* @param fAllowed Allowed choice. Applied both to the result and to
4048	* the default value.
4049	*/
4050	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
4051	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
4052	{
4053	int rc;
4054	if (fAllowed)
4055	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4056	else
4057	{
4058	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
4059	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
4060	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
4061	*penmValue = CPUMISAEXTCFG_DISABLED;
4062	}
4063	return rc;
4064	}
4065
4066
4067	/**
4068	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
4069	*
4070	* @returns VBox status code (error message raised).
4071	* @param pVM The cross context VM structure. (For errors.)
4072	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4073	* @param pCpumCfg The /CPUM node (can be NULL).
4074	* @param pszValueName The value / extension name.
4075	* @param penmValue Where to return the choice.
4076	* @param enmDefault The default choice.
4077	*/
4078	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
4079	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
4080	{
4081	if (CFGMR3Exists(pCpumCfg, pszValueName))
4082	{
4083	if (!CFGMR3Exists(pIsaExts, pszValueName))
4084	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
4085	else
4086	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
4087	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
4088	pszValueName, pszValueName);
4089
4090	bool fLegacy;
4091	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
4092	if (RT_SUCCESS(rc))
4093	{
4094	*penmValue = fLegacy;
4095	return VINF_SUCCESS;
4096	}
4097	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
4098	}
4099
4100	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4101	}
4102
4103
4104	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
4105	{
4106	int rc;
4107
4108	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
4109	* When non-zero CPUID features that could cause portability issues will be
4110	* stripped. The higher the value the more features gets stripped. Higher
4111	* values should only be used when older CPUs are involved since it may
4112	* harm performance and maybe also cause problems with specific guests. */
4113	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
4114	AssertLogRelRCReturn(rc, rc);
4115
4116	/** @cfgm{/CPUM/GuestCpuName, string}
4117	* The name of the CPU we're to emulate. The default is the host CPU.
4118	* Note! CPUs other than "host" one is currently unsupported. */
4119	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
4120	AssertLogRelRCReturn(rc, rc);
4121
4122	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
4123	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
4124	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
4125	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
4126	*/
4127	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
4128	AssertLogRelRCReturn(rc, rc);
4129
4130	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
4131	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
4132	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
4133	* 64-bit linux guests which assume the presence of AMD performance counters
4134	* that we do not virtualize.
4135	*/
4136	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
4137	AssertLogRelRCReturn(rc, rc);
4138
4139	/** @cfgm{/CPUM/ForceVme, boolean, false}
4140	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
4141	* By default the flag is passed thru as is from the host CPU, except
4142	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
4143	* guests and DOS boxes in general.
4144	*/
4145	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
4146	AssertLogRelRCReturn(rc, rc);
4147
4148	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
4149	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
4150	* probably going to be a temporary hack, so don't depend on this.
4151	* The 1st byte of the value is the stepping, the 2nd byte value is the model
4152	* number and the 3rd byte value is the family, and the 4th value must be zero.
4153	*/
4154	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
4155	AssertLogRelRCReturn(rc, rc);
4156
4157	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
4158	* The last standard leaf to keep. The actual last value that is stored in EAX
4159	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
4160	* removed. (This works independently of and differently from NT4LeafLimit.)
4161	* The default is usually set to what we're able to reasonably sanitize.
4162	*/
4163	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
4164	AssertLogRelRCReturn(rc, rc);
4165
4166	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
4167	* The last extended leaf to keep. The actual last value that is stored in EAX
4168	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
4169	* leaf are removed. The default is set to what we're able to sanitize.
4170	*/
4171	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
4172	AssertLogRelRCReturn(rc, rc);
4173
4174	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
4175	* The last extended leaf to keep. The actual last value that is stored in EAX
4176	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
4177	* leaf are removed. The default is set to what we're able to sanitize.
4178	*/
4179	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
4180	AssertLogRelRCReturn(rc, rc);
4181
4182	bool fQueryNestedHwvirt = false
4183	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4184	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4185	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON
4186	#endif
4187	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4188	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
4189	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA
4190	#endif
4191	;
4192	if (fQueryNestedHwvirt)
4193	{
4194	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
4195	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
4196	* The default is false, and when enabled requires a 64-bit CPU with support for
4197	* nested-paging and AMD-V or unrestricted guest mode.
4198	*/
4199	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
4200	AssertLogRelRCReturn(rc, rc);
4201	if (pConfig->fNestedHWVirt)
4202	{
4203	if (!fNestedPagingAndFullGuestExec)
4204	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4205	"Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
4206
4207	/** @todo Think about enabling this later with NEM/KVM. */
4208	if (VM_IS_NEM_ENABLED(pVM))
4209	{
4210	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
4211	pConfig->fNestedHWVirt = false;
4212	}
4213	}
4214
4215	if (pConfig->fNestedHWVirt)
4216	{
4217	/** @cfgm{/CPUM/NestedVmxPreemptTimer, bool, true}
4218	* Whether to expose the VMX-preemption timer feature to the guest (if also
4219	* supported by the host hardware). When disabled will prevent exposing the
4220	* VMX-preemption timer feature to the guest even if the host supports it.
4221	*
4222	* @todo Currently disabled, see @bugref{9180#c108}.
4223	*/
4224	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxPreemptTimer", &pVM->cpum.s.fNestedVmxPreemptTimer, false);
4225	AssertLogRelRCReturn(rc, rc);
4226
4227	/** @cfgm{/CPUM/NestedVmxEpt, bool, true}
4228	* Whether to expose the EPT feature to the guest. The default is false. When
4229	* disabled will automatically prevent exposing features that rely on
4230	*/
4231	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxEpt", &pVM->cpum.s.fNestedVmxEpt, false);
4232	AssertLogRelRCReturn(rc, rc);
4233
4234	/** @cfgm{/CPUM/NestedVmxUnrestrictedGuest, bool, true}
4235	* Whether to expose the Unrestricted Guest feature to the guest. The default is
4236	* false. When disabled will automatically prevent exposing features that rely on
4237	* it.
4238	*/
4239	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxUnrestrictedGuest", &pVM->cpum.s.fNestedVmxUnrestrictedGuest, false);
4240	AssertLogRelRCReturn(rc, rc);
4241
4242	if ( pVM->cpum.s.fNestedVmxUnrestrictedGuest
4243	&& !pVM->cpum.s.fNestedVmxEpt)
4244	{
4245	LogRel(("CPUM: WARNING! Can't expose \"Unrestricted Guest\" to the guest when EPT is not exposed!\n"));
4246	pVM->cpum.s.fNestedVmxUnrestrictedGuest = false;
4247	}
4248	}
4249	}
4250
4251	/*
4252	* Instruction Set Architecture (ISA) Extensions.
4253	*/
4254	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
4255	if (pIsaExts)
4256	{
4257	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
4258	"CMPXCHG16B"
4259	"\|MONITOR"
4260	"\|MWaitExtensions"
4261	"\|SSE4.1"
4262	"\|SSE4.2"
4263	"\|XSAVE"
4264	"\|AVX"
4265	"\|AVX2"
4266	"\|AESNI"
4267	"\|PCLMUL"
4268	"\|POPCNT"
4269	"\|MOVBE"
4270	"\|RDRAND"
4271	"\|RDSEED"
4272	"\|CLFLUSHOPT"
4273	"\|FSGSBASE"
4274	"\|PCID"
4275	"\|INVPCID"
4276	"\|FlushCmdMsr"
4277	"\|ABM"
4278	"\|SSE4A"
4279	"\|MISALNSSE"
4280	"\|3DNOWPRF"
4281	"\|AXMMX"
4282	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
4283	if (RT_FAILURE(rc))
4284	return rc;
4285	}
4286
4287	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, true}
4288	* Expose CMPXCHG16B to the guest if available. All host CPUs which support
4289	* hardware virtualization have it.
4290	*/
4291	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, true);
4292	AssertLogRelRCReturn(rc, rc);
4293
4294	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4295	* Expose MONITOR/MWAIT instructions to the guest.
4296	*/
4297	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4298	AssertLogRelRCReturn(rc, rc);
4299
4300	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4301	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4302	* break on interrupt feature (bit 1).
4303	*/
4304	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4305	AssertLogRelRCReturn(rc, rc);
4306
4307	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4308	* Expose SSE4.1 to the guest if available.
4309	*/
4310	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4311	AssertLogRelRCReturn(rc, rc);
4312
4313	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4314	* Expose SSE4.2 to the guest if available.
4315	*/
4316	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4317	AssertLogRelRCReturn(rc, rc);
4318
4319	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4320	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4321	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor;
4322	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4323
4324	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4325	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4326	* default is to only expose this to VMs with nested paging and AMD-V or
4327	* unrestricted guest execution mode. Not possible to force this one without
4328	* host support at the moment.
4329	*/
4330	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4331	fMayHaveXSave /fAllowed/);
4332	AssertLogRelRCReturn(rc, rc);
4333
4334	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4335	* Expose the AVX instruction set extensions to the guest if available and
4336	* XSAVE is exposed too. For the time being the default is to only expose this
4337	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4338	*/
4339	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4340	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4341	AssertLogRelRCReturn(rc, rc);
4342
4343	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4344	* Expose the AVX2 instruction set extensions to the guest if available and
4345	* XSAVE is exposed too. For the time being the default is to only expose this
4346	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4347	*/
4348	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4349	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4350	AssertLogRelRCReturn(rc, rc);
4351
4352	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4353	* Whether to expose the AES instructions to the guest. For the time being the
4354	* default is to only do this for VMs with nested paging and AMD-V or
4355	* unrestricted guest mode.
4356	*/
4357	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4358	AssertLogRelRCReturn(rc, rc);
4359
4360	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4361	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4362	* being the default is to only do this for VMs with nested paging and AMD-V or
4363	* unrestricted guest mode.
4364	*/
4365	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4366	AssertLogRelRCReturn(rc, rc);
4367
4368	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4369	* Whether to expose the POPCNT instructions to the guest. For the time
4370	* being the default is to only do this for VMs with nested paging and AMD-V or
4371	* unrestricted guest mode.
4372	*/
4373	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4374	AssertLogRelRCReturn(rc, rc);
4375
4376	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4377	* Whether to expose the MOVBE instructions to the guest. For the time
4378	* being the default is to only do this for VMs with nested paging and AMD-V or
4379	* unrestricted guest mode.
4380	*/
4381	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4382	AssertLogRelRCReturn(rc, rc);
4383
4384	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4385	* Whether to expose the RDRAND instructions to the guest. For the time being
4386	* the default is to only do this for VMs with nested paging and AMD-V or
4387	* unrestricted guest mode.
4388	*/
4389	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4390	AssertLogRelRCReturn(rc, rc);
4391
4392	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4393	* Whether to expose the RDSEED instructions to the guest. For the time being
4394	* the default is to only do this for VMs with nested paging and AMD-V or
4395	* unrestricted guest mode.
4396	*/
4397	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4398	AssertLogRelRCReturn(rc, rc);
4399
4400	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4401	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4402	* being the default is to only do this for VMs with nested paging and AMD-V or
4403	* unrestricted guest mode.
4404	*/
4405	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4406	AssertLogRelRCReturn(rc, rc);
4407
4408	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4409	* Whether to expose the read/write FSGSBASE instructions to the guest.
4410	*/
4411	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4412	AssertLogRelRCReturn(rc, rc);
4413
4414	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4415	* Whether to expose the PCID feature to the guest.
4416	*/
4417	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4418	AssertLogRelRCReturn(rc, rc);
4419
4420	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4421	* Whether to expose the INVPCID instruction to the guest.
4422	*/
4423	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4424	AssertLogRelRCReturn(rc, rc);
4425
4426	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
4427	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
4428	*/
4429	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4430	AssertLogRelRCReturn(rc, rc);
4431
4432	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
4433	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
4434	* the guest. Requires FlushCmdMsr to be present too.
4435	*/
4436	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4437	AssertLogRelRCReturn(rc, rc);
4438
4439	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
4440	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
4441	*/
4442	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4443	AssertLogRelRCReturn(rc, rc);
4444
4445
4446	/* AMD: */
4447
4448	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4449	* Whether to expose the AMD ABM instructions to the guest. For the time
4450	* being the default is to only do this for VMs with nested paging and AMD-V or
4451	* unrestricted guest mode.
4452	*/
4453	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4454	AssertLogRelRCReturn(rc, rc);
4455
4456	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4457	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4458	* being the default is to only do this for VMs with nested paging and AMD-V or
4459	* unrestricted guest mode.
4460	*/
4461	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4462	AssertLogRelRCReturn(rc, rc);
4463
4464	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4465	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4466	* the time being the default is to only do this for VMs with nested paging and
4467	* AMD-V or unrestricted guest mode.
4468	*/
4469	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4470	AssertLogRelRCReturn(rc, rc);
4471
4472	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4473	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4474	* For the time being the default is to only do this for VMs with nested paging
4475	* and AMD-V or unrestricted guest mode.
4476	*/
4477	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4478	AssertLogRelRCReturn(rc, rc);
4479
4480	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4481	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4482	* the default is to only do this for VMs with nested paging and AMD-V or
4483	* unrestricted guest mode.
4484	*/
4485	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4486	AssertLogRelRCReturn(rc, rc);
4487
4488	return VINF_SUCCESS;
4489	}
4490
4491
4492	/**
4493	* Initializes the emulated CPU's CPUID & MSR information.
4494	*
4495	* @returns VBox status code.
4496	* @param pVM The cross context VM structure.
4497	* @param pHostMsrs Pointer to the host MSRs.
4498	*/
4499	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
4500	{
4501	Assert(pHostMsrs);
4502
4503	PCPUM pCpum = &pVM->cpum.s;
4504	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4505
4506	/*
4507	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4508	* on construction and manage everything from here on.
4509	*/
4510	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4511	{
4512	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4513	pVCpu->cpum.s.fCpuIdApicFeatureVisible = true;
4514	}
4515
4516	/*
4517	* Read the configuration.
4518	*/
4519	CPUMCPUIDCONFIG Config;
4520	RT_ZERO(Config);
4521
4522	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4523	AssertRCReturn(rc, rc);
4524
4525	/*
4526	* Get the guest CPU data from the database and/or the host.
4527	*
4528	* The CPUID and MSRs are currently living on the regular heap to avoid
4529	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4530	* API for the hyper heap). This means special cleanup considerations.
4531	*/
4532	/** @todo The hyper heap will be removed ASAP, so the final destination is
4533	* now a fixed sized arrays in the VM structure. Maybe we can simplify
4534	* this allocation fun a little now? Or maybe it's too convenient for
4535	* the CPU reporter code... No time to figure that out now. */
4536	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4537	if (RT_FAILURE(rc))
4538	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4539	? VMSetError(pVM, rc, RT_SRC_POS,
4540	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4541	: rc;
4542
4543	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4544	{
4545	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4546	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4547	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4548	}
4549	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4550
4551	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4552	* Overrides the guest MSRs.
4553	*/
4554	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4555
4556	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4557	* Overrides the CPUID leaf values (from the host CPU usually) used for
4558	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4559	* values when moving a VM to a different machine. Another use is restricting
4560	* (or extending) the feature set exposed to the guest. */
4561	if (RT_SUCCESS(rc))
4562	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4563
4564	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4565	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4566	"Found unsupported configuration node '/CPUM/CPUID/'. "
4567	"Please use IMachine::setCPUIDLeaf() instead.");
4568
4569	CPUMMSRS GuestMsrs;
4570	RT_ZERO(GuestMsrs);
4571
4572	/*
4573	* Pre-explode the CPUID info.
4574	*/
4575	if (RT_SUCCESS(rc))
4576	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
4577	&pCpum->GuestFeatures);
4578
4579	/*
4580	* Sanitize the cpuid information passed on to the guest.
4581	*/
4582	if (RT_SUCCESS(rc))
4583	{
4584	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4585	if (RT_SUCCESS(rc))
4586	{
4587	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4588	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4589	}
4590	}
4591
4592	/*
4593	* Setup MSRs introduced in microcode updates or that are otherwise not in
4594	* the CPU profile, but are advertised in the CPUID info we just sanitized.
4595	*/
4596	if (RT_SUCCESS(rc))
4597	rc = cpumR3MsrReconcileWithCpuId(pVM);
4598	/*
4599	* MSR fudging.
4600	*/
4601	if (RT_SUCCESS(rc))
4602	{
4603	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4604	* Fudges some common MSRs if not present in the selected CPU database entry.
4605	* This is for trying to keep VMs running when moved between different hosts
4606	* and different CPU vendors. */
4607	bool fEnable;
4608	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4609	if (RT_SUCCESS(rc) && fEnable)
4610	{
4611	rc = cpumR3MsrApplyFudge(pVM);
4612	AssertLogRelRC(rc);
4613	}
4614	}
4615	if (RT_SUCCESS(rc))
4616	{
4617	/*
4618	* Move the MSR and CPUID arrays over to the static VM structure allocations
4619	* and explode guest CPU features again.
4620	*/
4621	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4622	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4623	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
4624	RTMemFree(pvFree);
4625
4626	AssertFatalMsg(pCpum->GuestInfo.cMsrRanges <= RT_ELEMENTS(pCpum->GuestInfo.aMsrRanges),
4627	("%u\n", pCpum->GuestInfo.cMsrRanges));
4628	memcpy(pCpum->GuestInfo.aMsrRanges, pCpum->GuestInfo.paMsrRangesR3,
4629	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges);
4630	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4631	pCpum->GuestInfo.paMsrRangesR3 = pCpum->GuestInfo.aMsrRanges;
4632
4633	AssertLogRelRCReturn(rc, rc);
4634
4635	/*
4636	* Finally, initialize guest VMX MSRs.
4637	*
4638	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
4639	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
4640	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
4641	*/
4642	if (pVM->cpum.s.GuestFeatures.fVmx)
4643	{
4644	Assert(Config.fNestedHWVirt);
4645	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
4646
4647	/* Copy MSRs to all VCPUs */
4648	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
4649	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4650	{
4651	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4652	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
4653	}
4654	}
4655
4656	/*
4657	* Some more configuration that we're applying at the end of everything
4658	* via the CPUMR3SetGuestCpuIdFeature API.
4659	*/
4660
4661	/* Check if PAE was explicitely enabled by the user. */
4662	bool fEnable;
4663	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4664	AssertRCReturn(rc, rc);
4665	if (fEnable)
4666	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4667
4668	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4669	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4670	AssertRCReturn(rc, rc);
4671	if (fEnable)
4672	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4673
4674	/* Check if speculation control is enabled. */
4675	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4676	AssertRCReturn(rc, rc);
4677	if (fEnable)
4678	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4679	else
4680	{
4681	/*
4682	* Set the "SSBD-not-needed" flag to work around a bug in some Linux kernels when the VIRT_SPEC_CTL
4683	* feature is not exposed on AMD CPUs and there is only 1 vCPU configured.
4684	* This was observed with kernel "4.15.0-29-generic #31~16.04.1-Ubuntu" but more versions are likely affected.
4685	*
4686	* The kernel doesn't initialize a lock and causes a NULL pointer exception later on when configuring SSBD:
4687	* EIP: _raw_spin_lock+0x14/0x30
4688	* EFLAGS: 00010046 CPU: 0
4689	* EAX: 00000000 EBX: 00000001 ECX: 00000004 EDX: 00000000
4690	* ESI: 00000000 EDI: 00000000 EBP: ee023f1c ESP: ee023f18
4691	* DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
4692	* CR0: 80050033 CR2: 00000004 CR3: 3671c180 CR4: 000006f0
4693	* Call Trace:
4694	* speculative_store_bypass_update+0x8e/0x180
4695	* ssb_prctl_set+0xc0/0xe0
4696	* arch_seccomp_spec_mitigate+0x1d/0x20
4697	* do_seccomp+0x3cb/0x610
4698	* SyS_seccomp+0x16/0x20
4699	* do_fast_syscall_32+0x7f/0x1d0
4700	* entry_SYSENTER_32+0x4e/0x7c
4701	*
4702	* The lock would've been initialized in process.c:speculative_store_bypass_ht_init() called from two places in smpboot.c.
4703	* First when a secondary CPU is started and second in native_smp_prepare_cpus() which is not called in a single vCPU environment.
4704	*
4705	* As spectre control features are completely disabled anyway when we arrived here there is no harm done in informing the
4706	* guest to not even try.
4707	*/
4708	if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4709	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
4710	{
4711	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x80000008), 0);
4712	if (pLeaf)
4713	{
4714	pLeaf->uEbx \|= X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED;
4715	LogRel(("CPUM: Set SSBD not required flag for AMD to work around some buggy Linux kernels!\n"));
4716	}
4717	}
4718	}
4719
4720	return VINF_SUCCESS;
4721	}
4722
4723	/*
4724	* Failed before switching to hyper heap.
4725	*/
4726	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4727	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4728	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4729	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4730	return rc;
4731	}
4732
4733
4734	/**
4735	* Sets a CPUID feature bit during VM initialization.
4736	*
4737	* Since the CPUID feature bits are generally related to CPU features, other
4738	* CPUM configuration like MSRs can also be modified by calls to this API.
4739	*
4740	* @param pVM The cross context VM structure.
4741	* @param enmFeature The feature to set.
4742	*/
4743	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4744	{
4745	PCPUMCPUIDLEAF pLeaf;
4746	PCPUMMSRRANGE pMsrRange;
4747
4748	switch (enmFeature)
4749	{
4750	/*
4751	* Set the APIC bit in both feature masks.
4752	*/
4753	case CPUMCPUIDFEATURE_APIC:
4754	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4755	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4756	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4757
4758	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4759	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4760	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4761
4762	pVM->cpum.s.GuestFeatures.fApic = 1;
4763
4764	/* Make sure we've got the APICBASE MSR present. */
4765	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4766	if (!pMsrRange)
4767	{
4768	static CPUMMSRRANGE const s_ApicBase =
4769	{
4770	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4771	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4772	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4773	/.szName = / "IA32_APIC_BASE"
4774	};
4775	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4776	AssertLogRelRC(rc);
4777	}
4778
4779	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4780	break;
4781
4782	/*
4783	* Set the x2APIC bit in the standard feature mask.
4784	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4785	*/
4786	case CPUMCPUIDFEATURE_X2APIC:
4787	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4788	if (pLeaf)
4789	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4790	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4791
4792	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4793	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4794	if (pMsrRange)
4795	{
4796	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4797	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4798	}
4799
4800	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4801	break;
4802
4803	/*
4804	* Set the sysenter/sysexit bit in the standard feature mask.
4805	* Assumes the caller knows what it's doing! (host must support these)
4806	*/
4807	case CPUMCPUIDFEATURE_SEP:
4808	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4809	{
4810	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4811	return;
4812	}
4813
4814	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4815	if (pLeaf)
4816	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4817	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4818	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4819	break;
4820
4821	/*
4822	* Set the syscall/sysret bit in the extended feature mask.
4823	* Assumes the caller knows what it's doing! (host must support these)
4824	*/
4825	case CPUMCPUIDFEATURE_SYSCALL:
4826	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4827	if ( !pLeaf
4828	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4829	{
4830	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4831	return;
4832	}
4833
4834	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4835	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4836	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4837	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4838	break;
4839
4840	/*
4841	* Set the PAE bit in both feature masks.
4842	* Assumes the caller knows what it's doing! (host must support these)
4843	*/
4844	case CPUMCPUIDFEATURE_PAE:
4845	if (!pVM->cpum.s.HostFeatures.fPae)
4846	{
4847	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4848	return;
4849	}
4850
4851	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4852	if (pLeaf)
4853	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4854
4855	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4856	if ( pLeaf
4857	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4858	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
4859	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4860
4861	pVM->cpum.s.GuestFeatures.fPae = 1;
4862	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4863	break;
4864
4865	/*
4866	* Set the LONG MODE bit in the extended feature mask.
4867	* Assumes the caller knows what it's doing! (host must support these)
4868	*/
4869	case CPUMCPUIDFEATURE_LONG_MODE:
4870	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4871	if ( !pLeaf
4872	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4873	{
4874	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4875	return;
4876	}
4877
4878	/* Valid for both Intel and AMD. */
4879	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4880	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4881	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
4882	if (pVM->cpum.s.GuestFeatures.fVmx)
4883	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4884	{
4885	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4886	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic &= ~VMX_BASIC_PHYSADDR_WIDTH_32BIT;
4887	}
4888	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4889	break;
4890
4891	/*
4892	* Set the NX/XD bit in the extended feature mask.
4893	* Assumes the caller knows what it's doing! (host must support these)
4894	*/
4895	case CPUMCPUIDFEATURE_NX:
4896	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4897	if ( !pLeaf
4898	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4899	{
4900	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4901	return;
4902	}
4903
4904	/* Valid for both Intel and AMD. */
4905	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4906	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4907	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4908	break;
4909
4910
4911	/*
4912	* Set the LAHF/SAHF support in 64-bit mode.
4913	* Assumes the caller knows what it's doing! (host must support this)
4914	*/
4915	case CPUMCPUIDFEATURE_LAHF:
4916	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4917	if ( !pLeaf
4918	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4919	{
4920	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4921	return;
4922	}
4923
4924	/* Valid for both Intel and AMD. */
4925	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4926	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4927	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4928	break;
4929
4930	/*
4931	* Set the RDTSCP support bit.
4932	* Assumes the caller knows what it's doing! (host must support this)
4933	*/
4934	case CPUMCPUIDFEATURE_RDTSCP:
4935	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4936	if ( !pLeaf
4937	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4938	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4939	{
4940	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4941	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4942	return;
4943	}
4944
4945	/* Valid for both Intel and AMD. */
4946	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4947	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4948	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4949	break;
4950
4951	/*
4952	* Set the Hypervisor Present bit in the standard feature mask.
4953	*/
4954	case CPUMCPUIDFEATURE_HVP:
4955	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4956	if (pLeaf)
4957	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4958	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4959	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4960	break;
4961
4962	/*
4963	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
4964	* on Intel CPUs, and different on AMDs.
4965	*/
4966	case CPUMCPUIDFEATURE_SPEC_CTRL:
4967	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4968	{
4969	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4970	if ( !pLeaf
4971	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
4972	{
4973	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4974	return;
4975	}
4976
4977	/* The feature can be enabled. Let's see what we can actually do. */
4978	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4979
4980	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4981	if (pVM->cpum.s.HostFeatures.fIbrs)
4982	{
4983	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4984	pVM->cpum.s.GuestFeatures.fIbrs = 1;
4985	if (pVM->cpum.s.HostFeatures.fStibp)
4986	{
4987	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4988	pVM->cpum.s.GuestFeatures.fStibp = 1;
4989	}
4990
4991	/* Make sure we have the speculation control MSR... */
4992	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4993	if (!pMsrRange)
4994	{
4995	static CPUMMSRRANGE const s_SpecCtrl =
4996	{
4997	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
4998	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
4999	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
5000	/.szName = / "IA32_SPEC_CTRL"
5001	};
5002	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
5003	AssertLogRelRC(rc);
5004	}
5005
5006	/* ... and the predictor command MSR. */
5007	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
5008	if (!pMsrRange)
5009	{
5010	/** @todo incorrect fWrGpMask. */
5011	static CPUMMSRRANGE const s_SpecCtrl =
5012	{
5013	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
5014	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
5015	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
5016	/.szName = / "IA32_PRED_CMD"
5017	};
5018	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
5019	AssertLogRelRC(rc);
5020	}
5021
5022	}
5023
5024	if (pVM->cpum.s.HostFeatures.fArchCap)
5025	{
5026	/* Install the architectural capabilities MSR. */
5027	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
5028	if (!pMsrRange)
5029	{
5030	static CPUMMSRRANGE const s_ArchCaps =
5031	{
5032	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
5033	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
5034	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
5035	/.szName = / "IA32_ARCH_CAPABILITIES"
5036	};
5037	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
5038	AssertLogRelRC(rc);
5039	}
5040
5041	/* Advertise IBRS_ALL if present at this point... */
5042	if (pVM->cpum.s.HostFeatures.fArchCap & MSR_IA32_ARCH_CAP_F_IBRS_ALL)
5043	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps \|= MSR_IA32_ARCH_CAP_F_IBRS_ALL);
5044	}
5045
5046	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
5047	}
5048	else if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
5049	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
5050	{
5051	/* The precise details of AMD's implementation are not yet clear. */
5052	}
5053	break;
5054
5055	default:
5056	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5057	break;
5058	}
5059
5060	/** @todo can probably kill this as this API is now init time only... */
5061	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5062	{
5063	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5064	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5065	}
5066	}
5067
5068
5069	/**
5070	* Queries a CPUID feature bit.
5071	*
5072	* @returns boolean for feature presence
5073	* @param pVM The cross context VM structure.
5074	* @param enmFeature The feature to query.
5075	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
5076	*/
5077	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5078	{
5079	switch (enmFeature)
5080	{
5081	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
5082	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
5083	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
5084	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
5085	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
5086	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
5087	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
5088	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
5089	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
5090	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
5091	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
5092	case CPUMCPUIDFEATURE_INVALID:
5093	case CPUMCPUIDFEATURE_32BIT_HACK:
5094	break;
5095	}
5096	AssertFailed();
5097	return false;
5098	}
5099
5100
5101	/**
5102	* Clears a CPUID feature bit.
5103	*
5104	* @param pVM The cross context VM structure.
5105	* @param enmFeature The feature to clear.
5106	*
5107	* @deprecated Probably better to default the feature to disabled and only allow
5108	* setting (enabling) it during construction.
5109	*/
5110	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5111	{
5112	PCPUMCPUIDLEAF pLeaf;
5113	switch (enmFeature)
5114	{
5115	case CPUMCPUIDFEATURE_APIC:
5116	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
5117	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5118	if (pLeaf)
5119	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
5120
5121	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5122	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
5123	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
5124
5125	pVM->cpum.s.GuestFeatures.fApic = 0;
5126	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
5127	break;
5128
5129	case CPUMCPUIDFEATURE_X2APIC:
5130	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
5131	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5132	if (pLeaf)
5133	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
5134	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
5135	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
5136	break;
5137
5138	case CPUMCPUIDFEATURE_PAE:
5139	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5140	if (pLeaf)
5141	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
5142
5143	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5144	if ( pLeaf
5145	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
5146	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
5147	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
5148
5149	pVM->cpum.s.GuestFeatures.fPae = 0;
5150	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
5151	break;
5152
5153	case CPUMCPUIDFEATURE_LONG_MODE:
5154	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5155	if (pLeaf)
5156	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
5157	pVM->cpum.s.GuestFeatures.fLongMode = 0;
5158	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
5159	if (pVM->cpum.s.GuestFeatures.fVmx)
5160	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5161	{
5162	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5163	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic \|= VMX_BASIC_PHYSADDR_WIDTH_32BIT;
5164	}
5165	break;
5166
5167	case CPUMCPUIDFEATURE_LAHF:
5168	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5169	if (pLeaf)
5170	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
5171	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
5172	break;
5173
5174	case CPUMCPUIDFEATURE_RDTSCP:
5175	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5176	if (pLeaf)
5177	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
5178	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
5179	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
5180	break;
5181
5182	case CPUMCPUIDFEATURE_HVP:
5183	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5184	if (pLeaf)
5185	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
5186	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
5187	break;
5188
5189	case CPUMCPUIDFEATURE_SPEC_CTRL:
5190	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
5191	if (pLeaf)
5192	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
5193	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL);
5194	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
5195	break;
5196
5197	default:
5198	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5199	break;
5200	}
5201
5202	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5203	{
5204	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5205	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
5206	}
5207	}
5208
5209
5210
5211	/*
5212	*
5213	*
5214	* Saved state related code.
5215	* Saved state related code.
5216	* Saved state related code.
5217	*
5218	*
5219	*/
5220
5221	/**
5222	* Called both in pass 0 and the final pass.
5223	*
5224	* @param pVM The cross context VM structure.
5225	* @param pSSM The saved state handle.
5226	*/
5227	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
5228	{
5229	/*
5230	* Save all the CPU ID leaves.
5231	*/
5232	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
5233	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5234	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
5235	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5236
5237	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5238
5239	/*
5240	* Save a good portion of the raw CPU IDs as well as they may come in
5241	* handy when validating features for raw mode.
5242	*/
5243	CPUMCPUID aRawStd[16];
5244	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
5245	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5246	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
5247	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
5248
5249	CPUMCPUID aRawExt[32];
5250	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
5251	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5252	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
5253	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
5254	}
5255
5256
5257	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5258	{
5259	uint32_t cCpuIds;
5260	int rc = SSMR3GetU32(pSSM, &cCpuIds);
5261	if (RT_SUCCESS(rc))
5262	{
5263	if (cCpuIds < 64)
5264	{
5265	for (uint32_t i = 0; i < cCpuIds; i++)
5266	{
5267	CPUMCPUID CpuId;
5268	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
5269	if (RT_FAILURE(rc))
5270	break;
5271
5272	CPUMCPUIDLEAF NewLeaf;
5273	NewLeaf.uLeaf = uBase + i;
5274	NewLeaf.uSubLeaf = 0;
5275	NewLeaf.fSubLeafMask = 0;
5276	NewLeaf.uEax = CpuId.uEax;
5277	NewLeaf.uEbx = CpuId.uEbx;
5278	NewLeaf.uEcx = CpuId.uEcx;
5279	NewLeaf.uEdx = CpuId.uEdx;
5280	NewLeaf.fFlags = 0;
5281	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
5282	}
5283	}
5284	else
5285	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5286	}
5287	if (RT_FAILURE(rc))
5288	{
5289	RTMemFree(*ppaLeaves);
5290	*ppaLeaves = NULL;
5291	*pcLeaves = 0;
5292	}
5293	return rc;
5294	}
5295
5296
5297	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
5298	{
5299	*ppaLeaves = NULL;
5300	*pcLeaves = 0;
5301
5302	int rc;
5303	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
5304	{
5305	/*
5306	* The new format. Starts by declaring the leave size and count.
5307	*/
5308	uint32_t cbLeaf;
5309	SSMR3GetU32(pSSM, &cbLeaf);
5310	uint32_t cLeaves;
5311	rc = SSMR3GetU32(pSSM, &cLeaves);
5312	if (RT_SUCCESS(rc))
5313	{
5314	if (cbLeaf == sizeof(**ppaLeaves))
5315	{
5316	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
5317	{
5318	/*
5319	* Load the leaves one by one.
5320	*
5321	* The uPrev stuff is a kludge for working around a week worth of bad saved
5322	* states during the CPUID revamp in March 2015. We saved too many leaves
5323	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
5324	* garbage entires at the end of the array when restoring. We also had
5325	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
5326	* this kludge doesn't deal correctly with that, but who cares...
5327	*/
5328	uint32_t uPrev = 0;
5329	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
5330	{
5331	CPUMCPUIDLEAF Leaf;
5332	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5333	if (RT_SUCCESS(rc))
5334	{
5335	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5336	\|\| Leaf.uLeaf >= uPrev)
5337	{
5338	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5339	uPrev = Leaf.uLeaf;
5340	}
5341	else
5342	uPrev = UINT32_MAX;
5343	}
5344	}
5345	}
5346	else
5347	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5348	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5349	}
5350	else
5351	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5352	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5353	}
5354	}
5355	else
5356	{
5357	/*
5358	* The old format with its three inflexible arrays.
5359	*/
5360	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5361	if (RT_SUCCESS(rc))
5362	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5363	if (RT_SUCCESS(rc))
5364	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5365	if (RT_SUCCESS(rc))
5366	{
5367	/*
5368	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5369	*/
5370	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5371	if ( pLeaf
5372	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5373	{
5374	CPUMCPUIDLEAF Leaf;
5375	Leaf.uLeaf = 4;
5376	Leaf.fSubLeafMask = UINT32_MAX;
5377	Leaf.uSubLeaf = 0;
5378	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5379	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5380	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5381	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5382	\| UINT32_C(63); /* system coherency line size - 1 */
5383	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5384	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5385	\| (UINT32_C(1) << 5) /* cache level */
5386	\| UINT32_C(1); /* cache type (data) */
5387	Leaf.fFlags = 0;
5388	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5389	if (RT_SUCCESS(rc))
5390	{
5391	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5392	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5393	}
5394	if (RT_SUCCESS(rc))
5395	{
5396	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5397	Leaf.uEcx = 4095; /* sets - 1 */
5398	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5399	Leaf.uEbx \|= UINT32_C(23) << 22;
5400	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5401	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5402	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5403	Leaf.uEax \|= UINT32_C(2) << 5;
5404	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5405	}
5406	}
5407	}
5408	}
5409	return rc;
5410	}
5411
5412
5413	/**
5414	* Loads the CPU ID leaves saved by pass 0, inner worker.
5415	*
5416	* @returns VBox status code.
5417	* @param pVM The cross context VM structure.
5418	* @param pSSM The saved state handle.
5419	* @param uVersion The format version.
5420	* @param paLeaves Guest CPUID leaves loaded from the state.
5421	* @param cLeaves The number of leaves in @a paLeaves.
5422	* @param pMsrs The guest MSRs.
5423	*/
5424	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
5425	{
5426	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5427
5428	/*
5429	* Continue loading the state into stack buffers.
5430	*/
5431	CPUMCPUID GuestDefCpuId;
5432	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5433	AssertRCReturn(rc, rc);
5434
5435	CPUMCPUID aRawStd[16];
5436	uint32_t cRawStd;
5437	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5438	if (cRawStd > RT_ELEMENTS(aRawStd))
5439	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5440	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5441	AssertRCReturn(rc, rc);
5442	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5443	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5444
5445	CPUMCPUID aRawExt[32];
5446	uint32_t cRawExt;
5447	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5448	if (cRawExt > RT_ELEMENTS(aRawExt))
5449	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5450	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5451	AssertRCReturn(rc, rc);
5452	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5453	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5454
5455	/*
5456	* Get the raw CPU IDs for the current host.
5457	*/
5458	CPUMCPUID aHostRawStd[16];
5459	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5460	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5461
5462	CPUMCPUID aHostRawExt[32];
5463	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5464	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5465	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5466
5467	/*
5468	* Get the host and guest overrides so we don't reject the state because
5469	* some feature was enabled thru these interfaces.
5470	* Note! We currently only need the feature leaves, so skip rest.
5471	*/
5472	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5473	CPUMCPUID aHostOverrideStd[2];
5474	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5475	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5476
5477	CPUMCPUID aHostOverrideExt[2];
5478	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5479	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5480
5481	/*
5482	* This can be skipped.
5483	*/
5484	bool fStrictCpuIdChecks;
5485	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5486
5487	/*
5488	* Define a bunch of macros for simplifying the santizing/checking code below.
5489	*/
5490	/* Generic expression + failure message. */
5491	#define CPUID_CHECK_RET(expr, fmt) \
5492	do { \
5493	if (!(expr)) \
5494	{ \
5495	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5496	if (fStrictCpuIdChecks) \
5497	{ \
5498	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5499	RTStrFree(pszMsg); \
5500	return rcCpuid; \
5501	} \
5502	LogRel(("CPUM: %s\n", pszMsg)); \
5503	RTStrFree(pszMsg); \
5504	} \
5505	} while (0)
5506	#define CPUID_CHECK_WRN(expr, fmt) \
5507	do { \
5508	if (!(expr)) \
5509	LogRel(fmt); \
5510	} while (0)
5511
5512	/* For comparing two values and bitch if they differs. */
5513	#define CPUID_CHECK2_RET(what, host, saved) \
5514	do { \
5515	if ((host) != (saved)) \
5516	{ \
5517	if (fStrictCpuIdChecks) \
5518	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5519	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5520	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5521	} \
5522	} while (0)
5523	#define CPUID_CHECK2_WRN(what, host, saved) \
5524	do { \
5525	if ((host) != (saved)) \
5526	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5527	} while (0)
5528
5529	/* For checking raw cpu features (raw mode). */
5530	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5531	do { \
5532	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5533	{ \
5534	if (fStrictCpuIdChecks) \
5535	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5536	N_(#bit " mismatch: host=%d saved=%d"), \
5537	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5538	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5539	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5540	} \
5541	} while (0)
5542	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5543	do { \
5544	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5545	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5546	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5547	} while (0)
5548	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5549
5550	/* For checking guest features. */
5551	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5552	do { \
5553	if ( (aGuestCpuId##set [1].reg & bit) \
5554	&& !(aHostRaw##set [1].reg & bit) \
5555	&& !(aHostOverride##set [1].reg & bit) \
5556	) \
5557	{ \
5558	if (fStrictCpuIdChecks) \
5559	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5560	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5561	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5562	} \
5563	} while (0)
5564	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5565	do { \
5566	if ( (aGuestCpuId##set [1].reg & bit) \
5567	&& !(aHostRaw##set [1].reg & bit) \
5568	&& !(aHostOverride##set [1].reg & bit) \
5569	) \
5570	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5571	} while (0)
5572	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5573	do { \
5574	if ( (aGuestCpuId##set [1].reg & bit) \
5575	&& !(aHostRaw##set [1].reg & bit) \
5576	&& !(aHostOverride##set [1].reg & bit) \
5577	) \
5578	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5579	} while (0)
5580	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5581
5582	/* For checking guest features if AMD guest CPU. */
5583	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5584	do { \
5585	if ( (aGuestCpuId##set [1].reg & bit) \
5586	&& fGuestAmd \
5587	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5588	&& !(aHostOverride##set [1].reg & bit) \
5589	) \
5590	{ \
5591	if (fStrictCpuIdChecks) \
5592	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5593	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5594	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5595	} \
5596	} while (0)
5597	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5598	do { \
5599	if ( (aGuestCpuId##set [1].reg & bit) \
5600	&& fGuestAmd \
5601	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5602	&& !(aHostOverride##set [1].reg & bit) \
5603	) \
5604	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5605	} while (0)
5606	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5607	do { \
5608	if ( (aGuestCpuId##set [1].reg & bit) \
5609	&& fGuestAmd \
5610	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5611	&& !(aHostOverride##set [1].reg & bit) \
5612	) \
5613	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5614	} while (0)
5615	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5616
5617	/* For checking AMD features which have a corresponding bit in the standard
5618	range. (Intel defines very few bits in the extended feature sets.) */
5619	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5620	do { \
5621	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5622	&& !(fHostAmd \
5623	? aHostRawExt[1].reg & (ExtBit) \
5624	: aHostRawStd[1].reg & (StdBit)) \
5625	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5626	) \
5627	{ \
5628	if (fStrictCpuIdChecks) \
5629	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5630	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5631	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5632	} \
5633	} while (0)
5634	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5635	do { \
5636	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5637	&& !(fHostAmd \
5638	? aHostRawExt[1].reg & (ExtBit) \
5639	: aHostRawStd[1].reg & (StdBit)) \
5640	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5641	) \
5642	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5643	} while (0)
5644	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5645	do { \
5646	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5647	&& !(fHostAmd \
5648	? aHostRawExt[1].reg & (ExtBit) \
5649	: aHostRawStd[1].reg & (StdBit)) \
5650	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5651	) \
5652	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5653	} while (0)
5654	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5655
5656
5657	/*
5658	* Verify that we can support the features already exposed to the guest on
5659	* this host.
5660	*
5661	* Most of the features we're emulating requires intercepting instruction
5662	* and doing it the slow way, so there is no need to warn when they aren't
5663	* present in the host CPU. Thus we use IGN instead of EMU on these.
5664	*
5665	* Trailing comments:
5666	* "EMU" - Possible to emulate, could be lots of work and very slow.
5667	* "EMU?" - Can this be emulated?
5668	*/
5669	CPUMCPUID aGuestCpuIdStd[2];
5670	RT_ZERO(aGuestCpuIdStd);
5671	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5672
5673	/* CPUID(1).ecx */
5674	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5675	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5676	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5677	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5678	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5679	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5680	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5681	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5682	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5683	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5684	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5685	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5686	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5687	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5688	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5689	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5690	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5691	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5692	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5693	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5694	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5695	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5696	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5697	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5698	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5699	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5700	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5701	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5702	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5703	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5704	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5705	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5706
5707	/* CPUID(1).edx */
5708	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5709	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5710	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5711	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5712	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5713	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5714	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5715	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5716	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5717	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5718	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5719	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5720	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5721	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5722	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5723	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5724	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5725	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5726	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5727	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5728	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5729	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5730	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5731	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5732	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5733	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5734	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5735	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5736	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5737	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5738	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5739	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5740
5741	/* CPUID(0x80000000). */
5742	CPUMCPUID aGuestCpuIdExt[2];
5743	RT_ZERO(aGuestCpuIdExt);
5744	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5745	{
5746	/** @todo deal with no 0x80000001 on the host. */
5747	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx)
5748	\|\| ASMIsHygonCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5749	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx)
5750	\|\| ASMIsHygonCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5751
5752	/* CPUID(0x80000001).ecx */
5753	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5754	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5755	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5756	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5757	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5758	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5759	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5760	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5761	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5762	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5763	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5764	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5765	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5766	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5767	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5768	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5769	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5770	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5771	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5772	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5773	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5774	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5775	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5776	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5777	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5778	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5779	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5780	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5781	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5782	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5783	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5784	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5785
5786	/* CPUID(0x80000001).edx */
5787	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5788	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5789	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5790	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5791	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5792	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5793	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5794	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5795	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5796	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5797	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5798	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5799	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5800	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5801	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5802	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5803	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5804	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5805	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5806	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5807	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5808	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5809	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5810	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5811	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5812	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5813	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5814	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5815	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5816	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5817	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5818	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5819	}
5820
5821	/** @todo check leaf 7 */
5822
5823	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5824	* ECX=0: EAX - Valid bits in XCR0[31:0].
5825	* EBX - Maximum state size as per current XCR0 value.
5826	* ECX - Maximum state size for all supported features.
5827	* EDX - Valid bits in XCR0[63:32].
5828	* ECX=1: EAX - Various X-features.
5829	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5830	* ECX - Valid bits in IA32_XSS[31:0].
5831	* EDX - Valid bits in IA32_XSS[63:32].
5832	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5833	* if the bit invalid all four registers are set to zero.
5834	* EAX - The state size for this feature.
5835	* EBX - The state byte offset of this feature.
5836	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5837	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5838	*/
5839	uint64_t fGuestXcr0Mask = 0;
5840	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5841	if ( pCurLeaf
5842	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5843	&& ( pCurLeaf->uEax
5844	\|\| pCurLeaf->uEbx
5845	\|\| pCurLeaf->uEcx
5846	\|\| pCurLeaf->uEdx) )
5847	{
5848	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5849	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5850	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5851	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5852	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5853	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5854	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5855	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5856
5857	/* We don't support any additional features yet. */
5858	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5859	if (pCurLeaf && pCurLeaf->uEax)
5860	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5861	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5862	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5863	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5864	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5865	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5866
5867
5868	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5869	{
5870	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5871	if (pCurLeaf)
5872	{
5873	/* If advertised, the state component offset and size must match the one used by host. */
5874	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5875	{
5876	CPUMCPUID RawHost;
5877	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5878	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5879	if ( RawHost.uEbx != pCurLeaf->uEbx
5880	\|\| RawHost.uEax != pCurLeaf->uEax)
5881	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5882	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5883	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5884	}
5885	}
5886	}
5887	}
5888	/* Clear leaf 0xd just in case we're loading an old state... */
5889	else if (pCurLeaf)
5890	{
5891	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5892	{
5893	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5894	if (pCurLeaf)
5895	{
5896	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5897	\|\| ( pCurLeaf->uEax == 0
5898	&& pCurLeaf->uEbx == 0
5899	&& pCurLeaf->uEcx == 0
5900	&& pCurLeaf->uEdx == 0),
5901	("uVersion=%#x; %#x %#x %#x %#x\n",
5902	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5903	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5904	}
5905	}
5906	}
5907
5908	/* Update the fXStateGuestMask value for the VM. */
5909	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5910	{
5911	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5912	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5913	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5914	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5915	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5916	}
5917
5918	#undef CPUID_CHECK_RET
5919	#undef CPUID_CHECK_WRN
5920	#undef CPUID_CHECK2_RET
5921	#undef CPUID_CHECK2_WRN
5922	#undef CPUID_RAW_FEATURE_RET
5923	#undef CPUID_RAW_FEATURE_WRN
5924	#undef CPUID_RAW_FEATURE_IGN
5925	#undef CPUID_GST_FEATURE_RET
5926	#undef CPUID_GST_FEATURE_WRN
5927	#undef CPUID_GST_FEATURE_EMU
5928	#undef CPUID_GST_FEATURE_IGN
5929	#undef CPUID_GST_FEATURE2_RET
5930	#undef CPUID_GST_FEATURE2_WRN
5931	#undef CPUID_GST_FEATURE2_EMU
5932	#undef CPUID_GST_FEATURE2_IGN
5933	#undef CPUID_GST_AMD_FEATURE_RET
5934	#undef CPUID_GST_AMD_FEATURE_WRN
5935	#undef CPUID_GST_AMD_FEATURE_EMU
5936	#undef CPUID_GST_AMD_FEATURE_IGN
5937
5938	/*
5939	* We're good, commit the CPU ID leaves.
5940	*/
5941	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5942	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
5943	AssertLogRelRCReturn(rc, rc);
5944
5945	return VINF_SUCCESS;
5946	}
5947
5948
5949	/**
5950	* Loads the CPU ID leaves saved by pass 0.
5951	*
5952	* @returns VBox status code.
5953	* @param pVM The cross context VM structure.
5954	* @param pSSM The saved state handle.
5955	* @param uVersion The format version.
5956	* @param pMsrs The guest MSRs.
5957	*/
5958	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
5959	{
5960	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5961
5962	/*
5963	* Load the CPUID leaves array first and call worker to do the rest, just so
5964	* we can free the memory when we need to without ending up in column 1000.
5965	*/
5966	PCPUMCPUIDLEAF paLeaves;
5967	uint32_t cLeaves;
5968	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5969	AssertRC(rc);
5970	if (RT_SUCCESS(rc))
5971	{
5972	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
5973	RTMemFree(paLeaves);
5974	}
5975	return rc;
5976	}
5977
5978
5979
5980	/**
5981	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5982	*
5983	* @returns VBox status code.
5984	* @param pVM The cross context VM structure.
5985	* @param pSSM The saved state handle.
5986	* @param uVersion The format version.
5987	*/
5988	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5989	{
5990	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5991
5992	/*
5993	* Restore the CPUID leaves.
5994	*
5995	* Note that we support restoring less than the current amount of standard
5996	* leaves because we've been allowed more is newer version of VBox.
5997	*/
5998	uint32_t cElements;
5999	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6000	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
6001	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6002	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
6003
6004	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6005	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
6006	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6007	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
6008
6009	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6010	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
6011	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6012	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
6013
6014	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
6015
6016	/*
6017	* Check that the basic cpuid id information is unchanged.
6018	*/
6019	/** @todo we should check the 64 bits capabilities too! */
6020	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
6021	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
6022	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
6023	uint32_t au32CpuIdSaved[8];
6024	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
6025	if (RT_SUCCESS(rc))
6026	{
6027	/* Ignore CPU stepping. */
6028	au32CpuId[4] &= 0xfffffff0;
6029	au32CpuIdSaved[4] &= 0xfffffff0;
6030
6031	/* Ignore APIC ID (AMD specs). */
6032	au32CpuId[5] &= ~0xff000000;
6033	au32CpuIdSaved[5] &= ~0xff000000;
6034
6035	/* Ignore the number of Logical CPUs (AMD specs). */
6036	au32CpuId[5] &= ~0x00ff0000;
6037	au32CpuIdSaved[5] &= ~0x00ff0000;
6038
6039	/* Ignore some advanced capability bits, that we don't expose to the guest. */
6040	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6041	\| X86_CPUID_FEATURE_ECX_VMX
6042	\| X86_CPUID_FEATURE_ECX_SMX
6043	\| X86_CPUID_FEATURE_ECX_EST
6044	\| X86_CPUID_FEATURE_ECX_TM2
6045	\| X86_CPUID_FEATURE_ECX_CNTXID
6046	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6047	\| X86_CPUID_FEATURE_ECX_PDCM
6048	\| X86_CPUID_FEATURE_ECX_DCA
6049	\| X86_CPUID_FEATURE_ECX_X2APIC
6050	);
6051	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6052	\| X86_CPUID_FEATURE_ECX_VMX
6053	\| X86_CPUID_FEATURE_ECX_SMX
6054	\| X86_CPUID_FEATURE_ECX_EST
6055	\| X86_CPUID_FEATURE_ECX_TM2
6056	\| X86_CPUID_FEATURE_ECX_CNTXID
6057	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6058	\| X86_CPUID_FEATURE_ECX_PDCM
6059	\| X86_CPUID_FEATURE_ECX_DCA
6060	\| X86_CPUID_FEATURE_ECX_X2APIC
6061	);
6062
6063	/* Make sure we don't forget to update the masks when enabling
6064	* features in the future.
6065	*/
6066	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
6067	( X86_CPUID_FEATURE_ECX_DTES64
6068	\| X86_CPUID_FEATURE_ECX_VMX
6069	\| X86_CPUID_FEATURE_ECX_SMX
6070	\| X86_CPUID_FEATURE_ECX_EST
6071	\| X86_CPUID_FEATURE_ECX_TM2
6072	\| X86_CPUID_FEATURE_ECX_CNTXID
6073	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
6074	\| X86_CPUID_FEATURE_ECX_PDCM
6075	\| X86_CPUID_FEATURE_ECX_DCA
6076	\| X86_CPUID_FEATURE_ECX_X2APIC
6077	)));
6078	/* do the compare */
6079	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
6080	{
6081	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
6082	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
6083	"Saved=%.*Rhxs\n"
6084	"Real =%.*Rhxs\n",
6085	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6086	sizeof(au32CpuId), au32CpuId));
6087	else
6088	{
6089	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
6090	"Saved=%.*Rhxs\n"
6091	"Real =%.*Rhxs\n",
6092	sizeof(au32CpuIdSaved), au32CpuIdSaved,
6093	sizeof(au32CpuId), au32CpuId));
6094	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
6095	}
6096	}
6097	}
6098
6099	return rc;
6100	}
6101
6102
6103
6104	/*
6105	*
6106	*
6107	* CPUID Info Handler.
6108	* CPUID Info Handler.
6109	* CPUID Info Handler.
6110	*
6111	*
6112	*/
6113
6114
6115
6116	/**
6117	* Get L1 cache / TLS associativity.
6118	*/
6119	static const char getCacheAss(unsigned u, char pszBuf)
6120	{
6121	if (u == 0)
6122	return "res0 ";
6123	if (u == 1)
6124	return "direct";
6125	if (u == 255)
6126	return "fully";
6127	if (u >= 256)
6128	return "???";
6129
6130	RTStrPrintf(pszBuf, 16, "%d way", u);
6131	return pszBuf;
6132	}
6133
6134
6135	/**
6136	* Get L2 cache associativity.
6137	*/
6138	const char *getL2CacheAss(unsigned u)
6139	{
6140	switch (u)
6141	{
6142	case 0: return "off ";
6143	case 1: return "direct";
6144	case 2: return "2 way ";
6145	case 3: return "res3 ";
6146	case 4: return "4 way ";
6147	case 5: return "res5 ";
6148	case 6: return "8 way ";
6149	case 7: return "res7 ";
6150	case 8: return "16 way";
6151	case 9: return "res9 ";
6152	case 10: return "res10 ";
6153	case 11: return "res11 ";
6154	case 12: return "res12 ";
6155	case 13: return "res13 ";
6156	case 14: return "res14 ";
6157	case 15: return "fully ";
6158	default: return "????";
6159	}
6160	}
6161
6162
6163	/** CPUID(1).EDX field descriptions. */
6164	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6165	{
6166	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6167	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6168	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6169	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6170	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6171	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6172	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6173	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6174	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6175	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6176	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6177	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6178	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6179	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6180	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6181	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6182	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6183	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6184	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6185	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6186	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6187	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6188	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6189	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6190	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6191	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6192	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6193	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6194	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6195	DBGFREGSUBFIELD_TERMINATOR()
6196	};
6197
6198	/** CPUID(1).ECX field descriptions. */
6199	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6200	{
6201	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6202	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6203	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6204	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6205	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6206	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6207	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6208	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6209	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6210	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6211	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6212	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6213	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6214	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6215	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6216	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6217	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6218	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6219	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6220	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6221	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6222	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6223	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6224	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6225	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6226	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6227	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6228	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6229	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6230	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6231	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6232	DBGFREGSUBFIELD_TERMINATOR()
6233	};
6234
6235	/** CPUID(7,0).EBX field descriptions. */
6236	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6237	{
6238	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6239	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6240	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6241	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6242	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6243	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6244	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6245	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6246	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6247	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6248	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6249	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6250	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6251	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6252	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6253	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6254	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6255	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6256	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6257	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6258	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6259	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6260	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6261	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6262	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6263	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6264	DBGFREGSUBFIELD_TERMINATOR()
6265	};
6266
6267	/** CPUID(7,0).ECX field descriptions. */
6268	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6269	{
6270	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6271	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6272	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6273	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6274	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6275	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6276	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6277	DBGFREGSUBFIELD_TERMINATOR()
6278	};
6279
6280	/** CPUID(7,0).EDX field descriptions. */
6281	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6282	{
6283	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
6284	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6285	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6286	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
6287	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6288	DBGFREGSUBFIELD_RO("CORECAP\0" "Supports IA32_CORE_CAP", 30, 1, 0),
6289	DBGFREGSUBFIELD_RO("SSBD\0" "Supports IA32_SPEC_CTRL.SSBD", 31, 1, 0),
6290	DBGFREGSUBFIELD_TERMINATOR()
6291	};
6292
6293
6294	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6295	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6296	{
6297	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6298	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6299	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6300	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6301	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6302	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6303	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6304	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6305	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6306	DBGFREGSUBFIELD_TERMINATOR()
6307	};
6308
6309	/** CPUID(13,1).EAX field descriptions. */
6310	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6311	{
6312	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6313	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6314	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6315	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6316	DBGFREGSUBFIELD_TERMINATOR()
6317	};
6318
6319
6320	/** CPUID(0x80000001,0).EDX field descriptions. */
6321	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6322	{
6323	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6324	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6325	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6326	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6327	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6328	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6329	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6330	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6331	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6332	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6333	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6334	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6335	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6336	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6337	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6338	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6339	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6340	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6341	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6342	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6343	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6344	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6345	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6346	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6347	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6348	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6349	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6350	DBGFREGSUBFIELD_TERMINATOR()
6351	};
6352
6353	/** CPUID(0x80000001,0).ECX field descriptions. */
6354	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6355	{
6356	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6357	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6358	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6359	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6360	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6361	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6362	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6363	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6364	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6365	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6366	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6367	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6368	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6369	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6370	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6371	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6372	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6373	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6374	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6375	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6376	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6377	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6378	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6379	DBGFREGSUBFIELD_RO("PCX_L2I\0" "L2I/L3 Performance Counter Extensions", 28, 1, 0),
6380	DBGFREGSUBFIELD_RO("MWAITX\0" "MWAITX and MONITORX instructions", 29, 1, 0),
6381	DBGFREGSUBFIELD_TERMINATOR()
6382	};
6383
6384	/** CPUID(0x8000000a,0).EDX field descriptions. */
6385	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6386	{
6387	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6388	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6389	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6390	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6391	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6392	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6393	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6394	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6395	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6396	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6397	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6398	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6399	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6400	DBGFREGSUBFIELD_RO("GMET\0" "Guest Mode Execute Trap Extension", 17, 1, 0),
6401	DBGFREGSUBFIELD_TERMINATOR()
6402	};
6403
6404
6405	/** CPUID(0x80000007,0).EDX field descriptions. */
6406	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6407	{
6408	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6409	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6410	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6411	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6412	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6413	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6414	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6415	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6416	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6417	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6418	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6419	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6420	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6421	DBGFREGSUBFIELD_TERMINATOR()
6422	};
6423
6424	/** CPUID(0x80000008,0).EBX field descriptions. */
6425	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6426	{
6427	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6428	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6429	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6430	DBGFREGSUBFIELD_RO("RDPRU\0" "RDPRU instruction", 4, 1, 0),
6431	DBGFREGSUBFIELD_RO("MCOMMIT\0" "MCOMMIT instruction", 8, 1, 0),
6432	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6433	DBGFREGSUBFIELD_TERMINATOR()
6434	};
6435
6436
6437	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6438	const char *pszLeadIn, uint32_t cchWidth)
6439	{
6440	if (pszLeadIn)
6441	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6442
6443	for (uint32_t iBit = 0; iBit < 32; iBit++)
6444	if (RT_BIT_32(iBit) & uVal)
6445	{
6446	while ( pDesc->pszName != NULL
6447	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6448	pDesc++;
6449	if ( pDesc->pszName != NULL
6450	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6451	{
6452	if (pDesc->cBits == 1)
6453	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6454	else
6455	{
6456	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6457	if (pDesc->cBits < 32)
6458	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6459	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6460	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6461	}
6462	}
6463	else
6464	pHlp->pfnPrintf(pHlp, " %u", iBit);
6465	}
6466	if (pszLeadIn)
6467	pHlp->pfnPrintf(pHlp, "\n");
6468	}
6469
6470
6471	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6472	const char *pszLeadIn, uint32_t cchWidth)
6473	{
6474	if (pszLeadIn)
6475	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6476
6477	for (uint32_t iBit = 0; iBit < 64; iBit++)
6478	if (RT_BIT_64(iBit) & uVal)
6479	{
6480	while ( pDesc->pszName != NULL
6481	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6482	pDesc++;
6483	if ( pDesc->pszName != NULL
6484	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6485	{
6486	if (pDesc->cBits == 1)
6487	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6488	else
6489	{
6490	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6491	if (pDesc->cBits < 64)
6492	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6493	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6494	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6495	}
6496	}
6497	else
6498	pHlp->pfnPrintf(pHlp, " %u", iBit);
6499	}
6500	if (pszLeadIn)
6501	pHlp->pfnPrintf(pHlp, "\n");
6502	}
6503
6504
6505	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6506	const char *pszLeadIn, uint32_t cchWidth)
6507	{
6508	if (!uVal)
6509	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6510	else
6511	{
6512	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6513	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6514	pHlp->pfnPrintf(pHlp, " )\n");
6515	}
6516	}
6517
6518
6519	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6520	uint32_t cchWidth)
6521	{
6522	uint32_t uCombined = uVal1 \| uVal2;
6523	for (uint32_t iBit = 0; iBit < 32; iBit++)
6524	if ( (RT_BIT_32(iBit) & uCombined)
6525	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6526	{
6527	while ( pDesc->pszName != NULL
6528	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6529	pDesc++;
6530
6531	if ( pDesc->pszName != NULL
6532	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6533	{
6534	size_t cchMnemonic = strlen(pDesc->pszName);
6535	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6536	size_t cchDesc = strlen(pszDesc);
6537	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6538	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6539	if (pDesc->cBits < 32)
6540	{
6541	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6542	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6543	}
6544
6545	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6546	pDesc->pszName, pszDesc,
6547	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6548	uFieldValue1, uFieldValue2);
6549
6550	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6551	pDesc++;
6552	}
6553	else
6554	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6555	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6556	}
6557	}
6558
6559
6560	/**
6561	* Produces a detailed summary of standard leaf 0x00000001.
6562	*
6563	* @param pHlp The info helper functions.
6564	* @param pCurLeaf The 0x00000001 leaf.
6565	* @param fVerbose Whether to be very verbose or not.
6566	* @param fIntel Set if intel CPU.
6567	*/
6568	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6569	{
6570	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6571	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6572	uint32_t uEAX = pCurLeaf->uEax;
6573	uint32_t uEBX = pCurLeaf->uEbx;
6574
6575	pHlp->pfnPrintf(pHlp,
6576	"%36s %2d \tExtended: %d \tEffective: %d\n"
6577	"%36s %2d \tExtended: %d \tEffective: %d\n"
6578	"%36s %d\n"
6579	"%36s %d (%s)\n"
6580	"%36s %#04x\n"
6581	"%36s %d\n"
6582	"%36s %d\n"
6583	"%36s %#04x\n"
6584	,
6585	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6586	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6587	"Stepping:", ASMGetCpuStepping(uEAX),
6588	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6589	"APIC ID:", (uEBX >> 24) & 0xff,
6590	"Logical CPUs:",(uEBX >> 16) & 0xff,
6591	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6592	"Brand ID:", (uEBX >> 0) & 0xff);
6593	if (fVerbose)
6594	{
6595	CPUMCPUID Host;
6596	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6597	pHlp->pfnPrintf(pHlp, "Features\n");
6598	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6599	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6600	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6601	}
6602	else
6603	{
6604	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6605	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6606	}
6607	}
6608
6609
6610	/**
6611	* Produces a detailed summary of standard leaf 0x00000007.
6612	*
6613	* @param pHlp The info helper functions.
6614	* @param paLeaves The CPUID leaves array.
6615	* @param cLeaves The number of leaves in the array.
6616	* @param pCurLeaf The first 0x00000007 leaf.
6617	* @param fVerbose Whether to be very verbose or not.
6618	*/
6619	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6620	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6621	{
6622	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6623	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6624	for (;;)
6625	{
6626	CPUMCPUID Host;
6627	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6628
6629	switch (pCurLeaf->uSubLeaf)
6630	{
6631	case 0:
6632	if (fVerbose)
6633	{
6634	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6635	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6636	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6637	if (pCurLeaf->uEdx \|\| Host.uEdx)
6638	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6639	}
6640	else
6641	{
6642	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6643	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6644	if (pCurLeaf->uEdx)
6645	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6646	}
6647	break;
6648
6649	default:
6650	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6651	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6652	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6653	break;
6654
6655	}
6656
6657	/* advance. */
6658	pCurLeaf++;
6659	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6660	\|\| pCurLeaf->uLeaf != 0x7)
6661	break;
6662	}
6663	}
6664
6665
6666	/**
6667	* Produces a detailed summary of standard leaf 0x0000000d.
6668	*
6669	* @param pHlp The info helper functions.
6670	* @param paLeaves The CPUID leaves array.
6671	* @param cLeaves The number of leaves in the array.
6672	* @param pCurLeaf The first 0x00000007 leaf.
6673	* @param fVerbose Whether to be very verbose or not.
6674	*/
6675	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6676	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6677	{
6678	RT_NOREF_PV(fVerbose);
6679	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6680	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6681	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6682	{
6683	CPUMCPUID Host;
6684	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6685
6686	switch (uSubLeaf)
6687	{
6688	case 0:
6689	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6690	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6691	pCurLeaf->uEbx, pCurLeaf->uEcx);
6692	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6693
6694	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6695	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6696	"Valid XCR0 bits, guest:", 42);
6697	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6698	"Valid XCR0 bits, host:", 42);
6699	break;
6700
6701	case 1:
6702	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6703	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6704	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6705
6706	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6707	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6708	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6709
6710	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6711	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6712	" Valid IA32_XSS bits, guest:", 42);
6713	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6714	" Valid IA32_XSS bits, host:", 42);
6715	break;
6716
6717	default:
6718	if ( pCurLeaf
6719	&& pCurLeaf->uSubLeaf == uSubLeaf
6720	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6721	{
6722	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6723	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6724	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6725	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6726	if (pCurLeaf->uEdx)
6727	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6728	pHlp->pfnPrintf(pHlp, " --");
6729	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6730	pHlp->pfnPrintf(pHlp, "\n");
6731	}
6732	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6733	{
6734	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6735	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6736	if (Host.uEcx & ~RT_BIT_32(0))
6737	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6738	if (Host.uEdx)
6739	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6740	pHlp->pfnPrintf(pHlp, " --");
6741	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6742	pHlp->pfnPrintf(pHlp, "\n");
6743	}
6744	break;
6745
6746	}
6747
6748	/* advance. */
6749	if (pCurLeaf)
6750	{
6751	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6752	&& pCurLeaf->uSubLeaf <= uSubLeaf
6753	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6754	pCurLeaf++;
6755	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6756	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6757	pCurLeaf = NULL;
6758	}
6759	}
6760	}
6761
6762
6763	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6764	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6765	{
6766	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6767	&& pCurLeaf->uLeaf <= uUpToLeaf)
6768	{
6769	pHlp->pfnPrintf(pHlp,
6770	" %s\n"
6771	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6772	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6773	&& pCurLeaf->uLeaf <= uUpToLeaf)
6774	{
6775	CPUMCPUID Host;
6776	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6777	pHlp->pfnPrintf(pHlp,
6778	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6779	"Hst: %08x %08x %08x %08x\n",
6780	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6781	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6782	pCurLeaf++;
6783	}
6784	}
6785
6786	return pCurLeaf;
6787	}
6788
6789
6790	/**
6791	* Display the guest CpuId leaves.
6792	*
6793	* @param pVM The cross context VM structure.
6794	* @param pHlp The info helper functions.
6795	* @param pszArgs "terse", "default" or "verbose".
6796	*/
6797	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6798	{
6799	/*
6800	* Parse the argument.
6801	*/
6802	unsigned iVerbosity = 1;
6803	if (pszArgs)
6804	{
6805	pszArgs = RTStrStripL(pszArgs);
6806	if (!strcmp(pszArgs, "terse"))
6807	iVerbosity--;
6808	else if (!strcmp(pszArgs, "verbose"))
6809	iVerbosity++;
6810	}
6811
6812	uint32_t uLeaf;
6813	CPUMCPUID Host;
6814	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6815	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6816	PCCPUMCPUIDLEAF pCurLeaf;
6817	PCCPUMCPUIDLEAF pNextLeaf;
6818	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6819	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6820	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6821
6822	/*
6823	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6824	*/
6825	uint32_t cHstMax = ASMCpuId_EAX(0);
6826	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6827	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6828	pHlp->pfnPrintf(pHlp,
6829	" Raw Standard CPUID Leaves\n"
6830	" Leaf/sub-leaf eax ebx ecx edx\n");
6831	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6832	{
6833	uint32_t cMaxSubLeaves = 1;
6834	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6835	cMaxSubLeaves = 16;
6836	else if (uLeaf == 0xd)
6837	cMaxSubLeaves = 128;
6838
6839	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6840	{
6841	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6842	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6843	&& pCurLeaf->uLeaf == uLeaf
6844	&& pCurLeaf->uSubLeaf == uSubLeaf)
6845	{
6846	pHlp->pfnPrintf(pHlp,
6847	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6848	"Hst: %08x %08x %08x %08x\n",
6849	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6850	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6851	pCurLeaf++;
6852	}
6853	else if ( uLeaf != 0xd
6854	\|\| uSubLeaf <= 1
6855	\|\| Host.uEbx != 0 )
6856	pHlp->pfnPrintf(pHlp,
6857	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6858	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6859
6860	/* Done? */
6861	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6862	\|\| pCurLeaf->uLeaf != uLeaf)
6863	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6864	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6865	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6866	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6867	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6868	)
6869	)
6870	break;
6871	}
6872	}
6873	pNextLeaf = pCurLeaf;
6874
6875	/*
6876	* If verbose, decode it.
6877	*/
6878	if (iVerbosity && paLeaves[0].uLeaf == 0)
6879	pHlp->pfnPrintf(pHlp,
6880	"%36s %.04s%.04s%.04s\n"
6881	"%36s 0x00000000-%#010x\n"
6882	,
6883	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6884	"Supports:", paLeaves[0].uEax);
6885
6886	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6887	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6888
6889	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6890	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6891
6892	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6893	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6894
6895	pCurLeaf = pNextLeaf;
6896
6897	/*
6898	* Hypervisor leaves.
6899	*
6900	* Unlike most of the other leaves reported, the guest hypervisor leaves
6901	* aren't a subset of the host CPUID bits.
6902	*/
6903	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6904
6905	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6906	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6907	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6908	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6909	cMax = RT_MAX(cHstMax, cGstMax);
6910	if (cMax >= UINT32_C(0x40000000))
6911	{
6912	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6913
6914	/** @todo dump these in more detail. */
6915
6916	pCurLeaf = pNextLeaf;
6917	}
6918
6919
6920	/*
6921	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6922	* Implemented after AMD specs.
6923	*/
6924	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6925
6926	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6927	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6928	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6929	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6930	cMax = RT_MAX(cHstMax, cGstMax);
6931	if (cMax >= UINT32_C(0x80000000))
6932	{
6933
6934	pHlp->pfnPrintf(pHlp,
6935	" Raw Extended CPUID Leaves\n"
6936	" Leaf/sub-leaf eax ebx ecx edx\n");
6937	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6938	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6939	{
6940	uint32_t cMaxSubLeaves = 1;
6941	if (uLeaf == UINT32_C(0x8000001d))
6942	cMaxSubLeaves = 16;
6943
6944	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6945	{
6946	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6947	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6948	&& pCurLeaf->uLeaf == uLeaf
6949	&& pCurLeaf->uSubLeaf == uSubLeaf)
6950	{
6951	pHlp->pfnPrintf(pHlp,
6952	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6953	"Hst: %08x %08x %08x %08x\n",
6954	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6955	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6956	pCurLeaf++;
6957	}
6958	else if ( uLeaf != 0xd
6959	\|\| uSubLeaf <= 1
6960	\|\| Host.uEbx != 0 )
6961	pHlp->pfnPrintf(pHlp,
6962	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6963	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6964
6965	/* Done? */
6966	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6967	\|\| pCurLeaf->uLeaf != uLeaf)
6968	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6969	break;
6970	}
6971	}
6972	pNextLeaf = pCurLeaf;
6973
6974	/*
6975	* Understandable output
6976	*/
6977	if (iVerbosity)
6978	pHlp->pfnPrintf(pHlp,
6979	"Ext Name: %.4s%.4s%.4s\n"
6980	"Ext Supports: 0x80000000-%#010x\n",
6981	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6982
6983	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6984	if (iVerbosity && pCurLeaf)
6985	{
6986	uint32_t uEAX = pCurLeaf->uEax;
6987	pHlp->pfnPrintf(pHlp,
6988	"Family: %d \tExtended: %d \tEffective: %d\n"
6989	"Model: %d \tExtended: %d \tEffective: %d\n"
6990	"Stepping: %d\n"
6991	"Brand ID: %#05x\n",
6992	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6993	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6994	ASMGetCpuStepping(uEAX),
6995	pCurLeaf->uEbx & 0xfff);
6996
6997	if (iVerbosity == 1)
6998	{
6999	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
7000	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
7001	}
7002	else
7003	{
7004	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7005	pHlp->pfnPrintf(pHlp, "Ext Features\n");
7006	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
7007	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
7008	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
7009	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
7010	{
7011	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
7012	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7013	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
7014	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
7015	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
7016	}
7017	}
7018	}
7019
7020	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
7021	{
7022	char szString[443+1] = {0};
7023	uint32_t pu32 = (uint32_t )szString;
7024	*pu32++ = pCurLeaf->uEax;
7025	*pu32++ = pCurLeaf->uEbx;
7026	*pu32++ = pCurLeaf->uEcx;
7027	*pu32++ = pCurLeaf->uEdx;
7028	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
7029	if (pCurLeaf)
7030	{
7031	*pu32++ = pCurLeaf->uEax;
7032	*pu32++ = pCurLeaf->uEbx;
7033	*pu32++ = pCurLeaf->uEcx;
7034	*pu32++ = pCurLeaf->uEdx;
7035	}
7036	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
7037	if (pCurLeaf)
7038	{
7039	*pu32++ = pCurLeaf->uEax;
7040	*pu32++ = pCurLeaf->uEbx;
7041	*pu32++ = pCurLeaf->uEcx;
7042	*pu32++ = pCurLeaf->uEdx;
7043	}
7044	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
7045	}
7046
7047	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
7048	{
7049	uint32_t uEAX = pCurLeaf->uEax;
7050	uint32_t uEBX = pCurLeaf->uEbx;
7051	uint32_t uECX = pCurLeaf->uEcx;
7052	uint32_t uEDX = pCurLeaf->uEdx;
7053	char sz1[32];
7054	char sz2[32];
7055
7056	pHlp->pfnPrintf(pHlp,
7057	"TLB 2/4M Instr/Uni: %s %3d entries\n"
7058	"TLB 2/4M Data: %s %3d entries\n",
7059	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
7060	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
7061	pHlp->pfnPrintf(pHlp,
7062	"TLB 4K Instr/Uni: %s %3d entries\n"
7063	"TLB 4K Data: %s %3d entries\n",
7064	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
7065	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
7066	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
7067	"L1 Instr Cache Lines Per Tag: %d\n"
7068	"L1 Instr Cache Associativity: %s\n"
7069	"L1 Instr Cache Size: %d KB\n",
7070	(uEDX >> 0) & 0xff,
7071	(uEDX >> 8) & 0xff,
7072	getCacheAss((uEDX >> 16) & 0xff, sz1),
7073	(uEDX >> 24) & 0xff);
7074	pHlp->pfnPrintf(pHlp,
7075	"L1 Data Cache Line Size: %d bytes\n"
7076	"L1 Data Cache Lines Per Tag: %d\n"
7077	"L1 Data Cache Associativity: %s\n"
7078	"L1 Data Cache Size: %d KB\n",
7079	(uECX >> 0) & 0xff,
7080	(uECX >> 8) & 0xff,
7081	getCacheAss((uECX >> 16) & 0xff, sz1),
7082	(uECX >> 24) & 0xff);
7083	}
7084
7085	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
7086	{
7087	uint32_t uEAX = pCurLeaf->uEax;
7088	uint32_t uEBX = pCurLeaf->uEbx;
7089	uint32_t uEDX = pCurLeaf->uEdx;
7090
7091	pHlp->pfnPrintf(pHlp,
7092	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
7093	"L2 TLB 2/4M Data: %s %4d entries\n",
7094	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
7095	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
7096	pHlp->pfnPrintf(pHlp,
7097	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
7098	"L2 TLB 4K Data: %s %4d entries\n",
7099	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
7100	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
7101	pHlp->pfnPrintf(pHlp,
7102	"L2 Cache Line Size: %d bytes\n"
7103	"L2 Cache Lines Per Tag: %d\n"
7104	"L2 Cache Associativity: %s\n"
7105	"L2 Cache Size: %d KB\n",
7106	(uEDX >> 0) & 0xff,
7107	(uEDX >> 8) & 0xf,
7108	getL2CacheAss((uEDX >> 12) & 0xf),
7109	(uEDX >> 16) & 0xffff);
7110	}
7111
7112	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
7113	{
7114	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7115	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
7116	{
7117	if (iVerbosity < 1)
7118	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7119	else
7120	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7121	}
7122	}
7123
7124	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7125	if (pCurLeaf != NULL)
7126	{
7127	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7128	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7129	{
7130	if (iVerbosity < 1)
7131	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7132	else
7133	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7134	}
7135
7136	if (iVerbosity)
7137	{
7138	uint32_t uEAX = pCurLeaf->uEax;
7139	uint32_t uECX = pCurLeaf->uEcx;
7140
7141	/** @todo 0x80000008:EAX[23:16] is only defined for AMD. We'll get 0 on Intel. On
7142	* AMD if we get 0, the guest physical address width should be taken from
7143	* 0x80000008:EAX[7:0] instead. Guest Physical address width is relevant
7144	* for guests using nested paging. */
7145	pHlp->pfnPrintf(pHlp,
7146	"Physical Address Width: %d bits\n"
7147	"Virtual Address Width: %d bits\n"
7148	"Guest Physical Address Width: %d bits\n",
7149	(uEAX >> 0) & 0xff,
7150	(uEAX >> 8) & 0xff,
7151	(uEAX >> 16) & 0xff);
7152
7153	/** @todo 0x80000008:ECX is reserved on Intel (we'll get incorrect physical core
7154	* count here). */
7155	pHlp->pfnPrintf(pHlp,
7156	"Physical Core Count: %d\n",
7157	((uECX >> 0) & 0xff) + 1);
7158	}
7159	}
7160
7161	pCurLeaf = pNextLeaf;
7162	}
7163
7164
7165
7166	/*
7167	* Centaur.
7168	*/
7169	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7170
7171	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7172	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7173	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7174	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7175	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7176	cMax = RT_MAX(cHstMax, cGstMax);
7177	if (cMax >= UINT32_C(0xc0000000))
7178	{
7179	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7180
7181	/*
7182	* Understandable output
7183	*/
7184	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7185	pHlp->pfnPrintf(pHlp,
7186	"Centaur Supports: 0xc0000000-%#010x\n",
7187	pCurLeaf->uEax);
7188
7189	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7190	{
7191	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7192	uint32_t uEdxGst = pCurLeaf->uEdx;
7193	uint32_t uEdxHst = Host.uEdx;
7194
7195	if (iVerbosity == 1)
7196	{
7197	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7198	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7199	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7200	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7201	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7202	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7203	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7204	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7205	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7206	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7207	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7208	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7209	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7210	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7211	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7212	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7213	for (unsigned iBit = 14; iBit < 32; iBit++)
7214	if (uEdxGst & RT_BIT(iBit))
7215	pHlp->pfnPrintf(pHlp, " %d", iBit);
7216	pHlp->pfnPrintf(pHlp, "\n");
7217	}
7218	else
7219	{
7220	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7221	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7222	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7223	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7224	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7225	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7226	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7227	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7228	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7229	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7230	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7231	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7232	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7233	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7234	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7235	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7236	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7237	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7238	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7239	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7240	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7241	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7242	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7243	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7244	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7245	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7246	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7247	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7248	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7249	for (unsigned iBit = 27; iBit < 32; iBit++)
7250	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7251	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7252	pHlp->pfnPrintf(pHlp, "\n");
7253	}
7254	}
7255
7256	pCurLeaf = pNextLeaf;
7257	}
7258
7259	/*
7260	* The remainder.
7261	*/
7262	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7263	}
7264
7265	#endif /* !IN_VBOX_CPU_REPORT */
7266

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 91535

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