VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 92192

Last change on this file since 92192 was 91710, checked in by vboxsync, 3 years ago

VMM/CPUM: Nested VMX: bugref:10092 Added some VMX CPUMFEATURES' bit. Cleaned up cpumR3AreVmxCpuFeaturesCompatible to avoid some duplication.

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 341.3 KB
Line 
1/* $Id: CPUMR3CpuId.cpp 91710 2021-10-13 11:05:26Z vboxsync $ */
2/** @file
3 * CPUM - CPU ID part.
4 */
5
6/*
7 * Copyright (C) 2013-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/dbgf.h>
25#include <VBox/vmm/hm.h>
26#include <VBox/vmm/nem.h>
27#include <VBox/vmm/ssm.h>
28#include "CPUMInternal.h"
29#include <VBox/vmm/vmcc.h>
30#include <VBox/sup.h>
31
32#include <VBox/err.h>
33#include <iprt/asm-amd64-x86.h>
34#include <iprt/ctype.h>
35#include <iprt/mem.h>
36#include <iprt/string.h>
37
38
39/*********************************************************************************************************************************
40* Defined Constants And Macros *
41*********************************************************************************************************************************/
42/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
43#define CPUM_CPUID_MAX_LEAVES 2048
44/** Max size we accept for the XSAVE area.
45 * @see CPUMCTX::abXSave */
46#define CPUM_MAX_XSAVE_AREA_SIZE (0x4000 - 0x300)
47/* Min size we accept for the XSAVE area. */
48#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
49
50
51/*********************************************************************************************************************************
52* Global Variables *
53*********************************************************************************************************************************/
54/**
55 * The intel pentium family.
56 */
57static const CPUMMICROARCH g_aenmIntelFamily06[] =
58{
59 /* [ 0(0x00)] = */ kCpumMicroarch_Intel_P6, /* Pentium Pro A-step (says sandpile.org). */
60 /* [ 1(0x01)] = */ kCpumMicroarch_Intel_P6, /* Pentium Pro */
61 /* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
62 /* [ 3(0x03)] = */ kCpumMicroarch_Intel_P6_II, /* PII Klamath */
63 /* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
64 /* [ 5(0x05)] = */ kCpumMicroarch_Intel_P6_II, /* PII Deschutes */
65 /* [ 6(0x06)] = */ kCpumMicroarch_Intel_P6_II, /* Celeron Mendocino. */
66 /* [ 7(0x07)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Katmai. */
67 /* [ 8(0x08)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Coppermine (includes Celeron). */
68 /* [ 9(0x09)] = */ kCpumMicroarch_Intel_P6_M_Banias, /* Pentium/Celeron M Banias. */
69 /* [10(0x0a)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Xeon */
70 /* [11(0x0b)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Tualatin (includes Celeron). */
71 /* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
72 /* [13(0x0d)] = */ kCpumMicroarch_Intel_P6_M_Dothan, /* Pentium/Celeron M Dothan. */
73 /* [14(0x0e)] = */ kCpumMicroarch_Intel_Core_Yonah, /* Core Yonah (Enhanced Pentium M). */
74 /* [15(0x0f)] = */ kCpumMicroarch_Intel_Core2_Merom, /* Merom */
75 /* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
76 /* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
77 /* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
78 /* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
79 /* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
80 /* [21(0x15)] = */ kCpumMicroarch_Intel_P6_M_Dothan, /* Tolapai - System-on-a-chip. */
81 /* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
82 /* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
83 /* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
84 /* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
85 /* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Nehalem-EP */
86 /* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
87 /* [28(0x1c)] = */ kCpumMicroarch_Intel_Atom_Bonnell, /* Diamonville, Pineview, */
88 /* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
89 /* [30(0x1e)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Clarksfield, Lynnfield, Jasper Forest. */
90 /* [31(0x1f)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
91 /* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
92 /* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
93 /* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
94 /* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
95 /* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
96 /* [37(0x25)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Arrandale, Clarksdale. */
97 /* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
98 /* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
99 /* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
100 /* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
101 /* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
102 /* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
103 /* [44(0x2c)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Gulftown, Westmere-EP. */
104 /* [45(0x2d)] = */ kCpumMicroarch_Intel_Core7_SandyBridge, /* SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
105 /* [46(0x2e)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Beckton (Xeon). */
106 /* [47(0x2f)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Westmere-EX. */
107 /* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
108 /* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
109 /* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
110 /* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
111 /* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
112 /* [53(0x35)] = */ kCpumMicroarch_Intel_Atom_Saltwell, /* ?? */
113 /* [54(0x36)] = */ kCpumMicroarch_Intel_Atom_Saltwell, /* Cedarview, ++ */
114 /* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
115 /* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
116 /* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
117 /* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
118 /* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
119 /* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120 /* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
121 /* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
122 /* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123 /* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
124 /* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
125 /* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
126 /* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
127 /* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
128 /* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129 /* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
130 /* [71(0x47)] = */ kCpumMicroarch_Intel_Core7_Broadwell, /* i7-5775C */
131 /* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
132 /* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
133 /* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134 /* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
135 /* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
136 /* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137 /* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,
138 /* [79(0x4f)] = */ kCpumMicroarch_Intel_Core7_Broadwell, /* Broadwell-E */
139 /* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
140 /* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
141 /* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
142 /* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
143 /* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
144 /* [85(0x55)] = */ kCpumMicroarch_Intel_Core7_Skylake, /* server cpu; skylake <= 4, cascade lake > 5 */
145 /* [86(0x56)] = */ kCpumMicroarch_Intel_Core7_Broadwell, /* Xeon D-1540, Broadwell-DE */
146 /* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
147 /* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
148 /* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
149 /* [90(0x5a)] = */ kCpumMicroarch_Intel_Atom_Silvermont, /* Moorefield */
150 /* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
151 /* [92(0x5c)] = */ kCpumMicroarch_Intel_Atom_Goldmont, /* Apollo Lake */
152 /* [93(0x5d)] = */ kCpumMicroarch_Intel_Atom_Silvermont, /* x3-C3230 */
153 /* [94(0x5e)] = */ kCpumMicroarch_Intel_Core7_Skylake, /* i7-6700K */
154 /* [95(0x5f)] = */ kCpumMicroarch_Intel_Atom_Goldmont, /* Denverton */
155 /* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
156 /* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
157 /* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
158 /* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
159 /*[100(0x64)] = */ kCpumMicroarch_Intel_Unknown,
160 /*[101(0x65)] = */ kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
161 /*[102(0x66)] = */ kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
162 /*[103(0x67)] = */ kCpumMicroarch_Intel_Unknown,
163 /*[104(0x68)] = */ kCpumMicroarch_Intel_Unknown,
164 /*[105(0x69)] = */ kCpumMicroarch_Intel_Unknown,
165 /*[106(0x6a)] = */ kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
166 /*[107(0x6b)] = */ kCpumMicroarch_Intel_Unknown,
167 /*[108(0x6c)] = */ kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed server */
168 /*[109(0x6d)] = */ kCpumMicroarch_Intel_Unknown,
169 /*[110(0x6e)] = */ kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
170 /*[111(0x6f)] = */ kCpumMicroarch_Intel_Unknown,
171 /*[112(0x70)] = */ kCpumMicroarch_Intel_Unknown,
172 /*[113(0x71)] = */ kCpumMicroarch_Intel_Unknown,
173 /*[114(0x72)] = */ kCpumMicroarch_Intel_Unknown,
174 /*[115(0x73)] = */ kCpumMicroarch_Intel_Unknown,
175 /*[116(0x74)] = */ kCpumMicroarch_Intel_Unknown,
176 /*[117(0x75)] = */ kCpumMicroarch_Intel_Atom_Airmount, /* or silvermount? */
177 /*[118(0x76)] = */ kCpumMicroarch_Intel_Unknown,
178 /*[119(0x77)] = */ kCpumMicroarch_Intel_Unknown,
179 /*[120(0x78)] = */ kCpumMicroarch_Intel_Unknown,
180 /*[121(0x79)] = */ kCpumMicroarch_Intel_Unknown,
181 /*[122(0x7a)] = */ kCpumMicroarch_Intel_Atom_GoldmontPlus,
182 /*[123(0x7b)] = */ kCpumMicroarch_Intel_Unknown,
183 /*[124(0x7c)] = */ kCpumMicroarch_Intel_Unknown,
184 /*[125(0x7d)] = */ kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
185 /*[126(0x7e)] = */ kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
186 /*[127(0x7f)] = */ kCpumMicroarch_Intel_Unknown,
187 /*[128(0x80)] = */ kCpumMicroarch_Intel_Unknown,
188 /*[129(0x81)] = */ kCpumMicroarch_Intel_Unknown,
189 /*[130(0x82)] = */ kCpumMicroarch_Intel_Unknown,
190 /*[131(0x83)] = */ kCpumMicroarch_Intel_Unknown,
191 /*[132(0x84)] = */ kCpumMicroarch_Intel_Unknown,
192 /*[133(0x85)] = */ kCpumMicroarch_Intel_Phi_KnightsMill,
193 /*[134(0x86)] = */ kCpumMicroarch_Intel_Unknown,
194 /*[135(0x87)] = */ kCpumMicroarch_Intel_Unknown,
195 /*[136(0x88)] = */ kCpumMicroarch_Intel_Unknown,
196 /*[137(0x89)] = */ kCpumMicroarch_Intel_Unknown,
197 /*[138(0x8a)] = */ kCpumMicroarch_Intel_Unknown,
198 /*[139(0x8b)] = */ kCpumMicroarch_Intel_Unknown,
199 /*[140(0x8c)] = */ kCpumMicroarch_Intel_Core7_TigerLake, /* 11th Gen Intel(R) Core(TM) i7-1185G7 @ 3.00GHz (bird) */
200 /*[141(0x8d)] = */ kCpumMicroarch_Intel_Core7_TigerLake, /* unconfirmed */
201 /*[142(0x8e)] = */ kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
202 /*[143(0x8f)] = */ kCpumMicroarch_Intel_Core7_SapphireRapids,
203 /*[144(0x90)] = */ kCpumMicroarch_Intel_Unknown,
204 /*[145(0x91)] = */ kCpumMicroarch_Intel_Unknown,
205 /*[146(0x92)] = */ kCpumMicroarch_Intel_Unknown,
206 /*[147(0x93)] = */ kCpumMicroarch_Intel_Unknown,
207 /*[148(0x94)] = */ kCpumMicroarch_Intel_Unknown,
208 /*[149(0x95)] = */ kCpumMicroarch_Intel_Unknown,
209 /*[150(0x96)] = */ kCpumMicroarch_Intel_Unknown,
210 /*[151(0x97)] = */ kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
211 /*[152(0x98)] = */ kCpumMicroarch_Intel_Unknown,
212 /*[153(0x99)] = */ kCpumMicroarch_Intel_Unknown,
213 /*[154(0x9a)] = */ kCpumMicroarch_Intel_Core7_AlderLake, /* unconfirmed, unreleased */
214 /*[155(0x9b)] = */ kCpumMicroarch_Intel_Unknown,
215 /*[156(0x9c)] = */ kCpumMicroarch_Intel_Unknown,
216 /*[157(0x9d)] = */ kCpumMicroarch_Intel_Unknown,
217 /*[158(0x9e)] = */ kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
218 /*[159(0x9f)] = */ kCpumMicroarch_Intel_Unknown,
219 /*[160(0xa0)] = */ kCpumMicroarch_Intel_Unknown,
220 /*[161(0xa1)] = */ kCpumMicroarch_Intel_Unknown,
221 /*[162(0xa2)] = */ kCpumMicroarch_Intel_Unknown,
222 /*[163(0xa3)] = */ kCpumMicroarch_Intel_Unknown,
223 /*[164(0xa4)] = */ kCpumMicroarch_Intel_Unknown,
224 /*[165(0xa5)] = */ kCpumMicroarch_Intel_Core7_CometLake, /* unconfirmed */
225 /*[166(0xa6)] = */ kCpumMicroarch_Intel_Unknown,
226 /*[167(0xa7)] = */ kCpumMicroarch_Intel_Core7_CypressCove, /* 14nm backport, unconfirmed */
227};
228AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0xa7+1);
229
230
231/**
232 * Figures out the (sub-)micro architecture given a bit of CPUID info.
233 *
234 * @returns Micro architecture.
235 * @param enmVendor The CPU vendor.
236 * @param bFamily The CPU family.
237 * @param bModel The CPU model.
238 * @param bStepping The CPU stepping.
239 */
240VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
241 uint8_t bModel, uint8_t bStepping)
242{
243 if (enmVendor == CPUMCPUVENDOR_AMD)
244 {
245 switch (bFamily)
246 {
247 case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
248 case 0x03: return kCpumMicroarch_AMD_Am386;
249 case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
250 case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
251 case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
252 case 0x06:
253 switch (bModel)
254 {
255 case 0: return kCpumMicroarch_AMD_K7_Palomino;
256 case 1: return kCpumMicroarch_AMD_K7_Palomino;
257 case 2: return kCpumMicroarch_AMD_K7_Palomino;
258 case 3: return kCpumMicroarch_AMD_K7_Spitfire;
259 case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
260 case 6: return kCpumMicroarch_AMD_K7_Palomino;
261 case 7: return kCpumMicroarch_AMD_K7_Morgan;
262 case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
263 case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
264 }
265 return kCpumMicroarch_AMD_K7_Unknown;
266 case 0x0f:
267 /*
268 * This family is a friggin mess. Trying my best to make some
269 * sense out of it. Too much happened in the 0x0f family to
270 * lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
271 *
272 * Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
273 * cpu-world.com, and other places:
274 * - 130nm:
275 * - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
276 * - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
277 * - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
278 * - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
279 * - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
280 * - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
281 * - 90nm:
282 * - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
283 * - Oakville: 10FC0/DH-D0.
284 * - Georgetown: 10FC0/DH-D0.
285 * - Sonora: 10FC0/DH-D0.
286 * - Venus: 20F71/SH-E4
287 * - Troy: 20F51/SH-E4
288 * - Athens: 20F51/SH-E4
289 * - San Diego: 20F71/SH-E4.
290 * - Lancaster: 20F42/SH-E5
291 * - Newark: 20F42/SH-E5.
292 * - Albany: 20FC2/DH-E6.
293 * - Roma: 20FC2/DH-E6.
294 * - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
295 * - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
296 * - 90nm introducing Dual core:
297 * - Denmark: 20F30/JH-E1, 20F32/JH-E6
298 * - Italy: 20F10/JH-E1, 20F12/JH-E6
299 * - Egypt: 20F10/JH-E1, 20F12/JH-E6
300 * - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
301 * - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
302 * - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
303 * - Santa Ana: 40F32/JH-F2, /-F3
304 * - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
305 * - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
306 * - Manila: 50FF2/DH-F2, 40FF2/DH-F2
307 * - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
308 * - Keene: 40FC2/DH-F2.
309 * - Richmond: 40FC2/DH-F2
310 * - Taylor: 40F82/BH-F2
311 * - Trinidad: 40F82/BH-F2
312 *
313 * - 65nm:
314 * - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
315 * - Tyler: 60F81/BH-G1, 60F82/BH-G2.
316 * - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
317 * - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
318 * - Sherman: /-G1, 70FC2/DH-G2.
319 * - Huron: 70FF2/DH-G2.
320 */
321 if (bModel < 0x10)
322 return kCpumMicroarch_AMD_K8_130nm;
323 if (bModel >= 0x60 && bModel < 0x80)
324 return kCpumMicroarch_AMD_K8_65nm;
325 if (bModel >= 0x40)
326 return kCpumMicroarch_AMD_K8_90nm_AMDV;
327 switch (bModel)
328 {
329 case 0x21:
330 case 0x23:
331 case 0x2b:
332 case 0x2f:
333 case 0x37:
334 case 0x3f:
335 return kCpumMicroarch_AMD_K8_90nm_DualCore;
336 }
337 return kCpumMicroarch_AMD_K8_90nm;
338 case 0x10:
339 return kCpumMicroarch_AMD_K10;
340 case 0x11:
341 return kCpumMicroarch_AMD_K10_Lion;
342 case 0x12:
343 return kCpumMicroarch_AMD_K10_Llano;
344 case 0x14:
345 return kCpumMicroarch_AMD_Bobcat;
346 case 0x15:
347 switch (bModel)
348 {
349 case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
350 case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
351 case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
352 case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
353 case 0x11: /* ?? */
354 case 0x12: /* ?? */
355 case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
356 }
357 return kCpumMicroarch_AMD_15h_Unknown;
358 case 0x16:
359 return kCpumMicroarch_AMD_Jaguar;
360 case 0x17:
361 return kCpumMicroarch_AMD_Zen_Ryzen;
362 }
363 return kCpumMicroarch_AMD_Unknown;
364 }
365
366 if (enmVendor == CPUMCPUVENDOR_INTEL)
367 {
368 switch (bFamily)
369 {
370 case 3:
371 return kCpumMicroarch_Intel_80386;
372 case 4:
373 return kCpumMicroarch_Intel_80486;
374 case 5:
375 return kCpumMicroarch_Intel_P5;
376 case 6:
377 if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
378 {
379 CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
380 if (enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake)
381 {
382 if (bStepping >= 0xa && bStepping <= 0xc)
383 enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
384 else if (bStepping >= 0xc)
385 enmMicroArch = kCpumMicroarch_Intel_Core7_WhiskeyLake;
386 }
387 else if ( enmMicroArch == kCpumMicroarch_Intel_Core7_Skylake
388 && bModel == 0x55
389 && bStepping >= 5)
390 enmMicroArch = kCpumMicroarch_Intel_Core7_CascadeLake;
391 return enmMicroArch;
392 }
393 return kCpumMicroarch_Intel_Atom_Unknown;
394 case 15:
395 switch (bModel)
396 {
397 case 0: return kCpumMicroarch_Intel_NB_Willamette;
398 case 1: return kCpumMicroarch_Intel_NB_Willamette;
399 case 2: return kCpumMicroarch_Intel_NB_Northwood;
400 case 3: return kCpumMicroarch_Intel_NB_Prescott;
401 case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
402 case 5: return kCpumMicroarch_Intel_NB_Unknown; /*??*/
403 case 6: return kCpumMicroarch_Intel_NB_CedarMill;
404 case 7: return kCpumMicroarch_Intel_NB_Gallatin;
405 default: return kCpumMicroarch_Intel_NB_Unknown;
406 }
407 break;
408 /* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
409 case 0:
410 return kCpumMicroarch_Intel_8086;
411 case 1:
412 return kCpumMicroarch_Intel_80186;
413 case 2:
414 return kCpumMicroarch_Intel_80286;
415 }
416 return kCpumMicroarch_Intel_Unknown;
417 }
418
419 if (enmVendor == CPUMCPUVENDOR_VIA)
420 {
421 switch (bFamily)
422 {
423 case 5:
424 switch (bModel)
425 {
426 case 1: return kCpumMicroarch_Centaur_C6;
427 case 4: return kCpumMicroarch_Centaur_C6;
428 case 8: return kCpumMicroarch_Centaur_C2;
429 case 9: return kCpumMicroarch_Centaur_C3;
430 }
431 break;
432
433 case 6:
434 switch (bModel)
435 {
436 case 5: return kCpumMicroarch_VIA_C3_M2;
437 case 6: return kCpumMicroarch_VIA_C3_C5A;
438 case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
439 case 8: return kCpumMicroarch_VIA_C3_C5N;
440 case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
441 case 10: return kCpumMicroarch_VIA_C7_C5J;
442 case 15: return kCpumMicroarch_VIA_Isaiah;
443 }
444 break;
445 }
446 return kCpumMicroarch_VIA_Unknown;
447 }
448
449 if (enmVendor == CPUMCPUVENDOR_SHANGHAI)
450 {
451 switch (bFamily)
452 {
453 case 6:
454 case 7:
455 return kCpumMicroarch_Shanghai_Wudaokou;
456 default:
457 break;
458 }
459 return kCpumMicroarch_Shanghai_Unknown;
460 }
461
462 if (enmVendor == CPUMCPUVENDOR_CYRIX)
463 {
464 switch (bFamily)
465 {
466 case 4:
467 switch (bModel)
468 {
469 case 9: return kCpumMicroarch_Cyrix_5x86;
470 }
471 break;
472
473 case 5:
474 switch (bModel)
475 {
476 case 2: return kCpumMicroarch_Cyrix_M1;
477 case 4: return kCpumMicroarch_Cyrix_MediaGX;
478 case 5: return kCpumMicroarch_Cyrix_MediaGXm;
479 }
480 break;
481
482 case 6:
483 switch (bModel)
484 {
485 case 0: return kCpumMicroarch_Cyrix_M2;
486 }
487 break;
488
489 }
490 return kCpumMicroarch_Cyrix_Unknown;
491 }
492
493 if (enmVendor == CPUMCPUVENDOR_HYGON)
494 {
495 switch (bFamily)
496 {
497 case 0x18:
498 return kCpumMicroarch_Hygon_Dhyana;
499 default:
500 break;
501 }
502 return kCpumMicroarch_Hygon_Unknown;
503 }
504
505 return kCpumMicroarch_Unknown;
506}
507
508
509/**
510 * Translates a microarchitecture enum value to the corresponding string
511 * constant.
512 *
513 * @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
514 * NULL if the value is invalid.
515 *
516 * @param enmMicroarch The enum value to convert.
517 */
518VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
519{
520 switch (enmMicroarch)
521 {
522#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
523 CASE_RET_STR(kCpumMicroarch_Intel_8086);
524 CASE_RET_STR(kCpumMicroarch_Intel_80186);
525 CASE_RET_STR(kCpumMicroarch_Intel_80286);
526 CASE_RET_STR(kCpumMicroarch_Intel_80386);
527 CASE_RET_STR(kCpumMicroarch_Intel_80486);
528 CASE_RET_STR(kCpumMicroarch_Intel_P5);
529
530 CASE_RET_STR(kCpumMicroarch_Intel_P6);
531 CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
532 CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
533
534 CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
535 CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
536 CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
537
538 CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
539 CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
540
541 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
542 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
543 CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
544 CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
545 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
546 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
547 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
548 CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
549 CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
550 CASE_RET_STR(kCpumMicroarch_Intel_Core7_WhiskeyLake);
551 CASE_RET_STR(kCpumMicroarch_Intel_Core7_CascadeLake);
552 CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
553 CASE_RET_STR(kCpumMicroarch_Intel_Core7_CometLake);
554 CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
555 CASE_RET_STR(kCpumMicroarch_Intel_Core7_RocketLake);
556 CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
557 CASE_RET_STR(kCpumMicroarch_Intel_Core7_AlderLake);
558 CASE_RET_STR(kCpumMicroarch_Intel_Core7_SapphireRapids);
559
560 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
561 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
562 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
563 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
564 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
565 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
566 CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
567 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
568
569 CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
570 CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
571 CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
572 CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
573 CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
574
575 CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
576 CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
577 CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
578 CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
579 CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
580 CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
581 CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
582
583 CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
584
585 CASE_RET_STR(kCpumMicroarch_AMD_Am286);
586 CASE_RET_STR(kCpumMicroarch_AMD_Am386);
587 CASE_RET_STR(kCpumMicroarch_AMD_Am486);
588 CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
589 CASE_RET_STR(kCpumMicroarch_AMD_K5);
590 CASE_RET_STR(kCpumMicroarch_AMD_K6);
591
592 CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
593 CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
594 CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
595 CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
596 CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
597 CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
598 CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
599
600 CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
601 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
602 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
603 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
604 CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
605
606 CASE_RET_STR(kCpumMicroarch_AMD_K10);
607 CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
608 CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
609 CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
610 CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
611
612 CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
613 CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
614 CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
615 CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
616 CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
617
618 CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
619
620 CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
621
622 CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
623
624 CASE_RET_STR(kCpumMicroarch_Hygon_Dhyana);
625 CASE_RET_STR(kCpumMicroarch_Hygon_Unknown);
626
627 CASE_RET_STR(kCpumMicroarch_Centaur_C6);
628 CASE_RET_STR(kCpumMicroarch_Centaur_C2);
629 CASE_RET_STR(kCpumMicroarch_Centaur_C3);
630 CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
631 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
632 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
633 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
634 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
635 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
636 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
637 CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
638 CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
639 CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
640
641 CASE_RET_STR(kCpumMicroarch_Shanghai_Wudaokou);
642 CASE_RET_STR(kCpumMicroarch_Shanghai_Unknown);
643
644 CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
645 CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
646 CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
647 CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
648 CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
649 CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
650
651 CASE_RET_STR(kCpumMicroarch_NEC_V20);
652 CASE_RET_STR(kCpumMicroarch_NEC_V30);
653
654 CASE_RET_STR(kCpumMicroarch_Unknown);
655
656#undef CASE_RET_STR
657 case kCpumMicroarch_Invalid:
658 case kCpumMicroarch_Intel_End:
659 case kCpumMicroarch_Intel_Core2_End:
660 case kCpumMicroarch_Intel_Core7_End:
661 case kCpumMicroarch_Intel_Atom_End:
662 case kCpumMicroarch_Intel_P6_Core_Atom_End:
663 case kCpumMicroarch_Intel_Phi_End:
664 case kCpumMicroarch_Intel_NB_End:
665 case kCpumMicroarch_AMD_K7_End:
666 case kCpumMicroarch_AMD_K8_End:
667 case kCpumMicroarch_AMD_15h_End:
668 case kCpumMicroarch_AMD_16h_End:
669 case kCpumMicroarch_AMD_Zen_End:
670 case kCpumMicroarch_AMD_End:
671 case kCpumMicroarch_Hygon_End:
672 case kCpumMicroarch_VIA_End:
673 case kCpumMicroarch_Shanghai_End:
674 case kCpumMicroarch_Cyrix_End:
675 case kCpumMicroarch_NEC_End:
676 case kCpumMicroarch_32BitHack:
677 break;
678 /* no default! */
679 }
680
681 return NULL;
682}
683
684
685/**
686 * Determins the host CPU MXCSR mask.
687 *
688 * @returns MXCSR mask.
689 */
690VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
691{
692 if ( ASMHasCpuId()
693 && ASMIsValidStdRange(ASMCpuId_EAX(0))
694 && ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
695 {
696 uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
697 PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
698 RT_ZERO(*pState);
699 ASMFxSave(pState);
700 if (pState->MXCSR_MASK == 0)
701 return 0xffbf;
702 return pState->MXCSR_MASK;
703 }
704 return 0;
705}
706
707
708/**
709 * Gets a matching leaf in the CPUID leaf array.
710 *
711 * @returns Pointer to the matching leaf, or NULL if not found.
712 * @param paLeaves The CPUID leaves to search. This is sorted.
713 * @param cLeaves The number of leaves in the array.
714 * @param uLeaf The leaf to locate.
715 * @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
716 */
717static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
718{
719 /* Lazy bird does linear lookup here since this is only used for the
720 occational CPUID overrides. */
721 for (uint32_t i = 0; i < cLeaves; i++)
722 if ( paLeaves[i].uLeaf == uLeaf
723 && paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
724 return &paLeaves[i];
725 return NULL;
726}
727
728
729#ifndef IN_VBOX_CPU_REPORT
730/**
731 * Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
732 *
733 * @returns true if found, false it not.
734 * @param paLeaves The CPUID leaves to search. This is sorted.
735 * @param cLeaves The number of leaves in the array.
736 * @param uLeaf The leaf to locate.
737 * @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
738 * @param pLegacy The legacy output leaf.
739 */
740static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
741 PCPUMCPUID pLegacy)
742{
743 PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
744 if (pLeaf)
745 {
746 pLegacy->uEax = pLeaf->uEax;
747 pLegacy->uEbx = pLeaf->uEbx;
748 pLegacy->uEcx = pLeaf->uEcx;
749 pLegacy->uEdx = pLeaf->uEdx;
750 return true;
751 }
752 return false;
753}
754#endif /* IN_VBOX_CPU_REPORT */
755
756
757/**
758 * Ensures that the CPUID leaf array can hold one more leaf.
759 *
760 * @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
761 * failure.
762 * @param pVM The cross context VM structure. If NULL, use
763 * the process heap, otherwise the VM's hyper heap.
764 * @param ppaLeaves Pointer to the variable holding the array pointer
765 * (input/output).
766 * @param cLeaves The current array size.
767 *
768 * @remarks This function will automatically update the R0 and RC pointers when
769 * using the hyper heap, which means @a ppaLeaves and @a cLeaves must
770 * be the corresponding VM's CPUID arrays (which is asserted).
771 */
772static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
773{
774 /*
775 * If pVM is not specified, we're on the regular heap and can waste a
776 * little space to speed things up.
777 */
778 uint32_t cAllocated;
779 if (!pVM)
780 {
781 cAllocated = RT_ALIGN(cLeaves, 16);
782 if (cLeaves + 1 > cAllocated)
783 {
784 void *pvNew = RTMemRealloc(*ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
785 if (pvNew)
786 *ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
787 else
788 {
789 RTMemFree(*ppaLeaves);
790 *ppaLeaves = NULL;
791 }
792 }
793 }
794 /*
795 * Otherwise, we're on the hyper heap and are probably just inserting
796 * one or two leaves and should conserve space.
797 */
798 else
799 {
800#ifdef IN_VBOX_CPU_REPORT
801 AssertReleaseFailed();
802#else
803 Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
804 Assert(*ppaLeaves == pVM->cpum.s.GuestInfo.aCpuIdLeaves);
805 Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
806
807 if (cLeaves + 1 <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves))
808 { }
809 else
810 {
811 *ppaLeaves = NULL;
812 LogRel(("CPUM: cpumR3CpuIdEnsureSpace: Out of CPUID space!\n"));
813 }
814#endif
815 }
816 return *ppaLeaves;
817}
818
819
820/**
821 * Append a CPUID leaf or sub-leaf.
822 *
823 * ASSUMES linear insertion order, so we'll won't need to do any searching or
824 * replace anything. Use cpumR3CpuIdInsert() for those cases.
825 *
826 * @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
827 * the caller need do no more work.
828 * @param ppaLeaves Pointer to the pointer to the array of sorted
829 * CPUID leaves and sub-leaves.
830 * @param pcLeaves Where we keep the leaf count for *ppaLeaves.
831 * @param uLeaf The leaf we're adding.
832 * @param uSubLeaf The sub-leaf number.
833 * @param fSubLeafMask The sub-leaf mask.
834 * @param uEax The EAX value.
835 * @param uEbx The EBX value.
836 * @param uEcx The ECX value.
837 * @param uEdx The EDX value.
838 * @param fFlags The flags.
839 */
840static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves,
841 uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
842 uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
843{
844 if (!cpumR3CpuIdEnsureSpace(NULL /* pVM */, ppaLeaves, *pcLeaves))
845 return VERR_NO_MEMORY;
846
847 PCPUMCPUIDLEAF pNew = &(*ppaLeaves)[*pcLeaves];
848 Assert( *pcLeaves == 0
849 || pNew[-1].uLeaf < uLeaf
850 || (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
851
852 pNew->uLeaf = uLeaf;
853 pNew->uSubLeaf = uSubLeaf;
854 pNew->fSubLeafMask = fSubLeafMask;
855 pNew->uEax = uEax;
856 pNew->uEbx = uEbx;
857 pNew->uEcx = uEcx;
858 pNew->uEdx = uEdx;
859 pNew->fFlags = fFlags;
860
861 *pcLeaves += 1;
862 return VINF_SUCCESS;
863}
864
865
866/**
867 * Checks that we've updated the CPUID leaves array correctly.
868 *
869 * This is a no-op in non-strict builds.
870 *
871 * @param paLeaves The leaves array.
872 * @param cLeaves The number of leaves.
873 */
874static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
875{
876#ifdef VBOX_STRICT
877 for (uint32_t i = 1; i < cLeaves; i++)
878 if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
879 AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
880 else
881 {
882 AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
883 ("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
884 AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
885 ("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
886 AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
887 ("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
888 }
889#else
890 NOREF(paLeaves);
891 NOREF(cLeaves);
892#endif
893}
894
895
896/**
897 * Inserts a CPU ID leaf, replacing any existing ones.
898 *
899 * When inserting a simple leaf where we already got a series of sub-leaves with
900 * the same leaf number (eax), the simple leaf will replace the whole series.
901 *
902 * When pVM is NULL, this ASSUMES that the leaves array is still on the normal
903 * host-context heap and has only been allocated/reallocated by the
904 * cpumR3CpuIdEnsureSpace function.
905 *
906 * @returns VBox status code.
907 * @param pVM The cross context VM structure. If NULL, use
908 * the process heap, otherwise the VM's hyper heap.
909 * @param ppaLeaves Pointer to the pointer to the array of sorted
910 * CPUID leaves and sub-leaves. Must be NULL if using
911 * the hyper heap.
912 * @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
913 * be NULL if using the hyper heap.
914 * @param pNewLeaf Pointer to the data of the new leaf we're about to
915 * insert.
916 */
917static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
918{
919 /*
920 * Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
921 */
922 if (pVM)
923 {
924 AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
925 AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
926 AssertReturn(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 == pVM->cpum.s.GuestInfo.aCpuIdLeaves, VERR_INVALID_PARAMETER);
927
928 ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
929 pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
930 }
931
932 PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
933 uint32_t cLeaves = *pcLeaves;
934
935 /*
936 * Validate the new leaf a little.
937 */
938 AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
939 ("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
940 VERR_INVALID_FLAGS);
941 AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 || pNewLeaf->uSubLeaf == 0,
942 ("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
943 VERR_INVALID_PARAMETER);
944 AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
945 ("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
946 VERR_INVALID_PARAMETER);
947 AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
948 ("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
949 VERR_INVALID_PARAMETER);
950
951 /*
952 * Find insertion point. The lazy bird uses the same excuse as in
953 * cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
954 */
955 uint32_t i;
956 if ( cLeaves > 0
957 && paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
958 {
959 /* Add at end. */
960 i = cLeaves;
961 }
962 else if ( cLeaves > 0
963 && paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
964 {
965 /* Either replacing the last leaf or dealing with sub-leaves. Spool
966 back to the first sub-leaf to pretend we did the linear search. */
967 i = cLeaves - 1;
968 while ( i > 0
969 && paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
970 i--;
971 }
972 else
973 {
974 /* Linear search from the start. */
975 i = 0;
976 while ( i < cLeaves
977 && paLeaves[i].uLeaf < pNewLeaf->uLeaf)
978 i++;
979 }
980 if ( i < cLeaves
981 && paLeaves[i].uLeaf == pNewLeaf->uLeaf)
982 {
983 if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
984 {
985 /*
986 * The sub-leaf mask differs, replace all existing leaves with the
987 * same leaf number.
988 */
989 uint32_t c = 1;
990 while ( i + c < cLeaves
991 && paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
992 c++;
993 if (c > 1 && i + c < cLeaves)
994 {
995 memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
996 *pcLeaves = cLeaves -= c - 1;
997 }
998
999 paLeaves[i] = *pNewLeaf;
1000 cpumR3CpuIdAssertOrder(*ppaLeaves, *pcLeaves);
1001 return VINF_SUCCESS;
1002 }
1003
1004 /* Find sub-leaf insertion point. */
1005 while ( i < cLeaves
1006 && paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
1007 && paLeaves[i].uLeaf == pNewLeaf->uLeaf)
1008 i++;
1009
1010 /*
1011 * If we've got an exactly matching leaf, replace it.
1012 */
1013 if ( i < cLeaves
1014 && paLeaves[i].uLeaf == pNewLeaf->uLeaf
1015 && paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
1016 {
1017 paLeaves[i] = *pNewLeaf;
1018 cpumR3CpuIdAssertOrder(*ppaLeaves, *pcLeaves);
1019 return VINF_SUCCESS;
1020 }
1021 }
1022
1023 /*
1024 * Adding a new leaf at 'i'.
1025 */
1026 AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
1027 paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
1028 if (!paLeaves)
1029 return VERR_NO_MEMORY;
1030
1031 if (i < cLeaves)
1032 memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
1033 *pcLeaves += 1;
1034 paLeaves[i] = *pNewLeaf;
1035
1036 cpumR3CpuIdAssertOrder(*ppaLeaves, *pcLeaves);
1037 return VINF_SUCCESS;
1038}
1039
1040
1041#ifndef IN_VBOX_CPU_REPORT
1042/**
1043 * Removes a range of CPUID leaves.
1044 *
1045 * This will not reallocate the array.
1046 *
1047 * @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1048 * @param pcLeaves Where we keep the leaf count for @a paLeaves.
1049 * @param uFirst The first leaf.
1050 * @param uLast The last leaf.
1051 */
1052static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1053{
1054 uint32_t cLeaves = *pcLeaves;
1055
1056 Assert(uFirst <= uLast);
1057
1058 /*
1059 * Find the first one.
1060 */
1061 uint32_t iFirst = 0;
1062 while ( iFirst < cLeaves
1063 && paLeaves[iFirst].uLeaf < uFirst)
1064 iFirst++;
1065
1066 /*
1067 * Find the end (last + 1).
1068 */
1069 uint32_t iEnd = iFirst;
1070 while ( iEnd < cLeaves
1071 && paLeaves[iEnd].uLeaf <= uLast)
1072 iEnd++;
1073
1074 /*
1075 * Adjust the array if anything needs removing.
1076 */
1077 if (iFirst < iEnd)
1078 {
1079 if (iEnd < cLeaves)
1080 memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1081 *pcLeaves = cLeaves -= (iEnd - iFirst);
1082 }
1083
1084 cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1085}
1086#endif /* IN_VBOX_CPU_REPORT */
1087
1088
1089/**
1090 * Checks if ECX make a difference when reading a given CPUID leaf.
1091 *
1092 * @returns @c true if it does, @c false if it doesn't.
1093 * @param uLeaf The leaf we're reading.
1094 * @param pcSubLeaves Number of sub-leaves accessible via ECX.
1095 * @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1096 * final sub-leaf (for leaf 0xb only).
1097 */
1098static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t *pcSubLeaves, bool *pfFinalEcxUnchanged)
1099{
1100 *pfFinalEcxUnchanged = false;
1101
1102 uint32_t auCur[4];
1103 uint32_t auPrev[4];
1104 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1105
1106 /* Look for sub-leaves. */
1107 uint32_t uSubLeaf = 1;
1108 for (;;)
1109 {
1110 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1111 if (memcmp(auCur, auPrev, sizeof(auCur)))
1112 break;
1113
1114 /* Advance / give up. */
1115 uSubLeaf++;
1116 if (uSubLeaf >= 64)
1117 {
1118 *pcSubLeaves = 1;
1119 return false;
1120 }
1121 }
1122
1123 /* Count sub-leaves. */
1124 uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1125 uint32_t cRepeats = 0;
1126 uSubLeaf = 0;
1127 for (;;)
1128 {
1129 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1130
1131 /* Figuring out when to stop isn't entirely straight forward as we need
1132 to cover undocumented behavior up to a point and implementation shortcuts. */
1133
1134 /* 1. Look for more than 4 repeating value sets. */
1135 if ( auCur[0] == auPrev[0]
1136 && auCur[1] == auPrev[1]
1137 && ( auCur[2] == auPrev[2]
1138 || ( auCur[2] == uSubLeaf
1139 && auPrev[2] == uSubLeaf - 1) )
1140 && auCur[3] == auPrev[3])
1141 {
1142 if ( uLeaf != 0xd
1143 || uSubLeaf >= 64
1144 || ( auCur[0] == 0
1145 && auCur[1] == 0
1146 && auCur[2] == 0
1147 && auCur[3] == 0
1148 && auPrev[2] == 0) )
1149 cRepeats++;
1150 if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1151 break;
1152 }
1153 else
1154 cRepeats = 0;
1155
1156 /* 2. Look for zero values. */
1157 if ( auCur[0] == 0
1158 && auCur[1] == 0
1159 && (auCur[2] == 0 || auCur[2] == uSubLeaf)
1160 && (auCur[3] == 0 || uLeaf == 0xb /* edx is fixed */)
1161 && uSubLeaf >= cMinLeaves)
1162 {
1163 cRepeats = 0;
1164 break;
1165 }
1166
1167 /* 3. Leaf 0xb level type 0 check. */
1168 if ( uLeaf == 0xb
1169 && (auCur[2] & 0xff00) == 0
1170 && (auPrev[2] & 0xff00) == 0)
1171 {
1172 cRepeats = 0;
1173 break;
1174 }
1175
1176 /* 99. Give up. */
1177 if (uSubLeaf >= 128)
1178 {
1179#ifndef IN_VBOX_CPU_REPORT
1180 /* Ok, limit it according to the documentation if possible just to
1181 avoid annoying users with these detection issues. */
1182 uint32_t cDocLimit = UINT32_MAX;
1183 if (uLeaf == 0x4)
1184 cDocLimit = 4;
1185 else if (uLeaf == 0x7)
1186 cDocLimit = 1;
1187 else if (uLeaf == 0xd)
1188 cDocLimit = 63;
1189 else if (uLeaf == 0xf)
1190 cDocLimit = 2;
1191 if (cDocLimit != UINT32_MAX)
1192 {
1193 *pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1194 *pcSubLeaves = cDocLimit + 3;
1195 return true;
1196 }
1197#endif
1198 *pcSubLeaves = UINT32_MAX;
1199 return true;
1200 }
1201
1202 /* Advance. */
1203 uSubLeaf++;
1204 memcpy(auPrev, auCur, sizeof(auCur));
1205 }
1206
1207 /* Standard exit. */
1208 *pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1209 *pcSubLeaves = uSubLeaf + 1 - cRepeats;
1210 if (*pcSubLeaves == 0)
1211 *pcSubLeaves = 1;
1212 return true;
1213}
1214
1215
1216/**
1217 * Gets a CPU ID leaf.
1218 *
1219 * @returns VBox status code.
1220 * @param pVM The cross context VM structure.
1221 * @param pLeaf Where to store the found leaf.
1222 * @param uLeaf The leaf to locate.
1223 * @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1224 */
1225VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1226{
1227 PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1228 uLeaf, uSubLeaf);
1229 if (pcLeaf)
1230 {
1231 memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1232 return VINF_SUCCESS;
1233 }
1234
1235 return VERR_NOT_FOUND;
1236}
1237
1238
1239/**
1240 * Inserts a CPU ID leaf, replacing any existing ones.
1241 *
1242 * @returns VBox status code.
1243 * @param pVM The cross context VM structure.
1244 * @param pNewLeaf Pointer to the leaf being inserted.
1245 */
1246VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1247{
1248 /*
1249 * Validate parameters.
1250 */
1251 AssertReturn(pVM, VERR_INVALID_PARAMETER);
1252 AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1253
1254 /*
1255 * Disallow replacing CPU ID leaves that this API currently cannot manage.
1256 * These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1257 * If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1258 */
1259 if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1260 || pNewLeaf->uLeaf == UINT32_C(0x00000001)
1261 || pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1262 || pNewLeaf->uLeaf == UINT32_C(0x80000001)
1263 || pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1264 || pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1265 {
1266 return VERR_NOT_SUPPORTED;
1267 }
1268
1269 return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves */, NULL /* pcLeaves */, pNewLeaf);
1270}
1271
1272/**
1273 * Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1274 *
1275 * @returns VBox status code.
1276 * @param ppaLeaves Where to return the array pointer on success.
1277 * Use RTMemFree to release.
1278 * @param pcLeaves Where to return the size of the array on
1279 * success.
1280 */
1281VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
1282{
1283 *ppaLeaves = NULL;
1284 *pcLeaves = 0;
1285
1286 /*
1287 * Try out various candidates. This must be sorted!
1288 */
1289 static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1290 {
1291 { UINT32_C(0x00000000), false },
1292 { UINT32_C(0x10000000), false },
1293 { UINT32_C(0x20000000), false },
1294 { UINT32_C(0x30000000), false },
1295 { UINT32_C(0x40000000), false },
1296 { UINT32_C(0x50000000), false },
1297 { UINT32_C(0x60000000), false },
1298 { UINT32_C(0x70000000), false },
1299 { UINT32_C(0x80000000), false },
1300 { UINT32_C(0x80860000), false },
1301 { UINT32_C(0x8ffffffe), true },
1302 { UINT32_C(0x8fffffff), true },
1303 { UINT32_C(0x90000000), false },
1304 { UINT32_C(0xa0000000), false },
1305 { UINT32_C(0xb0000000), false },
1306 { UINT32_C(0xc0000000), false },
1307 { UINT32_C(0xd0000000), false },
1308 { UINT32_C(0xe0000000), false },
1309 { UINT32_C(0xf0000000), false },
1310 };
1311
1312 for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1313 {
1314 uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1315 uint32_t uEax, uEbx, uEcx, uEdx;
1316 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1317
1318 /*
1319 * Does EAX look like a typical leaf count value?
1320 */
1321 if ( uEax > uLeaf
1322 && uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1323 {
1324 /* Yes, dump them. */
1325 uint32_t cLeaves = uEax - uLeaf + 1;
1326 while (cLeaves-- > 0)
1327 {
1328 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1329
1330 uint32_t fFlags = 0;
1331
1332 /* There are currently three known leaves containing an APIC ID
1333 that needs EMT specific attention */
1334 if (uLeaf == 1)
1335 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1336 else if (uLeaf == 0xb && uEcx != 0)
1337 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1338 else if ( uLeaf == UINT32_C(0x8000001e)
1339 && ( uEax
1340 || uEbx
1341 || uEdx
1342 || ASMIsAmdCpuEx((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1343 || ASMIsHygonCpuEx((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1344 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1345
1346 /* The APIC bit is per-VCpu and needs flagging. */
1347 if (uLeaf == 1)
1348 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1349 else if ( uLeaf == UINT32_C(0x80000001)
1350 && ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1351 || ASMIsAmdCpuEx((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)
1352 || ASMIsHygonCpuEx((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1353 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1354
1355 /* Check three times here to reduce the chance of CPU migration
1356 resulting in false positives with things like the APIC ID. */
1357 uint32_t cSubLeaves;
1358 bool fFinalEcxUnchanged;
1359 if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1360 && cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1361 && cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1362 {
1363 if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1364 {
1365 /* This shouldn't happen. But in case it does, file all
1366 relevant details in the release log. */
1367 LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1368 LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1369 for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1370 {
1371 uint32_t auTmp[4];
1372 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1373 LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1374 uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1375 }
1376 LogRel(("----------------- dump of what we've found so far -----------------\n"));
1377 for (uint32_t i = 0 ; i < *pcLeaves; i++)
1378 LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1379 (*ppaLeaves)[i].uLeaf, (*ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1380 (*ppaLeaves)[i].uEax, (*ppaLeaves)[i].uEbx, (*ppaLeaves)[i].uEcx, (*ppaLeaves)[i].uEdx));
1381 LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1382 return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1383 }
1384
1385 if (fFinalEcxUnchanged)
1386 fFlags |= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1387
1388 for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1389 {
1390 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1391 int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1392 uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1393 if (RT_FAILURE(rc))
1394 return rc;
1395 }
1396 }
1397 else
1398 {
1399 int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1400 uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1401 if (RT_FAILURE(rc))
1402 return rc;
1403 }
1404
1405 /* next */
1406 uLeaf++;
1407 }
1408 }
1409 /*
1410 * Special CPUIDs needs special handling as they don't follow the
1411 * leaf count principle used above.
1412 */
1413 else if (s_aCandidates[iOuter].fSpecial)
1414 {
1415 bool fKeep = false;
1416 if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1417 fKeep = true;
1418 else if ( uLeaf == 0x8fffffff
1419 && RT_C_IS_PRINT(RT_BYTE1(uEax))
1420 && RT_C_IS_PRINT(RT_BYTE2(uEax))
1421 && RT_C_IS_PRINT(RT_BYTE3(uEax))
1422 && RT_C_IS_PRINT(RT_BYTE4(uEax))
1423 && RT_C_IS_PRINT(RT_BYTE1(uEbx))
1424 && RT_C_IS_PRINT(RT_BYTE2(uEbx))
1425 && RT_C_IS_PRINT(RT_BYTE3(uEbx))
1426 && RT_C_IS_PRINT(RT_BYTE4(uEbx))
1427 && RT_C_IS_PRINT(RT_BYTE1(uEcx))
1428 && RT_C_IS_PRINT(RT_BYTE2(uEcx))
1429 && RT_C_IS_PRINT(RT_BYTE3(uEcx))
1430 && RT_C_IS_PRINT(RT_BYTE4(uEcx))
1431 && RT_C_IS_PRINT(RT_BYTE1(uEdx))
1432 && RT_C_IS_PRINT(RT_BYTE2(uEdx))
1433 && RT_C_IS_PRINT(RT_BYTE3(uEdx))
1434 && RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1435 fKeep = true;
1436 if (fKeep)
1437 {
1438 int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1439 uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1440 if (RT_FAILURE(rc))
1441 return rc;
1442 }
1443 }
1444 }
1445
1446 cpumR3CpuIdAssertOrder(*ppaLeaves, *pcLeaves);
1447 return VINF_SUCCESS;
1448}
1449
1450
1451/**
1452 * Determines the method the CPU uses to handle unknown CPUID leaves.
1453 *
1454 * @returns VBox status code.
1455 * @param penmUnknownMethod Where to return the method.
1456 * @param pDefUnknown Where to return default unknown values. This
1457 * will be set, even if the resulting method
1458 * doesn't actually needs it.
1459 */
1460VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1461{
1462 uint32_t uLastStd = ASMCpuId_EAX(0);
1463 uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1464 if (!ASMIsValidExtRange(uLastExt))
1465 uLastExt = 0x80000000;
1466
1467 uint32_t auChecks[] =
1468 {
1469 uLastStd + 1,
1470 uLastStd + 5,
1471 uLastStd + 8,
1472 uLastStd + 32,
1473 uLastStd + 251,
1474 uLastExt + 1,
1475 uLastExt + 8,
1476 uLastExt + 15,
1477 uLastExt + 63,
1478 uLastExt + 255,
1479 0x7fbbffcc,
1480 0x833f7872,
1481 0xefff2353,
1482 0x35779456,
1483 0x1ef6d33e,
1484 };
1485
1486 static const uint32_t s_auValues[] =
1487 {
1488 0xa95d2156,
1489 0x00000001,
1490 0x00000002,
1491 0x00000008,
1492 0x00000000,
1493 0x55773399,
1494 0x93401769,
1495 0x12039587,
1496 };
1497
1498 /*
1499 * Simple method, all zeros.
1500 */
1501 *penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1502 pDefUnknown->uEax = 0;
1503 pDefUnknown->uEbx = 0;
1504 pDefUnknown->uEcx = 0;
1505 pDefUnknown->uEdx = 0;
1506
1507 /*
1508 * Intel has been observed returning the last standard leaf.
1509 */
1510 uint32_t auLast[4];
1511 ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1512
1513 uint32_t cChecks = RT_ELEMENTS(auChecks);
1514 while (cChecks > 0)
1515 {
1516 uint32_t auCur[4];
1517 ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1518 if (memcmp(auCur, auLast, sizeof(auCur)))
1519 break;
1520 cChecks--;
1521 }
1522 if (cChecks == 0)
1523 {
1524 /* Now, what happens when the input changes? Esp. ECX. */
1525 uint32_t cTotal = 0;
1526 uint32_t cSame = 0;
1527 uint32_t cLastWithEcx = 0;
1528 uint32_t cNeither = 0;
1529 uint32_t cValues = RT_ELEMENTS(s_auValues);
1530 while (cValues > 0)
1531 {
1532 uint32_t uValue = s_auValues[cValues - 1];
1533 uint32_t auLastWithEcx[4];
1534 ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1535 &auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1536
1537 cChecks = RT_ELEMENTS(auChecks);
1538 while (cChecks > 0)
1539 {
1540 uint32_t auCur[4];
1541 ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1542 if (!memcmp(auCur, auLast, sizeof(auCur)))
1543 {
1544 cSame++;
1545 if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1546 cLastWithEcx++;
1547 }
1548 else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1549 cLastWithEcx++;
1550 else
1551 cNeither++;
1552 cTotal++;
1553 cChecks--;
1554 }
1555 cValues--;
1556 }
1557
1558 Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1559 if (cSame == cTotal)
1560 *penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1561 else if (cLastWithEcx == cTotal)
1562 *penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1563 else
1564 *penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1565 pDefUnknown->uEax = auLast[0];
1566 pDefUnknown->uEbx = auLast[1];
1567 pDefUnknown->uEcx = auLast[2];
1568 pDefUnknown->uEdx = auLast[3];
1569 return VINF_SUCCESS;
1570 }
1571
1572 /*
1573 * Unchanged register values?
1574 */
1575 cChecks = RT_ELEMENTS(auChecks);
1576 while (cChecks > 0)
1577 {
1578 uint32_t const uLeaf = auChecks[cChecks - 1];
1579 uint32_t cValues = RT_ELEMENTS(s_auValues);
1580 while (cValues > 0)
1581 {
1582 uint32_t uValue = s_auValues[cValues - 1];
1583 uint32_t auCur[4];
1584 ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1585 if ( auCur[0] != uLeaf
1586 || auCur[1] != uValue
1587 || auCur[2] != uValue
1588 || auCur[3] != uValue)
1589 break;
1590 cValues--;
1591 }
1592 if (cValues != 0)
1593 break;
1594 cChecks--;
1595 }
1596 if (cChecks == 0)
1597 {
1598 *penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1599 return VINF_SUCCESS;
1600 }
1601
1602 /*
1603 * Just go with the simple method.
1604 */
1605 return VINF_SUCCESS;
1606}
1607
1608
1609/**
1610 * Translates a unknow CPUID leaf method into the constant name (sans prefix).
1611 *
1612 * @returns Read only name string.
1613 * @param enmUnknownMethod The method to translate.
1614 */
1615VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1616{
1617 switch (enmUnknownMethod)
1618 {
1619 case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1620 case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1621 case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1622 case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1623
1624 case CPUMUNKNOWNCPUID_INVALID:
1625 case CPUMUNKNOWNCPUID_END:
1626 case CPUMUNKNOWNCPUID_32BIT_HACK:
1627 break;
1628 }
1629 return "Invalid-unknown-CPUID-method";
1630}
1631
1632
1633/**
1634 * Detect the CPU vendor give n the
1635 *
1636 * @returns The vendor.
1637 * @param uEAX EAX from CPUID(0).
1638 * @param uEBX EBX from CPUID(0).
1639 * @param uECX ECX from CPUID(0).
1640 * @param uEDX EDX from CPUID(0).
1641 */
1642VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1643{
1644 if (ASMIsValidStdRange(uEAX))
1645 {
1646 if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1647 return CPUMCPUVENDOR_AMD;
1648
1649 if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1650 return CPUMCPUVENDOR_INTEL;
1651
1652 if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1653 return CPUMCPUVENDOR_VIA;
1654
1655 if (ASMIsShanghaiCpuEx(uEBX, uECX, uEDX))
1656 return CPUMCPUVENDOR_SHANGHAI;
1657
1658 if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1659 && uECX == UINT32_C(0x64616574)
1660 && uEDX == UINT32_C(0x736E4978))
1661 return CPUMCPUVENDOR_CYRIX;
1662
1663 if (ASMIsHygonCpuEx(uEBX, uECX, uEDX))
1664 return CPUMCPUVENDOR_HYGON;
1665
1666 /* "Geode by NSC", example: family 5, model 9. */
1667
1668 /** @todo detect the other buggers... */
1669 }
1670
1671 return CPUMCPUVENDOR_UNKNOWN;
1672}
1673
1674
1675/**
1676 * Translates a CPU vendor enum value into the corresponding string constant.
1677 *
1678 * The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1679 * value name. This can be useful when generating code.
1680 *
1681 * @returns Read only name string.
1682 * @param enmVendor The CPU vendor value.
1683 */
1684VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1685{
1686 switch (enmVendor)
1687 {
1688 case CPUMCPUVENDOR_INTEL: return "INTEL";
1689 case CPUMCPUVENDOR_AMD: return "AMD";
1690 case CPUMCPUVENDOR_VIA: return "VIA";
1691 case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1692 case CPUMCPUVENDOR_SHANGHAI: return "SHANGHAI";
1693 case CPUMCPUVENDOR_HYGON: return "HYGON";
1694 case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1695
1696 case CPUMCPUVENDOR_INVALID:
1697 case CPUMCPUVENDOR_32BIT_HACK:
1698 break;
1699 }
1700 return "Invalid-cpu-vendor";
1701}
1702
1703
1704static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1705{
1706 /* Could do binary search, doing linear now because I'm lazy. */
1707 PCCPUMCPUIDLEAF pLeaf = paLeaves;
1708 while (cLeaves-- > 0)
1709 {
1710 if (pLeaf->uLeaf == uLeaf)
1711 return pLeaf;
1712 pLeaf++;
1713 }
1714 return NULL;
1715}
1716
1717
1718static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1719{
1720 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1721 if ( !pLeaf
1722 || pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1723 return pLeaf;
1724
1725 /* Linear sub-leaf search. Lazy as usual. */
1726 cLeaves -= pLeaf - paLeaves;
1727 while ( cLeaves-- > 0
1728 && pLeaf->uLeaf == uLeaf)
1729 {
1730 if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1731 return pLeaf;
1732 pLeaf++;
1733 }
1734
1735 return NULL;
1736}
1737
1738
1739static void cpumR3ExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURES pFeatures)
1740{
1741 Assert(pVmxMsrs);
1742 Assert(pFeatures);
1743 Assert(pFeatures->fVmx);
1744
1745 /* Basic information. */
1746 {
1747 uint64_t const u64Basic = pVmxMsrs->u64Basic;
1748 pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1749 }
1750
1751 /* Pin-based VM-execution controls. */
1752 {
1753 uint32_t const fPinCtls = pVmxMsrs->PinCtls.n.allowed1;
1754 pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1755 pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1756 pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1757 pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1758 pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1759 }
1760
1761 /* Processor-based VM-execution controls. */
1762 {
1763 uint32_t const fProcCtls = pVmxMsrs->ProcCtls.n.allowed1;
1764 pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1765 pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1766 pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1767 pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1768 pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1769 pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1770 pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1771 pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1772 pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1773 pFeatures->fVmxTertiaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1774 pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1775 pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1776 pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1777 pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1778 pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1779 pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1780 pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1781 pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1782 pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1783 pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1784 pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1785 pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1786 }
1787
1788 /* Secondary processor-based VM-execution controls. */
1789 {
1790 uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1791 pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1792 pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1793 pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1794 pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1795 pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1796 pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1797 pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1798 pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1799 pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1800 pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1801 pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1802 pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1803 pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1804 pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1805 pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1806 pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1807 pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1808 pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE);
1809 pFeatures->fVmxConcealVmxFromPt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1810 pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1811 pFeatures->fVmxModeBasedExecuteEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1812 pFeatures->fVmxSppEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_SPP_EPT);
1813 pFeatures->fVmxPtEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PT_EPT);
1814 pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1815 pFeatures->fVmxUserWaitPause = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1816 pFeatures->fVmxEnclvExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_ENCLV_EXIT);
1817 }
1818
1819 /* Tertiary processor-based VM-execution controls. */
1820 {
1821 uint64_t const fProcCtls3 = pFeatures->fVmxTertiaryExecCtls ? pVmxMsrs->u64ProcCtls3 : 0;
1822 pFeatures->fVmxLoadIwKeyExit = RT_BOOL(fProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT);
1823 }
1824
1825 /* VM-exit controls. */
1826 {
1827 uint32_t const fExitCtls = pVmxMsrs->ExitCtls.n.allowed1;
1828 pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1829 pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1830 pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1831 pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1832 pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1833 pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1834 pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1835 pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1836 }
1837
1838 /* VM-entry controls. */
1839 {
1840 uint32_t const fEntryCtls = pVmxMsrs->EntryCtls.n.allowed1;
1841 pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1842 pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1843 pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1844 pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1845 }
1846
1847 /* Miscellaneous data. */
1848 {
1849 uint32_t const fMiscData = pVmxMsrs->u64Misc;
1850 pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1851 pFeatures->fVmxPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1852 pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1853 pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1854 }
1855}
1856
1857
1858int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures)
1859{
1860 Assert(pMsrs);
1861 RT_ZERO(*pFeatures);
1862 if (cLeaves >= 2)
1863 {
1864 AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1865 AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1866 PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1867 AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1868 PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1869 AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1870
1871 pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1872 pStd0Leaf->uEbx,
1873 pStd0Leaf->uEcx,
1874 pStd0Leaf->uEdx);
1875 pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1876 pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1877 pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1878 pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1879 pFeatures->uFamily,
1880 pFeatures->uModel,
1881 pFeatures->uStepping);
1882
1883 PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1884 if (pExtLeaf8)
1885 {
1886 pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1887 pFeatures->cMaxLinearAddrWidth = (pExtLeaf8->uEax >> 8) & 0xff;
1888 }
1889 else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1890 {
1891 pFeatures->cMaxPhysAddrWidth = 36;
1892 pFeatures->cMaxLinearAddrWidth = 36;
1893 }
1894 else
1895 {
1896 pFeatures->cMaxPhysAddrWidth = 32;
1897 pFeatures->cMaxLinearAddrWidth = 32;
1898 }
1899
1900 /* Standard features. */
1901 pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1902 pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1903 pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1904 pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1905 pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1906 pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1907 pFeatures->fPge = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PGE);
1908 pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1909 pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1910 pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1911 pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1912 pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1913 pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1914 pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1915 pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1916 pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1917 pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1918 pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1919 pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1920 pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1921 pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1922 pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1923 pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1924 pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1925 pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1926 pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1927 pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1928 if (pFeatures->fVmx)
1929 cpumR3ExplodeVmxFeatures(&pMsrs->hwvirt.vmx, pFeatures);
1930
1931 /* Structured extended features. */
1932 PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1933 if (pSxfLeaf0)
1934 {
1935 pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1936 pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1937 pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1938 pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1939 pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1940
1941 pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1942 pFeatures->fIbrs = pFeatures->fIbpb;
1943 pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1944 pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
1945 pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1946 pFeatures->fMdsClear = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
1947 }
1948
1949 /* MWAIT/MONITOR leaf. */
1950 PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1951 if (pMWaitLeaf)
1952 pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1953 == (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1954
1955 /* Extended features. */
1956 PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1957 if (pExtLeaf)
1958 {
1959 pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1960 pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1961 pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1962 pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1963 pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1964 pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1965 pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1966 pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1967 || (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1968 | X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1969 }
1970
1971 /* VMX (VMXON, VMCS region and related data structures) physical address width (depends on long-mode). */
1972 pFeatures->cVmxMaxPhysAddrWidth = pFeatures->fLongMode ? pFeatures->cMaxPhysAddrWidth : 32;
1973
1974 if ( pExtLeaf
1975 && ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1976 || pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON))
1977 {
1978 /* AMD features. */
1979 pFeatures->fMsr |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1980 pFeatures->fApic |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1981 pFeatures->fPse |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1982 pFeatures->fPse36 |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1983 pFeatures->fPae |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1984 pFeatures->fPge |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PGE);
1985 pFeatures->fPat |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1986 pFeatures->fFxSaveRstor |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1987 pFeatures->fMmx |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1988 pFeatures->fTsc |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1989 pFeatures->fIbpb |= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1990 pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1991 pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1992 pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1993 if (pFeatures->fSvm)
1994 {
1995 PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1996 AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1997 pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1998 pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1999 pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
2000 pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
2001 pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
2002 pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
2003 pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
2004 pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
2005 pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
2006 pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
2007 pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
2008 pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
2009 pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
2010 pFeatures->fSvmGmet = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_GMET);
2011 pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
2012 }
2013 }
2014
2015 /*
2016 * Quirks.
2017 */
2018 pFeatures->fLeakyFxSR = pExtLeaf
2019 && (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2020 && ( ( pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
2021 && pFeatures->uFamily >= 6 /* K7 and up */)
2022 || pFeatures->enmCpuVendor == CPUMCPUVENDOR_HYGON);
2023
2024 /*
2025 * Max extended (/FPU) state.
2026 */
2027 pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
2028 if (pFeatures->fXSaveRstor)
2029 {
2030 PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
2031 if (pXStateLeaf0)
2032 {
2033 if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
2034 && pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
2035 && RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
2036 && pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
2037 && pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
2038 && RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
2039 {
2040 pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
2041
2042 /* (paranoia:) */
2043 PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
2044 if ( pXStateLeaf1
2045 && pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
2046 && pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
2047 && (pXStateLeaf1->uEcx || pXStateLeaf1->uEdx) )
2048 pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
2049 }
2050 else
2051 AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
2052 pFeatures->fXSaveRstor = 0);
2053 }
2054 else
2055 AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
2056 pFeatures->fXSaveRstor = 0);
2057 }
2058 }
2059 else
2060 AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
2061 return VINF_SUCCESS;
2062}
2063
2064
2065/*
2066 *
2067 * Init related code.
2068 * Init related code.
2069 * Init related code.
2070 *
2071 *
2072 */
2073#ifndef IN_VBOX_CPU_REPORT
2074
2075
2076/**
2077 * Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
2078 *
2079 * This ignores the fSubLeafMask.
2080 *
2081 * @returns Pointer to the matching leaf, or NULL if not found.
2082 * @param pCpum The CPUM instance data.
2083 * @param uLeaf The leaf to locate.
2084 * @param uSubLeaf The subleaf to locate.
2085 */
2086static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
2087{
2088 uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
2089 PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
2090 uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
2091 if (iEnd)
2092 {
2093 uint32_t iBegin = 0;
2094 for (;;)
2095 {
2096 uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
2097 uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
2098 if (uNeedle < uCur)
2099 {
2100 if (i > iBegin)
2101 iEnd = i;
2102 else
2103 break;
2104 }
2105 else if (uNeedle > uCur)
2106 {
2107 if (i + 1 < iEnd)
2108 iBegin = i + 1;
2109 else
2110 break;
2111 }
2112 else
2113 return &paLeaves[i];
2114 }
2115 }
2116 return NULL;
2117}
2118
2119
2120/**
2121 * Loads MSR range overrides.
2122 *
2123 * This must be called before the MSR ranges are moved from the normal heap to
2124 * the hyper heap!
2125 *
2126 * @returns VBox status code (VMSetError called).
2127 * @param pVM The cross context VM structure.
2128 * @param pMsrNode The CFGM node with the MSR overrides.
2129 */
2130static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
2131{
2132 for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2133 {
2134 /*
2135 * Assemble a valid MSR range.
2136 */
2137 CPUMMSRRANGE MsrRange;
2138 MsrRange.offCpumCpu = 0;
2139 MsrRange.fReserved = 0;
2140
2141 int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
2142 if (RT_FAILURE(rc))
2143 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
2144
2145 rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
2146 if (RT_FAILURE(rc))
2147 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
2148 MsrRange.szName, rc);
2149
2150 rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
2151 if (RT_FAILURE(rc))
2152 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
2153 MsrRange.szName, rc);
2154
2155 char szType[32];
2156 rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
2157 if (RT_FAILURE(rc))
2158 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
2159 MsrRange.szName, rc);
2160 if (!RTStrICmp(szType, "FixedValue"))
2161 {
2162 MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
2163 MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
2164
2165 rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
2166 if (RT_FAILURE(rc))
2167 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
2168 MsrRange.szName, rc);
2169
2170 rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
2171 if (RT_FAILURE(rc))
2172 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
2173 MsrRange.szName, rc);
2174
2175 rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
2176 if (RT_FAILURE(rc))
2177 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
2178 MsrRange.szName, rc);
2179 }
2180 else
2181 return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
2182 "Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
2183
2184 /*
2185 * Insert the range into the table (replaces/splits/shrinks existing
2186 * MSR ranges).
2187 */
2188 rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
2189 &MsrRange);
2190 if (RT_FAILURE(rc))
2191 return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
2192 }
2193
2194 return VINF_SUCCESS;
2195}
2196
2197
2198/**
2199 * Loads CPUID leaf overrides.
2200 *
2201 * This must be called before the CPUID leaves are moved from the normal
2202 * heap to the hyper heap!
2203 *
2204 * @returns VBox status code (VMSetError called).
2205 * @param pVM The cross context VM structure.
2206 * @param pParentNode The CFGM node with the CPUID leaves.
2207 * @param pszLabel How to label the overrides we're loading.
2208 */
2209static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2210{
2211 for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2212 {
2213 /*
2214 * Get the leaf and subleaf numbers.
2215 */
2216 char szName[128];
2217 int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2218 if (RT_FAILURE(rc))
2219 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2220
2221 /* The leaf number is either specified directly or thru the node name. */
2222 uint32_t uLeaf;
2223 rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2224 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2225 {
2226 rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2227 if (rc != VINF_SUCCESS)
2228 return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2229 "Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2230 }
2231 else if (RT_FAILURE(rc))
2232 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2233 pszLabel, szName, rc);
2234
2235 uint32_t uSubLeaf;
2236 rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2237 if (RT_FAILURE(rc))
2238 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2239 pszLabel, szName, rc);
2240
2241 uint32_t fSubLeafMask;
2242 rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2243 if (RT_FAILURE(rc))
2244 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2245 pszLabel, szName, rc);
2246
2247 /*
2248 * Look up the specified leaf, since the output register values
2249 * defaults to any existing values. This allows overriding a single
2250 * register, without needing to know the other values.
2251 */
2252 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2253 CPUMCPUIDLEAF Leaf;
2254 if (pLeaf)
2255 Leaf = *pLeaf;
2256 else
2257 RT_ZERO(Leaf);
2258 Leaf.uLeaf = uLeaf;
2259 Leaf.uSubLeaf = uSubLeaf;
2260 Leaf.fSubLeafMask = fSubLeafMask;
2261
2262 rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2263 if (RT_FAILURE(rc))
2264 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2265 pszLabel, szName, rc);
2266 rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2267 if (RT_FAILURE(rc))
2268 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2269 pszLabel, szName, rc);
2270 rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2271 if (RT_FAILURE(rc))
2272 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2273 pszLabel, szName, rc);
2274 rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2275 if (RT_FAILURE(rc))
2276 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2277 pszLabel, szName, rc);
2278
2279 /*
2280 * Insert the leaf into the table (replaces existing ones).
2281 */
2282 rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2283 &Leaf);
2284 if (RT_FAILURE(rc))
2285 return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2286 }
2287
2288 return VINF_SUCCESS;
2289}
2290
2291
2292
2293/**
2294 * Fetches overrides for a CPUID leaf.
2295 *
2296 * @returns VBox status code.
2297 * @param pLeaf The leaf to load the overrides into.
2298 * @param pCfgNode The CFGM node containing the overrides
2299 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2300 * @param iLeaf The CPUID leaf number.
2301 */
2302static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2303{
2304 PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2305 if (pLeafNode)
2306 {
2307 uint32_t u32;
2308 int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2309 if (RT_SUCCESS(rc))
2310 pLeaf->uEax = u32;
2311 else
2312 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2313
2314 rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2315 if (RT_SUCCESS(rc))
2316 pLeaf->uEbx = u32;
2317 else
2318 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2319
2320 rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2321 if (RT_SUCCESS(rc))
2322 pLeaf->uEcx = u32;
2323 else
2324 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2325
2326 rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2327 if (RT_SUCCESS(rc))
2328 pLeaf->uEdx = u32;
2329 else
2330 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2331
2332 }
2333 return VINF_SUCCESS;
2334}
2335
2336
2337/**
2338 * Load the overrides for a set of CPUID leaves.
2339 *
2340 * @returns VBox status code.
2341 * @param paLeaves The leaf array.
2342 * @param cLeaves The number of leaves.
2343 * @param uStart The start leaf number.
2344 * @param pCfgNode The CFGM node containing the overrides
2345 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2346 */
2347static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2348{
2349 for (uint32_t i = 0; i < cLeaves; i++)
2350 {
2351 int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2352 if (RT_FAILURE(rc))
2353 return rc;
2354 }
2355
2356 return VINF_SUCCESS;
2357}
2358
2359
2360/**
2361 * Installs the CPUID leaves and explods the data into structures like
2362 * GuestFeatures and CPUMCTX::aoffXState.
2363 *
2364 * @returns VBox status code.
2365 * @param pVM The cross context VM structure.
2366 * @param pCpum The CPUM part of @a VM.
2367 * @param paLeaves The leaves. These will be copied (but not freed).
2368 * @param cLeaves The number of leaves.
2369 * @param pMsrs The MSRs.
2370 */
2371static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
2372{
2373 cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2374
2375 /*
2376 * Install the CPUID information.
2377 */
2378 AssertLogRelMsgReturn(cLeaves <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves),
2379 ("cLeaves=%u - max %u\n", cLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves)),
2380 VERR_CPUM_IPE_1); /** @todo better status! */
2381 if (paLeaves != pCpum->GuestInfo.aCpuIdLeaves)
2382 memcpy(pCpum->GuestInfo.aCpuIdLeaves, paLeaves, cLeaves * sizeof(paLeaves[0]));
2383 pCpum->GuestInfo.paCpuIdLeavesR3 = pCpum->GuestInfo.aCpuIdLeaves;
2384 pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2385
2386 /*
2387 * Update the default CPUID leaf if necessary.
2388 */
2389 switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2390 {
2391 case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2392 case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2393 {
2394 /* We don't use CPUID(0).eax here because of the NT hack that only
2395 changes that value without actually removing any leaves. */
2396 uint32_t i = 0;
2397 if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2398 && pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2399 {
2400 while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2401 && pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2402 i++;
2403 pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2404 pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2405 pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2406 pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2407 }
2408 break;
2409 }
2410 default:
2411 break;
2412 }
2413
2414 /*
2415 * Explode the guest CPU features.
2416 */
2417 int rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
2418 &pCpum->GuestFeatures);
2419 AssertLogRelRCReturn(rc, rc);
2420
2421 /*
2422 * Adjust the scalable bus frequency according to the CPUID information
2423 * we're now using.
2424 */
2425 if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2426 pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2427 ? UINT64_C(100000000) /* 100MHz */
2428 : UINT64_C(133333333); /* 133MHz */
2429
2430 /*
2431 * Populate the legacy arrays. Currently used for everything, later only
2432 * for patch manager.
2433 */
2434 struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2435 {
2436 { pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2437 { pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2438 { pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2439 };
2440 for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2441 {
2442 uint32_t cLeft = aOldRanges[i].cCpuIds;
2443 uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2444 PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2445 while (cLeft-- > 0)
2446 {
2447 uLeaf--;
2448 pLegacyLeaf--;
2449
2450 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2451 if (pLeaf)
2452 {
2453 pLegacyLeaf->uEax = pLeaf->uEax;
2454 pLegacyLeaf->uEbx = pLeaf->uEbx;
2455 pLegacyLeaf->uEcx = pLeaf->uEcx;
2456 pLegacyLeaf->uEdx = pLeaf->uEdx;
2457 }
2458 else
2459 *pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2460 }
2461 }
2462
2463 /*
2464 * Configure XSAVE offsets according to the CPUID info and set the feature flags.
2465 */
2466 PVMCPU pVCpu0 = pVM->apCpusR3[0];
2467 AssertCompile(sizeof(pVCpu0->cpum.s.Guest.abXState) == CPUM_MAX_XSAVE_AREA_SIZE);
2468 memset(&pVCpu0->cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2469 pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2470 pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2471 for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2472 if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2473 {
2474 PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2475 AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2476 AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2477 AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2478 && pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2479 && pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2480 && pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2481 && pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2482 ("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2483 pCpum->GuestFeatures.cbMaxExtendedState),
2484 VERR_CPUM_IPE_1);
2485 pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2486 }
2487
2488 /* Copy the CPU #0 data to the other CPUs. */
2489 for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
2490 {
2491 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2492 memcpy(&pVCpu->cpum.s.Guest.aoffXState[0], &pVCpu0->cpum.s.Guest.aoffXState[0], sizeof(pVCpu0->cpum.s.Guest.aoffXState));
2493 }
2494
2495 return VINF_SUCCESS;
2496}
2497
2498
2499/** @name Instruction Set Extension Options
2500 * @{ */
2501/** Configuration option type (extended boolean, really). */
2502typedef uint8_t CPUMISAEXTCFG;
2503/** Always disable the extension. */
2504#define CPUMISAEXTCFG_DISABLED false
2505/** Enable the extension if it's supported by the host CPU. */
2506#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2507/** Enable the extension if it's supported by the host CPU, but don't let
2508 * the portable CPUID feature disable it. */
2509#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2510/** Always enable the extension. */
2511#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2512/** @} */
2513
2514/**
2515 * CPUID Configuration (from CFGM).
2516 *
2517 * @remarks The members aren't document since we would only be duplicating the
2518 * \@cfgm entries in cpumR3CpuIdReadConfig.
2519 */
2520typedef struct CPUMCPUIDCONFIG
2521{
2522 bool fNt4LeafLimit;
2523 bool fInvariantTsc;
2524 bool fForceVme;
2525 bool fNestedHWVirt;
2526
2527 CPUMISAEXTCFG enmCmpXchg16b;
2528 CPUMISAEXTCFG enmMonitor;
2529 CPUMISAEXTCFG enmMWaitExtensions;
2530 CPUMISAEXTCFG enmSse41;
2531 CPUMISAEXTCFG enmSse42;
2532 CPUMISAEXTCFG enmAvx;
2533 CPUMISAEXTCFG enmAvx2;
2534 CPUMISAEXTCFG enmXSave;
2535 CPUMISAEXTCFG enmAesNi;
2536 CPUMISAEXTCFG enmPClMul;
2537 CPUMISAEXTCFG enmPopCnt;
2538 CPUMISAEXTCFG enmMovBe;
2539 CPUMISAEXTCFG enmRdRand;
2540 CPUMISAEXTCFG enmRdSeed;
2541 CPUMISAEXTCFG enmCLFlushOpt;
2542 CPUMISAEXTCFG enmFsGsBase;
2543 CPUMISAEXTCFG enmPcid;
2544 CPUMISAEXTCFG enmInvpcid;
2545 CPUMISAEXTCFG enmFlushCmdMsr;
2546 CPUMISAEXTCFG enmMdsClear;
2547 CPUMISAEXTCFG enmArchCapMsr;
2548
2549 CPUMISAEXTCFG enmAbm;
2550 CPUMISAEXTCFG enmSse4A;
2551 CPUMISAEXTCFG enmMisAlnSse;
2552 CPUMISAEXTCFG enm3dNowPrf;
2553 CPUMISAEXTCFG enmAmdExtMmx;
2554
2555 uint32_t uMaxStdLeaf;
2556 uint32_t uMaxExtLeaf;
2557 uint32_t uMaxCentaurLeaf;
2558 uint32_t uMaxIntelFamilyModelStep;
2559 char szCpuName[128];
2560} CPUMCPUIDCONFIG;
2561/** Pointer to CPUID config (from CFGM). */
2562typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2563
2564
2565/**
2566 * Mini CPU selection support for making Mac OS X happy.
2567 *
2568 * Executes the /CPUM/MaxIntelFamilyModelStep config.
2569 *
2570 * @param pCpum The CPUM instance data.
2571 * @param pConfig The CPUID configuration we've read from CFGM.
2572 */
2573static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2574{
2575 if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2576 {
2577 PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2578 uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2579 ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2580 ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2581 0);
2582 uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2583 if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2584 {
2585 uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2586 uNew |= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2587 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2588 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2589 uNew |= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2590 if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2591 uNew |= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2592 LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2593 pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2594 pStdFeatureLeaf->uEax = uNew;
2595 }
2596 }
2597}
2598
2599
2600
2601/**
2602 * Limit it the number of entries, zapping the remainder.
2603 *
2604 * The limits are masking off stuff about power saving and similar, this
2605 * is perhaps a bit crudely done as there is probably some relatively harmless
2606 * info too in these leaves (like words about having a constant TSC).
2607 *
2608 * @param pCpum The CPUM instance data.
2609 * @param pConfig The CPUID configuration we've read from CFGM.
2610 */
2611static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2612{
2613 /*
2614 * Standard leaves.
2615 */
2616 uint32_t uSubLeaf = 0;
2617 PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2618 if (pCurLeaf)
2619 {
2620 uint32_t uLimit = pCurLeaf->uEax;
2621 if (uLimit <= UINT32_C(0x000fffff))
2622 {
2623 if (uLimit > pConfig->uMaxStdLeaf)
2624 {
2625 pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2626 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2627 uLimit + 1, UINT32_C(0x000fffff));
2628 }
2629
2630 /* NT4 hack, no zapping of extra leaves here. */
2631 if (pConfig->fNt4LeafLimit && uLimit > 3)
2632 pCurLeaf->uEax = uLimit = 3;
2633
2634 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2635 pCurLeaf->uEax = uLimit;
2636 }
2637 else
2638 {
2639 LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2640 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2641 UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2642 }
2643 }
2644
2645 /*
2646 * Extended leaves.
2647 */
2648 uSubLeaf = 0;
2649 pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2650 if (pCurLeaf)
2651 {
2652 uint32_t uLimit = pCurLeaf->uEax;
2653 if ( uLimit >= UINT32_C(0x80000000)
2654 && uLimit <= UINT32_C(0x800fffff))
2655 {
2656 if (uLimit > pConfig->uMaxExtLeaf)
2657 {
2658 pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2659 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2660 uLimit + 1, UINT32_C(0x800fffff));
2661 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2662 pCurLeaf->uEax = uLimit;
2663 }
2664 }
2665 else
2666 {
2667 LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2668 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2669 UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2670 }
2671 }
2672
2673 /*
2674 * Centaur leaves (VIA).
2675 */
2676 uSubLeaf = 0;
2677 pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2678 if (pCurLeaf)
2679 {
2680 uint32_t uLimit = pCurLeaf->uEax;
2681 if ( uLimit >= UINT32_C(0xc0000000)
2682 && uLimit <= UINT32_C(0xc00fffff))
2683 {
2684 if (uLimit > pConfig->uMaxCentaurLeaf)
2685 {
2686 pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2687 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2688 uLimit + 1, UINT32_C(0xcfffffff));
2689 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2690 pCurLeaf->uEax = uLimit;
2691 }
2692 }
2693 else
2694 {
2695 LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2696 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2697 UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2698 }
2699 }
2700}
2701
2702
2703/**
2704 * Clears a CPUID leaf and all sub-leaves (to zero).
2705 *
2706 * @param pCpum The CPUM instance data.
2707 * @param uLeaf The leaf to clear.
2708 */
2709static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2710{
2711 uint32_t uSubLeaf = 0;
2712 PCPUMCPUIDLEAF pCurLeaf;
2713 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2714 {
2715 pCurLeaf->uEax = 0;
2716 pCurLeaf->uEbx = 0;
2717 pCurLeaf->uEcx = 0;
2718 pCurLeaf->uEdx = 0;
2719 uSubLeaf++;
2720 }
2721}
2722
2723
2724/**
2725 * Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2726 * the given leaf.
2727 *
2728 * @returns pLeaf.
2729 * @param pCpum The CPUM instance data.
2730 * @param pLeaf The leaf to ensure is alone with it's EAX input value.
2731 */
2732static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2733{
2734 Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2735 if (pLeaf->fSubLeafMask != 0)
2736 {
2737 /*
2738 * Figure out how many sub-leaves in need of removal (we'll keep the first).
2739 * Log everything while we're at it.
2740 */
2741 LogRel(("CPUM:\n"
2742 "CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2743 PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2744 PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2745 for (;;)
2746 {
2747 LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2748 pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2749 pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2750 pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2751 if (pSubLeaf == pLast || pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2752 break;
2753 pSubLeaf++;
2754 }
2755 LogRel(("CPUM:\n"));
2756
2757 /*
2758 * Remove the offending sub-leaves.
2759 */
2760 if (pSubLeaf != pLeaf)
2761 {
2762 if (pSubLeaf != pLast)
2763 memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2764 pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2765 }
2766
2767 /*
2768 * Convert the first sub-leaf into a single leaf.
2769 */
2770 pLeaf->uSubLeaf = 0;
2771 pLeaf->fSubLeafMask = 0;
2772 }
2773 return pLeaf;
2774}
2775
2776
2777/**
2778 * Sanitizes and adjust the CPUID leaves.
2779 *
2780 * Drop features that aren't virtualized (or virtualizable). Adjust information
2781 * and capabilities to fit the virtualized hardware. Remove information the
2782 * guest shouldn't have (because it's wrong in the virtual world or because it
2783 * gives away host details) or that we don't have documentation for and no idea
2784 * what means.
2785 *
2786 * @returns VBox status code.
2787 * @param pVM The cross context VM structure (for cCpus).
2788 * @param pCpum The CPUM instance data.
2789 * @param pConfig The CPUID configuration we've read from CFGM.
2790 */
2791static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2792{
2793#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2794 if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2795 { \
2796 LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2797 (a_pLeafReg) &= ~(uint32_t)(fMask); \
2798 }
2799#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2800 if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2801 { \
2802 LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2803 (a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2804 }
2805#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2806 if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2807 && ((a_pLeafReg) & (fBitMask)) \
2808 && (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2809 { \
2810 LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2811 (a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2812 }
2813 Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2814
2815 /* The CPUID entries we start with here isn't necessarily the ones of the host, so we
2816 must consult HostFeatures when processing CPUMISAEXTCFG variables. */
2817 PCCPUMFEATURES pHstFeat = &pCpum->HostFeatures;
2818#define PASSTHRU_FEATURE(enmConfig, fHostFeature, fConst) \
2819 ((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS || (fHostFeature)) ? (fConst) : 0)
2820#define PASSTHRU_FEATURE_EX(enmConfig, fHostFeature, fAndExpr, fConst) \
2821 ((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS || (fHostFeature)) && (fAndExpr) ? (fConst) : 0)
2822#define PASSTHRU_FEATURE_TODO(enmConfig, fConst) ((enmConfig) ? (fConst) : 0)
2823
2824 /* Cpuid 1:
2825 * EAX: CPU model, family and stepping.
2826 *
2827 * ECX + EDX: Supported features. Only report features we can support.
2828 * Note! When enabling new features the Synthetic CPU and Portable CPUID
2829 * options may require adjusting (i.e. stripping what was enabled).
2830 *
2831 * EBX: Branding, CLFLUSH line size, logical processors per package and
2832 * initial APIC ID.
2833 */
2834 PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2835 AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2836 pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2837
2838 pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2839 | X86_CPUID_FEATURE_EDX_VME
2840 | X86_CPUID_FEATURE_EDX_DE
2841 | X86_CPUID_FEATURE_EDX_PSE
2842 | X86_CPUID_FEATURE_EDX_TSC
2843 | X86_CPUID_FEATURE_EDX_MSR
2844 //| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2845 | X86_CPUID_FEATURE_EDX_MCE
2846 | X86_CPUID_FEATURE_EDX_CX8
2847 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2848 //| RT_BIT_32(10) - not defined
2849 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2850 //| X86_CPUID_FEATURE_EDX_SEP
2851 | X86_CPUID_FEATURE_EDX_MTRR
2852 | X86_CPUID_FEATURE_EDX_PGE
2853 | X86_CPUID_FEATURE_EDX_MCA
2854 | X86_CPUID_FEATURE_EDX_CMOV
2855 | X86_CPUID_FEATURE_EDX_PAT /* 16 */
2856 | X86_CPUID_FEATURE_EDX_PSE36
2857 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2858 | X86_CPUID_FEATURE_EDX_CLFSH
2859 //| RT_BIT_32(20) - not defined
2860 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
2861 //| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2862 | X86_CPUID_FEATURE_EDX_MMX
2863 | X86_CPUID_FEATURE_EDX_FXSR
2864 | X86_CPUID_FEATURE_EDX_SSE
2865 | X86_CPUID_FEATURE_EDX_SSE2
2866 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2867 | X86_CPUID_FEATURE_EDX_HTT
2868 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2869 //| RT_BIT_32(30) - not defined
2870 //| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2871 ;
2872 pStdFeatureLeaf->uEcx &= X86_CPUID_FEATURE_ECX_SSE3
2873 | PASSTHRU_FEATURE_TODO(pConfig->enmPClMul, X86_CPUID_FEATURE_ECX_PCLMUL)
2874 //| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2875 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2876 | PASSTHRU_FEATURE_EX(pConfig->enmMonitor, pHstFeat->fMonitorMWait, pVM->cCpus == 1, X86_CPUID_FEATURE_ECX_MONITOR)
2877 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2878 | (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2879 //| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2880 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2881 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2882 | X86_CPUID_FEATURE_ECX_SSSE3
2883 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2884 //| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2885 | PASSTHRU_FEATURE(pConfig->enmCmpXchg16b, pHstFeat->fMovCmpXchg16b, X86_CPUID_FEATURE_ECX_CX16)
2886 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2887 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
2888 //| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2889 | PASSTHRU_FEATURE(pConfig->enmPcid, pHstFeat->fPcid, X86_CPUID_FEATURE_ECX_PCID)
2890 //| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2891 | PASSTHRU_FEATURE(pConfig->enmSse41, pHstFeat->fSse41, X86_CPUID_FEATURE_ECX_SSE4_1)
2892 | PASSTHRU_FEATURE(pConfig->enmSse42, pHstFeat->fSse42, X86_CPUID_FEATURE_ECX_SSE4_2)
2893 //| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2894 | PASSTHRU_FEATURE_TODO(pConfig->enmMovBe, X86_CPUID_FEATURE_ECX_MOVBE)
2895 | PASSTHRU_FEATURE_TODO(pConfig->enmPopCnt, X86_CPUID_FEATURE_ECX_POPCNT)
2896 //| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2897 | PASSTHRU_FEATURE_TODO(pConfig->enmAesNi, X86_CPUID_FEATURE_ECX_AES)
2898 | PASSTHRU_FEATURE(pConfig->enmXSave, pHstFeat->fXSaveRstor, X86_CPUID_FEATURE_ECX_XSAVE)
2899 //| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2900 | PASSTHRU_FEATURE(pConfig->enmAvx, pHstFeat->fAvx, X86_CPUID_FEATURE_ECX_AVX)
2901 //| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2902 | PASSTHRU_FEATURE_TODO(pConfig->enmRdRand, X86_CPUID_FEATURE_ECX_RDRAND)
2903 //| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2904 ;
2905
2906 /* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2907 if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2908 && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2909 {
2910 pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2911 LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2912 }
2913
2914 if (pCpum->u8PortableCpuIdLevel > 0)
2915 {
2916 PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2917 PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2918 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2919 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2920 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2921 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2922 PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2923 PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2924 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2925 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2926 PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2927 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2928 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2929 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2930 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2931 PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2932 PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2933 PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2934 PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2935 PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2936
2937 Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2938 | X86_CPUID_FEATURE_EDX_PSN
2939 | X86_CPUID_FEATURE_EDX_DS
2940 | X86_CPUID_FEATURE_EDX_ACPI
2941 | X86_CPUID_FEATURE_EDX_SS
2942 | X86_CPUID_FEATURE_EDX_TM
2943 | X86_CPUID_FEATURE_EDX_PBE
2944 )));
2945 Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2946 | X86_CPUID_FEATURE_ECX_CPLDS
2947 | X86_CPUID_FEATURE_ECX_AES
2948 | X86_CPUID_FEATURE_ECX_VMX
2949 | X86_CPUID_FEATURE_ECX_SMX
2950 | X86_CPUID_FEATURE_ECX_EST
2951 | X86_CPUID_FEATURE_ECX_TM2
2952 | X86_CPUID_FEATURE_ECX_CNTXID
2953 | X86_CPUID_FEATURE_ECX_FMA
2954 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2955 | X86_CPUID_FEATURE_ECX_PDCM
2956 | X86_CPUID_FEATURE_ECX_DCA
2957 | X86_CPUID_FEATURE_ECX_OSXSAVE
2958 )));
2959 }
2960
2961 /* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2962 pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2963
2964 /* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2965 * it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2966 * information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2967 */
2968#ifdef VBOX_WITH_MULTI_CORE
2969 if (pVM->cCpus > 1)
2970 pStdFeatureLeaf->uEdx |= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2971#endif
2972 if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2973 {
2974 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2975 core times the number of CPU cores per processor */
2976#ifdef VBOX_WITH_MULTI_CORE
2977 pStdFeatureLeaf->uEbx |= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2978#else
2979 /* Single logical processor in a package. */
2980 pStdFeatureLeaf->uEbx |= (1 << 16);
2981#endif
2982 }
2983
2984 uint32_t uMicrocodeRev;
2985 int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2986 if (RT_SUCCESS(rc))
2987 {
2988 LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2989 }
2990 else
2991 {
2992 uMicrocodeRev = 0;
2993 LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2994 }
2995
2996 /* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2997 * VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2998 */
2999 if ( ( pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen
3000 /** @todo The following ASSUMES that Hygon uses the same version numbering
3001 * as AMD and that they shipped buggy firmware. */
3002 || pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Hygon_Dhyana)
3003 && uMicrocodeRev < 0x8001126
3004 && !pConfig->fForceVme)
3005 {
3006 /** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
3007 LogRel(("CPUM: Zen VME workaround engaged\n"));
3008 pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
3009 }
3010
3011 /* Force standard feature bits. */
3012 if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
3013 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_PCLMUL;
3014 if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
3015 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_MONITOR;
3016 if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
3017 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_CX16;
3018 if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3019 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_SSE4_1;
3020 if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3021 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_SSE4_2;
3022 if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
3023 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_MOVBE;
3024 if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3025 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_POPCNT;
3026 if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
3027 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_AES;
3028 if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
3029 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_XSAVE;
3030 if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3031 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_AVX;
3032 if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
3033 pStdFeatureLeaf->uEcx |= X86_CPUID_FEATURE_ECX_RDRAND;
3034
3035 pStdFeatureLeaf = NULL; /* Must refetch! */
3036
3037 /* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
3038 * AMD:
3039 * EAX: CPU model, family and stepping.
3040 *
3041 * ECX + EDX: Supported features. Only report features we can support.
3042 * Note! When enabling new features the Synthetic CPU and Portable CPUID
3043 * options may require adjusting (i.e. stripping what was enabled).
3044 * ASSUMES that this is ALWAYS the AMD defined feature set if present.
3045 *
3046 * EBX: Branding ID and package type (or reserved).
3047 *
3048 * Intel and probably most others:
3049 * EAX: 0
3050 * EBX: 0
3051 * ECX + EDX: Subset of AMD features, mainly for AMD64 support.
3052 */
3053 PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3054 if (pExtFeatureLeaf)
3055 {
3056 pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
3057
3058 pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
3059 | X86_CPUID_AMD_FEATURE_EDX_VME
3060 | X86_CPUID_AMD_FEATURE_EDX_DE
3061 | X86_CPUID_AMD_FEATURE_EDX_PSE
3062 | X86_CPUID_AMD_FEATURE_EDX_TSC
3063 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
3064 //| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
3065 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
3066 | X86_CPUID_AMD_FEATURE_EDX_CX8
3067 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
3068 //| RT_BIT_32(10) - reserved
3069 /* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
3070 eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
3071 //| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3072 | X86_CPUID_AMD_FEATURE_EDX_MTRR
3073 | X86_CPUID_AMD_FEATURE_EDX_PGE
3074 | X86_CPUID_AMD_FEATURE_EDX_MCA
3075 | X86_CPUID_AMD_FEATURE_EDX_CMOV
3076 | X86_CPUID_AMD_FEATURE_EDX_PAT
3077 | X86_CPUID_AMD_FEATURE_EDX_PSE36
3078 //| RT_BIT_32(18) - reserved
3079 //| RT_BIT_32(19) - reserved
3080 //| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
3081 //| RT_BIT_32(21) - reserved
3082 | PASSTHRU_FEATURE(pConfig->enmAmdExtMmx, pHstFeat->fAmdMmxExts, X86_CPUID_AMD_FEATURE_EDX_AXMMX)
3083 | X86_CPUID_AMD_FEATURE_EDX_MMX
3084 | X86_CPUID_AMD_FEATURE_EDX_FXSR
3085 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
3086 //| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3087 | X86_CPUID_EXT_FEATURE_EDX_RDTSCP
3088 //| RT_BIT_32(28) - reserved
3089 //| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
3090 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
3091 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
3092 ;
3093 pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
3094 //| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
3095 | (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
3096 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3097 /* Note: This could prevent teleporting from AMD to Intel CPUs! */
3098 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
3099 | PASSTHRU_FEATURE_TODO(pConfig->enmAbm, X86_CPUID_AMD_FEATURE_ECX_ABM)
3100 | PASSTHRU_FEATURE_TODO(pConfig->enmSse4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A)
3101 | PASSTHRU_FEATURE_TODO(pConfig->enmMisAlnSse, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE)
3102 | PASSTHRU_FEATURE(pConfig->enm3dNowPrf, pHstFeat->f3DNowPrefetch, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
3103 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
3104 //| X86_CPUID_AMD_FEATURE_ECX_IBS
3105 //| X86_CPUID_AMD_FEATURE_ECX_XOP
3106 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
3107 //| X86_CPUID_AMD_FEATURE_ECX_WDT
3108 //| RT_BIT_32(14) - reserved
3109 //| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
3110 //| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
3111 //| RT_BIT_32(17) - reserved
3112 //| RT_BIT_32(18) - reserved
3113 //| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
3114 //| RT_BIT_32(20) - reserved
3115 //| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
3116 //| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
3117 //| RT_BIT_32(23) - reserved
3118 //| RT_BIT_32(24) - reserved
3119 //| RT_BIT_32(25) - reserved
3120 //| RT_BIT_32(26) - reserved
3121 //| RT_BIT_32(27) - reserved
3122 //| RT_BIT_32(28) - reserved
3123 //| RT_BIT_32(29) - reserved
3124 //| RT_BIT_32(30) - reserved
3125 //| RT_BIT_32(31) - reserved
3126 ;
3127#ifdef VBOX_WITH_MULTI_CORE
3128 if ( pVM->cCpus > 1
3129 && ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3130 || pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3131 pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
3132#endif
3133
3134 if (pCpum->u8PortableCpuIdLevel > 0)
3135 {
3136 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
3137 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
3138 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
3139 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
3140 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
3141 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
3142 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
3143 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
3144 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
3145 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
3146 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
3147 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
3148 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
3149 PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
3150 PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
3151 PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
3152
3153 Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
3154 | X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
3155 | X86_CPUID_AMD_FEATURE_ECX_OSVW
3156 | X86_CPUID_AMD_FEATURE_ECX_IBS
3157 | X86_CPUID_AMD_FEATURE_ECX_SKINIT
3158 | X86_CPUID_AMD_FEATURE_ECX_WDT
3159 | X86_CPUID_AMD_FEATURE_ECX_LWP
3160 | X86_CPUID_AMD_FEATURE_ECX_NODEID
3161 | X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
3162 | UINT32_C(0xff964000)
3163 )));
3164 Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
3165 | X86_CPUID_EXT_FEATURE_EDX_SYSCALL
3166 | RT_BIT(18)
3167 | RT_BIT(19)
3168 | RT_BIT(21)
3169 | X86_CPUID_AMD_FEATURE_EDX_AXMMX
3170 | X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
3171 | RT_BIT(28)
3172 )));
3173 }
3174
3175 /* Force extended feature bits. */
3176 if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
3177 pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_ABM;
3178 if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
3179 pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
3180 if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
3181 pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
3182 if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
3183 pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
3184 if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
3185 pExtFeatureLeaf->uEdx |= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
3186 }
3187 pExtFeatureLeaf = NULL; /* Must refetch! */
3188
3189
3190 /* Cpuid 2:
3191 * Intel: (Nondeterministic) Cache and TLB information
3192 * AMD: Reserved
3193 * VIA: Reserved
3194 * Safe to expose.
3195 */
3196 uint32_t uSubLeaf = 0;
3197 PCPUMCPUIDLEAF pCurLeaf;
3198 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
3199 {
3200 if ((pCurLeaf->uEax & 0xff) > 1)
3201 {
3202 LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
3203 pCurLeaf->uEax &= UINT32_C(0xffffff01);
3204 }
3205 uSubLeaf++;
3206 }
3207
3208 /* Cpuid 3:
3209 * Intel: EAX, EBX - reserved (transmeta uses these)
3210 * ECX, EDX - Processor Serial Number if available, otherwise reserved
3211 * AMD: Reserved
3212 * VIA: Reserved
3213 * Safe to expose
3214 */
3215 pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3216 if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3217 {
3218 uSubLeaf = 0;
3219 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3220 {
3221 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3222 if (pCpum->u8PortableCpuIdLevel > 0)
3223 pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3224 uSubLeaf++;
3225 }
3226 }
3227
3228 /* Cpuid 4 + ECX:
3229 * Intel: Deterministic Cache Parameters Leaf.
3230 * AMD: Reserved
3231 * VIA: Reserved
3232 * Safe to expose, except for EAX:
3233 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3234 * Bits 31-26: Maximum number of processor cores in this physical package**
3235 * Note: These SMP values are constant regardless of ECX
3236 */
3237 uSubLeaf = 0;
3238 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3239 {
3240 pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3241#ifdef VBOX_WITH_MULTI_CORE
3242 if ( pVM->cCpus > 1
3243 && pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3244 {
3245 AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3246 /* One logical processor with possibly multiple cores. */
3247 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3248 pCurLeaf->uEax |= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3249 }
3250#endif
3251 uSubLeaf++;
3252 }
3253
3254 /* Cpuid 5: Monitor/mwait Leaf
3255 * Intel: ECX, EDX - reserved
3256 * EAX, EBX - Smallest and largest monitor line size
3257 * AMD: EDX - reserved
3258 * EAX, EBX - Smallest and largest monitor line size
3259 * ECX - extensions (ignored for now)
3260 * VIA: Reserved
3261 * Safe to expose
3262 */
3263 uSubLeaf = 0;
3264 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3265 {
3266 pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3267 if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3268 pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3269
3270 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3271 if (pConfig->enmMWaitExtensions)
3272 {
3273 pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3274 /** @todo for now we just expose host's MWAIT C-states, although conceptually
3275 it shall be part of our power management virtualization model */
3276#if 0
3277 /* MWAIT sub C-states */
3278 pCurLeaf->uEdx =
3279 (0 << 0) /* 0 in C0 */ |
3280 (2 << 4) /* 2 in C1 */ |
3281 (2 << 8) /* 2 in C2 */ |
3282 (2 << 12) /* 2 in C3 */ |
3283 (0 << 16) /* 0 in C4 */
3284 ;
3285#endif
3286 }
3287 else
3288 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3289 uSubLeaf++;
3290 }
3291
3292 /* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3293 * Intel: Various stuff.
3294 * AMD: EAX, EBX, EDX - reserved.
3295 * ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3296 * present. Same as intel.
3297 * VIA: ??
3298 *
3299 * We clear everything here for now.
3300 */
3301 cpumR3CpuIdZeroLeaf(pCpum, 6);
3302
3303 /* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3304 * EAX: Number of sub leaves.
3305 * EBX+ECX+EDX: Feature flags
3306 *
3307 * We only have documentation for one sub-leaf, so clear all other (no need
3308 * to remove them as such, just set them to zero).
3309 *
3310 * Note! When enabling new features the Synthetic CPU and Portable CPUID
3311 * options may require adjusting (i.e. stripping what was enabled).
3312 */
3313 uSubLeaf = 0;
3314 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3315 {
3316 switch (uSubLeaf)
3317 {
3318 case 0:
3319 {
3320 pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3321 pCurLeaf->uEbx &= 0
3322 | PASSTHRU_FEATURE(pConfig->enmFsGsBase, pHstFeat->fFsGsBase, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE)
3323 //| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3324 //| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3325 //| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3326 //| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3327 | PASSTHRU_FEATURE(pConfig->enmAvx2, pHstFeat->fAvx2, X86_CPUID_STEXT_FEATURE_EBX_AVX2)
3328 | X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3329 //| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3330 //| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3331 //| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3332 | PASSTHRU_FEATURE(pConfig->enmInvpcid, pHstFeat->fInvpcid, X86_CPUID_STEXT_FEATURE_EBX_INVPCID)
3333 //| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3334 //| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3335 | X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3336 //| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3337 //| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3338 //| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3339 //| RT_BIT(17) - reserved
3340 | PASSTHRU_FEATURE_TODO(pConfig->enmRdSeed, X86_CPUID_STEXT_FEATURE_EBX_RDSEED)
3341 //| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3342 //| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3343 //| RT_BIT(21) - reserved
3344 //| RT_BIT(22) - reserved
3345 | PASSTHRU_FEATURE(pConfig->enmCLFlushOpt, pHstFeat->fClFlushOpt, X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT)
3346 //| RT_BIT(24) - reserved
3347 //| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3348 //| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3349 //| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3350 //| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3351 //| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3352 //| RT_BIT(30) - reserved
3353 //| RT_BIT(31) - reserved
3354 ;
3355 pCurLeaf->uEcx &= 0
3356 //| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3357 ;
3358 pCurLeaf->uEdx &= 0
3359 | PASSTHRU_FEATURE(pConfig->enmMdsClear, pHstFeat->fMdsClear, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR)
3360 //| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3361 //| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3362 | PASSTHRU_FEATURE(pConfig->enmFlushCmdMsr, pHstFeat->fFlushCmd, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD)
3363 | PASSTHRU_FEATURE(pConfig->enmArchCapMsr, pHstFeat->fArchCap, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
3364 ;
3365
3366 /* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3367 if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3368 && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3369 {
3370 pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3371 LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3372 }
3373
3374 if (pCpum->u8PortableCpuIdLevel > 0)
3375 {
3376 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3377 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3378 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3379 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3380 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3381 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3382 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3383 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3384 PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3385 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3386 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3387 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3388 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3389 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3390 PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3391 PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
3392 PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
3393 PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
3394 }
3395
3396 /* Dependencies. */
3397 if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
3398 pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3399
3400 /* Force standard feature bits. */
3401 if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3402 pCurLeaf->uEbx |= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3403 if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3404 pCurLeaf->uEbx |= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3405 if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3406 pCurLeaf->uEbx |= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3407 if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3408 pCurLeaf->uEbx |= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3409 if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3410 pCurLeaf->uEbx |= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3411 if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3412 pCurLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
3413 if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
3414 pCurLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
3415 if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
3416 pCurLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
3417 break;
3418 }
3419
3420 default:
3421 /* Invalid index, all values are zero. */
3422 pCurLeaf->uEax = 0;
3423 pCurLeaf->uEbx = 0;
3424 pCurLeaf->uEcx = 0;
3425 pCurLeaf->uEdx = 0;
3426 break;
3427 }
3428 uSubLeaf++;
3429 }
3430
3431 /* Cpuid 8: Marked as reserved by Intel and AMD.
3432 * We zero this since we don't know what it may have been used for.
3433 */
3434 cpumR3CpuIdZeroLeaf(pCpum, 8);
3435
3436 /* Cpuid 9: Direct Cache Access (DCA) Parameters
3437 * Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3438 * EBX, ECX, EDX - reserved.
3439 * AMD: Reserved
3440 * VIA: ??
3441 *
3442 * We zero this.
3443 */
3444 cpumR3CpuIdZeroLeaf(pCpum, 9);
3445
3446 /* Cpuid 0xa: Architectural Performance Monitor Features
3447 * Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3448 * EBX, ECX, EDX - reserved.
3449 * AMD: Reserved
3450 * VIA: ??
3451 *
3452 * We zero this, for now at least.
3453 */
3454 cpumR3CpuIdZeroLeaf(pCpum, 10);
3455
3456 /* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3457 * Intel: EAX - APCI ID shift right for next level.
3458 * EBX - Factory configured cores/threads at this level.
3459 * ECX - Level number (same as input) and level type (1,2,0).
3460 * EDX - Extended initial APIC ID.
3461 * AMD: Reserved
3462 * VIA: ??
3463 */
3464 uSubLeaf = 0;
3465 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3466 {
3467 if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3468 {
3469 uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3470 if (bLevelType == 1)
3471 {
3472 /* Thread level - we don't do threads at the moment. */
3473 pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3474 pCurLeaf->uEbx = 1;
3475 }
3476 else if (bLevelType == 2)
3477 {
3478 /* Core level. */
3479 pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3480#ifdef VBOX_WITH_MULTI_CORE
3481 while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3482 pCurLeaf->uEax++;
3483#endif
3484 pCurLeaf->uEbx = pVM->cCpus;
3485 }
3486 else
3487 {
3488 AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3489 pCurLeaf->uEax = 0;
3490 pCurLeaf->uEbx = 0;
3491 pCurLeaf->uEcx = 0;
3492 }
3493 pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) | (uSubLeaf & 0xff);
3494 pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3495 }
3496 else
3497 {
3498 pCurLeaf->uEax = 0;
3499 pCurLeaf->uEbx = 0;
3500 pCurLeaf->uEcx = 0;
3501 pCurLeaf->uEdx = 0;
3502 }
3503 uSubLeaf++;
3504 }
3505
3506 /* Cpuid 0xc: Marked as reserved by Intel and AMD.
3507 * We zero this since we don't know what it may have been used for.
3508 */
3509 cpumR3CpuIdZeroLeaf(pCpum, 12);
3510
3511 /* Cpuid 0xd + ECX: Processor Extended State Enumeration
3512 * ECX=0: EAX - Valid bits in XCR0[31:0].
3513 * EBX - Maximum state size as per current XCR0 value.
3514 * ECX - Maximum state size for all supported features.
3515 * EDX - Valid bits in XCR0[63:32].
3516 * ECX=1: EAX - Various X-features.
3517 * EBX - Maximum state size as per current XCR0|IA32_XSS value.
3518 * ECX - Valid bits in IA32_XSS[31:0].
3519 * EDX - Valid bits in IA32_XSS[63:32].
3520 * ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3521 * if the bit invalid all four registers are set to zero.
3522 * EAX - The state size for this feature.
3523 * EBX - The state byte offset of this feature.
3524 * ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3525 * EDX - Reserved, but is set to zero if invalid sub-leaf index.
3526 *
3527 * Clear them all as we don't currently implement extended CPU state.
3528 */
3529 /* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3530 uint64_t fGuestXcr0Mask = 0;
3531 pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3532 if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3533 {
3534 fGuestXcr0Mask = XSAVE_C_X87 | XSAVE_C_SSE;
3535 if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3536 fGuestXcr0Mask |= XSAVE_C_YMM;
3537 pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3538 if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3539 fGuestXcr0Mask |= XSAVE_C_ZMM_16HI | XSAVE_C_ZMM_HI256 | XSAVE_C_OPMASK;
3540 fGuestXcr0Mask &= pCpum->fXStateHostMask;
3541
3542 pStdFeatureLeaf->fFlags |= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3543 }
3544 pStdFeatureLeaf = NULL;
3545 pCpum->fXStateGuestMask = fGuestXcr0Mask;
3546
3547 /* Work the sub-leaves. */
3548 uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3549 uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3550 for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3551 {
3552 pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3553 if (pCurLeaf)
3554 {
3555 if (fGuestXcr0Mask)
3556 {
3557 switch (uSubLeaf)
3558 {
3559 case 0:
3560 pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3561 pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3562 AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 | XSAVE_C_SSE)) == (XSAVE_C_X87 | XSAVE_C_SSE),
3563 ("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3564 VERR_CPUM_IPE_1);
3565 cbXSaveMaxActual = pCurLeaf->uEcx;
3566 AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3567 ("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3568 AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3569 ("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3570 VERR_CPUM_IPE_2);
3571 continue;
3572 case 1:
3573 pCurLeaf->uEax &= 0;
3574 pCurLeaf->uEcx &= 0;
3575 pCurLeaf->uEdx &= 0;
3576 /** @todo what about checking ebx? */
3577 continue;
3578 default:
3579 if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3580 {
3581 AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3582 && pCurLeaf->uEax > 0
3583 && pCurLeaf->uEbx < cbXSaveMaxActual
3584 && pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3585 && pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3586 ("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3587 uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3588 VERR_CPUM_IPE_2);
3589 AssertLogRel(!(pCurLeaf->uEcx & 1));
3590 pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3591 pCurLeaf->uEdx = 0; /* it's reserved... */
3592 if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3593 cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3594 continue;
3595 }
3596 break;
3597 }
3598 }
3599
3600 /* Clear the leaf. */
3601 pCurLeaf->uEax = 0;
3602 pCurLeaf->uEbx = 0;
3603 pCurLeaf->uEcx = 0;
3604 pCurLeaf->uEdx = 0;
3605 }
3606 }
3607
3608 /* Update the max and current feature sizes to shut up annoying Linux kernels. */
3609 if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3610 {
3611 pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3612 if (pCurLeaf)
3613 {
3614 LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3615 pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3616 pCurLeaf->uEbx = cbXSaveMaxReport;
3617 pCurLeaf->uEcx = cbXSaveMaxReport;
3618 }
3619 }
3620
3621 /* Cpuid 0xe: Marked as reserved by Intel and AMD.
3622 * We zero this since we don't know what it may have been used for.
3623 */
3624 cpumR3CpuIdZeroLeaf(pCpum, 14);
3625
3626 /* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3627 * also known as Intel Resource Director Technology (RDT) Monitoring
3628 * We zero this as we don't currently virtualize PQM.
3629 */
3630 cpumR3CpuIdZeroLeaf(pCpum, 15);
3631
3632 /* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3633 * also known as Intel Resource Director Technology (RDT) Allocation
3634 * We zero this as we don't currently virtualize PQE.
3635 */
3636 cpumR3CpuIdZeroLeaf(pCpum, 16);
3637
3638 /* Cpuid 0x11: Marked as reserved by Intel and AMD.
3639 * We zero this since we don't know what it may have been used for.
3640 */
3641 cpumR3CpuIdZeroLeaf(pCpum, 17);
3642
3643 /* Cpuid 0x12 + ECX: SGX resource enumeration.
3644 * We zero this as we don't currently virtualize this.
3645 */
3646 cpumR3CpuIdZeroLeaf(pCpum, 18);
3647
3648 /* Cpuid 0x13: Marked as reserved by Intel and AMD.
3649 * We zero this since we don't know what it may have been used for.
3650 */
3651 cpumR3CpuIdZeroLeaf(pCpum, 19);
3652
3653 /* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3654 * We zero this as we don't currently virtualize this.
3655 */
3656 cpumR3CpuIdZeroLeaf(pCpum, 20);
3657
3658 /* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3659 * Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3660 * EAX - denominator (unsigned).
3661 * EBX - numerator (unsigned).
3662 * ECX, EDX - reserved.
3663 * AMD: Reserved / undefined / not implemented.
3664 * VIA: Reserved / undefined / not implemented.
3665 * We zero this as we don't currently virtualize this.
3666 */
3667 cpumR3CpuIdZeroLeaf(pCpum, 21);
3668
3669 /* Cpuid 0x16: Processor frequency info
3670 * Intel: EAX - Core base frequency in MHz.
3671 * EBX - Core maximum frequency in MHz.
3672 * ECX - Bus (reference) frequency in MHz.
3673 * EDX - Reserved.
3674 * AMD: Reserved / undefined / not implemented.
3675 * VIA: Reserved / undefined / not implemented.
3676 * We zero this as we don't currently virtualize this.
3677 */
3678 cpumR3CpuIdZeroLeaf(pCpum, 22);
3679
3680 /* Cpuid 0x17..0x10000000: Unknown.
3681 * We don't know these and what they mean, so remove them. */
3682 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3683 UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3684
3685
3686 /* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3687 * We remove all these as we're a hypervisor and must provide our own.
3688 */
3689 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3690 UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3691
3692
3693 /* Cpuid 0x80000000 is harmless. */
3694
3695 /* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3696
3697 /* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3698
3699 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3700 * Safe to pass on to the guest.
3701 *
3702 * AMD: 0x800000005 L1 cache information
3703 * 0x800000006 L2/L3 cache information
3704 * Intel: 0x800000005 reserved
3705 * 0x800000006 L2 cache information
3706 * VIA: 0x800000005 TLB and L1 cache information
3707 * 0x800000006 L2 cache information
3708 */
3709
3710 /* Cpuid 0x800000007: Advanced Power Management Information.
3711 * AMD: EAX: Processor feedback capabilities.
3712 * EBX: RAS capabilites.
3713 * ECX: Advanced power monitoring interface.
3714 * EDX: Enhanced power management capabilities.
3715 * Intel: EAX, EBX, ECX - reserved.
3716 * EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3717 * VIA: Reserved
3718 * We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3719 */
3720 uSubLeaf = 0;
3721 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3722 {
3723 pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3724 if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3725 || pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3726 {
3727 /*
3728 * Older 64-bit linux kernels blindly assume that the AMD performance counters work
3729 * if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3730 * bit is now configurable.
3731 */
3732 pCurLeaf->uEdx &= 0
3733 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
3734 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
3735 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
3736 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3737 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
3738 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
3739 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
3740 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3741 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3742 //| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3743 //| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3744 //| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3745 //| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3746 | 0;
3747 }
3748 else
3749 pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3750 if (!pConfig->fInvariantTsc)
3751 pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3752 uSubLeaf++;
3753 }
3754
3755 /* Cpuid 0x80000008:
3756 * AMD: EBX, EDX - reserved
3757 * EAX: Virtual/Physical/Guest address Size
3758 * ECX: Number of cores + APICIdCoreIdSize
3759 * Intel: EAX: Virtual/Physical address Size
3760 * EBX, ECX, EDX - reserved
3761 * VIA: EAX: Virtual/Physical address Size
3762 * EBX, ECX, EDX - reserved
3763 *
3764 * We only expose the virtual+pysical address size to the guest atm.
3765 * On AMD we set the core count, but not the apic id stuff as we're
3766 * currently not doing the apic id assignments in a complatible manner.
3767 */
3768 uSubLeaf = 0;
3769 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3770 {
3771 pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3772 pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3773 pCurLeaf->uEdx = 0; /* reserved */
3774
3775 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3776 * Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3777 pCurLeaf->uEcx = 0;
3778#ifdef VBOX_WITH_MULTI_CORE
3779 if ( pVM->cCpus > 1
3780 && ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3781 || pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3782 pCurLeaf->uEcx |= (pVM->cCpus - 1) & UINT32_C(0xff);
3783#endif
3784 uSubLeaf++;
3785 }
3786
3787 /* Cpuid 0x80000009: Reserved
3788 * We zero this since we don't know what it may have been used for.
3789 */
3790 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3791
3792 /* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
3793 * AMD: EAX - SVM revision.
3794 * EBX - Number of ASIDs.
3795 * ECX - Reserved.
3796 * EDX - SVM Feature identification.
3797 */
3798 if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3799 || pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3800 {
3801 pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3802 if ( pExtFeatureLeaf
3803 && (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
3804 {
3805 PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3806 if (pSvmFeatureLeaf)
3807 {
3808 pSvmFeatureLeaf->uEax = 0x1;
3809 pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3810 pSvmFeatureLeaf->uEcx = 0;
3811 pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3812 | X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3813 | X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3814 }
3815 else
3816 {
3817 /* Should never happen. */
3818 LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
3819 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3820 }
3821 }
3822 else
3823 {
3824 /* If SVM is not supported, this is reserved, zero out. */
3825 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3826 }
3827 }
3828 else
3829 {
3830 /* Cpuid 0x8000000a: Reserved on Intel.
3831 * We zero this since we don't know what it may have been used for.
3832 */
3833 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3834 }
3835
3836 /* Cpuid 0x8000000b thru 0x80000018: Reserved
3837 * We clear these as we don't know what purpose they might have. */
3838 for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3839 cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3840
3841 /* Cpuid 0x80000019: TLB configuration
3842 * Seems to be harmless, pass them thru as is. */
3843
3844 /* Cpuid 0x8000001a: Peformance optimization identifiers.
3845 * Strip anything we don't know what is or addresses feature we don't implement. */
3846 uSubLeaf = 0;
3847 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3848 {
3849 pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3850 | RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3851 //| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3852 ;
3853 pCurLeaf->uEbx = 0; /* reserved */
3854 pCurLeaf->uEcx = 0; /* reserved */
3855 pCurLeaf->uEdx = 0; /* reserved */
3856 uSubLeaf++;
3857 }
3858
3859 /* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3860 * Clear this as we don't currently virtualize this feature. */
3861 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3862
3863 /* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3864 * Clear this as we don't currently virtualize this feature. */
3865 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3866
3867 /* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3868 * We need to sanitize the cores per cache (EAX[25:14]).
3869 *
3870 * This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3871 * and EDX[2] are reserved here, and EAX[14:25] is documented having a
3872 * slightly different meaning.
3873 */
3874 uSubLeaf = 0;
3875 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3876 {
3877#ifdef VBOX_WITH_MULTI_CORE
3878 uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3879 if (cCores > pVM->cCpus)
3880 cCores = pVM->cCpus;
3881 pCurLeaf->uEax &= UINT32_C(0x00003fff);
3882 pCurLeaf->uEax |= ((cCores - 1) & 0xfff) << 14;
3883#else
3884 pCurLeaf->uEax &= UINT32_C(0x00003fff);
3885#endif
3886 uSubLeaf++;
3887 }
3888
3889 /* Cpuid 0x8000001e: Get APIC / unit / node information.
3890 * If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3891 * setup, we have one compute unit with all the cores in it. Single node.
3892 */
3893 uSubLeaf = 0;
3894 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3895 {
3896 pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3897 if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3898 {
3899#ifdef VBOX_WITH_MULTI_CORE
3900 pCurLeaf->uEbx = pVM->cCpus < 0x100
3901 ? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3902#else
3903 pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3904#endif
3905 pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3906 }
3907 else
3908 {
3909 Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3910 Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_HYGON);
3911 pCurLeaf->uEbx = 0; /* Reserved. */
3912 pCurLeaf->uEcx = 0; /* Reserved. */
3913 }
3914 pCurLeaf->uEdx = 0; /* Reserved. */
3915 uSubLeaf++;
3916 }
3917
3918 /* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3919 * We don't know these and what they mean, so remove them. */
3920 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3921 UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3922
3923 /* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3924 * Just pass it thru for now. */
3925
3926 /* Cpuid 0x8fffffff: Mystery hammer time leaf!
3927 * Just pass it thru for now. */
3928
3929 /* Cpuid 0xc0000000: Centaur stuff.
3930 * Harmless, pass it thru. */
3931
3932 /* Cpuid 0xc0000001: Centaur features.
3933 * VIA: EAX - Family, model, stepping.
3934 * EDX - Centaur extended feature flags. Nothing interesting, except may
3935 * FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3936 * EBX, ECX - reserved.
3937 * We keep EAX but strips the rest.
3938 */
3939 uSubLeaf = 0;
3940 while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3941 {
3942 pCurLeaf->uEbx = 0;
3943 pCurLeaf->uEcx = 0;
3944 pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3945 uSubLeaf++;
3946 }
3947
3948 /* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3949 * We only have fixed stale values, but should be harmless. */
3950
3951 /* Cpuid 0xc0000003: Reserved.
3952 * We zero this since we don't know what it may have been used for.
3953 */
3954 cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3955
3956 /* Cpuid 0xc0000004: Centaur Performance Info.
3957 * We only have fixed stale values, but should be harmless. */
3958
3959
3960 /* Cpuid 0xc0000005...0xcfffffff: Unknown.
3961 * We don't know these and what they mean, so remove them. */
3962 cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3963 UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3964
3965 return VINF_SUCCESS;
3966#undef PORTABLE_DISABLE_FEATURE_BIT
3967#undef PORTABLE_CLEAR_BITS_WHEN
3968}
3969
3970
3971/**
3972 * Reads a value in /CPUM/IsaExts/ node.
3973 *
3974 * @returns VBox status code (error message raised).
3975 * @param pVM The cross context VM structure. (For errors.)
3976 * @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3977 * @param pszValueName The value / extension name.
3978 * @param penmValue Where to return the choice.
3979 * @param enmDefault The default choice.
3980 */
3981static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3982 CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3983{
3984 /*
3985 * Try integer encoding first.
3986 */
3987 uint64_t uValue;
3988 int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3989 if (RT_SUCCESS(rc))
3990 switch (uValue)
3991 {
3992 case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3993 case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3994 case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3995 case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3996 default:
3997 return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3998 "Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3999 pszValueName, uValue);
4000 }
4001 /*
4002 * If missing, use default.
4003 */
4004 else if (rc == VERR_CFGM_VALUE_NOT_FOUND || rc == VERR_CFGM_NO_PARENT)
4005 *penmValue = enmDefault;
4006 else
4007 {
4008 if (rc == VERR_CFGM_NOT_INTEGER)
4009 {
4010 /*
4011 * Not an integer, try read it as a string.
4012 */
4013 char szValue[32];
4014 rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
4015 if (RT_SUCCESS(rc))
4016 {
4017 RTStrToLower(szValue);
4018 size_t cchValue = strlen(szValue);
4019#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
4020 if ( EQ("disabled") || EQ("disable") || EQ("off") || EQ("no"))
4021 *penmValue = CPUMISAEXTCFG_DISABLED;
4022 else if (EQ("enabled") || EQ("enable") || EQ("on") || EQ("yes"))
4023 *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
4024 else if (EQ("forced") || EQ("force") || EQ("always"))
4025 *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
4026 else if (EQ("portable"))
4027 *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
4028 else if (EQ("default") || EQ("def"))
4029 *penmValue = enmDefault;
4030 else
4031 return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
4032 "Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
4033 pszValueName, uValue);
4034#undef EQ
4035 }
4036 }
4037 if (RT_FAILURE(rc))
4038 return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
4039 }
4040 return VINF_SUCCESS;
4041}
4042
4043
4044/**
4045 * Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
4046 *
4047 * @returns VBox status code (error message raised).
4048 * @param pVM The cross context VM structure. (For errors.)
4049 * @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4050 * @param pszValueName The value / extension name.
4051 * @param penmValue Where to return the choice.
4052 * @param enmDefault The default choice.
4053 * @param fAllowed Allowed choice. Applied both to the result and to
4054 * the default value.
4055 */
4056static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
4057 CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
4058{
4059 int rc;
4060 if (fAllowed)
4061 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4062 else
4063 {
4064 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /*enmDefault*/);
4065 if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
4066 LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
4067 *penmValue = CPUMISAEXTCFG_DISABLED;
4068 }
4069 return rc;
4070}
4071
4072
4073/**
4074 * Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
4075 *
4076 * @returns VBox status code (error message raised).
4077 * @param pVM The cross context VM structure. (For errors.)
4078 * @param pIsaExts The /CPUM/IsaExts node (can be NULL).
4079 * @param pCpumCfg The /CPUM node (can be NULL).
4080 * @param pszValueName The value / extension name.
4081 * @param penmValue Where to return the choice.
4082 * @param enmDefault The default choice.
4083 */
4084static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
4085 CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
4086{
4087 if (CFGMR3Exists(pCpumCfg, pszValueName))
4088 {
4089 if (!CFGMR3Exists(pIsaExts, pszValueName))
4090 LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
4091 else
4092 return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
4093 "Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
4094 pszValueName, pszValueName);
4095
4096 bool fLegacy;
4097 int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
4098 if (RT_SUCCESS(rc))
4099 {
4100 *penmValue = fLegacy;
4101 return VINF_SUCCESS;
4102 }
4103 return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
4104 }
4105
4106 return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
4107}
4108
4109
4110static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
4111{
4112 int rc;
4113
4114 /** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
4115 * When non-zero CPUID features that could cause portability issues will be
4116 * stripped. The higher the value the more features gets stripped. Higher
4117 * values should only be used when older CPUs are involved since it may
4118 * harm performance and maybe also cause problems with specific guests. */
4119 rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
4120 AssertLogRelRCReturn(rc, rc);
4121
4122 /** @cfgm{/CPUM/GuestCpuName, string}
4123 * The name of the CPU we're to emulate. The default is the host CPU.
4124 * Note! CPUs other than "host" one is currently unsupported. */
4125 rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
4126 AssertLogRelRCReturn(rc, rc);
4127
4128 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
4129 * Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
4130 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
4131 * This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
4132 */
4133 rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
4134 AssertLogRelRCReturn(rc, rc);
4135
4136 /** @cfgm{/CPUM/InvariantTsc, boolean, true}
4137 * Pass-through the invariant TSC flag in 0x80000007 if available on the host
4138 * CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
4139 * 64-bit linux guests which assume the presence of AMD performance counters
4140 * that we do not virtualize.
4141 */
4142 rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
4143 AssertLogRelRCReturn(rc, rc);
4144
4145 /** @cfgm{/CPUM/ForceVme, boolean, false}
4146 * Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
4147 * By default the flag is passed thru as is from the host CPU, except
4148 * on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
4149 * guests and DOS boxes in general.
4150 */
4151 rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
4152 AssertLogRelRCReturn(rc, rc);
4153
4154 /** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
4155 * Restrict the reported CPU family+model+stepping of intel CPUs. This is
4156 * probably going to be a temporary hack, so don't depend on this.
4157 * The 1st byte of the value is the stepping, the 2nd byte value is the model
4158 * number and the 3rd byte value is the family, and the 4th value must be zero.
4159 */
4160 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
4161 AssertLogRelRCReturn(rc, rc);
4162
4163 /** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
4164 * The last standard leaf to keep. The actual last value that is stored in EAX
4165 * is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
4166 * removed. (This works independently of and differently from NT4LeafLimit.)
4167 * The default is usually set to what we're able to reasonably sanitize.
4168 */
4169 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
4170 AssertLogRelRCReturn(rc, rc);
4171
4172 /** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
4173 * The last extended leaf to keep. The actual last value that is stored in EAX
4174 * is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
4175 * leaf are removed. The default is set to what we're able to sanitize.
4176 */
4177 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
4178 AssertLogRelRCReturn(rc, rc);
4179
4180 /** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
4181 * The last extended leaf to keep. The actual last value that is stored in EAX
4182 * is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
4183 * leaf are removed. The default is set to what we're able to sanitize.
4184 */
4185 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
4186 AssertLogRelRCReturn(rc, rc);
4187
4188 bool fQueryNestedHwvirt = false
4189#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4190 || pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4191 || pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON
4192#endif
4193#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4194 || pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
4195 || pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA
4196#endif
4197 ;
4198 if (fQueryNestedHwvirt)
4199 {
4200 /** @cfgm{/CPUM/NestedHWVirt, bool, false}
4201 * Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
4202 * The default is false, and when enabled requires a 64-bit CPU with support for
4203 * nested-paging and AMD-V or unrestricted guest mode.
4204 */
4205 rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
4206 AssertLogRelRCReturn(rc, rc);
4207 if (pConfig->fNestedHWVirt)
4208 {
4209 /** @todo Think about enabling this later with NEM/KVM. */
4210 if (VM_IS_NEM_ENABLED(pVM))
4211 {
4212 LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
4213 pConfig->fNestedHWVirt = false;
4214 }
4215 else if (!fNestedPagingAndFullGuestExec)
4216 return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
4217 "Cannot enable nested VT-x/AMD-V without nested-paging and unrestricted guest execution!\n");
4218 }
4219
4220 if (pConfig->fNestedHWVirt)
4221 {
4222 /** @cfgm{/CPUM/NestedVmxPreemptTimer, bool, true}
4223 * Whether to expose the VMX-preemption timer feature to the guest (if also
4224 * supported by the host hardware). When disabled will prevent exposing the
4225 * VMX-preemption timer feature to the guest even if the host supports it.
4226 *
4227 * @todo Currently disabled, see @bugref{9180#c108}.
4228 */
4229 rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxPreemptTimer", &pVM->cpum.s.fNestedVmxPreemptTimer, false);
4230 AssertLogRelRCReturn(rc, rc);
4231
4232 /** @cfgm{/CPUM/NestedVmxEpt, bool, true}
4233 * Whether to expose the EPT feature to the guest. The default is false. When
4234 * disabled will automatically prevent exposing features that rely on
4235 */
4236 rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxEpt", &pVM->cpum.s.fNestedVmxEpt, false);
4237 AssertLogRelRCReturn(rc, rc);
4238
4239 /** @cfgm{/CPUM/NestedVmxUnrestrictedGuest, bool, true}
4240 * Whether to expose the Unrestricted Guest feature to the guest. The default is
4241 * false. When disabled will automatically prevent exposing features that rely on
4242 * it.
4243 */
4244 rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxUnrestrictedGuest", &pVM->cpum.s.fNestedVmxUnrestrictedGuest, false);
4245 AssertLogRelRCReturn(rc, rc);
4246
4247 if ( pVM->cpum.s.fNestedVmxUnrestrictedGuest
4248 && !pVM->cpum.s.fNestedVmxEpt)
4249 {
4250 LogRel(("CPUM: WARNING! Can't expose \"Unrestricted Guest\" to the guest when EPT is not exposed!\n"));
4251 pVM->cpum.s.fNestedVmxUnrestrictedGuest = false;
4252 }
4253 }
4254 }
4255
4256 /*
4257 * Instruction Set Architecture (ISA) Extensions.
4258 */
4259 PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
4260 if (pIsaExts)
4261 {
4262 rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
4263 "CMPXCHG16B"
4264 "|MONITOR"
4265 "|MWaitExtensions"
4266 "|SSE4.1"
4267 "|SSE4.2"
4268 "|XSAVE"
4269 "|AVX"
4270 "|AVX2"
4271 "|AESNI"
4272 "|PCLMUL"
4273 "|POPCNT"
4274 "|MOVBE"
4275 "|RDRAND"
4276 "|RDSEED"
4277 "|CLFLUSHOPT"
4278 "|FSGSBASE"
4279 "|PCID"
4280 "|INVPCID"
4281 "|FlushCmdMsr"
4282 "|ABM"
4283 "|SSE4A"
4284 "|MISALNSSE"
4285 "|3DNOWPRF"
4286 "|AXMMX"
4287 , "" /*pszValidNodes*/, "CPUM" /*pszWho*/, 0 /*uInstance*/);
4288 if (RT_FAILURE(rc))
4289 return rc;
4290 }
4291
4292 /** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, true}
4293 * Expose CMPXCHG16B to the guest if available. All host CPUs which support
4294 * hardware virtualization have it.
4295 */
4296 rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, true);
4297 AssertLogRelRCReturn(rc, rc);
4298
4299 /** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4300 * Expose MONITOR/MWAIT instructions to the guest.
4301 */
4302 rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4303 AssertLogRelRCReturn(rc, rc);
4304
4305 /** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4306 * Expose MWAIT extended features to the guest. For now we expose just MWAIT
4307 * break on interrupt feature (bit 1).
4308 */
4309 rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4310 AssertLogRelRCReturn(rc, rc);
4311
4312 /** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4313 * Expose SSE4.1 to the guest if available.
4314 */
4315 rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4316 AssertLogRelRCReturn(rc, rc);
4317
4318 /** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4319 * Expose SSE4.2 to the guest if available.
4320 */
4321 rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4322 AssertLogRelRCReturn(rc, rc);
4323
4324 bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4325 && pVM->cpum.s.HostFeatures.fXSaveRstor
4326 && pVM->cpum.s.HostFeatures.fOpSysXSaveRstor;
4327 uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4328
4329 /** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4330 * Expose XSAVE/XRSTOR to the guest if available. For the time being the
4331 * default is to only expose this to VMs with nested paging and AMD-V or
4332 * unrestricted guest execution mode. Not possible to force this one without
4333 * host support at the moment.
4334 */
4335 rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4336 fMayHaveXSave /*fAllowed*/);
4337 AssertLogRelRCReturn(rc, rc);
4338
4339 /** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4340 * Expose the AVX instruction set extensions to the guest if available and
4341 * XSAVE is exposed too. For the time being the default is to only expose this
4342 * to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4343 */
4344 rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4345 fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /*fAllowed*/);
4346 AssertLogRelRCReturn(rc, rc);
4347
4348 /** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4349 * Expose the AVX2 instruction set extensions to the guest if available and
4350 * XSAVE is exposed too. For the time being the default is to only expose this
4351 * to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4352 */
4353 rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4354 fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /*fAllowed*/);
4355 AssertLogRelRCReturn(rc, rc);
4356
4357 /** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4358 * Whether to expose the AES instructions to the guest. For the time being the
4359 * default is to only do this for VMs with nested paging and AMD-V or
4360 * unrestricted guest mode.
4361 */
4362 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4363 AssertLogRelRCReturn(rc, rc);
4364
4365 /** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4366 * Whether to expose the PCLMULQDQ instructions to the guest. For the time
4367 * being the default is to only do this for VMs with nested paging and AMD-V or
4368 * unrestricted guest mode.
4369 */
4370 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4371 AssertLogRelRCReturn(rc, rc);
4372
4373 /** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4374 * Whether to expose the POPCNT instructions to the guest. For the time
4375 * being the default is to only do this for VMs with nested paging and AMD-V or
4376 * unrestricted guest mode.
4377 */
4378 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4379 AssertLogRelRCReturn(rc, rc);
4380
4381 /** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4382 * Whether to expose the MOVBE instructions to the guest. For the time
4383 * being the default is to only do this for VMs with nested paging and AMD-V or
4384 * unrestricted guest mode.
4385 */
4386 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4387 AssertLogRelRCReturn(rc, rc);
4388
4389 /** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4390 * Whether to expose the RDRAND instructions to the guest. For the time being
4391 * the default is to only do this for VMs with nested paging and AMD-V or
4392 * unrestricted guest mode.
4393 */
4394 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4395 AssertLogRelRCReturn(rc, rc);
4396
4397 /** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4398 * Whether to expose the RDSEED instructions to the guest. For the time being
4399 * the default is to only do this for VMs with nested paging and AMD-V or
4400 * unrestricted guest mode.
4401 */
4402 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4403 AssertLogRelRCReturn(rc, rc);
4404
4405 /** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4406 * Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4407 * being the default is to only do this for VMs with nested paging and AMD-V or
4408 * unrestricted guest mode.
4409 */
4410 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4411 AssertLogRelRCReturn(rc, rc);
4412
4413 /** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4414 * Whether to expose the read/write FSGSBASE instructions to the guest.
4415 */
4416 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4417 AssertLogRelRCReturn(rc, rc);
4418
4419 /** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4420 * Whether to expose the PCID feature to the guest.
4421 */
4422 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4423 AssertLogRelRCReturn(rc, rc);
4424
4425 /** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4426 * Whether to expose the INVPCID instruction to the guest.
4427 */
4428 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4429 AssertLogRelRCReturn(rc, rc);
4430
4431 /** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
4432 * Whether to expose the IA32_FLUSH_CMD MSR to the guest.
4433 */
4434 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4435 AssertLogRelRCReturn(rc, rc);
4436
4437 /** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
4438 * Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
4439 * the guest. Requires FlushCmdMsr to be present too.
4440 */
4441 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4442 AssertLogRelRCReturn(rc, rc);
4443
4444 /** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
4445 * Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
4446 */
4447 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
4448 AssertLogRelRCReturn(rc, rc);
4449
4450
4451 /* AMD: */
4452
4453 /** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4454 * Whether to expose the AMD ABM instructions to the guest. For the time
4455 * being the default is to only do this for VMs with nested paging and AMD-V or
4456 * unrestricted guest mode.
4457 */
4458 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4459 AssertLogRelRCReturn(rc, rc);
4460
4461 /** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4462 * Whether to expose the AMD SSE4A instructions to the guest. For the time
4463 * being the default is to only do this for VMs with nested paging and AMD-V or
4464 * unrestricted guest mode.
4465 */
4466 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4467 AssertLogRelRCReturn(rc, rc);
4468
4469 /** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4470 * Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4471 * the time being the default is to only do this for VMs with nested paging and
4472 * AMD-V or unrestricted guest mode.
4473 */
4474 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4475 AssertLogRelRCReturn(rc, rc);
4476
4477 /** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4478 * Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4479 * For the time being the default is to only do this for VMs with nested paging
4480 * and AMD-V or unrestricted guest mode.
4481 */
4482 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4483 AssertLogRelRCReturn(rc, rc);
4484
4485 /** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4486 * Whether to expose the AMD's MMX Extensions to the guest. For the time being
4487 * the default is to only do this for VMs with nested paging and AMD-V or
4488 * unrestricted guest mode.
4489 */
4490 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4491 AssertLogRelRCReturn(rc, rc);
4492
4493 return VINF_SUCCESS;
4494}
4495
4496
4497/**
4498 * Initializes the emulated CPU's CPUID & MSR information.
4499 *
4500 * @returns VBox status code.
4501 * @param pVM The cross context VM structure.
4502 * @param pHostMsrs Pointer to the host MSRs.
4503 */
4504int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
4505{
4506 Assert(pHostMsrs);
4507
4508 PCPUM pCpum = &pVM->cpum.s;
4509 PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4510
4511 /*
4512 * Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4513 * on construction and manage everything from here on.
4514 */
4515 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4516 {
4517 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4518 pVCpu->cpum.s.fCpuIdApicFeatureVisible = true;
4519 }
4520
4521 /*
4522 * Read the configuration.
4523 */
4524 CPUMCPUIDCONFIG Config;
4525 RT_ZERO(Config);
4526
4527 int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4528 AssertRCReturn(rc, rc);
4529
4530 /*
4531 * Get the guest CPU data from the database and/or the host.
4532 *
4533 * The CPUID and MSRs are currently living on the regular heap to avoid
4534 * fragmenting the hyper heap (and because there isn't/wasn't any realloc
4535 * API for the hyper heap). This means special cleanup considerations.
4536 */
4537 /** @todo The hyper heap will be removed ASAP, so the final destination is
4538 * now a fixed sized arrays in the VM structure. Maybe we can simplify
4539 * this allocation fun a little now? Or maybe it's too convenient for
4540 * the CPU reporter code... No time to figure that out now. */
4541 rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4542 if (RT_FAILURE(rc))
4543 return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4544 ? VMSetError(pVM, rc, RT_SRC_POS,
4545 "Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4546 : rc;
4547
4548 if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4549 {
4550 LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4551 pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4552 pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4553 }
4554 LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4555
4556 /** @cfgm{/CPUM/MSRs/[Name]/[First|Last|Type|Value|...],}
4557 * Overrides the guest MSRs.
4558 */
4559 rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4560
4561 /** @cfgm{/CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
4562 * Overrides the CPUID leaf values (from the host CPU usually) used for
4563 * calculating the guest CPUID leaves. This can be used to preserve the CPUID
4564 * values when moving a VM to a different machine. Another use is restricting
4565 * (or extending) the feature set exposed to the guest. */
4566 if (RT_SUCCESS(rc))
4567 rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4568
4569 if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4570 rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4571 "Found unsupported configuration node '/CPUM/CPUID/'. "
4572 "Please use IMachine::setCPUIDLeaf() instead.");
4573
4574 CPUMMSRS GuestMsrs;
4575 RT_ZERO(GuestMsrs);
4576
4577 /*
4578 * Pre-explode the CPUID info.
4579 */
4580 if (RT_SUCCESS(rc))
4581 rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
4582 &pCpum->GuestFeatures);
4583
4584 /*
4585 * Sanitize the cpuid information passed on to the guest.
4586 */
4587 if (RT_SUCCESS(rc))
4588 {
4589 rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4590 if (RT_SUCCESS(rc))
4591 {
4592 cpumR3CpuIdLimitLeaves(pCpum, &Config);
4593 cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4594 }
4595 }
4596
4597 /*
4598 * Setup MSRs introduced in microcode updates or that are otherwise not in
4599 * the CPU profile, but are advertised in the CPUID info we just sanitized.
4600 */
4601 if (RT_SUCCESS(rc))
4602 rc = cpumR3MsrReconcileWithCpuId(pVM);
4603 /*
4604 * MSR fudging.
4605 */
4606 if (RT_SUCCESS(rc))
4607 {
4608 /** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4609 * Fudges some common MSRs if not present in the selected CPU database entry.
4610 * This is for trying to keep VMs running when moved between different hosts
4611 * and different CPU vendors. */
4612 bool fEnable;
4613 rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4614 if (RT_SUCCESS(rc) && fEnable)
4615 {
4616 rc = cpumR3MsrApplyFudge(pVM);
4617 AssertLogRelRC(rc);
4618 }
4619 }
4620 if (RT_SUCCESS(rc))
4621 {
4622 /*
4623 * Move the MSR and CPUID arrays over to the static VM structure allocations
4624 * and explode guest CPU features again.
4625 */
4626 void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4627 rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4628 pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
4629 RTMemFree(pvFree);
4630
4631 AssertFatalMsg(pCpum->GuestInfo.cMsrRanges <= RT_ELEMENTS(pCpum->GuestInfo.aMsrRanges),
4632 ("%u\n", pCpum->GuestInfo.cMsrRanges));
4633 memcpy(pCpum->GuestInfo.aMsrRanges, pCpum->GuestInfo.paMsrRangesR3,
4634 sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges);
4635 RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4636 pCpum->GuestInfo.paMsrRangesR3 = pCpum->GuestInfo.aMsrRanges;
4637
4638 AssertLogRelRCReturn(rc, rc);
4639
4640 /*
4641 * Finally, initialize guest VMX MSRs.
4642 *
4643 * This needs to be done -after- exploding guest features and sanitizing CPUID leaves
4644 * as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
4645 * unrestricted-guest execution, CR4 feature bits and possibly more in the future.
4646 */
4647 if (pVM->cpum.s.GuestFeatures.fVmx)
4648 {
4649 Assert(Config.fNestedHWVirt);
4650 cpumR3InitVmxGuestFeaturesAndMsrs(pVM, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
4651
4652 /* Copy MSRs to all VCPUs */
4653 PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
4654 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4655 {
4656 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4657 memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
4658 }
4659 }
4660
4661 /*
4662 * Some more configuration that we're applying at the end of everything
4663 * via the CPUMR3SetGuestCpuIdFeature API.
4664 */
4665
4666 /* Check if PAE was explicitely enabled by the user. */
4667 bool fEnable;
4668 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4669 AssertRCReturn(rc, rc);
4670 if (fEnable)
4671 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4672
4673 /* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4674 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4675 AssertRCReturn(rc, rc);
4676 if (fEnable)
4677 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4678
4679 /* Check if speculation control is enabled. */
4680 rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4681 AssertRCReturn(rc, rc);
4682 if (fEnable)
4683 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4684 else
4685 {
4686 /*
4687 * Set the "SSBD-not-needed" flag to work around a bug in some Linux kernels when the VIRT_SPEC_CTL
4688 * feature is not exposed on AMD CPUs and there is only 1 vCPU configured.
4689 * This was observed with kernel "4.15.0-29-generic #31~16.04.1-Ubuntu" but more versions are likely affected.
4690 *
4691 * The kernel doesn't initialize a lock and causes a NULL pointer exception later on when configuring SSBD:
4692 * EIP: _raw_spin_lock+0x14/0x30
4693 * EFLAGS: 00010046 CPU: 0
4694 * EAX: 00000000 EBX: 00000001 ECX: 00000004 EDX: 00000000
4695 * ESI: 00000000 EDI: 00000000 EBP: ee023f1c ESP: ee023f18
4696 * DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
4697 * CR0: 80050033 CR2: 00000004 CR3: 3671c180 CR4: 000006f0
4698 * Call Trace:
4699 * speculative_store_bypass_update+0x8e/0x180
4700 * ssb_prctl_set+0xc0/0xe0
4701 * arch_seccomp_spec_mitigate+0x1d/0x20
4702 * do_seccomp+0x3cb/0x610
4703 * SyS_seccomp+0x16/0x20
4704 * do_fast_syscall_32+0x7f/0x1d0
4705 * entry_SYSENTER_32+0x4e/0x7c
4706 *
4707 * The lock would've been initialized in process.c:speculative_store_bypass_ht_init() called from two places in smpboot.c.
4708 * First when a secondary CPU is started and second in native_smp_prepare_cpus() which is not called in a single vCPU environment.
4709 *
4710 * As spectre control features are completely disabled anyway when we arrived here there is no harm done in informing the
4711 * guest to not even try.
4712 */
4713 if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4714 || pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
4715 {
4716 PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x80000008), 0);
4717 if (pLeaf)
4718 {
4719 pLeaf->uEbx |= X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED;
4720 LogRel(("CPUM: Set SSBD not required flag for AMD to work around some buggy Linux kernels!\n"));
4721 }
4722 }
4723 }
4724
4725 return VINF_SUCCESS;
4726 }
4727
4728 /*
4729 * Failed before switching to hyper heap.
4730 */
4731 RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4732 pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4733 RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4734 pCpum->GuestInfo.paMsrRangesR3 = NULL;
4735 return rc;
4736}
4737
4738
4739/**
4740 * Sets a CPUID feature bit during VM initialization.
4741 *
4742 * Since the CPUID feature bits are generally related to CPU features, other
4743 * CPUM configuration like MSRs can also be modified by calls to this API.
4744 *
4745 * @param pVM The cross context VM structure.
4746 * @param enmFeature The feature to set.
4747 */
4748VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4749{
4750 PCPUMCPUIDLEAF pLeaf;
4751 PCPUMMSRRANGE pMsrRange;
4752
4753 switch (enmFeature)
4754 {
4755 /*
4756 * Set the APIC bit in both feature masks.
4757 */
4758 case CPUMCPUIDFEATURE_APIC:
4759 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4760 if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4761 pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx |= X86_CPUID_FEATURE_EDX_APIC;
4762
4763 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4764 if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4765 pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
4766
4767 pVM->cpum.s.GuestFeatures.fApic = 1;
4768
4769 /* Make sure we've got the APICBASE MSR present. */
4770 pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4771 if (!pMsrRange)
4772 {
4773 static CPUMMSRRANGE const s_ApicBase =
4774 {
4775 /*.uFirst =*/ MSR_IA32_APICBASE, /*.uLast =*/ MSR_IA32_APICBASE,
4776 /*.enmRdFn =*/ kCpumMsrRdFn_Ia32ApicBase, /*.enmWrFn =*/ kCpumMsrWrFn_Ia32ApicBase,
4777 /*.offCpumCpu =*/ UINT16_MAX, /*.fReserved =*/ 0, /*.uValue =*/ 0, /*.fWrIgnMask =*/ 0, /*.fWrGpMask =*/ 0,
4778 /*.szName = */ "IA32_APIC_BASE"
4779 };
4780 int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4781 AssertLogRelRC(rc);
4782 }
4783
4784 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4785 break;
4786
4787 /*
4788 * Set the x2APIC bit in the standard feature mask.
4789 * Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4790 */
4791 case CPUMCPUIDFEATURE_X2APIC:
4792 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4793 if (pLeaf)
4794 pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx |= X86_CPUID_FEATURE_ECX_X2APIC;
4795 pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4796
4797 /* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4798 pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4799 if (pMsrRange)
4800 {
4801 pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4802 pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4803 }
4804
4805 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4806 break;
4807
4808 /*
4809 * Set the sysenter/sysexit bit in the standard feature mask.
4810 * Assumes the caller knows what it's doing! (host must support these)
4811 */
4812 case CPUMCPUIDFEATURE_SEP:
4813 if (!pVM->cpum.s.HostFeatures.fSysEnter)
4814 {
4815 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4816 return;
4817 }
4818
4819 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4820 if (pLeaf)
4821 pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx |= X86_CPUID_FEATURE_EDX_SEP;
4822 pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4823 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4824 break;
4825
4826 /*
4827 * Set the syscall/sysret bit in the extended feature mask.
4828 * Assumes the caller knows what it's doing! (host must support these)
4829 */
4830 case CPUMCPUIDFEATURE_SYSCALL:
4831 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4832 if ( !pLeaf
4833 || !pVM->cpum.s.HostFeatures.fSysCall)
4834 {
4835 LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4836 return;
4837 }
4838
4839 /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4840 pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx |= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4841 pVM->cpum.s.GuestFeatures.fSysCall = 1;
4842 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4843 break;
4844
4845 /*
4846 * Set the PAE bit in both feature masks.
4847 * Assumes the caller knows what it's doing! (host must support these)
4848 */
4849 case CPUMCPUIDFEATURE_PAE:
4850 if (!pVM->cpum.s.HostFeatures.fPae)
4851 {
4852 LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4853 return;
4854 }
4855
4856 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4857 if (pLeaf)
4858 pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx |= X86_CPUID_FEATURE_EDX_PAE;
4859
4860 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4861 if ( pLeaf
4862 && ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4863 || pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
4864 pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
4865
4866 pVM->cpum.s.GuestFeatures.fPae = 1;
4867 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4868 break;
4869
4870 /*
4871 * Set the LONG MODE bit in the extended feature mask.
4872 * Assumes the caller knows what it's doing! (host must support these)
4873 */
4874 case CPUMCPUIDFEATURE_LONG_MODE:
4875 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4876 if ( !pLeaf
4877 || !pVM->cpum.s.HostFeatures.fLongMode)
4878 {
4879 LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4880 return;
4881 }
4882
4883 /* Valid for both Intel and AMD. */
4884 pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx |= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4885 pVM->cpum.s.GuestFeatures.fLongMode = 1;
4886 pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
4887 if (pVM->cpum.s.GuestFeatures.fVmx)
4888 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4889 {
4890 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4891 pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic &= ~VMX_BASIC_PHYSADDR_WIDTH_32BIT;
4892 }
4893 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4894 break;
4895
4896 /*
4897 * Set the NX/XD bit in the extended feature mask.
4898 * Assumes the caller knows what it's doing! (host must support these)
4899 */
4900 case CPUMCPUIDFEATURE_NX:
4901 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4902 if ( !pLeaf
4903 || !pVM->cpum.s.HostFeatures.fNoExecute)
4904 {
4905 LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4906 return;
4907 }
4908
4909 /* Valid for both Intel and AMD. */
4910 pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx |= X86_CPUID_EXT_FEATURE_EDX_NX;
4911 pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4912 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4913 break;
4914
4915
4916 /*
4917 * Set the LAHF/SAHF support in 64-bit mode.
4918 * Assumes the caller knows what it's doing! (host must support this)
4919 */
4920 case CPUMCPUIDFEATURE_LAHF:
4921 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4922 if ( !pLeaf
4923 || !pVM->cpum.s.HostFeatures.fLahfSahf)
4924 {
4925 LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4926 return;
4927 }
4928
4929 /* Valid for both Intel and AMD. */
4930 pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx |= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4931 pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4932 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4933 break;
4934
4935 /*
4936 * Set the RDTSCP support bit.
4937 * Assumes the caller knows what it's doing! (host must support this)
4938 */
4939 case CPUMCPUIDFEATURE_RDTSCP:
4940 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4941 if ( !pLeaf
4942 || !pVM->cpum.s.HostFeatures.fRdTscP
4943 || pVM->cpum.s.u8PortableCpuIdLevel > 0)
4944 {
4945 if (!pVM->cpum.s.u8PortableCpuIdLevel)
4946 LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4947 return;
4948 }
4949
4950 /* Valid for both Intel and AMD. */
4951 pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx |= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4952 pVM->cpum.s.HostFeatures.fRdTscP = 1;
4953 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4954 break;
4955
4956 /*
4957 * Set the Hypervisor Present bit in the standard feature mask.
4958 */
4959 case CPUMCPUIDFEATURE_HVP:
4960 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4961 if (pLeaf)
4962 pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx |= X86_CPUID_FEATURE_ECX_HVP;
4963 pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4964 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4965 break;
4966
4967 /*
4968 * Set up the speculation control CPUID bits and MSRs. This is quite complicated
4969 * on Intel CPUs, and different on AMDs.
4970 */
4971 case CPUMCPUIDFEATURE_SPEC_CTRL:
4972 if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4973 {
4974 pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4975 if ( !pLeaf
4976 || !(pVM->cpum.s.HostFeatures.fIbpb || pVM->cpum.s.HostFeatures.fIbrs))
4977 {
4978 LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4979 return;
4980 }
4981
4982 /* The feature can be enabled. Let's see what we can actually do. */
4983 pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4984
4985 /* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4986 if (pVM->cpum.s.HostFeatures.fIbrs)
4987 {
4988 pLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4989 pVM->cpum.s.GuestFeatures.fIbrs = 1;
4990 if (pVM->cpum.s.HostFeatures.fStibp)
4991 {
4992 pLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4993 pVM->cpum.s.GuestFeatures.fStibp = 1;
4994 }
4995
4996 /* Make sure we have the speculation control MSR... */
4997 pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4998 if (!pMsrRange)
4999 {
5000 static CPUMMSRRANGE const s_SpecCtrl =
5001 {
5002 /*.uFirst =*/ MSR_IA32_SPEC_CTRL, /*.uLast =*/ MSR_IA32_SPEC_CTRL,
5003 /*.enmRdFn =*/ kCpumMsrRdFn_Ia32SpecCtrl, /*.enmWrFn =*/ kCpumMsrWrFn_Ia32SpecCtrl,
5004 /*.offCpumCpu =*/ UINT16_MAX, /*.fReserved =*/ 0, /*.uValue =*/ 0, /*.fWrIgnMask =*/ 0, /*.fWrGpMask =*/ 0,
5005 /*.szName = */ "IA32_SPEC_CTRL"
5006 };
5007 int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
5008 AssertLogRelRC(rc);
5009 }
5010
5011 /* ... and the predictor command MSR. */
5012 pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
5013 if (!pMsrRange)
5014 {
5015 /** @todo incorrect fWrGpMask. */
5016 static CPUMMSRRANGE const s_SpecCtrl =
5017 {
5018 /*.uFirst =*/ MSR_IA32_PRED_CMD, /*.uLast =*/ MSR_IA32_PRED_CMD,
5019 /*.enmRdFn =*/ kCpumMsrRdFn_WriteOnly, /*.enmWrFn =*/ kCpumMsrWrFn_Ia32PredCmd,
5020 /*.offCpumCpu =*/ UINT16_MAX, /*.fReserved =*/ 0, /*.uValue =*/ 0, /*.fWrIgnMask =*/ 0, /*.fWrGpMask =*/ 0,
5021 /*.szName = */ "IA32_PRED_CMD"
5022 };
5023 int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
5024 AssertLogRelRC(rc);
5025 }
5026
5027 }
5028
5029 if (pVM->cpum.s.HostFeatures.fArchCap)
5030 {
5031 /* Install the architectural capabilities MSR. */
5032 pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
5033 if (!pMsrRange)
5034 {
5035 static CPUMMSRRANGE const s_ArchCaps =
5036 {
5037 /*.uFirst =*/ MSR_IA32_ARCH_CAPABILITIES, /*.uLast =*/ MSR_IA32_ARCH_CAPABILITIES,
5038 /*.enmRdFn =*/ kCpumMsrRdFn_Ia32ArchCapabilities, /*.enmWrFn =*/ kCpumMsrWrFn_ReadOnly,
5039 /*.offCpumCpu =*/ UINT16_MAX, /*.fReserved =*/ 0, /*.uValue =*/ 0, /*.fWrIgnMask =*/ 0, /*.fWrGpMask =*/ UINT64_MAX,
5040 /*.szName = */ "IA32_ARCH_CAPABILITIES"
5041 };
5042 int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
5043 AssertLogRelRC(rc);
5044 }
5045
5046 /* Advertise IBRS_ALL if present at this point... */
5047 if (pVM->cpum.s.HostFeatures.fArchCap & MSR_IA32_ARCH_CAP_F_IBRS_ALL)
5048 VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps |= MSR_IA32_ARCH_CAP_F_IBRS_ALL);
5049 }
5050
5051 LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
5052 }
5053 else if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
5054 || pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
5055 {
5056 /* The precise details of AMD's implementation are not yet clear. */
5057 }
5058 break;
5059
5060 default:
5061 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5062 break;
5063 }
5064
5065 /** @todo can probably kill this as this API is now init time only... */
5066 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5067 {
5068 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5069 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
5070 }
5071}
5072
5073
5074/**
5075 * Queries a CPUID feature bit.
5076 *
5077 * @returns boolean for feature presence
5078 * @param pVM The cross context VM structure.
5079 * @param enmFeature The feature to query.
5080 * @deprecated Use the cpum.ro.GuestFeatures directly instead.
5081 */
5082VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5083{
5084 switch (enmFeature)
5085 {
5086 case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
5087 case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
5088 case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
5089 case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
5090 case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
5091 case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
5092 case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
5093 case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
5094 case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
5095 case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
5096 case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
5097 case CPUMCPUIDFEATURE_INVALID:
5098 case CPUMCPUIDFEATURE_32BIT_HACK:
5099 break;
5100 }
5101 AssertFailed();
5102 return false;
5103}
5104
5105
5106/**
5107 * Clears a CPUID feature bit.
5108 *
5109 * @param pVM The cross context VM structure.
5110 * @param enmFeature The feature to clear.
5111 *
5112 * @deprecated Probably better to default the feature to disabled and only allow
5113 * setting (enabling) it during construction.
5114 */
5115VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
5116{
5117 PCPUMCPUIDLEAF pLeaf;
5118 switch (enmFeature)
5119 {
5120 case CPUMCPUIDFEATURE_APIC:
5121 Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
5122 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5123 if (pLeaf)
5124 pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
5125
5126 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5127 if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
5128 pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
5129
5130 pVM->cpum.s.GuestFeatures.fApic = 0;
5131 Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
5132 break;
5133
5134 case CPUMCPUIDFEATURE_X2APIC:
5135 Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
5136 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5137 if (pLeaf)
5138 pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
5139 pVM->cpum.s.GuestFeatures.fX2Apic = 0;
5140 Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
5141 break;
5142
5143 case CPUMCPUIDFEATURE_PAE:
5144 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5145 if (pLeaf)
5146 pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
5147
5148 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5149 if ( pLeaf
5150 && ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
5151 || pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
5152 pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
5153
5154 pVM->cpum.s.GuestFeatures.fPae = 0;
5155 Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
5156 break;
5157
5158 case CPUMCPUIDFEATURE_LONG_MODE:
5159 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5160 if (pLeaf)
5161 pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
5162 pVM->cpum.s.GuestFeatures.fLongMode = 0;
5163 pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
5164 if (pVM->cpum.s.GuestFeatures.fVmx)
5165 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5166 {
5167 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5168 pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic |= VMX_BASIC_PHYSADDR_WIDTH_32BIT;
5169 }
5170 break;
5171
5172 case CPUMCPUIDFEATURE_LAHF:
5173 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5174 if (pLeaf)
5175 pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
5176 pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
5177 break;
5178
5179 case CPUMCPUIDFEATURE_RDTSCP:
5180 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
5181 if (pLeaf)
5182 pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
5183 pVM->cpum.s.GuestFeatures.fRdTscP = 0;
5184 Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
5185 break;
5186
5187 case CPUMCPUIDFEATURE_HVP:
5188 pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
5189 if (pLeaf)
5190 pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
5191 pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
5192 break;
5193
5194 case CPUMCPUIDFEATURE_SPEC_CTRL:
5195 pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
5196 if (pLeaf)
5197 pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB | X86_CPUID_STEXT_FEATURE_EDX_STIBP);
5198 VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL);
5199 Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
5200 break;
5201
5202 default:
5203 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
5204 break;
5205 }
5206
5207 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5208 {
5209 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5210 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
5211 }
5212}
5213
5214
5215
5216/*
5217 *
5218 *
5219 * Saved state related code.
5220 * Saved state related code.
5221 * Saved state related code.
5222 *
5223 *
5224 */
5225
5226/**
5227 * Called both in pass 0 and the final pass.
5228 *
5229 * @param pVM The cross context VM structure.
5230 * @param pSSM The saved state handle.
5231 */
5232void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
5233{
5234 /*
5235 * Save all the CPU ID leaves.
5236 */
5237 SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
5238 SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5239 SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
5240 sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
5241
5242 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5243
5244 /*
5245 * Save a good portion of the raw CPU IDs as well as they may come in
5246 * handy when validating features for raw mode.
5247 */
5248 CPUMCPUID aRawStd[16];
5249 for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
5250 ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5251 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
5252 SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
5253
5254 CPUMCPUID aRawExt[32];
5255 for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
5256 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5257 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
5258 SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
5259}
5260
5261
5262static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
5263{
5264 uint32_t cCpuIds;
5265 int rc = SSMR3GetU32(pSSM, &cCpuIds);
5266 if (RT_SUCCESS(rc))
5267 {
5268 if (cCpuIds < 64)
5269 {
5270 for (uint32_t i = 0; i < cCpuIds; i++)
5271 {
5272 CPUMCPUID CpuId;
5273 rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
5274 if (RT_FAILURE(rc))
5275 break;
5276
5277 CPUMCPUIDLEAF NewLeaf;
5278 NewLeaf.uLeaf = uBase + i;
5279 NewLeaf.uSubLeaf = 0;
5280 NewLeaf.fSubLeafMask = 0;
5281 NewLeaf.uEax = CpuId.uEax;
5282 NewLeaf.uEbx = CpuId.uEbx;
5283 NewLeaf.uEcx = CpuId.uEcx;
5284 NewLeaf.uEdx = CpuId.uEdx;
5285 NewLeaf.fFlags = 0;
5286 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
5287 }
5288 }
5289 else
5290 rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5291 }
5292 if (RT_FAILURE(rc))
5293 {
5294 RTMemFree(*ppaLeaves);
5295 *ppaLeaves = NULL;
5296 *pcLeaves = 0;
5297 }
5298 return rc;
5299}
5300
5301
5302static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
5303{
5304 *ppaLeaves = NULL;
5305 *pcLeaves = 0;
5306
5307 int rc;
5308 if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
5309 {
5310 /*
5311 * The new format. Starts by declaring the leave size and count.
5312 */
5313 uint32_t cbLeaf;
5314 SSMR3GetU32(pSSM, &cbLeaf);
5315 uint32_t cLeaves;
5316 rc = SSMR3GetU32(pSSM, &cLeaves);
5317 if (RT_SUCCESS(rc))
5318 {
5319 if (cbLeaf == sizeof(**ppaLeaves))
5320 {
5321 if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
5322 {
5323 /*
5324 * Load the leaves one by one.
5325 *
5326 * The uPrev stuff is a kludge for working around a week worth of bad saved
5327 * states during the CPUID revamp in March 2015. We saved too many leaves
5328 * due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
5329 * garbage entires at the end of the array when restoring. We also had
5330 * a subleaf insertion bug that triggered with the leaf 4 stuff below,
5331 * this kludge doesn't deal correctly with that, but who cares...
5332 */
5333 uint32_t uPrev = 0;
5334 for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
5335 {
5336 CPUMCPUIDLEAF Leaf;
5337 rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5338 if (RT_SUCCESS(rc))
5339 {
5340 if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5341 || Leaf.uLeaf >= uPrev)
5342 {
5343 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5344 uPrev = Leaf.uLeaf;
5345 }
5346 else
5347 uPrev = UINT32_MAX;
5348 }
5349 }
5350 }
5351 else
5352 rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5353 "Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5354 }
5355 else
5356 rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5357 "CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5358 }
5359 }
5360 else
5361 {
5362 /*
5363 * The old format with its three inflexible arrays.
5364 */
5365 rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5366 if (RT_SUCCESS(rc))
5367 rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5368 if (RT_SUCCESS(rc))
5369 rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5370 if (RT_SUCCESS(rc))
5371 {
5372 /*
5373 * Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5374 */
5375 PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(*ppaLeaves, *pcLeaves, 0, 0);
5376 if ( pLeaf
5377 && ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5378 {
5379 CPUMCPUIDLEAF Leaf;
5380 Leaf.uLeaf = 4;
5381 Leaf.fSubLeafMask = UINT32_MAX;
5382 Leaf.uSubLeaf = 0;
5383 Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5384 Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5385 Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5386 | (UINT32_C(0) << 12) /* phys line partitions - 1 */
5387 | UINT32_C(63); /* system coherency line size - 1 */
5388 Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5389 | (UINT32_C(0) << 14) /* threads per cache - 1 */
5390 | (UINT32_C(1) << 5) /* cache level */
5391 | UINT32_C(1); /* cache type (data) */
5392 Leaf.fFlags = 0;
5393 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5394 if (RT_SUCCESS(rc))
5395 {
5396 Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5397 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5398 }
5399 if (RT_SUCCESS(rc))
5400 {
5401 Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5402 Leaf.uEcx = 4095; /* sets - 1 */
5403 Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5404 Leaf.uEbx |= UINT32_C(23) << 22;
5405 Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5406 Leaf.uEax |= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5407 Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5408 Leaf.uEax |= UINT32_C(2) << 5;
5409 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5410 }
5411 }
5412 }
5413 }
5414 return rc;
5415}
5416
5417
5418/**
5419 * Loads the CPU ID leaves saved by pass 0, inner worker.
5420 *
5421 * @returns VBox status code.
5422 * @param pVM The cross context VM structure.
5423 * @param pSSM The saved state handle.
5424 * @param uVersion The format version.
5425 * @param paLeaves Guest CPUID leaves loaded from the state.
5426 * @param cLeaves The number of leaves in @a paLeaves.
5427 * @param pMsrs The guest MSRs.
5428 */
5429int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
5430{
5431 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5432
5433 /*
5434 * Continue loading the state into stack buffers.
5435 */
5436 CPUMCPUID GuestDefCpuId;
5437 int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5438 AssertRCReturn(rc, rc);
5439
5440 CPUMCPUID aRawStd[16];
5441 uint32_t cRawStd;
5442 rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5443 if (cRawStd > RT_ELEMENTS(aRawStd))
5444 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5445 rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5446 AssertRCReturn(rc, rc);
5447 for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5448 ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5449
5450 CPUMCPUID aRawExt[32];
5451 uint32_t cRawExt;
5452 rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5453 if (cRawExt > RT_ELEMENTS(aRawExt))
5454 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5455 rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5456 AssertRCReturn(rc, rc);
5457 for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5458 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5459
5460 /*
5461 * Get the raw CPU IDs for the current host.
5462 */
5463 CPUMCPUID aHostRawStd[16];
5464 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5465 ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5466
5467 CPUMCPUID aHostRawExt[32];
5468 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5469 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0,
5470 &aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5471
5472 /*
5473 * Get the host and guest overrides so we don't reject the state because
5474 * some feature was enabled thru these interfaces.
5475 * Note! We currently only need the feature leaves, so skip rest.
5476 */
5477 PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5478 CPUMCPUID aHostOverrideStd[2];
5479 memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5480 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5481
5482 CPUMCPUID aHostOverrideExt[2];
5483 memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5484 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5485
5486 /*
5487 * This can be skipped.
5488 */
5489 bool fStrictCpuIdChecks;
5490 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5491
5492 /*
5493 * Define a bunch of macros for simplifying the santizing/checking code below.
5494 */
5495 /* Generic expression + failure message. */
5496#define CPUID_CHECK_RET(expr, fmt) \
5497 do { \
5498 if (!(expr)) \
5499 { \
5500 char *pszMsg = RTStrAPrintf2 fmt; /* lack of variadic macros sucks */ \
5501 if (fStrictCpuIdChecks) \
5502 { \
5503 int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5504 RTStrFree(pszMsg); \
5505 return rcCpuid; \
5506 } \
5507 LogRel(("CPUM: %s\n", pszMsg)); \
5508 RTStrFree(pszMsg); \
5509 } \
5510 } while (0)
5511#define CPUID_CHECK_WRN(expr, fmt) \
5512 do { \
5513 if (!(expr)) \
5514 LogRel(fmt); \
5515 } while (0)
5516
5517 /* For comparing two values and bitch if they differs. */
5518#define CPUID_CHECK2_RET(what, host, saved) \
5519 do { \
5520 if ((host) != (saved)) \
5521 { \
5522 if (fStrictCpuIdChecks) \
5523 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5524 N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5525 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5526 } \
5527 } while (0)
5528#define CPUID_CHECK2_WRN(what, host, saved) \
5529 do { \
5530 if ((host) != (saved)) \
5531 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5532 } while (0)
5533
5534 /* For checking raw cpu features (raw mode). */
5535#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5536 do { \
5537 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5538 { \
5539 if (fStrictCpuIdChecks) \
5540 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5541 N_(#bit " mismatch: host=%d saved=%d"), \
5542 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5543 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5544 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5545 } \
5546 } while (0)
5547#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5548 do { \
5549 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5550 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5551 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5552 } while (0)
5553#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5554
5555 /* For checking guest features. */
5556#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5557 do { \
5558 if ( (aGuestCpuId##set [1].reg & bit) \
5559 && !(aHostRaw##set [1].reg & bit) \
5560 && !(aHostOverride##set [1].reg & bit) \
5561 ) \
5562 { \
5563 if (fStrictCpuIdChecks) \
5564 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5565 N_(#bit " is not supported by the host but has already exposed to the guest")); \
5566 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5567 } \
5568 } while (0)
5569#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5570 do { \
5571 if ( (aGuestCpuId##set [1].reg & bit) \
5572 && !(aHostRaw##set [1].reg & bit) \
5573 && !(aHostOverride##set [1].reg & bit) \
5574 ) \
5575 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5576 } while (0)
5577#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5578 do { \
5579 if ( (aGuestCpuId##set [1].reg & bit) \
5580 && !(aHostRaw##set [1].reg & bit) \
5581 && !(aHostOverride##set [1].reg & bit) \
5582 ) \
5583 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5584 } while (0)
5585#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5586
5587 /* For checking guest features if AMD guest CPU. */
5588#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5589 do { \
5590 if ( (aGuestCpuId##set [1].reg & bit) \
5591 && fGuestAmd \
5592 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
5593 && !(aHostOverride##set [1].reg & bit) \
5594 ) \
5595 { \
5596 if (fStrictCpuIdChecks) \
5597 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5598 N_(#bit " is not supported by the host but has already exposed to the guest")); \
5599 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5600 } \
5601 } while (0)
5602#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5603 do { \
5604 if ( (aGuestCpuId##set [1].reg & bit) \
5605 && fGuestAmd \
5606 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
5607 && !(aHostOverride##set [1].reg & bit) \
5608 ) \
5609 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5610 } while (0)
5611#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5612 do { \
5613 if ( (aGuestCpuId##set [1].reg & bit) \
5614 && fGuestAmd \
5615 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
5616 && !(aHostOverride##set [1].reg & bit) \
5617 ) \
5618 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5619 } while (0)
5620#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5621
5622 /* For checking AMD features which have a corresponding bit in the standard
5623 range. (Intel defines very few bits in the extended feature sets.) */
5624#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5625 do { \
5626 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5627 && !(fHostAmd \
5628 ? aHostRawExt[1].reg & (ExtBit) \
5629 : aHostRawStd[1].reg & (StdBit)) \
5630 && !(aHostOverrideExt[1].reg & (ExtBit)) \
5631 ) \
5632 { \
5633 if (fStrictCpuIdChecks) \
5634 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5635 N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5636 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5637 } \
5638 } while (0)
5639#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5640 do { \
5641 if ( (aGuestCpuId[1].reg & (ExtBit)) \
5642 && !(fHostAmd \
5643 ? aHostRawExt[1].reg & (ExtBit) \
5644 : aHostRawStd[1].reg & (StdBit)) \
5645 && !(aHostOverrideExt[1].reg & (ExtBit)) \
5646 ) \
5647 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5648 } while (0)
5649#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5650 do { \
5651 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5652 && !(fHostAmd \
5653 ? aHostRawExt[1].reg & (ExtBit) \
5654 : aHostRawStd[1].reg & (StdBit)) \
5655 && !(aHostOverrideExt[1].reg & (ExtBit)) \
5656 ) \
5657 LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5658 } while (0)
5659#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5660
5661
5662 /*
5663 * Verify that we can support the features already exposed to the guest on
5664 * this host.
5665 *
5666 * Most of the features we're emulating requires intercepting instruction
5667 * and doing it the slow way, so there is no need to warn when they aren't
5668 * present in the host CPU. Thus we use IGN instead of EMU on these.
5669 *
5670 * Trailing comments:
5671 * "EMU" - Possible to emulate, could be lots of work and very slow.
5672 * "EMU?" - Can this be emulated?
5673 */
5674 CPUMCPUID aGuestCpuIdStd[2];
5675 RT_ZERO(aGuestCpuIdStd);
5676 cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5677
5678 /* CPUID(1).ecx */
5679 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5680 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5681 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5682 CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5683 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5684 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5685 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5686 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5687 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5688 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5689 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5690 CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5691 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5692 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5693 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5694 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5695 CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /*reserved*/);
5696 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5697 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5698 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5699 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5700 CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5701 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5702 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5703 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5704 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5705 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5706 CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5707 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5708 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5709 CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5710 CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5711
5712 /* CPUID(1).edx */
5713 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5714 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5715 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5716 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5717 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5718 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5719 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5720 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5721 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5722 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5723 CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /*reserved*/);
5724 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5725 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5726 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5727 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5728 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5729 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5730 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5731 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5732 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5733 CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /*reserved*/);
5734 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5735 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5736 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5737 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5738 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5739 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5740 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5741 CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5742 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5743 CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /*JMPE/IA64*/); // -> EMU
5744 CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5745
5746 /* CPUID(0x80000000). */
5747 CPUMCPUID aGuestCpuIdExt[2];
5748 RT_ZERO(aGuestCpuIdExt);
5749 if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5750 {
5751 /** @todo deal with no 0x80000001 on the host. */
5752 bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx)
5753 || ASMIsHygonCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5754 bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx)
5755 || ASMIsHygonCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5756
5757 /* CPUID(0x80000001).ecx */
5758 CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5759 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5760 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5761 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5762 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5763 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5764 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5765 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5766 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5767 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5768 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5769 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5770 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5771 CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5772 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5773 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5774 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5775 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5776 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5777 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5778 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5779 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5780 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5781 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5782 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5783 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5784 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5785 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5786 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5787 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5788 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5789 CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5790
5791 /* CPUID(0x80000001).edx */
5792 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5793 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5794 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5795 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5796 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5797 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5798 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5799 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5800 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5801 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5802 CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /*reserved*/);
5803 CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5804 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5805 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5806 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5807 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5808 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5809 CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5810 CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /*reserved*/);
5811 CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /*reserved*/);
5812 CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5813 CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /*reserved*/);
5814 CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5815 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5816 CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5817 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5818 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5819 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5820 CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /*reserved*/);
5821 CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5822 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5823 CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5824 }
5825
5826 /** @todo check leaf 7 */
5827
5828 /* CPUID(d) - XCR0 stuff - takes ECX as input.
5829 * ECX=0: EAX - Valid bits in XCR0[31:0].
5830 * EBX - Maximum state size as per current XCR0 value.
5831 * ECX - Maximum state size for all supported features.
5832 * EDX - Valid bits in XCR0[63:32].
5833 * ECX=1: EAX - Various X-features.
5834 * EBX - Maximum state size as per current XCR0|IA32_XSS value.
5835 * ECX - Valid bits in IA32_XSS[31:0].
5836 * EDX - Valid bits in IA32_XSS[63:32].
5837 * ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5838 * if the bit invalid all four registers are set to zero.
5839 * EAX - The state size for this feature.
5840 * EBX - The state byte offset of this feature.
5841 * ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5842 * EDX - Reserved, but is set to zero if invalid sub-leaf index.
5843 */
5844 uint64_t fGuestXcr0Mask = 0;
5845 PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5846 if ( pCurLeaf
5847 && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5848 && ( pCurLeaf->uEax
5849 || pCurLeaf->uEbx
5850 || pCurLeaf->uEcx
5851 || pCurLeaf->uEdx) )
5852 {
5853 fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5854 if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5855 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5856 N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5857 fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5858 if ((fGuestXcr0Mask & (XSAVE_C_X87 | XSAVE_C_SSE)) != (XSAVE_C_X87 | XSAVE_C_SSE))
5859 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5860 N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5861
5862 /* We don't support any additional features yet. */
5863 pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5864 if (pCurLeaf && pCurLeaf->uEax)
5865 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5866 N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5867 if (pCurLeaf && (pCurLeaf->uEcx || pCurLeaf->uEdx))
5868 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5869 N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5870 RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5871
5872
5873 for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5874 {
5875 pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5876 if (pCurLeaf)
5877 {
5878 /* If advertised, the state component offset and size must match the one used by host. */
5879 if (pCurLeaf->uEax || pCurLeaf->uEbx || pCurLeaf->uEcx || pCurLeaf->uEdx)
5880 {
5881 CPUMCPUID RawHost;
5882 ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5883 &RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5884 if ( RawHost.uEbx != pCurLeaf->uEbx
5885 || RawHost.uEax != pCurLeaf->uEax)
5886 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5887 N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5888 uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5889 }
5890 }
5891 }
5892 }
5893 /* Clear leaf 0xd just in case we're loading an old state... */
5894 else if (pCurLeaf)
5895 {
5896 for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5897 {
5898 pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5899 if (pCurLeaf)
5900 {
5901 AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5902 || ( pCurLeaf->uEax == 0
5903 && pCurLeaf->uEbx == 0
5904 && pCurLeaf->uEcx == 0
5905 && pCurLeaf->uEdx == 0),
5906 ("uVersion=%#x; %#x %#x %#x %#x\n",
5907 uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5908 pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5909 }
5910 }
5911 }
5912
5913 /* Update the fXStateGuestMask value for the VM. */
5914 if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5915 {
5916 LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5917 pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5918 if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5919 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5920 N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5921 }
5922
5923#undef CPUID_CHECK_RET
5924#undef CPUID_CHECK_WRN
5925#undef CPUID_CHECK2_RET
5926#undef CPUID_CHECK2_WRN
5927#undef CPUID_RAW_FEATURE_RET
5928#undef CPUID_RAW_FEATURE_WRN
5929#undef CPUID_RAW_FEATURE_IGN
5930#undef CPUID_GST_FEATURE_RET
5931#undef CPUID_GST_FEATURE_WRN
5932#undef CPUID_GST_FEATURE_EMU
5933#undef CPUID_GST_FEATURE_IGN
5934#undef CPUID_GST_FEATURE2_RET
5935#undef CPUID_GST_FEATURE2_WRN
5936#undef CPUID_GST_FEATURE2_EMU
5937#undef CPUID_GST_FEATURE2_IGN
5938#undef CPUID_GST_AMD_FEATURE_RET
5939#undef CPUID_GST_AMD_FEATURE_WRN
5940#undef CPUID_GST_AMD_FEATURE_EMU
5941#undef CPUID_GST_AMD_FEATURE_IGN
5942
5943 /*
5944 * We're good, commit the CPU ID leaves.
5945 */
5946 pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5947 rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
5948 AssertLogRelRCReturn(rc, rc);
5949
5950 return VINF_SUCCESS;
5951}
5952
5953
5954/**
5955 * Loads the CPU ID leaves saved by pass 0.
5956 *
5957 * @returns VBox status code.
5958 * @param pVM The cross context VM structure.
5959 * @param pSSM The saved state handle.
5960 * @param uVersion The format version.
5961 * @param pMsrs The guest MSRs.
5962 */
5963int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
5964{
5965 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5966
5967 /*
5968 * Load the CPUID leaves array first and call worker to do the rest, just so
5969 * we can free the memory when we need to without ending up in column 1000.
5970 */
5971 PCPUMCPUIDLEAF paLeaves;
5972 uint32_t cLeaves;
5973 int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5974 AssertRC(rc);
5975 if (RT_SUCCESS(rc))
5976 {
5977 rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
5978 RTMemFree(paLeaves);
5979 }
5980 return rc;
5981}
5982
5983
5984
5985/**
5986 * Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5987 *
5988 * @returns VBox status code.
5989 * @param pVM The cross context VM structure.
5990 * @param pSSM The saved state handle.
5991 * @param uVersion The format version.
5992 */
5993int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5994{
5995 AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5996
5997 /*
5998 * Restore the CPUID leaves.
5999 *
6000 * Note that we support restoring less than the current amount of standard
6001 * leaves because we've been allowed more is newer version of VBox.
6002 */
6003 uint32_t cElements;
6004 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6005 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
6006 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6007 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
6008
6009 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6010 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
6011 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6012 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
6013
6014 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
6015 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
6016 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6017 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
6018
6019 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
6020
6021 /*
6022 * Check that the basic cpuid id information is unchanged.
6023 */
6024 /** @todo we should check the 64 bits capabilities too! */
6025 uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
6026 ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
6027 ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
6028 uint32_t au32CpuIdSaved[8];
6029 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
6030 if (RT_SUCCESS(rc))
6031 {
6032 /* Ignore CPU stepping. */
6033 au32CpuId[4] &= 0xfffffff0;
6034 au32CpuIdSaved[4] &= 0xfffffff0;
6035
6036 /* Ignore APIC ID (AMD specs). */
6037 au32CpuId[5] &= ~0xff000000;
6038 au32CpuIdSaved[5] &= ~0xff000000;
6039
6040 /* Ignore the number of Logical CPUs (AMD specs). */
6041 au32CpuId[5] &= ~0x00ff0000;
6042 au32CpuIdSaved[5] &= ~0x00ff0000;
6043
6044 /* Ignore some advanced capability bits, that we don't expose to the guest. */
6045 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6046 | X86_CPUID_FEATURE_ECX_VMX
6047 | X86_CPUID_FEATURE_ECX_SMX
6048 | X86_CPUID_FEATURE_ECX_EST
6049 | X86_CPUID_FEATURE_ECX_TM2
6050 | X86_CPUID_FEATURE_ECX_CNTXID
6051 | X86_CPUID_FEATURE_ECX_TPRUPDATE
6052 | X86_CPUID_FEATURE_ECX_PDCM
6053 | X86_CPUID_FEATURE_ECX_DCA
6054 | X86_CPUID_FEATURE_ECX_X2APIC
6055 );
6056 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
6057 | X86_CPUID_FEATURE_ECX_VMX
6058 | X86_CPUID_FEATURE_ECX_SMX
6059 | X86_CPUID_FEATURE_ECX_EST
6060 | X86_CPUID_FEATURE_ECX_TM2
6061 | X86_CPUID_FEATURE_ECX_CNTXID
6062 | X86_CPUID_FEATURE_ECX_TPRUPDATE
6063 | X86_CPUID_FEATURE_ECX_PDCM
6064 | X86_CPUID_FEATURE_ECX_DCA
6065 | X86_CPUID_FEATURE_ECX_X2APIC
6066 );
6067
6068 /* Make sure we don't forget to update the masks when enabling
6069 * features in the future.
6070 */
6071 AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
6072 ( X86_CPUID_FEATURE_ECX_DTES64
6073 | X86_CPUID_FEATURE_ECX_VMX
6074 | X86_CPUID_FEATURE_ECX_SMX
6075 | X86_CPUID_FEATURE_ECX_EST
6076 | X86_CPUID_FEATURE_ECX_TM2
6077 | X86_CPUID_FEATURE_ECX_CNTXID
6078 | X86_CPUID_FEATURE_ECX_TPRUPDATE
6079 | X86_CPUID_FEATURE_ECX_PDCM
6080 | X86_CPUID_FEATURE_ECX_DCA
6081 | X86_CPUID_FEATURE_ECX_X2APIC
6082 )));
6083 /* do the compare */
6084 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
6085 {
6086 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
6087 LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
6088 "Saved=%.*Rhxs\n"
6089 "Real =%.*Rhxs\n",
6090 sizeof(au32CpuIdSaved), au32CpuIdSaved,
6091 sizeof(au32CpuId), au32CpuId));
6092 else
6093 {
6094 LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
6095 "Saved=%.*Rhxs\n"
6096 "Real =%.*Rhxs\n",
6097 sizeof(au32CpuIdSaved), au32CpuIdSaved,
6098 sizeof(au32CpuId), au32CpuId));
6099 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
6100 }
6101 }
6102 }
6103
6104 return rc;
6105}
6106
6107
6108
6109/*
6110 *
6111 *
6112 * CPUID Info Handler.
6113 * CPUID Info Handler.
6114 * CPUID Info Handler.
6115 *
6116 *
6117 */
6118
6119
6120
6121/**
6122 * Get L1 cache / TLS associativity.
6123 */
6124static const char *getCacheAss(unsigned u, char *pszBuf)
6125{
6126 if (u == 0)
6127 return "res0 ";
6128 if (u == 1)
6129 return "direct";
6130 if (u == 255)
6131 return "fully";
6132 if (u >= 256)
6133 return "???";
6134
6135 RTStrPrintf(pszBuf, 16, "%d way", u);
6136 return pszBuf;
6137}
6138
6139
6140/**
6141 * Get L2 cache associativity.
6142 */
6143const char *getL2CacheAss(unsigned u)
6144{
6145 switch (u)
6146 {
6147 case 0: return "off ";
6148 case 1: return "direct";
6149 case 2: return "2 way ";
6150 case 3: return "res3 ";
6151 case 4: return "4 way ";
6152 case 5: return "res5 ";
6153 case 6: return "8 way ";
6154 case 7: return "res7 ";
6155 case 8: return "16 way";
6156 case 9: return "res9 ";
6157 case 10: return "res10 ";
6158 case 11: return "res11 ";
6159 case 12: return "res12 ";
6160 case 13: return "res13 ";
6161 case 14: return "res14 ";
6162 case 15: return "fully ";
6163 default: return "????";
6164 }
6165}
6166
6167
6168/** CPUID(1).EDX field descriptions. */
6169static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6170{
6171 DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6172 DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6173 DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6174 DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6175 DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6176 DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6177 DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6178 DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6179 DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6180 DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6181 DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6182 DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6183 DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6184 DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6185 DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6186 DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6187 DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6188 DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6189 DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6190 DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6191 DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6192 DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6193 DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6194 DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6195 DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6196 DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6197 DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6198 DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6199 DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6200 DBGFREGSUBFIELD_TERMINATOR()
6201};
6202
6203/** CPUID(1).ECX field descriptions. */
6204static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6205{
6206 DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6207 DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6208 DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6209 DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6210 DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6211 DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6212 DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6213 DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6214 DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6215 DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6216 DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6217 DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6218 DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6219 DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6220 DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6221 DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6222 DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6223 DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6224 DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6225 DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6226 DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6227 DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6228 DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6229 DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6230 DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6231 DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6232 DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6233 DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6234 DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6235 DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6236 DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6237 DBGFREGSUBFIELD_TERMINATOR()
6238};
6239
6240/** CPUID(7,0).EBX field descriptions. */
6241static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6242{
6243 DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6244 DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6245 DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6246 DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6247 DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6248 DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6249 DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6250 DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6251 DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6252 DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6253 DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6254 DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6255 DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6256 DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6257 DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6258 DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6259 DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6260 DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6261 DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6262 DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6263 DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6264 DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6265 DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6266 DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6267 DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6268 DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6269 DBGFREGSUBFIELD_TERMINATOR()
6270};
6271
6272/** CPUID(7,0).ECX field descriptions. */
6273static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6274{
6275 DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6276 DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6277 DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6278 DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6279 DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6280 DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6281 DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6282 DBGFREGSUBFIELD_TERMINATOR()
6283};
6284
6285/** CPUID(7,0).EDX field descriptions. */
6286static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6287{
6288 DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
6289 DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6290 DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6291 DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
6292 DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6293 DBGFREGSUBFIELD_RO("CORECAP\0" "Supports IA32_CORE_CAP", 30, 1, 0),
6294 DBGFREGSUBFIELD_RO("SSBD\0" "Supports IA32_SPEC_CTRL.SSBD", 31, 1, 0),
6295 DBGFREGSUBFIELD_TERMINATOR()
6296};
6297
6298
6299/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6300static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6301{
6302 DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6303 DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6304 DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6305 DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6306 DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6307 DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6308 DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6309 DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6310 DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6311 DBGFREGSUBFIELD_TERMINATOR()
6312};
6313
6314/** CPUID(13,1).EAX field descriptions. */
6315static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6316{
6317 DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6318 DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6319 DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6320 DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6321 DBGFREGSUBFIELD_TERMINATOR()
6322};
6323
6324
6325/** CPUID(0x80000001,0).EDX field descriptions. */
6326static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6327{
6328 DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6329 DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6330 DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6331 DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6332 DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6333 DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6334 DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6335 DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6336 DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6337 DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6338 DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6339 DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6340 DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6341 DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6342 DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6343 DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6344 DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6345 DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6346 DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6347 DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6348 DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6349 DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6350 DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6351 DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6352 DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6353 DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6354 DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6355 DBGFREGSUBFIELD_TERMINATOR()
6356};
6357
6358/** CPUID(0x80000001,0).ECX field descriptions. */
6359static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6360{
6361 DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6362 DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6363 DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6364 DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6365 DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6366 DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6367 DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6368 DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6369 DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6370 DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6371 DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6372 DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6373 DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6374 DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6375 DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6376 DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6377 DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6378 DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6379 DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6380 DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6381 DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6382 DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6383 DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6384 DBGFREGSUBFIELD_RO("PCX_L2I\0" "L2I/L3 Performance Counter Extensions", 28, 1, 0),
6385 DBGFREGSUBFIELD_RO("MWAITX\0" "MWAITX and MONITORX instructions", 29, 1, 0),
6386 DBGFREGSUBFIELD_TERMINATOR()
6387};
6388
6389/** CPUID(0x8000000a,0).EDX field descriptions. */
6390static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6391{
6392 DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6393 DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6394 DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6395 DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6396 DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6397 DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6398 DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6399 DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6400 DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6401 DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6402 DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6403 DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6404 DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6405 DBGFREGSUBFIELD_RO("GMET\0" "Guest Mode Execute Trap Extension", 17, 1, 0),
6406 DBGFREGSUBFIELD_TERMINATOR()
6407};
6408
6409
6410/** CPUID(0x80000007,0).EDX field descriptions. */
6411static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6412{
6413 DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6414 DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6415 DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6416 DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6417 DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6418 DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6419 DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6420 DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6421 DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6422 DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6423 DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6424 DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6425 DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6426 DBGFREGSUBFIELD_TERMINATOR()
6427};
6428
6429/** CPUID(0x80000008,0).EBX field descriptions. */
6430static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6431{
6432 DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6433 DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6434 DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6435 DBGFREGSUBFIELD_RO("RDPRU\0" "RDPRU instruction", 4, 1, 0),
6436 DBGFREGSUBFIELD_RO("MCOMMIT\0" "MCOMMIT instruction", 8, 1, 0),
6437 DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6438 DBGFREGSUBFIELD_TERMINATOR()
6439};
6440
6441
6442static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6443 const char *pszLeadIn, uint32_t cchWidth)
6444{
6445 if (pszLeadIn)
6446 pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6447
6448 for (uint32_t iBit = 0; iBit < 32; iBit++)
6449 if (RT_BIT_32(iBit) & uVal)
6450 {
6451 while ( pDesc->pszName != NULL
6452 && iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6453 pDesc++;
6454 if ( pDesc->pszName != NULL
6455 && iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6456 {
6457 if (pDesc->cBits == 1)
6458 pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6459 else
6460 {
6461 uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6462 if (pDesc->cBits < 32)
6463 uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6464 pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6465 iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6466 }
6467 }
6468 else
6469 pHlp->pfnPrintf(pHlp, " %u", iBit);
6470 }
6471 if (pszLeadIn)
6472 pHlp->pfnPrintf(pHlp, "\n");
6473}
6474
6475
6476static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6477 const char *pszLeadIn, uint32_t cchWidth)
6478{
6479 if (pszLeadIn)
6480 pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6481
6482 for (uint32_t iBit = 0; iBit < 64; iBit++)
6483 if (RT_BIT_64(iBit) & uVal)
6484 {
6485 while ( pDesc->pszName != NULL
6486 && iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6487 pDesc++;
6488 if ( pDesc->pszName != NULL
6489 && iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6490 {
6491 if (pDesc->cBits == 1)
6492 pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6493 else
6494 {
6495 uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6496 if (pDesc->cBits < 64)
6497 uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6498 pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6499 iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6500 }
6501 }
6502 else
6503 pHlp->pfnPrintf(pHlp, " %u", iBit);
6504 }
6505 if (pszLeadIn)
6506 pHlp->pfnPrintf(pHlp, "\n");
6507}
6508
6509
6510static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6511 const char *pszLeadIn, uint32_t cchWidth)
6512{
6513 if (!uVal)
6514 pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6515 else
6516 {
6517 pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6518 cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6519 pHlp->pfnPrintf(pHlp, " )\n");
6520 }
6521}
6522
6523
6524static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6525 uint32_t cchWidth)
6526{
6527 uint32_t uCombined = uVal1 | uVal2;
6528 for (uint32_t iBit = 0; iBit < 32; iBit++)
6529 if ( (RT_BIT_32(iBit) & uCombined)
6530 || (iBit == pDesc->iFirstBit && pDesc->pszName) )
6531 {
6532 while ( pDesc->pszName != NULL
6533 && iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6534 pDesc++;
6535
6536 if ( pDesc->pszName != NULL
6537 && iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6538 {
6539 size_t cchMnemonic = strlen(pDesc->pszName);
6540 const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6541 size_t cchDesc = strlen(pszDesc);
6542 uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6543 uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6544 if (pDesc->cBits < 32)
6545 {
6546 uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6547 uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6548 }
6549
6550 pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%*s= %u (%u)\n" : " %s - %s%*s= %#x (%#x)\n",
6551 pDesc->pszName, pszDesc,
6552 cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6553 uFieldValue1, uFieldValue2);
6554
6555 iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6556 pDesc++;
6557 }
6558 else
6559 pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6560 RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6561 }
6562}
6563
6564
6565/**
6566 * Produces a detailed summary of standard leaf 0x00000001.
6567 *
6568 * @param pHlp The info helper functions.
6569 * @param pCurLeaf The 0x00000001 leaf.
6570 * @param fVerbose Whether to be very verbose or not.
6571 * @param fIntel Set if intel CPU.
6572 */
6573static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6574{
6575 Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6576 static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6577 uint32_t uEAX = pCurLeaf->uEax;
6578 uint32_t uEBX = pCurLeaf->uEbx;
6579
6580 pHlp->pfnPrintf(pHlp,
6581 "%36s %2d \tExtended: %d \tEffective: %d\n"
6582 "%36s %2d \tExtended: %d \tEffective: %d\n"
6583 "%36s %d\n"
6584 "%36s %d (%s)\n"
6585 "%36s %#04x\n"
6586 "%36s %d\n"
6587 "%36s %d\n"
6588 "%36s %#04x\n"
6589 ,
6590 "Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6591 "Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6592 "Stepping:", ASMGetCpuStepping(uEAX),
6593 "Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6594 "APIC ID:", (uEBX >> 24) & 0xff,
6595 "Logical CPUs:",(uEBX >> 16) & 0xff,
6596 "CLFLUSH Size:",(uEBX >> 8) & 0xff,
6597 "Brand ID:", (uEBX >> 0) & 0xff);
6598 if (fVerbose)
6599 {
6600 CPUMCPUID Host;
6601 ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6602 pHlp->pfnPrintf(pHlp, "Features\n");
6603 pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6604 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6605 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6606 }
6607 else
6608 {
6609 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6610 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6611 }
6612}
6613
6614
6615/**
6616 * Produces a detailed summary of standard leaf 0x00000007.
6617 *
6618 * @param pHlp The info helper functions.
6619 * @param paLeaves The CPUID leaves array.
6620 * @param cLeaves The number of leaves in the array.
6621 * @param pCurLeaf The first 0x00000007 leaf.
6622 * @param fVerbose Whether to be very verbose or not.
6623 */
6624static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6625 PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6626{
6627 Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6628 pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6629 for (;;)
6630 {
6631 CPUMCPUID Host;
6632 ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6633
6634 switch (pCurLeaf->uSubLeaf)
6635 {
6636 case 0:
6637 if (fVerbose)
6638 {
6639 pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6640 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6641 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6642 if (pCurLeaf->uEdx || Host.uEdx)
6643 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6644 }
6645 else
6646 {
6647 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6648 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6649 if (pCurLeaf->uEdx)
6650 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6651 }
6652 break;
6653
6654 default:
6655 if (pCurLeaf->uEdx || pCurLeaf->uEcx || pCurLeaf->uEbx)
6656 pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6657 pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6658 break;
6659
6660 }
6661
6662 /* advance. */
6663 pCurLeaf++;
6664 if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6665 || pCurLeaf->uLeaf != 0x7)
6666 break;
6667 }
6668}
6669
6670
6671/**
6672 * Produces a detailed summary of standard leaf 0x0000000d.
6673 *
6674 * @param pHlp The info helper functions.
6675 * @param paLeaves The CPUID leaves array.
6676 * @param cLeaves The number of leaves in the array.
6677 * @param pCurLeaf The first 0x00000007 leaf.
6678 * @param fVerbose Whether to be very verbose or not.
6679 */
6680static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6681 PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6682{
6683 RT_NOREF_PV(fVerbose);
6684 Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6685 pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6686 for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6687 {
6688 CPUMCPUID Host;
6689 ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6690
6691 switch (uSubLeaf)
6692 {
6693 case 0:
6694 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6695 pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6696 pCurLeaf->uEbx, pCurLeaf->uEcx);
6697 pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6698
6699 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6700 cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6701 "Valid XCR0 bits, guest:", 42);
6702 cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6703 "Valid XCR0 bits, host:", 42);
6704 break;
6705
6706 case 1:
6707 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6708 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6709 cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6710
6711 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6712 pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0|XSS, guest:", pCurLeaf->uEbx);
6713 pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0|XSS, host:", Host.uEbx);
6714
6715 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6716 cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6717 " Valid IA32_XSS bits, guest:", 42);
6718 cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6719 " Valid IA32_XSS bits, host:", 42);
6720 break;
6721
6722 default:
6723 if ( pCurLeaf
6724 && pCurLeaf->uSubLeaf == uSubLeaf
6725 && (pCurLeaf->uEax || pCurLeaf->uEbx || pCurLeaf->uEcx || pCurLeaf->uEdx) )
6726 {
6727 pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6728 pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6729 if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6730 pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6731 if (pCurLeaf->uEdx)
6732 pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6733 pHlp->pfnPrintf(pHlp, " --");
6734 cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6735 pHlp->pfnPrintf(pHlp, "\n");
6736 }
6737 if (Host.uEax || Host.uEbx || Host.uEcx || Host.uEdx)
6738 {
6739 pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6740 Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6741 if (Host.uEcx & ~RT_BIT_32(0))
6742 pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6743 if (Host.uEdx)
6744 pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6745 pHlp->pfnPrintf(pHlp, " --");
6746 cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6747 pHlp->pfnPrintf(pHlp, "\n");
6748 }
6749 break;
6750
6751 }
6752
6753 /* advance. */
6754 if (pCurLeaf)
6755 {
6756 while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6757 && pCurLeaf->uSubLeaf <= uSubLeaf
6758 && pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6759 pCurLeaf++;
6760 if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6761 || pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6762 pCurLeaf = NULL;
6763 }
6764 }
6765}
6766
6767
6768static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6769 PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6770{
6771 if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6772 && pCurLeaf->uLeaf <= uUpToLeaf)
6773 {
6774 pHlp->pfnPrintf(pHlp,
6775 " %s\n"
6776 " Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6777 while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6778 && pCurLeaf->uLeaf <= uUpToLeaf)
6779 {
6780 CPUMCPUID Host;
6781 ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6782 pHlp->pfnPrintf(pHlp,
6783 "Gst: %08x/%04x %08x %08x %08x %08x\n"
6784 "Hst: %08x %08x %08x %08x\n",
6785 pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6786 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6787 pCurLeaf++;
6788 }
6789 }
6790
6791 return pCurLeaf;
6792}
6793
6794
6795/**
6796 * Display the guest CpuId leaves.
6797 *
6798 * @param pVM The cross context VM structure.
6799 * @param pHlp The info helper functions.
6800 * @param pszArgs "terse", "default" or "verbose".
6801 */
6802DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6803{
6804 /*
6805 * Parse the argument.
6806 */
6807 unsigned iVerbosity = 1;
6808 if (pszArgs)
6809 {
6810 pszArgs = RTStrStripL(pszArgs);
6811 if (!strcmp(pszArgs, "terse"))
6812 iVerbosity--;
6813 else if (!strcmp(pszArgs, "verbose"))
6814 iVerbosity++;
6815 }
6816
6817 uint32_t uLeaf;
6818 CPUMCPUID Host;
6819 uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6820 PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6821 PCCPUMCPUIDLEAF pCurLeaf;
6822 PCCPUMCPUIDLEAF pNextLeaf;
6823 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6824 pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6825 pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6826
6827 /*
6828 * Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6829 */
6830 uint32_t cHstMax = ASMCpuId_EAX(0);
6831 uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6832 uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6833 pHlp->pfnPrintf(pHlp,
6834 " Raw Standard CPUID Leaves\n"
6835 " Leaf/sub-leaf eax ebx ecx edx\n");
6836 for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6837 {
6838 uint32_t cMaxSubLeaves = 1;
6839 if (uLeaf == 4 || uLeaf == 7 || uLeaf == 0xb)
6840 cMaxSubLeaves = 16;
6841 else if (uLeaf == 0xd)
6842 cMaxSubLeaves = 128;
6843
6844 for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6845 {
6846 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6847 if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6848 && pCurLeaf->uLeaf == uLeaf
6849 && pCurLeaf->uSubLeaf == uSubLeaf)
6850 {
6851 pHlp->pfnPrintf(pHlp,
6852 "Gst: %08x/%04x %08x %08x %08x %08x\n"
6853 "Hst: %08x %08x %08x %08x\n",
6854 uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6855 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6856 pCurLeaf++;
6857 }
6858 else if ( uLeaf != 0xd
6859 || uSubLeaf <= 1
6860 || Host.uEbx != 0 )
6861 pHlp->pfnPrintf(pHlp,
6862 "Hst: %08x/%04x %08x %08x %08x %08x\n",
6863 uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6864
6865 /* Done? */
6866 if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6867 || pCurLeaf->uLeaf != uLeaf)
6868 && ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 || (Host.uEax & 0x000f) >= 8))
6869 || (uLeaf == 0x7 && Host.uEax == 0)
6870 || (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 || (Host.uEcx & 0xff00) >= 8))
6871 || (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6872 || (uLeaf == 0xd && uSubLeaf >= 128)
6873 )
6874 )
6875 break;
6876 }
6877 }
6878 pNextLeaf = pCurLeaf;
6879
6880 /*
6881 * If verbose, decode it.
6882 */
6883 if (iVerbosity && paLeaves[0].uLeaf == 0)
6884 pHlp->pfnPrintf(pHlp,
6885 "%36s %.04s%.04s%.04s\n"
6886 "%36s 0x00000000-%#010x\n"
6887 ,
6888 "Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6889 "Supports:", paLeaves[0].uEax);
6890
6891 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6892 cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6893
6894 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6895 cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6896
6897 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6898 cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6899
6900 pCurLeaf = pNextLeaf;
6901
6902 /*
6903 * Hypervisor leaves.
6904 *
6905 * Unlike most of the other leaves reported, the guest hypervisor leaves
6906 * aren't a subset of the host CPUID bits.
6907 */
6908 pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6909
6910 ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6911 cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6912 cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6913 ? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6914 cMax = RT_MAX(cHstMax, cGstMax);
6915 if (cMax >= UINT32_C(0x40000000))
6916 {
6917 pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6918
6919 /** @todo dump these in more detail. */
6920
6921 pCurLeaf = pNextLeaf;
6922 }
6923
6924
6925 /*
6926 * Extended. Custom raw dump here due to ECX sub-leaves host handling.
6927 * Implemented after AMD specs.
6928 */
6929 pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6930
6931 ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6932 cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6933 cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6934 ? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6935 cMax = RT_MAX(cHstMax, cGstMax);
6936 if (cMax >= UINT32_C(0x80000000))
6937 {
6938
6939 pHlp->pfnPrintf(pHlp,
6940 " Raw Extended CPUID Leaves\n"
6941 " Leaf/sub-leaf eax ebx ecx edx\n");
6942 PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6943 for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6944 {
6945 uint32_t cMaxSubLeaves = 1;
6946 if (uLeaf == UINT32_C(0x8000001d))
6947 cMaxSubLeaves = 16;
6948
6949 for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6950 {
6951 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6952 if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6953 && pCurLeaf->uLeaf == uLeaf
6954 && pCurLeaf->uSubLeaf == uSubLeaf)
6955 {
6956 pHlp->pfnPrintf(pHlp,
6957 "Gst: %08x/%04x %08x %08x %08x %08x\n"
6958 "Hst: %08x %08x %08x %08x\n",
6959 uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6960 Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6961 pCurLeaf++;
6962 }
6963 else if ( uLeaf != 0xd
6964 || uSubLeaf <= 1
6965 || Host.uEbx != 0 )
6966 pHlp->pfnPrintf(pHlp,
6967 "Hst: %08x/%04x %08x %08x %08x %08x\n",
6968 uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6969
6970 /* Done? */
6971 if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6972 || pCurLeaf->uLeaf != uLeaf)
6973 && (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 || (Host.uEax & 0x000f) >= 8)) )
6974 break;
6975 }
6976 }
6977 pNextLeaf = pCurLeaf;
6978
6979 /*
6980 * Understandable output
6981 */
6982 if (iVerbosity)
6983 pHlp->pfnPrintf(pHlp,
6984 "Ext Name: %.4s%.4s%.4s\n"
6985 "Ext Supports: 0x80000000-%#010x\n",
6986 &pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6987
6988 pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6989 if (iVerbosity && pCurLeaf)
6990 {
6991 uint32_t uEAX = pCurLeaf->uEax;
6992 pHlp->pfnPrintf(pHlp,
6993 "Family: %d \tExtended: %d \tEffective: %d\n"
6994 "Model: %d \tExtended: %d \tEffective: %d\n"
6995 "Stepping: %d\n"
6996 "Brand ID: %#05x\n",
6997 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6998 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6999 ASMGetCpuStepping(uEAX),
7000 pCurLeaf->uEbx & 0xfff);
7001
7002 if (iVerbosity == 1)
7003 {
7004 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
7005 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
7006 }
7007 else
7008 {
7009 ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7010 pHlp->pfnPrintf(pHlp, "Ext Features\n");
7011 pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
7012 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
7013 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
7014 if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
7015 {
7016 pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
7017 ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7018 pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
7019 uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
7020 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
7021 }
7022 }
7023 }
7024
7025 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
7026 {
7027 char szString[4*4*3+1] = {0};
7028 uint32_t *pu32 = (uint32_t *)szString;
7029 *pu32++ = pCurLeaf->uEax;
7030 *pu32++ = pCurLeaf->uEbx;
7031 *pu32++ = pCurLeaf->uEcx;
7032 *pu32++ = pCurLeaf->uEdx;
7033 pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
7034 if (pCurLeaf)
7035 {
7036 *pu32++ = pCurLeaf->uEax;
7037 *pu32++ = pCurLeaf->uEbx;
7038 *pu32++ = pCurLeaf->uEcx;
7039 *pu32++ = pCurLeaf->uEdx;
7040 }
7041 pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
7042 if (pCurLeaf)
7043 {
7044 *pu32++ = pCurLeaf->uEax;
7045 *pu32++ = pCurLeaf->uEbx;
7046 *pu32++ = pCurLeaf->uEcx;
7047 *pu32++ = pCurLeaf->uEdx;
7048 }
7049 pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
7050 }
7051
7052 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
7053 {
7054 uint32_t uEAX = pCurLeaf->uEax;
7055 uint32_t uEBX = pCurLeaf->uEbx;
7056 uint32_t uECX = pCurLeaf->uEcx;
7057 uint32_t uEDX = pCurLeaf->uEdx;
7058 char sz1[32];
7059 char sz2[32];
7060
7061 pHlp->pfnPrintf(pHlp,
7062 "TLB 2/4M Instr/Uni: %s %3d entries\n"
7063 "TLB 2/4M Data: %s %3d entries\n",
7064 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
7065 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
7066 pHlp->pfnPrintf(pHlp,
7067 "TLB 4K Instr/Uni: %s %3d entries\n"
7068 "TLB 4K Data: %s %3d entries\n",
7069 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
7070 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
7071 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
7072 "L1 Instr Cache Lines Per Tag: %d\n"
7073 "L1 Instr Cache Associativity: %s\n"
7074 "L1 Instr Cache Size: %d KB\n",
7075 (uEDX >> 0) & 0xff,
7076 (uEDX >> 8) & 0xff,
7077 getCacheAss((uEDX >> 16) & 0xff, sz1),
7078 (uEDX >> 24) & 0xff);
7079 pHlp->pfnPrintf(pHlp,
7080 "L1 Data Cache Line Size: %d bytes\n"
7081 "L1 Data Cache Lines Per Tag: %d\n"
7082 "L1 Data Cache Associativity: %s\n"
7083 "L1 Data Cache Size: %d KB\n",
7084 (uECX >> 0) & 0xff,
7085 (uECX >> 8) & 0xff,
7086 getCacheAss((uECX >> 16) & 0xff, sz1),
7087 (uECX >> 24) & 0xff);
7088 }
7089
7090 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
7091 {
7092 uint32_t uEAX = pCurLeaf->uEax;
7093 uint32_t uEBX = pCurLeaf->uEbx;
7094 uint32_t uEDX = pCurLeaf->uEdx;
7095
7096 pHlp->pfnPrintf(pHlp,
7097 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
7098 "L2 TLB 2/4M Data: %s %4d entries\n",
7099 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
7100 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
7101 pHlp->pfnPrintf(pHlp,
7102 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
7103 "L2 TLB 4K Data: %s %4d entries\n",
7104 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
7105 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
7106 pHlp->pfnPrintf(pHlp,
7107 "L2 Cache Line Size: %d bytes\n"
7108 "L2 Cache Lines Per Tag: %d\n"
7109 "L2 Cache Associativity: %s\n"
7110 "L2 Cache Size: %d KB\n",
7111 (uEDX >> 0) & 0xff,
7112 (uEDX >> 8) & 0xf,
7113 getL2CacheAss((uEDX >> 12) & 0xf),
7114 (uEDX >> 16) & 0xffff);
7115 }
7116
7117 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
7118 {
7119 ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7120 if (pCurLeaf->uEdx || (Host.uEdx && iVerbosity))
7121 {
7122 if (iVerbosity < 1)
7123 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7124 else
7125 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7126 }
7127 }
7128
7129 pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7130 if (pCurLeaf != NULL)
7131 {
7132 ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7133 if (pCurLeaf->uEbx || (Host.uEbx && iVerbosity))
7134 {
7135 if (iVerbosity < 1)
7136 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7137 else
7138 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7139 }
7140
7141 if (iVerbosity)
7142 {
7143 uint32_t uEAX = pCurLeaf->uEax;
7144 uint32_t uECX = pCurLeaf->uEcx;
7145
7146 /** @todo 0x80000008:EAX[23:16] is only defined for AMD. We'll get 0 on Intel. On
7147 * AMD if we get 0, the guest physical address width should be taken from
7148 * 0x80000008:EAX[7:0] instead. Guest Physical address width is relevant
7149 * for guests using nested paging. */
7150 pHlp->pfnPrintf(pHlp,
7151 "Physical Address Width: %d bits\n"
7152 "Virtual Address Width: %d bits\n"
7153 "Guest Physical Address Width: %d bits\n",
7154 (uEAX >> 0) & 0xff,
7155 (uEAX >> 8) & 0xff,
7156 (uEAX >> 16) & 0xff);
7157
7158 /** @todo 0x80000008:ECX is reserved on Intel (we'll get incorrect physical core
7159 * count here). */
7160 pHlp->pfnPrintf(pHlp,
7161 "Physical Core Count: %d\n",
7162 ((uECX >> 0) & 0xff) + 1);
7163 }
7164 }
7165
7166 pCurLeaf = pNextLeaf;
7167 }
7168
7169
7170
7171 /*
7172 * Centaur.
7173 */
7174 pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7175
7176 ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7177 cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7178 ? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7179 cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7180 ? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7181 cMax = RT_MAX(cHstMax, cGstMax);
7182 if (cMax >= UINT32_C(0xc0000000))
7183 {
7184 pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7185
7186 /*
7187 * Understandable output
7188 */
7189 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7190 pHlp->pfnPrintf(pHlp,
7191 "Centaur Supports: 0xc0000000-%#010x\n",
7192 pCurLeaf->uEax);
7193
7194 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7195 {
7196 ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7197 uint32_t uEdxGst = pCurLeaf->uEdx;
7198 uint32_t uEdxHst = Host.uEdx;
7199
7200 if (iVerbosity == 1)
7201 {
7202 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7203 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7204 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7205 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7206 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7207 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7208 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7209 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7210 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7211 /* possibly indicating MM/HE and MM/HE-E on older chips... */
7212 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7213 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7214 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7215 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7216 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7217 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7218 for (unsigned iBit = 14; iBit < 32; iBit++)
7219 if (uEdxGst & RT_BIT(iBit))
7220 pHlp->pfnPrintf(pHlp, " %d", iBit);
7221 pHlp->pfnPrintf(pHlp, "\n");
7222 }
7223 else
7224 {
7225 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7226 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7227 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7228 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7229 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7230 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7231 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7232 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7233 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7234 /* possibly indicating MM/HE and MM/HE-E on older chips... */
7235 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7236 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7237 pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7238 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7239 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7240 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7241 pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7242 pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7243 pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7244 pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7245 pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7246 pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7247 pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7248 pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7249 pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7250 pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7251 pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7252 pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7253 pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7254 for (unsigned iBit = 27; iBit < 32; iBit++)
7255 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
7256 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7257 pHlp->pfnPrintf(pHlp, "\n");
7258 }
7259 }
7260
7261 pCurLeaf = pNextLeaf;
7262 }
7263
7264 /*
7265 * The remainder.
7266 */
7267 pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7268}
7269
7270#endif /* !IN_VBOX_CPU_REPORT */
7271
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