CPUMR3Db.cpp@ 58591

Last change on this file since 58591 was 58569, checked in by vboxsync, 9 years ago
VMM: Added intel skylake CPU profile.
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1	/* $Id: CPUMR3Db.cpp 58569 2015-11-04 14:28:31Z vboxsync $ */
2	/** @file
3	* CPUM - CPU database part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/mm.h>
27
28	#include <VBox/err.h>
29	#include <iprt/asm-amd64-x86.h>
30	#include <iprt/mem.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Structures and Typedefs *
36	*********************************************************************************************************************************/
37	typedef struct CPUMDBENTRY
38	{
39	/** The CPU name. */
40	const char *pszName;
41	/** The full CPU name. */
42	const char *pszFullName;
43	/** The CPU vendor (CPUMCPUVENDOR). */
44	uint8_t enmVendor;
45	/** The CPU family. */
46	uint8_t uFamily;
47	/** The CPU model. */
48	uint8_t uModel;
49	/** The CPU stepping. */
50	uint8_t uStepping;
51	/** The microarchitecture. */
52	CPUMMICROARCH enmMicroarch;
53	/** Scalable bus frequency used for reporting other frequencies. */
54	uint64_t uScalableBusFreq;
55	/** Flags (TBD). */
56	uint32_t fFlags;
57	/** The maximum physical address with of the CPU. This should correspond to
58	* the value in CPUID leaf 0x80000008 when present. */
59	uint8_t cMaxPhysAddrWidth;
60	/** Pointer to an array of CPUID leaves. */
61	PCCPUMCPUIDLEAF paCpuIdLeaves;
62	/** The number of CPUID leaves in the array paCpuIdLeaves points to. */
63	uint32_t cCpuIdLeaves;
64	/** The method used to deal with unknown CPUID leaves. */
65	CPUMUNKNOWNCPUID enmUnknownCpuId;
66	/** The default unknown CPUID value. */
67	CPUMCPUID DefUnknownCpuId;
68
69	/** MSR mask. Several microarchitectures ignore higher bits of the */
70	uint32_t fMsrMask;
71
72	/** The number of ranges in the table pointed to b paMsrRanges. */
73	uint32_t cMsrRanges;
74	/** MSR ranges for this CPU. */
75	PCCPUMMSRRANGE paMsrRanges;
76	} CPUMDBENTRY;
77
78
79	/*********************************************************************************************************************************
80	* Defined Constants And Macros *
81	*********************************************************************************************************************************/
82
83	/** @def NULL_ALONE
84	* For eliminating an unnecessary data dependency in standalone builds (for
85	* VBoxSVC). */
86	/** @def ZERO_ALONE
87	* For eliminating an unnecessary data size dependency in standalone builds (for
88	* VBoxSVC). */
89	#ifndef CPUM_DB_STANDALONE
90	# define NULL_ALONE(a_aTable) a_aTable
91	# define ZERO_ALONE(a_cTable) a_cTable
92	#else
93	# define NULL_ALONE(a_aTable) NULL
94	# define ZERO_ALONE(a_cTable) 0
95	#endif
96
97
98	/** @name Short macros for the MSR range entries.
99	*
100	* These are rather cryptic, but this is to reduce the attack on the right
101	* margin.
102	*
103	* @{ */
104	/** Alias one MSR onto another (a_uTarget). */
105	#define MAL(a_uMsr, a_szName, a_uTarget) \
106	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
107	/** Functions handles everything. */
108	#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
109	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
110	/** Functions handles everything, with GP mask. */
111	#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
112	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
113	/** Function handlers, read-only. */
114	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
115	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
116	/** Function handlers, ignore all writes. */
117	#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
118	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
119	/** Function handlers, with value. */
120	#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
121	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
122	/** Function handlers, with write ignore mask. */
123	#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
124	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
125	/** Function handlers, extended version. */
126	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
127	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
128	/** Function handlers, with CPUMCPU storage variable. */
129	#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
130	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
131	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
132	/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
133	#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
134	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
135	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
136	/** Read-only fixed value. */
137	#define MVO(a_uMsr, a_szName, a_uValue) \
138	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
139	/** Read-only fixed value, ignores all writes. */
140	#define MVI(a_uMsr, a_szName, a_uValue) \
141	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
142	/** Read fixed value, ignore writes outside GP mask. */
143	#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
144	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
145	/** Read fixed value, extended version with both GP and ignore masks. */
146	#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
147	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
148	/** The short form, no CPUM backing. */
149	#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
150	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
151	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
152
153	/** Range: Functions handles everything. */
154	#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
155	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
156	/** Range: Read fixed value, read-only. */
157	#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
158	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
159	/** Range: Read fixed value, ignore writes. */
160	#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
161	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
162	/** Range: The short form, no CPUM backing. */
163	#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
164	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
165	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
166
167	/** Internal form used by the macros. */
168	#ifdef VBOX_WITH_STATISTICS
169	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
170	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
171	{ 0 }, { 0 }, { 0 }, { 0 } }
172	#else
173	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
174	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
175	#endif
176	/** @} */
177
178
179	#include "cpus/Intel_Core_i7_5600U.h"
180	#include "cpus/Intel_Core_i7_3960X.h"
181	#include "cpus/Intel_Core_i5_3570.h"
182	#include "cpus/Intel_Core_i7_2635QM.h"
183	#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
184	#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
185	#include "cpus/Intel_Pentium_4_3_00GHz.h"
186	#include "cpus/Intel_Atom_330_1_60GHz.h"
187
188	#include "cpus/AMD_FX_8150_Eight_Core.h"
189	#include "cpus/AMD_Phenom_II_X6_1100T.h"
190	#include "cpus/Quad_Core_AMD_Opteron_2384.h"
191	#include "cpus/AMD_Athlon_64_X2_Dual_Core_4200.h"
192	#include "cpus/AMD_Athlon_64_3200.h"
193
194	#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
195
196
197
198	/**
199	* The database entries.
200	*
201	* 1. The first entry is special. It is the fallback for unknown
202	* processors. Thus, it better be pretty representative.
203	*
204	* 2. The first entry for a CPU vendor is likewise important as it is
205	* the default entry for that vendor.
206	*
207	* Generally we put the most recent CPUs first, since these tend to have the
208	* most complicated and backwards compatible list of MSRs.
209	*/
210	static CPUMDBENTRY const * const g_apCpumDbEntries[] =
211	{
212	#ifdef VBOX_CPUDB_Intel_Core_i7_6700K
213	&g_Entry_Intel_Core_i7_6700K,
214	#endif
215	#ifdef VBOX_CPUDB_Intel_Core_i7_5600U
216	&g_Entry_Intel_Core_i7_5600U,
217	#endif
218	#ifdef VBOX_CPUDB_Intel_Core_i5_3570
219	&g_Entry_Intel_Core_i5_3570,
220	#endif
221	#ifdef VBOX_CPUDB_Intel_Core_i7_3960X
222	&g_Entry_Intel_Core_i7_3960X,
223	#endif
224	#ifdef VBOX_CPUDB_Intel_Core_i7_2635QM
225	&g_Entry_Intel_Core_i7_2635QM,
226	#endif
227	#ifdef VBOX_CPUDB_Intel_Atom_330_1_60GHz
228	&g_Entry_Intel_Atom_330_1_60GHz,
229	#endif
230	#ifdef Intel_Pentium_M_processor_2_00GHz
231	&g_Entry_Intel_Pentium_M_processor_2_00GHz,
232	#endif
233	#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz
234	&g_Entry_Intel_Xeon_X5482_3_20GHz,
235	#endif
236	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz
237	&g_Entry_Intel_Pentium_4_3_00GHz,
238	#endif
239
240	#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core
241	&g_Entry_AMD_FX_8150_Eight_Core,
242	#endif
243	#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T
244	&g_Entry_AMD_Phenom_II_X6_1100T,
245	#endif
246	#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384
247	&g_Entry_Quad_Core_AMD_Opteron_2384,
248	#endif
249	#ifdef VBOX_CPUDB_AMD_Athlon_64_X2_Dual_Core_4200
250	&g_Entry_AMD_Athlon_64_X2_Dual_Core_4200,
251	#endif
252	#ifdef VBOX_CPUDB_AMD_Athlon_64_3200
253	&g_Entry_AMD_Athlon_64_3200,
254	#endif
255
256	#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz
257	&g_Entry_VIA_QuadCore_L4700_1_2_GHz,
258	#endif
259	};
260
261
262	#ifndef CPUM_DB_STANDALONE
263
264	/**
265	* Binary search used by cpumR3MsrRangesInsert and has some special properties
266	* wrt to mismatches.
267	*
268	* @returns Insert location.
269	* @param paMsrRanges The MSR ranges to search.
270	* @param cMsrRanges The number of MSR ranges.
271	* @param uMsr What to search for.
272	*/
273	static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
274	{
275	if (!cMsrRanges)
276	return 0;
277
278	uint32_t iStart = 0;
279	uint32_t iLast = cMsrRanges - 1;
280	for (;;)
281	{
282	uint32_t i = iStart + (iLast - iStart + 1) / 2;
283	if ( uMsr >= paMsrRanges[i].uFirst
284	&& uMsr <= paMsrRanges[i].uLast)
285	return i;
286	if (uMsr < paMsrRanges[i].uFirst)
287	{
288	if (i <= iStart)
289	return i;
290	iLast = i - 1;
291	}
292	else
293	{
294	if (i >= iLast)
295	{
296	if (i < cMsrRanges)
297	i++;
298	return i;
299	}
300	iStart = i + 1;
301	}
302	}
303	}
304
305
306	/**
307	* Ensures that there is space for at least @a cNewRanges in the table,
308	* reallocating the table if necessary.
309	*
310	* @returns Pointer to the MSR ranges on success, NULL on failure. On failure
311	* @a *ppaMsrRanges is freed and set to NULL.
312	* @param pVM The cross context VM structure. If NULL,
313	* use the process heap, otherwise the VM's hyper heap.
314	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
315	* @param cMsrRanges The current number of ranges.
316	* @param cNewRanges The number of ranges to be added.
317	*/
318	static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
319	{
320	uint32_t cMsrRangesAllocated;
321	if (!pVM)
322	cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
323	else
324	{
325	/*
326	* We're using the hyper heap now, but when the range array was copied over to it from
327	* the host-context heap, we only copy the exact size and not the ensured size.
328	* See @bugref{7270}.
329	*/
330	cMsrRangesAllocated = cMsrRanges;
331	}
332	if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
333	{
334	void *pvNew;
335	uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
336	if (pVM)
337	{
338	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
339	Assert(cMsrRanges == pVM->cpum.s.GuestInfo.cMsrRanges);
340
341	size_t cb = cMsrRangesAllocated * sizeof(**ppaMsrRanges);
342	size_t cbNew = cNew * sizeof(**ppaMsrRanges);
343	int rc = MMR3HyperRealloc(pVM, *ppaMsrRanges, cb, 32, MM_TAG_CPUM_MSRS, cbNew, &pvNew);
344	if (RT_FAILURE(rc))
345	{
346	*ppaMsrRanges = NULL;
347	pVM->cpum.s.GuestInfo.paMsrRangesR0 = NIL_RTR0PTR;
348	pVM->cpum.s.GuestInfo.paMsrRangesRC = NIL_RTRCPTR;
349	LogRel(("CPUM: cpumR3MsrRangesEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
350	return NULL;
351	}
352	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
353	}
354	else
355	{
356	pvNew = RTMemRealloc(ppaMsrRanges, cNew sizeof(**ppaMsrRanges));
357	if (!pvNew)
358	{
359	RTMemFree(*ppaMsrRanges);
360	*ppaMsrRanges = NULL;
361	return NULL;
362	}
363	}
364	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
365	}
366
367	if (pVM)
368	{
369	/* Update R0 and RC pointers. */
370	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
371	pVM->cpum.s.GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, *ppaMsrRanges);
372	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, *ppaMsrRanges);
373	}
374
375	return *ppaMsrRanges;
376	}
377
378
379	/**
380	* Inserts a new MSR range in into an sorted MSR range array.
381	*
382	* If the new MSR range overlaps existing ranges, the existing ones will be
383	* adjusted/removed to fit in the new one.
384	*
385	* @returns VBox status code.
386	* @retval VINF_SUCCESS
387	* @retval VERR_NO_MEMORY
388	*
389	* @param pVM The cross context VM structure. If NULL,
390	* use the process heap, otherwise the VM's hyper heap.
391	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
392	* Must be NULL if using the hyper heap.
393	* @param pcMsrRanges The variable holding number of ranges. Must be NULL
394	* if using the hyper heap.
395	* @param pNewRange The new range.
396	*/
397	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange)
398	{
399	Assert(pNewRange->uLast >= pNewRange->uFirst);
400	Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
401	Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
402
403	/*
404	* Validate and use the VM's MSR ranges array if we are using the hyper heap.
405	*/
406	if (pVM)
407	{
408	AssertReturn(!ppaMsrRanges, VERR_INVALID_PARAMETER);
409	AssertReturn(!pcMsrRanges, VERR_INVALID_PARAMETER);
410
411	ppaMsrRanges = &pVM->cpum.s.GuestInfo.paMsrRangesR3;
412	pcMsrRanges = &pVM->cpum.s.GuestInfo.cMsrRanges;
413	}
414
415	uint32_t cMsrRanges = *pcMsrRanges;
416	PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
417
418	/*
419	* Optimize the linear insertion case where we add new entries at the end.
420	*/
421	if ( cMsrRanges > 0
422	&& paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
423	{
424	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
425	if (!paMsrRanges)
426	return VERR_NO_MEMORY;
427	paMsrRanges[cMsrRanges] = *pNewRange;
428	*pcMsrRanges += 1;
429	}
430	else
431	{
432	uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
433	Assert(i == cMsrRanges \|\| pNewRange->uFirst <= paMsrRanges[i].uLast);
434	Assert(i == 0 \|\| pNewRange->uFirst > paMsrRanges[i - 1].uLast);
435
436	/*
437	* Adding an entirely new entry?
438	*/
439	if ( i >= cMsrRanges
440	\|\| pNewRange->uLast < paMsrRanges[i].uFirst)
441	{
442	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
443	if (!paMsrRanges)
444	return VERR_NO_MEMORY;
445	if (i < cMsrRanges)
446	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
447	paMsrRanges[i] = *pNewRange;
448	*pcMsrRanges += 1;
449	}
450	/*
451	* Replace existing entry?
452	*/
453	else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
454	&& pNewRange->uLast == paMsrRanges[i].uLast)
455	paMsrRanges[i] = *pNewRange;
456	/*
457	* Splitting an existing entry?
458	*/
459	else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
460	&& pNewRange->uLast < paMsrRanges[i].uLast)
461	{
462	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 2);
463	if (!paMsrRanges)
464	return VERR_NO_MEMORY;
465	if (i < cMsrRanges)
466	memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
467	paMsrRanges[i + 1] = *pNewRange;
468	paMsrRanges[i + 2] = paMsrRanges[i];
469	paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
470	paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
471	*pcMsrRanges += 2;
472	}
473	/*
474	* Complicated scenarios that can affect more than one range.
475	*
476	* The current code does not optimize memmove calls when replacing
477	* one or more existing ranges, because it's tedious to deal with and
478	* not expected to be a frequent usage scenario.
479	*/
480	else
481	{
482	/* Adjust start of first match? */
483	if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
484	&& pNewRange->uLast < paMsrRanges[i].uLast)
485	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
486	else
487	{
488	/* Adjust end of first match? */
489	if (pNewRange->uFirst > paMsrRanges[i].uFirst)
490	{
491	Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
492	paMsrRanges[i].uLast = pNewRange->uFirst - 1;
493	i++;
494	}
495	/* Replace the whole first match (lazy bird). */
496	else
497	{
498	if (i + 1 < cMsrRanges)
499	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
500	cMsrRanges = *pcMsrRanges -= 1;
501	}
502
503	/* Do the new range affect more ranges? */
504	while ( i < cMsrRanges
505	&& pNewRange->uLast >= paMsrRanges[i].uFirst)
506	{
507	if (pNewRange->uLast < paMsrRanges[i].uLast)
508	{
509	/* Adjust the start of it, then we're done. */
510	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
511	break;
512	}
513
514	/* Remove it entirely. */
515	if (i + 1 < cMsrRanges)
516	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
517	cMsrRanges = *pcMsrRanges -= 1;
518	}
519	}
520
521	/* Now, perform a normal insertion. */
522	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
523	if (!paMsrRanges)
524	return VERR_NO_MEMORY;
525	if (i < cMsrRanges)
526	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
527	paMsrRanges[i] = *pNewRange;
528	*pcMsrRanges += 1;
529	}
530	}
531
532	return VINF_SUCCESS;
533	}
534
535
536	/**
537	* Worker for cpumR3MsrApplyFudge that applies one table.
538	*
539	* @returns VBox status code.
540	* @param pVM The cross context VM structure.
541	* @param paRanges Array of MSRs to fudge.
542	* @param cRanges Number of MSRs in the array.
543	*/
544	static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
545	{
546	for (uint32_t i = 0; i < cRanges; i++)
547	if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
548	{
549	LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
550	int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
551	&paRanges[i]);
552	if (RT_FAILURE(rc))
553	return rc;
554	}
555	return VINF_SUCCESS;
556	}
557
558
559	/**
560	* Fudges the MSRs that guest are known to access in some odd cases.
561	*
562	* A typical example is a VM that has been moved between different hosts where
563	* for instance the cpu vendor differs.
564	*
565	* @returns VBox status code.
566	* @param pVM The cross context VM structure.
567	*/
568	int cpumR3MsrApplyFudge(PVM pVM)
569	{
570	/*
571	* Basic.
572	*/
573	static CPUMMSRRANGE const s_aFudgeMsrs[] =
574	{
575	MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
576	MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
577	MVO(0x00000017, "IA32_PLATFORM_ID", 0),
578	MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
579	MVI(0x0000008b, "BIOS_SIGN", 0),
580	MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
581	MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
582	MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
583	MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
584	MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
585	MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
586	MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
587	MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
588	MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
589	MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
590	MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
591	MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
592	};
593	int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
594	AssertLogRelRCReturn(rc, rc);
595
596	/*
597	* XP might mistake opterons and other newer CPUs for P4s.
598	*/
599	if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
600	{
601	static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
602	{
603	MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
604	};
605	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
606	AssertLogRelRCReturn(rc, rc);
607	}
608
609	return rc;
610	}
611
612
613	/**
614	* Do we consider @a enmConsider a better match for @a enmTarget than
615	* @a enmFound?
616	*
617	* Only called when @a enmConsider isn't exactly what we're looking for.
618	*
619	* @returns true/false.
620	* @param enmConsider The new microarch to consider.
621	* @param enmTarget The target microarch.
622	* @param enmFound The best microarch match we've found thus far.
623	*/
624	DECLINLINE(bool) cpumR3DbIsBetterMarchMatch(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
625	{
626	Assert(enmConsider != enmTarget);
627
628	/*
629	* If we've got an march match, don't bother with enmConsider.
630	*/
631	if (enmFound == enmTarget)
632	return false;
633
634	/*
635	* Found is below: Pick 'consider' if it's closer to the target or above it.
636	*/
637	if (enmFound < enmTarget)
638	return enmConsider > enmFound;
639
640	/*
641	* Found is above: Pick 'consider' if it's also above (paranoia: or equal)
642	* and but closer to the target.
643	*/
644	return enmConsider >= enmTarget && enmConsider < enmFound;
645	}
646
647
648	/**
649	* Do we consider @a enmConsider a better match for @a enmTarget than
650	* @a enmFound?
651	*
652	* Only called for intel family 06h CPUs.
653	*
654	* @returns true/false.
655	* @param enmConsider The new microarch to consider.
656	* @param enmTarget The target microarch.
657	* @param enmFound The best microarch match we've found thus far.
658	*/
659	static bool cpumR3DbIsBetterIntelFam06Match(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
660	{
661	/* Check intel family 06h claims. */
662	AssertReturn(enmConsider >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmConsider <= kCpumMicroarch_Intel_P6_Core_Atom_End,
663	false);
664	AssertReturn(enmTarget >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmTarget <= kCpumMicroarch_Intel_P6_Core_Atom_End,
665	false);
666
667	/* Put matches out of the way. */
668	if (enmConsider == enmTarget)
669	return true;
670	if (enmFound == enmTarget)
671	return false;
672
673	/* If found isn't a family 06h march, whatever we're considering must be a better choice. */
674	if ( enmFound < kCpumMicroarch_Intel_P6_Core_Atom_First
675	\|\| enmFound > kCpumMicroarch_Intel_P6_Core_Atom_End)
676	return true;
677
678	/*
679	* The family 06h stuff is split into three categories:
680	* - Common P6 heritage
681	* - Core
682	* - Atom
683	*
684	* Determin which of the three arguments are Atom marchs, because that's
685	* all we need to make the right choice.
686	*/
687	bool const fConsiderAtom = enmConsider >= kCpumMicroarch_Intel_Atom_First;
688	bool const fTargetAtom = enmTarget >= kCpumMicroarch_Intel_Atom_First;
689	bool const fFoundAtom = enmFound >= kCpumMicroarch_Intel_Atom_First;
690
691	/*
692	* Want atom:
693	*/
694	if (fTargetAtom)
695	{
696	/* Pick the atom if we've got one of each.*/
697	if (fConsiderAtom != fFoundAtom)
698	return fConsiderAtom;
699	/* If we haven't got any atoms under consideration, pick a P6 or the earlier core.
700	Note! Not entirely sure Dothan is the best choice, but it'll do for now. */
701	if (!fConsiderAtom)
702	{
703	if (enmConsider > enmFound)
704	return enmConsider <= kCpumMicroarch_Intel_P6_M_Dothan;
705	return enmFound > kCpumMicroarch_Intel_P6_M_Dothan;
706	}
707	/* else: same category, default comparison rules. */
708	Assert(fConsiderAtom && fFoundAtom);
709	}
710	/*
711	* Want non-atom:
712	*/
713	/* Pick the non-atom if we've got one of each. */
714	else if (fConsiderAtom != fFoundAtom)
715	return fFoundAtom;
716	/* If we've only got atoms under consideration, pick the older one just to pick something. */
717	else if (fConsiderAtom)
718	return enmConsider < enmFound;
719	else
720	Assert(!fConsiderAtom && !fFoundAtom);
721
722	/*
723	* Same basic category. Do same compare as caller.
724	*/
725	return cpumR3DbIsBetterMarchMatch(enmConsider, enmTarget, enmFound);
726	}
727
728
729	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
730	{
731	CPUMDBENTRY const *pEntry = NULL;
732	int rc;
733
734	if (!strcmp(pszName, "host"))
735	{
736	/*
737	* Create a CPU database entry for the host CPU. This means getting
738	* the CPUID bits from the real CPU and grabbing the closest matching
739	* database entry for MSRs.
740	*/
741	rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
742	if (RT_FAILURE(rc))
743	return rc;
744	rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
745	if (RT_FAILURE(rc))
746	return rc;
747
748	/* Lookup database entry for MSRs. */
749	CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
750	pInfo->paCpuIdLeavesR3[0].uEbx,
751	pInfo->paCpuIdLeavesR3[0].uEcx,
752	pInfo->paCpuIdLeavesR3[0].uEdx);
753	uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
754	uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
755	uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
756	uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
757	CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
758
759	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
760	{
761	CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
762	if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
763	{
764	/* Match against Family, Microarch, model and stepping. Except
765	for family, always match the closer with preference given to
766	the later/older ones. */
767	if (pCur->uFamily == uFamily)
768	{
769	if (pCur->enmMicroarch == enmMicroarch)
770	{
771	if (pCur->uModel == uModel)
772	{
773	if (pCur->uStepping == uStepping)
774	{
775	/* Perfect match. */
776	pEntry = pCur;
777	break;
778	}
779
780	if ( !pEntry
781	\|\| pEntry->uModel != uModel
782	\|\| pEntry->enmMicroarch != enmMicroarch
783	\|\| pEntry->uFamily != uFamily)
784	pEntry = pCur;
785	else if ( pCur->uStepping >= uStepping
786	? pCur->uStepping < pEntry->uStepping \|\| pEntry->uStepping < uStepping
787	: pCur->uStepping > pEntry->uStepping)
788	pEntry = pCur;
789	}
790	else if ( !pEntry
791	\|\| pEntry->enmMicroarch != enmMicroarch
792	\|\| pEntry->uFamily != uFamily)
793	pEntry = pCur;
794	else if ( pCur->uModel >= uModel
795	? pCur->uModel < pEntry->uModel \|\| pEntry->uModel < uModel
796	: pCur->uModel > pEntry->uModel)
797	pEntry = pCur;
798	}
799	else if ( !pEntry
800	\|\| pEntry->uFamily != uFamily)
801	pEntry = pCur;
802	/* Special march matching rules applies to intel family 06h. */
803	else if ( enmVendor == CPUMCPUVENDOR_INTEL
804	&& uFamily == 6
805	? cpumR3DbIsBetterIntelFam06Match(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch)
806	: cpumR3DbIsBetterMarchMatch(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch))
807	pEntry = pCur;
808	}
809	/* We don't do closeness matching on family, we use the first
810	entry for the CPU vendor instead. (P4 workaround.) */
811	else if (!pEntry)
812	pEntry = pCur;
813	}
814	}
815
816	if (pEntry)
817	LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
818	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
819	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
820	pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
821	else
822	{
823	pEntry = g_apCpumDbEntries[0];
824	LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'\n",
825	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
826	pEntry->pszName));
827	}
828	}
829	else
830	{
831	/*
832	* We're supposed to be emulating a specific CPU that is included in
833	* our CPU database. The CPUID tables needs to be copied onto the
834	* heap so the caller can modify them and so they can be freed like
835	* in the host case above.
836	*/
837	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
838	if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
839	{
840	pEntry = g_apCpumDbEntries[i];
841	break;
842	}
843	if (!pEntry)
844	{
845	LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
846	return VERR_CPUM_DB_CPU_NOT_FOUND;
847	}
848
849	pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
850	if (pEntry->cCpuIdLeaves)
851	{
852	pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDup(pEntry->paCpuIdLeaves,
853	sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves);
854	if (!pInfo->paCpuIdLeavesR3)
855	return VERR_NO_MEMORY;
856	}
857	else
858	pInfo->paCpuIdLeavesR3 = NULL;
859
860	pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
861	pInfo->DefCpuId = pEntry->DefUnknownCpuId;
862
863	LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
864	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
865	pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
866	}
867
868	pInfo->fMsrMask = pEntry->fMsrMask;
869	pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
870	pInfo->uPadding = 0;
871	pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
872	pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
873	pInfo->paMsrRangesR0 = NIL_RTR0PTR;
874	pInfo->paCpuIdLeavesRC = NIL_RTRCPTR;
875	pInfo->paMsrRangesRC = NIL_RTRCPTR;
876
877	/*
878	* Copy the MSR range.
879	*/
880	uint32_t cMsrs = 0;
881	PCPUMMSRRANGE paMsrs = NULL;
882
883	PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
884	uint32_t cLeft = pEntry->cMsrRanges;
885	while (cLeft-- > 0)
886	{
887	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &paMsrs, &cMsrs, pCurMsr);
888	if (RT_FAILURE(rc))
889	{
890	Assert(!paMsrs); /* The above function frees this. */
891	RTMemFree(pInfo->paCpuIdLeavesR3);
892	pInfo->paCpuIdLeavesR3 = NULL;
893	return rc;
894	}
895	pCurMsr++;
896	}
897
898	pInfo->paMsrRangesR3 = paMsrs;
899	pInfo->cMsrRanges = cMsrs;
900	return VINF_SUCCESS;
901	}
902
903
904	/**
905	* Insert an MSR range into the VM.
906	*
907	* If the new MSR range overlaps existing ranges, the existing ones will be
908	* adjusted/removed to fit in the new one.
909	*
910	* @returns VBox status code.
911	* @param pVM The cross context VM structure.
912	* @param pNewRange Pointer to the MSR range being inserted.
913	*/
914	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange)
915	{
916	AssertReturn(pVM, VERR_INVALID_PARAMETER);
917	AssertReturn(pNewRange, VERR_INVALID_PARAMETER);
918
919	return cpumR3MsrRangesInsert(pVM, NULL /* ppaMsrRanges /, NULL / pcMsrRanges */, pNewRange);
920	}
921
922
923	/**
924	* Register statistics for the MSRs.
925	*
926	* This must not be called before the MSRs have been finalized and moved to the
927	* hyper heap.
928	*
929	* @returns VBox status code.
930	* @param pVM The cross context VM structure.
931	*/
932	int cpumR3MsrRegStats(PVM pVM)
933	{
934	/*
935	* Global statistics.
936	*/
937	PCPUM pCpum = &pVM->cpum.s;
938	STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
939	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
940	STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
941	STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
942	STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
943	STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
944	STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
945	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
946	STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
947	STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
948	STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
949	STAMUNIT_OCCURENCES, "Writing of ignored bits.");
950	STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
951	STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
952
953
954	# ifdef VBOX_WITH_STATISTICS
955	/*
956	* Per range.
957	*/
958	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
959	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
960	for (uint32_t i = 0; i < cRanges; i++)
961	{
962	char szName[160];
963	ssize_t cchName;
964
965	if (paRanges[i].uFirst == paRanges[i].uLast)
966	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
967	paRanges[i].uFirst, paRanges[i].szName);
968	else
969	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
970	paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
971
972	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
973	STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
974
975	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
976	STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
977
978	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
979	STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
980
981	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
982	STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
983	}
984	# endif /* VBOX_WITH_STATISTICS */
985
986	return VINF_SUCCESS;
987	}
988
989	#endif /* !CPUM_DB_STANDALONE */
990

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 58591

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