CPUMR3Db.cpp@ 60682

Last change on this file since 60682 was 60664, checked in by vboxsync, 9 years ago
VMM,ConsoleImpl2: Added 386 profile, adding IEM code for some obvious 386isms (EFLAGS and CR0/MSW).
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File size: 41.0 KB

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1	/* $Id: CPUMR3Db.cpp 60664 2016-04-22 23:35:07Z vboxsync $ */
2	/** @file
3	* CPUM - CPU database part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/mm.h>
27
28	#include <VBox/err.h>
29	#include <iprt/asm-amd64-x86.h>
30	#include <iprt/mem.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Structures and Typedefs *
36	*********************************************************************************************************************************/
37	typedef struct CPUMDBENTRY
38	{
39	/** The CPU name. */
40	const char *pszName;
41	/** The full CPU name. */
42	const char *pszFullName;
43	/** The CPU vendor (CPUMCPUVENDOR). */
44	uint8_t enmVendor;
45	/** The CPU family. */
46	uint8_t uFamily;
47	/** The CPU model. */
48	uint8_t uModel;
49	/** The CPU stepping. */
50	uint8_t uStepping;
51	/** The microarchitecture. */
52	CPUMMICROARCH enmMicroarch;
53	/** Scalable bus frequency used for reporting other frequencies. */
54	uint64_t uScalableBusFreq;
55	/** Flags - CPUDB_F_XXX. */
56	uint32_t fFlags;
57	/** The maximum physical address with of the CPU. This should correspond to
58	* the value in CPUID leaf 0x80000008 when present. */
59	uint8_t cMaxPhysAddrWidth;
60	/** Pointer to an array of CPUID leaves. */
61	PCCPUMCPUIDLEAF paCpuIdLeaves;
62	/** The number of CPUID leaves in the array paCpuIdLeaves points to. */
63	uint32_t cCpuIdLeaves;
64	/** The method used to deal with unknown CPUID leaves. */
65	CPUMUNKNOWNCPUID enmUnknownCpuId;
66	/** The default unknown CPUID value. */
67	CPUMCPUID DefUnknownCpuId;
68
69	/** MSR mask. Several microarchitectures ignore higher bits of the */
70	uint32_t fMsrMask;
71
72	/** The number of ranges in the table pointed to b paMsrRanges. */
73	uint32_t cMsrRanges;
74	/** MSR ranges for this CPU. */
75	PCCPUMMSRRANGE paMsrRanges;
76	} CPUMDBENTRY;
77
78
79	/*********************************************************************************************************************************
80	* Defined Constants And Macros *
81	*********************************************************************************************************************************/
82	/** @name CPUDB_F_XXX - CPUDBENTRY::fFlags
83	* @{ */
84	/** Should execute all in IEM.
85	* @todo Implement this - currently done in Main... */
86	#define CPUDB_F_EXECUTE_ALL_IN_IEM RT_BIT_32(0)
87	/** @} */
88
89
90	/** @def NULL_ALONE
91	* For eliminating an unnecessary data dependency in standalone builds (for
92	* VBoxSVC). */
93	/** @def ZERO_ALONE
94	* For eliminating an unnecessary data size dependency in standalone builds (for
95	* VBoxSVC). */
96	#ifndef CPUM_DB_STANDALONE
97	# define NULL_ALONE(a_aTable) a_aTable
98	# define ZERO_ALONE(a_cTable) a_cTable
99	#else
100	# define NULL_ALONE(a_aTable) NULL
101	# define ZERO_ALONE(a_cTable) 0
102	#endif
103
104
105	/** @name Short macros for the MSR range entries.
106	*
107	* These are rather cryptic, but this is to reduce the attack on the right
108	* margin.
109	*
110	* @{ */
111	/** Alias one MSR onto another (a_uTarget). */
112	#define MAL(a_uMsr, a_szName, a_uTarget) \
113	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
114	/** Functions handles everything. */
115	#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
116	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
117	/** Functions handles everything, with GP mask. */
118	#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
119	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
120	/** Function handlers, read-only. */
121	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
122	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
123	/** Function handlers, ignore all writes. */
124	#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
125	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
126	/** Function handlers, with value. */
127	#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
128	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
129	/** Function handlers, with write ignore mask. */
130	#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
131	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
132	/** Function handlers, extended version. */
133	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
134	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
135	/** Function handlers, with CPUMCPU storage variable. */
136	#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
137	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
138	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
139	/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
140	#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
141	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
142	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
143	/** Read-only fixed value. */
144	#define MVO(a_uMsr, a_szName, a_uValue) \
145	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
146	/** Read-only fixed value, ignores all writes. */
147	#define MVI(a_uMsr, a_szName, a_uValue) \
148	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
149	/** Read fixed value, ignore writes outside GP mask. */
150	#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
151	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
152	/** Read fixed value, extended version with both GP and ignore masks. */
153	#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
154	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
155	/** The short form, no CPUM backing. */
156	#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
157	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
158	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
159
160	/** Range: Functions handles everything. */
161	#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
162	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
163	/** Range: Read fixed value, read-only. */
164	#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
165	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
166	/** Range: Read fixed value, ignore writes. */
167	#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
168	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
169	/** Range: The short form, no CPUM backing. */
170	#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
171	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
172	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
173
174	/** Internal form used by the macros. */
175	#ifdef VBOX_WITH_STATISTICS
176	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
177	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
178	{ 0 }, { 0 }, { 0 }, { 0 } }
179	#else
180	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
181	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
182	#endif
183	/** @} */
184
185
186	#include "cpus/Intel_Core_i7_6700K.h"
187	#include "cpus/Intel_Core_i7_5600U.h"
188	#include "cpus/Intel_Core_i7_3960X.h"
189	#include "cpus/Intel_Core_i5_3570.h"
190	#include "cpus/Intel_Core_i7_2635QM.h"
191	#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
192	#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
193	#include "cpus/Intel_Pentium_4_3_00GHz.h"
194	#include "cpus/Intel_Atom_330_1_60GHz.h"
195	#include "cpus/Intel_80386.h"
196	#include "cpus/Intel_80286.h"
197	#include "cpus/Intel_80186.h"
198	#include "cpus/Intel_8086.h"
199
200	#include "cpus/AMD_FX_8150_Eight_Core.h"
201	#include "cpus/AMD_Phenom_II_X6_1100T.h"
202	#include "cpus/Quad_Core_AMD_Opteron_2384.h"
203	#include "cpus/AMD_Athlon_64_X2_Dual_Core_4200.h"
204	#include "cpus/AMD_Athlon_64_3200.h"
205
206	#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
207
208
209
210	/**
211	* The database entries.
212	*
213	* 1. The first entry is special. It is the fallback for unknown
214	* processors. Thus, it better be pretty representative.
215	*
216	* 2. The first entry for a CPU vendor is likewise important as it is
217	* the default entry for that vendor.
218	*
219	* Generally we put the most recent CPUs first, since these tend to have the
220	* most complicated and backwards compatible list of MSRs.
221	*/
222	static CPUMDBENTRY const * const g_apCpumDbEntries[] =
223	{
224	#ifdef VBOX_CPUDB_Intel_Core_i7_6700K
225	&g_Entry_Intel_Core_i7_6700K,
226	#endif
227	#ifdef VBOX_CPUDB_Intel_Core_i7_5600U
228	&g_Entry_Intel_Core_i7_5600U,
229	#endif
230	#ifdef VBOX_CPUDB_Intel_Core_i5_3570
231	&g_Entry_Intel_Core_i5_3570,
232	#endif
233	#ifdef VBOX_CPUDB_Intel_Core_i7_3960X
234	&g_Entry_Intel_Core_i7_3960X,
235	#endif
236	#ifdef VBOX_CPUDB_Intel_Core_i7_2635QM
237	&g_Entry_Intel_Core_i7_2635QM,
238	#endif
239	#ifdef VBOX_CPUDB_Intel_Atom_330_1_60GHz
240	&g_Entry_Intel_Atom_330_1_60GHz,
241	#endif
242	#ifdef Intel_Pentium_M_processor_2_00GHz
243	&g_Entry_Intel_Pentium_M_processor_2_00GHz,
244	#endif
245	#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz
246	&g_Entry_Intel_Xeon_X5482_3_20GHz,
247	#endif
248	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz
249	&g_Entry_Intel_Pentium_4_3_00GHz,
250	#endif
251	#ifdef VBOX_CPUDB_Intel_80486
252	&g_Entry_Intel_80486,
253	#endif
254	#ifdef VBOX_CPUDB_Intel_80386
255	&g_Entry_Intel_80386,
256	#endif
257	#ifdef VBOX_CPUDB_Intel_80286
258	&g_Entry_Intel_80286,
259	#endif
260	#ifdef VBOX_CPUDB_Intel_80186
261	&g_Entry_Intel_80186,
262	#endif
263	#ifdef VBOX_CPUDB_Intel_8086
264	&g_Entry_Intel_8086,
265	#endif
266
267	#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core
268	&g_Entry_AMD_FX_8150_Eight_Core,
269	#endif
270	#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T
271	&g_Entry_AMD_Phenom_II_X6_1100T,
272	#endif
273	#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384
274	&g_Entry_Quad_Core_AMD_Opteron_2384,
275	#endif
276	#ifdef VBOX_CPUDB_AMD_Athlon_64_X2_Dual_Core_4200
277	&g_Entry_AMD_Athlon_64_X2_Dual_Core_4200,
278	#endif
279	#ifdef VBOX_CPUDB_AMD_Athlon_64_3200
280	&g_Entry_AMD_Athlon_64_3200,
281	#endif
282
283	#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz
284	&g_Entry_VIA_QuadCore_L4700_1_2_GHz,
285	#endif
286
287	#ifdef VBOX_CPUDB_NEC_V20
288	&g_Entry_NEC_V20,
289	#endif
290	};
291
292
293	#ifndef CPUM_DB_STANDALONE
294
295	/**
296	* Binary search used by cpumR3MsrRangesInsert and has some special properties
297	* wrt to mismatches.
298	*
299	* @returns Insert location.
300	* @param paMsrRanges The MSR ranges to search.
301	* @param cMsrRanges The number of MSR ranges.
302	* @param uMsr What to search for.
303	*/
304	static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
305	{
306	if (!cMsrRanges)
307	return 0;
308
309	uint32_t iStart = 0;
310	uint32_t iLast = cMsrRanges - 1;
311	for (;;)
312	{
313	uint32_t i = iStart + (iLast - iStart + 1) / 2;
314	if ( uMsr >= paMsrRanges[i].uFirst
315	&& uMsr <= paMsrRanges[i].uLast)
316	return i;
317	if (uMsr < paMsrRanges[i].uFirst)
318	{
319	if (i <= iStart)
320	return i;
321	iLast = i - 1;
322	}
323	else
324	{
325	if (i >= iLast)
326	{
327	if (i < cMsrRanges)
328	i++;
329	return i;
330	}
331	iStart = i + 1;
332	}
333	}
334	}
335
336
337	/**
338	* Ensures that there is space for at least @a cNewRanges in the table,
339	* reallocating the table if necessary.
340	*
341	* @returns Pointer to the MSR ranges on success, NULL on failure. On failure
342	* @a *ppaMsrRanges is freed and set to NULL.
343	* @param pVM The cross context VM structure. If NULL,
344	* use the process heap, otherwise the VM's hyper heap.
345	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
346	* @param cMsrRanges The current number of ranges.
347	* @param cNewRanges The number of ranges to be added.
348	*/
349	static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
350	{
351	uint32_t cMsrRangesAllocated;
352	if (!pVM)
353	cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
354	else
355	{
356	/*
357	* We're using the hyper heap now, but when the range array was copied over to it from
358	* the host-context heap, we only copy the exact size and not the ensured size.
359	* See @bugref{7270}.
360	*/
361	cMsrRangesAllocated = cMsrRanges;
362	}
363	if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
364	{
365	void *pvNew;
366	uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
367	if (pVM)
368	{
369	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
370	Assert(cMsrRanges == pVM->cpum.s.GuestInfo.cMsrRanges);
371
372	size_t cb = cMsrRangesAllocated * sizeof(**ppaMsrRanges);
373	size_t cbNew = cNew * sizeof(**ppaMsrRanges);
374	int rc = MMR3HyperRealloc(pVM, *ppaMsrRanges, cb, 32, MM_TAG_CPUM_MSRS, cbNew, &pvNew);
375	if (RT_FAILURE(rc))
376	{
377	*ppaMsrRanges = NULL;
378	pVM->cpum.s.GuestInfo.paMsrRangesR0 = NIL_RTR0PTR;
379	pVM->cpum.s.GuestInfo.paMsrRangesRC = NIL_RTRCPTR;
380	LogRel(("CPUM: cpumR3MsrRangesEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
381	return NULL;
382	}
383	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
384	}
385	else
386	{
387	pvNew = RTMemRealloc(ppaMsrRanges, cNew sizeof(**ppaMsrRanges));
388	if (!pvNew)
389	{
390	RTMemFree(*ppaMsrRanges);
391	*ppaMsrRanges = NULL;
392	return NULL;
393	}
394	}
395	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
396	}
397
398	if (pVM)
399	{
400	/* Update R0 and RC pointers. */
401	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
402	pVM->cpum.s.GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, *ppaMsrRanges);
403	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, *ppaMsrRanges);
404	}
405
406	return *ppaMsrRanges;
407	}
408
409
410	/**
411	* Inserts a new MSR range in into an sorted MSR range array.
412	*
413	* If the new MSR range overlaps existing ranges, the existing ones will be
414	* adjusted/removed to fit in the new one.
415	*
416	* @returns VBox status code.
417	* @retval VINF_SUCCESS
418	* @retval VERR_NO_MEMORY
419	*
420	* @param pVM The cross context VM structure. If NULL,
421	* use the process heap, otherwise the VM's hyper heap.
422	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
423	* Must be NULL if using the hyper heap.
424	* @param pcMsrRanges The variable holding number of ranges. Must be NULL
425	* if using the hyper heap.
426	* @param pNewRange The new range.
427	*/
428	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange)
429	{
430	Assert(pNewRange->uLast >= pNewRange->uFirst);
431	Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
432	Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
433
434	/*
435	* Validate and use the VM's MSR ranges array if we are using the hyper heap.
436	*/
437	if (pVM)
438	{
439	AssertReturn(!ppaMsrRanges, VERR_INVALID_PARAMETER);
440	AssertReturn(!pcMsrRanges, VERR_INVALID_PARAMETER);
441
442	ppaMsrRanges = &pVM->cpum.s.GuestInfo.paMsrRangesR3;
443	pcMsrRanges = &pVM->cpum.s.GuestInfo.cMsrRanges;
444	}
445
446	uint32_t cMsrRanges = *pcMsrRanges;
447	PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
448
449	/*
450	* Optimize the linear insertion case where we add new entries at the end.
451	*/
452	if ( cMsrRanges > 0
453	&& paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
454	{
455	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
456	if (!paMsrRanges)
457	return VERR_NO_MEMORY;
458	paMsrRanges[cMsrRanges] = *pNewRange;
459	*pcMsrRanges += 1;
460	}
461	else
462	{
463	uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
464	Assert(i == cMsrRanges \|\| pNewRange->uFirst <= paMsrRanges[i].uLast);
465	Assert(i == 0 \|\| pNewRange->uFirst > paMsrRanges[i - 1].uLast);
466
467	/*
468	* Adding an entirely new entry?
469	*/
470	if ( i >= cMsrRanges
471	\|\| pNewRange->uLast < paMsrRanges[i].uFirst)
472	{
473	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
474	if (!paMsrRanges)
475	return VERR_NO_MEMORY;
476	if (i < cMsrRanges)
477	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
478	paMsrRanges[i] = *pNewRange;
479	*pcMsrRanges += 1;
480	}
481	/*
482	* Replace existing entry?
483	*/
484	else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
485	&& pNewRange->uLast == paMsrRanges[i].uLast)
486	paMsrRanges[i] = *pNewRange;
487	/*
488	* Splitting an existing entry?
489	*/
490	else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
491	&& pNewRange->uLast < paMsrRanges[i].uLast)
492	{
493	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 2);
494	if (!paMsrRanges)
495	return VERR_NO_MEMORY;
496	if (i < cMsrRanges)
497	memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
498	paMsrRanges[i + 1] = *pNewRange;
499	paMsrRanges[i + 2] = paMsrRanges[i];
500	paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
501	paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
502	*pcMsrRanges += 2;
503	}
504	/*
505	* Complicated scenarios that can affect more than one range.
506	*
507	* The current code does not optimize memmove calls when replacing
508	* one or more existing ranges, because it's tedious to deal with and
509	* not expected to be a frequent usage scenario.
510	*/
511	else
512	{
513	/* Adjust start of first match? */
514	if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
515	&& pNewRange->uLast < paMsrRanges[i].uLast)
516	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
517	else
518	{
519	/* Adjust end of first match? */
520	if (pNewRange->uFirst > paMsrRanges[i].uFirst)
521	{
522	Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
523	paMsrRanges[i].uLast = pNewRange->uFirst - 1;
524	i++;
525	}
526	/* Replace the whole first match (lazy bird). */
527	else
528	{
529	if (i + 1 < cMsrRanges)
530	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
531	cMsrRanges = *pcMsrRanges -= 1;
532	}
533
534	/* Do the new range affect more ranges? */
535	while ( i < cMsrRanges
536	&& pNewRange->uLast >= paMsrRanges[i].uFirst)
537	{
538	if (pNewRange->uLast < paMsrRanges[i].uLast)
539	{
540	/* Adjust the start of it, then we're done. */
541	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
542	break;
543	}
544
545	/* Remove it entirely. */
546	if (i + 1 < cMsrRanges)
547	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
548	cMsrRanges = *pcMsrRanges -= 1;
549	}
550	}
551
552	/* Now, perform a normal insertion. */
553	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
554	if (!paMsrRanges)
555	return VERR_NO_MEMORY;
556	if (i < cMsrRanges)
557	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
558	paMsrRanges[i] = *pNewRange;
559	*pcMsrRanges += 1;
560	}
561	}
562
563	return VINF_SUCCESS;
564	}
565
566
567	/**
568	* Worker for cpumR3MsrApplyFudge that applies one table.
569	*
570	* @returns VBox status code.
571	* @param pVM The cross context VM structure.
572	* @param paRanges Array of MSRs to fudge.
573	* @param cRanges Number of MSRs in the array.
574	*/
575	static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
576	{
577	for (uint32_t i = 0; i < cRanges; i++)
578	if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
579	{
580	LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
581	int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
582	&paRanges[i]);
583	if (RT_FAILURE(rc))
584	return rc;
585	}
586	return VINF_SUCCESS;
587	}
588
589
590	/**
591	* Fudges the MSRs that guest are known to access in some odd cases.
592	*
593	* A typical example is a VM that has been moved between different hosts where
594	* for instance the cpu vendor differs.
595	*
596	* @returns VBox status code.
597	* @param pVM The cross context VM structure.
598	*/
599	int cpumR3MsrApplyFudge(PVM pVM)
600	{
601	/*
602	* Basic.
603	*/
604	static CPUMMSRRANGE const s_aFudgeMsrs[] =
605	{
606	MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
607	MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
608	MVO(0x00000017, "IA32_PLATFORM_ID", 0),
609	MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
610	MVI(0x0000008b, "BIOS_SIGN", 0),
611	MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
612	MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
613	MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
614	MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
615	MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
616	MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
617	MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
618	MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
619	MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
620	MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
621	MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
622	MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
623	};
624	int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
625	AssertLogRelRCReturn(rc, rc);
626
627	/*
628	* XP might mistake opterons and other newer CPUs for P4s.
629	*/
630	if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
631	{
632	static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
633	{
634	MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
635	};
636	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
637	AssertLogRelRCReturn(rc, rc);
638	}
639
640	return rc;
641	}
642
643
644	/**
645	* Do we consider @a enmConsider a better match for @a enmTarget than
646	* @a enmFound?
647	*
648	* Only called when @a enmConsider isn't exactly what we're looking for.
649	*
650	* @returns true/false.
651	* @param enmConsider The new microarch to consider.
652	* @param enmTarget The target microarch.
653	* @param enmFound The best microarch match we've found thus far.
654	*/
655	DECLINLINE(bool) cpumR3DbIsBetterMarchMatch(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
656	{
657	Assert(enmConsider != enmTarget);
658
659	/*
660	* If we've got an march match, don't bother with enmConsider.
661	*/
662	if (enmFound == enmTarget)
663	return false;
664
665	/*
666	* Found is below: Pick 'consider' if it's closer to the target or above it.
667	*/
668	if (enmFound < enmTarget)
669	return enmConsider > enmFound;
670
671	/*
672	* Found is above: Pick 'consider' if it's also above (paranoia: or equal)
673	* and but closer to the target.
674	*/
675	return enmConsider >= enmTarget && enmConsider < enmFound;
676	}
677
678
679	/**
680	* Do we consider @a enmConsider a better match for @a enmTarget than
681	* @a enmFound?
682	*
683	* Only called for intel family 06h CPUs.
684	*
685	* @returns true/false.
686	* @param enmConsider The new microarch to consider.
687	* @param enmTarget The target microarch.
688	* @param enmFound The best microarch match we've found thus far.
689	*/
690	static bool cpumR3DbIsBetterIntelFam06Match(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
691	{
692	/* Check intel family 06h claims. */
693	AssertReturn(enmConsider >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmConsider <= kCpumMicroarch_Intel_P6_Core_Atom_End,
694	false);
695	AssertReturn(enmTarget >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmTarget <= kCpumMicroarch_Intel_P6_Core_Atom_End,
696	false);
697
698	/* Put matches out of the way. */
699	if (enmConsider == enmTarget)
700	return true;
701	if (enmFound == enmTarget)
702	return false;
703
704	/* If found isn't a family 06h march, whatever we're considering must be a better choice. */
705	if ( enmFound < kCpumMicroarch_Intel_P6_Core_Atom_First
706	\|\| enmFound > kCpumMicroarch_Intel_P6_Core_Atom_End)
707	return true;
708
709	/*
710	* The family 06h stuff is split into three categories:
711	* - Common P6 heritage
712	* - Core
713	* - Atom
714	*
715	* Determin which of the three arguments are Atom marchs, because that's
716	* all we need to make the right choice.
717	*/
718	bool const fConsiderAtom = enmConsider >= kCpumMicroarch_Intel_Atom_First;
719	bool const fTargetAtom = enmTarget >= kCpumMicroarch_Intel_Atom_First;
720	bool const fFoundAtom = enmFound >= kCpumMicroarch_Intel_Atom_First;
721
722	/*
723	* Want atom:
724	*/
725	if (fTargetAtom)
726	{
727	/* Pick the atom if we've got one of each.*/
728	if (fConsiderAtom != fFoundAtom)
729	return fConsiderAtom;
730	/* If we haven't got any atoms under consideration, pick a P6 or the earlier core.
731	Note! Not entirely sure Dothan is the best choice, but it'll do for now. */
732	if (!fConsiderAtom)
733	{
734	if (enmConsider > enmFound)
735	return enmConsider <= kCpumMicroarch_Intel_P6_M_Dothan;
736	return enmFound > kCpumMicroarch_Intel_P6_M_Dothan;
737	}
738	/* else: same category, default comparison rules. */
739	Assert(fConsiderAtom && fFoundAtom);
740	}
741	/*
742	* Want non-atom:
743	*/
744	/* Pick the non-atom if we've got one of each. */
745	else if (fConsiderAtom != fFoundAtom)
746	return fFoundAtom;
747	/* If we've only got atoms under consideration, pick the older one just to pick something. */
748	else if (fConsiderAtom)
749	return enmConsider < enmFound;
750	else
751	Assert(!fConsiderAtom && !fFoundAtom);
752
753	/*
754	* Same basic category. Do same compare as caller.
755	*/
756	return cpumR3DbIsBetterMarchMatch(enmConsider, enmTarget, enmFound);
757	}
758
759
760	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
761	{
762	CPUMDBENTRY const *pEntry = NULL;
763	int rc;
764
765	if (!strcmp(pszName, "host"))
766	{
767	/*
768	* Create a CPU database entry for the host CPU. This means getting
769	* the CPUID bits from the real CPU and grabbing the closest matching
770	* database entry for MSRs.
771	*/
772	rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
773	if (RT_FAILURE(rc))
774	return rc;
775	rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
776	if (RT_FAILURE(rc))
777	return rc;
778
779	/* Lookup database entry for MSRs. */
780	CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
781	pInfo->paCpuIdLeavesR3[0].uEbx,
782	pInfo->paCpuIdLeavesR3[0].uEcx,
783	pInfo->paCpuIdLeavesR3[0].uEdx);
784	uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
785	uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
786	uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
787	uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
788	CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
789
790	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
791	{
792	CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
793	if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
794	{
795	/* Match against Family, Microarch, model and stepping. Except
796	for family, always match the closer with preference given to
797	the later/older ones. */
798	if (pCur->uFamily == uFamily)
799	{
800	if (pCur->enmMicroarch == enmMicroarch)
801	{
802	if (pCur->uModel == uModel)
803	{
804	if (pCur->uStepping == uStepping)
805	{
806	/* Perfect match. */
807	pEntry = pCur;
808	break;
809	}
810
811	if ( !pEntry
812	\|\| pEntry->uModel != uModel
813	\|\| pEntry->enmMicroarch != enmMicroarch
814	\|\| pEntry->uFamily != uFamily)
815	pEntry = pCur;
816	else if ( pCur->uStepping >= uStepping
817	? pCur->uStepping < pEntry->uStepping \|\| pEntry->uStepping < uStepping
818	: pCur->uStepping > pEntry->uStepping)
819	pEntry = pCur;
820	}
821	else if ( !pEntry
822	\|\| pEntry->enmMicroarch != enmMicroarch
823	\|\| pEntry->uFamily != uFamily)
824	pEntry = pCur;
825	else if ( pCur->uModel >= uModel
826	? pCur->uModel < pEntry->uModel \|\| pEntry->uModel < uModel
827	: pCur->uModel > pEntry->uModel)
828	pEntry = pCur;
829	}
830	else if ( !pEntry
831	\|\| pEntry->uFamily != uFamily)
832	pEntry = pCur;
833	/* Special march matching rules applies to intel family 06h. */
834	else if ( enmVendor == CPUMCPUVENDOR_INTEL
835	&& uFamily == 6
836	? cpumR3DbIsBetterIntelFam06Match(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch)
837	: cpumR3DbIsBetterMarchMatch(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch))
838	pEntry = pCur;
839	}
840	/* We don't do closeness matching on family, we use the first
841	entry for the CPU vendor instead. (P4 workaround.) */
842	else if (!pEntry)
843	pEntry = pCur;
844	}
845	}
846
847	if (pEntry)
848	LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
849	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
850	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
851	pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
852	else
853	{
854	pEntry = g_apCpumDbEntries[0];
855	LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'\n",
856	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
857	pEntry->pszName));
858	}
859	}
860	else
861	{
862	/*
863	* We're supposed to be emulating a specific CPU that is included in
864	* our CPU database. The CPUID tables needs to be copied onto the
865	* heap so the caller can modify them and so they can be freed like
866	* in the host case above.
867	*/
868	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
869	if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
870	{
871	pEntry = g_apCpumDbEntries[i];
872	break;
873	}
874	if (!pEntry)
875	{
876	LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
877	return VERR_CPUM_DB_CPU_NOT_FOUND;
878	}
879
880	pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
881	if (pEntry->cCpuIdLeaves)
882	{
883	/* Must allocate a multiple of 16 here, matching cpumR3CpuIdEnsureSpace. */
884	size_t cbExtra = sizeof(pEntry->paCpuIdLeaves[0]) * (RT_ALIGN(pEntry->cCpuIdLeaves, 16) - pEntry->cCpuIdLeaves);
885	pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDupEx(pEntry->paCpuIdLeaves,
886	sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves,
887	cbExtra);
888	if (!pInfo->paCpuIdLeavesR3)
889	return VERR_NO_MEMORY;
890	}
891	else
892	pInfo->paCpuIdLeavesR3 = NULL;
893
894	pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
895	pInfo->DefCpuId = pEntry->DefUnknownCpuId;
896
897	LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
898	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
899	pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
900	}
901
902	pInfo->fMsrMask = pEntry->fMsrMask;
903	pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
904	pInfo->uPadding = 0;
905	pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
906	pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
907	pInfo->paMsrRangesR0 = NIL_RTR0PTR;
908	pInfo->paCpuIdLeavesRC = NIL_RTRCPTR;
909	pInfo->paMsrRangesRC = NIL_RTRCPTR;
910
911	/*
912	* Copy the MSR range.
913	*/
914	uint32_t cMsrs = 0;
915	PCPUMMSRRANGE paMsrs = NULL;
916
917	PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
918	uint32_t cLeft = pEntry->cMsrRanges;
919	while (cLeft-- > 0)
920	{
921	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &paMsrs, &cMsrs, pCurMsr);
922	if (RT_FAILURE(rc))
923	{
924	Assert(!paMsrs); /* The above function frees this. */
925	RTMemFree(pInfo->paCpuIdLeavesR3);
926	pInfo->paCpuIdLeavesR3 = NULL;
927	return rc;
928	}
929	pCurMsr++;
930	}
931
932	pInfo->paMsrRangesR3 = paMsrs;
933	pInfo->cMsrRanges = cMsrs;
934	return VINF_SUCCESS;
935	}
936
937
938	/**
939	* Insert an MSR range into the VM.
940	*
941	* If the new MSR range overlaps existing ranges, the existing ones will be
942	* adjusted/removed to fit in the new one.
943	*
944	* @returns VBox status code.
945	* @param pVM The cross context VM structure.
946	* @param pNewRange Pointer to the MSR range being inserted.
947	*/
948	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange)
949	{
950	AssertReturn(pVM, VERR_INVALID_PARAMETER);
951	AssertReturn(pNewRange, VERR_INVALID_PARAMETER);
952
953	return cpumR3MsrRangesInsert(pVM, NULL /* ppaMsrRanges /, NULL / pcMsrRanges */, pNewRange);
954	}
955
956
957	/**
958	* Register statistics for the MSRs.
959	*
960	* This must not be called before the MSRs have been finalized and moved to the
961	* hyper heap.
962	*
963	* @returns VBox status code.
964	* @param pVM The cross context VM structure.
965	*/
966	int cpumR3MsrRegStats(PVM pVM)
967	{
968	/*
969	* Global statistics.
970	*/
971	PCPUM pCpum = &pVM->cpum.s;
972	STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
973	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
974	STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
975	STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
976	STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
977	STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
978	STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
979	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
980	STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
981	STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
982	STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
983	STAMUNIT_OCCURENCES, "Writing of ignored bits.");
984	STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
985	STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
986
987
988	# ifdef VBOX_WITH_STATISTICS
989	/*
990	* Per range.
991	*/
992	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
993	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
994	for (uint32_t i = 0; i < cRanges; i++)
995	{
996	char szName[160];
997	ssize_t cchName;
998
999	if (paRanges[i].uFirst == paRanges[i].uLast)
1000	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
1001	paRanges[i].uFirst, paRanges[i].szName);
1002	else
1003	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
1004	paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
1005
1006	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
1007	STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
1008
1009	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
1010	STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
1011
1012	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
1013	STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
1014
1015	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
1016	STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
1017	}
1018	# endif /* VBOX_WITH_STATISTICS */
1019
1020	return VINF_SUCCESS;
1021	}
1022
1023	#endif /* !CPUM_DB_STANDALONE */
1024

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 60682

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