CPUMR3Db.cpp@ 100696

Last change on this file since 100696 was 99756, checked in by vboxsync, 19 months ago
VMM/CPUMR3Db: Fix harmless range check, bugref:3409
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1	/* $Id: CPUMR3Db.cpp 99756 2023-05-11 19:26:52Z vboxsync $ */
2	/** @file
3	* CPUM - CPU database part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_CPUM
33	#include <VBox/vmm/cpum.h>
34	#include "CPUMInternal.h"
35	#include <VBox/vmm/vm.h>
36	#include <VBox/vmm/mm.h>
37
38	#include <VBox/err.h>
39	#if !defined(RT_ARCH_ARM64)
40	# include <iprt/asm-amd64-x86.h>
41	#endif
42	#include <iprt/mem.h>
43	#include <iprt/string.h>
44
45
46	/*********************************************************************************************************************************
47	* Defined Constants And Macros *
48	*********************************************************************************************************************************/
49	/** @def NULL_ALONE
50	* For eliminating an unnecessary data dependency in standalone builds (for
51	* VBoxSVC). */
52	/** @def ZERO_ALONE
53	* For eliminating an unnecessary data size dependency in standalone builds (for
54	* VBoxSVC). */
55	#ifndef CPUM_DB_STANDALONE
56	# define NULL_ALONE(a_aTable) a_aTable
57	# define ZERO_ALONE(a_cTable) a_cTable
58	#else
59	# define NULL_ALONE(a_aTable) NULL
60	# define ZERO_ALONE(a_cTable) 0
61	#endif
62
63
64	/** @name Short macros for the MSR range entries.
65	*
66	* These are rather cryptic, but this is to reduce the attack on the right
67	* margin.
68	*
69	* @{ */
70	/** Alias one MSR onto another (a_uTarget). */
71	#define MAL(a_uMsr, a_szName, a_uTarget) \
72	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
73	/** Functions handles everything. */
74	#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
75	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
76	/** Functions handles everything, with GP mask. */
77	#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
78	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
79	/** Function handlers, read-only. */
80	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
81	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
82	/** Function handlers, ignore all writes. */
83	#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
84	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
85	/** Function handlers, with value. */
86	#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
87	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
88	/** Function handlers, with write ignore mask. */
89	#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
90	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
91	/** Function handlers, extended version. */
92	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
93	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
94	/** Function handlers, with CPUMCPU storage variable. */
95	#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
96	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
97	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
98	/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
99	#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
100	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
101	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
102	/** Read-only fixed value. */
103	#define MVO(a_uMsr, a_szName, a_uValue) \
104	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
105	/** Read-only fixed value, ignores all writes. */
106	#define MVI(a_uMsr, a_szName, a_uValue) \
107	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
108	/** Read fixed value, ignore writes outside GP mask. */
109	#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
110	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
111	/** Read fixed value, extended version with both GP and ignore masks. */
112	#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
113	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
114	/** The short form, no CPUM backing. */
115	#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
116	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
117	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
118
119	/** Range: Functions handles everything. */
120	#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
121	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
122	/** Range: Read fixed value, read-only. */
123	#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
124	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
125	/** Range: Read fixed value, ignore writes. */
126	#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
127	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
128	/** Range: The short form, no CPUM backing. */
129	#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
130	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
131	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
132
133	/** Internal form used by the macros. */
134	#ifdef VBOX_WITH_STATISTICS
135	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
136	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
137	{ 0 }, { 0 }, { 0 }, { 0 } }
138	#else
139	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
140	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
141	#endif
142	/** @} */
143
144	#ifndef CPUM_DB_STANDALONE
145
146	#include "cpus/Intel_Core_i7_6700K.h"
147	#include "cpus/Intel_Core_i7_5600U.h"
148	#include "cpus/Intel_Core_i7_3960X.h"
149	#include "cpus/Intel_Core_i5_3570.h"
150	#include "cpus/Intel_Core_i7_2635QM.h"
151	#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
152	#include "cpus/Intel_Core2_X6800_2_93GHz.h"
153	#include "cpus/Intel_Core2_T7600_2_33GHz.h"
154	#include "cpus/Intel_Core_Duo_T2600_2_16GHz.h"
155	#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
156	#include "cpus/Intel_Pentium_4_3_00GHz.h"
157	#include "cpus/Intel_Pentium_N3530_2_16GHz.h"
158	#include "cpus/Intel_Atom_330_1_60GHz.h"
159	#include "cpus/Intel_80486.h"
160	#include "cpus/Intel_80386.h"
161	#include "cpus/Intel_80286.h"
162	#include "cpus/Intel_80186.h"
163	#include "cpus/Intel_8086.h"
164
165	#include "cpus/AMD_Ryzen_7_1800X_Eight_Core.h"
166	#include "cpus/AMD_FX_8150_Eight_Core.h"
167	#include "cpus/AMD_Phenom_II_X6_1100T.h"
168	#include "cpus/Quad_Core_AMD_Opteron_2384.h"
169	#include "cpus/AMD_Athlon_64_X2_Dual_Core_4200.h"
170	#include "cpus/AMD_Athlon_64_3200.h"
171
172	#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
173
174	#include "cpus/ZHAOXIN_KaiXian_KX_U5581_1_8GHz.h"
175
176	#include "cpus/Hygon_C86_7185_32_core.h"
177
178
179	/**
180	* The database entries.
181	*
182	* 1. The first entry is special. It is the fallback for unknown
183	* processors. Thus, it better be pretty representative.
184	*
185	* 2. The first entry for a CPU vendor is likewise important as it is
186	* the default entry for that vendor.
187	*
188	* Generally we put the most recent CPUs first, since these tend to have the
189	* most complicated and backwards compatible list of MSRs.
190	*/
191	static CPUMDBENTRY const * const g_apCpumDbEntries[] =
192	{
193	#ifdef VBOX_CPUDB_Intel_Core_i7_6700K_h
194	&g_Entry_Intel_Core_i7_6700K,
195	#endif
196	#ifdef VBOX_CPUDB_Intel_Core_i7_5600U_h
197	&g_Entry_Intel_Core_i7_5600U,
198	#endif
199	#ifdef VBOX_CPUDB_Intel_Core_i5_3570_h
200	&g_Entry_Intel_Core_i5_3570,
201	#endif
202	#ifdef VBOX_CPUDB_Intel_Core_i7_3960X_h
203	&g_Entry_Intel_Core_i7_3960X,
204	#endif
205	#ifdef VBOX_CPUDB_Intel_Core_i7_2635QM_h
206	&g_Entry_Intel_Core_i7_2635QM,
207	#endif
208	#ifdef VBOX_CPUDB_Intel_Pentium_N3530_2_16GHz_h
209	&g_Entry_Intel_Pentium_N3530_2_16GHz,
210	#endif
211	#ifdef VBOX_CPUDB_Intel_Atom_330_1_60GHz_h
212	&g_Entry_Intel_Atom_330_1_60GHz,
213	#endif
214	#ifdef VBOX_CPUDB_Intel_Pentium_M_processor_2_00GHz_h
215	&g_Entry_Intel_Pentium_M_processor_2_00GHz,
216	#endif
217	#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz_h
218	&g_Entry_Intel_Xeon_X5482_3_20GHz,
219	#endif
220	#ifdef VBOX_CPUDB_Intel_Core2_X6800_2_93GHz_h
221	&g_Entry_Intel_Core2_X6800_2_93GHz,
222	#endif
223	#ifdef VBOX_CPUDB_Intel_Core2_T7600_2_33GHz_h
224	&g_Entry_Intel_Core2_T7600_2_33GHz,
225	#endif
226	#ifdef VBOX_CPUDB_Intel_Core_Duo_T2600_2_16GHz_h
227	&g_Entry_Intel_Core_Duo_T2600_2_16GHz,
228	#endif
229	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz_h
230	&g_Entry_Intel_Pentium_4_3_00GHz,
231	#endif
232	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz_h
233	&g_Entry_Intel_Pentium_4_3_00GHz,
234	#endif
235	/** @todo pentium, pentium mmx, pentium pro, pentium II, pentium III */
236	#ifdef VBOX_CPUDB_Intel_80486_h
237	&g_Entry_Intel_80486,
238	#endif
239	#ifdef VBOX_CPUDB_Intel_80386_h
240	&g_Entry_Intel_80386,
241	#endif
242	#ifdef VBOX_CPUDB_Intel_80286_h
243	&g_Entry_Intel_80286,
244	#endif
245	#ifdef VBOX_CPUDB_Intel_80186_h
246	&g_Entry_Intel_80186,
247	#endif
248	#ifdef VBOX_CPUDB_Intel_8086_h
249	&g_Entry_Intel_8086,
250	#endif
251
252	#ifdef VBOX_CPUDB_AMD_Ryzen_7_1800X_Eight_Core_h
253	&g_Entry_AMD_Ryzen_7_1800X_Eight_Core,
254	#endif
255	#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core_h
256	&g_Entry_AMD_FX_8150_Eight_Core,
257	#endif
258	#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T_h
259	&g_Entry_AMD_Phenom_II_X6_1100T,
260	#endif
261	#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384_h
262	&g_Entry_Quad_Core_AMD_Opteron_2384,
263	#endif
264	#ifdef VBOX_CPUDB_AMD_Athlon_64_X2_Dual_Core_4200_h
265	&g_Entry_AMD_Athlon_64_X2_Dual_Core_4200,
266	#endif
267	#ifdef VBOX_CPUDB_AMD_Athlon_64_3200_h
268	&g_Entry_AMD_Athlon_64_3200,
269	#endif
270
271	#ifdef VBOX_CPUDB_ZHAOXIN_KaiXian_KX_U5581_1_8GHz_h
272	&g_Entry_ZHAOXIN_KaiXian_KX_U5581_1_8GHz,
273	#endif
274
275	#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz_h
276	&g_Entry_VIA_QuadCore_L4700_1_2_GHz,
277	#endif
278
279	#ifdef VBOX_CPUDB_NEC_V20_h
280	&g_Entry_NEC_V20,
281	#endif
282
283	#ifdef VBOX_CPUDB_Hygon_C86_7185_32_core_h
284	&g_Entry_Hygon_C86_7185_32_core,
285	#endif
286	};
287
288
289	/**
290	* Returns the number of entries in the CPU database.
291	*
292	* @returns Number of entries.
293	* @sa PFNCPUMDBGETENTRIES
294	*/
295	VMMR3DECL(uint32_t) CPUMR3DbGetEntries(void)
296	{
297	return RT_ELEMENTS(g_apCpumDbEntries);
298	}
299
300
301	/**
302	* Returns CPU database entry for the given index.
303	*
304	* @returns Pointer the CPU database entry, NULL if index is out of bounds.
305	* @param idxCpuDb The index (0..CPUMR3DbGetEntries).
306	* @sa PFNCPUMDBGETENTRYBYINDEX
307	*/
308	VMMR3DECL(PCCPUMDBENTRY) CPUMR3DbGetEntryByIndex(uint32_t idxCpuDb)
309	{
310	AssertReturn(idxCpuDb < RT_ELEMENTS(g_apCpumDbEntries), NULL);
311	return g_apCpumDbEntries[idxCpuDb];
312	}
313
314
315	/**
316	* Returns CPU database entry with the given name.
317	*
318	* @returns Pointer the CPU database entry, NULL if not found.
319	* @param pszName The name of the profile to return.
320	* @sa PFNCPUMDBGETENTRYBYNAME
321	*/
322	VMMR3DECL(PCCPUMDBENTRY) CPUMR3DbGetEntryByName(const char *pszName)
323	{
324	AssertPtrReturn(pszName, NULL);
325	AssertReturn(*pszName, NULL);
326	for (size_t i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
327	if (strcmp(g_apCpumDbEntries[i]->pszName, pszName) == 0)
328	return g_apCpumDbEntries[i];
329	return NULL;
330	}
331
332
333
334	/**
335	* Binary search used by cpumR3MsrRangesInsert and has some special properties
336	* wrt to mismatches.
337	*
338	* @returns Insert location.
339	* @param paMsrRanges The MSR ranges to search.
340	* @param cMsrRanges The number of MSR ranges.
341	* @param uMsr What to search for.
342	*/
343	static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
344	{
345	if (!cMsrRanges)
346	return 0;
347
348	uint32_t iStart = 0;
349	uint32_t iLast = cMsrRanges - 1;
350	for (;;)
351	{
352	uint32_t i = iStart + (iLast - iStart + 1) / 2;
353	if ( uMsr >= paMsrRanges[i].uFirst
354	&& uMsr <= paMsrRanges[i].uLast)
355	return i;
356	if (uMsr < paMsrRanges[i].uFirst)
357	{
358	if (i <= iStart)
359	return i;
360	iLast = i - 1;
361	}
362	else
363	{
364	if (i >= iLast)
365	{
366	if (i < cMsrRanges)
367	i++;
368	return i;
369	}
370	iStart = i + 1;
371	}
372	}
373	}
374
375
376	/**
377	* Ensures that there is space for at least @a cNewRanges in the table,
378	* reallocating the table if necessary.
379	*
380	* @returns Pointer to the MSR ranges on success, NULL on failure. On failure
381	* @a *ppaMsrRanges is freed and set to NULL.
382	* @param pVM The cross context VM structure. If NULL,
383	* use the process heap, otherwise the VM's hyper heap.
384	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
385	* @param cMsrRanges The current number of ranges.
386	* @param cNewRanges The number of ranges to be added.
387	*/
388	static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
389	{
390	if ( cMsrRanges + cNewRanges
391	> RT_ELEMENTS(pVM->cpum.s.GuestInfo.aMsrRanges) + (pVM ? 0 : 128 /* Catch too many MSRs in CPU reporter! */))
392	{
393	LogRel(("CPUM: Too many MSR ranges! %#x, max %#x\n",
394	cMsrRanges + cNewRanges, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aMsrRanges)));
395	return NULL;
396	}
397	if (pVM)
398	{
399	Assert(cMsrRanges == pVM->cpum.s.GuestInfo.cMsrRanges);
400	Assert(*ppaMsrRanges == pVM->cpum.s.GuestInfo.aMsrRanges);
401	}
402	else
403	{
404	if (cMsrRanges + cNewRanges > RT_ALIGN_32(cMsrRanges, 16))
405	{
406
407	uint32_t const cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
408	void pvNew = RTMemRealloc(ppaMsrRanges, cNew * sizeof(**ppaMsrRanges));
409	if (pvNew)
410	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
411	else
412	{
413	RTMemFree(*ppaMsrRanges);
414	*ppaMsrRanges = NULL;
415	return NULL;
416	}
417	}
418	}
419
420	return *ppaMsrRanges;
421	}
422
423
424	/**
425	* Inserts a new MSR range in into an sorted MSR range array.
426	*
427	* If the new MSR range overlaps existing ranges, the existing ones will be
428	* adjusted/removed to fit in the new one.
429	*
430	* @returns VBox status code.
431	* @retval VINF_SUCCESS
432	* @retval VERR_NO_MEMORY
433	*
434	* @param pVM The cross context VM structure. If NULL,
435	* use the process heap, otherwise the VM's hyper heap.
436	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
437	* Must be NULL if using the hyper heap.
438	* @param pcMsrRanges The variable holding number of ranges. Must be NULL
439	* if using the hyper heap.
440	* @param pNewRange The new range.
441	*/
442	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange)
443	{
444	Assert(pNewRange->uLast >= pNewRange->uFirst);
445	Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
446	Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
447
448	/*
449	* Validate and use the VM's MSR ranges array if we are using the hyper heap.
450	*/
451	if (pVM)
452	{
453	AssertReturn(!ppaMsrRanges, VERR_INVALID_PARAMETER);
454	AssertReturn(!pcMsrRanges, VERR_INVALID_PARAMETER);
455	AssertReturn(pVM->cpum.s.GuestInfo.paMsrRangesR3 == pVM->cpum.s.GuestInfo.aMsrRanges, VERR_INTERNAL_ERROR_3);
456
457	ppaMsrRanges = &pVM->cpum.s.GuestInfo.paMsrRangesR3;
458	pcMsrRanges = &pVM->cpum.s.GuestInfo.cMsrRanges;
459	}
460	else
461	{
462	AssertReturn(ppaMsrRanges, VERR_INVALID_POINTER);
463	AssertReturn(pcMsrRanges, VERR_INVALID_POINTER);
464	}
465
466	uint32_t cMsrRanges = *pcMsrRanges;
467	PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
468
469	/*
470	* Optimize the linear insertion case where we add new entries at the end.
471	*/
472	if ( cMsrRanges > 0
473	&& paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
474	{
475	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
476	if (!paMsrRanges)
477	return VERR_NO_MEMORY;
478	paMsrRanges[cMsrRanges] = *pNewRange;
479	*pcMsrRanges += 1;
480	}
481	else
482	{
483	uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
484	Assert(i == cMsrRanges \|\| pNewRange->uFirst <= paMsrRanges[i].uLast);
485	Assert(i == 0 \|\| pNewRange->uFirst > paMsrRanges[i - 1].uLast);
486
487	/*
488	* Adding an entirely new entry?
489	*/
490	if ( i >= cMsrRanges
491	\|\| pNewRange->uLast < paMsrRanges[i].uFirst)
492	{
493	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
494	if (!paMsrRanges)
495	return VERR_NO_MEMORY;
496	if (i < cMsrRanges)
497	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
498	paMsrRanges[i] = *pNewRange;
499	*pcMsrRanges += 1;
500	}
501	/*
502	* Replace existing entry?
503	*/
504	else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
505	&& pNewRange->uLast == paMsrRanges[i].uLast)
506	paMsrRanges[i] = *pNewRange;
507	/*
508	* Splitting an existing entry?
509	*/
510	else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
511	&& pNewRange->uLast < paMsrRanges[i].uLast)
512	{
513	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 2);
514	if (!paMsrRanges)
515	return VERR_NO_MEMORY;
516	if (i < cMsrRanges)
517	memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
518	paMsrRanges[i + 1] = *pNewRange;
519	paMsrRanges[i + 2] = paMsrRanges[i];
520	paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
521	paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
522	*pcMsrRanges += 2;
523	}
524	/*
525	* Complicated scenarios that can affect more than one range.
526	*
527	* The current code does not optimize memmove calls when replacing
528	* one or more existing ranges, because it's tedious to deal with and
529	* not expected to be a frequent usage scenario.
530	*/
531	else
532	{
533	/* Adjust start of first match? */
534	if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
535	&& pNewRange->uLast < paMsrRanges[i].uLast)
536	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
537	else
538	{
539	/* Adjust end of first match? */
540	if (pNewRange->uFirst > paMsrRanges[i].uFirst)
541	{
542	Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
543	paMsrRanges[i].uLast = pNewRange->uFirst - 1;
544	i++;
545	}
546	/* Replace the whole first match (lazy bird). */
547	else
548	{
549	if (i + 1 < cMsrRanges)
550	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
551	cMsrRanges = *pcMsrRanges -= 1;
552	}
553
554	/* Do the new range affect more ranges? */
555	while ( i < cMsrRanges
556	&& pNewRange->uLast >= paMsrRanges[i].uFirst)
557	{
558	if (pNewRange->uLast < paMsrRanges[i].uLast)
559	{
560	/* Adjust the start of it, then we're done. */
561	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
562	break;
563	}
564
565	/* Remove it entirely. */
566	if (i + 1 < cMsrRanges)
567	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
568	cMsrRanges = *pcMsrRanges -= 1;
569	}
570	}
571
572	/* Now, perform a normal insertion. */
573	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
574	if (!paMsrRanges)
575	return VERR_NO_MEMORY;
576	if (i < cMsrRanges)
577	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
578	paMsrRanges[i] = *pNewRange;
579	*pcMsrRanges += 1;
580	}
581	}
582
583	return VINF_SUCCESS;
584	}
585
586
587	/**
588	* Reconciles CPUID info with MSRs (selected ones).
589	*
590	* @returns VBox status code.
591	* @param pVM The cross context VM structure.
592	*/
593	int cpumR3MsrReconcileWithCpuId(PVM pVM)
594	{
595	PCCPUMMSRRANGE papToAdd[10];
596	uint32_t cToAdd = 0;
597
598	/*
599	* The IA32_FLUSH_CMD MSR was introduced in MCUs for CVS-2018-3646 and associates.
600	*/
601	if (pVM->cpum.s.GuestFeatures.fFlushCmd && !cpumLookupMsrRange(pVM, MSR_IA32_FLUSH_CMD))
602	{
603	static CPUMMSRRANGE const s_FlushCmd =
604	{
605	/.uFirst =/ MSR_IA32_FLUSH_CMD,
606	/.uLast =/ MSR_IA32_FLUSH_CMD,
607	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly,
608	/.enmWrFn =/ kCpumMsrWrFn_Ia32FlushCmd,
609	/.offCpumCpu =/ UINT16_MAX,
610	/.fReserved =/ 0,
611	/.uValue =/ 0,
612	/.fWrIgnMask =/ 0,
613	/.fWrGpMask =/ ~MSR_IA32_FLUSH_CMD_F_L1D,
614	/.szName = / "IA32_FLUSH_CMD"
615	};
616	papToAdd[cToAdd++] = &s_FlushCmd;
617	}
618
619	/*
620	* The MSR_IA32_ARCH_CAPABILITIES was introduced in various spectre MCUs, or at least
621	* documented in relation to such.
622	*/
623	if (pVM->cpum.s.GuestFeatures.fArchCap && !cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES))
624	{
625	static CPUMMSRRANGE const s_ArchCaps =
626	{
627	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES,
628	/.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
629	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities,
630	/.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
631	/.offCpumCpu =/ UINT16_MAX,
632	/.fReserved =/ 0,
633	/.uValue =/ 0,
634	/.fWrIgnMask =/ 0,
635	/.fWrGpMask =/ UINT64_MAX,
636	/.szName = / "IA32_ARCH_CAPABILITIES"
637	};
638	papToAdd[cToAdd++] = &s_ArchCaps;
639	}
640
641	/*
642	* Do the adding.
643	*/
644	for (uint32_t i = 0; i < cToAdd; i++)
645	{
646	PCCPUMMSRRANGE pRange = papToAdd[i];
647	LogRel(("CPUM: MSR/CPUID reconciliation insert: %#010x %s\n", pRange->uFirst, pRange->szName));
648	int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
649	pRange);
650	if (RT_FAILURE(rc))
651	return rc;
652	}
653	return VINF_SUCCESS;
654	}
655
656
657	/**
658	* Worker for cpumR3MsrApplyFudge that applies one table.
659	*
660	* @returns VBox status code.
661	* @param pVM The cross context VM structure.
662	* @param paRanges Array of MSRs to fudge.
663	* @param cRanges Number of MSRs in the array.
664	*/
665	static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
666	{
667	for (uint32_t i = 0; i < cRanges; i++)
668	if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
669	{
670	LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
671	int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
672	&paRanges[i]);
673	if (RT_FAILURE(rc))
674	return rc;
675	}
676	return VINF_SUCCESS;
677	}
678
679
680	/**
681	* Fudges the MSRs that guest are known to access in some odd cases.
682	*
683	* A typical example is a VM that has been moved between different hosts where
684	* for instance the cpu vendor differs.
685	*
686	* Another example is older CPU profiles (e.g. Atom Bonnet) for newer CPUs (e.g.
687	* Atom Silvermont), where features reported thru CPUID aren't present in the
688	* MSRs (e.g. AMD64_TSC_AUX).
689	*
690	*
691	* @returns VBox status code.
692	* @param pVM The cross context VM structure.
693	*/
694	int cpumR3MsrApplyFudge(PVM pVM)
695	{
696	/*
697	* Basic.
698	*/
699	static CPUMMSRRANGE const s_aFudgeMsrs[] =
700	{
701	MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
702	MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
703	MVO(0x00000017, "IA32_PLATFORM_ID", 0),
704	MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
705	MVI(0x0000008b, "BIOS_SIGN", 0),
706	MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
707	MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
708	MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
709	MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
710	MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
711	MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
712	MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
713	MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
714	MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
715	MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
716	MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
717	MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
718	};
719	int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
720	AssertLogRelRCReturn(rc, rc);
721
722	/*
723	* XP might mistake opterons and other newer CPUs for P4s.
724	*/
725	if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
726	{
727	static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
728	{
729	MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
730	};
731	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
732	AssertLogRelRCReturn(rc, rc);
733	}
734
735	if (pVM->cpum.s.GuestFeatures.fRdTscP)
736	{
737	static CPUMMSRRANGE const s_aRdTscPFudgeMsrs[] =
738	{
739	MFX(0xc0000103, "AMD64_TSC_AUX", Amd64TscAux, Amd64TscAux, 0, 0, ~(uint64_t)UINT32_MAX),
740	};
741	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aRdTscPFudgeMsrs[0], RT_ELEMENTS(s_aRdTscPFudgeMsrs));
742	AssertLogRelRCReturn(rc, rc);
743	}
744
745	/*
746	* Windows 10 incorrectly writes to MSR_IA32_TSX_CTRL without checking
747	* CPUID.ARCH_CAP(EAX=7h,ECX=0):EDX[bit 29] or the MSR feature bits in
748	* MSR_IA32_ARCH_CAPABILITIES[bit 7], see @bugref{9630}.
749	* Ignore writes to this MSR and return 0 on reads.
750	*/
751	if (pVM->cpum.s.GuestFeatures.fArchCap)
752	{
753	static CPUMMSRRANGE const s_aTsxCtrl[] =
754	{
755	MVI(MSR_IA32_TSX_CTRL, "IA32_TSX_CTRL", 0),
756	};
757	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aTsxCtrl[0], RT_ELEMENTS(s_aTsxCtrl));
758	AssertLogRelRCReturn(rc, rc);
759	}
760
761	return rc;
762	}
763
764	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
765
766	/**
767	* Do we consider @a enmConsider a better match for @a enmTarget than
768	* @a enmFound?
769	*
770	* Only called when @a enmConsider isn't exactly what we're looking for.
771	*
772	* @returns true/false.
773	* @param enmConsider The new microarch to consider.
774	* @param enmTarget The target microarch.
775	* @param enmFound The best microarch match we've found thus far.
776	*/
777	DECLINLINE(bool) cpumR3DbIsBetterMarchMatch(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
778	{
779	Assert(enmConsider != enmTarget);
780
781	/*
782	* If we've got an march match, don't bother with enmConsider.
783	*/
784	if (enmFound == enmTarget)
785	return false;
786
787	/*
788	* Found is below: Pick 'consider' if it's closer to the target or above it.
789	*/
790	if (enmFound < enmTarget)
791	return enmConsider > enmFound;
792
793	/*
794	* Found is above: Pick 'consider' if it's also above (paranoia: or equal)
795	* and but closer to the target.
796	*/
797	return enmConsider >= enmTarget && enmConsider < enmFound;
798	}
799
800
801	/**
802	* Do we consider @a enmConsider a better match for @a enmTarget than
803	* @a enmFound?
804	*
805	* Only called for intel family 06h CPUs.
806	*
807	* @returns true/false.
808	* @param enmConsider The new microarch to consider.
809	* @param enmTarget The target microarch.
810	* @param enmFound The best microarch match we've found thus far.
811	*/
812	static bool cpumR3DbIsBetterIntelFam06Match(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
813	{
814	/* Check intel family 06h claims. */
815	AssertReturn(enmConsider >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmConsider <= kCpumMicroarch_Intel_P6_Core_Atom_End,
816	false);
817	AssertReturn( (enmTarget >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmTarget <= kCpumMicroarch_Intel_P6_Core_Atom_End)
818	\|\| enmTarget == kCpumMicroarch_Intel_Unknown,
819	false);
820
821	/* Put matches out of the way. */
822	if (enmConsider == enmTarget)
823	return true;
824	if (enmFound == enmTarget)
825	return false;
826
827	/* If found isn't a family 06h march, whatever we're considering must be a better choice. */
828	if ( enmFound < kCpumMicroarch_Intel_P6_Core_Atom_First
829	\|\| enmFound > kCpumMicroarch_Intel_P6_Core_Atom_End)
830	return true;
831
832	/*
833	* The family 06h stuff is split into three categories:
834	* - Common P6 heritage
835	* - Core
836	* - Atom
837	*
838	* Determin which of the three arguments are Atom marchs, because that's
839	* all we need to make the right choice.
840	*/
841	bool const fConsiderAtom = enmConsider >= kCpumMicroarch_Intel_Atom_First;
842	bool const fTargetAtom = enmTarget >= kCpumMicroarch_Intel_Atom_First;
843	bool const fFoundAtom = enmFound >= kCpumMicroarch_Intel_Atom_First;
844
845	/*
846	* Want atom:
847	*/
848	if (fTargetAtom)
849	{
850	/* Pick the atom if we've got one of each.*/
851	if (fConsiderAtom != fFoundAtom)
852	return fConsiderAtom;
853	/* If we haven't got any atoms under consideration, pick a P6 or the earlier core.
854	Note! Not entirely sure Dothan is the best choice, but it'll do for now. */
855	if (!fConsiderAtom)
856	{
857	if (enmConsider > enmFound)
858	return enmConsider <= kCpumMicroarch_Intel_P6_M_Dothan;
859	return enmFound > kCpumMicroarch_Intel_P6_M_Dothan;
860	}
861	/* else: same category, default comparison rules. */
862	Assert(fConsiderAtom && fFoundAtom);
863	}
864	/*
865	* Want non-atom:
866	*/
867	/* Pick the non-atom if we've got one of each. */
868	else if (fConsiderAtom != fFoundAtom)
869	return fFoundAtom;
870	/* If we've only got atoms under consideration, pick the older one just to pick something. */
871	else if (fConsiderAtom)
872	return enmConsider < enmFound;
873	else
874	Assert(!fConsiderAtom && !fFoundAtom);
875
876	/*
877	* Same basic category. Do same compare as caller.
878	*/
879	return cpumR3DbIsBetterMarchMatch(enmConsider, enmTarget, enmFound);
880	}
881
882	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
883
884	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
885	{
886	CPUMDBENTRY const *pEntry = NULL;
887	int rc;
888
889	if (!strcmp(pszName, "host"))
890	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
891	{
892	/*
893	* Create a CPU database entry for the host CPU. This means getting
894	* the CPUID bits from the real CPU and grabbing the closest matching
895	* database entry for MSRs.
896	*/
897	rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
898	if (RT_FAILURE(rc))
899	return rc;
900	rc = CPUMCpuIdCollectLeavesX86(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
901	if (RT_FAILURE(rc))
902	return rc;
903	pInfo->fMxCsrMask = CPUMR3DeterminHostMxCsrMask();
904
905	/* Lookup database entry for MSRs. */
906	CPUMCPUVENDOR const enmVendor = CPUMCpuIdDetectX86VendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
907	pInfo->paCpuIdLeavesR3[0].uEbx,
908	pInfo->paCpuIdLeavesR3[0].uEcx,
909	pInfo->paCpuIdLeavesR3[0].uEdx);
910	uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
911	uint8_t const uFamily = RTX86GetCpuFamily(uStd1Eax);
912	uint8_t const uModel = RTX86GetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
913	uint8_t const uStepping = RTX86GetCpuStepping(uStd1Eax);
914	CPUMMICROARCH const enmMicroarch = CPUMCpuIdDetermineX86MicroarchEx(enmVendor, uFamily, uModel, uStepping);
915
916	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
917	{
918	CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
919	if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
920	{
921	/* Match against Family, Microarch, model and stepping. Except
922	for family, always match the closer with preference given to
923	the later/older ones. */
924	if (pCur->uFamily == uFamily)
925	{
926	if (pCur->enmMicroarch == enmMicroarch)
927	{
928	if (pCur->uModel == uModel)
929	{
930	if (pCur->uStepping == uStepping)
931	{
932	/* Perfect match. */
933	pEntry = pCur;
934	break;
935	}
936
937	if ( !pEntry
938	\|\| pEntry->uModel != uModel
939	\|\| pEntry->enmMicroarch != enmMicroarch
940	\|\| pEntry->uFamily != uFamily)
941	pEntry = pCur;
942	else if ( pCur->uStepping >= uStepping
943	? pCur->uStepping < pEntry->uStepping \|\| pEntry->uStepping < uStepping
944	: pCur->uStepping > pEntry->uStepping)
945	pEntry = pCur;
946	}
947	else if ( !pEntry
948	\|\| pEntry->enmMicroarch != enmMicroarch
949	\|\| pEntry->uFamily != uFamily)
950	pEntry = pCur;
951	else if ( pCur->uModel >= uModel
952	? pCur->uModel < pEntry->uModel \|\| pEntry->uModel < uModel
953	: pCur->uModel > pEntry->uModel)
954	pEntry = pCur;
955	}
956	else if ( !pEntry
957	\|\| pEntry->uFamily != uFamily)
958	pEntry = pCur;
959	/* Special march matching rules applies to intel family 06h. */
960	else if ( enmVendor == CPUMCPUVENDOR_INTEL
961	&& uFamily == 6
962	? cpumR3DbIsBetterIntelFam06Match(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch)
963	: cpumR3DbIsBetterMarchMatch(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch))
964	pEntry = pCur;
965	}
966	/* We don't do closeness matching on family, we use the first
967	entry for the CPU vendor instead. (P4 workaround.) */
968	else if (!pEntry)
969	pEntry = pCur;
970	}
971	}
972
973	if (pEntry)
974	LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
975	CPUMCpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMMicroarchName(enmMicroarch),
976	pEntry->pszName, CPUMCpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
977	pEntry->uStepping, CPUMMicroarchName(pEntry->enmMicroarch) ));
978	else
979	{
980	pEntry = g_apCpumDbEntries[0];
981	LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'\n",
982	CPUMCpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMMicroarchName(enmMicroarch),
983	pEntry->pszName));
984	}
985	}
986	else
987	#else
988	pszName = g_apCpumDbEntries[0]->pszName; /* Just pick the first entry for non-x86 hosts. */
989	#endif
990	{
991	/*
992	* We're supposed to be emulating a specific CPU that is included in
993	* our CPU database. The CPUID tables needs to be copied onto the
994	* heap so the caller can modify them and so they can be freed like
995	* in the host case above.
996	*/
997	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
998	if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
999	{
1000	pEntry = g_apCpumDbEntries[i];
1001	break;
1002	}
1003	if (!pEntry)
1004	{
1005	LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
1006	return VERR_CPUM_DB_CPU_NOT_FOUND;
1007	}
1008
1009	pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
1010	if (pEntry->cCpuIdLeaves)
1011	{
1012	/* Must allocate a multiple of 16 here, matching cpumR3CpuIdEnsureSpace. */
1013	size_t cbExtra = sizeof(pEntry->paCpuIdLeaves[0]) * (RT_ALIGN(pEntry->cCpuIdLeaves, 16) - pEntry->cCpuIdLeaves);
1014	pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDupEx(pEntry->paCpuIdLeaves,
1015	sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves,
1016	cbExtra);
1017	if (!pInfo->paCpuIdLeavesR3)
1018	return VERR_NO_MEMORY;
1019	}
1020	else
1021	pInfo->paCpuIdLeavesR3 = NULL;
1022
1023	pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
1024	pInfo->DefCpuId = pEntry->DefUnknownCpuId;
1025	pInfo->fMxCsrMask = pEntry->fMxCsrMask;
1026
1027	LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
1028	pEntry->pszName, CPUMCpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
1029	pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMMicroarchName(pEntry->enmMicroarch) ));
1030	}
1031
1032	pInfo->fMsrMask = pEntry->fMsrMask;
1033	pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
1034	pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
1035
1036	/*
1037	* Copy the MSR range.
1038	*/
1039	uint32_t cMsrs = 0;
1040	PCPUMMSRRANGE paMsrs = NULL;
1041
1042	PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
1043	uint32_t cLeft = pEntry->cMsrRanges;
1044	while (cLeft-- > 0)
1045	{
1046	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &paMsrs, &cMsrs, pCurMsr);
1047	if (RT_FAILURE(rc))
1048	{
1049	Assert(!paMsrs); /* The above function frees this. */
1050	RTMemFree(pInfo->paCpuIdLeavesR3);
1051	pInfo->paCpuIdLeavesR3 = NULL;
1052	return rc;
1053	}
1054	pCurMsr++;
1055	}
1056
1057	pInfo->paMsrRangesR3 = paMsrs;
1058	pInfo->cMsrRanges = cMsrs;
1059	return VINF_SUCCESS;
1060	}
1061
1062
1063	/**
1064	* Insert an MSR range into the VM.
1065	*
1066	* If the new MSR range overlaps existing ranges, the existing ones will be
1067	* adjusted/removed to fit in the new one.
1068	*
1069	* @returns VBox status code.
1070	* @param pVM The cross context VM structure.
1071	* @param pNewRange Pointer to the MSR range being inserted.
1072	*/
1073	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange)
1074	{
1075	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1076	AssertReturn(pNewRange, VERR_INVALID_PARAMETER);
1077
1078	return cpumR3MsrRangesInsert(pVM, NULL /* ppaMsrRanges /, NULL / pcMsrRanges */, pNewRange);
1079	}
1080
1081
1082	/**
1083	* Register statistics for the MSRs.
1084	*
1085	* This must not be called before the MSRs have been finalized and moved to the
1086	* hyper heap.
1087	*
1088	* @returns VBox status code.
1089	* @param pVM The cross context VM structure.
1090	*/
1091	int cpumR3MsrRegStats(PVM pVM)
1092	{
1093	/*
1094	* Global statistics.
1095	*/
1096	PCPUM pCpum = &pVM->cpum.s;
1097	STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
1098	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
1099	STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
1100	STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
1101	STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
1102	STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
1103	STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
1104	STAMUNIT_OCCURENCES, "All WRMSRs making it to CPUM.");
1105	STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
1106	STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
1107	STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
1108	STAMUNIT_OCCURENCES, "Writing of ignored bits.");
1109	STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
1110	STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
1111
1112
1113	# ifdef VBOX_WITH_STATISTICS
1114	/*
1115	* Per range.
1116	*/
1117	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
1118	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
1119	for (uint32_t i = 0; i < cRanges; i++)
1120	{
1121	char szName[160];
1122	ssize_t cchName;
1123
1124	if (paRanges[i].uFirst == paRanges[i].uLast)
1125	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
1126	paRanges[i].uFirst, paRanges[i].szName);
1127	else
1128	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
1129	paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
1130
1131	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
1132	STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
1133
1134	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
1135	STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
1136
1137	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
1138	STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
1139
1140	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
1141	STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
1142	}
1143	# endif /* VBOX_WITH_STATISTICS */
1144
1145	return VINF_SUCCESS;
1146	}
1147
1148	#endif /* !CPUM_DB_STANDALONE */
1149

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 100696

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