CPUMR3Db.cpp@ 49893

Last change on this file since 49893 was 49893, checked in by vboxsync, 11 years ago
MSR rewrite: initial hacking - half disabled.
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1	/* $Id: CPUMR3Db.cpp 49893 2013-12-13 00:40:20Z vboxsync $ */
2	/** @file
3	* CPUM - CPU database part.
4	*/
5
6	/*
7	* Copyright (C) 2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_CPUM
22	#include <VBox/vmm/cpum.h>
23	#include "CPUMInternal.h"
24	#include <VBox/vmm/vm.h>
25
26	#include <VBox/err.h>
27	#include <iprt/asm-amd64-x86.h>
28	#include <iprt/mem.h>
29	#include <iprt/string.h>
30
31
32	/*******************************************************************************
33	* Structures and Typedefs *
34	*******************************************************************************/
35	typedef struct CPUMDBENTRY
36	{
37	/** The CPU name. */
38	const char *pszName;
39	/** The full CPU name. */
40	const char *pszFullName;
41	/** The CPU vendor (CPUMCPUVENDOR). */
42	uint8_t enmVendor;
43	/** The CPU family. */
44	uint8_t uFamily;
45	/** The CPU model. */
46	uint8_t uModel;
47	/** The CPU stepping. */
48	uint8_t uStepping;
49	/** The microarchitecture. */
50	CPUMMICROARCH enmMicroarch;
51	/** Flags (TBD). */
52	uint32_t fFlags;
53	/** The maximum physical address with of the CPU. This should correspond to
54	* the value in CPUID leaf 0x80000008 when present. */
55	uint8_t cMaxPhysAddrWidth;
56	/** Pointer to an array of CPUID leaves. */
57	PCCPUMCPUIDLEAF paCpuIdLeaves;
58	/** The number of CPUID leaves in the array paCpuIdLeaves points to. */
59	uint32_t cCpuIdLeaves;
60	/** The method used to deal with unknown CPUID leaves. */
61	CPUMUKNOWNCPUID enmUnknownCpuId;
62	/** The default unknown CPUID value. */
63	CPUMCPUID DefUnknownCpuId;
64
65	/** MSR mask. Several microarchitectures ignore higher bits of the */
66	uint32_t fMsrMask;
67
68	/** The number of ranges in the table pointed to b paMsrRanges. */
69	uint32_t cMsrRanges;
70	/** MSR ranges for this CPU. */
71	PCCPUMMSRRANGE paMsrRanges;
72	} CPUMDBENTRY;
73
74
75	/*******************************************************************************
76	* Defined Constants And Macros *
77	*******************************************************************************/
78
79	/** @def NULL_ALONE
80	* For eliminating an unnecessary data dependency in standalone builds (for
81	* VBoxSVC). */
82	/** @def ZERO_ALONE
83	* For eliminating an unnecessary data size dependency in standalone builds (for
84	* VBoxSVC). */
85	#ifndef CPUM_DB_STANDALONE
86	# define NULL_ALONE(a_aTable) a_aTable
87	# define ZERO_ALONE(a_cTable) a_cTable
88	#else
89	# define NULL_ALONE(a_aTable) NULL
90	# define ZERO_ALONE(a_cTable) 0
91	#endif
92
93
94	/** @name Short macros for the MSR range entries.
95	*
96	* These are rather cryptic, but this is to reduce the attack on the right
97	* margin.
98	*
99	* @{ */
100	/** Alias one MSR onto another (a_uTarget). */
101	#define MAL(a_uMsr, a_szName, a_uTarget) \
102	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
103	/** Functions handles everything. */
104	#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
105	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
106	/** Functions handles everything, with GP mask. */
107	#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
108	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
109	/** Function handlers, read-only. */
110	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
111	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
112	/** Function handlers, ignore all writes. */
113	#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
114	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
115	/** Function handlers, with value. */
116	#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
117	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
118	/** Function handlers, with write ignore mask. */
119	#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
120	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
121	/** Function handlers, extended version. */
122	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
123	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
124	/** Function handlers, with CPUMCPU storage variable. */
125	#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
126	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
127	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
128	/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
129	#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
130	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
131	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
132	/** Read-only fixed value. */
133	#define MVO(a_uMsr, a_szName, a_uValue) \
134	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
135	/** Read-only fixed value, ignores all writes. */
136	#define MVI(a_uMsr, a_szName, a_uValue) \
137	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
138	/** Read fixed value, ignore writes outside GP mask. */
139	#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
140	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
141	/** Read fixed value, extended version with both GP and ignore masks. */
142	#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
143	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
144	/** The short form, no CPUM backing. */
145	#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
146	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
147	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
148
149	/** Range: Functions handles everything. */
150	#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
151	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
152	/** Range: Read fixed value, read-only. */
153	#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
154	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
155	/** Range: Read fixed value, ignore writes. */
156	#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
157	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
158	/** Range: The short form, no CPUM backing. */
159	#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
160	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
161	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
162
163	/** Internal form used by the macros. */
164	#ifdef VBOX_WITH_STATISTICS
165	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
166	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
167	{ 0 }, { 0 }, { 0 }, { 0 } }
168	#else
169	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
170	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
171	#endif
172	/** @} */
173
174
175	#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
176	#include "cpus/Intel_Core_i7_3960X.h"
177	#include "cpus/AMD_FX_8150_Eight_Core.h"
178	#include "cpus/Quad_Core_AMD_Opteron_2384.h"
179
180
181
182	/**
183	* The database entries.
184	*
185	* Warning! The first entry is special. It is the fallback for unknown
186	* processors. Thus, it better be pretty representative.
187	*/
188	static CPUMDBENTRY const * const g_apCpumDbEntries[] =
189	{
190	#ifdef VBOX_CPUDB_Intel_Core_i7_3960X
191	&g_Entry_Intel_Core_i7_3960X,
192	#endif
193	#ifdef Intel_Pentium_M_processor_2_00GHz
194	&g_Entry_Intel_Pentium_M_processor_2_00GHz,
195	#endif
196	#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core
197	&g_Entry_AMD_FX_8150_Eight_Core,
198	#endif
199	#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T
200	&g_Entry_AMD_Phenom_II_X6_1100T,
201	#endif
202	#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384
203	&g_Entry_Quad_Core_AMD_Opteron_2384,
204	#endif
205	};
206
207
208	#ifndef CPUM_DB_STANDALONE
209
210	/**
211	* Binary search used by cpumR3MsrRangesInsert and has some special properties
212	* wrt to mismatches.
213	*
214	* @returns Insert location.
215	* @param paMsrRanges The MSR ranges to search.
216	* @param cMsrRanges The number of MSR ranges.
217	* @param uMsr What to search for.
218	*/
219	static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
220	{
221	if (!cMsrRanges)
222	return 0;
223
224	uint32_t iStart = 0;
225	uint32_t iLast = cMsrRanges - 1;
226	for (;;)
227	{
228	uint32_t i = iStart + (iLast - iStart + 1) / 2;
229	if ( uMsr >= paMsrRanges[i].uFirst
230	&& uMsr <= paMsrRanges[i].uLast)
231	return i;
232	if (uMsr < paMsrRanges[i].uFirst)
233	{
234	if (i <= iStart)
235	return i;
236	iLast = i - 1;
237	}
238	else
239	{
240	if (i >= iLast)
241	{
242	if (i < cMsrRanges)
243	i++;
244	return i;
245	}
246	iStart = i + 1;
247	}
248	}
249	}
250
251
252	/**
253	* Ensures that there is space for at least @a cNewRanges in the table,
254	* reallocating the table if necessary.
255	*
256	* @returns Pointer to the MSR ranges on success, NULL on failure. On failure
257	* @a *ppaMsrRanges is freed and set to NULL.
258	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
259	* @param cMsrRanges The current number of ranges.
260	* @param cNewRanges The number of ranges to be added.
261	*/
262	static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
263	{
264	uint32_t cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
265	if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
266	{
267	uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
268	void pvNew = RTMemRealloc(ppaMsrRanges, cNew * sizeof(**ppaMsrRanges));
269	if (!pvNew)
270	{
271	RTMemFree(*ppaMsrRanges);
272	*ppaMsrRanges = NULL;
273	return NULL;
274	}
275	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
276	}
277	return *ppaMsrRanges;
278	}
279
280
281	/**
282	* Inserts a new MSR range in into an sorted MSR range array.
283	*
284	* If the new MSR range overlaps existing ranges, the existing ones will be
285	* adjusted/removed to fit in the new one.
286	*
287	* @returns VBox status code.
288	* @retval VINF_SUCCESS
289	* @retval VERR_NO_MEMORY
290	*
291	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
292	* @param pcMsrRanges The variable holding number of ranges.
293	* @param pNewRange The new range.
294	*/
295	int cpumR3MsrRangesInsert(PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange)
296	{
297	uint32_t cMsrRanges = *pcMsrRanges;
298	PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
299
300	Assert(pNewRange->uLast >= pNewRange->uFirst);
301	Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
302	Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
303
304	/*
305	* Optimize the linear insertion case where we add new entries at the end.
306	*/
307	if ( cMsrRanges > 0
308	&& paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
309	{
310	paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
311	if (!paMsrRanges)
312	return VERR_NO_MEMORY;
313	paMsrRanges[cMsrRanges] = *pNewRange;
314	*pcMsrRanges += 1;
315	}
316	else
317	{
318	uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
319	Assert(i == cMsrRanges \|\| pNewRange->uFirst <= paMsrRanges[i].uLast);
320	Assert(i == 0 \|\| pNewRange->uFirst > paMsrRanges[i - 1].uLast);
321
322	/*
323	* Adding an entirely new entry?
324	*/
325	if ( i >= cMsrRanges
326	\|\| pNewRange->uLast < paMsrRanges[i].uFirst)
327	{
328	paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
329	if (!paMsrRanges)
330	return VERR_NO_MEMORY;
331	if (i < cMsrRanges)
332	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
333	paMsrRanges[i] = *pNewRange;
334	*pcMsrRanges += 1;
335	}
336	/*
337	* Replace existing entry?
338	*/
339	else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
340	&& pNewRange->uLast == paMsrRanges[i].uLast)
341	paMsrRanges[i] = *pNewRange;
342	/*
343	* Splitting an existing entry?
344	*/
345	else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
346	&& pNewRange->uLast < paMsrRanges[i].uLast)
347	{
348	paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 2);
349	if (!paMsrRanges)
350	return VERR_NO_MEMORY;
351	if (i < cMsrRanges)
352	memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
353	paMsrRanges[i + 1] = *pNewRange;
354	paMsrRanges[i + 2] = paMsrRanges[i];
355	paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
356	paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
357	*pcMsrRanges += 2;
358	}
359	/*
360	* Complicated scenarios that can affect more than one range.
361	*
362	* The current code does not optimize memmove calls when replacing
363	* one or more existing ranges, because it's tedious to deal with and
364	* not expected to be a frequent usage scenario.
365	*/
366	else
367	{
368	/* Adjust start of first match? */
369	if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
370	&& pNewRange->uLast < paMsrRanges[i].uLast)
371	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
372	else
373	{
374	/* Adjust end of first match? */
375	if (pNewRange->uFirst > paMsrRanges[i].uFirst)
376	{
377	Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
378	paMsrRanges[i].uLast = pNewRange->uFirst - 1;
379	i++;
380	}
381	/* Replace the whole first match (lazy bird). */
382	else
383	{
384	if (i + 1 < cMsrRanges)
385	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
386	cMsrRanges = *pcMsrRanges -= 1;
387	}
388
389	/* Do the new range affect more ranges? */
390	while ( i < cMsrRanges
391	&& pNewRange->uLast >= paMsrRanges[i].uFirst)
392	{
393	if (pNewRange->uLast < paMsrRanges[i].uLast)
394	{
395	/* Adjust the start of it, then we're done. */
396	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
397	break;
398	}
399
400	/* Remove it entirely. */
401	if (i + 1 < cMsrRanges)
402	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
403	cMsrRanges = *pcMsrRanges -= 1;
404	}
405	}
406
407	/* Now, perform a normal insertion. */
408	paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
409	if (!paMsrRanges)
410	return VERR_NO_MEMORY;
411	if (i < cMsrRanges)
412	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
413	paMsrRanges[i] = *pNewRange;
414	*pcMsrRanges += 1;
415	}
416	}
417
418	return VINF_SUCCESS;
419	}
420
421
422	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
423	{
424	CPUMDBENTRY const *pEntry = NULL;
425	int rc;
426
427	if (!strcmp(pszName, "host"))
428	{
429	/*
430	* Create a CPU database entry for the host CPU. This means getting
431	* the CPUID bits from the real CPU and grabbing the closest matching
432	* database entry for MSRs.
433	*/
434	rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
435	if (RT_FAILURE(rc))
436	return rc;
437	rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
438	if (RT_FAILURE(rc))
439	return rc;
440
441	/* Lookup database entry for MSRs. */
442	CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
443	pInfo->paCpuIdLeavesR3[0].uEbx,
444	pInfo->paCpuIdLeavesR3[0].uEcx,
445	pInfo->paCpuIdLeavesR3[0].uEdx);
446	uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
447	uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
448	uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
449	uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
450	CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
451
452	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
453	{
454	CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
455	if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
456	{
457	/* Anything from the same vendor is better than nothing: */
458	if (!pEntry)
459	pEntry = pCur;
460	/* Newer micro arch is better than an older one: */
461	else if ( pEntry->enmMicroarch < enmMicroarch
462	&& pCur->enmMicroarch >= enmMicroarch)
463	pEntry = pCur;
464	/* Prefer a micro arch match: */
465	else if ( pEntry->enmMicroarch != enmMicroarch
466	&& pCur->enmMicroarch == enmMicroarch)
467	pEntry = pCur;
468	/* If the micro arch matches, check model and stepping. Stop
469	looping if we get an exact match. */
470	else if ( pEntry->enmMicroarch == enmMicroarch
471	&& pCur->enmMicroarch == enmMicroarch)
472	{
473	if (pCur->uModel == uModel)
474	{
475	/* Perfect match? */
476	if (pCur->uStepping == uStepping)
477	{
478	pEntry = pCur;
479	break;
480	}
481
482	/* Better model match? */
483	if (pEntry->uModel != uModel)
484	pEntry = pCur;
485	/* The one with the closest stepping, prefering ones over earlier ones. */
486	else if ( pCur->uStepping > uStepping
487	? pCur->uStepping < pEntry->uStepping \|\| pEntry->uStepping < uStepping
488	: pCur->uStepping > pEntry->uStepping)
489	pEntry = pCur;
490	}
491	/* The one with the closest model, prefering later ones over earlier ones. */
492	else if ( pCur->uModel > uModel
493	? pCur->uModel < pEntry->uModel \|\| pEntry->uModel < uModel
494	: pCur->uModel > pEntry->uModel)
495	pEntry = pCur;
496	}
497	}
498	}
499
500	if (pEntry)
501	LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s).\n",
502	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
503	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
504	pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
505	else
506	{
507	pEntry = g_apCpumDbEntries[0];
508	LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'.\n",
509	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
510	pEntry->pszName));
511	}
512	}
513	else
514	{
515	/*
516	* We're supposed to be emulating a specific CPU that is included in
517	* our CPU database. The CPUID tables needs to be copied onto the
518	* heap so the caller can modify them and so they can be freed like
519	* in the host case above.
520	*/
521	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
522	if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
523	{
524	pEntry = g_apCpumDbEntries[i];
525	break;
526	}
527	if (!pEntry)
528	{
529	LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
530	return VERR_CPUM_DB_CPU_NOT_FOUND;
531	}
532
533	pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
534	if (pEntry->cCpuIdLeaves)
535	{
536	pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDup(pEntry->paCpuIdLeaves,
537	sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves);
538	if (!pInfo->paCpuIdLeavesR3)
539	return VERR_NO_MEMORY;
540	}
541	else
542	pInfo->paCpuIdLeavesR3 = NULL;
543
544	pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
545	pInfo->DefCpuId = pEntry->DefUnknownCpuId;
546
547	LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s).\n",
548	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
549	pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
550	}
551
552	pInfo->fMsrMask = pEntry->fMsrMask;
553	pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
554	pInfo->uPadding = 0;
555	pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
556	pInfo->paMsrRangesR0 = NIL_RTR0PTR;
557	pInfo->paCpuIdLeavesRC = NIL_RTRCPTR;
558	pInfo->paMsrRangesRC = NIL_RTRCPTR;
559
560	/*
561	* Copy the MSR range.
562	*/
563	uint32_t cMsrs = 0;
564	PCPUMMSRRANGE paMsrs = NULL;
565
566	PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
567	uint32_t cLeft = pEntry->cMsrRanges;
568	while (cLeft-- > 0)
569	{
570	rc = cpumR3MsrRangesInsert(&paMsrs, &cMsrs, pCurMsr);
571	if (RT_FAILURE(rc))
572	{
573	Assert(!paMsrs); /* The above function frees this. */
574	RTMemFree(pInfo->paCpuIdLeavesR3);
575	pInfo->paCpuIdLeavesR3 = NULL;
576	return rc;
577	}
578	pCurMsr++;
579	}
580
581	pInfo->paMsrRangesR3 = paMsrs;
582	pInfo->cMsrRanges = cMsrs;
583	return VINF_SUCCESS;
584	}
585
586
587	/**
588	* Register statistics for the MSRs.
589	*
590	* This must not be called before the MSRs have been finalized and moved to the
591	* hyper heap.
592	*
593	* @returns VBox status code.
594	* @param pVM Pointer to the cross context VM structure.
595	*/
596	int cpumR3MsrRegStats(PVM pVM)
597	{
598	/*
599	* Global statistics.
600	*/
601	PCPUM pCpum = &pVM->cpum.s;
602	STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
603	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
604	STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
605	STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
606	STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
607	STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
608	STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
609	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
610	STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
611	STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
612	STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
613	STAMUNIT_OCCURENCES, "Writing of ignored bits.");
614	STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
615	STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
616
617
618	# ifdef VBOX_WITH_STATISTICS
619	/*
620	* Per range.
621	*/
622	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
623	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
624	for (uint32_t i = 0; i < cRanges; i++)
625	{
626	char szName[160];
627	ssize_t cchName;
628
629	if (paRanges[i].uFirst == paRanges[i].uLast)
630	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
631	paRanges[i].uFirst, paRanges[i].szName);
632	else
633	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
634	paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
635
636	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
637	STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
638
639	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
640	STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
641
642	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
643	STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
644
645	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
646	STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
647	}
648	# endif /* VBOX_WITH_STATISTICS */
649
650	return VINF_SUCCESS;
651	}
652
653	#endif /* !CPUM_DB_STANDALONE */
654

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 49893

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