VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 49899

Last change on this file since 49899 was 49899, checked in by vboxsync, 11 years ago

Added data for i5-3570.
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1/* $Id: CPUMR3Db.cpp 49899 2013-12-13 16:17:46Z vboxsync $ */
2/** @file
3 * CPUM - CPU database part.
4 */
5
6/*
7 * Copyright (C) 2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_CPUM
22#include <VBox/vmm/cpum.h>
23#include "CPUMInternal.h"
24#include <VBox/vmm/vm.h>
25
26#include <VBox/err.h>
27#include <iprt/asm-amd64-x86.h>
28#include <iprt/mem.h>
29#include <iprt/string.h>
30
31
32/*******************************************************************************
33* Structures and Typedefs *
34*******************************************************************************/
35typedef struct CPUMDBENTRY
36{
37 /** The CPU name. */
38 const char *pszName;
39 /** The full CPU name. */
40 const char *pszFullName;
41 /** The CPU vendor (CPUMCPUVENDOR). */
42 uint8_t enmVendor;
43 /** The CPU family. */
44 uint8_t uFamily;
45 /** The CPU model. */
46 uint8_t uModel;
47 /** The CPU stepping. */
48 uint8_t uStepping;
49 /** The microarchitecture. */
50 CPUMMICROARCH enmMicroarch;
51 /** Flags (TBD). */
52 uint32_t fFlags;
53 /** The maximum physical address with of the CPU. This should correspond to
54 * the value in CPUID leaf 0x80000008 when present. */
55 uint8_t cMaxPhysAddrWidth;
56 /** Pointer to an array of CPUID leaves. */
57 PCCPUMCPUIDLEAF paCpuIdLeaves;
58 /** The number of CPUID leaves in the array paCpuIdLeaves points to. */
59 uint32_t cCpuIdLeaves;
60 /** The method used to deal with unknown CPUID leaves. */
61 CPUMUKNOWNCPUID enmUnknownCpuId;
62 /** The default unknown CPUID value. */
63 CPUMCPUID DefUnknownCpuId;
64
65 /** MSR mask. Several microarchitectures ignore higher bits of the */
66 uint32_t fMsrMask;
67
68 /** The number of ranges in the table pointed to b paMsrRanges. */
69 uint32_t cMsrRanges;
70 /** MSR ranges for this CPU. */
71 PCCPUMMSRRANGE paMsrRanges;
72} CPUMDBENTRY;
73
74
75/*******************************************************************************
76* Defined Constants And Macros *
77*******************************************************************************/
78
79/** @def NULL_ALONE
80 * For eliminating an unnecessary data dependency in standalone builds (for
81 * VBoxSVC). */
82/** @def ZERO_ALONE
83 * For eliminating an unnecessary data size dependency in standalone builds (for
84 * VBoxSVC). */
85#ifndef CPUM_DB_STANDALONE
86# define NULL_ALONE(a_aTable) a_aTable
87# define ZERO_ALONE(a_cTable) a_cTable
88#else
89# define NULL_ALONE(a_aTable) NULL
90# define ZERO_ALONE(a_cTable) 0
91#endif
92
93
94/** @name Short macros for the MSR range entries.
95 *
96 * These are rather cryptic, but this is to reduce the attack on the right
97 * margin.
98 *
99 * @{ */
100/** Alias one MSR onto another (a_uTarget). */
101#define MAL(a_uMsr, a_szName, a_uTarget) \
102 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
103/** Functions handles everything. */
104#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
105 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
106/** Functions handles everything, with GP mask. */
107#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
108 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
109/** Function handlers, read-only. */
110#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
111 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
112/** Function handlers, ignore all writes. */
113#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
114 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
115/** Function handlers, with value. */
116#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
117 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
118/** Function handlers, with write ignore mask. */
119#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
120 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
121/** Function handlers, extended version. */
122#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
123 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
124/** Function handlers, with CPUMCPU storage variable. */
125#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
126 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
127 RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
128/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
129#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
130 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
131 RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
132/** Read-only fixed value. */
133#define MVO(a_uMsr, a_szName, a_uValue) \
134 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
135/** Read-only fixed value, ignores all writes. */
136#define MVI(a_uMsr, a_szName, a_uValue) \
137 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
138/** Read fixed value, ignore writes outside GP mask. */
139#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
140 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
141/** Read fixed value, extended version with both GP and ignore masks. */
142#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
143 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
144/** The short form, no CPUM backing. */
145#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
146 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
147 a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
148
149/** Range: Functions handles everything. */
150#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
151 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
152/** Range: Read fixed value, read-only. */
153#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
154 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
155/** Range: Read fixed value, ignore writes. */
156#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
157 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
158/** Range: The short form, no CPUM backing. */
159#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
160 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
161 a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
162
163/** Internal form used by the macros. */
164#ifdef VBOX_WITH_STATISTICS
165# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
166 { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
167 { 0 }, { 0 }, { 0 }, { 0 } }
168#else
169# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
170 { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
171#endif
172/** @} */
173
174
175#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
176#include "cpus/Intel_Core_i7_3960X.h"
177#include "cpus/Intel_Core_i5_3570.h"
178
179#include "cpus/AMD_FX_8150_Eight_Core.h"
180#include "cpus/Quad_Core_AMD_Opteron_2384.h"
181
182
183
184/**
185 * The database entries.
186 *
187 * Warning! The first entry is special. It is the fallback for unknown
188 * processors. Thus, it better be pretty representative.
189 */
190static CPUMDBENTRY const * const g_apCpumDbEntries[] =
191{
192#ifdef VBOX_CPUDB_Intel_Core_i5_3570
193 &g_Entry_Intel_Core_i5_3570,
194#endif
195#ifdef VBOX_CPUDB_Intel_Core_i7_3960X
196 &g_Entry_Intel_Core_i7_3960X,
197#endif
198#ifdef Intel_Pentium_M_processor_2_00GHz
199 &g_Entry_Intel_Pentium_M_processor_2_00GHz,
200#endif
201#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core
202 &g_Entry_AMD_FX_8150_Eight_Core,
203#endif
204#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T
205 &g_Entry_AMD_Phenom_II_X6_1100T,
206#endif
207#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384
208 &g_Entry_Quad_Core_AMD_Opteron_2384,
209#endif
210};
211
212
213#ifndef CPUM_DB_STANDALONE
214
215/**
216 * Binary search used by cpumR3MsrRangesInsert and has some special properties
217 * wrt to mismatches.
218 *
219 * @returns Insert location.
220 * @param paMsrRanges The MSR ranges to search.
221 * @param cMsrRanges The number of MSR ranges.
222 * @param uMsr What to search for.
223 */
224static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
225{
226 if (!cMsrRanges)
227 return 0;
228
229 uint32_t iStart = 0;
230 uint32_t iLast = cMsrRanges - 1;
231 for (;;)
232 {
233 uint32_t i = iStart + (iLast - iStart + 1) / 2;
234 if ( uMsr >= paMsrRanges[i].uFirst
235 && uMsr <= paMsrRanges[i].uLast)
236 return i;
237 if (uMsr < paMsrRanges[i].uFirst)
238 {
239 if (i <= iStart)
240 return i;
241 iLast = i - 1;
242 }
243 else
244 {
245 if (i >= iLast)
246 {
247 if (i < cMsrRanges)
248 i++;
249 return i;
250 }
251 iStart = i + 1;
252 }
253 }
254}
255
256
257/**
258 * Ensures that there is space for at least @a cNewRanges in the table,
259 * reallocating the table if necessary.
260 *
261 * @returns Pointer to the MSR ranges on success, NULL on failure. On failure
262 * @a *ppaMsrRanges is freed and set to NULL.
263 * @param ppaMsrRanges The variable pointing to the ranges (input/output).
264 * @param cMsrRanges The current number of ranges.
265 * @param cNewRanges The number of ranges to be added.
266 */
267static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
268{
269 uint32_t cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
270 if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
271 {
272 uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
273 void *pvNew = RTMemRealloc(*ppaMsrRanges, cNew * sizeof(**ppaMsrRanges));
274 if (!pvNew)
275 {
276 RTMemFree(*ppaMsrRanges);
277 *ppaMsrRanges = NULL;
278 return NULL;
279 }
280 *ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
281 }
282 return *ppaMsrRanges;
283}
284
285
286/**
287 * Inserts a new MSR range in into an sorted MSR range array.
288 *
289 * If the new MSR range overlaps existing ranges, the existing ones will be
290 * adjusted/removed to fit in the new one.
291 *
292 * @returns VBox status code.
293 * @retval VINF_SUCCESS
294 * @retval VERR_NO_MEMORY
295 *
296 * @param ppaMsrRanges The variable pointing to the ranges (input/output).
297 * @param pcMsrRanges The variable holding number of ranges.
298 * @param pNewRange The new range.
299 */
300int cpumR3MsrRangesInsert(PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange)
301{
302 uint32_t cMsrRanges = *pcMsrRanges;
303 PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
304
305 Assert(pNewRange->uLast >= pNewRange->uFirst);
306 Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
307 Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
308
309 /*
310 * Optimize the linear insertion case where we add new entries at the end.
311 */
312 if ( cMsrRanges > 0
313 && paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
314 {
315 paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
316 if (!paMsrRanges)
317 return VERR_NO_MEMORY;
318 paMsrRanges[cMsrRanges] = *pNewRange;
319 *pcMsrRanges += 1;
320 }
321 else
322 {
323 uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
324 Assert(i == cMsrRanges || pNewRange->uFirst <= paMsrRanges[i].uLast);
325 Assert(i == 0 || pNewRange->uFirst > paMsrRanges[i - 1].uLast);
326
327 /*
328 * Adding an entirely new entry?
329 */
330 if ( i >= cMsrRanges
331 || pNewRange->uLast < paMsrRanges[i].uFirst)
332 {
333 paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
334 if (!paMsrRanges)
335 return VERR_NO_MEMORY;
336 if (i < cMsrRanges)
337 memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
338 paMsrRanges[i] = *pNewRange;
339 *pcMsrRanges += 1;
340 }
341 /*
342 * Replace existing entry?
343 */
344 else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
345 && pNewRange->uLast == paMsrRanges[i].uLast)
346 paMsrRanges[i] = *pNewRange;
347 /*
348 * Splitting an existing entry?
349 */
350 else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
351 && pNewRange->uLast < paMsrRanges[i].uLast)
352 {
353 paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 2);
354 if (!paMsrRanges)
355 return VERR_NO_MEMORY;
356 if (i < cMsrRanges)
357 memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
358 paMsrRanges[i + 1] = *pNewRange;
359 paMsrRanges[i + 2] = paMsrRanges[i];
360 paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
361 paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
362 *pcMsrRanges += 2;
363 }
364 /*
365 * Complicated scenarios that can affect more than one range.
366 *
367 * The current code does not optimize memmove calls when replacing
368 * one or more existing ranges, because it's tedious to deal with and
369 * not expected to be a frequent usage scenario.
370 */
371 else
372 {
373 /* Adjust start of first match? */
374 if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
375 && pNewRange->uLast < paMsrRanges[i].uLast)
376 paMsrRanges[i].uFirst = pNewRange->uLast + 1;
377 else
378 {
379 /* Adjust end of first match? */
380 if (pNewRange->uFirst > paMsrRanges[i].uFirst)
381 {
382 Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
383 paMsrRanges[i].uLast = pNewRange->uFirst - 1;
384 i++;
385 }
386 /* Replace the whole first match (lazy bird). */
387 else
388 {
389 if (i + 1 < cMsrRanges)
390 memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
391 cMsrRanges = *pcMsrRanges -= 1;
392 }
393
394 /* Do the new range affect more ranges? */
395 while ( i < cMsrRanges
396 && pNewRange->uLast >= paMsrRanges[i].uFirst)
397 {
398 if (pNewRange->uLast < paMsrRanges[i].uLast)
399 {
400 /* Adjust the start of it, then we're done. */
401 paMsrRanges[i].uFirst = pNewRange->uLast + 1;
402 break;
403 }
404
405 /* Remove it entirely. */
406 if (i + 1 < cMsrRanges)
407 memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
408 cMsrRanges = *pcMsrRanges -= 1;
409 }
410 }
411
412 /* Now, perform a normal insertion. */
413 paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
414 if (!paMsrRanges)
415 return VERR_NO_MEMORY;
416 if (i < cMsrRanges)
417 memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
418 paMsrRanges[i] = *pNewRange;
419 *pcMsrRanges += 1;
420 }
421 }
422
423 return VINF_SUCCESS;
424}
425
426
427int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
428{
429 CPUMDBENTRY const *pEntry = NULL;
430 int rc;
431
432 if (!strcmp(pszName, "host"))
433 {
434 /*
435 * Create a CPU database entry for the host CPU. This means getting
436 * the CPUID bits from the real CPU and grabbing the closest matching
437 * database entry for MSRs.
438 */
439 rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
440 if (RT_FAILURE(rc))
441 return rc;
442 rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
443 if (RT_FAILURE(rc))
444 return rc;
445
446 /* Lookup database entry for MSRs. */
447 CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
448 pInfo->paCpuIdLeavesR3[0].uEbx,
449 pInfo->paCpuIdLeavesR3[0].uEcx,
450 pInfo->paCpuIdLeavesR3[0].uEdx);
451 uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
452 uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
453 uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
454 uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
455 CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
456
457 for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
458 {
459 CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
460 if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
461 {
462 /* Anything from the same vendor is better than nothing: */
463 if (!pEntry)
464 pEntry = pCur;
465 /* Newer micro arch is better than an older one: */
466 else if ( pEntry->enmMicroarch < enmMicroarch
467 && pCur->enmMicroarch >= enmMicroarch)
468 pEntry = pCur;
469 /* Prefer a micro arch match: */
470 else if ( pEntry->enmMicroarch != enmMicroarch
471 && pCur->enmMicroarch == enmMicroarch)
472 pEntry = pCur;
473 /* If the micro arch matches, check model and stepping. Stop
474 looping if we get an exact match. */
475 else if ( pEntry->enmMicroarch == enmMicroarch
476 && pCur->enmMicroarch == enmMicroarch)
477 {
478 if (pCur->uModel == uModel)
479 {
480 /* Perfect match? */
481 if (pCur->uStepping == uStepping)
482 {
483 pEntry = pCur;
484 break;
485 }
486
487 /* Better model match? */
488 if (pEntry->uModel != uModel)
489 pEntry = pCur;
490 /* The one with the closest stepping, prefering ones over earlier ones. */
491 else if ( pCur->uStepping > uStepping
492 ? pCur->uStepping < pEntry->uStepping || pEntry->uStepping < uStepping
493 : pCur->uStepping > pEntry->uStepping)
494 pEntry = pCur;
495 }
496 /* The one with the closest model, prefering later ones over earlier ones. */
497 else if ( pCur->uModel > uModel
498 ? pCur->uModel < pEntry->uModel || pEntry->uModel < uModel
499 : pCur->uModel > pEntry->uModel)
500 pEntry = pCur;
501 }
502 }
503 }
504
505 if (pEntry)
506 LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s).\n",
507 CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
508 pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
509 pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
510 else
511 {
512 pEntry = g_apCpumDbEntries[0];
513 LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'.\n",
514 CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
515 pEntry->pszName));
516 }
517 }
518 else
519 {
520 /*
521 * We're supposed to be emulating a specific CPU that is included in
522 * our CPU database. The CPUID tables needs to be copied onto the
523 * heap so the caller can modify them and so they can be freed like
524 * in the host case above.
525 */
526 for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
527 if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
528 {
529 pEntry = g_apCpumDbEntries[i];
530 break;
531 }
532 if (!pEntry)
533 {
534 LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
535 return VERR_CPUM_DB_CPU_NOT_FOUND;
536 }
537
538 pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
539 if (pEntry->cCpuIdLeaves)
540 {
541 pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDup(pEntry->paCpuIdLeaves,
542 sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves);
543 if (!pInfo->paCpuIdLeavesR3)
544 return VERR_NO_MEMORY;
545 }
546 else
547 pInfo->paCpuIdLeavesR3 = NULL;
548
549 pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
550 pInfo->DefCpuId = pEntry->DefUnknownCpuId;
551
552 LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s).\n",
553 pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
554 pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
555 }
556
557 pInfo->fMsrMask = pEntry->fMsrMask;
558 pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
559 pInfo->uPadding = 0;
560 pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
561 pInfo->paMsrRangesR0 = NIL_RTR0PTR;
562 pInfo->paCpuIdLeavesRC = NIL_RTRCPTR;
563 pInfo->paMsrRangesRC = NIL_RTRCPTR;
564
565 /*
566 * Copy the MSR range.
567 */
568 uint32_t cMsrs = 0;
569 PCPUMMSRRANGE paMsrs = NULL;
570
571 PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
572 uint32_t cLeft = pEntry->cMsrRanges;
573 while (cLeft-- > 0)
574 {
575 rc = cpumR3MsrRangesInsert(&paMsrs, &cMsrs, pCurMsr);
576 if (RT_FAILURE(rc))
577 {
578 Assert(!paMsrs); /* The above function frees this. */
579 RTMemFree(pInfo->paCpuIdLeavesR3);
580 pInfo->paCpuIdLeavesR3 = NULL;
581 return rc;
582 }
583 pCurMsr++;
584 }
585
586 pInfo->paMsrRangesR3 = paMsrs;
587 pInfo->cMsrRanges = cMsrs;
588 return VINF_SUCCESS;
589}
590
591
592/**
593 * Register statistics for the MSRs.
594 *
595 * This must not be called before the MSRs have been finalized and moved to the
596 * hyper heap.
597 *
598 * @returns VBox status code.
599 * @param pVM Pointer to the cross context VM structure.
600 */
601int cpumR3MsrRegStats(PVM pVM)
602{
603 /*
604 * Global statistics.
605 */
606 PCPUM pCpum = &pVM->cpum.s;
607 STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
608 STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
609 STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
610 STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
611 STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
612 STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
613 STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
614 STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
615 STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
616 STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
617 STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
618 STAMUNIT_OCCURENCES, "Writing of ignored bits.");
619 STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
620 STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
621
622
623# ifdef VBOX_WITH_STATISTICS
624 /*
625 * Per range.
626 */
627 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
628 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
629 for (uint32_t i = 0; i < cRanges; i++)
630 {
631 char szName[160];
632 ssize_t cchName;
633
634 if (paRanges[i].uFirst == paRanges[i].uLast)
635 cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
636 paRanges[i].uFirst, paRanges[i].szName);
637 else
638 cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
639 paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
640
641 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
642 STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
643
644 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
645 STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
646
647 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
648 STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
649
650 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
651 STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
652 }
653# endif /* VBOX_WITH_STATISTICS */
654
655 return VINF_SUCCESS;
656}
657
658#endif /* !CPUM_DB_STANDALONE */
659
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