CPUMR3Db.cpp@ 57394

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*: scm cleanup run.
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1	/* $Id: CPUMR3Db.cpp 57358 2015-08-14 15:16:38Z vboxsync $ */
2	/** @file
3	* CPUM - CPU database part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/mm.h>
27
28	#include <VBox/err.h>
29	#include <iprt/asm-amd64-x86.h>
30	#include <iprt/mem.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Structures and Typedefs *
36	*********************************************************************************************************************************/
37	typedef struct CPUMDBENTRY
38	{
39	/** The CPU name. */
40	const char *pszName;
41	/** The full CPU name. */
42	const char *pszFullName;
43	/** The CPU vendor (CPUMCPUVENDOR). */
44	uint8_t enmVendor;
45	/** The CPU family. */
46	uint8_t uFamily;
47	/** The CPU model. */
48	uint8_t uModel;
49	/** The CPU stepping. */
50	uint8_t uStepping;
51	/** The microarchitecture. */
52	CPUMMICROARCH enmMicroarch;
53	/** Scalable bus frequency used for reporting other frequencies. */
54	uint64_t uScalableBusFreq;
55	/** Flags (TBD). */
56	uint32_t fFlags;
57	/** The maximum physical address with of the CPU. This should correspond to
58	* the value in CPUID leaf 0x80000008 when present. */
59	uint8_t cMaxPhysAddrWidth;
60	/** Pointer to an array of CPUID leaves. */
61	PCCPUMCPUIDLEAF paCpuIdLeaves;
62	/** The number of CPUID leaves in the array paCpuIdLeaves points to. */
63	uint32_t cCpuIdLeaves;
64	/** The method used to deal with unknown CPUID leaves. */
65	CPUMUNKNOWNCPUID enmUnknownCpuId;
66	/** The default unknown CPUID value. */
67	CPUMCPUID DefUnknownCpuId;
68
69	/** MSR mask. Several microarchitectures ignore higher bits of the */
70	uint32_t fMsrMask;
71
72	/** The number of ranges in the table pointed to b paMsrRanges. */
73	uint32_t cMsrRanges;
74	/** MSR ranges for this CPU. */
75	PCCPUMMSRRANGE paMsrRanges;
76	} CPUMDBENTRY;
77
78
79	/*********************************************************************************************************************************
80	* Defined Constants And Macros *
81	*********************************************************************************************************************************/
82
83	/** @def NULL_ALONE
84	* For eliminating an unnecessary data dependency in standalone builds (for
85	* VBoxSVC). */
86	/** @def ZERO_ALONE
87	* For eliminating an unnecessary data size dependency in standalone builds (for
88	* VBoxSVC). */
89	#ifndef CPUM_DB_STANDALONE
90	# define NULL_ALONE(a_aTable) a_aTable
91	# define ZERO_ALONE(a_cTable) a_cTable
92	#else
93	# define NULL_ALONE(a_aTable) NULL
94	# define ZERO_ALONE(a_cTable) 0
95	#endif
96
97
98	/** @name Short macros for the MSR range entries.
99	*
100	* These are rather cryptic, but this is to reduce the attack on the right
101	* margin.
102	*
103	* @{ */
104	/** Alias one MSR onto another (a_uTarget). */
105	#define MAL(a_uMsr, a_szName, a_uTarget) \
106	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
107	/** Functions handles everything. */
108	#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
109	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
110	/** Functions handles everything, with GP mask. */
111	#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
112	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
113	/** Function handlers, read-only. */
114	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
115	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
116	/** Function handlers, ignore all writes. */
117	#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
118	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
119	/** Function handlers, with value. */
120	#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
121	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
122	/** Function handlers, with write ignore mask. */
123	#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
124	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
125	/** Function handlers, extended version. */
126	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
127	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
128	/** Function handlers, with CPUMCPU storage variable. */
129	#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
130	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
131	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
132	/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
133	#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
134	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
135	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
136	/** Read-only fixed value. */
137	#define MVO(a_uMsr, a_szName, a_uValue) \
138	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
139	/** Read-only fixed value, ignores all writes. */
140	#define MVI(a_uMsr, a_szName, a_uValue) \
141	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
142	/** Read fixed value, ignore writes outside GP mask. */
143	#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
144	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
145	/** Read fixed value, extended version with both GP and ignore masks. */
146	#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
147	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
148	/** The short form, no CPUM backing. */
149	#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
150	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
151	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
152
153	/** Range: Functions handles everything. */
154	#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
155	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
156	/** Range: Read fixed value, read-only. */
157	#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
158	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
159	/** Range: Read fixed value, ignore writes. */
160	#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
161	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
162	/** Range: The short form, no CPUM backing. */
163	#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
164	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
165	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
166
167	/** Internal form used by the macros. */
168	#ifdef VBOX_WITH_STATISTICS
169	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
170	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
171	{ 0 }, { 0 }, { 0 }, { 0 } }
172	#else
173	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
174	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
175	#endif
176	/** @} */
177
178
179	#include "cpus/Intel_Core_i7_3960X.h"
180	#include "cpus/Intel_Core_i5_3570.h"
181	#include "cpus/Intel_Core_i7_2635QM.h"
182	#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
183	#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
184	#include "cpus/Intel_Pentium_4_3_00GHz.h"
185
186	#include "cpus/AMD_FX_8150_Eight_Core.h"
187	#include "cpus/AMD_Phenom_II_X6_1100T.h"
188	#include "cpus/Quad_Core_AMD_Opteron_2384.h"
189	#include "cpus/AMD_Athlon_64_X2_Dual_Core_4200.h"
190	#include "cpus/AMD_Athlon_64_3200.h"
191
192	#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
193
194
195
196	/**
197	* The database entries.
198	*
199	* 1. The first entry is special. It is the fallback for unknown
200	* processors. Thus, it better be pretty representative.
201	*
202	* 2. The first entry for a CPU vendor is likewise important as it is
203	* the default entry for that vendor.
204	*
205	* Generally we put the most recent CPUs first, since these tend to have the
206	* most complicated and backwards compatible list of MSRs.
207	*/
208	static CPUMDBENTRY const * const g_apCpumDbEntries[] =
209	{
210	#ifdef VBOX_CPUDB_Intel_Core_i5_3570
211	&g_Entry_Intel_Core_i5_3570,
212	#endif
213	#ifdef VBOX_CPUDB_Intel_Core_i7_3960X
214	&g_Entry_Intel_Core_i7_3960X,
215	#endif
216	#ifdef VBOX_CPUDB_Intel_Core_i7_2635QM
217	&g_Entry_Intel_Core_i7_2635QM,
218	#endif
219	#ifdef Intel_Pentium_M_processor_2_00GHz
220	&g_Entry_Intel_Pentium_M_processor_2_00GHz,
221	#endif
222	#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz
223	&g_Entry_Intel_Xeon_X5482_3_20GHz,
224	#endif
225	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz
226	&g_Entry_Intel_Pentium_4_3_00GHz,
227	#endif
228
229	#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core
230	&g_Entry_AMD_FX_8150_Eight_Core,
231	#endif
232	#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T
233	&g_Entry_AMD_Phenom_II_X6_1100T,
234	#endif
235	#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384
236	&g_Entry_Quad_Core_AMD_Opteron_2384,
237	#endif
238	#ifdef VBOX_CPUDB_AMD_Athlon_64_X2_Dual_Core_4200
239	&g_Entry_AMD_Athlon_64_X2_Dual_Core_4200,
240	#endif
241	#ifdef VBOX_CPUDB_AMD_Athlon_64_3200
242	&g_Entry_AMD_Athlon_64_3200,
243	#endif
244
245	#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz
246	&g_Entry_VIA_QuadCore_L4700_1_2_GHz,
247	#endif
248	};
249
250
251	#ifndef CPUM_DB_STANDALONE
252
253	/**
254	* Binary search used by cpumR3MsrRangesInsert and has some special properties
255	* wrt to mismatches.
256	*
257	* @returns Insert location.
258	* @param paMsrRanges The MSR ranges to search.
259	* @param cMsrRanges The number of MSR ranges.
260	* @param uMsr What to search for.
261	*/
262	static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
263	{
264	if (!cMsrRanges)
265	return 0;
266
267	uint32_t iStart = 0;
268	uint32_t iLast = cMsrRanges - 1;
269	for (;;)
270	{
271	uint32_t i = iStart + (iLast - iStart + 1) / 2;
272	if ( uMsr >= paMsrRanges[i].uFirst
273	&& uMsr <= paMsrRanges[i].uLast)
274	return i;
275	if (uMsr < paMsrRanges[i].uFirst)
276	{
277	if (i <= iStart)
278	return i;
279	iLast = i - 1;
280	}
281	else
282	{
283	if (i >= iLast)
284	{
285	if (i < cMsrRanges)
286	i++;
287	return i;
288	}
289	iStart = i + 1;
290	}
291	}
292	}
293
294
295	/**
296	* Ensures that there is space for at least @a cNewRanges in the table,
297	* reallocating the table if necessary.
298	*
299	* @returns Pointer to the MSR ranges on success, NULL on failure. On failure
300	* @a *ppaMsrRanges is freed and set to NULL.
301	* @param pVM Pointer to the VM, used as the heap selector.
302	* Passing NULL uses the host-context heap, otherwise
303	* the VM's hyper heap is used.
304	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
305	* @param cMsrRanges The current number of ranges.
306	* @param cNewRanges The number of ranges to be added.
307	*/
308	static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
309	{
310	uint32_t cMsrRangesAllocated;
311	if (!pVM)
312	cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
313	else
314	{
315	/*
316	* We're using the hyper heap now, but when the range array was copied over to it from
317	* the host-context heap, we only copy the exact size and not the ensured size.
318	* See @bugref{7270}.
319	*/
320	cMsrRangesAllocated = cMsrRanges;
321	}
322	if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
323	{
324	void *pvNew;
325	uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
326	if (pVM)
327	{
328	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
329	Assert(cMsrRanges == pVM->cpum.s.GuestInfo.cMsrRanges);
330
331	size_t cb = cMsrRangesAllocated * sizeof(**ppaMsrRanges);
332	size_t cbNew = cNew * sizeof(**ppaMsrRanges);
333	int rc = MMR3HyperRealloc(pVM, *ppaMsrRanges, cb, 32, MM_TAG_CPUM_MSRS, cbNew, &pvNew);
334	if (RT_FAILURE(rc))
335	{
336	*ppaMsrRanges = NULL;
337	pVM->cpum.s.GuestInfo.paMsrRangesR0 = NIL_RTR0PTR;
338	pVM->cpum.s.GuestInfo.paMsrRangesRC = NIL_RTRCPTR;
339	LogRel(("CPUM: cpumR3MsrRangesEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
340	return NULL;
341	}
342	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
343	}
344	else
345	{
346	pvNew = RTMemRealloc(ppaMsrRanges, cNew sizeof(**ppaMsrRanges));
347	if (!pvNew)
348	{
349	RTMemFree(*ppaMsrRanges);
350	*ppaMsrRanges = NULL;
351	return NULL;
352	}
353	}
354	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
355	}
356
357	if (pVM)
358	{
359	/* Update R0 and RC pointers. */
360	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
361	pVM->cpum.s.GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, *ppaMsrRanges);
362	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, *ppaMsrRanges);
363	}
364
365	return *ppaMsrRanges;
366	}
367
368
369	/**
370	* Inserts a new MSR range in into an sorted MSR range array.
371	*
372	* If the new MSR range overlaps existing ranges, the existing ones will be
373	* adjusted/removed to fit in the new one.
374	*
375	* @returns VBox status code.
376	* @retval VINF_SUCCESS
377	* @retval VERR_NO_MEMORY
378	*
379	* @param pVM Pointer to the VM, used as the heap selector.
380	* Passing NULL uses the host-context heap, otherwise
381	* the hyper heap.
382	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
383	* Must be NULL if using the hyper heap.
384	* @param pcMsrRanges The variable holding number of ranges. Must be NULL
385	* if using the hyper heap.
386	* @param pNewRange The new range.
387	*/
388	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange)
389	{
390	Assert(pNewRange->uLast >= pNewRange->uFirst);
391	Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
392	Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
393
394	/*
395	* Validate and use the VM's MSR ranges array if we are using the hyper heap.
396	*/
397	if (pVM)
398	{
399	AssertReturn(!ppaMsrRanges, VERR_INVALID_PARAMETER);
400	AssertReturn(!pcMsrRanges, VERR_INVALID_PARAMETER);
401
402	ppaMsrRanges = &pVM->cpum.s.GuestInfo.paMsrRangesR3;
403	pcMsrRanges = &pVM->cpum.s.GuestInfo.cMsrRanges;
404	}
405
406	uint32_t cMsrRanges = *pcMsrRanges;
407	PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
408
409	/*
410	* Optimize the linear insertion case where we add new entries at the end.
411	*/
412	if ( cMsrRanges > 0
413	&& paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
414	{
415	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
416	if (!paMsrRanges)
417	return VERR_NO_MEMORY;
418	paMsrRanges[cMsrRanges] = *pNewRange;
419	*pcMsrRanges += 1;
420	}
421	else
422	{
423	uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
424	Assert(i == cMsrRanges \|\| pNewRange->uFirst <= paMsrRanges[i].uLast);
425	Assert(i == 0 \|\| pNewRange->uFirst > paMsrRanges[i - 1].uLast);
426
427	/*
428	* Adding an entirely new entry?
429	*/
430	if ( i >= cMsrRanges
431	\|\| pNewRange->uLast < paMsrRanges[i].uFirst)
432	{
433	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
434	if (!paMsrRanges)
435	return VERR_NO_MEMORY;
436	if (i < cMsrRanges)
437	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
438	paMsrRanges[i] = *pNewRange;
439	*pcMsrRanges += 1;
440	}
441	/*
442	* Replace existing entry?
443	*/
444	else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
445	&& pNewRange->uLast == paMsrRanges[i].uLast)
446	paMsrRanges[i] = *pNewRange;
447	/*
448	* Splitting an existing entry?
449	*/
450	else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
451	&& pNewRange->uLast < paMsrRanges[i].uLast)
452	{
453	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 2);
454	if (!paMsrRanges)
455	return VERR_NO_MEMORY;
456	if (i < cMsrRanges)
457	memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
458	paMsrRanges[i + 1] = *pNewRange;
459	paMsrRanges[i + 2] = paMsrRanges[i];
460	paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
461	paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
462	*pcMsrRanges += 2;
463	}
464	/*
465	* Complicated scenarios that can affect more than one range.
466	*
467	* The current code does not optimize memmove calls when replacing
468	* one or more existing ranges, because it's tedious to deal with and
469	* not expected to be a frequent usage scenario.
470	*/
471	else
472	{
473	/* Adjust start of first match? */
474	if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
475	&& pNewRange->uLast < paMsrRanges[i].uLast)
476	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
477	else
478	{
479	/* Adjust end of first match? */
480	if (pNewRange->uFirst > paMsrRanges[i].uFirst)
481	{
482	Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
483	paMsrRanges[i].uLast = pNewRange->uFirst - 1;
484	i++;
485	}
486	/* Replace the whole first match (lazy bird). */
487	else
488	{
489	if (i + 1 < cMsrRanges)
490	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
491	cMsrRanges = *pcMsrRanges -= 1;
492	}
493
494	/* Do the new range affect more ranges? */
495	while ( i < cMsrRanges
496	&& pNewRange->uLast >= paMsrRanges[i].uFirst)
497	{
498	if (pNewRange->uLast < paMsrRanges[i].uLast)
499	{
500	/* Adjust the start of it, then we're done. */
501	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
502	break;
503	}
504
505	/* Remove it entirely. */
506	if (i + 1 < cMsrRanges)
507	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
508	cMsrRanges = *pcMsrRanges -= 1;
509	}
510	}
511
512	/* Now, perform a normal insertion. */
513	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
514	if (!paMsrRanges)
515	return VERR_NO_MEMORY;
516	if (i < cMsrRanges)
517	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
518	paMsrRanges[i] = *pNewRange;
519	*pcMsrRanges += 1;
520	}
521	}
522
523	return VINF_SUCCESS;
524	}
525
526
527	/**
528	* Worker for cpumR3MsrApplyFudge that applies one table.
529	*
530	* @returns VBox status code.
531	* @param pVM Pointer to the cross context VM structure.
532	* @param paRanges Array of MSRs to fudge.
533	* @param cRanges Number of MSRs in the array.
534	*/
535	static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
536	{
537	for (uint32_t i = 0; i < cRanges; i++)
538	if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
539	{
540	LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
541	int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
542	&paRanges[i]);
543	if (RT_FAILURE(rc))
544	return rc;
545	}
546	return VINF_SUCCESS;
547	}
548
549
550	/**
551	* Fudges the MSRs that guest are known to access in some odd cases.
552	*
553	* A typical example is a VM that has been moved between different hosts where
554	* for instance the cpu vendor differs.
555	*
556	* @returns VBox status code.
557	* @param pVM Pointer to the cross context VM structure.
558	*/
559	int cpumR3MsrApplyFudge(PVM pVM)
560	{
561	/*
562	* Basic.
563	*/
564	static CPUMMSRRANGE const s_aFudgeMsrs[] =
565	{
566	MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
567	MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
568	MVO(0x00000017, "IA32_PLATFORM_ID", 0),
569	MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
570	MVI(0x0000008b, "BIOS_SIGN", 0),
571	MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
572	MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
573	MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
574	MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
575	MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
576	MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
577	MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
578	MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
579	MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
580	MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
581	MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
582	MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
583	};
584	int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
585	AssertLogRelRCReturn(rc, rc);
586
587	/*
588	* XP might mistake opterons and other newer CPUs for P4s.
589	*/
590	if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
591	{
592	static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
593	{
594	MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
595	};
596	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
597	AssertLogRelRCReturn(rc, rc);
598	}
599
600	return rc;
601	}
602
603
604	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
605	{
606	CPUMDBENTRY const *pEntry = NULL;
607	int rc;
608
609	if (!strcmp(pszName, "host"))
610	{
611	/*
612	* Create a CPU database entry for the host CPU. This means getting
613	* the CPUID bits from the real CPU and grabbing the closest matching
614	* database entry for MSRs.
615	*/
616	rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
617	if (RT_FAILURE(rc))
618	return rc;
619	rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
620	if (RT_FAILURE(rc))
621	return rc;
622
623	/* Lookup database entry for MSRs. */
624	CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
625	pInfo->paCpuIdLeavesR3[0].uEbx,
626	pInfo->paCpuIdLeavesR3[0].uEcx,
627	pInfo->paCpuIdLeavesR3[0].uEdx);
628	uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
629	uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
630	uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
631	uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
632	CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
633
634	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
635	{
636	CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
637	if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
638	{
639	/* Match against Family, Microarch, model and stepping. Except
640	for family, always match the closer with preference given to
641	the later/older ones. */
642	if (pCur->uFamily == uFamily)
643	{
644	if (pCur->enmMicroarch == enmMicroarch)
645	{
646	if (pCur->uModel == uModel)
647	{
648	if (pCur->uStepping == uStepping)
649	{
650	/* Perfect match. */
651	pEntry = pCur;
652	break;
653	}
654
655	if ( !pEntry
656	\|\| pEntry->uModel != uModel
657	\|\| pEntry->enmMicroarch != enmMicroarch
658	\|\| pEntry->uFamily != uFamily)
659	pEntry = pCur;
660	else if ( pCur->uStepping >= uStepping
661	? pCur->uStepping < pEntry->uStepping \|\| pEntry->uStepping < uStepping
662	: pCur->uStepping > pEntry->uStepping)
663	pEntry = pCur;
664	}
665	else if ( !pEntry
666	\|\| pEntry->enmMicroarch != enmMicroarch
667	\|\| pEntry->uFamily != uFamily)
668	pEntry = pCur;
669	else if ( pCur->uModel >= uModel
670	? pCur->uModel < pEntry->uModel \|\| pEntry->uModel < uModel
671	: pCur->uModel > pEntry->uModel)
672	pEntry = pCur;
673	}
674	else if ( !pEntry
675	\|\| pEntry->uFamily != uFamily)
676	pEntry = pCur;
677	else if ( pCur->enmMicroarch >= enmMicroarch
678	? pCur->enmMicroarch < pEntry->enmMicroarch \|\| pEntry->enmMicroarch < enmMicroarch
679	: pCur->enmMicroarch > pEntry->enmMicroarch)
680	pEntry = pCur;
681	}
682	/* We don't do closeness matching on family, we use the first
683	entry for the CPU vendor instead. (P4 workaround.) */
684	else if (!pEntry)
685	pEntry = pCur;
686	}
687	}
688
689	if (pEntry)
690	LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
691	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
692	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
693	pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
694	else
695	{
696	pEntry = g_apCpumDbEntries[0];
697	LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'\n",
698	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
699	pEntry->pszName));
700	}
701	}
702	else
703	{
704	/*
705	* We're supposed to be emulating a specific CPU that is included in
706	* our CPU database. The CPUID tables needs to be copied onto the
707	* heap so the caller can modify them and so they can be freed like
708	* in the host case above.
709	*/
710	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
711	if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
712	{
713	pEntry = g_apCpumDbEntries[i];
714	break;
715	}
716	if (!pEntry)
717	{
718	LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
719	return VERR_CPUM_DB_CPU_NOT_FOUND;
720	}
721
722	pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
723	if (pEntry->cCpuIdLeaves)
724	{
725	pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDup(pEntry->paCpuIdLeaves,
726	sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves);
727	if (!pInfo->paCpuIdLeavesR3)
728	return VERR_NO_MEMORY;
729	}
730	else
731	pInfo->paCpuIdLeavesR3 = NULL;
732
733	pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
734	pInfo->DefCpuId = pEntry->DefUnknownCpuId;
735
736	LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
737	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
738	pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
739	}
740
741	pInfo->fMsrMask = pEntry->fMsrMask;
742	pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
743	pInfo->uPadding = 0;
744	pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
745	pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
746	pInfo->paMsrRangesR0 = NIL_RTR0PTR;
747	pInfo->paCpuIdLeavesRC = NIL_RTRCPTR;
748	pInfo->paMsrRangesRC = NIL_RTRCPTR;
749
750	/*
751	* Copy the MSR range.
752	*/
753	uint32_t cMsrs = 0;
754	PCPUMMSRRANGE paMsrs = NULL;
755
756	PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
757	uint32_t cLeft = pEntry->cMsrRanges;
758	while (cLeft-- > 0)
759	{
760	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &paMsrs, &cMsrs, pCurMsr);
761	if (RT_FAILURE(rc))
762	{
763	Assert(!paMsrs); /* The above function frees this. */
764	RTMemFree(pInfo->paCpuIdLeavesR3);
765	pInfo->paCpuIdLeavesR3 = NULL;
766	return rc;
767	}
768	pCurMsr++;
769	}
770
771	pInfo->paMsrRangesR3 = paMsrs;
772	pInfo->cMsrRanges = cMsrs;
773	return VINF_SUCCESS;
774	}
775
776
777	/**
778	* Insert an MSR range into the VM.
779	*
780	* If the new MSR range overlaps existing ranges, the existing ones will be
781	* adjusted/removed to fit in the new one.
782	*
783	* @returns VBox status code.
784	* @param pVM Pointer to the cross context VM structure.
785	* @param pNewRange Pointer to the MSR range being inserted.
786	*/
787	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange)
788	{
789	AssertReturn(pVM, VERR_INVALID_PARAMETER);
790	AssertReturn(pNewRange, VERR_INVALID_PARAMETER);
791
792	return cpumR3MsrRangesInsert(pVM, NULL /* ppaMsrRanges /, NULL / pcMsrRanges */, pNewRange);
793	}
794
795
796	/**
797	* Register statistics for the MSRs.
798	*
799	* This must not be called before the MSRs have been finalized and moved to the
800	* hyper heap.
801	*
802	* @returns VBox status code.
803	* @param pVM Pointer to the cross context VM structure.
804	*/
805	int cpumR3MsrRegStats(PVM pVM)
806	{
807	/*
808	* Global statistics.
809	*/
810	PCPUM pCpum = &pVM->cpum.s;
811	STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
812	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
813	STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
814	STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
815	STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
816	STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
817	STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
818	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
819	STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
820	STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
821	STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
822	STAMUNIT_OCCURENCES, "Writing of ignored bits.");
823	STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
824	STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
825
826
827	# ifdef VBOX_WITH_STATISTICS
828	/*
829	* Per range.
830	*/
831	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
832	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
833	for (uint32_t i = 0; i < cRanges; i++)
834	{
835	char szName[160];
836	ssize_t cchName;
837
838	if (paRanges[i].uFirst == paRanges[i].uLast)
839	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
840	paRanges[i].uFirst, paRanges[i].szName);
841	else
842	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
843	paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
844
845	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
846	STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
847
848	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
849	STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
850
851	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
852	STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
853
854	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
855	STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
856	}
857	# endif /* VBOX_WITH_STATISTICS */
858
859	return VINF_SUCCESS;
860	}
861
862	#endif /* !CPUM_DB_STANDALONE */
863

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 57394

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