CPUMR3Db.cpp@ 58561

Last change on this file since 58561 was 58561, checked in by vboxsync, 9 years ago
CPUMR3Db.cpp: Adjusted the 'host' matching in cpumR3DbGetCpuInfo to not pick Atom profiles for Core cpus just because the march enum value is higher.
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File size: 39.8 KB

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1	/* $Id: CPUMR3Db.cpp 58561 2015-11-04 13:35:11Z vboxsync $ */
2	/** @file
3	* CPUM - CPU database part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/mm.h>
27
28	#include <VBox/err.h>
29	#include <iprt/asm-amd64-x86.h>
30	#include <iprt/mem.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Structures and Typedefs *
36	*********************************************************************************************************************************/
37	typedef struct CPUMDBENTRY
38	{
39	/** The CPU name. */
40	const char *pszName;
41	/** The full CPU name. */
42	const char *pszFullName;
43	/** The CPU vendor (CPUMCPUVENDOR). */
44	uint8_t enmVendor;
45	/** The CPU family. */
46	uint8_t uFamily;
47	/** The CPU model. */
48	uint8_t uModel;
49	/** The CPU stepping. */
50	uint8_t uStepping;
51	/** The microarchitecture. */
52	CPUMMICROARCH enmMicroarch;
53	/** Scalable bus frequency used for reporting other frequencies. */
54	uint64_t uScalableBusFreq;
55	/** Flags (TBD). */
56	uint32_t fFlags;
57	/** The maximum physical address with of the CPU. This should correspond to
58	* the value in CPUID leaf 0x80000008 when present. */
59	uint8_t cMaxPhysAddrWidth;
60	/** Pointer to an array of CPUID leaves. */
61	PCCPUMCPUIDLEAF paCpuIdLeaves;
62	/** The number of CPUID leaves in the array paCpuIdLeaves points to. */
63	uint32_t cCpuIdLeaves;
64	/** The method used to deal with unknown CPUID leaves. */
65	CPUMUNKNOWNCPUID enmUnknownCpuId;
66	/** The default unknown CPUID value. */
67	CPUMCPUID DefUnknownCpuId;
68
69	/** MSR mask. Several microarchitectures ignore higher bits of the */
70	uint32_t fMsrMask;
71
72	/** The number of ranges in the table pointed to b paMsrRanges. */
73	uint32_t cMsrRanges;
74	/** MSR ranges for this CPU. */
75	PCCPUMMSRRANGE paMsrRanges;
76	} CPUMDBENTRY;
77
78
79	/*********************************************************************************************************************************
80	* Defined Constants And Macros *
81	*********************************************************************************************************************************/
82
83	/** @def NULL_ALONE
84	* For eliminating an unnecessary data dependency in standalone builds (for
85	* VBoxSVC). */
86	/** @def ZERO_ALONE
87	* For eliminating an unnecessary data size dependency in standalone builds (for
88	* VBoxSVC). */
89	#ifndef CPUM_DB_STANDALONE
90	# define NULL_ALONE(a_aTable) a_aTable
91	# define ZERO_ALONE(a_cTable) a_cTable
92	#else
93	# define NULL_ALONE(a_aTable) NULL
94	# define ZERO_ALONE(a_cTable) 0
95	#endif
96
97
98	/** @name Short macros for the MSR range entries.
99	*
100	* These are rather cryptic, but this is to reduce the attack on the right
101	* margin.
102	*
103	* @{ */
104	/** Alias one MSR onto another (a_uTarget). */
105	#define MAL(a_uMsr, a_szName, a_uTarget) \
106	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
107	/** Functions handles everything. */
108	#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
109	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
110	/** Functions handles everything, with GP mask. */
111	#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
112	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
113	/** Function handlers, read-only. */
114	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
115	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
116	/** Function handlers, ignore all writes. */
117	#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
118	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
119	/** Function handlers, with value. */
120	#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
121	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
122	/** Function handlers, with write ignore mask. */
123	#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
124	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
125	/** Function handlers, extended version. */
126	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
127	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
128	/** Function handlers, with CPUMCPU storage variable. */
129	#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
130	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
131	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
132	/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
133	#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
134	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
135	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
136	/** Read-only fixed value. */
137	#define MVO(a_uMsr, a_szName, a_uValue) \
138	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
139	/** Read-only fixed value, ignores all writes. */
140	#define MVI(a_uMsr, a_szName, a_uValue) \
141	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
142	/** Read fixed value, ignore writes outside GP mask. */
143	#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
144	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
145	/** Read fixed value, extended version with both GP and ignore masks. */
146	#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
147	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
148	/** The short form, no CPUM backing. */
149	#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
150	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
151	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
152
153	/** Range: Functions handles everything. */
154	#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
155	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
156	/** Range: Read fixed value, read-only. */
157	#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
158	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
159	/** Range: Read fixed value, ignore writes. */
160	#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
161	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
162	/** Range: The short form, no CPUM backing. */
163	#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
164	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
165	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
166
167	/** Internal form used by the macros. */
168	#ifdef VBOX_WITH_STATISTICS
169	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
170	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
171	{ 0 }, { 0 }, { 0 }, { 0 } }
172	#else
173	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
174	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
175	#endif
176	/** @} */
177
178
179	#include "cpus/Intel_Core_i7_3960X.h"
180	#include "cpus/Intel_Core_i5_3570.h"
181	#include "cpus/Intel_Core_i7_2635QM.h"
182	#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
183	#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
184	#include "cpus/Intel_Pentium_4_3_00GHz.h"
185	#include "cpus/Intel_Atom_330_1_60GHz.h"
186
187	#include "cpus/AMD_FX_8150_Eight_Core.h"
188	#include "cpus/AMD_Phenom_II_X6_1100T.h"
189	#include "cpus/Quad_Core_AMD_Opteron_2384.h"
190	#include "cpus/AMD_Athlon_64_X2_Dual_Core_4200.h"
191	#include "cpus/AMD_Athlon_64_3200.h"
192
193	#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
194
195
196
197	/**
198	* The database entries.
199	*
200	* 1. The first entry is special. It is the fallback for unknown
201	* processors. Thus, it better be pretty representative.
202	*
203	* 2. The first entry for a CPU vendor is likewise important as it is
204	* the default entry for that vendor.
205	*
206	* Generally we put the most recent CPUs first, since these tend to have the
207	* most complicated and backwards compatible list of MSRs.
208	*/
209	static CPUMDBENTRY const * const g_apCpumDbEntries[] =
210	{
211	#ifdef VBOX_CPUDB_Intel_Core_i5_3570
212	&g_Entry_Intel_Core_i5_3570,
213	#endif
214	#ifdef VBOX_CPUDB_Intel_Core_i7_3960X
215	&g_Entry_Intel_Core_i7_3960X,
216	#endif
217	#ifdef VBOX_CPUDB_Intel_Core_i7_2635QM
218	&g_Entry_Intel_Core_i7_2635QM,
219	#endif
220	#ifdef VBOX_CPUDB_Intel_Atom_330_1_60GHz
221	&g_Entry_Intel_Atom_330_1_60GHz,
222	#endif
223	#ifdef Intel_Pentium_M_processor_2_00GHz
224	&g_Entry_Intel_Pentium_M_processor_2_00GHz,
225	#endif
226	#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz
227	&g_Entry_Intel_Xeon_X5482_3_20GHz,
228	#endif
229	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz
230	&g_Entry_Intel_Pentium_4_3_00GHz,
231	#endif
232
233	#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core
234	&g_Entry_AMD_FX_8150_Eight_Core,
235	#endif
236	#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T
237	&g_Entry_AMD_Phenom_II_X6_1100T,
238	#endif
239	#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384
240	&g_Entry_Quad_Core_AMD_Opteron_2384,
241	#endif
242	#ifdef VBOX_CPUDB_AMD_Athlon_64_X2_Dual_Core_4200
243	&g_Entry_AMD_Athlon_64_X2_Dual_Core_4200,
244	#endif
245	#ifdef VBOX_CPUDB_AMD_Athlon_64_3200
246	&g_Entry_AMD_Athlon_64_3200,
247	#endif
248
249	#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz
250	&g_Entry_VIA_QuadCore_L4700_1_2_GHz,
251	#endif
252	};
253
254
255	#ifndef CPUM_DB_STANDALONE
256
257	/**
258	* Binary search used by cpumR3MsrRangesInsert and has some special properties
259	* wrt to mismatches.
260	*
261	* @returns Insert location.
262	* @param paMsrRanges The MSR ranges to search.
263	* @param cMsrRanges The number of MSR ranges.
264	* @param uMsr What to search for.
265	*/
266	static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
267	{
268	if (!cMsrRanges)
269	return 0;
270
271	uint32_t iStart = 0;
272	uint32_t iLast = cMsrRanges - 1;
273	for (;;)
274	{
275	uint32_t i = iStart + (iLast - iStart + 1) / 2;
276	if ( uMsr >= paMsrRanges[i].uFirst
277	&& uMsr <= paMsrRanges[i].uLast)
278	return i;
279	if (uMsr < paMsrRanges[i].uFirst)
280	{
281	if (i <= iStart)
282	return i;
283	iLast = i - 1;
284	}
285	else
286	{
287	if (i >= iLast)
288	{
289	if (i < cMsrRanges)
290	i++;
291	return i;
292	}
293	iStart = i + 1;
294	}
295	}
296	}
297
298
299	/**
300	* Ensures that there is space for at least @a cNewRanges in the table,
301	* reallocating the table if necessary.
302	*
303	* @returns Pointer to the MSR ranges on success, NULL on failure. On failure
304	* @a *ppaMsrRanges is freed and set to NULL.
305	* @param pVM The cross context VM structure. If NULL,
306	* use the process heap, otherwise the VM's hyper heap.
307	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
308	* @param cMsrRanges The current number of ranges.
309	* @param cNewRanges The number of ranges to be added.
310	*/
311	static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
312	{
313	uint32_t cMsrRangesAllocated;
314	if (!pVM)
315	cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
316	else
317	{
318	/*
319	* We're using the hyper heap now, but when the range array was copied over to it from
320	* the host-context heap, we only copy the exact size and not the ensured size.
321	* See @bugref{7270}.
322	*/
323	cMsrRangesAllocated = cMsrRanges;
324	}
325	if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
326	{
327	void *pvNew;
328	uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
329	if (pVM)
330	{
331	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
332	Assert(cMsrRanges == pVM->cpum.s.GuestInfo.cMsrRanges);
333
334	size_t cb = cMsrRangesAllocated * sizeof(**ppaMsrRanges);
335	size_t cbNew = cNew * sizeof(**ppaMsrRanges);
336	int rc = MMR3HyperRealloc(pVM, *ppaMsrRanges, cb, 32, MM_TAG_CPUM_MSRS, cbNew, &pvNew);
337	if (RT_FAILURE(rc))
338	{
339	*ppaMsrRanges = NULL;
340	pVM->cpum.s.GuestInfo.paMsrRangesR0 = NIL_RTR0PTR;
341	pVM->cpum.s.GuestInfo.paMsrRangesRC = NIL_RTRCPTR;
342	LogRel(("CPUM: cpumR3MsrRangesEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
343	return NULL;
344	}
345	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
346	}
347	else
348	{
349	pvNew = RTMemRealloc(ppaMsrRanges, cNew sizeof(**ppaMsrRanges));
350	if (!pvNew)
351	{
352	RTMemFree(*ppaMsrRanges);
353	*ppaMsrRanges = NULL;
354	return NULL;
355	}
356	}
357	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
358	}
359
360	if (pVM)
361	{
362	/* Update R0 and RC pointers. */
363	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
364	pVM->cpum.s.GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, *ppaMsrRanges);
365	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, *ppaMsrRanges);
366	}
367
368	return *ppaMsrRanges;
369	}
370
371
372	/**
373	* Inserts a new MSR range in into an sorted MSR range array.
374	*
375	* If the new MSR range overlaps existing ranges, the existing ones will be
376	* adjusted/removed to fit in the new one.
377	*
378	* @returns VBox status code.
379	* @retval VINF_SUCCESS
380	* @retval VERR_NO_MEMORY
381	*
382	* @param pVM The cross context VM structure. If NULL,
383	* use the process heap, otherwise the VM's hyper heap.
384	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
385	* Must be NULL if using the hyper heap.
386	* @param pcMsrRanges The variable holding number of ranges. Must be NULL
387	* if using the hyper heap.
388	* @param pNewRange The new range.
389	*/
390	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange)
391	{
392	Assert(pNewRange->uLast >= pNewRange->uFirst);
393	Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
394	Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
395
396	/*
397	* Validate and use the VM's MSR ranges array if we are using the hyper heap.
398	*/
399	if (pVM)
400	{
401	AssertReturn(!ppaMsrRanges, VERR_INVALID_PARAMETER);
402	AssertReturn(!pcMsrRanges, VERR_INVALID_PARAMETER);
403
404	ppaMsrRanges = &pVM->cpum.s.GuestInfo.paMsrRangesR3;
405	pcMsrRanges = &pVM->cpum.s.GuestInfo.cMsrRanges;
406	}
407
408	uint32_t cMsrRanges = *pcMsrRanges;
409	PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
410
411	/*
412	* Optimize the linear insertion case where we add new entries at the end.
413	*/
414	if ( cMsrRanges > 0
415	&& paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
416	{
417	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
418	if (!paMsrRanges)
419	return VERR_NO_MEMORY;
420	paMsrRanges[cMsrRanges] = *pNewRange;
421	*pcMsrRanges += 1;
422	}
423	else
424	{
425	uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
426	Assert(i == cMsrRanges \|\| pNewRange->uFirst <= paMsrRanges[i].uLast);
427	Assert(i == 0 \|\| pNewRange->uFirst > paMsrRanges[i - 1].uLast);
428
429	/*
430	* Adding an entirely new entry?
431	*/
432	if ( i >= cMsrRanges
433	\|\| pNewRange->uLast < paMsrRanges[i].uFirst)
434	{
435	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
436	if (!paMsrRanges)
437	return VERR_NO_MEMORY;
438	if (i < cMsrRanges)
439	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
440	paMsrRanges[i] = *pNewRange;
441	*pcMsrRanges += 1;
442	}
443	/*
444	* Replace existing entry?
445	*/
446	else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
447	&& pNewRange->uLast == paMsrRanges[i].uLast)
448	paMsrRanges[i] = *pNewRange;
449	/*
450	* Splitting an existing entry?
451	*/
452	else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
453	&& pNewRange->uLast < paMsrRanges[i].uLast)
454	{
455	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 2);
456	if (!paMsrRanges)
457	return VERR_NO_MEMORY;
458	if (i < cMsrRanges)
459	memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
460	paMsrRanges[i + 1] = *pNewRange;
461	paMsrRanges[i + 2] = paMsrRanges[i];
462	paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
463	paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
464	*pcMsrRanges += 2;
465	}
466	/*
467	* Complicated scenarios that can affect more than one range.
468	*
469	* The current code does not optimize memmove calls when replacing
470	* one or more existing ranges, because it's tedious to deal with and
471	* not expected to be a frequent usage scenario.
472	*/
473	else
474	{
475	/* Adjust start of first match? */
476	if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
477	&& pNewRange->uLast < paMsrRanges[i].uLast)
478	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
479	else
480	{
481	/* Adjust end of first match? */
482	if (pNewRange->uFirst > paMsrRanges[i].uFirst)
483	{
484	Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
485	paMsrRanges[i].uLast = pNewRange->uFirst - 1;
486	i++;
487	}
488	/* Replace the whole first match (lazy bird). */
489	else
490	{
491	if (i + 1 < cMsrRanges)
492	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
493	cMsrRanges = *pcMsrRanges -= 1;
494	}
495
496	/* Do the new range affect more ranges? */
497	while ( i < cMsrRanges
498	&& pNewRange->uLast >= paMsrRanges[i].uFirst)
499	{
500	if (pNewRange->uLast < paMsrRanges[i].uLast)
501	{
502	/* Adjust the start of it, then we're done. */
503	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
504	break;
505	}
506
507	/* Remove it entirely. */
508	if (i + 1 < cMsrRanges)
509	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
510	cMsrRanges = *pcMsrRanges -= 1;
511	}
512	}
513
514	/* Now, perform a normal insertion. */
515	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
516	if (!paMsrRanges)
517	return VERR_NO_MEMORY;
518	if (i < cMsrRanges)
519	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
520	paMsrRanges[i] = *pNewRange;
521	*pcMsrRanges += 1;
522	}
523	}
524
525	return VINF_SUCCESS;
526	}
527
528
529	/**
530	* Worker for cpumR3MsrApplyFudge that applies one table.
531	*
532	* @returns VBox status code.
533	* @param pVM The cross context VM structure.
534	* @param paRanges Array of MSRs to fudge.
535	* @param cRanges Number of MSRs in the array.
536	*/
537	static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
538	{
539	for (uint32_t i = 0; i < cRanges; i++)
540	if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
541	{
542	LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
543	int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
544	&paRanges[i]);
545	if (RT_FAILURE(rc))
546	return rc;
547	}
548	return VINF_SUCCESS;
549	}
550
551
552	/**
553	* Fudges the MSRs that guest are known to access in some odd cases.
554	*
555	* A typical example is a VM that has been moved between different hosts where
556	* for instance the cpu vendor differs.
557	*
558	* @returns VBox status code.
559	* @param pVM The cross context VM structure.
560	*/
561	int cpumR3MsrApplyFudge(PVM pVM)
562	{
563	/*
564	* Basic.
565	*/
566	static CPUMMSRRANGE const s_aFudgeMsrs[] =
567	{
568	MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
569	MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
570	MVO(0x00000017, "IA32_PLATFORM_ID", 0),
571	MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
572	MVI(0x0000008b, "BIOS_SIGN", 0),
573	MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
574	MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
575	MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
576	MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
577	MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
578	MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
579	MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
580	MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
581	MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
582	MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
583	MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
584	MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
585	};
586	int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
587	AssertLogRelRCReturn(rc, rc);
588
589	/*
590	* XP might mistake opterons and other newer CPUs for P4s.
591	*/
592	if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
593	{
594	static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
595	{
596	MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
597	};
598	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
599	AssertLogRelRCReturn(rc, rc);
600	}
601
602	return rc;
603	}
604
605
606	/**
607	* Do we consider @a enmConsider a better match for @a enmTarget than
608	* @a enmFound?
609	*
610	* Only called when @a enmConsider isn't exactly what we're looking for.
611	*
612	* @returns true/false.
613	* @param enmConsider The new microarch to consider.
614	* @param enmTarget The target microarch.
615	* @param enmFound The best microarch match we've found thus far.
616	*/
617	DECLINLINE(bool) cpumR3DbIsBetterMarchMatch(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
618	{
619	Assert(enmConsider != enmTarget);
620
621	/*
622	* If we've got an march match, don't bother with enmConsider.
623	*/
624	if (enmFound == enmTarget)
625	return false;
626
627	/*
628	* Found is below: Pick 'consider' if it's closer to the target or above it.
629	*/
630	if (enmFound < enmTarget)
631	return enmConsider > enmFound;
632
633	/*
634	* Found is above: Pick 'consider' if it's also above (paranoia: or equal)
635	* and but closer to the target.
636	*/
637	return enmConsider >= enmTarget && enmConsider < enmFound;
638	}
639
640
641	/**
642	* Do we consider @a enmConsider a better match for @a enmTarget than
643	* @a enmFound?
644	*
645	* Only called for intel family 06h CPUs.
646	*
647	* @returns true/false.
648	* @param enmConsider The new microarch to consider.
649	* @param enmTarget The target microarch.
650	* @param enmFound The best microarch match we've found thus far.
651	*/
652	static bool cpumR3DbIsBetterIntelFam06Match(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
653	{
654	/* Check intel family 06h claims. */
655	AssertReturn(enmConsider >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmConsider <= kCpumMicroarch_Intel_P6_Core_Atom_End,
656	false);
657	AssertReturn(enmTarget >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmTarget <= kCpumMicroarch_Intel_P6_Core_Atom_End,
658	false);
659
660	/* Put matches out of the way. */
661	if (enmConsider == enmTarget)
662	return true;
663	if (enmFound == enmTarget)
664	return false;
665
666	/* If found isn't a family 06h march, whatever we're considering must be a better choice. */
667	if ( enmFound < kCpumMicroarch_Intel_P6_Core_Atom_First
668	\|\| enmFound > kCpumMicroarch_Intel_P6_Core_Atom_End)
669	return true;
670
671	/*
672	* The family 06h stuff is split into three categories:
673	* - Common P6 heritage
674	* - Core
675	* - Atom
676	*
677	* Determin which of the three arguments are Atom marchs, because that's
678	* all we need to make the right choice.
679	*/
680	bool const fConsiderAtom = enmConsider >= kCpumMicroarch_Intel_Atom_First;
681	bool const fTargetAtom = enmTarget >= kCpumMicroarch_Intel_Atom_First;
682	bool const fFoundAtom = enmFound >= kCpumMicroarch_Intel_Atom_First;
683
684	/*
685	* Want atom:
686	*/
687	if (fTargetAtom)
688	{
689	/* Pick the atom if we've got one of each.*/
690	if (fConsiderAtom != fFoundAtom)
691	return fConsiderAtom;
692	/* If we haven't got any atoms under consideration, pick a P6 or the earlier core.
693	Note! Not entirely sure Dothan is the best choice, but it'll do for now. */
694	if (!fConsiderAtom)
695	{
696	if (enmConsider > enmFound)
697	return enmConsider <= kCpumMicroarch_Intel_P6_M_Dothan;
698	return enmFound > kCpumMicroarch_Intel_P6_M_Dothan;
699	}
700	/* else: same category, default comparison rules. */
701	Assert(fConsiderAtom && fFoundAtom);
702	}
703	/*
704	* Want non-atom:
705	*/
706	/* Pick the non-atom if we've got one of each. */
707	else if (fConsiderAtom != fFoundAtom)
708	return fFoundAtom;
709	/* If we've only got atoms under consideration, pick the older one just to pick something. */
710	else if (fConsiderAtom)
711	return enmConsider < enmFound;
712	else
713	Assert(!fConsiderAtom && !fFoundAtom);
714
715	/*
716	* Same basic category. Do same compare as caller.
717	*/
718	return cpumR3DbIsBetterMarchMatch(enmConsider, enmTarget, enmFound);
719	}
720
721
722	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
723	{
724	CPUMDBENTRY const *pEntry = NULL;
725	int rc;
726
727	if (!strcmp(pszName, "host"))
728	{
729	/*
730	* Create a CPU database entry for the host CPU. This means getting
731	* the CPUID bits from the real CPU and grabbing the closest matching
732	* database entry for MSRs.
733	*/
734	rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
735	if (RT_FAILURE(rc))
736	return rc;
737	rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
738	if (RT_FAILURE(rc))
739	return rc;
740
741	/* Lookup database entry for MSRs. */
742	CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
743	pInfo->paCpuIdLeavesR3[0].uEbx,
744	pInfo->paCpuIdLeavesR3[0].uEcx,
745	pInfo->paCpuIdLeavesR3[0].uEdx);
746	uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
747	uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
748	uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
749	uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
750	CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
751
752	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
753	{
754	CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
755	if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
756	{
757	/* Match against Family, Microarch, model and stepping. Except
758	for family, always match the closer with preference given to
759	the later/older ones. */
760	if (pCur->uFamily == uFamily)
761	{
762	if (pCur->enmMicroarch == enmMicroarch)
763	{
764	if (pCur->uModel == uModel)
765	{
766	if (pCur->uStepping == uStepping)
767	{
768	/* Perfect match. */
769	pEntry = pCur;
770	break;
771	}
772
773	if ( !pEntry
774	\|\| pEntry->uModel != uModel
775	\|\| pEntry->enmMicroarch != enmMicroarch
776	\|\| pEntry->uFamily != uFamily)
777	pEntry = pCur;
778	else if ( pCur->uStepping >= uStepping
779	? pCur->uStepping < pEntry->uStepping \|\| pEntry->uStepping < uStepping
780	: pCur->uStepping > pEntry->uStepping)
781	pEntry = pCur;
782	}
783	else if ( !pEntry
784	\|\| pEntry->enmMicroarch != enmMicroarch
785	\|\| pEntry->uFamily != uFamily)
786	pEntry = pCur;
787	else if ( pCur->uModel >= uModel
788	? pCur->uModel < pEntry->uModel \|\| pEntry->uModel < uModel
789	: pCur->uModel > pEntry->uModel)
790	pEntry = pCur;
791	}
792	else if ( !pEntry
793	\|\| pEntry->uFamily != uFamily)
794	pEntry = pCur;
795	/* Special march matching rules applies to intel family 06h. */
796	else if ( enmVendor == CPUMCPUVENDOR_INTEL
797	&& uFamily == 6
798	? cpumR3DbIsBetterIntelFam06Match(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch)
799	: cpumR3DbIsBetterMarchMatch(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch))
800	pEntry = pCur;
801	}
802	/* We don't do closeness matching on family, we use the first
803	entry for the CPU vendor instead. (P4 workaround.) */
804	else if (!pEntry)
805	pEntry = pCur;
806	}
807	}
808
809	if (pEntry)
810	LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
811	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
812	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
813	pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
814	else
815	{
816	pEntry = g_apCpumDbEntries[0];
817	LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'\n",
818	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
819	pEntry->pszName));
820	}
821	}
822	else
823	{
824	/*
825	* We're supposed to be emulating a specific CPU that is included in
826	* our CPU database. The CPUID tables needs to be copied onto the
827	* heap so the caller can modify them and so they can be freed like
828	* in the host case above.
829	*/
830	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
831	if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
832	{
833	pEntry = g_apCpumDbEntries[i];
834	break;
835	}
836	if (!pEntry)
837	{
838	LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
839	return VERR_CPUM_DB_CPU_NOT_FOUND;
840	}
841
842	pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
843	if (pEntry->cCpuIdLeaves)
844	{
845	pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDup(pEntry->paCpuIdLeaves,
846	sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves);
847	if (!pInfo->paCpuIdLeavesR3)
848	return VERR_NO_MEMORY;
849	}
850	else
851	pInfo->paCpuIdLeavesR3 = NULL;
852
853	pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
854	pInfo->DefCpuId = pEntry->DefUnknownCpuId;
855
856	LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
857	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
858	pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
859	}
860
861	pInfo->fMsrMask = pEntry->fMsrMask;
862	pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
863	pInfo->uPadding = 0;
864	pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
865	pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
866	pInfo->paMsrRangesR0 = NIL_RTR0PTR;
867	pInfo->paCpuIdLeavesRC = NIL_RTRCPTR;
868	pInfo->paMsrRangesRC = NIL_RTRCPTR;
869
870	/*
871	* Copy the MSR range.
872	*/
873	uint32_t cMsrs = 0;
874	PCPUMMSRRANGE paMsrs = NULL;
875
876	PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
877	uint32_t cLeft = pEntry->cMsrRanges;
878	while (cLeft-- > 0)
879	{
880	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &paMsrs, &cMsrs, pCurMsr);
881	if (RT_FAILURE(rc))
882	{
883	Assert(!paMsrs); /* The above function frees this. */
884	RTMemFree(pInfo->paCpuIdLeavesR3);
885	pInfo->paCpuIdLeavesR3 = NULL;
886	return rc;
887	}
888	pCurMsr++;
889	}
890
891	pInfo->paMsrRangesR3 = paMsrs;
892	pInfo->cMsrRanges = cMsrs;
893	return VINF_SUCCESS;
894	}
895
896
897	/**
898	* Insert an MSR range into the VM.
899	*
900	* If the new MSR range overlaps existing ranges, the existing ones will be
901	* adjusted/removed to fit in the new one.
902	*
903	* @returns VBox status code.
904	* @param pVM The cross context VM structure.
905	* @param pNewRange Pointer to the MSR range being inserted.
906	*/
907	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange)
908	{
909	AssertReturn(pVM, VERR_INVALID_PARAMETER);
910	AssertReturn(pNewRange, VERR_INVALID_PARAMETER);
911
912	return cpumR3MsrRangesInsert(pVM, NULL /* ppaMsrRanges /, NULL / pcMsrRanges */, pNewRange);
913	}
914
915
916	/**
917	* Register statistics for the MSRs.
918	*
919	* This must not be called before the MSRs have been finalized and moved to the
920	* hyper heap.
921	*
922	* @returns VBox status code.
923	* @param pVM The cross context VM structure.
924	*/
925	int cpumR3MsrRegStats(PVM pVM)
926	{
927	/*
928	* Global statistics.
929	*/
930	PCPUM pCpum = &pVM->cpum.s;
931	STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
932	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
933	STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
934	STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
935	STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
936	STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
937	STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
938	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
939	STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
940	STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
941	STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
942	STAMUNIT_OCCURENCES, "Writing of ignored bits.");
943	STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
944	STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
945
946
947	# ifdef VBOX_WITH_STATISTICS
948	/*
949	* Per range.
950	*/
951	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
952	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
953	for (uint32_t i = 0; i < cRanges; i++)
954	{
955	char szName[160];
956	ssize_t cchName;
957
958	if (paRanges[i].uFirst == paRanges[i].uLast)
959	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
960	paRanges[i].uFirst, paRanges[i].szName);
961	else
962	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
963	paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
964
965	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
966	STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
967
968	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
969	STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
970
971	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
972	STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
973
974	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
975	STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
976	}
977	# endif /* VBOX_WITH_STATISTICS */
978
979	return VINF_SUCCESS;
980	}
981
982	#endif /* !CPUM_DB_STANDALONE */
983

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 58561

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