CPUMR3Db.cpp@ 60601

Last change on this file since 60601 was 60411, checked in by vboxsync, 9 years ago
VMM,Main: Added 286, 186 and 8086 CPU profiles to play with.
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1	/* $Id: CPUMR3Db.cpp 60411 2016-04-10 17:16:09Z vboxsync $ */
2	/** @file
3	* CPUM - CPU database part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/mm.h>
27
28	#include <VBox/err.h>
29	#include <iprt/asm-amd64-x86.h>
30	#include <iprt/mem.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Structures and Typedefs *
36	*********************************************************************************************************************************/
37	typedef struct CPUMDBENTRY
38	{
39	/** The CPU name. */
40	const char *pszName;
41	/** The full CPU name. */
42	const char *pszFullName;
43	/** The CPU vendor (CPUMCPUVENDOR). */
44	uint8_t enmVendor;
45	/** The CPU family. */
46	uint8_t uFamily;
47	/** The CPU model. */
48	uint8_t uModel;
49	/** The CPU stepping. */
50	uint8_t uStepping;
51	/** The microarchitecture. */
52	CPUMMICROARCH enmMicroarch;
53	/** Scalable bus frequency used for reporting other frequencies. */
54	uint64_t uScalableBusFreq;
55	/** Flags - CPUDB_F_XXX. */
56	uint32_t fFlags;
57	/** The maximum physical address with of the CPU. This should correspond to
58	* the value in CPUID leaf 0x80000008 when present. */
59	uint8_t cMaxPhysAddrWidth;
60	/** Pointer to an array of CPUID leaves. */
61	PCCPUMCPUIDLEAF paCpuIdLeaves;
62	/** The number of CPUID leaves in the array paCpuIdLeaves points to. */
63	uint32_t cCpuIdLeaves;
64	/** The method used to deal with unknown CPUID leaves. */
65	CPUMUNKNOWNCPUID enmUnknownCpuId;
66	/** The default unknown CPUID value. */
67	CPUMCPUID DefUnknownCpuId;
68
69	/** MSR mask. Several microarchitectures ignore higher bits of the */
70	uint32_t fMsrMask;
71
72	/** The number of ranges in the table pointed to b paMsrRanges. */
73	uint32_t cMsrRanges;
74	/** MSR ranges for this CPU. */
75	PCCPUMMSRRANGE paMsrRanges;
76	} CPUMDBENTRY;
77
78
79	/*********************************************************************************************************************************
80	* Defined Constants And Macros *
81	*********************************************************************************************************************************/
82	/** @name CPUDB_F_XXX - CPUDBENTRY::fFlags
83	* @{ */
84	/** Should execute all in IEM.
85	* @todo Implement this - currently done in Main... */
86	#define CPUDB_F_EXECUTE_ALL_IN_IEM RT_BIT_32(0)
87	/** @} */
88
89
90	/** @def NULL_ALONE
91	* For eliminating an unnecessary data dependency in standalone builds (for
92	* VBoxSVC). */
93	/** @def ZERO_ALONE
94	* For eliminating an unnecessary data size dependency in standalone builds (for
95	* VBoxSVC). */
96	#ifndef CPUM_DB_STANDALONE
97	# define NULL_ALONE(a_aTable) a_aTable
98	# define ZERO_ALONE(a_cTable) a_cTable
99	#else
100	# define NULL_ALONE(a_aTable) NULL
101	# define ZERO_ALONE(a_cTable) 0
102	#endif
103
104
105	/** @name Short macros for the MSR range entries.
106	*
107	* These are rather cryptic, but this is to reduce the attack on the right
108	* margin.
109	*
110	* @{ */
111	/** Alias one MSR onto another (a_uTarget). */
112	#define MAL(a_uMsr, a_szName, a_uTarget) \
113	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
114	/** Functions handles everything. */
115	#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
116	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
117	/** Functions handles everything, with GP mask. */
118	#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
119	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
120	/** Function handlers, read-only. */
121	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
122	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
123	/** Function handlers, ignore all writes. */
124	#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
125	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
126	/** Function handlers, with value. */
127	#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
128	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
129	/** Function handlers, with write ignore mask. */
130	#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
131	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
132	/** Function handlers, extended version. */
133	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
134	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
135	/** Function handlers, with CPUMCPU storage variable. */
136	#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
137	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
138	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
139	/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
140	#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
141	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
142	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
143	/** Read-only fixed value. */
144	#define MVO(a_uMsr, a_szName, a_uValue) \
145	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
146	/** Read-only fixed value, ignores all writes. */
147	#define MVI(a_uMsr, a_szName, a_uValue) \
148	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
149	/** Read fixed value, ignore writes outside GP mask. */
150	#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
151	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
152	/** Read fixed value, extended version with both GP and ignore masks. */
153	#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
154	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
155	/** The short form, no CPUM backing. */
156	#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
157	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
158	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
159
160	/** Range: Functions handles everything. */
161	#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
162	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
163	/** Range: Read fixed value, read-only. */
164	#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
165	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
166	/** Range: Read fixed value, ignore writes. */
167	#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
168	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
169	/** Range: The short form, no CPUM backing. */
170	#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
171	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
172	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
173
174	/** Internal form used by the macros. */
175	#ifdef VBOX_WITH_STATISTICS
176	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
177	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
178	{ 0 }, { 0 }, { 0 }, { 0 } }
179	#else
180	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
181	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
182	#endif
183	/** @} */
184
185
186	#include "cpus/Intel_Core_i7_6700K.h"
187	#include "cpus/Intel_Core_i7_5600U.h"
188	#include "cpus/Intel_Core_i7_3960X.h"
189	#include "cpus/Intel_Core_i5_3570.h"
190	#include "cpus/Intel_Core_i7_2635QM.h"
191	#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
192	#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
193	#include "cpus/Intel_Pentium_4_3_00GHz.h"
194	#include "cpus/Intel_Atom_330_1_60GHz.h"
195	#include "cpus/Intel_80286.h"
196	#include "cpus/Intel_80186.h"
197	#include "cpus/Intel_8086.h"
198
199	#include "cpus/AMD_FX_8150_Eight_Core.h"
200	#include "cpus/AMD_Phenom_II_X6_1100T.h"
201	#include "cpus/Quad_Core_AMD_Opteron_2384.h"
202	#include "cpus/AMD_Athlon_64_X2_Dual_Core_4200.h"
203	#include "cpus/AMD_Athlon_64_3200.h"
204
205	#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
206
207
208
209	/**
210	* The database entries.
211	*
212	* 1. The first entry is special. It is the fallback for unknown
213	* processors. Thus, it better be pretty representative.
214	*
215	* 2. The first entry for a CPU vendor is likewise important as it is
216	* the default entry for that vendor.
217	*
218	* Generally we put the most recent CPUs first, since these tend to have the
219	* most complicated and backwards compatible list of MSRs.
220	*/
221	static CPUMDBENTRY const * const g_apCpumDbEntries[] =
222	{
223	#ifdef VBOX_CPUDB_Intel_Core_i7_6700K
224	&g_Entry_Intel_Core_i7_6700K,
225	#endif
226	#ifdef VBOX_CPUDB_Intel_Core_i7_5600U
227	&g_Entry_Intel_Core_i7_5600U,
228	#endif
229	#ifdef VBOX_CPUDB_Intel_Core_i5_3570
230	&g_Entry_Intel_Core_i5_3570,
231	#endif
232	#ifdef VBOX_CPUDB_Intel_Core_i7_3960X
233	&g_Entry_Intel_Core_i7_3960X,
234	#endif
235	#ifdef VBOX_CPUDB_Intel_Core_i7_2635QM
236	&g_Entry_Intel_Core_i7_2635QM,
237	#endif
238	#ifdef VBOX_CPUDB_Intel_Atom_330_1_60GHz
239	&g_Entry_Intel_Atom_330_1_60GHz,
240	#endif
241	#ifdef Intel_Pentium_M_processor_2_00GHz
242	&g_Entry_Intel_Pentium_M_processor_2_00GHz,
243	#endif
244	#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz
245	&g_Entry_Intel_Xeon_X5482_3_20GHz,
246	#endif
247	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz
248	&g_Entry_Intel_Pentium_4_3_00GHz,
249	#endif
250	#ifdef VBOX_CPUDB_Intel_80486
251	&g_Entry_Intel_80486,
252	#endif
253	#ifdef VBOX_CPUDB_Intel_80386
254	&g_Entry_Intel_80386,
255	#endif
256	#ifdef VBOX_CPUDB_Intel_80286
257	&g_Entry_Intel_80286,
258	#endif
259	#ifdef VBOX_CPUDB_Intel_80186
260	&g_Entry_Intel_80186,
261	#endif
262	#ifdef VBOX_CPUDB_Intel_8086
263	&g_Entry_Intel_8086,
264	#endif
265
266	#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core
267	&g_Entry_AMD_FX_8150_Eight_Core,
268	#endif
269	#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T
270	&g_Entry_AMD_Phenom_II_X6_1100T,
271	#endif
272	#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384
273	&g_Entry_Quad_Core_AMD_Opteron_2384,
274	#endif
275	#ifdef VBOX_CPUDB_AMD_Athlon_64_X2_Dual_Core_4200
276	&g_Entry_AMD_Athlon_64_X2_Dual_Core_4200,
277	#endif
278	#ifdef VBOX_CPUDB_AMD_Athlon_64_3200
279	&g_Entry_AMD_Athlon_64_3200,
280	#endif
281
282	#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz
283	&g_Entry_VIA_QuadCore_L4700_1_2_GHz,
284	#endif
285
286	#ifdef VBOX_CPUDB_NEC_V20
287	&g_Entry_NEC_V20,
288	#endif
289	};
290
291
292	#ifndef CPUM_DB_STANDALONE
293
294	/**
295	* Binary search used by cpumR3MsrRangesInsert and has some special properties
296	* wrt to mismatches.
297	*
298	* @returns Insert location.
299	* @param paMsrRanges The MSR ranges to search.
300	* @param cMsrRanges The number of MSR ranges.
301	* @param uMsr What to search for.
302	*/
303	static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
304	{
305	if (!cMsrRanges)
306	return 0;
307
308	uint32_t iStart = 0;
309	uint32_t iLast = cMsrRanges - 1;
310	for (;;)
311	{
312	uint32_t i = iStart + (iLast - iStart + 1) / 2;
313	if ( uMsr >= paMsrRanges[i].uFirst
314	&& uMsr <= paMsrRanges[i].uLast)
315	return i;
316	if (uMsr < paMsrRanges[i].uFirst)
317	{
318	if (i <= iStart)
319	return i;
320	iLast = i - 1;
321	}
322	else
323	{
324	if (i >= iLast)
325	{
326	if (i < cMsrRanges)
327	i++;
328	return i;
329	}
330	iStart = i + 1;
331	}
332	}
333	}
334
335
336	/**
337	* Ensures that there is space for at least @a cNewRanges in the table,
338	* reallocating the table if necessary.
339	*
340	* @returns Pointer to the MSR ranges on success, NULL on failure. On failure
341	* @a *ppaMsrRanges is freed and set to NULL.
342	* @param pVM The cross context VM structure. If NULL,
343	* use the process heap, otherwise the VM's hyper heap.
344	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
345	* @param cMsrRanges The current number of ranges.
346	* @param cNewRanges The number of ranges to be added.
347	*/
348	static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
349	{
350	uint32_t cMsrRangesAllocated;
351	if (!pVM)
352	cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
353	else
354	{
355	/*
356	* We're using the hyper heap now, but when the range array was copied over to it from
357	* the host-context heap, we only copy the exact size and not the ensured size.
358	* See @bugref{7270}.
359	*/
360	cMsrRangesAllocated = cMsrRanges;
361	}
362	if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
363	{
364	void *pvNew;
365	uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
366	if (pVM)
367	{
368	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
369	Assert(cMsrRanges == pVM->cpum.s.GuestInfo.cMsrRanges);
370
371	size_t cb = cMsrRangesAllocated * sizeof(**ppaMsrRanges);
372	size_t cbNew = cNew * sizeof(**ppaMsrRanges);
373	int rc = MMR3HyperRealloc(pVM, *ppaMsrRanges, cb, 32, MM_TAG_CPUM_MSRS, cbNew, &pvNew);
374	if (RT_FAILURE(rc))
375	{
376	*ppaMsrRanges = NULL;
377	pVM->cpum.s.GuestInfo.paMsrRangesR0 = NIL_RTR0PTR;
378	pVM->cpum.s.GuestInfo.paMsrRangesRC = NIL_RTRCPTR;
379	LogRel(("CPUM: cpumR3MsrRangesEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
380	return NULL;
381	}
382	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
383	}
384	else
385	{
386	pvNew = RTMemRealloc(ppaMsrRanges, cNew sizeof(**ppaMsrRanges));
387	if (!pvNew)
388	{
389	RTMemFree(*ppaMsrRanges);
390	*ppaMsrRanges = NULL;
391	return NULL;
392	}
393	}
394	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
395	}
396
397	if (pVM)
398	{
399	/* Update R0 and RC pointers. */
400	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
401	pVM->cpum.s.GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, *ppaMsrRanges);
402	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, *ppaMsrRanges);
403	}
404
405	return *ppaMsrRanges;
406	}
407
408
409	/**
410	* Inserts a new MSR range in into an sorted MSR range array.
411	*
412	* If the new MSR range overlaps existing ranges, the existing ones will be
413	* adjusted/removed to fit in the new one.
414	*
415	* @returns VBox status code.
416	* @retval VINF_SUCCESS
417	* @retval VERR_NO_MEMORY
418	*
419	* @param pVM The cross context VM structure. If NULL,
420	* use the process heap, otherwise the VM's hyper heap.
421	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
422	* Must be NULL if using the hyper heap.
423	* @param pcMsrRanges The variable holding number of ranges. Must be NULL
424	* if using the hyper heap.
425	* @param pNewRange The new range.
426	*/
427	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange)
428	{
429	Assert(pNewRange->uLast >= pNewRange->uFirst);
430	Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
431	Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
432
433	/*
434	* Validate and use the VM's MSR ranges array if we are using the hyper heap.
435	*/
436	if (pVM)
437	{
438	AssertReturn(!ppaMsrRanges, VERR_INVALID_PARAMETER);
439	AssertReturn(!pcMsrRanges, VERR_INVALID_PARAMETER);
440
441	ppaMsrRanges = &pVM->cpum.s.GuestInfo.paMsrRangesR3;
442	pcMsrRanges = &pVM->cpum.s.GuestInfo.cMsrRanges;
443	}
444
445	uint32_t cMsrRanges = *pcMsrRanges;
446	PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
447
448	/*
449	* Optimize the linear insertion case where we add new entries at the end.
450	*/
451	if ( cMsrRanges > 0
452	&& paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
453	{
454	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
455	if (!paMsrRanges)
456	return VERR_NO_MEMORY;
457	paMsrRanges[cMsrRanges] = *pNewRange;
458	*pcMsrRanges += 1;
459	}
460	else
461	{
462	uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
463	Assert(i == cMsrRanges \|\| pNewRange->uFirst <= paMsrRanges[i].uLast);
464	Assert(i == 0 \|\| pNewRange->uFirst > paMsrRanges[i - 1].uLast);
465
466	/*
467	* Adding an entirely new entry?
468	*/
469	if ( i >= cMsrRanges
470	\|\| pNewRange->uLast < paMsrRanges[i].uFirst)
471	{
472	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
473	if (!paMsrRanges)
474	return VERR_NO_MEMORY;
475	if (i < cMsrRanges)
476	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
477	paMsrRanges[i] = *pNewRange;
478	*pcMsrRanges += 1;
479	}
480	/*
481	* Replace existing entry?
482	*/
483	else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
484	&& pNewRange->uLast == paMsrRanges[i].uLast)
485	paMsrRanges[i] = *pNewRange;
486	/*
487	* Splitting an existing entry?
488	*/
489	else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
490	&& pNewRange->uLast < paMsrRanges[i].uLast)
491	{
492	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 2);
493	if (!paMsrRanges)
494	return VERR_NO_MEMORY;
495	if (i < cMsrRanges)
496	memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
497	paMsrRanges[i + 1] = *pNewRange;
498	paMsrRanges[i + 2] = paMsrRanges[i];
499	paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
500	paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
501	*pcMsrRanges += 2;
502	}
503	/*
504	* Complicated scenarios that can affect more than one range.
505	*
506	* The current code does not optimize memmove calls when replacing
507	* one or more existing ranges, because it's tedious to deal with and
508	* not expected to be a frequent usage scenario.
509	*/
510	else
511	{
512	/* Adjust start of first match? */
513	if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
514	&& pNewRange->uLast < paMsrRanges[i].uLast)
515	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
516	else
517	{
518	/* Adjust end of first match? */
519	if (pNewRange->uFirst > paMsrRanges[i].uFirst)
520	{
521	Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
522	paMsrRanges[i].uLast = pNewRange->uFirst - 1;
523	i++;
524	}
525	/* Replace the whole first match (lazy bird). */
526	else
527	{
528	if (i + 1 < cMsrRanges)
529	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
530	cMsrRanges = *pcMsrRanges -= 1;
531	}
532
533	/* Do the new range affect more ranges? */
534	while ( i < cMsrRanges
535	&& pNewRange->uLast >= paMsrRanges[i].uFirst)
536	{
537	if (pNewRange->uLast < paMsrRanges[i].uLast)
538	{
539	/* Adjust the start of it, then we're done. */
540	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
541	break;
542	}
543
544	/* Remove it entirely. */
545	if (i + 1 < cMsrRanges)
546	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
547	cMsrRanges = *pcMsrRanges -= 1;
548	}
549	}
550
551	/* Now, perform a normal insertion. */
552	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
553	if (!paMsrRanges)
554	return VERR_NO_MEMORY;
555	if (i < cMsrRanges)
556	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
557	paMsrRanges[i] = *pNewRange;
558	*pcMsrRanges += 1;
559	}
560	}
561
562	return VINF_SUCCESS;
563	}
564
565
566	/**
567	* Worker for cpumR3MsrApplyFudge that applies one table.
568	*
569	* @returns VBox status code.
570	* @param pVM The cross context VM structure.
571	* @param paRanges Array of MSRs to fudge.
572	* @param cRanges Number of MSRs in the array.
573	*/
574	static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
575	{
576	for (uint32_t i = 0; i < cRanges; i++)
577	if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
578	{
579	LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
580	int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
581	&paRanges[i]);
582	if (RT_FAILURE(rc))
583	return rc;
584	}
585	return VINF_SUCCESS;
586	}
587
588
589	/**
590	* Fudges the MSRs that guest are known to access in some odd cases.
591	*
592	* A typical example is a VM that has been moved between different hosts where
593	* for instance the cpu vendor differs.
594	*
595	* @returns VBox status code.
596	* @param pVM The cross context VM structure.
597	*/
598	int cpumR3MsrApplyFudge(PVM pVM)
599	{
600	/*
601	* Basic.
602	*/
603	static CPUMMSRRANGE const s_aFudgeMsrs[] =
604	{
605	MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
606	MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
607	MVO(0x00000017, "IA32_PLATFORM_ID", 0),
608	MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
609	MVI(0x0000008b, "BIOS_SIGN", 0),
610	MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
611	MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
612	MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
613	MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
614	MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
615	MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
616	MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
617	MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
618	MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
619	MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
620	MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
621	MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
622	};
623	int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
624	AssertLogRelRCReturn(rc, rc);
625
626	/*
627	* XP might mistake opterons and other newer CPUs for P4s.
628	*/
629	if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
630	{
631	static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
632	{
633	MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
634	};
635	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
636	AssertLogRelRCReturn(rc, rc);
637	}
638
639	return rc;
640	}
641
642
643	/**
644	* Do we consider @a enmConsider a better match for @a enmTarget than
645	* @a enmFound?
646	*
647	* Only called when @a enmConsider isn't exactly what we're looking for.
648	*
649	* @returns true/false.
650	* @param enmConsider The new microarch to consider.
651	* @param enmTarget The target microarch.
652	* @param enmFound The best microarch match we've found thus far.
653	*/
654	DECLINLINE(bool) cpumR3DbIsBetterMarchMatch(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
655	{
656	Assert(enmConsider != enmTarget);
657
658	/*
659	* If we've got an march match, don't bother with enmConsider.
660	*/
661	if (enmFound == enmTarget)
662	return false;
663
664	/*
665	* Found is below: Pick 'consider' if it's closer to the target or above it.
666	*/
667	if (enmFound < enmTarget)
668	return enmConsider > enmFound;
669
670	/*
671	* Found is above: Pick 'consider' if it's also above (paranoia: or equal)
672	* and but closer to the target.
673	*/
674	return enmConsider >= enmTarget && enmConsider < enmFound;
675	}
676
677
678	/**
679	* Do we consider @a enmConsider a better match for @a enmTarget than
680	* @a enmFound?
681	*
682	* Only called for intel family 06h CPUs.
683	*
684	* @returns true/false.
685	* @param enmConsider The new microarch to consider.
686	* @param enmTarget The target microarch.
687	* @param enmFound The best microarch match we've found thus far.
688	*/
689	static bool cpumR3DbIsBetterIntelFam06Match(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
690	{
691	/* Check intel family 06h claims. */
692	AssertReturn(enmConsider >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmConsider <= kCpumMicroarch_Intel_P6_Core_Atom_End,
693	false);
694	AssertReturn(enmTarget >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmTarget <= kCpumMicroarch_Intel_P6_Core_Atom_End,
695	false);
696
697	/* Put matches out of the way. */
698	if (enmConsider == enmTarget)
699	return true;
700	if (enmFound == enmTarget)
701	return false;
702
703	/* If found isn't a family 06h march, whatever we're considering must be a better choice. */
704	if ( enmFound < kCpumMicroarch_Intel_P6_Core_Atom_First
705	\|\| enmFound > kCpumMicroarch_Intel_P6_Core_Atom_End)
706	return true;
707
708	/*
709	* The family 06h stuff is split into three categories:
710	* - Common P6 heritage
711	* - Core
712	* - Atom
713	*
714	* Determin which of the three arguments are Atom marchs, because that's
715	* all we need to make the right choice.
716	*/
717	bool const fConsiderAtom = enmConsider >= kCpumMicroarch_Intel_Atom_First;
718	bool const fTargetAtom = enmTarget >= kCpumMicroarch_Intel_Atom_First;
719	bool const fFoundAtom = enmFound >= kCpumMicroarch_Intel_Atom_First;
720
721	/*
722	* Want atom:
723	*/
724	if (fTargetAtom)
725	{
726	/* Pick the atom if we've got one of each.*/
727	if (fConsiderAtom != fFoundAtom)
728	return fConsiderAtom;
729	/* If we haven't got any atoms under consideration, pick a P6 or the earlier core.
730	Note! Not entirely sure Dothan is the best choice, but it'll do for now. */
731	if (!fConsiderAtom)
732	{
733	if (enmConsider > enmFound)
734	return enmConsider <= kCpumMicroarch_Intel_P6_M_Dothan;
735	return enmFound > kCpumMicroarch_Intel_P6_M_Dothan;
736	}
737	/* else: same category, default comparison rules. */
738	Assert(fConsiderAtom && fFoundAtom);
739	}
740	/*
741	* Want non-atom:
742	*/
743	/* Pick the non-atom if we've got one of each. */
744	else if (fConsiderAtom != fFoundAtom)
745	return fFoundAtom;
746	/* If we've only got atoms under consideration, pick the older one just to pick something. */
747	else if (fConsiderAtom)
748	return enmConsider < enmFound;
749	else
750	Assert(!fConsiderAtom && !fFoundAtom);
751
752	/*
753	* Same basic category. Do same compare as caller.
754	*/
755	return cpumR3DbIsBetterMarchMatch(enmConsider, enmTarget, enmFound);
756	}
757
758
759	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
760	{
761	CPUMDBENTRY const *pEntry = NULL;
762	int rc;
763
764	if (!strcmp(pszName, "host"))
765	{
766	/*
767	* Create a CPU database entry for the host CPU. This means getting
768	* the CPUID bits from the real CPU and grabbing the closest matching
769	* database entry for MSRs.
770	*/
771	rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
772	if (RT_FAILURE(rc))
773	return rc;
774	rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
775	if (RT_FAILURE(rc))
776	return rc;
777
778	/* Lookup database entry for MSRs. */
779	CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
780	pInfo->paCpuIdLeavesR3[0].uEbx,
781	pInfo->paCpuIdLeavesR3[0].uEcx,
782	pInfo->paCpuIdLeavesR3[0].uEdx);
783	uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
784	uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
785	uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
786	uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
787	CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
788
789	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
790	{
791	CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
792	if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
793	{
794	/* Match against Family, Microarch, model and stepping. Except
795	for family, always match the closer with preference given to
796	the later/older ones. */
797	if (pCur->uFamily == uFamily)
798	{
799	if (pCur->enmMicroarch == enmMicroarch)
800	{
801	if (pCur->uModel == uModel)
802	{
803	if (pCur->uStepping == uStepping)
804	{
805	/* Perfect match. */
806	pEntry = pCur;
807	break;
808	}
809
810	if ( !pEntry
811	\|\| pEntry->uModel != uModel
812	\|\| pEntry->enmMicroarch != enmMicroarch
813	\|\| pEntry->uFamily != uFamily)
814	pEntry = pCur;
815	else if ( pCur->uStepping >= uStepping
816	? pCur->uStepping < pEntry->uStepping \|\| pEntry->uStepping < uStepping
817	: pCur->uStepping > pEntry->uStepping)
818	pEntry = pCur;
819	}
820	else if ( !pEntry
821	\|\| pEntry->enmMicroarch != enmMicroarch
822	\|\| pEntry->uFamily != uFamily)
823	pEntry = pCur;
824	else if ( pCur->uModel >= uModel
825	? pCur->uModel < pEntry->uModel \|\| pEntry->uModel < uModel
826	: pCur->uModel > pEntry->uModel)
827	pEntry = pCur;
828	}
829	else if ( !pEntry
830	\|\| pEntry->uFamily != uFamily)
831	pEntry = pCur;
832	/* Special march matching rules applies to intel family 06h. */
833	else if ( enmVendor == CPUMCPUVENDOR_INTEL
834	&& uFamily == 6
835	? cpumR3DbIsBetterIntelFam06Match(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch)
836	: cpumR3DbIsBetterMarchMatch(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch))
837	pEntry = pCur;
838	}
839	/* We don't do closeness matching on family, we use the first
840	entry for the CPU vendor instead. (P4 workaround.) */
841	else if (!pEntry)
842	pEntry = pCur;
843	}
844	}
845
846	if (pEntry)
847	LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
848	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
849	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
850	pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
851	else
852	{
853	pEntry = g_apCpumDbEntries[0];
854	LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'\n",
855	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
856	pEntry->pszName));
857	}
858	}
859	else
860	{
861	/*
862	* We're supposed to be emulating a specific CPU that is included in
863	* our CPU database. The CPUID tables needs to be copied onto the
864	* heap so the caller can modify them and so they can be freed like
865	* in the host case above.
866	*/
867	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
868	if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
869	{
870	pEntry = g_apCpumDbEntries[i];
871	break;
872	}
873	if (!pEntry)
874	{
875	LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
876	return VERR_CPUM_DB_CPU_NOT_FOUND;
877	}
878
879	pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
880	if (pEntry->cCpuIdLeaves)
881	{
882	/* Must allocate a multiple of 16 here, matching cpumR3CpuIdEnsureSpace. */
883	size_t cbExtra = sizeof(pEntry->paCpuIdLeaves[0]) * (RT_ALIGN(pEntry->cCpuIdLeaves, 16) - pEntry->cCpuIdLeaves);
884	pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDupEx(pEntry->paCpuIdLeaves,
885	sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves,
886	cbExtra);
887	if (!pInfo->paCpuIdLeavesR3)
888	return VERR_NO_MEMORY;
889	}
890	else
891	pInfo->paCpuIdLeavesR3 = NULL;
892
893	pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
894	pInfo->DefCpuId = pEntry->DefUnknownCpuId;
895
896	LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
897	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
898	pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
899	}
900
901	pInfo->fMsrMask = pEntry->fMsrMask;
902	pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
903	pInfo->uPadding = 0;
904	pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
905	pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
906	pInfo->paMsrRangesR0 = NIL_RTR0PTR;
907	pInfo->paCpuIdLeavesRC = NIL_RTRCPTR;
908	pInfo->paMsrRangesRC = NIL_RTRCPTR;
909
910	/*
911	* Copy the MSR range.
912	*/
913	uint32_t cMsrs = 0;
914	PCPUMMSRRANGE paMsrs = NULL;
915
916	PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
917	uint32_t cLeft = pEntry->cMsrRanges;
918	while (cLeft-- > 0)
919	{
920	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &paMsrs, &cMsrs, pCurMsr);
921	if (RT_FAILURE(rc))
922	{
923	Assert(!paMsrs); /* The above function frees this. */
924	RTMemFree(pInfo->paCpuIdLeavesR3);
925	pInfo->paCpuIdLeavesR3 = NULL;
926	return rc;
927	}
928	pCurMsr++;
929	}
930
931	pInfo->paMsrRangesR3 = paMsrs;
932	pInfo->cMsrRanges = cMsrs;
933	return VINF_SUCCESS;
934	}
935
936
937	/**
938	* Insert an MSR range into the VM.
939	*
940	* If the new MSR range overlaps existing ranges, the existing ones will be
941	* adjusted/removed to fit in the new one.
942	*
943	* @returns VBox status code.
944	* @param pVM The cross context VM structure.
945	* @param pNewRange Pointer to the MSR range being inserted.
946	*/
947	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange)
948	{
949	AssertReturn(pVM, VERR_INVALID_PARAMETER);
950	AssertReturn(pNewRange, VERR_INVALID_PARAMETER);
951
952	return cpumR3MsrRangesInsert(pVM, NULL /* ppaMsrRanges /, NULL / pcMsrRanges */, pNewRange);
953	}
954
955
956	/**
957	* Register statistics for the MSRs.
958	*
959	* This must not be called before the MSRs have been finalized and moved to the
960	* hyper heap.
961	*
962	* @returns VBox status code.
963	* @param pVM The cross context VM structure.
964	*/
965	int cpumR3MsrRegStats(PVM pVM)
966	{
967	/*
968	* Global statistics.
969	*/
970	PCPUM pCpum = &pVM->cpum.s;
971	STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
972	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
973	STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
974	STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
975	STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
976	STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
977	STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
978	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
979	STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
980	STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
981	STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
982	STAMUNIT_OCCURENCES, "Writing of ignored bits.");
983	STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
984	STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
985
986
987	# ifdef VBOX_WITH_STATISTICS
988	/*
989	* Per range.
990	*/
991	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
992	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
993	for (uint32_t i = 0; i < cRanges; i++)
994	{
995	char szName[160];
996	ssize_t cchName;
997
998	if (paRanges[i].uFirst == paRanges[i].uLast)
999	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
1000	paRanges[i].uFirst, paRanges[i].szName);
1001	else
1002	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
1003	paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
1004
1005	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
1006	STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
1007
1008	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
1009	STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
1010
1011	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
1012	STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
1013
1014	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
1015	STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
1016	}
1017	# endif /* VBOX_WITH_STATISTICS */
1018
1019	return VINF_SUCCESS;
1020	}
1021
1022	#endif /* !CPUM_DB_STANDALONE */
1023

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 60601

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