CPUMR3Db.cpp@ 69900

Last change on this file since 69900 was 69900, checked in by vboxsync, 7 years ago
CPUDb: Added T2600 (Yonah), T7600 (Merom) CPU profiles.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 42.4 KB

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1	/* $Id: CPUMR3Db.cpp 69900 2017-12-01 15:32:11Z vboxsync $ */
2	/** @file
3	* CPUM - CPU database part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/mm.h>
27
28	#include <VBox/err.h>
29	#include <iprt/asm-amd64-x86.h>
30	#include <iprt/mem.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Structures and Typedefs *
36	*********************************************************************************************************************************/
37	typedef struct CPUMDBENTRY
38	{
39	/** The CPU name. */
40	const char *pszName;
41	/** The full CPU name. */
42	const char *pszFullName;
43	/** The CPU vendor (CPUMCPUVENDOR). */
44	uint8_t enmVendor;
45	/** The CPU family. */
46	uint8_t uFamily;
47	/** The CPU model. */
48	uint8_t uModel;
49	/** The CPU stepping. */
50	uint8_t uStepping;
51	/** The microarchitecture. */
52	CPUMMICROARCH enmMicroarch;
53	/** Scalable bus frequency used for reporting other frequencies. */
54	uint64_t uScalableBusFreq;
55	/** Flags - CPUDB_F_XXX. */
56	uint32_t fFlags;
57	/** The maximum physical address with of the CPU. This should correspond to
58	* the value in CPUID leaf 0x80000008 when present. */
59	uint8_t cMaxPhysAddrWidth;
60	/** The MXCSR mask. */
61	uint32_t fMxCsrMask;
62	/** Pointer to an array of CPUID leaves. */
63	PCCPUMCPUIDLEAF paCpuIdLeaves;
64	/** The number of CPUID leaves in the array paCpuIdLeaves points to. */
65	uint32_t cCpuIdLeaves;
66	/** The method used to deal with unknown CPUID leaves. */
67	CPUMUNKNOWNCPUID enmUnknownCpuId;
68	/** The default unknown CPUID value. */
69	CPUMCPUID DefUnknownCpuId;
70
71	/** MSR mask. Several microarchitectures ignore the higher bits of ECX in
72	* the RDMSR and WRMSR instructions. */
73	uint32_t fMsrMask;
74
75	/** The number of ranges in the table pointed to b paMsrRanges. */
76	uint32_t cMsrRanges;
77	/** MSR ranges for this CPU. */
78	PCCPUMMSRRANGE paMsrRanges;
79	} CPUMDBENTRY;
80
81
82	/*********************************************************************************************************************************
83	* Defined Constants And Macros *
84	*********************************************************************************************************************************/
85	/** @name CPUDB_F_XXX - CPUDBENTRY::fFlags
86	* @{ */
87	/** Should execute all in IEM.
88	* @todo Implement this - currently done in Main... */
89	#define CPUDB_F_EXECUTE_ALL_IN_IEM RT_BIT_32(0)
90	/** @} */
91
92
93	/** @def NULL_ALONE
94	* For eliminating an unnecessary data dependency in standalone builds (for
95	* VBoxSVC). */
96	/** @def ZERO_ALONE
97	* For eliminating an unnecessary data size dependency in standalone builds (for
98	* VBoxSVC). */
99	#ifndef CPUM_DB_STANDALONE
100	# define NULL_ALONE(a_aTable) a_aTable
101	# define ZERO_ALONE(a_cTable) a_cTable
102	#else
103	# define NULL_ALONE(a_aTable) NULL
104	# define ZERO_ALONE(a_cTable) 0
105	#endif
106
107
108	/** @name Short macros for the MSR range entries.
109	*
110	* These are rather cryptic, but this is to reduce the attack on the right
111	* margin.
112	*
113	* @{ */
114	/** Alias one MSR onto another (a_uTarget). */
115	#define MAL(a_uMsr, a_szName, a_uTarget) \
116	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
117	/** Functions handles everything. */
118	#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
119	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
120	/** Functions handles everything, with GP mask. */
121	#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
122	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
123	/** Function handlers, read-only. */
124	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
125	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
126	/** Function handlers, ignore all writes. */
127	#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
128	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
129	/** Function handlers, with value. */
130	#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
131	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
132	/** Function handlers, with write ignore mask. */
133	#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
134	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
135	/** Function handlers, extended version. */
136	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
137	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
138	/** Function handlers, with CPUMCPU storage variable. */
139	#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
140	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
141	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
142	/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
143	#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
144	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
145	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
146	/** Read-only fixed value. */
147	#define MVO(a_uMsr, a_szName, a_uValue) \
148	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
149	/** Read-only fixed value, ignores all writes. */
150	#define MVI(a_uMsr, a_szName, a_uValue) \
151	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
152	/** Read fixed value, ignore writes outside GP mask. */
153	#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
154	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
155	/** Read fixed value, extended version with both GP and ignore masks. */
156	#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
157	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
158	/** The short form, no CPUM backing. */
159	#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
160	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
161	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
162
163	/** Range: Functions handles everything. */
164	#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
165	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
166	/** Range: Read fixed value, read-only. */
167	#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
168	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
169	/** Range: Read fixed value, ignore writes. */
170	#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
171	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
172	/** Range: The short form, no CPUM backing. */
173	#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
174	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
175	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
176
177	/** Internal form used by the macros. */
178	#ifdef VBOX_WITH_STATISTICS
179	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
180	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
181	{ 0 }, { 0 }, { 0 }, { 0 } }
182	#else
183	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
184	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
185	#endif
186	/** @} */
187
188	#ifndef CPUM_DB_STANDALONE
189
190	#include "cpus/Intel_Core_i7_6700K.h"
191	#include "cpus/Intel_Core_i7_5600U.h"
192	#include "cpus/Intel_Core_i7_3960X.h"
193	#include "cpus/Intel_Core_i5_3570.h"
194	#include "cpus/Intel_Core_i7_2635QM.h"
195	#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
196	#include "cpus/Intel_Core2_X6800_2_93GHz.h"
197	#include "cpus/Intel_Core2_T7600_2_33GHz.h"
198	#include "cpus/Intel_Core_Duo_T2600_2_16GHz.h"
199	#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
200	#include "cpus/Intel_Pentium_4_3_00GHz.h"
201	#include "cpus/Intel_Pentium_N3530_2_16GHz.h"
202	#include "cpus/Intel_Atom_330_1_60GHz.h"
203	#include "cpus/Intel_80386.h"
204	#include "cpus/Intel_80286.h"
205	#include "cpus/Intel_80186.h"
206	#include "cpus/Intel_8086.h"
207
208	#include "cpus/AMD_FX_8150_Eight_Core.h"
209	#include "cpus/AMD_Phenom_II_X6_1100T.h"
210	#include "cpus/Quad_Core_AMD_Opteron_2384.h"
211	#include "cpus/AMD_Athlon_64_X2_Dual_Core_4200.h"
212	#include "cpus/AMD_Athlon_64_3200.h"
213
214	#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
215
216
217
218	/**
219	* The database entries.
220	*
221	* 1. The first entry is special. It is the fallback for unknown
222	* processors. Thus, it better be pretty representative.
223	*
224	* 2. The first entry for a CPU vendor is likewise important as it is
225	* the default entry for that vendor.
226	*
227	* Generally we put the most recent CPUs first, since these tend to have the
228	* most complicated and backwards compatible list of MSRs.
229	*/
230	static CPUMDBENTRY const * const g_apCpumDbEntries[] =
231	{
232	#ifdef VBOX_CPUDB_Intel_Core_i7_6700K
233	&g_Entry_Intel_Core_i7_6700K,
234	#endif
235	#ifdef VBOX_CPUDB_Intel_Core_i7_5600U
236	&g_Entry_Intel_Core_i7_5600U,
237	#endif
238	#ifdef VBOX_CPUDB_Intel_Core_i5_3570
239	&g_Entry_Intel_Core_i5_3570,
240	#endif
241	#ifdef VBOX_CPUDB_Intel_Core_i7_3960X
242	&g_Entry_Intel_Core_i7_3960X,
243	#endif
244	#ifdef VBOX_CPUDB_Intel_Core_i7_2635QM
245	&g_Entry_Intel_Core_i7_2635QM,
246	#endif
247	#ifdef VBOX_CPUDB_Intel_Pentium_N3530_2_16GHz
248	&g_Entry_Intel_Pentium_N3530_2_16GHz,
249	#endif
250	#ifdef VBOX_CPUDB_Intel_Atom_330_1_60GHz
251	&g_Entry_Intel_Atom_330_1_60GHz,
252	#endif
253	#ifdef VBOX_CPUDB_Intel_Pentium_M_processor_2_00GHz
254	&g_Entry_Intel_Pentium_M_processor_2_00GHz,
255	#endif
256	#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz
257	&g_Entry_Intel_Xeon_X5482_3_20GHz,
258	#endif
259	#ifdef VBOX_CPUDB_Intel_Core2_X6800_2_93GHz
260	&g_Entry_Intel_Core2_X6800_2_93GHz,
261	#endif
262	#ifdef VBOX_CPUDB_Intel_Core2_T7600_2_33GHz
263	&g_Entry_Intel_Core2_T7600_2_33GHz,
264	#endif
265	#ifdef VBOX_CPUDB_Intel_Core_Duo_T2600_2_16GHz
266	&g_Entry_Intel_Core_Duo_T2600_2_16GHz,
267	#endif
268	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz
269	&g_Entry_Intel_Pentium_4_3_00GHz,
270	#endif
271	#ifdef VBOX_CPUDB_Intel_80486
272	&g_Entry_Intel_80486,
273	#endif
274	#ifdef VBOX_CPUDB_Intel_80386
275	&g_Entry_Intel_80386,
276	#endif
277	#ifdef VBOX_CPUDB_Intel_80286
278	&g_Entry_Intel_80286,
279	#endif
280	#ifdef VBOX_CPUDB_Intel_80186
281	&g_Entry_Intel_80186,
282	#endif
283	#ifdef VBOX_CPUDB_Intel_8086
284	&g_Entry_Intel_8086,
285	#endif
286
287	#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core
288	&g_Entry_AMD_FX_8150_Eight_Core,
289	#endif
290	#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T
291	&g_Entry_AMD_Phenom_II_X6_1100T,
292	#endif
293	#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384
294	&g_Entry_Quad_Core_AMD_Opteron_2384,
295	#endif
296	#ifdef VBOX_CPUDB_AMD_Athlon_64_X2_Dual_Core_4200
297	&g_Entry_AMD_Athlon_64_X2_Dual_Core_4200,
298	#endif
299	#ifdef VBOX_CPUDB_AMD_Athlon_64_3200
300	&g_Entry_AMD_Athlon_64_3200,
301	#endif
302
303	#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz
304	&g_Entry_VIA_QuadCore_L4700_1_2_GHz,
305	#endif
306
307	#ifdef VBOX_CPUDB_NEC_V20
308	&g_Entry_NEC_V20,
309	#endif
310	};
311
312
313
314	/**
315	* Binary search used by cpumR3MsrRangesInsert and has some special properties
316	* wrt to mismatches.
317	*
318	* @returns Insert location.
319	* @param paMsrRanges The MSR ranges to search.
320	* @param cMsrRanges The number of MSR ranges.
321	* @param uMsr What to search for.
322	*/
323	static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
324	{
325	if (!cMsrRanges)
326	return 0;
327
328	uint32_t iStart = 0;
329	uint32_t iLast = cMsrRanges - 1;
330	for (;;)
331	{
332	uint32_t i = iStart + (iLast - iStart + 1) / 2;
333	if ( uMsr >= paMsrRanges[i].uFirst
334	&& uMsr <= paMsrRanges[i].uLast)
335	return i;
336	if (uMsr < paMsrRanges[i].uFirst)
337	{
338	if (i <= iStart)
339	return i;
340	iLast = i - 1;
341	}
342	else
343	{
344	if (i >= iLast)
345	{
346	if (i < cMsrRanges)
347	i++;
348	return i;
349	}
350	iStart = i + 1;
351	}
352	}
353	}
354
355
356	/**
357	* Ensures that there is space for at least @a cNewRanges in the table,
358	* reallocating the table if necessary.
359	*
360	* @returns Pointer to the MSR ranges on success, NULL on failure. On failure
361	* @a *ppaMsrRanges is freed and set to NULL.
362	* @param pVM The cross context VM structure. If NULL,
363	* use the process heap, otherwise the VM's hyper heap.
364	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
365	* @param cMsrRanges The current number of ranges.
366	* @param cNewRanges The number of ranges to be added.
367	*/
368	static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
369	{
370	uint32_t cMsrRangesAllocated;
371	if (!pVM)
372	cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
373	else
374	{
375	/*
376	* We're using the hyper heap now, but when the range array was copied over to it from
377	* the host-context heap, we only copy the exact size and not the ensured size.
378	* See @bugref{7270}.
379	*/
380	cMsrRangesAllocated = cMsrRanges;
381	}
382	if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
383	{
384	void *pvNew;
385	uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
386	if (pVM)
387	{
388	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
389	Assert(cMsrRanges == pVM->cpum.s.GuestInfo.cMsrRanges);
390
391	size_t cb = cMsrRangesAllocated * sizeof(**ppaMsrRanges);
392	size_t cbNew = cNew * sizeof(**ppaMsrRanges);
393	int rc = MMR3HyperRealloc(pVM, *ppaMsrRanges, cb, 32, MM_TAG_CPUM_MSRS, cbNew, &pvNew);
394	if (RT_FAILURE(rc))
395	{
396	*ppaMsrRanges = NULL;
397	pVM->cpum.s.GuestInfo.paMsrRangesR0 = NIL_RTR0PTR;
398	pVM->cpum.s.GuestInfo.paMsrRangesRC = NIL_RTRCPTR;
399	LogRel(("CPUM: cpumR3MsrRangesEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
400	return NULL;
401	}
402	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
403	}
404	else
405	{
406	pvNew = RTMemRealloc(ppaMsrRanges, cNew sizeof(**ppaMsrRanges));
407	if (!pvNew)
408	{
409	RTMemFree(*ppaMsrRanges);
410	*ppaMsrRanges = NULL;
411	return NULL;
412	}
413	}
414	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
415	}
416
417	if (pVM)
418	{
419	/* Update R0 and RC pointers. */
420	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
421	pVM->cpum.s.GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, *ppaMsrRanges);
422	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, *ppaMsrRanges);
423	}
424
425	return *ppaMsrRanges;
426	}
427
428
429	/**
430	* Inserts a new MSR range in into an sorted MSR range array.
431	*
432	* If the new MSR range overlaps existing ranges, the existing ones will be
433	* adjusted/removed to fit in the new one.
434	*
435	* @returns VBox status code.
436	* @retval VINF_SUCCESS
437	* @retval VERR_NO_MEMORY
438	*
439	* @param pVM The cross context VM structure. If NULL,
440	* use the process heap, otherwise the VM's hyper heap.
441	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
442	* Must be NULL if using the hyper heap.
443	* @param pcMsrRanges The variable holding number of ranges. Must be NULL
444	* if using the hyper heap.
445	* @param pNewRange The new range.
446	*/
447	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange)
448	{
449	Assert(pNewRange->uLast >= pNewRange->uFirst);
450	Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
451	Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
452
453	/*
454	* Validate and use the VM's MSR ranges array if we are using the hyper heap.
455	*/
456	if (pVM)
457	{
458	AssertReturn(!ppaMsrRanges, VERR_INVALID_PARAMETER);
459	AssertReturn(!pcMsrRanges, VERR_INVALID_PARAMETER);
460
461	ppaMsrRanges = &pVM->cpum.s.GuestInfo.paMsrRangesR3;
462	pcMsrRanges = &pVM->cpum.s.GuestInfo.cMsrRanges;
463	}
464	else
465	{
466	AssertReturn(ppaMsrRanges, VERR_INVALID_POINTER);
467	AssertReturn(pcMsrRanges, VERR_INVALID_POINTER);
468	}
469
470	uint32_t cMsrRanges = *pcMsrRanges;
471	PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
472
473	/*
474	* Optimize the linear insertion case where we add new entries at the end.
475	*/
476	if ( cMsrRanges > 0
477	&& paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
478	{
479	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
480	if (!paMsrRanges)
481	return VERR_NO_MEMORY;
482	paMsrRanges[cMsrRanges] = *pNewRange;
483	*pcMsrRanges += 1;
484	}
485	else
486	{
487	uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
488	Assert(i == cMsrRanges \|\| pNewRange->uFirst <= paMsrRanges[i].uLast);
489	Assert(i == 0 \|\| pNewRange->uFirst > paMsrRanges[i - 1].uLast);
490
491	/*
492	* Adding an entirely new entry?
493	*/
494	if ( i >= cMsrRanges
495	\|\| pNewRange->uLast < paMsrRanges[i].uFirst)
496	{
497	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
498	if (!paMsrRanges)
499	return VERR_NO_MEMORY;
500	if (i < cMsrRanges)
501	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
502	paMsrRanges[i] = *pNewRange;
503	*pcMsrRanges += 1;
504	}
505	/*
506	* Replace existing entry?
507	*/
508	else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
509	&& pNewRange->uLast == paMsrRanges[i].uLast)
510	paMsrRanges[i] = *pNewRange;
511	/*
512	* Splitting an existing entry?
513	*/
514	else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
515	&& pNewRange->uLast < paMsrRanges[i].uLast)
516	{
517	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 2);
518	if (!paMsrRanges)
519	return VERR_NO_MEMORY;
520	if (i < cMsrRanges)
521	memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
522	paMsrRanges[i + 1] = *pNewRange;
523	paMsrRanges[i + 2] = paMsrRanges[i];
524	paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
525	paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
526	*pcMsrRanges += 2;
527	}
528	/*
529	* Complicated scenarios that can affect more than one range.
530	*
531	* The current code does not optimize memmove calls when replacing
532	* one or more existing ranges, because it's tedious to deal with and
533	* not expected to be a frequent usage scenario.
534	*/
535	else
536	{
537	/* Adjust start of first match? */
538	if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
539	&& pNewRange->uLast < paMsrRanges[i].uLast)
540	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
541	else
542	{
543	/* Adjust end of first match? */
544	if (pNewRange->uFirst > paMsrRanges[i].uFirst)
545	{
546	Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
547	paMsrRanges[i].uLast = pNewRange->uFirst - 1;
548	i++;
549	}
550	/* Replace the whole first match (lazy bird). */
551	else
552	{
553	if (i + 1 < cMsrRanges)
554	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
555	cMsrRanges = *pcMsrRanges -= 1;
556	}
557
558	/* Do the new range affect more ranges? */
559	while ( i < cMsrRanges
560	&& pNewRange->uLast >= paMsrRanges[i].uFirst)
561	{
562	if (pNewRange->uLast < paMsrRanges[i].uLast)
563	{
564	/* Adjust the start of it, then we're done. */
565	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
566	break;
567	}
568
569	/* Remove it entirely. */
570	if (i + 1 < cMsrRanges)
571	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
572	cMsrRanges = *pcMsrRanges -= 1;
573	}
574	}
575
576	/* Now, perform a normal insertion. */
577	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
578	if (!paMsrRanges)
579	return VERR_NO_MEMORY;
580	if (i < cMsrRanges)
581	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
582	paMsrRanges[i] = *pNewRange;
583	*pcMsrRanges += 1;
584	}
585	}
586
587	return VINF_SUCCESS;
588	}
589
590
591	/**
592	* Worker for cpumR3MsrApplyFudge that applies one table.
593	*
594	* @returns VBox status code.
595	* @param pVM The cross context VM structure.
596	* @param paRanges Array of MSRs to fudge.
597	* @param cRanges Number of MSRs in the array.
598	*/
599	static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
600	{
601	for (uint32_t i = 0; i < cRanges; i++)
602	if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
603	{
604	LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
605	int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
606	&paRanges[i]);
607	if (RT_FAILURE(rc))
608	return rc;
609	}
610	return VINF_SUCCESS;
611	}
612
613
614	/**
615	* Fudges the MSRs that guest are known to access in some odd cases.
616	*
617	* A typical example is a VM that has been moved between different hosts where
618	* for instance the cpu vendor differs.
619	*
620	* Another example is older CPU profiles (e.g. Atom Bonnet) for newer CPUs (e.g.
621	* Atom Silvermont), where features reported thru CPUID aren't present in the
622	* MSRs (e.g. AMD64_TSC_AUX).
623	*
624	*
625	* @returns VBox status code.
626	* @param pVM The cross context VM structure.
627	*/
628	int cpumR3MsrApplyFudge(PVM pVM)
629	{
630	/*
631	* Basic.
632	*/
633	static CPUMMSRRANGE const s_aFudgeMsrs[] =
634	{
635	MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
636	MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
637	MVO(0x00000017, "IA32_PLATFORM_ID", 0),
638	MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
639	MVI(0x0000008b, "BIOS_SIGN", 0),
640	MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
641	MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
642	MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
643	MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
644	MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
645	MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
646	MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
647	MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
648	MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
649	MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
650	MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
651	MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
652	};
653	int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
654	AssertLogRelRCReturn(rc, rc);
655
656	/*
657	* XP might mistake opterons and other newer CPUs for P4s.
658	*/
659	if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
660	{
661	static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
662	{
663	MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
664	};
665	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
666	AssertLogRelRCReturn(rc, rc);
667	}
668
669	if (pVM->cpum.s.GuestFeatures.fRdTscP)
670	{
671	static CPUMMSRRANGE const s_aRdTscPFudgeMsrs[] =
672	{
673	MFX(0xc0000103, "AMD64_TSC_AUX", Amd64TscAux, Amd64TscAux, 0, 0, ~(uint64_t)UINT32_MAX),
674	};
675	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aRdTscPFudgeMsrs[0], RT_ELEMENTS(s_aRdTscPFudgeMsrs));
676	AssertLogRelRCReturn(rc, rc);
677	}
678
679	return rc;
680	}
681
682
683	/**
684	* Do we consider @a enmConsider a better match for @a enmTarget than
685	* @a enmFound?
686	*
687	* Only called when @a enmConsider isn't exactly what we're looking for.
688	*
689	* @returns true/false.
690	* @param enmConsider The new microarch to consider.
691	* @param enmTarget The target microarch.
692	* @param enmFound The best microarch match we've found thus far.
693	*/
694	DECLINLINE(bool) cpumR3DbIsBetterMarchMatch(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
695	{
696	Assert(enmConsider != enmTarget);
697
698	/*
699	* If we've got an march match, don't bother with enmConsider.
700	*/
701	if (enmFound == enmTarget)
702	return false;
703
704	/*
705	* Found is below: Pick 'consider' if it's closer to the target or above it.
706	*/
707	if (enmFound < enmTarget)
708	return enmConsider > enmFound;
709
710	/*
711	* Found is above: Pick 'consider' if it's also above (paranoia: or equal)
712	* and but closer to the target.
713	*/
714	return enmConsider >= enmTarget && enmConsider < enmFound;
715	}
716
717
718	/**
719	* Do we consider @a enmConsider a better match for @a enmTarget than
720	* @a enmFound?
721	*
722	* Only called for intel family 06h CPUs.
723	*
724	* @returns true/false.
725	* @param enmConsider The new microarch to consider.
726	* @param enmTarget The target microarch.
727	* @param enmFound The best microarch match we've found thus far.
728	*/
729	static bool cpumR3DbIsBetterIntelFam06Match(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
730	{
731	/* Check intel family 06h claims. */
732	AssertReturn(enmConsider >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmConsider <= kCpumMicroarch_Intel_P6_Core_Atom_End,
733	false);
734	AssertReturn(enmTarget >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmTarget <= kCpumMicroarch_Intel_P6_Core_Atom_End,
735	false);
736
737	/* Put matches out of the way. */
738	if (enmConsider == enmTarget)
739	return true;
740	if (enmFound == enmTarget)
741	return false;
742
743	/* If found isn't a family 06h march, whatever we're considering must be a better choice. */
744	if ( enmFound < kCpumMicroarch_Intel_P6_Core_Atom_First
745	\|\| enmFound > kCpumMicroarch_Intel_P6_Core_Atom_End)
746	return true;
747
748	/*
749	* The family 06h stuff is split into three categories:
750	* - Common P6 heritage
751	* - Core
752	* - Atom
753	*
754	* Determin which of the three arguments are Atom marchs, because that's
755	* all we need to make the right choice.
756	*/
757	bool const fConsiderAtom = enmConsider >= kCpumMicroarch_Intel_Atom_First;
758	bool const fTargetAtom = enmTarget >= kCpumMicroarch_Intel_Atom_First;
759	bool const fFoundAtom = enmFound >= kCpumMicroarch_Intel_Atom_First;
760
761	/*
762	* Want atom:
763	*/
764	if (fTargetAtom)
765	{
766	/* Pick the atom if we've got one of each.*/
767	if (fConsiderAtom != fFoundAtom)
768	return fConsiderAtom;
769	/* If we haven't got any atoms under consideration, pick a P6 or the earlier core.
770	Note! Not entirely sure Dothan is the best choice, but it'll do for now. */
771	if (!fConsiderAtom)
772	{
773	if (enmConsider > enmFound)
774	return enmConsider <= kCpumMicroarch_Intel_P6_M_Dothan;
775	return enmFound > kCpumMicroarch_Intel_P6_M_Dothan;
776	}
777	/* else: same category, default comparison rules. */
778	Assert(fConsiderAtom && fFoundAtom);
779	}
780	/*
781	* Want non-atom:
782	*/
783	/* Pick the non-atom if we've got one of each. */
784	else if (fConsiderAtom != fFoundAtom)
785	return fFoundAtom;
786	/* If we've only got atoms under consideration, pick the older one just to pick something. */
787	else if (fConsiderAtom)
788	return enmConsider < enmFound;
789	else
790	Assert(!fConsiderAtom && !fFoundAtom);
791
792	/*
793	* Same basic category. Do same compare as caller.
794	*/
795	return cpumR3DbIsBetterMarchMatch(enmConsider, enmTarget, enmFound);
796	}
797
798
799	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
800	{
801	CPUMDBENTRY const *pEntry = NULL;
802	int rc;
803
804	if (!strcmp(pszName, "host"))
805	{
806	/*
807	* Create a CPU database entry for the host CPU. This means getting
808	* the CPUID bits from the real CPU and grabbing the closest matching
809	* database entry for MSRs.
810	*/
811	rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
812	if (RT_FAILURE(rc))
813	return rc;
814	rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
815	if (RT_FAILURE(rc))
816	return rc;
817	pInfo->fMxCsrMask = CPUMR3DeterminHostMxCsrMask();
818
819	/* Lookup database entry for MSRs. */
820	CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
821	pInfo->paCpuIdLeavesR3[0].uEbx,
822	pInfo->paCpuIdLeavesR3[0].uEcx,
823	pInfo->paCpuIdLeavesR3[0].uEdx);
824	uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
825	uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
826	uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
827	uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
828	CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
829
830	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
831	{
832	CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
833	if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
834	{
835	/* Match against Family, Microarch, model and stepping. Except
836	for family, always match the closer with preference given to
837	the later/older ones. */
838	if (pCur->uFamily == uFamily)
839	{
840	if (pCur->enmMicroarch == enmMicroarch)
841	{
842	if (pCur->uModel == uModel)
843	{
844	if (pCur->uStepping == uStepping)
845	{
846	/* Perfect match. */
847	pEntry = pCur;
848	break;
849	}
850
851	if ( !pEntry
852	\|\| pEntry->uModel != uModel
853	\|\| pEntry->enmMicroarch != enmMicroarch
854	\|\| pEntry->uFamily != uFamily)
855	pEntry = pCur;
856	else if ( pCur->uStepping >= uStepping
857	? pCur->uStepping < pEntry->uStepping \|\| pEntry->uStepping < uStepping
858	: pCur->uStepping > pEntry->uStepping)
859	pEntry = pCur;
860	}
861	else if ( !pEntry
862	\|\| pEntry->enmMicroarch != enmMicroarch
863	\|\| pEntry->uFamily != uFamily)
864	pEntry = pCur;
865	else if ( pCur->uModel >= uModel
866	? pCur->uModel < pEntry->uModel \|\| pEntry->uModel < uModel
867	: pCur->uModel > pEntry->uModel)
868	pEntry = pCur;
869	}
870	else if ( !pEntry
871	\|\| pEntry->uFamily != uFamily)
872	pEntry = pCur;
873	/* Special march matching rules applies to intel family 06h. */
874	else if ( enmVendor == CPUMCPUVENDOR_INTEL
875	&& uFamily == 6
876	? cpumR3DbIsBetterIntelFam06Match(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch)
877	: cpumR3DbIsBetterMarchMatch(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch))
878	pEntry = pCur;
879	}
880	/* We don't do closeness matching on family, we use the first
881	entry for the CPU vendor instead. (P4 workaround.) */
882	else if (!pEntry)
883	pEntry = pCur;
884	}
885	}
886
887	if (pEntry)
888	LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
889	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
890	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
891	pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
892	else
893	{
894	pEntry = g_apCpumDbEntries[0];
895	LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'\n",
896	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
897	pEntry->pszName));
898	}
899	}
900	else
901	{
902	/*
903	* We're supposed to be emulating a specific CPU that is included in
904	* our CPU database. The CPUID tables needs to be copied onto the
905	* heap so the caller can modify them and so they can be freed like
906	* in the host case above.
907	*/
908	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
909	if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
910	{
911	pEntry = g_apCpumDbEntries[i];
912	break;
913	}
914	if (!pEntry)
915	{
916	LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
917	return VERR_CPUM_DB_CPU_NOT_FOUND;
918	}
919
920	pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
921	if (pEntry->cCpuIdLeaves)
922	{
923	/* Must allocate a multiple of 16 here, matching cpumR3CpuIdEnsureSpace. */
924	size_t cbExtra = sizeof(pEntry->paCpuIdLeaves[0]) * (RT_ALIGN(pEntry->cCpuIdLeaves, 16) - pEntry->cCpuIdLeaves);
925	pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDupEx(pEntry->paCpuIdLeaves,
926	sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves,
927	cbExtra);
928	if (!pInfo->paCpuIdLeavesR3)
929	return VERR_NO_MEMORY;
930	}
931	else
932	pInfo->paCpuIdLeavesR3 = NULL;
933
934	pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
935	pInfo->DefCpuId = pEntry->DefUnknownCpuId;
936	pInfo->fMxCsrMask = pEntry->fMxCsrMask;
937
938	LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
939	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
940	pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
941	}
942
943	pInfo->fMsrMask = pEntry->fMsrMask;
944	pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
945	pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
946	pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
947	pInfo->paMsrRangesR0 = NIL_RTR0PTR;
948	pInfo->paCpuIdLeavesRC = NIL_RTRCPTR;
949	pInfo->paMsrRangesRC = NIL_RTRCPTR;
950
951	/*
952	* Copy the MSR range.
953	*/
954	uint32_t cMsrs = 0;
955	PCPUMMSRRANGE paMsrs = NULL;
956
957	PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
958	uint32_t cLeft = pEntry->cMsrRanges;
959	while (cLeft-- > 0)
960	{
961	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &paMsrs, &cMsrs, pCurMsr);
962	if (RT_FAILURE(rc))
963	{
964	Assert(!paMsrs); /* The above function frees this. */
965	RTMemFree(pInfo->paCpuIdLeavesR3);
966	pInfo->paCpuIdLeavesR3 = NULL;
967	return rc;
968	}
969	pCurMsr++;
970	}
971
972	pInfo->paMsrRangesR3 = paMsrs;
973	pInfo->cMsrRanges = cMsrs;
974	return VINF_SUCCESS;
975	}
976
977
978	/**
979	* Insert an MSR range into the VM.
980	*
981	* If the new MSR range overlaps existing ranges, the existing ones will be
982	* adjusted/removed to fit in the new one.
983	*
984	* @returns VBox status code.
985	* @param pVM The cross context VM structure.
986	* @param pNewRange Pointer to the MSR range being inserted.
987	*/
988	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange)
989	{
990	AssertReturn(pVM, VERR_INVALID_PARAMETER);
991	AssertReturn(pNewRange, VERR_INVALID_PARAMETER);
992
993	return cpumR3MsrRangesInsert(pVM, NULL /* ppaMsrRanges /, NULL / pcMsrRanges */, pNewRange);
994	}
995
996
997	/**
998	* Register statistics for the MSRs.
999	*
1000	* This must not be called before the MSRs have been finalized and moved to the
1001	* hyper heap.
1002	*
1003	* @returns VBox status code.
1004	* @param pVM The cross context VM structure.
1005	*/
1006	int cpumR3MsrRegStats(PVM pVM)
1007	{
1008	/*
1009	* Global statistics.
1010	*/
1011	PCPUM pCpum = &pVM->cpum.s;
1012	STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
1013	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
1014	STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
1015	STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
1016	STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
1017	STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
1018	STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
1019	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
1020	STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
1021	STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
1022	STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
1023	STAMUNIT_OCCURENCES, "Writing of ignored bits.");
1024	STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
1025	STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
1026
1027
1028	# ifdef VBOX_WITH_STATISTICS
1029	/*
1030	* Per range.
1031	*/
1032	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
1033	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
1034	for (uint32_t i = 0; i < cRanges; i++)
1035	{
1036	char szName[160];
1037	ssize_t cchName;
1038
1039	if (paRanges[i].uFirst == paRanges[i].uLast)
1040	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
1041	paRanges[i].uFirst, paRanges[i].szName);
1042	else
1043	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
1044	paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
1045
1046	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
1047	STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
1048
1049	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
1050	STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
1051
1052	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
1053	STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
1054
1055	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
1056	STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
1057	}
1058	# endif /* VBOX_WITH_STATISTICS */
1059
1060	return VINF_SUCCESS;
1061	}
1062
1063	#endif /* !CPUM_DB_STANDALONE */
1064

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 69900

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