CPUMR3Db.cpp@ 78254

Last change on this file since 78254 was 76886, checked in by vboxsync, 6 years ago
VMM (and related changes): Add support for Shanghai/Zhaoxin CPUs. Modified and improved contribution by Journey Ren submitted under MIT license. Thank you!
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1	/* $Id: CPUMR3Db.cpp 76886 2019-01-18 10:57:02Z vboxsync $ */
2	/** @file
3	* CPUM - CPU database part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/mm.h>
27
28	#include <VBox/err.h>
29	#include <iprt/asm-amd64-x86.h>
30	#include <iprt/mem.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Structures and Typedefs *
36	*********************************************************************************************************************************/
37	typedef struct CPUMDBENTRY
38	{
39	/** The CPU name. */
40	const char *pszName;
41	/** The full CPU name. */
42	const char *pszFullName;
43	/** The CPU vendor (CPUMCPUVENDOR). */
44	uint8_t enmVendor;
45	/** The CPU family. */
46	uint8_t uFamily;
47	/** The CPU model. */
48	uint8_t uModel;
49	/** The CPU stepping. */
50	uint8_t uStepping;
51	/** The microarchitecture. */
52	CPUMMICROARCH enmMicroarch;
53	/** Scalable bus frequency used for reporting other frequencies. */
54	uint64_t uScalableBusFreq;
55	/** Flags - CPUDB_F_XXX. */
56	uint32_t fFlags;
57	/** The maximum physical address with of the CPU. This should correspond to
58	* the value in CPUID leaf 0x80000008 when present. */
59	uint8_t cMaxPhysAddrWidth;
60	/** The MXCSR mask. */
61	uint32_t fMxCsrMask;
62	/** Pointer to an array of CPUID leaves. */
63	PCCPUMCPUIDLEAF paCpuIdLeaves;
64	/** The number of CPUID leaves in the array paCpuIdLeaves points to. */
65	uint32_t cCpuIdLeaves;
66	/** The method used to deal with unknown CPUID leaves. */
67	CPUMUNKNOWNCPUID enmUnknownCpuId;
68	/** The default unknown CPUID value. */
69	CPUMCPUID DefUnknownCpuId;
70
71	/** MSR mask. Several microarchitectures ignore the higher bits of ECX in
72	* the RDMSR and WRMSR instructions. */
73	uint32_t fMsrMask;
74
75	/** The number of ranges in the table pointed to b paMsrRanges. */
76	uint32_t cMsrRanges;
77	/** MSR ranges for this CPU. */
78	PCCPUMMSRRANGE paMsrRanges;
79	} CPUMDBENTRY;
80
81
82	/*********************************************************************************************************************************
83	* Defined Constants And Macros *
84	*********************************************************************************************************************************/
85	/** @name CPUDB_F_XXX - CPUDBENTRY::fFlags
86	* @{ */
87	/** Should execute all in IEM.
88	* @todo Implement this - currently done in Main... */
89	#define CPUDB_F_EXECUTE_ALL_IN_IEM RT_BIT_32(0)
90	/** @} */
91
92
93	/** @def NULL_ALONE
94	* For eliminating an unnecessary data dependency in standalone builds (for
95	* VBoxSVC). */
96	/** @def ZERO_ALONE
97	* For eliminating an unnecessary data size dependency in standalone builds (for
98	* VBoxSVC). */
99	#ifndef CPUM_DB_STANDALONE
100	# define NULL_ALONE(a_aTable) a_aTable
101	# define ZERO_ALONE(a_cTable) a_cTable
102	#else
103	# define NULL_ALONE(a_aTable) NULL
104	# define ZERO_ALONE(a_cTable) 0
105	#endif
106
107
108	/** @name Short macros for the MSR range entries.
109	*
110	* These are rather cryptic, but this is to reduce the attack on the right
111	* margin.
112	*
113	* @{ */
114	/** Alias one MSR onto another (a_uTarget). */
115	#define MAL(a_uMsr, a_szName, a_uTarget) \
116	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
117	/** Functions handles everything. */
118	#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
119	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
120	/** Functions handles everything, with GP mask. */
121	#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
122	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
123	/** Function handlers, read-only. */
124	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
125	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
126	/** Function handlers, ignore all writes. */
127	#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
128	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
129	/** Function handlers, with value. */
130	#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
131	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
132	/** Function handlers, with write ignore mask. */
133	#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
134	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
135	/** Function handlers, extended version. */
136	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
137	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
138	/** Function handlers, with CPUMCPU storage variable. */
139	#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
140	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
141	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
142	/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
143	#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
144	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
145	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
146	/** Read-only fixed value. */
147	#define MVO(a_uMsr, a_szName, a_uValue) \
148	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
149	/** Read-only fixed value, ignores all writes. */
150	#define MVI(a_uMsr, a_szName, a_uValue) \
151	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
152	/** Read fixed value, ignore writes outside GP mask. */
153	#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
154	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
155	/** Read fixed value, extended version with both GP and ignore masks. */
156	#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
157	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
158	/** The short form, no CPUM backing. */
159	#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
160	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
161	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
162
163	/** Range: Functions handles everything. */
164	#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
165	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
166	/** Range: Read fixed value, read-only. */
167	#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
168	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
169	/** Range: Read fixed value, ignore writes. */
170	#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
171	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
172	/** Range: The short form, no CPUM backing. */
173	#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
174	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
175	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
176
177	/** Internal form used by the macros. */
178	#ifdef VBOX_WITH_STATISTICS
179	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
180	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
181	{ 0 }, { 0 }, { 0 }, { 0 } }
182	#else
183	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
184	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
185	#endif
186	/** @} */
187
188	#ifndef CPUM_DB_STANDALONE
189
190	#include "cpus/Intel_Core_i7_6700K.h"
191	#include "cpus/Intel_Core_i7_5600U.h"
192	#include "cpus/Intel_Core_i7_3960X.h"
193	#include "cpus/Intel_Core_i5_3570.h"
194	#include "cpus/Intel_Core_i7_2635QM.h"
195	#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
196	#include "cpus/Intel_Core2_X6800_2_93GHz.h"
197	#include "cpus/Intel_Core2_T7600_2_33GHz.h"
198	#include "cpus/Intel_Core_Duo_T2600_2_16GHz.h"
199	#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
200	#include "cpus/Intel_Pentium_4_3_00GHz.h"
201	#include "cpus/Intel_Pentium_N3530_2_16GHz.h"
202	#include "cpus/Intel_Atom_330_1_60GHz.h"
203	#include "cpus/Intel_80486.h"
204	#include "cpus/Intel_80386.h"
205	#include "cpus/Intel_80286.h"
206	#include "cpus/Intel_80186.h"
207	#include "cpus/Intel_8086.h"
208
209	#include "cpus/AMD_FX_8150_Eight_Core.h"
210	#include "cpus/AMD_Phenom_II_X6_1100T.h"
211	#include "cpus/Quad_Core_AMD_Opteron_2384.h"
212	#include "cpus/AMD_Athlon_64_X2_Dual_Core_4200.h"
213	#include "cpus/AMD_Athlon_64_3200.h"
214
215	#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
216
217	#include "cpus/ZHAOXIN_KaiXian_KX_U5581_1_8GHz.h"
218
219
220
221	/**
222	* The database entries.
223	*
224	* 1. The first entry is special. It is the fallback for unknown
225	* processors. Thus, it better be pretty representative.
226	*
227	* 2. The first entry for a CPU vendor is likewise important as it is
228	* the default entry for that vendor.
229	*
230	* Generally we put the most recent CPUs first, since these tend to have the
231	* most complicated and backwards compatible list of MSRs.
232	*/
233	static CPUMDBENTRY const * const g_apCpumDbEntries[] =
234	{
235	#ifdef VBOX_CPUDB_Intel_Core_i7_6700K_h
236	&g_Entry_Intel_Core_i7_6700K,
237	#endif
238	#ifdef VBOX_CPUDB_Intel_Core_i7_5600U_h
239	&g_Entry_Intel_Core_i7_5600U,
240	#endif
241	#ifdef VBOX_CPUDB_Intel_Core_i5_3570_h
242	&g_Entry_Intel_Core_i5_3570,
243	#endif
244	#ifdef VBOX_CPUDB_Intel_Core_i7_3960X_h
245	&g_Entry_Intel_Core_i7_3960X,
246	#endif
247	#ifdef VBOX_CPUDB_Intel_Core_i7_2635QM_h
248	&g_Entry_Intel_Core_i7_2635QM,
249	#endif
250	#ifdef VBOX_CPUDB_Intel_Pentium_N3530_2_16GHz_h
251	&g_Entry_Intel_Pentium_N3530_2_16GHz,
252	#endif
253	#ifdef VBOX_CPUDB_Intel_Atom_330_1_60GHz_h
254	&g_Entry_Intel_Atom_330_1_60GHz,
255	#endif
256	#ifdef VBOX_CPUDB_Intel_Pentium_M_processor_2_00GHz_h
257	&g_Entry_Intel_Pentium_M_processor_2_00GHz,
258	#endif
259	#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz_h
260	&g_Entry_Intel_Xeon_X5482_3_20GHz,
261	#endif
262	#ifdef VBOX_CPUDB_Intel_Core2_X6800_2_93GHz_h
263	&g_Entry_Intel_Core2_X6800_2_93GHz,
264	#endif
265	#ifdef VBOX_CPUDB_Intel_Core2_T7600_2_33GHz_h
266	&g_Entry_Intel_Core2_T7600_2_33GHz,
267	#endif
268	#ifdef VBOX_CPUDB_Intel_Core_Duo_T2600_2_16GHz_h
269	&g_Entry_Intel_Core_Duo_T2600_2_16GHz,
270	#endif
271	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz_h
272	&g_Entry_Intel_Pentium_4_3_00GHz,
273	#endif
274	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz_h
275	&g_Entry_Intel_Pentium_4_3_00GHz,
276	#endif
277	/** @todo pentium, pentium mmx, pentium pro, pentium II, pentium III */
278	#ifdef VBOX_CPUDB_Intel_80486_h
279	&g_Entry_Intel_80486,
280	#endif
281	#ifdef VBOX_CPUDB_Intel_80386_h
282	&g_Entry_Intel_80386,
283	#endif
284	#ifdef VBOX_CPUDB_Intel_80286_h
285	&g_Entry_Intel_80286,
286	#endif
287	#ifdef VBOX_CPUDB_Intel_80186_h
288	&g_Entry_Intel_80186,
289	#endif
290	#ifdef VBOX_CPUDB_Intel_8086_h
291	&g_Entry_Intel_8086,
292	#endif
293
294	#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core_h
295	&g_Entry_AMD_FX_8150_Eight_Core,
296	#endif
297	#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T_h
298	&g_Entry_AMD_Phenom_II_X6_1100T,
299	#endif
300	#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384_h
301	&g_Entry_Quad_Core_AMD_Opteron_2384,
302	#endif
303	#ifdef VBOX_CPUDB_AMD_Athlon_64_X2_Dual_Core_4200_h
304	&g_Entry_AMD_Athlon_64_X2_Dual_Core_4200,
305	#endif
306	#ifdef VBOX_CPUDB_AMD_Athlon_64_3200_h
307	&g_Entry_AMD_Athlon_64_3200,
308	#endif
309
310	#ifdef VBOX_CPUDB_ZHAOXIN_KaiXian_KX_U5581_1_8GHz_h
311	&g_Entry_ZHAOXIN_KaiXian_KX_U5581_1_8GHz,
312	#endif
313
314	#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz_h
315	&g_Entry_VIA_QuadCore_L4700_1_2_GHz,
316	#endif
317
318	#ifdef VBOX_CPUDB_NEC_V20_h
319	&g_Entry_NEC_V20,
320	#endif
321	};
322
323
324
325	/**
326	* Binary search used by cpumR3MsrRangesInsert and has some special properties
327	* wrt to mismatches.
328	*
329	* @returns Insert location.
330	* @param paMsrRanges The MSR ranges to search.
331	* @param cMsrRanges The number of MSR ranges.
332	* @param uMsr What to search for.
333	*/
334	static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
335	{
336	if (!cMsrRanges)
337	return 0;
338
339	uint32_t iStart = 0;
340	uint32_t iLast = cMsrRanges - 1;
341	for (;;)
342	{
343	uint32_t i = iStart + (iLast - iStart + 1) / 2;
344	if ( uMsr >= paMsrRanges[i].uFirst
345	&& uMsr <= paMsrRanges[i].uLast)
346	return i;
347	if (uMsr < paMsrRanges[i].uFirst)
348	{
349	if (i <= iStart)
350	return i;
351	iLast = i - 1;
352	}
353	else
354	{
355	if (i >= iLast)
356	{
357	if (i < cMsrRanges)
358	i++;
359	return i;
360	}
361	iStart = i + 1;
362	}
363	}
364	}
365
366
367	/**
368	* Ensures that there is space for at least @a cNewRanges in the table,
369	* reallocating the table if necessary.
370	*
371	* @returns Pointer to the MSR ranges on success, NULL on failure. On failure
372	* @a *ppaMsrRanges is freed and set to NULL.
373	* @param pVM The cross context VM structure. If NULL,
374	* use the process heap, otherwise the VM's hyper heap.
375	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
376	* @param cMsrRanges The current number of ranges.
377	* @param cNewRanges The number of ranges to be added.
378	*/
379	static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
380	{
381	uint32_t cMsrRangesAllocated;
382	if (!pVM)
383	cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
384	else
385	{
386	/*
387	* We're using the hyper heap now, but when the range array was copied over to it from
388	* the host-context heap, we only copy the exact size and not the ensured size.
389	* See @bugref{7270}.
390	*/
391	cMsrRangesAllocated = cMsrRanges;
392	}
393	if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
394	{
395	void *pvNew;
396	uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
397	if (pVM)
398	{
399	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
400	Assert(cMsrRanges == pVM->cpum.s.GuestInfo.cMsrRanges);
401
402	size_t cb = cMsrRangesAllocated * sizeof(**ppaMsrRanges);
403	size_t cbNew = cNew * sizeof(**ppaMsrRanges);
404	int rc = MMR3HyperRealloc(pVM, *ppaMsrRanges, cb, 32, MM_TAG_CPUM_MSRS, cbNew, &pvNew);
405	if (RT_FAILURE(rc))
406	{
407	*ppaMsrRanges = NULL;
408	pVM->cpum.s.GuestInfo.paMsrRangesR0 = NIL_RTR0PTR;
409	pVM->cpum.s.GuestInfo.paMsrRangesRC = NIL_RTRCPTR;
410	LogRel(("CPUM: cpumR3MsrRangesEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
411	return NULL;
412	}
413	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
414	}
415	else
416	{
417	pvNew = RTMemRealloc(ppaMsrRanges, cNew sizeof(**ppaMsrRanges));
418	if (!pvNew)
419	{
420	RTMemFree(*ppaMsrRanges);
421	*ppaMsrRanges = NULL;
422	return NULL;
423	}
424	}
425	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
426	}
427
428	if (pVM)
429	{
430	/* Update R0 and RC pointers. */
431	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
432	pVM->cpum.s.GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, *ppaMsrRanges);
433	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, *ppaMsrRanges);
434	}
435
436	return *ppaMsrRanges;
437	}
438
439
440	/**
441	* Inserts a new MSR range in into an sorted MSR range array.
442	*
443	* If the new MSR range overlaps existing ranges, the existing ones will be
444	* adjusted/removed to fit in the new one.
445	*
446	* @returns VBox status code.
447	* @retval VINF_SUCCESS
448	* @retval VERR_NO_MEMORY
449	*
450	* @param pVM The cross context VM structure. If NULL,
451	* use the process heap, otherwise the VM's hyper heap.
452	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
453	* Must be NULL if using the hyper heap.
454	* @param pcMsrRanges The variable holding number of ranges. Must be NULL
455	* if using the hyper heap.
456	* @param pNewRange The new range.
457	*/
458	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange)
459	{
460	Assert(pNewRange->uLast >= pNewRange->uFirst);
461	Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
462	Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
463
464	/*
465	* Validate and use the VM's MSR ranges array if we are using the hyper heap.
466	*/
467	if (pVM)
468	{
469	AssertReturn(!ppaMsrRanges, VERR_INVALID_PARAMETER);
470	AssertReturn(!pcMsrRanges, VERR_INVALID_PARAMETER);
471
472	ppaMsrRanges = &pVM->cpum.s.GuestInfo.paMsrRangesR3;
473	pcMsrRanges = &pVM->cpum.s.GuestInfo.cMsrRanges;
474	}
475	else
476	{
477	AssertReturn(ppaMsrRanges, VERR_INVALID_POINTER);
478	AssertReturn(pcMsrRanges, VERR_INVALID_POINTER);
479	}
480
481	uint32_t cMsrRanges = *pcMsrRanges;
482	PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
483
484	/*
485	* Optimize the linear insertion case where we add new entries at the end.
486	*/
487	if ( cMsrRanges > 0
488	&& paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
489	{
490	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
491	if (!paMsrRanges)
492	return VERR_NO_MEMORY;
493	paMsrRanges[cMsrRanges] = *pNewRange;
494	*pcMsrRanges += 1;
495	}
496	else
497	{
498	uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
499	Assert(i == cMsrRanges \|\| pNewRange->uFirst <= paMsrRanges[i].uLast);
500	Assert(i == 0 \|\| pNewRange->uFirst > paMsrRanges[i - 1].uLast);
501
502	/*
503	* Adding an entirely new entry?
504	*/
505	if ( i >= cMsrRanges
506	\|\| pNewRange->uLast < paMsrRanges[i].uFirst)
507	{
508	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
509	if (!paMsrRanges)
510	return VERR_NO_MEMORY;
511	if (i < cMsrRanges)
512	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
513	paMsrRanges[i] = *pNewRange;
514	*pcMsrRanges += 1;
515	}
516	/*
517	* Replace existing entry?
518	*/
519	else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
520	&& pNewRange->uLast == paMsrRanges[i].uLast)
521	paMsrRanges[i] = *pNewRange;
522	/*
523	* Splitting an existing entry?
524	*/
525	else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
526	&& pNewRange->uLast < paMsrRanges[i].uLast)
527	{
528	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 2);
529	if (!paMsrRanges)
530	return VERR_NO_MEMORY;
531	if (i < cMsrRanges)
532	memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
533	paMsrRanges[i + 1] = *pNewRange;
534	paMsrRanges[i + 2] = paMsrRanges[i];
535	paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
536	paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
537	*pcMsrRanges += 2;
538	}
539	/*
540	* Complicated scenarios that can affect more than one range.
541	*
542	* The current code does not optimize memmove calls when replacing
543	* one or more existing ranges, because it's tedious to deal with and
544	* not expected to be a frequent usage scenario.
545	*/
546	else
547	{
548	/* Adjust start of first match? */
549	if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
550	&& pNewRange->uLast < paMsrRanges[i].uLast)
551	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
552	else
553	{
554	/* Adjust end of first match? */
555	if (pNewRange->uFirst > paMsrRanges[i].uFirst)
556	{
557	Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
558	paMsrRanges[i].uLast = pNewRange->uFirst - 1;
559	i++;
560	}
561	/* Replace the whole first match (lazy bird). */
562	else
563	{
564	if (i + 1 < cMsrRanges)
565	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
566	cMsrRanges = *pcMsrRanges -= 1;
567	}
568
569	/* Do the new range affect more ranges? */
570	while ( i < cMsrRanges
571	&& pNewRange->uLast >= paMsrRanges[i].uFirst)
572	{
573	if (pNewRange->uLast < paMsrRanges[i].uLast)
574	{
575	/* Adjust the start of it, then we're done. */
576	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
577	break;
578	}
579
580	/* Remove it entirely. */
581	if (i + 1 < cMsrRanges)
582	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
583	cMsrRanges = *pcMsrRanges -= 1;
584	}
585	}
586
587	/* Now, perform a normal insertion. */
588	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
589	if (!paMsrRanges)
590	return VERR_NO_MEMORY;
591	if (i < cMsrRanges)
592	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
593	paMsrRanges[i] = *pNewRange;
594	*pcMsrRanges += 1;
595	}
596	}
597
598	return VINF_SUCCESS;
599	}
600
601
602	/**
603	* Reconciles CPUID info with MSRs (selected ones).
604	*
605	* @returns VBox status code.
606	* @param pVM The cross context VM structure.
607	*/
608	int cpumR3MsrReconcileWithCpuId(PVM pVM)
609	{
610	PCCPUMMSRRANGE papToAdd[10];
611	uint32_t cToAdd = 0;
612
613	/*
614	* The IA32_FLUSH_CMD MSR was introduced in MCUs for CVS-2018-3646 and associates.
615	*/
616	if (pVM->cpum.s.GuestFeatures.fFlushCmd && !cpumLookupMsrRange(pVM, MSR_IA32_FLUSH_CMD))
617	{
618	static CPUMMSRRANGE const s_FlushCmd =
619	{
620	/.uFirst =/ MSR_IA32_FLUSH_CMD,
621	/.uLast =/ MSR_IA32_FLUSH_CMD,
622	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly,
623	/.enmWrFn =/ kCpumMsrWrFn_Ia32FlushCmd,
624	/.offCpumCpu =/ UINT16_MAX,
625	/.fReserved =/ 0,
626	/.uValue =/ 0,
627	/.fWrIgnMask =/ 0,
628	/.fWrGpMask =/ ~MSR_IA32_FLUSH_CMD_F_L1D,
629	/.szName = / "IA32_FLUSH_CMD"
630	};
631	papToAdd[cToAdd++] = &s_FlushCmd;
632	}
633
634	/*
635	* Do the adding.
636	*/
637	for (uint32_t i = 0; i < cToAdd; i++)
638	{
639	PCCPUMMSRRANGE pRange = papToAdd[i];
640	LogRel(("CPUM: MSR/CPUID reconciliation insert: %#010x %s\n", pRange->uFirst, pRange->szName));
641	int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
642	pRange);
643	if (RT_FAILURE(rc))
644	return rc;
645	}
646	return VINF_SUCCESS;
647	}
648
649
650	/**
651	* Worker for cpumR3MsrApplyFudge that applies one table.
652	*
653	* @returns VBox status code.
654	* @param pVM The cross context VM structure.
655	* @param paRanges Array of MSRs to fudge.
656	* @param cRanges Number of MSRs in the array.
657	*/
658	static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
659	{
660	for (uint32_t i = 0; i < cRanges; i++)
661	if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
662	{
663	LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
664	int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
665	&paRanges[i]);
666	if (RT_FAILURE(rc))
667	return rc;
668	}
669	return VINF_SUCCESS;
670	}
671
672
673	/**
674	* Fudges the MSRs that guest are known to access in some odd cases.
675	*
676	* A typical example is a VM that has been moved between different hosts where
677	* for instance the cpu vendor differs.
678	*
679	* Another example is older CPU profiles (e.g. Atom Bonnet) for newer CPUs (e.g.
680	* Atom Silvermont), where features reported thru CPUID aren't present in the
681	* MSRs (e.g. AMD64_TSC_AUX).
682	*
683	*
684	* @returns VBox status code.
685	* @param pVM The cross context VM structure.
686	*/
687	int cpumR3MsrApplyFudge(PVM pVM)
688	{
689	/*
690	* Basic.
691	*/
692	static CPUMMSRRANGE const s_aFudgeMsrs[] =
693	{
694	MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
695	MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
696	MVO(0x00000017, "IA32_PLATFORM_ID", 0),
697	MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
698	MVI(0x0000008b, "BIOS_SIGN", 0),
699	MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
700	MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
701	MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
702	MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
703	MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
704	MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
705	MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
706	MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
707	MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
708	MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
709	MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
710	MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
711	};
712	int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
713	AssertLogRelRCReturn(rc, rc);
714
715	/*
716	* XP might mistake opterons and other newer CPUs for P4s.
717	*/
718	if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
719	{
720	static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
721	{
722	MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
723	};
724	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
725	AssertLogRelRCReturn(rc, rc);
726	}
727
728	if (pVM->cpum.s.GuestFeatures.fRdTscP)
729	{
730	static CPUMMSRRANGE const s_aRdTscPFudgeMsrs[] =
731	{
732	MFX(0xc0000103, "AMD64_TSC_AUX", Amd64TscAux, Amd64TscAux, 0, 0, ~(uint64_t)UINT32_MAX),
733	};
734	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aRdTscPFudgeMsrs[0], RT_ELEMENTS(s_aRdTscPFudgeMsrs));
735	AssertLogRelRCReturn(rc, rc);
736	}
737
738	return rc;
739	}
740
741
742	/**
743	* Do we consider @a enmConsider a better match for @a enmTarget than
744	* @a enmFound?
745	*
746	* Only called when @a enmConsider isn't exactly what we're looking for.
747	*
748	* @returns true/false.
749	* @param enmConsider The new microarch to consider.
750	* @param enmTarget The target microarch.
751	* @param enmFound The best microarch match we've found thus far.
752	*/
753	DECLINLINE(bool) cpumR3DbIsBetterMarchMatch(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
754	{
755	Assert(enmConsider != enmTarget);
756
757	/*
758	* If we've got an march match, don't bother with enmConsider.
759	*/
760	if (enmFound == enmTarget)
761	return false;
762
763	/*
764	* Found is below: Pick 'consider' if it's closer to the target or above it.
765	*/
766	if (enmFound < enmTarget)
767	return enmConsider > enmFound;
768
769	/*
770	* Found is above: Pick 'consider' if it's also above (paranoia: or equal)
771	* and but closer to the target.
772	*/
773	return enmConsider >= enmTarget && enmConsider < enmFound;
774	}
775
776
777	/**
778	* Do we consider @a enmConsider a better match for @a enmTarget than
779	* @a enmFound?
780	*
781	* Only called for intel family 06h CPUs.
782	*
783	* @returns true/false.
784	* @param enmConsider The new microarch to consider.
785	* @param enmTarget The target microarch.
786	* @param enmFound The best microarch match we've found thus far.
787	*/
788	static bool cpumR3DbIsBetterIntelFam06Match(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
789	{
790	/* Check intel family 06h claims. */
791	AssertReturn(enmConsider >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmConsider <= kCpumMicroarch_Intel_P6_Core_Atom_End,
792	false);
793	AssertReturn(enmTarget >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmTarget <= kCpumMicroarch_Intel_P6_Core_Atom_End,
794	false);
795
796	/* Put matches out of the way. */
797	if (enmConsider == enmTarget)
798	return true;
799	if (enmFound == enmTarget)
800	return false;
801
802	/* If found isn't a family 06h march, whatever we're considering must be a better choice. */
803	if ( enmFound < kCpumMicroarch_Intel_P6_Core_Atom_First
804	\|\| enmFound > kCpumMicroarch_Intel_P6_Core_Atom_End)
805	return true;
806
807	/*
808	* The family 06h stuff is split into three categories:
809	* - Common P6 heritage
810	* - Core
811	* - Atom
812	*
813	* Determin which of the three arguments are Atom marchs, because that's
814	* all we need to make the right choice.
815	*/
816	bool const fConsiderAtom = enmConsider >= kCpumMicroarch_Intel_Atom_First;
817	bool const fTargetAtom = enmTarget >= kCpumMicroarch_Intel_Atom_First;
818	bool const fFoundAtom = enmFound >= kCpumMicroarch_Intel_Atom_First;
819
820	/*
821	* Want atom:
822	*/
823	if (fTargetAtom)
824	{
825	/* Pick the atom if we've got one of each.*/
826	if (fConsiderAtom != fFoundAtom)
827	return fConsiderAtom;
828	/* If we haven't got any atoms under consideration, pick a P6 or the earlier core.
829	Note! Not entirely sure Dothan is the best choice, but it'll do for now. */
830	if (!fConsiderAtom)
831	{
832	if (enmConsider > enmFound)
833	return enmConsider <= kCpumMicroarch_Intel_P6_M_Dothan;
834	return enmFound > kCpumMicroarch_Intel_P6_M_Dothan;
835	}
836	/* else: same category, default comparison rules. */
837	Assert(fConsiderAtom && fFoundAtom);
838	}
839	/*
840	* Want non-atom:
841	*/
842	/* Pick the non-atom if we've got one of each. */
843	else if (fConsiderAtom != fFoundAtom)
844	return fFoundAtom;
845	/* If we've only got atoms under consideration, pick the older one just to pick something. */
846	else if (fConsiderAtom)
847	return enmConsider < enmFound;
848	else
849	Assert(!fConsiderAtom && !fFoundAtom);
850
851	/*
852	* Same basic category. Do same compare as caller.
853	*/
854	return cpumR3DbIsBetterMarchMatch(enmConsider, enmTarget, enmFound);
855	}
856
857
858	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
859	{
860	CPUMDBENTRY const *pEntry = NULL;
861	int rc;
862
863	if (!strcmp(pszName, "host"))
864	{
865	/*
866	* Create a CPU database entry for the host CPU. This means getting
867	* the CPUID bits from the real CPU and grabbing the closest matching
868	* database entry for MSRs.
869	*/
870	rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
871	if (RT_FAILURE(rc))
872	return rc;
873	rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
874	if (RT_FAILURE(rc))
875	return rc;
876	pInfo->fMxCsrMask = CPUMR3DeterminHostMxCsrMask();
877
878	/* Lookup database entry for MSRs. */
879	CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
880	pInfo->paCpuIdLeavesR3[0].uEbx,
881	pInfo->paCpuIdLeavesR3[0].uEcx,
882	pInfo->paCpuIdLeavesR3[0].uEdx);
883	uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
884	uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
885	uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
886	uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
887	CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
888
889	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
890	{
891	CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
892	if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
893	{
894	/* Match against Family, Microarch, model and stepping. Except
895	for family, always match the closer with preference given to
896	the later/older ones. */
897	if (pCur->uFamily == uFamily)
898	{
899	if (pCur->enmMicroarch == enmMicroarch)
900	{
901	if (pCur->uModel == uModel)
902	{
903	if (pCur->uStepping == uStepping)
904	{
905	/* Perfect match. */
906	pEntry = pCur;
907	break;
908	}
909
910	if ( !pEntry
911	\|\| pEntry->uModel != uModel
912	\|\| pEntry->enmMicroarch != enmMicroarch
913	\|\| pEntry->uFamily != uFamily)
914	pEntry = pCur;
915	else if ( pCur->uStepping >= uStepping
916	? pCur->uStepping < pEntry->uStepping \|\| pEntry->uStepping < uStepping
917	: pCur->uStepping > pEntry->uStepping)
918	pEntry = pCur;
919	}
920	else if ( !pEntry
921	\|\| pEntry->enmMicroarch != enmMicroarch
922	\|\| pEntry->uFamily != uFamily)
923	pEntry = pCur;
924	else if ( pCur->uModel >= uModel
925	? pCur->uModel < pEntry->uModel \|\| pEntry->uModel < uModel
926	: pCur->uModel > pEntry->uModel)
927	pEntry = pCur;
928	}
929	else if ( !pEntry
930	\|\| pEntry->uFamily != uFamily)
931	pEntry = pCur;
932	/* Special march matching rules applies to intel family 06h. */
933	else if ( enmVendor == CPUMCPUVENDOR_INTEL
934	&& uFamily == 6
935	? cpumR3DbIsBetterIntelFam06Match(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch)
936	: cpumR3DbIsBetterMarchMatch(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch))
937	pEntry = pCur;
938	}
939	/* We don't do closeness matching on family, we use the first
940	entry for the CPU vendor instead. (P4 workaround.) */
941	else if (!pEntry)
942	pEntry = pCur;
943	}
944	}
945
946	if (pEntry)
947	LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
948	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
949	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
950	pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
951	else
952	{
953	pEntry = g_apCpumDbEntries[0];
954	LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'\n",
955	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
956	pEntry->pszName));
957	}
958	}
959	else
960	{
961	/*
962	* We're supposed to be emulating a specific CPU that is included in
963	* our CPU database. The CPUID tables needs to be copied onto the
964	* heap so the caller can modify them and so they can be freed like
965	* in the host case above.
966	*/
967	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
968	if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
969	{
970	pEntry = g_apCpumDbEntries[i];
971	break;
972	}
973	if (!pEntry)
974	{
975	LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
976	return VERR_CPUM_DB_CPU_NOT_FOUND;
977	}
978
979	pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
980	if (pEntry->cCpuIdLeaves)
981	{
982	/* Must allocate a multiple of 16 here, matching cpumR3CpuIdEnsureSpace. */
983	size_t cbExtra = sizeof(pEntry->paCpuIdLeaves[0]) * (RT_ALIGN(pEntry->cCpuIdLeaves, 16) - pEntry->cCpuIdLeaves);
984	pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDupEx(pEntry->paCpuIdLeaves,
985	sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves,
986	cbExtra);
987	if (!pInfo->paCpuIdLeavesR3)
988	return VERR_NO_MEMORY;
989	}
990	else
991	pInfo->paCpuIdLeavesR3 = NULL;
992
993	pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
994	pInfo->DefCpuId = pEntry->DefUnknownCpuId;
995	pInfo->fMxCsrMask = pEntry->fMxCsrMask;
996
997	LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
998	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
999	pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
1000	}
1001
1002	pInfo->fMsrMask = pEntry->fMsrMask;
1003	pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
1004	pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
1005	pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
1006	pInfo->paMsrRangesR0 = NIL_RTR0PTR;
1007	pInfo->paCpuIdLeavesRC = NIL_RTRCPTR;
1008	pInfo->paMsrRangesRC = NIL_RTRCPTR;
1009
1010	/*
1011	* Copy the MSR range.
1012	*/
1013	uint32_t cMsrs = 0;
1014	PCPUMMSRRANGE paMsrs = NULL;
1015
1016	PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
1017	uint32_t cLeft = pEntry->cMsrRanges;
1018	while (cLeft-- > 0)
1019	{
1020	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &paMsrs, &cMsrs, pCurMsr);
1021	if (RT_FAILURE(rc))
1022	{
1023	Assert(!paMsrs); /* The above function frees this. */
1024	RTMemFree(pInfo->paCpuIdLeavesR3);
1025	pInfo->paCpuIdLeavesR3 = NULL;
1026	return rc;
1027	}
1028	pCurMsr++;
1029	}
1030
1031	pInfo->paMsrRangesR3 = paMsrs;
1032	pInfo->cMsrRanges = cMsrs;
1033	return VINF_SUCCESS;
1034	}
1035
1036
1037	/**
1038	* Insert an MSR range into the VM.
1039	*
1040	* If the new MSR range overlaps existing ranges, the existing ones will be
1041	* adjusted/removed to fit in the new one.
1042	*
1043	* @returns VBox status code.
1044	* @param pVM The cross context VM structure.
1045	* @param pNewRange Pointer to the MSR range being inserted.
1046	*/
1047	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange)
1048	{
1049	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1050	AssertReturn(pNewRange, VERR_INVALID_PARAMETER);
1051
1052	return cpumR3MsrRangesInsert(pVM, NULL /* ppaMsrRanges /, NULL / pcMsrRanges */, pNewRange);
1053	}
1054
1055
1056	/**
1057	* Register statistics for the MSRs.
1058	*
1059	* This must not be called before the MSRs have been finalized and moved to the
1060	* hyper heap.
1061	*
1062	* @returns VBox status code.
1063	* @param pVM The cross context VM structure.
1064	*/
1065	int cpumR3MsrRegStats(PVM pVM)
1066	{
1067	/*
1068	* Global statistics.
1069	*/
1070	PCPUM pCpum = &pVM->cpum.s;
1071	STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
1072	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
1073	STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
1074	STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
1075	STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
1076	STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
1077	STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
1078	STAMUNIT_OCCURENCES, "All WRMSRs making it to CPUM.");
1079	STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
1080	STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
1081	STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
1082	STAMUNIT_OCCURENCES, "Writing of ignored bits.");
1083	STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
1084	STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
1085
1086
1087	# ifdef VBOX_WITH_STATISTICS
1088	/*
1089	* Per range.
1090	*/
1091	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
1092	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
1093	for (uint32_t i = 0; i < cRanges; i++)
1094	{
1095	char szName[160];
1096	ssize_t cchName;
1097
1098	if (paRanges[i].uFirst == paRanges[i].uLast)
1099	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
1100	paRanges[i].uFirst, paRanges[i].szName);
1101	else
1102	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
1103	paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
1104
1105	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
1106	STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
1107
1108	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
1109	STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
1110
1111	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
1112	STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
1113
1114	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
1115	STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
1116	}
1117	# endif /* VBOX_WITH_STATISTICS */
1118
1119	return VINF_SUCCESS;
1120	}
1121
1122	#endif /* !CPUM_DB_STANDALONE */
1123

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 78254

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