CPUMR3Db.cpp@ 80239

Last change on this file since 80239 was 80191, checked in by vboxsync, 5 years ago
VMM/r3: Refactored VMCPU enumeration in preparation that aCpus will be replaced with a pointer array. Removed two raw-mode offset members from the CPUM and CPUMCPU sub-structures. bugref:9217 bugref:9517
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 45.0 KB

Line
1	/* $Id: CPUMR3Db.cpp 80191 2019-08-08 00:36:57Z vboxsync $ */
2	/** @file
3	* CPUM - CPU database part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define VBOX_BUGREF_9217_PART_I
23	#define LOG_GROUP LOG_GROUP_CPUM
24	#include <VBox/vmm/cpum.h>
25	#include "CPUMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/mm.h>
28
29	#include <VBox/err.h>
30	#include <iprt/asm-amd64-x86.h>
31	#include <iprt/mem.h>
32	#include <iprt/string.h>
33
34
35	/*********************************************************************************************************************************
36	* Structures and Typedefs *
37	*********************************************************************************************************************************/
38	typedef struct CPUMDBENTRY
39	{
40	/** The CPU name. */
41	const char *pszName;
42	/** The full CPU name. */
43	const char *pszFullName;
44	/** The CPU vendor (CPUMCPUVENDOR). */
45	uint8_t enmVendor;
46	/** The CPU family. */
47	uint8_t uFamily;
48	/** The CPU model. */
49	uint8_t uModel;
50	/** The CPU stepping. */
51	uint8_t uStepping;
52	/** The microarchitecture. */
53	CPUMMICROARCH enmMicroarch;
54	/** Scalable bus frequency used for reporting other frequencies. */
55	uint64_t uScalableBusFreq;
56	/** Flags - CPUDB_F_XXX. */
57	uint32_t fFlags;
58	/** The maximum physical address with of the CPU. This should correspond to
59	* the value in CPUID leaf 0x80000008 when present. */
60	uint8_t cMaxPhysAddrWidth;
61	/** The MXCSR mask. */
62	uint32_t fMxCsrMask;
63	/** Pointer to an array of CPUID leaves. */
64	PCCPUMCPUIDLEAF paCpuIdLeaves;
65	/** The number of CPUID leaves in the array paCpuIdLeaves points to. */
66	uint32_t cCpuIdLeaves;
67	/** The method used to deal with unknown CPUID leaves. */
68	CPUMUNKNOWNCPUID enmUnknownCpuId;
69	/** The default unknown CPUID value. */
70	CPUMCPUID DefUnknownCpuId;
71
72	/** MSR mask. Several microarchitectures ignore the higher bits of ECX in
73	* the RDMSR and WRMSR instructions. */
74	uint32_t fMsrMask;
75
76	/** The number of ranges in the table pointed to b paMsrRanges. */
77	uint32_t cMsrRanges;
78	/** MSR ranges for this CPU. */
79	PCCPUMMSRRANGE paMsrRanges;
80	} CPUMDBENTRY;
81
82
83	/*********************************************************************************************************************************
84	* Defined Constants And Macros *
85	*********************************************************************************************************************************/
86	/** @name CPUDB_F_XXX - CPUDBENTRY::fFlags
87	* @{ */
88	/** Should execute all in IEM.
89	* @todo Implement this - currently done in Main... */
90	#define CPUDB_F_EXECUTE_ALL_IN_IEM RT_BIT_32(0)
91	/** @} */
92
93
94	/** @def NULL_ALONE
95	* For eliminating an unnecessary data dependency in standalone builds (for
96	* VBoxSVC). */
97	/** @def ZERO_ALONE
98	* For eliminating an unnecessary data size dependency in standalone builds (for
99	* VBoxSVC). */
100	#ifndef CPUM_DB_STANDALONE
101	# define NULL_ALONE(a_aTable) a_aTable
102	# define ZERO_ALONE(a_cTable) a_cTable
103	#else
104	# define NULL_ALONE(a_aTable) NULL
105	# define ZERO_ALONE(a_cTable) 0
106	#endif
107
108
109	/** @name Short macros for the MSR range entries.
110	*
111	* These are rather cryptic, but this is to reduce the attack on the right
112	* margin.
113	*
114	* @{ */
115	/** Alias one MSR onto another (a_uTarget). */
116	#define MAL(a_uMsr, a_szName, a_uTarget) \
117	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
118	/** Functions handles everything. */
119	#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
120	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
121	/** Functions handles everything, with GP mask. */
122	#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
123	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
124	/** Function handlers, read-only. */
125	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
126	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
127	/** Function handlers, ignore all writes. */
128	#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
129	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
130	/** Function handlers, with value. */
131	#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
132	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
133	/** Function handlers, with write ignore mask. */
134	#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
135	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
136	/** Function handlers, extended version. */
137	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
138	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
139	/** Function handlers, with CPUMCPU storage variable. */
140	#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
141	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
142	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
143	/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
144	#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
145	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
146	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
147	/** Read-only fixed value. */
148	#define MVO(a_uMsr, a_szName, a_uValue) \
149	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
150	/** Read-only fixed value, ignores all writes. */
151	#define MVI(a_uMsr, a_szName, a_uValue) \
152	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
153	/** Read fixed value, ignore writes outside GP mask. */
154	#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
155	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
156	/** Read fixed value, extended version with both GP and ignore masks. */
157	#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
158	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
159	/** The short form, no CPUM backing. */
160	#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
161	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
162	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
163
164	/** Range: Functions handles everything. */
165	#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
166	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
167	/** Range: Read fixed value, read-only. */
168	#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
169	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
170	/** Range: Read fixed value, ignore writes. */
171	#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
172	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
173	/** Range: The short form, no CPUM backing. */
174	#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
175	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
176	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
177
178	/** Internal form used by the macros. */
179	#ifdef VBOX_WITH_STATISTICS
180	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
181	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
182	{ 0 }, { 0 }, { 0 }, { 0 } }
183	#else
184	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
185	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
186	#endif
187	/** @} */
188
189	#ifndef CPUM_DB_STANDALONE
190
191	#include "cpus/Intel_Core_i7_6700K.h"
192	#include "cpus/Intel_Core_i7_5600U.h"
193	#include "cpus/Intel_Core_i7_3960X.h"
194	#include "cpus/Intel_Core_i5_3570.h"
195	#include "cpus/Intel_Core_i7_2635QM.h"
196	#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
197	#include "cpus/Intel_Core2_X6800_2_93GHz.h"
198	#include "cpus/Intel_Core2_T7600_2_33GHz.h"
199	#include "cpus/Intel_Core_Duo_T2600_2_16GHz.h"
200	#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
201	#include "cpus/Intel_Pentium_4_3_00GHz.h"
202	#include "cpus/Intel_Pentium_N3530_2_16GHz.h"
203	#include "cpus/Intel_Atom_330_1_60GHz.h"
204	#include "cpus/Intel_80486.h"
205	#include "cpus/Intel_80386.h"
206	#include "cpus/Intel_80286.h"
207	#include "cpus/Intel_80186.h"
208	#include "cpus/Intel_8086.h"
209
210	#include "cpus/AMD_FX_8150_Eight_Core.h"
211	#include "cpus/AMD_Phenom_II_X6_1100T.h"
212	#include "cpus/Quad_Core_AMD_Opteron_2384.h"
213	#include "cpus/AMD_Athlon_64_X2_Dual_Core_4200.h"
214	#include "cpus/AMD_Athlon_64_3200.h"
215
216	#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
217
218	#include "cpus/ZHAOXIN_KaiXian_KX_U5581_1_8GHz.h"
219
220
221
222	/**
223	* The database entries.
224	*
225	* 1. The first entry is special. It is the fallback for unknown
226	* processors. Thus, it better be pretty representative.
227	*
228	* 2. The first entry for a CPU vendor is likewise important as it is
229	* the default entry for that vendor.
230	*
231	* Generally we put the most recent CPUs first, since these tend to have the
232	* most complicated and backwards compatible list of MSRs.
233	*/
234	static CPUMDBENTRY const * const g_apCpumDbEntries[] =
235	{
236	#ifdef VBOX_CPUDB_Intel_Core_i7_6700K_h
237	&g_Entry_Intel_Core_i7_6700K,
238	#endif
239	#ifdef VBOX_CPUDB_Intel_Core_i7_5600U_h
240	&g_Entry_Intel_Core_i7_5600U,
241	#endif
242	#ifdef VBOX_CPUDB_Intel_Core_i5_3570_h
243	&g_Entry_Intel_Core_i5_3570,
244	#endif
245	#ifdef VBOX_CPUDB_Intel_Core_i7_3960X_h
246	&g_Entry_Intel_Core_i7_3960X,
247	#endif
248	#ifdef VBOX_CPUDB_Intel_Core_i7_2635QM_h
249	&g_Entry_Intel_Core_i7_2635QM,
250	#endif
251	#ifdef VBOX_CPUDB_Intel_Pentium_N3530_2_16GHz_h
252	&g_Entry_Intel_Pentium_N3530_2_16GHz,
253	#endif
254	#ifdef VBOX_CPUDB_Intel_Atom_330_1_60GHz_h
255	&g_Entry_Intel_Atom_330_1_60GHz,
256	#endif
257	#ifdef VBOX_CPUDB_Intel_Pentium_M_processor_2_00GHz_h
258	&g_Entry_Intel_Pentium_M_processor_2_00GHz,
259	#endif
260	#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz_h
261	&g_Entry_Intel_Xeon_X5482_3_20GHz,
262	#endif
263	#ifdef VBOX_CPUDB_Intel_Core2_X6800_2_93GHz_h
264	&g_Entry_Intel_Core2_X6800_2_93GHz,
265	#endif
266	#ifdef VBOX_CPUDB_Intel_Core2_T7600_2_33GHz_h
267	&g_Entry_Intel_Core2_T7600_2_33GHz,
268	#endif
269	#ifdef VBOX_CPUDB_Intel_Core_Duo_T2600_2_16GHz_h
270	&g_Entry_Intel_Core_Duo_T2600_2_16GHz,
271	#endif
272	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz_h
273	&g_Entry_Intel_Pentium_4_3_00GHz,
274	#endif
275	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz_h
276	&g_Entry_Intel_Pentium_4_3_00GHz,
277	#endif
278	/** @todo pentium, pentium mmx, pentium pro, pentium II, pentium III */
279	#ifdef VBOX_CPUDB_Intel_80486_h
280	&g_Entry_Intel_80486,
281	#endif
282	#ifdef VBOX_CPUDB_Intel_80386_h
283	&g_Entry_Intel_80386,
284	#endif
285	#ifdef VBOX_CPUDB_Intel_80286_h
286	&g_Entry_Intel_80286,
287	#endif
288	#ifdef VBOX_CPUDB_Intel_80186_h
289	&g_Entry_Intel_80186,
290	#endif
291	#ifdef VBOX_CPUDB_Intel_8086_h
292	&g_Entry_Intel_8086,
293	#endif
294
295	#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core_h
296	&g_Entry_AMD_FX_8150_Eight_Core,
297	#endif
298	#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T_h
299	&g_Entry_AMD_Phenom_II_X6_1100T,
300	#endif
301	#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384_h
302	&g_Entry_Quad_Core_AMD_Opteron_2384,
303	#endif
304	#ifdef VBOX_CPUDB_AMD_Athlon_64_X2_Dual_Core_4200_h
305	&g_Entry_AMD_Athlon_64_X2_Dual_Core_4200,
306	#endif
307	#ifdef VBOX_CPUDB_AMD_Athlon_64_3200_h
308	&g_Entry_AMD_Athlon_64_3200,
309	#endif
310
311	#ifdef VBOX_CPUDB_ZHAOXIN_KaiXian_KX_U5581_1_8GHz_h
312	&g_Entry_ZHAOXIN_KaiXian_KX_U5581_1_8GHz,
313	#endif
314
315	#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz_h
316	&g_Entry_VIA_QuadCore_L4700_1_2_GHz,
317	#endif
318
319	#ifdef VBOX_CPUDB_NEC_V20_h
320	&g_Entry_NEC_V20,
321	#endif
322	};
323
324
325
326	/**
327	* Binary search used by cpumR3MsrRangesInsert and has some special properties
328	* wrt to mismatches.
329	*
330	* @returns Insert location.
331	* @param paMsrRanges The MSR ranges to search.
332	* @param cMsrRanges The number of MSR ranges.
333	* @param uMsr What to search for.
334	*/
335	static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
336	{
337	if (!cMsrRanges)
338	return 0;
339
340	uint32_t iStart = 0;
341	uint32_t iLast = cMsrRanges - 1;
342	for (;;)
343	{
344	uint32_t i = iStart + (iLast - iStart + 1) / 2;
345	if ( uMsr >= paMsrRanges[i].uFirst
346	&& uMsr <= paMsrRanges[i].uLast)
347	return i;
348	if (uMsr < paMsrRanges[i].uFirst)
349	{
350	if (i <= iStart)
351	return i;
352	iLast = i - 1;
353	}
354	else
355	{
356	if (i >= iLast)
357	{
358	if (i < cMsrRanges)
359	i++;
360	return i;
361	}
362	iStart = i + 1;
363	}
364	}
365	}
366
367
368	/**
369	* Ensures that there is space for at least @a cNewRanges in the table,
370	* reallocating the table if necessary.
371	*
372	* @returns Pointer to the MSR ranges on success, NULL on failure. On failure
373	* @a *ppaMsrRanges is freed and set to NULL.
374	* @param pVM The cross context VM structure. If NULL,
375	* use the process heap, otherwise the VM's hyper heap.
376	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
377	* @param cMsrRanges The current number of ranges.
378	* @param cNewRanges The number of ranges to be added.
379	*/
380	static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
381	{
382	uint32_t cMsrRangesAllocated;
383	if (!pVM)
384	cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
385	else
386	{
387	/*
388	* We're using the hyper heap now, but when the range array was copied over to it from
389	* the host-context heap, we only copy the exact size and not the ensured size.
390	* See @bugref{7270}.
391	*/
392	cMsrRangesAllocated = cMsrRanges;
393	}
394	if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
395	{
396	void *pvNew;
397	uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
398	if (pVM)
399	{
400	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
401	Assert(cMsrRanges == pVM->cpum.s.GuestInfo.cMsrRanges);
402
403	size_t cb = cMsrRangesAllocated * sizeof(**ppaMsrRanges);
404	size_t cbNew = cNew * sizeof(**ppaMsrRanges);
405	int rc = MMR3HyperRealloc(pVM, *ppaMsrRanges, cb, 32, MM_TAG_CPUM_MSRS, cbNew, &pvNew);
406	if (RT_FAILURE(rc))
407	{
408	*ppaMsrRanges = NULL;
409	pVM->cpum.s.GuestInfo.paMsrRangesR0 = NIL_RTR0PTR;
410	LogRel(("CPUM: cpumR3MsrRangesEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
411	return NULL;
412	}
413	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
414	}
415	else
416	{
417	pvNew = RTMemRealloc(ppaMsrRanges, cNew sizeof(**ppaMsrRanges));
418	if (!pvNew)
419	{
420	RTMemFree(*ppaMsrRanges);
421	*ppaMsrRanges = NULL;
422	return NULL;
423	}
424	}
425	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
426	}
427
428	if (pVM)
429	{
430	/* Update the R0 pointer. */
431	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
432	pVM->cpum.s.GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, *ppaMsrRanges);
433	}
434
435	return *ppaMsrRanges;
436	}
437
438
439	/**
440	* Inserts a new MSR range in into an sorted MSR range array.
441	*
442	* If the new MSR range overlaps existing ranges, the existing ones will be
443	* adjusted/removed to fit in the new one.
444	*
445	* @returns VBox status code.
446	* @retval VINF_SUCCESS
447	* @retval VERR_NO_MEMORY
448	*
449	* @param pVM The cross context VM structure. If NULL,
450	* use the process heap, otherwise the VM's hyper heap.
451	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
452	* Must be NULL if using the hyper heap.
453	* @param pcMsrRanges The variable holding number of ranges. Must be NULL
454	* if using the hyper heap.
455	* @param pNewRange The new range.
456	*/
457	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange)
458	{
459	Assert(pNewRange->uLast >= pNewRange->uFirst);
460	Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
461	Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
462
463	/*
464	* Validate and use the VM's MSR ranges array if we are using the hyper heap.
465	*/
466	if (pVM)
467	{
468	AssertReturn(!ppaMsrRanges, VERR_INVALID_PARAMETER);
469	AssertReturn(!pcMsrRanges, VERR_INVALID_PARAMETER);
470
471	ppaMsrRanges = &pVM->cpum.s.GuestInfo.paMsrRangesR3;
472	pcMsrRanges = &pVM->cpum.s.GuestInfo.cMsrRanges;
473	}
474	else
475	{
476	AssertReturn(ppaMsrRanges, VERR_INVALID_POINTER);
477	AssertReturn(pcMsrRanges, VERR_INVALID_POINTER);
478	}
479
480	uint32_t cMsrRanges = *pcMsrRanges;
481	PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
482
483	/*
484	* Optimize the linear insertion case where we add new entries at the end.
485	*/
486	if ( cMsrRanges > 0
487	&& paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
488	{
489	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
490	if (!paMsrRanges)
491	return VERR_NO_MEMORY;
492	paMsrRanges[cMsrRanges] = *pNewRange;
493	*pcMsrRanges += 1;
494	}
495	else
496	{
497	uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
498	Assert(i == cMsrRanges \|\| pNewRange->uFirst <= paMsrRanges[i].uLast);
499	Assert(i == 0 \|\| pNewRange->uFirst > paMsrRanges[i - 1].uLast);
500
501	/*
502	* Adding an entirely new entry?
503	*/
504	if ( i >= cMsrRanges
505	\|\| pNewRange->uLast < paMsrRanges[i].uFirst)
506	{
507	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
508	if (!paMsrRanges)
509	return VERR_NO_MEMORY;
510	if (i < cMsrRanges)
511	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
512	paMsrRanges[i] = *pNewRange;
513	*pcMsrRanges += 1;
514	}
515	/*
516	* Replace existing entry?
517	*/
518	else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
519	&& pNewRange->uLast == paMsrRanges[i].uLast)
520	paMsrRanges[i] = *pNewRange;
521	/*
522	* Splitting an existing entry?
523	*/
524	else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
525	&& pNewRange->uLast < paMsrRanges[i].uLast)
526	{
527	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 2);
528	if (!paMsrRanges)
529	return VERR_NO_MEMORY;
530	if (i < cMsrRanges)
531	memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
532	paMsrRanges[i + 1] = *pNewRange;
533	paMsrRanges[i + 2] = paMsrRanges[i];
534	paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
535	paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
536	*pcMsrRanges += 2;
537	}
538	/*
539	* Complicated scenarios that can affect more than one range.
540	*
541	* The current code does not optimize memmove calls when replacing
542	* one or more existing ranges, because it's tedious to deal with and
543	* not expected to be a frequent usage scenario.
544	*/
545	else
546	{
547	/* Adjust start of first match? */
548	if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
549	&& pNewRange->uLast < paMsrRanges[i].uLast)
550	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
551	else
552	{
553	/* Adjust end of first match? */
554	if (pNewRange->uFirst > paMsrRanges[i].uFirst)
555	{
556	Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
557	paMsrRanges[i].uLast = pNewRange->uFirst - 1;
558	i++;
559	}
560	/* Replace the whole first match (lazy bird). */
561	else
562	{
563	if (i + 1 < cMsrRanges)
564	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
565	cMsrRanges = *pcMsrRanges -= 1;
566	}
567
568	/* Do the new range affect more ranges? */
569	while ( i < cMsrRanges
570	&& pNewRange->uLast >= paMsrRanges[i].uFirst)
571	{
572	if (pNewRange->uLast < paMsrRanges[i].uLast)
573	{
574	/* Adjust the start of it, then we're done. */
575	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
576	break;
577	}
578
579	/* Remove it entirely. */
580	if (i + 1 < cMsrRanges)
581	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
582	cMsrRanges = *pcMsrRanges -= 1;
583	}
584	}
585
586	/* Now, perform a normal insertion. */
587	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
588	if (!paMsrRanges)
589	return VERR_NO_MEMORY;
590	if (i < cMsrRanges)
591	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
592	paMsrRanges[i] = *pNewRange;
593	*pcMsrRanges += 1;
594	}
595	}
596
597	return VINF_SUCCESS;
598	}
599
600
601	/**
602	* Reconciles CPUID info with MSRs (selected ones).
603	*
604	* @returns VBox status code.
605	* @param pVM The cross context VM structure.
606	*/
607	int cpumR3MsrReconcileWithCpuId(PVM pVM)
608	{
609	PCCPUMMSRRANGE papToAdd[10];
610	uint32_t cToAdd = 0;
611
612	/*
613	* The IA32_FLUSH_CMD MSR was introduced in MCUs for CVS-2018-3646 and associates.
614	*/
615	if (pVM->cpum.s.GuestFeatures.fFlushCmd && !cpumLookupMsrRange(pVM, MSR_IA32_FLUSH_CMD))
616	{
617	static CPUMMSRRANGE const s_FlushCmd =
618	{
619	/.uFirst =/ MSR_IA32_FLUSH_CMD,
620	/.uLast =/ MSR_IA32_FLUSH_CMD,
621	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly,
622	/.enmWrFn =/ kCpumMsrWrFn_Ia32FlushCmd,
623	/.offCpumCpu =/ UINT16_MAX,
624	/.fReserved =/ 0,
625	/.uValue =/ 0,
626	/.fWrIgnMask =/ 0,
627	/.fWrGpMask =/ ~MSR_IA32_FLUSH_CMD_F_L1D,
628	/.szName = / "IA32_FLUSH_CMD"
629	};
630	papToAdd[cToAdd++] = &s_FlushCmd;
631	}
632
633	/*
634	* The MSR_IA32_ARCH_CAPABILITIES was introduced in various spectre MCUs, or at least
635	* documented in relation to such.
636	*/
637	if (pVM->cpum.s.GuestFeatures.fArchCap && !cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES))
638	{
639	static CPUMMSRRANGE const s_ArchCaps =
640	{
641	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES,
642	/.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
643	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities,
644	/.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
645	/.offCpumCpu =/ UINT16_MAX,
646	/.fReserved =/ 0,
647	/.uValue =/ 0,
648	/.fWrIgnMask =/ 0,
649	/.fWrGpMask =/ UINT64_MAX,
650	/.szName = / "IA32_ARCH_CAPABILITIES"
651	};
652	papToAdd[cToAdd++] = &s_ArchCaps;
653	}
654
655	/*
656	* Do the adding.
657	*/
658	for (uint32_t i = 0; i < cToAdd; i++)
659	{
660	PCCPUMMSRRANGE pRange = papToAdd[i];
661	LogRel(("CPUM: MSR/CPUID reconciliation insert: %#010x %s\n", pRange->uFirst, pRange->szName));
662	int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
663	pRange);
664	if (RT_FAILURE(rc))
665	return rc;
666	}
667	return VINF_SUCCESS;
668	}
669
670
671	/**
672	* Worker for cpumR3MsrApplyFudge that applies one table.
673	*
674	* @returns VBox status code.
675	* @param pVM The cross context VM structure.
676	* @param paRanges Array of MSRs to fudge.
677	* @param cRanges Number of MSRs in the array.
678	*/
679	static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
680	{
681	for (uint32_t i = 0; i < cRanges; i++)
682	if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
683	{
684	LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
685	int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
686	&paRanges[i]);
687	if (RT_FAILURE(rc))
688	return rc;
689	}
690	return VINF_SUCCESS;
691	}
692
693
694	/**
695	* Fudges the MSRs that guest are known to access in some odd cases.
696	*
697	* A typical example is a VM that has been moved between different hosts where
698	* for instance the cpu vendor differs.
699	*
700	* Another example is older CPU profiles (e.g. Atom Bonnet) for newer CPUs (e.g.
701	* Atom Silvermont), where features reported thru CPUID aren't present in the
702	* MSRs (e.g. AMD64_TSC_AUX).
703	*
704	*
705	* @returns VBox status code.
706	* @param pVM The cross context VM structure.
707	*/
708	int cpumR3MsrApplyFudge(PVM pVM)
709	{
710	/*
711	* Basic.
712	*/
713	static CPUMMSRRANGE const s_aFudgeMsrs[] =
714	{
715	MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
716	MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
717	MVO(0x00000017, "IA32_PLATFORM_ID", 0),
718	MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
719	MVI(0x0000008b, "BIOS_SIGN", 0),
720	MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
721	MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
722	MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
723	MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
724	MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
725	MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
726	MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
727	MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
728	MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
729	MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
730	MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
731	MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
732	};
733	int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
734	AssertLogRelRCReturn(rc, rc);
735
736	/*
737	* XP might mistake opterons and other newer CPUs for P4s.
738	*/
739	if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
740	{
741	static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
742	{
743	MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
744	};
745	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
746	AssertLogRelRCReturn(rc, rc);
747	}
748
749	if (pVM->cpum.s.GuestFeatures.fRdTscP)
750	{
751	static CPUMMSRRANGE const s_aRdTscPFudgeMsrs[] =
752	{
753	MFX(0xc0000103, "AMD64_TSC_AUX", Amd64TscAux, Amd64TscAux, 0, 0, ~(uint64_t)UINT32_MAX),
754	};
755	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aRdTscPFudgeMsrs[0], RT_ELEMENTS(s_aRdTscPFudgeMsrs));
756	AssertLogRelRCReturn(rc, rc);
757	}
758
759	return rc;
760	}
761
762
763	/**
764	* Do we consider @a enmConsider a better match for @a enmTarget than
765	* @a enmFound?
766	*
767	* Only called when @a enmConsider isn't exactly what we're looking for.
768	*
769	* @returns true/false.
770	* @param enmConsider The new microarch to consider.
771	* @param enmTarget The target microarch.
772	* @param enmFound The best microarch match we've found thus far.
773	*/
774	DECLINLINE(bool) cpumR3DbIsBetterMarchMatch(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
775	{
776	Assert(enmConsider != enmTarget);
777
778	/*
779	* If we've got an march match, don't bother with enmConsider.
780	*/
781	if (enmFound == enmTarget)
782	return false;
783
784	/*
785	* Found is below: Pick 'consider' if it's closer to the target or above it.
786	*/
787	if (enmFound < enmTarget)
788	return enmConsider > enmFound;
789
790	/*
791	* Found is above: Pick 'consider' if it's also above (paranoia: or equal)
792	* and but closer to the target.
793	*/
794	return enmConsider >= enmTarget && enmConsider < enmFound;
795	}
796
797
798	/**
799	* Do we consider @a enmConsider a better match for @a enmTarget than
800	* @a enmFound?
801	*
802	* Only called for intel family 06h CPUs.
803	*
804	* @returns true/false.
805	* @param enmConsider The new microarch to consider.
806	* @param enmTarget The target microarch.
807	* @param enmFound The best microarch match we've found thus far.
808	*/
809	static bool cpumR3DbIsBetterIntelFam06Match(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
810	{
811	/* Check intel family 06h claims. */
812	AssertReturn(enmConsider >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmConsider <= kCpumMicroarch_Intel_P6_Core_Atom_End,
813	false);
814	AssertReturn(enmTarget >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmTarget <= kCpumMicroarch_Intel_P6_Core_Atom_End,
815	false);
816
817	/* Put matches out of the way. */
818	if (enmConsider == enmTarget)
819	return true;
820	if (enmFound == enmTarget)
821	return false;
822
823	/* If found isn't a family 06h march, whatever we're considering must be a better choice. */
824	if ( enmFound < kCpumMicroarch_Intel_P6_Core_Atom_First
825	\|\| enmFound > kCpumMicroarch_Intel_P6_Core_Atom_End)
826	return true;
827
828	/*
829	* The family 06h stuff is split into three categories:
830	* - Common P6 heritage
831	* - Core
832	* - Atom
833	*
834	* Determin which of the three arguments are Atom marchs, because that's
835	* all we need to make the right choice.
836	*/
837	bool const fConsiderAtom = enmConsider >= kCpumMicroarch_Intel_Atom_First;
838	bool const fTargetAtom = enmTarget >= kCpumMicroarch_Intel_Atom_First;
839	bool const fFoundAtom = enmFound >= kCpumMicroarch_Intel_Atom_First;
840
841	/*
842	* Want atom:
843	*/
844	if (fTargetAtom)
845	{
846	/* Pick the atom if we've got one of each.*/
847	if (fConsiderAtom != fFoundAtom)
848	return fConsiderAtom;
849	/* If we haven't got any atoms under consideration, pick a P6 or the earlier core.
850	Note! Not entirely sure Dothan is the best choice, but it'll do for now. */
851	if (!fConsiderAtom)
852	{
853	if (enmConsider > enmFound)
854	return enmConsider <= kCpumMicroarch_Intel_P6_M_Dothan;
855	return enmFound > kCpumMicroarch_Intel_P6_M_Dothan;
856	}
857	/* else: same category, default comparison rules. */
858	Assert(fConsiderAtom && fFoundAtom);
859	}
860	/*
861	* Want non-atom:
862	*/
863	/* Pick the non-atom if we've got one of each. */
864	else if (fConsiderAtom != fFoundAtom)
865	return fFoundAtom;
866	/* If we've only got atoms under consideration, pick the older one just to pick something. */
867	else if (fConsiderAtom)
868	return enmConsider < enmFound;
869	else
870	Assert(!fConsiderAtom && !fFoundAtom);
871
872	/*
873	* Same basic category. Do same compare as caller.
874	*/
875	return cpumR3DbIsBetterMarchMatch(enmConsider, enmTarget, enmFound);
876	}
877
878
879	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
880	{
881	CPUMDBENTRY const *pEntry = NULL;
882	int rc;
883
884	if (!strcmp(pszName, "host"))
885	{
886	/*
887	* Create a CPU database entry for the host CPU. This means getting
888	* the CPUID bits from the real CPU and grabbing the closest matching
889	* database entry for MSRs.
890	*/
891	rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
892	if (RT_FAILURE(rc))
893	return rc;
894	rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
895	if (RT_FAILURE(rc))
896	return rc;
897	pInfo->fMxCsrMask = CPUMR3DeterminHostMxCsrMask();
898
899	/* Lookup database entry for MSRs. */
900	CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
901	pInfo->paCpuIdLeavesR3[0].uEbx,
902	pInfo->paCpuIdLeavesR3[0].uEcx,
903	pInfo->paCpuIdLeavesR3[0].uEdx);
904	uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
905	uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
906	uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
907	uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
908	CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
909
910	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
911	{
912	CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
913	if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
914	{
915	/* Match against Family, Microarch, model and stepping. Except
916	for family, always match the closer with preference given to
917	the later/older ones. */
918	if (pCur->uFamily == uFamily)
919	{
920	if (pCur->enmMicroarch == enmMicroarch)
921	{
922	if (pCur->uModel == uModel)
923	{
924	if (pCur->uStepping == uStepping)
925	{
926	/* Perfect match. */
927	pEntry = pCur;
928	break;
929	}
930
931	if ( !pEntry
932	\|\| pEntry->uModel != uModel
933	\|\| pEntry->enmMicroarch != enmMicroarch
934	\|\| pEntry->uFamily != uFamily)
935	pEntry = pCur;
936	else if ( pCur->uStepping >= uStepping
937	? pCur->uStepping < pEntry->uStepping \|\| pEntry->uStepping < uStepping
938	: pCur->uStepping > pEntry->uStepping)
939	pEntry = pCur;
940	}
941	else if ( !pEntry
942	\|\| pEntry->enmMicroarch != enmMicroarch
943	\|\| pEntry->uFamily != uFamily)
944	pEntry = pCur;
945	else if ( pCur->uModel >= uModel
946	? pCur->uModel < pEntry->uModel \|\| pEntry->uModel < uModel
947	: pCur->uModel > pEntry->uModel)
948	pEntry = pCur;
949	}
950	else if ( !pEntry
951	\|\| pEntry->uFamily != uFamily)
952	pEntry = pCur;
953	/* Special march matching rules applies to intel family 06h. */
954	else if ( enmVendor == CPUMCPUVENDOR_INTEL
955	&& uFamily == 6
956	? cpumR3DbIsBetterIntelFam06Match(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch)
957	: cpumR3DbIsBetterMarchMatch(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch))
958	pEntry = pCur;
959	}
960	/* We don't do closeness matching on family, we use the first
961	entry for the CPU vendor instead. (P4 workaround.) */
962	else if (!pEntry)
963	pEntry = pCur;
964	}
965	}
966
967	if (pEntry)
968	LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
969	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
970	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
971	pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
972	else
973	{
974	pEntry = g_apCpumDbEntries[0];
975	LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'\n",
976	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
977	pEntry->pszName));
978	}
979	}
980	else
981	{
982	/*
983	* We're supposed to be emulating a specific CPU that is included in
984	* our CPU database. The CPUID tables needs to be copied onto the
985	* heap so the caller can modify them and so they can be freed like
986	* in the host case above.
987	*/
988	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
989	if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
990	{
991	pEntry = g_apCpumDbEntries[i];
992	break;
993	}
994	if (!pEntry)
995	{
996	LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
997	return VERR_CPUM_DB_CPU_NOT_FOUND;
998	}
999
1000	pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
1001	if (pEntry->cCpuIdLeaves)
1002	{
1003	/* Must allocate a multiple of 16 here, matching cpumR3CpuIdEnsureSpace. */
1004	size_t cbExtra = sizeof(pEntry->paCpuIdLeaves[0]) * (RT_ALIGN(pEntry->cCpuIdLeaves, 16) - pEntry->cCpuIdLeaves);
1005	pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDupEx(pEntry->paCpuIdLeaves,
1006	sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves,
1007	cbExtra);
1008	if (!pInfo->paCpuIdLeavesR3)
1009	return VERR_NO_MEMORY;
1010	}
1011	else
1012	pInfo->paCpuIdLeavesR3 = NULL;
1013
1014	pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
1015	pInfo->DefCpuId = pEntry->DefUnknownCpuId;
1016	pInfo->fMxCsrMask = pEntry->fMxCsrMask;
1017
1018	LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
1019	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
1020	pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
1021	}
1022
1023	pInfo->fMsrMask = pEntry->fMsrMask;
1024	pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
1025	pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
1026	pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
1027	pInfo->paMsrRangesR0 = NIL_RTR0PTR;
1028
1029	/*
1030	* Copy the MSR range.
1031	*/
1032	uint32_t cMsrs = 0;
1033	PCPUMMSRRANGE paMsrs = NULL;
1034
1035	PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
1036	uint32_t cLeft = pEntry->cMsrRanges;
1037	while (cLeft-- > 0)
1038	{
1039	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &paMsrs, &cMsrs, pCurMsr);
1040	if (RT_FAILURE(rc))
1041	{
1042	Assert(!paMsrs); /* The above function frees this. */
1043	RTMemFree(pInfo->paCpuIdLeavesR3);
1044	pInfo->paCpuIdLeavesR3 = NULL;
1045	return rc;
1046	}
1047	pCurMsr++;
1048	}
1049
1050	pInfo->paMsrRangesR3 = paMsrs;
1051	pInfo->cMsrRanges = cMsrs;
1052	return VINF_SUCCESS;
1053	}
1054
1055
1056	/**
1057	* Insert an MSR range into the VM.
1058	*
1059	* If the new MSR range overlaps existing ranges, the existing ones will be
1060	* adjusted/removed to fit in the new one.
1061	*
1062	* @returns VBox status code.
1063	* @param pVM The cross context VM structure.
1064	* @param pNewRange Pointer to the MSR range being inserted.
1065	*/
1066	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange)
1067	{
1068	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1069	AssertReturn(pNewRange, VERR_INVALID_PARAMETER);
1070
1071	return cpumR3MsrRangesInsert(pVM, NULL /* ppaMsrRanges /, NULL / pcMsrRanges */, pNewRange);
1072	}
1073
1074
1075	/**
1076	* Register statistics for the MSRs.
1077	*
1078	* This must not be called before the MSRs have been finalized and moved to the
1079	* hyper heap.
1080	*
1081	* @returns VBox status code.
1082	* @param pVM The cross context VM structure.
1083	*/
1084	int cpumR3MsrRegStats(PVM pVM)
1085	{
1086	/*
1087	* Global statistics.
1088	*/
1089	PCPUM pCpum = &pVM->cpum.s;
1090	STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
1091	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
1092	STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
1093	STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
1094	STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
1095	STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
1096	STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
1097	STAMUNIT_OCCURENCES, "All WRMSRs making it to CPUM.");
1098	STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
1099	STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
1100	STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
1101	STAMUNIT_OCCURENCES, "Writing of ignored bits.");
1102	STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
1103	STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
1104
1105
1106	# ifdef VBOX_WITH_STATISTICS
1107	/*
1108	* Per range.
1109	*/
1110	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
1111	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
1112	for (uint32_t i = 0; i < cRanges; i++)
1113	{
1114	char szName[160];
1115	ssize_t cchName;
1116
1117	if (paRanges[i].uFirst == paRanges[i].uLast)
1118	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
1119	paRanges[i].uFirst, paRanges[i].szName);
1120	else
1121	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
1122	paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
1123
1124	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
1125	STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
1126
1127	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
1128	STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
1129
1130	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
1131	STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
1132
1133	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
1134	STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
1135	}
1136	# endif /* VBOX_WITH_STATISTICS */
1137
1138	return VINF_SUCCESS;
1139	}
1140
1141	#endif /* !CPUM_DB_STANDALONE */
1142

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 80239

Download in other formats: