CPUMR3Db.cpp@ 80386

Last change on this file since 80386 was 80333, checked in by vboxsync, 5 years ago
VMM: Eliminating the VBOX_BUGREF_9217_PART_I preprocessor macro. bugref:9217
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1	/* $Id: CPUMR3Db.cpp 80333 2019-08-16 20:28:38Z vboxsync $ */
2	/** @file
3	* CPUM - CPU database part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/mm.h>
27
28	#include <VBox/err.h>
29	#include <iprt/asm-amd64-x86.h>
30	#include <iprt/mem.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Structures and Typedefs *
36	*********************************************************************************************************************************/
37	typedef struct CPUMDBENTRY
38	{
39	/** The CPU name. */
40	const char *pszName;
41	/** The full CPU name. */
42	const char *pszFullName;
43	/** The CPU vendor (CPUMCPUVENDOR). */
44	uint8_t enmVendor;
45	/** The CPU family. */
46	uint8_t uFamily;
47	/** The CPU model. */
48	uint8_t uModel;
49	/** The CPU stepping. */
50	uint8_t uStepping;
51	/** The microarchitecture. */
52	CPUMMICROARCH enmMicroarch;
53	/** Scalable bus frequency used for reporting other frequencies. */
54	uint64_t uScalableBusFreq;
55	/** Flags - CPUDB_F_XXX. */
56	uint32_t fFlags;
57	/** The maximum physical address with of the CPU. This should correspond to
58	* the value in CPUID leaf 0x80000008 when present. */
59	uint8_t cMaxPhysAddrWidth;
60	/** The MXCSR mask. */
61	uint32_t fMxCsrMask;
62	/** Pointer to an array of CPUID leaves. */
63	PCCPUMCPUIDLEAF paCpuIdLeaves;
64	/** The number of CPUID leaves in the array paCpuIdLeaves points to. */
65	uint32_t cCpuIdLeaves;
66	/** The method used to deal with unknown CPUID leaves. */
67	CPUMUNKNOWNCPUID enmUnknownCpuId;
68	/** The default unknown CPUID value. */
69	CPUMCPUID DefUnknownCpuId;
70
71	/** MSR mask. Several microarchitectures ignore the higher bits of ECX in
72	* the RDMSR and WRMSR instructions. */
73	uint32_t fMsrMask;
74
75	/** The number of ranges in the table pointed to b paMsrRanges. */
76	uint32_t cMsrRanges;
77	/** MSR ranges for this CPU. */
78	PCCPUMMSRRANGE paMsrRanges;
79	} CPUMDBENTRY;
80
81
82	/*********************************************************************************************************************************
83	* Defined Constants And Macros *
84	*********************************************************************************************************************************/
85	/** @name CPUDB_F_XXX - CPUDBENTRY::fFlags
86	* @{ */
87	/** Should execute all in IEM.
88	* @todo Implement this - currently done in Main... */
89	#define CPUDB_F_EXECUTE_ALL_IN_IEM RT_BIT_32(0)
90	/** @} */
91
92
93	/** @def NULL_ALONE
94	* For eliminating an unnecessary data dependency in standalone builds (for
95	* VBoxSVC). */
96	/** @def ZERO_ALONE
97	* For eliminating an unnecessary data size dependency in standalone builds (for
98	* VBoxSVC). */
99	#ifndef CPUM_DB_STANDALONE
100	# define NULL_ALONE(a_aTable) a_aTable
101	# define ZERO_ALONE(a_cTable) a_cTable
102	#else
103	# define NULL_ALONE(a_aTable) NULL
104	# define ZERO_ALONE(a_cTable) 0
105	#endif
106
107
108	/** @name Short macros for the MSR range entries.
109	*
110	* These are rather cryptic, but this is to reduce the attack on the right
111	* margin.
112	*
113	* @{ */
114	/** Alias one MSR onto another (a_uTarget). */
115	#define MAL(a_uMsr, a_szName, a_uTarget) \
116	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
117	/** Functions handles everything. */
118	#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
119	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
120	/** Functions handles everything, with GP mask. */
121	#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
122	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
123	/** Function handlers, read-only. */
124	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
125	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
126	/** Function handlers, ignore all writes. */
127	#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
128	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
129	/** Function handlers, with value. */
130	#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
131	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
132	/** Function handlers, with write ignore mask. */
133	#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
134	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
135	/** Function handlers, extended version. */
136	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
137	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
138	/** Function handlers, with CPUMCPU storage variable. */
139	#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
140	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
141	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
142	/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
143	#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
144	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
145	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
146	/** Read-only fixed value. */
147	#define MVO(a_uMsr, a_szName, a_uValue) \
148	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
149	/** Read-only fixed value, ignores all writes. */
150	#define MVI(a_uMsr, a_szName, a_uValue) \
151	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
152	/** Read fixed value, ignore writes outside GP mask. */
153	#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
154	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
155	/** Read fixed value, extended version with both GP and ignore masks. */
156	#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
157	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
158	/** The short form, no CPUM backing. */
159	#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
160	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
161	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
162
163	/** Range: Functions handles everything. */
164	#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
165	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
166	/** Range: Read fixed value, read-only. */
167	#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
168	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
169	/** Range: Read fixed value, ignore writes. */
170	#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
171	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
172	/** Range: The short form, no CPUM backing. */
173	#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
174	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
175	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
176
177	/** Internal form used by the macros. */
178	#ifdef VBOX_WITH_STATISTICS
179	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
180	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
181	{ 0 }, { 0 }, { 0 }, { 0 } }
182	#else
183	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
184	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
185	#endif
186	/** @} */
187
188	#ifndef CPUM_DB_STANDALONE
189
190	#include "cpus/Intel_Core_i7_6700K.h"
191	#include "cpus/Intel_Core_i7_5600U.h"
192	#include "cpus/Intel_Core_i7_3960X.h"
193	#include "cpus/Intel_Core_i5_3570.h"
194	#include "cpus/Intel_Core_i7_2635QM.h"
195	#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
196	#include "cpus/Intel_Core2_X6800_2_93GHz.h"
197	#include "cpus/Intel_Core2_T7600_2_33GHz.h"
198	#include "cpus/Intel_Core_Duo_T2600_2_16GHz.h"
199	#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
200	#include "cpus/Intel_Pentium_4_3_00GHz.h"
201	#include "cpus/Intel_Pentium_N3530_2_16GHz.h"
202	#include "cpus/Intel_Atom_330_1_60GHz.h"
203	#include "cpus/Intel_80486.h"
204	#include "cpus/Intel_80386.h"
205	#include "cpus/Intel_80286.h"
206	#include "cpus/Intel_80186.h"
207	#include "cpus/Intel_8086.h"
208
209	#include "cpus/AMD_FX_8150_Eight_Core.h"
210	#include "cpus/AMD_Phenom_II_X6_1100T.h"
211	#include "cpus/Quad_Core_AMD_Opteron_2384.h"
212	#include "cpus/AMD_Athlon_64_X2_Dual_Core_4200.h"
213	#include "cpus/AMD_Athlon_64_3200.h"
214
215	#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
216
217	#include "cpus/ZHAOXIN_KaiXian_KX_U5581_1_8GHz.h"
218
219
220
221	/**
222	* The database entries.
223	*
224	* 1. The first entry is special. It is the fallback for unknown
225	* processors. Thus, it better be pretty representative.
226	*
227	* 2. The first entry for a CPU vendor is likewise important as it is
228	* the default entry for that vendor.
229	*
230	* Generally we put the most recent CPUs first, since these tend to have the
231	* most complicated and backwards compatible list of MSRs.
232	*/
233	static CPUMDBENTRY const * const g_apCpumDbEntries[] =
234	{
235	#ifdef VBOX_CPUDB_Intel_Core_i7_6700K_h
236	&g_Entry_Intel_Core_i7_6700K,
237	#endif
238	#ifdef VBOX_CPUDB_Intel_Core_i7_5600U_h
239	&g_Entry_Intel_Core_i7_5600U,
240	#endif
241	#ifdef VBOX_CPUDB_Intel_Core_i5_3570_h
242	&g_Entry_Intel_Core_i5_3570,
243	#endif
244	#ifdef VBOX_CPUDB_Intel_Core_i7_3960X_h
245	&g_Entry_Intel_Core_i7_3960X,
246	#endif
247	#ifdef VBOX_CPUDB_Intel_Core_i7_2635QM_h
248	&g_Entry_Intel_Core_i7_2635QM,
249	#endif
250	#ifdef VBOX_CPUDB_Intel_Pentium_N3530_2_16GHz_h
251	&g_Entry_Intel_Pentium_N3530_2_16GHz,
252	#endif
253	#ifdef VBOX_CPUDB_Intel_Atom_330_1_60GHz_h
254	&g_Entry_Intel_Atom_330_1_60GHz,
255	#endif
256	#ifdef VBOX_CPUDB_Intel_Pentium_M_processor_2_00GHz_h
257	&g_Entry_Intel_Pentium_M_processor_2_00GHz,
258	#endif
259	#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz_h
260	&g_Entry_Intel_Xeon_X5482_3_20GHz,
261	#endif
262	#ifdef VBOX_CPUDB_Intel_Core2_X6800_2_93GHz_h
263	&g_Entry_Intel_Core2_X6800_2_93GHz,
264	#endif
265	#ifdef VBOX_CPUDB_Intel_Core2_T7600_2_33GHz_h
266	&g_Entry_Intel_Core2_T7600_2_33GHz,
267	#endif
268	#ifdef VBOX_CPUDB_Intel_Core_Duo_T2600_2_16GHz_h
269	&g_Entry_Intel_Core_Duo_T2600_2_16GHz,
270	#endif
271	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz_h
272	&g_Entry_Intel_Pentium_4_3_00GHz,
273	#endif
274	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz_h
275	&g_Entry_Intel_Pentium_4_3_00GHz,
276	#endif
277	/** @todo pentium, pentium mmx, pentium pro, pentium II, pentium III */
278	#ifdef VBOX_CPUDB_Intel_80486_h
279	&g_Entry_Intel_80486,
280	#endif
281	#ifdef VBOX_CPUDB_Intel_80386_h
282	&g_Entry_Intel_80386,
283	#endif
284	#ifdef VBOX_CPUDB_Intel_80286_h
285	&g_Entry_Intel_80286,
286	#endif
287	#ifdef VBOX_CPUDB_Intel_80186_h
288	&g_Entry_Intel_80186,
289	#endif
290	#ifdef VBOX_CPUDB_Intel_8086_h
291	&g_Entry_Intel_8086,
292	#endif
293
294	#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core_h
295	&g_Entry_AMD_FX_8150_Eight_Core,
296	#endif
297	#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T_h
298	&g_Entry_AMD_Phenom_II_X6_1100T,
299	#endif
300	#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384_h
301	&g_Entry_Quad_Core_AMD_Opteron_2384,
302	#endif
303	#ifdef VBOX_CPUDB_AMD_Athlon_64_X2_Dual_Core_4200_h
304	&g_Entry_AMD_Athlon_64_X2_Dual_Core_4200,
305	#endif
306	#ifdef VBOX_CPUDB_AMD_Athlon_64_3200_h
307	&g_Entry_AMD_Athlon_64_3200,
308	#endif
309
310	#ifdef VBOX_CPUDB_ZHAOXIN_KaiXian_KX_U5581_1_8GHz_h
311	&g_Entry_ZHAOXIN_KaiXian_KX_U5581_1_8GHz,
312	#endif
313
314	#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz_h
315	&g_Entry_VIA_QuadCore_L4700_1_2_GHz,
316	#endif
317
318	#ifdef VBOX_CPUDB_NEC_V20_h
319	&g_Entry_NEC_V20,
320	#endif
321	};
322
323
324
325	/**
326	* Binary search used by cpumR3MsrRangesInsert and has some special properties
327	* wrt to mismatches.
328	*
329	* @returns Insert location.
330	* @param paMsrRanges The MSR ranges to search.
331	* @param cMsrRanges The number of MSR ranges.
332	* @param uMsr What to search for.
333	*/
334	static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
335	{
336	if (!cMsrRanges)
337	return 0;
338
339	uint32_t iStart = 0;
340	uint32_t iLast = cMsrRanges - 1;
341	for (;;)
342	{
343	uint32_t i = iStart + (iLast - iStart + 1) / 2;
344	if ( uMsr >= paMsrRanges[i].uFirst
345	&& uMsr <= paMsrRanges[i].uLast)
346	return i;
347	if (uMsr < paMsrRanges[i].uFirst)
348	{
349	if (i <= iStart)
350	return i;
351	iLast = i - 1;
352	}
353	else
354	{
355	if (i >= iLast)
356	{
357	if (i < cMsrRanges)
358	i++;
359	return i;
360	}
361	iStart = i + 1;
362	}
363	}
364	}
365
366
367	/**
368	* Ensures that there is space for at least @a cNewRanges in the table,
369	* reallocating the table if necessary.
370	*
371	* @returns Pointer to the MSR ranges on success, NULL on failure. On failure
372	* @a *ppaMsrRanges is freed and set to NULL.
373	* @param pVM The cross context VM structure. If NULL,
374	* use the process heap, otherwise the VM's hyper heap.
375	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
376	* @param cMsrRanges The current number of ranges.
377	* @param cNewRanges The number of ranges to be added.
378	*/
379	static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
380	{
381	uint32_t cMsrRangesAllocated;
382	if (!pVM)
383	cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
384	else
385	{
386	/*
387	* We're using the hyper heap now, but when the range array was copied over to it from
388	* the host-context heap, we only copy the exact size and not the ensured size.
389	* See @bugref{7270}.
390	*/
391	cMsrRangesAllocated = cMsrRanges;
392	}
393	if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
394	{
395	void *pvNew;
396	uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
397	if (pVM)
398	{
399	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
400	Assert(cMsrRanges == pVM->cpum.s.GuestInfo.cMsrRanges);
401
402	size_t cb = cMsrRangesAllocated * sizeof(**ppaMsrRanges);
403	size_t cbNew = cNew * sizeof(**ppaMsrRanges);
404	int rc = MMR3HyperRealloc(pVM, *ppaMsrRanges, cb, 32, MM_TAG_CPUM_MSRS, cbNew, &pvNew);
405	if (RT_FAILURE(rc))
406	{
407	*ppaMsrRanges = NULL;
408	pVM->cpum.s.GuestInfo.paMsrRangesR0 = NIL_RTR0PTR;
409	LogRel(("CPUM: cpumR3MsrRangesEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
410	return NULL;
411	}
412	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
413	}
414	else
415	{
416	pvNew = RTMemRealloc(ppaMsrRanges, cNew sizeof(**ppaMsrRanges));
417	if (!pvNew)
418	{
419	RTMemFree(*ppaMsrRanges);
420	*ppaMsrRanges = NULL;
421	return NULL;
422	}
423	}
424	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
425	}
426
427	if (pVM)
428	{
429	/* Update the R0 pointer. */
430	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
431	pVM->cpum.s.GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, *ppaMsrRanges);
432	}
433
434	return *ppaMsrRanges;
435	}
436
437
438	/**
439	* Inserts a new MSR range in into an sorted MSR range array.
440	*
441	* If the new MSR range overlaps existing ranges, the existing ones will be
442	* adjusted/removed to fit in the new one.
443	*
444	* @returns VBox status code.
445	* @retval VINF_SUCCESS
446	* @retval VERR_NO_MEMORY
447	*
448	* @param pVM The cross context VM structure. If NULL,
449	* use the process heap, otherwise the VM's hyper heap.
450	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
451	* Must be NULL if using the hyper heap.
452	* @param pcMsrRanges The variable holding number of ranges. Must be NULL
453	* if using the hyper heap.
454	* @param pNewRange The new range.
455	*/
456	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange)
457	{
458	Assert(pNewRange->uLast >= pNewRange->uFirst);
459	Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
460	Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
461
462	/*
463	* Validate and use the VM's MSR ranges array if we are using the hyper heap.
464	*/
465	if (pVM)
466	{
467	AssertReturn(!ppaMsrRanges, VERR_INVALID_PARAMETER);
468	AssertReturn(!pcMsrRanges, VERR_INVALID_PARAMETER);
469
470	ppaMsrRanges = &pVM->cpum.s.GuestInfo.paMsrRangesR3;
471	pcMsrRanges = &pVM->cpum.s.GuestInfo.cMsrRanges;
472	}
473	else
474	{
475	AssertReturn(ppaMsrRanges, VERR_INVALID_POINTER);
476	AssertReturn(pcMsrRanges, VERR_INVALID_POINTER);
477	}
478
479	uint32_t cMsrRanges = *pcMsrRanges;
480	PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
481
482	/*
483	* Optimize the linear insertion case where we add new entries at the end.
484	*/
485	if ( cMsrRanges > 0
486	&& paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
487	{
488	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
489	if (!paMsrRanges)
490	return VERR_NO_MEMORY;
491	paMsrRanges[cMsrRanges] = *pNewRange;
492	*pcMsrRanges += 1;
493	}
494	else
495	{
496	uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
497	Assert(i == cMsrRanges \|\| pNewRange->uFirst <= paMsrRanges[i].uLast);
498	Assert(i == 0 \|\| pNewRange->uFirst > paMsrRanges[i - 1].uLast);
499
500	/*
501	* Adding an entirely new entry?
502	*/
503	if ( i >= cMsrRanges
504	\|\| pNewRange->uLast < paMsrRanges[i].uFirst)
505	{
506	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
507	if (!paMsrRanges)
508	return VERR_NO_MEMORY;
509	if (i < cMsrRanges)
510	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
511	paMsrRanges[i] = *pNewRange;
512	*pcMsrRanges += 1;
513	}
514	/*
515	* Replace existing entry?
516	*/
517	else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
518	&& pNewRange->uLast == paMsrRanges[i].uLast)
519	paMsrRanges[i] = *pNewRange;
520	/*
521	* Splitting an existing entry?
522	*/
523	else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
524	&& pNewRange->uLast < paMsrRanges[i].uLast)
525	{
526	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 2);
527	if (!paMsrRanges)
528	return VERR_NO_MEMORY;
529	if (i < cMsrRanges)
530	memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
531	paMsrRanges[i + 1] = *pNewRange;
532	paMsrRanges[i + 2] = paMsrRanges[i];
533	paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
534	paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
535	*pcMsrRanges += 2;
536	}
537	/*
538	* Complicated scenarios that can affect more than one range.
539	*
540	* The current code does not optimize memmove calls when replacing
541	* one or more existing ranges, because it's tedious to deal with and
542	* not expected to be a frequent usage scenario.
543	*/
544	else
545	{
546	/* Adjust start of first match? */
547	if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
548	&& pNewRange->uLast < paMsrRanges[i].uLast)
549	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
550	else
551	{
552	/* Adjust end of first match? */
553	if (pNewRange->uFirst > paMsrRanges[i].uFirst)
554	{
555	Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
556	paMsrRanges[i].uLast = pNewRange->uFirst - 1;
557	i++;
558	}
559	/* Replace the whole first match (lazy bird). */
560	else
561	{
562	if (i + 1 < cMsrRanges)
563	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
564	cMsrRanges = *pcMsrRanges -= 1;
565	}
566
567	/* Do the new range affect more ranges? */
568	while ( i < cMsrRanges
569	&& pNewRange->uLast >= paMsrRanges[i].uFirst)
570	{
571	if (pNewRange->uLast < paMsrRanges[i].uLast)
572	{
573	/* Adjust the start of it, then we're done. */
574	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
575	break;
576	}
577
578	/* Remove it entirely. */
579	if (i + 1 < cMsrRanges)
580	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
581	cMsrRanges = *pcMsrRanges -= 1;
582	}
583	}
584
585	/* Now, perform a normal insertion. */
586	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
587	if (!paMsrRanges)
588	return VERR_NO_MEMORY;
589	if (i < cMsrRanges)
590	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
591	paMsrRanges[i] = *pNewRange;
592	*pcMsrRanges += 1;
593	}
594	}
595
596	return VINF_SUCCESS;
597	}
598
599
600	/**
601	* Reconciles CPUID info with MSRs (selected ones).
602	*
603	* @returns VBox status code.
604	* @param pVM The cross context VM structure.
605	*/
606	int cpumR3MsrReconcileWithCpuId(PVM pVM)
607	{
608	PCCPUMMSRRANGE papToAdd[10];
609	uint32_t cToAdd = 0;
610
611	/*
612	* The IA32_FLUSH_CMD MSR was introduced in MCUs for CVS-2018-3646 and associates.
613	*/
614	if (pVM->cpum.s.GuestFeatures.fFlushCmd && !cpumLookupMsrRange(pVM, MSR_IA32_FLUSH_CMD))
615	{
616	static CPUMMSRRANGE const s_FlushCmd =
617	{
618	/.uFirst =/ MSR_IA32_FLUSH_CMD,
619	/.uLast =/ MSR_IA32_FLUSH_CMD,
620	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly,
621	/.enmWrFn =/ kCpumMsrWrFn_Ia32FlushCmd,
622	/.offCpumCpu =/ UINT16_MAX,
623	/.fReserved =/ 0,
624	/.uValue =/ 0,
625	/.fWrIgnMask =/ 0,
626	/.fWrGpMask =/ ~MSR_IA32_FLUSH_CMD_F_L1D,
627	/.szName = / "IA32_FLUSH_CMD"
628	};
629	papToAdd[cToAdd++] = &s_FlushCmd;
630	}
631
632	/*
633	* The MSR_IA32_ARCH_CAPABILITIES was introduced in various spectre MCUs, or at least
634	* documented in relation to such.
635	*/
636	if (pVM->cpum.s.GuestFeatures.fArchCap && !cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES))
637	{
638	static CPUMMSRRANGE const s_ArchCaps =
639	{
640	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES,
641	/.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
642	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities,
643	/.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
644	/.offCpumCpu =/ UINT16_MAX,
645	/.fReserved =/ 0,
646	/.uValue =/ 0,
647	/.fWrIgnMask =/ 0,
648	/.fWrGpMask =/ UINT64_MAX,
649	/.szName = / "IA32_ARCH_CAPABILITIES"
650	};
651	papToAdd[cToAdd++] = &s_ArchCaps;
652	}
653
654	/*
655	* Do the adding.
656	*/
657	for (uint32_t i = 0; i < cToAdd; i++)
658	{
659	PCCPUMMSRRANGE pRange = papToAdd[i];
660	LogRel(("CPUM: MSR/CPUID reconciliation insert: %#010x %s\n", pRange->uFirst, pRange->szName));
661	int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
662	pRange);
663	if (RT_FAILURE(rc))
664	return rc;
665	}
666	return VINF_SUCCESS;
667	}
668
669
670	/**
671	* Worker for cpumR3MsrApplyFudge that applies one table.
672	*
673	* @returns VBox status code.
674	* @param pVM The cross context VM structure.
675	* @param paRanges Array of MSRs to fudge.
676	* @param cRanges Number of MSRs in the array.
677	*/
678	static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
679	{
680	for (uint32_t i = 0; i < cRanges; i++)
681	if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
682	{
683	LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
684	int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
685	&paRanges[i]);
686	if (RT_FAILURE(rc))
687	return rc;
688	}
689	return VINF_SUCCESS;
690	}
691
692
693	/**
694	* Fudges the MSRs that guest are known to access in some odd cases.
695	*
696	* A typical example is a VM that has been moved between different hosts where
697	* for instance the cpu vendor differs.
698	*
699	* Another example is older CPU profiles (e.g. Atom Bonnet) for newer CPUs (e.g.
700	* Atom Silvermont), where features reported thru CPUID aren't present in the
701	* MSRs (e.g. AMD64_TSC_AUX).
702	*
703	*
704	* @returns VBox status code.
705	* @param pVM The cross context VM structure.
706	*/
707	int cpumR3MsrApplyFudge(PVM pVM)
708	{
709	/*
710	* Basic.
711	*/
712	static CPUMMSRRANGE const s_aFudgeMsrs[] =
713	{
714	MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
715	MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
716	MVO(0x00000017, "IA32_PLATFORM_ID", 0),
717	MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
718	MVI(0x0000008b, "BIOS_SIGN", 0),
719	MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
720	MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
721	MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
722	MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
723	MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
724	MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
725	MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
726	MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
727	MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
728	MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
729	MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
730	MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
731	};
732	int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
733	AssertLogRelRCReturn(rc, rc);
734
735	/*
736	* XP might mistake opterons and other newer CPUs for P4s.
737	*/
738	if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
739	{
740	static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
741	{
742	MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
743	};
744	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
745	AssertLogRelRCReturn(rc, rc);
746	}
747
748	if (pVM->cpum.s.GuestFeatures.fRdTscP)
749	{
750	static CPUMMSRRANGE const s_aRdTscPFudgeMsrs[] =
751	{
752	MFX(0xc0000103, "AMD64_TSC_AUX", Amd64TscAux, Amd64TscAux, 0, 0, ~(uint64_t)UINT32_MAX),
753	};
754	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aRdTscPFudgeMsrs[0], RT_ELEMENTS(s_aRdTscPFudgeMsrs));
755	AssertLogRelRCReturn(rc, rc);
756	}
757
758	return rc;
759	}
760
761
762	/**
763	* Do we consider @a enmConsider a better match for @a enmTarget than
764	* @a enmFound?
765	*
766	* Only called when @a enmConsider isn't exactly what we're looking for.
767	*
768	* @returns true/false.
769	* @param enmConsider The new microarch to consider.
770	* @param enmTarget The target microarch.
771	* @param enmFound The best microarch match we've found thus far.
772	*/
773	DECLINLINE(bool) cpumR3DbIsBetterMarchMatch(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
774	{
775	Assert(enmConsider != enmTarget);
776
777	/*
778	* If we've got an march match, don't bother with enmConsider.
779	*/
780	if (enmFound == enmTarget)
781	return false;
782
783	/*
784	* Found is below: Pick 'consider' if it's closer to the target or above it.
785	*/
786	if (enmFound < enmTarget)
787	return enmConsider > enmFound;
788
789	/*
790	* Found is above: Pick 'consider' if it's also above (paranoia: or equal)
791	* and but closer to the target.
792	*/
793	return enmConsider >= enmTarget && enmConsider < enmFound;
794	}
795
796
797	/**
798	* Do we consider @a enmConsider a better match for @a enmTarget than
799	* @a enmFound?
800	*
801	* Only called for intel family 06h CPUs.
802	*
803	* @returns true/false.
804	* @param enmConsider The new microarch to consider.
805	* @param enmTarget The target microarch.
806	* @param enmFound The best microarch match we've found thus far.
807	*/
808	static bool cpumR3DbIsBetterIntelFam06Match(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
809	{
810	/* Check intel family 06h claims. */
811	AssertReturn(enmConsider >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmConsider <= kCpumMicroarch_Intel_P6_Core_Atom_End,
812	false);
813	AssertReturn(enmTarget >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmTarget <= kCpumMicroarch_Intel_P6_Core_Atom_End,
814	false);
815
816	/* Put matches out of the way. */
817	if (enmConsider == enmTarget)
818	return true;
819	if (enmFound == enmTarget)
820	return false;
821
822	/* If found isn't a family 06h march, whatever we're considering must be a better choice. */
823	if ( enmFound < kCpumMicroarch_Intel_P6_Core_Atom_First
824	\|\| enmFound > kCpumMicroarch_Intel_P6_Core_Atom_End)
825	return true;
826
827	/*
828	* The family 06h stuff is split into three categories:
829	* - Common P6 heritage
830	* - Core
831	* - Atom
832	*
833	* Determin which of the three arguments are Atom marchs, because that's
834	* all we need to make the right choice.
835	*/
836	bool const fConsiderAtom = enmConsider >= kCpumMicroarch_Intel_Atom_First;
837	bool const fTargetAtom = enmTarget >= kCpumMicroarch_Intel_Atom_First;
838	bool const fFoundAtom = enmFound >= kCpumMicroarch_Intel_Atom_First;
839
840	/*
841	* Want atom:
842	*/
843	if (fTargetAtom)
844	{
845	/* Pick the atom if we've got one of each.*/
846	if (fConsiderAtom != fFoundAtom)
847	return fConsiderAtom;
848	/* If we haven't got any atoms under consideration, pick a P6 or the earlier core.
849	Note! Not entirely sure Dothan is the best choice, but it'll do for now. */
850	if (!fConsiderAtom)
851	{
852	if (enmConsider > enmFound)
853	return enmConsider <= kCpumMicroarch_Intel_P6_M_Dothan;
854	return enmFound > kCpumMicroarch_Intel_P6_M_Dothan;
855	}
856	/* else: same category, default comparison rules. */
857	Assert(fConsiderAtom && fFoundAtom);
858	}
859	/*
860	* Want non-atom:
861	*/
862	/* Pick the non-atom if we've got one of each. */
863	else if (fConsiderAtom != fFoundAtom)
864	return fFoundAtom;
865	/* If we've only got atoms under consideration, pick the older one just to pick something. */
866	else if (fConsiderAtom)
867	return enmConsider < enmFound;
868	else
869	Assert(!fConsiderAtom && !fFoundAtom);
870
871	/*
872	* Same basic category. Do same compare as caller.
873	*/
874	return cpumR3DbIsBetterMarchMatch(enmConsider, enmTarget, enmFound);
875	}
876
877
878	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
879	{
880	CPUMDBENTRY const *pEntry = NULL;
881	int rc;
882
883	if (!strcmp(pszName, "host"))
884	{
885	/*
886	* Create a CPU database entry for the host CPU. This means getting
887	* the CPUID bits from the real CPU and grabbing the closest matching
888	* database entry for MSRs.
889	*/
890	rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
891	if (RT_FAILURE(rc))
892	return rc;
893	rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
894	if (RT_FAILURE(rc))
895	return rc;
896	pInfo->fMxCsrMask = CPUMR3DeterminHostMxCsrMask();
897
898	/* Lookup database entry for MSRs. */
899	CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
900	pInfo->paCpuIdLeavesR3[0].uEbx,
901	pInfo->paCpuIdLeavesR3[0].uEcx,
902	pInfo->paCpuIdLeavesR3[0].uEdx);
903	uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
904	uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
905	uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
906	uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
907	CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
908
909	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
910	{
911	CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
912	if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
913	{
914	/* Match against Family, Microarch, model and stepping. Except
915	for family, always match the closer with preference given to
916	the later/older ones. */
917	if (pCur->uFamily == uFamily)
918	{
919	if (pCur->enmMicroarch == enmMicroarch)
920	{
921	if (pCur->uModel == uModel)
922	{
923	if (pCur->uStepping == uStepping)
924	{
925	/* Perfect match. */
926	pEntry = pCur;
927	break;
928	}
929
930	if ( !pEntry
931	\|\| pEntry->uModel != uModel
932	\|\| pEntry->enmMicroarch != enmMicroarch
933	\|\| pEntry->uFamily != uFamily)
934	pEntry = pCur;
935	else if ( pCur->uStepping >= uStepping
936	? pCur->uStepping < pEntry->uStepping \|\| pEntry->uStepping < uStepping
937	: pCur->uStepping > pEntry->uStepping)
938	pEntry = pCur;
939	}
940	else if ( !pEntry
941	\|\| pEntry->enmMicroarch != enmMicroarch
942	\|\| pEntry->uFamily != uFamily)
943	pEntry = pCur;
944	else if ( pCur->uModel >= uModel
945	? pCur->uModel < pEntry->uModel \|\| pEntry->uModel < uModel
946	: pCur->uModel > pEntry->uModel)
947	pEntry = pCur;
948	}
949	else if ( !pEntry
950	\|\| pEntry->uFamily != uFamily)
951	pEntry = pCur;
952	/* Special march matching rules applies to intel family 06h. */
953	else if ( enmVendor == CPUMCPUVENDOR_INTEL
954	&& uFamily == 6
955	? cpumR3DbIsBetterIntelFam06Match(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch)
956	: cpumR3DbIsBetterMarchMatch(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch))
957	pEntry = pCur;
958	}
959	/* We don't do closeness matching on family, we use the first
960	entry for the CPU vendor instead. (P4 workaround.) */
961	else if (!pEntry)
962	pEntry = pCur;
963	}
964	}
965
966	if (pEntry)
967	LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
968	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
969	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
970	pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
971	else
972	{
973	pEntry = g_apCpumDbEntries[0];
974	LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'\n",
975	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
976	pEntry->pszName));
977	}
978	}
979	else
980	{
981	/*
982	* We're supposed to be emulating a specific CPU that is included in
983	* our CPU database. The CPUID tables needs to be copied onto the
984	* heap so the caller can modify them and so they can be freed like
985	* in the host case above.
986	*/
987	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
988	if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
989	{
990	pEntry = g_apCpumDbEntries[i];
991	break;
992	}
993	if (!pEntry)
994	{
995	LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
996	return VERR_CPUM_DB_CPU_NOT_FOUND;
997	}
998
999	pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
1000	if (pEntry->cCpuIdLeaves)
1001	{
1002	/* Must allocate a multiple of 16 here, matching cpumR3CpuIdEnsureSpace. */
1003	size_t cbExtra = sizeof(pEntry->paCpuIdLeaves[0]) * (RT_ALIGN(pEntry->cCpuIdLeaves, 16) - pEntry->cCpuIdLeaves);
1004	pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDupEx(pEntry->paCpuIdLeaves,
1005	sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves,
1006	cbExtra);
1007	if (!pInfo->paCpuIdLeavesR3)
1008	return VERR_NO_MEMORY;
1009	}
1010	else
1011	pInfo->paCpuIdLeavesR3 = NULL;
1012
1013	pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
1014	pInfo->DefCpuId = pEntry->DefUnknownCpuId;
1015	pInfo->fMxCsrMask = pEntry->fMxCsrMask;
1016
1017	LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
1018	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
1019	pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
1020	}
1021
1022	pInfo->fMsrMask = pEntry->fMsrMask;
1023	pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
1024	pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
1025	pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
1026	pInfo->paMsrRangesR0 = NIL_RTR0PTR;
1027
1028	/*
1029	* Copy the MSR range.
1030	*/
1031	uint32_t cMsrs = 0;
1032	PCPUMMSRRANGE paMsrs = NULL;
1033
1034	PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
1035	uint32_t cLeft = pEntry->cMsrRanges;
1036	while (cLeft-- > 0)
1037	{
1038	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &paMsrs, &cMsrs, pCurMsr);
1039	if (RT_FAILURE(rc))
1040	{
1041	Assert(!paMsrs); /* The above function frees this. */
1042	RTMemFree(pInfo->paCpuIdLeavesR3);
1043	pInfo->paCpuIdLeavesR3 = NULL;
1044	return rc;
1045	}
1046	pCurMsr++;
1047	}
1048
1049	pInfo->paMsrRangesR3 = paMsrs;
1050	pInfo->cMsrRanges = cMsrs;
1051	return VINF_SUCCESS;
1052	}
1053
1054
1055	/**
1056	* Insert an MSR range into the VM.
1057	*
1058	* If the new MSR range overlaps existing ranges, the existing ones will be
1059	* adjusted/removed to fit in the new one.
1060	*
1061	* @returns VBox status code.
1062	* @param pVM The cross context VM structure.
1063	* @param pNewRange Pointer to the MSR range being inserted.
1064	*/
1065	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange)
1066	{
1067	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1068	AssertReturn(pNewRange, VERR_INVALID_PARAMETER);
1069
1070	return cpumR3MsrRangesInsert(pVM, NULL /* ppaMsrRanges /, NULL / pcMsrRanges */, pNewRange);
1071	}
1072
1073
1074	/**
1075	* Register statistics for the MSRs.
1076	*
1077	* This must not be called before the MSRs have been finalized and moved to the
1078	* hyper heap.
1079	*
1080	* @returns VBox status code.
1081	* @param pVM The cross context VM structure.
1082	*/
1083	int cpumR3MsrRegStats(PVM pVM)
1084	{
1085	/*
1086	* Global statistics.
1087	*/
1088	PCPUM pCpum = &pVM->cpum.s;
1089	STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
1090	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
1091	STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
1092	STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
1093	STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
1094	STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
1095	STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
1096	STAMUNIT_OCCURENCES, "All WRMSRs making it to CPUM.");
1097	STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
1098	STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
1099	STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
1100	STAMUNIT_OCCURENCES, "Writing of ignored bits.");
1101	STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
1102	STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
1103
1104
1105	# ifdef VBOX_WITH_STATISTICS
1106	/*
1107	* Per range.
1108	*/
1109	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
1110	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
1111	for (uint32_t i = 0; i < cRanges; i++)
1112	{
1113	char szName[160];
1114	ssize_t cchName;
1115
1116	if (paRanges[i].uFirst == paRanges[i].uLast)
1117	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
1118	paRanges[i].uFirst, paRanges[i].szName);
1119	else
1120	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
1121	paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
1122
1123	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
1124	STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
1125
1126	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
1127	STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
1128
1129	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
1130	STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
1131
1132	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
1133	STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
1134	}
1135	# endif /* VBOX_WITH_STATISTICS */
1136
1137	return VINF_SUCCESS;
1138	}
1139
1140	#endif /* !CPUM_DB_STANDALONE */
1141

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 80386

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